Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* DAG Instruction Selector for the AMDGPU target *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 : // *** NOTE: This file is #included into the middle of the target
10 : // *** instruction selector class. These functions are really methods.
11 :
12 : // The main instruction selector code.
13 : SDNode *SelectCode(SDNode *N) {
14 : // Some target values are emitted as 2 bytes, TARGET_VAL handles
15 : // this.
16 : #define TARGET_VAL(X) X & 255, unsigned(X) >> 8
17 : static const unsigned char MatcherTable[] = {
18 : /*0*/ OPC_SwitchOpcode /*139 cases */, 71|128,8/*1095*/, TARGET_VAL(ISD::STORE),// ->1100
19 : /*5*/ OPC_RecordMemRef,
20 : /*6*/ OPC_RecordNode, // #0 = 'SIst_local' chained node
21 : /*7*/ OPC_Scope, 33, /*->42*/ // 4 children in Scope
22 : /*9*/ OPC_CaptureGlueInput,
23 : /*10*/ OPC_RecordChild1, // #1 = $value
24 : /*11*/ OPC_CheckChild1Type, MVT::v2i32,
25 : /*13*/ OPC_RecordChild2, // #2 = $DS1Addr1Offset:ptr:offset
26 : /*14*/ OPC_CheckPredicate, 0, // Predicate_si_st_local
27 : /*16*/ OPC_CheckPredicate, 1, // Predicate_si_store_local
28 : /*18*/ OPC_CheckPredicate, 2, // Predicate_si_store_local_align8
29 : /*20*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
30 : /*22*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectDS1Addr1Offset:$ #3 #4
31 : /*25*/ OPC_EmitMergeInputChains1_0,
32 : /*26*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
33 : /*29*/ OPC_EmitInteger, MVT::i1, 0,
34 : /*32*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_WRITE_B64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
35 : 0/*#VTs*/, 4/*#Ops*/, 3, 1, 5, 6,
36 : // Src: (SIst_local v2i32:v2i32:$value, (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_st_local>><<P:Predicate_si_store_local>><<P:Predicate_si_store_local_align8>> - Complexity = 113
37 : // Dst: (DS_WRITE_B64 ?:i32:$ptr, ?:v2i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
38 : /*42*/ /*Scope*/ 64|128,3/*448*/, /*->492*/
39 : /*44*/ OPC_RecordChild1, // #1 = $vdata
40 : /*45*/ OPC_Scope, 15|128,2/*271*/, /*->319*/ // 3 children in Scope
41 : /*48*/ OPC_CheckChild1Type, MVT::i32,
42 : /*50*/ OPC_RecordChild2, // #2 = $MUBUFAddr64:srsrc:vaddr:soffset:offset:glc:slc:tfe
43 : /*51*/ OPC_CheckPredicate, 3, // Predicate_unindexedstore
44 : /*53*/ OPC_Scope, 54, /*->109*/ // 6 children in Scope
45 : /*55*/ OPC_CheckPredicate, 4, // Predicate_truncstore
46 : /*57*/ OPC_Scope, 24, /*->83*/ // 2 children in Scope
47 : /*59*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
48 : /*61*/ OPC_CheckPredicate, 6, // Predicate_truncstorei8_global
49 : /*63*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
50 : /*65*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7 #8 #9
51 : /*68*/ OPC_EmitMergeInputChains1_0,
52 : /*69*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_BYTE_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
53 : 0/*#VTs*/, 8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9,
54 : // Src: (st i32:i32:$vdata, (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> - Complexity = 28
55 : // Dst: (BUFFER_STORE_BYTE_ADDR64 i32:i32:$vdata, i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
56 : /*83*/ /*Scope*/ 24, /*->108*/
57 : /*84*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
58 : /*86*/ OPC_CheckPredicate, 8, // Predicate_truncstorei16_global
59 : /*88*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
60 : /*90*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7 #8 #9
61 : /*93*/ OPC_EmitMergeInputChains1_0,
62 : /*94*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_SHORT_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
63 : 0/*#VTs*/, 8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9,
64 : // Src: (st i32:i32:$vdata, (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>> - Complexity = 28
65 : // Dst: (BUFFER_STORE_SHORT_ADDR64 i32:i32:$vdata, i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
66 : /*108*/ 0, /*End of Scope*/
67 : /*109*/ /*Scope*/ 24, /*->134*/
68 : /*110*/ OPC_CheckPredicate, 9, // Predicate_store
69 : /*112*/ OPC_CheckPredicate, 10, // Predicate_global_store
70 : /*114*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
71 : /*116*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7 #8 #9
72 : /*119*/ OPC_EmitMergeInputChains1_0,
73 : /*120*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
74 : 0/*#VTs*/, 8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9,
75 : // Src: (st i32:i32:$vdata, (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 28
76 : // Dst: (BUFFER_STORE_DWORD_ADDR64 i32:i32:$vdata, i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
77 : /*134*/ /*Scope*/ 52, /*->187*/
78 : /*135*/ OPC_CheckPredicate, 4, // Predicate_truncstore
79 : /*137*/ OPC_Scope, 23, /*->162*/ // 2 children in Scope
80 : /*139*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
81 : /*141*/ OPC_CheckPredicate, 6, // Predicate_truncstorei8_global
82 : /*143*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
83 : /*145*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
84 : /*148*/ OPC_EmitMergeInputChains1_0,
85 : /*149*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_BYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
86 : 0/*#VTs*/, 7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8,
87 : // Src: (st i32:i32:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> - Complexity = 25
88 : // Dst: (BUFFER_STORE_BYTE_OFFSET i32:i32:$vdata, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
89 : /*162*/ /*Scope*/ 23, /*->186*/
90 : /*163*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
91 : /*165*/ OPC_CheckPredicate, 8, // Predicate_truncstorei16_global
92 : /*167*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
93 : /*169*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
94 : /*172*/ OPC_EmitMergeInputChains1_0,
95 : /*173*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_SHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
96 : 0/*#VTs*/, 7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8,
97 : // Src: (st i32:i32:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>> - Complexity = 25
98 : // Dst: (BUFFER_STORE_SHORT_OFFSET i32:i32:$vdata, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
99 : /*186*/ 0, /*End of Scope*/
100 : /*187*/ /*Scope*/ 23, /*->211*/
101 : /*188*/ OPC_CheckPredicate, 9, // Predicate_store
102 : /*190*/ OPC_CheckPredicate, 10, // Predicate_global_store
103 : /*192*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
104 : /*194*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
105 : /*197*/ OPC_EmitMergeInputChains1_0,
106 : /*198*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
107 : 0/*#VTs*/, 7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8,
108 : // Src: (st i32:i32:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 25
109 : // Dst: (BUFFER_STORE_DWORD_OFFSET i32:i32:$vdata, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
110 : /*211*/ /*Scope*/ 72, /*->284*/
111 : /*212*/ OPC_CheckPredicate, 4, // Predicate_truncstore
112 : /*214*/ OPC_Scope, 33, /*->249*/ // 2 children in Scope
113 : /*216*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
114 : /*218*/ OPC_CheckPredicate, 11, // Predicate_truncstorei8_private
115 : /*220*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
116 : /*222*/ OPC_CheckComplexPat, /*CP*/3, /*#*/2, // SelectMUBUFScratch:$ #3 #4 #5 #6
117 : /*225*/ OPC_EmitMergeInputChains1_0,
118 : /*226*/ OPC_EmitInteger, MVT::i1, 0,
119 : /*229*/ OPC_EmitInteger, MVT::i1, 0,
120 : /*232*/ OPC_EmitInteger, MVT::i1, 0,
121 : /*235*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_BYTE_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
122 : 0/*#VTs*/, 8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9,
123 : // Src: (st i32:i32:$value, (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> - Complexity = 19
124 : // Dst: (BUFFER_STORE_BYTE_OFFEN ?:i32:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
125 : /*249*/ /*Scope*/ 33, /*->283*/
126 : /*250*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
127 : /*252*/ OPC_CheckPredicate, 12, // Predicate_truncstorei16_private
128 : /*254*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
129 : /*256*/ OPC_CheckComplexPat, /*CP*/3, /*#*/2, // SelectMUBUFScratch:$ #3 #4 #5 #6
130 : /*259*/ OPC_EmitMergeInputChains1_0,
131 : /*260*/ OPC_EmitInteger, MVT::i1, 0,
132 : /*263*/ OPC_EmitInteger, MVT::i1, 0,
133 : /*266*/ OPC_EmitInteger, MVT::i1, 0,
134 : /*269*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_SHORT_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
135 : 0/*#VTs*/, 8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9,
136 : // Src: (st i32:i32:$value, (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>> - Complexity = 19
137 : // Dst: (BUFFER_STORE_SHORT_OFFEN ?:i32:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
138 : /*283*/ 0, /*End of Scope*/
139 : /*284*/ /*Scope*/ 33, /*->318*/
140 : /*285*/ OPC_CheckPredicate, 9, // Predicate_store
141 : /*287*/ OPC_CheckPredicate, 13, // Predicate_store_private
142 : /*289*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
143 : /*291*/ OPC_CheckComplexPat, /*CP*/3, /*#*/2, // SelectMUBUFScratch:$ #3 #4 #5 #6
144 : /*294*/ OPC_EmitMergeInputChains1_0,
145 : /*295*/ OPC_EmitInteger, MVT::i1, 0,
146 : /*298*/ OPC_EmitInteger, MVT::i1, 0,
147 : /*301*/ OPC_EmitInteger, MVT::i1, 0,
148 : /*304*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORD_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
149 : 0/*#VTs*/, 8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9,
150 : // Src: (st i32:i32:$value, (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 19
151 : // Dst: (BUFFER_STORE_DWORD_OFFEN ?:i32:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
152 : /*318*/ 0, /*End of Scope*/
153 : /*319*/ /*Scope*/ 85, /*->405*/
154 : /*320*/ OPC_CheckChild1Type, MVT::v2i32,
155 : /*322*/ OPC_RecordChild2, // #2 = $MUBUFAddr64:srsrc:vaddr:soffset:offset:glc:slc:tfe
156 : /*323*/ OPC_CheckPredicate, 3, // Predicate_unindexedstore
157 : /*325*/ OPC_CheckPredicate, 9, // Predicate_store
158 : /*327*/ OPC_Scope, 43, /*->372*/ // 2 children in Scope
159 : /*329*/ OPC_CheckPredicate, 10, // Predicate_global_store
160 : /*331*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
161 : /*333*/ OPC_Scope, 18, /*->353*/ // 2 children in Scope
162 : /*335*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7 #8 #9
163 : /*338*/ OPC_EmitMergeInputChains1_0,
164 : /*339*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
165 : 0/*#VTs*/, 8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9,
166 : // Src: (st v2i32:v2i32:$vdata, (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 28
167 : // Dst: (BUFFER_STORE_DWORDX2_ADDR64 v2i32:v2i32:$vdata, i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
168 : /*353*/ /*Scope*/ 17, /*->371*/
169 : /*354*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
170 : /*357*/ OPC_EmitMergeInputChains1_0,
171 : /*358*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
172 : 0/*#VTs*/, 7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8,
173 : // Src: (st v2i32:v2i32:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 25
174 : // Dst: (BUFFER_STORE_DWORDX2_OFFSET v2i32:v2i32:$vdata, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
175 : /*371*/ 0, /*End of Scope*/
176 : /*372*/ /*Scope*/ 31, /*->404*/
177 : /*373*/ OPC_CheckPredicate, 13, // Predicate_store_private
178 : /*375*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
179 : /*377*/ OPC_CheckComplexPat, /*CP*/3, /*#*/2, // SelectMUBUFScratch:$ #3 #4 #5 #6
180 : /*380*/ OPC_EmitMergeInputChains1_0,
181 : /*381*/ OPC_EmitInteger, MVT::i1, 0,
182 : /*384*/ OPC_EmitInteger, MVT::i1, 0,
183 : /*387*/ OPC_EmitInteger, MVT::i1, 0,
184 : /*390*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
185 : 0/*#VTs*/, 8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9,
186 : // Src: (st v2i32:v2i32:$value, (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 19
187 : // Dst: (BUFFER_STORE_DWORDX2_OFFEN ?:v2i32:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
188 : /*404*/ 0, /*End of Scope*/
189 : /*405*/ /*Scope*/ 85, /*->491*/
190 : /*406*/ OPC_CheckChild1Type, MVT::v4i32,
191 : /*408*/ OPC_RecordChild2, // #2 = $MUBUFAddr64:srsrc:vaddr:soffset:offset:glc:slc:tfe
192 : /*409*/ OPC_CheckPredicate, 3, // Predicate_unindexedstore
193 : /*411*/ OPC_CheckPredicate, 9, // Predicate_store
194 : /*413*/ OPC_Scope, 43, /*->458*/ // 2 children in Scope
195 : /*415*/ OPC_CheckPredicate, 10, // Predicate_global_store
196 : /*417*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
197 : /*419*/ OPC_Scope, 18, /*->439*/ // 2 children in Scope
198 : /*421*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7 #8 #9
199 : /*424*/ OPC_EmitMergeInputChains1_0,
200 : /*425*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
201 : 0/*#VTs*/, 8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9,
202 : // Src: (st v4i32:v4i32:$vdata, (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 28
203 : // Dst: (BUFFER_STORE_DWORDX4_ADDR64 v4i32:v4i32:$vdata, i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
204 : /*439*/ /*Scope*/ 17, /*->457*/
205 : /*440*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // SelectMUBUFOffset:$ #3 #4 #5 #6 #7 #8
206 : /*443*/ OPC_EmitMergeInputChains1_0,
207 : /*444*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
208 : 0/*#VTs*/, 7/*#Ops*/, 1, 3, 4, 5, 6, 7, 8,
209 : // Src: (st v4i32:v4i32:$vdata, (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 25
210 : // Dst: (BUFFER_STORE_DWORDX4_OFFSET v4i32:v4i32:$vdata, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
211 : /*457*/ 0, /*End of Scope*/
212 : /*458*/ /*Scope*/ 31, /*->490*/
213 : /*459*/ OPC_CheckPredicate, 13, // Predicate_store_private
214 : /*461*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
215 : /*463*/ OPC_CheckComplexPat, /*CP*/3, /*#*/2, // SelectMUBUFScratch:$ #3 #4 #5 #6
216 : /*466*/ OPC_EmitMergeInputChains1_0,
217 : /*467*/ OPC_EmitInteger, MVT::i1, 0,
218 : /*470*/ OPC_EmitInteger, MVT::i1, 0,
219 : /*473*/ OPC_EmitInteger, MVT::i1, 0,
220 : /*476*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
221 : 0/*#VTs*/, 8/*#Ops*/, 1, 4, 3, 5, 6, 7, 8, 9,
222 : // Src: (st v4i32:v4i32:$value, (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_store_private>> - Complexity = 19
223 : // Dst: (BUFFER_STORE_DWORDX4_OFFEN ?:v4i32:$value, ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
224 : /*490*/ 0, /*End of Scope*/
225 : /*491*/ 0, /*End of Scope*/
226 : /*492*/ /*Scope*/ 17|128,1/*145*/, /*->639*/
227 : /*494*/ OPC_CaptureGlueInput,
228 : /*495*/ OPC_RecordChild1, // #1 = $value
229 : /*496*/ OPC_Scope, 52, /*->550*/ // 2 children in Scope
230 : /*498*/ OPC_CheckChild1Type, MVT::v2i32,
231 : /*500*/ OPC_RecordChild2, // #2 = $DS64Bit4ByteAligned:ptr:offset0:offset1
232 : /*501*/ OPC_CheckPredicate, 0, // Predicate_si_st_local
233 : /*503*/ OPC_CheckPredicate, 1, // Predicate_si_store_local
234 : /*505*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
235 : /*507*/ OPC_CheckComplexPat, /*CP*/4, /*#*/2, // SelectDS64Bit4ByteAligned:$ #3 #4 #5
236 : /*510*/ OPC_EmitMergeInputChains1_0,
237 : /*511*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
238 : /*514*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
239 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 6, // Results = #7
240 : /*523*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
241 : /*526*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
242 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 8, // Results = #9
243 : /*535*/ OPC_EmitInteger, MVT::i1, 0,
244 : /*538*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_WRITE2_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
245 : 0/*#VTs*/, 6/*#Ops*/, 3, 7, 9, 4, 5, 10,
246 : // Src: (SIst_local v2i32:v2i32:$value, (DS64Bit4ByteAligned:iPTR i32:i32:$ptr, i8:i8:$offset0, i8:i8:$offset1))<<P:Predicate_si_st_local>><<P:Predicate_si_store_local>> - Complexity = 16
247 : // Dst: (DS_WRITE2_B32 ?:i32:$ptr, (EXTRACT_SUBREG:i32 ?:v2i32:$value, sub0:i32), (EXTRACT_SUBREG:i32 ?:v2i32:$value, sub1:i32), ?:i8:$offset0, ?:i8:$offset1, 0:i1)
248 : /*550*/ /*Scope*/ 87, /*->638*/
249 : /*551*/ OPC_CheckChild1Type, MVT::i32,
250 : /*553*/ OPC_RecordChild2, // #2 = $DS1Addr1Offset:ptr:offset
251 : /*554*/ OPC_CheckPredicate, 0, // Predicate_si_st_local
252 : /*556*/ OPC_Scope, 54, /*->612*/ // 2 children in Scope
253 : /*558*/ OPC_CheckPredicate, 14, // Predicate_si_truncstore_local
254 : /*560*/ OPC_Scope, 24, /*->586*/ // 2 children in Scope
255 : /*562*/ OPC_CheckPredicate, 15, // Predicate_si_truncstore_local_i8
256 : /*564*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
257 : /*566*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectDS1Addr1Offset:$ #3 #4
258 : /*569*/ OPC_EmitMergeInputChains1_0,
259 : /*570*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
260 : /*573*/ OPC_EmitInteger, MVT::i1, 0,
261 : /*576*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_WRITE_B8), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
262 : 0/*#VTs*/, 4/*#Ops*/, 3, 1, 5, 6,
263 : // Src: (SIst_local i32:i32:$value, (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_st_local>><<P:Predicate_si_truncstore_local>><<P:Predicate_si_truncstore_local_i8>> - Complexity = 13
264 : // Dst: (DS_WRITE_B8 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
265 : /*586*/ /*Scope*/ 24, /*->611*/
266 : /*587*/ OPC_CheckPredicate, 16, // Predicate_si_truncstore_local_i16
267 : /*589*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
268 : /*591*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectDS1Addr1Offset:$ #3 #4
269 : /*594*/ OPC_EmitMergeInputChains1_0,
270 : /*595*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
271 : /*598*/ OPC_EmitInteger, MVT::i1, 0,
272 : /*601*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_WRITE_B16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
273 : 0/*#VTs*/, 4/*#Ops*/, 3, 1, 5, 6,
274 : // Src: (SIst_local i32:i32:$value, (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_st_local>><<P:Predicate_si_truncstore_local>><<P:Predicate_si_truncstore_local_i16>> - Complexity = 13
275 : // Dst: (DS_WRITE_B16 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
276 : /*611*/ 0, /*End of Scope*/
277 : /*612*/ /*Scope*/ 24, /*->637*/
278 : /*613*/ OPC_CheckPredicate, 1, // Predicate_si_store_local
279 : /*615*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
280 : /*617*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectDS1Addr1Offset:$ #3 #4
281 : /*620*/ OPC_EmitMergeInputChains1_0,
282 : /*621*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
283 : /*624*/ OPC_EmitInteger, MVT::i1, 0,
284 : /*627*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_WRITE_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
285 : 0/*#VTs*/, 4/*#Ops*/, 3, 1, 5, 6,
286 : // Src: (SIst_local i32:i32:$value, (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_st_local>><<P:Predicate_si_store_local>> - Complexity = 13
287 : // Dst: (DS_WRITE_B32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
288 : /*637*/ 0, /*End of Scope*/
289 : /*638*/ 0, /*End of Scope*/
290 : /*639*/ /*Scope*/ 74|128,3/*458*/, /*->1099*/
291 : /*641*/ OPC_RecordChild1, // #1 = $src1
292 : /*642*/ OPC_Scope, 44|128,2/*300*/, /*->945*/ // 4 children in Scope
293 : /*645*/ OPC_CheckChild1Type, MVT::i32,
294 : /*647*/ OPC_RecordChild2, // #2 = $src0
295 : /*648*/ OPC_Scope, 105|128,1/*233*/, /*->884*/ // 2 children in Scope
296 : /*651*/ OPC_CheckChild2Type, MVT::i32,
297 : /*653*/ OPC_CheckPredicate, 3, // Predicate_unindexedstore
298 : /*655*/ OPC_Scope, 61, /*->718*/ // 3 children in Scope
299 : /*657*/ OPC_CheckPredicate, 9, // Predicate_store
300 : /*659*/ OPC_CheckPredicate, 17, // Predicate_local_store
301 : /*661*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
302 : /*663*/ OPC_EmitMergeInputChains1_0,
303 : /*664*/ OPC_EmitInteger, MVT::i32, 0,
304 : /*667*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
305 : /*679*/ OPC_EmitInteger, MVT::i32, 0,
306 : /*682*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
307 : /*694*/ OPC_EmitInteger, MVT::i32, 1,
308 : /*697*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
309 : /*700*/ OPC_EmitInteger, MVT::i32, 0,
310 : /*703*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_WRITE), 0|OPFL_Chain|OPFL_MemRefs,
311 : 0/*#VTs*/, 9/*#Ops*/, 2, 3, 4, 1, 5, 6, 7, 8, 9,
312 : // Src: (st R600_Reg32:i32:$src1, R600_Reg32:i32:$src0)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_local_store>> - Complexity = 4
313 : // Dst: (LDS_WRITE R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
314 : /*718*/ /*Scope*/ 0|128,1/*128*/, /*->848*/
315 : /*720*/ OPC_CheckPredicate, 4, // Predicate_truncstore
316 : /*722*/ OPC_Scope, 61, /*->785*/ // 2 children in Scope
317 : /*724*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
318 : /*726*/ OPC_CheckPredicate, 18, // Predicate_truncstorei8_local
319 : /*728*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
320 : /*730*/ OPC_EmitMergeInputChains1_0,
321 : /*731*/ OPC_EmitInteger, MVT::i32, 0,
322 : /*734*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
323 : /*746*/ OPC_EmitInteger, MVT::i32, 0,
324 : /*749*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
325 : /*761*/ OPC_EmitInteger, MVT::i32, 1,
326 : /*764*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
327 : /*767*/ OPC_EmitInteger, MVT::i32, 0,
328 : /*770*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_BYTE_WRITE), 0|OPFL_Chain|OPFL_MemRefs,
329 : 0/*#VTs*/, 9/*#Ops*/, 2, 3, 4, 1, 5, 6, 7, 8, 9,
330 : // Src: (st i32:i32:$src1, i32:i32:$src0)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>> - Complexity = 4
331 : // Dst: (LDS_BYTE_WRITE i32:i32:$src0, i32:i32:$src1)
332 : /*785*/ /*Scope*/ 61, /*->847*/
333 : /*786*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
334 : /*788*/ OPC_CheckPredicate, 19, // Predicate_truncstorei16_local
335 : /*790*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
336 : /*792*/ OPC_EmitMergeInputChains1_0,
337 : /*793*/ OPC_EmitInteger, MVT::i32, 0,
338 : /*796*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
339 : /*808*/ OPC_EmitInteger, MVT::i32, 0,
340 : /*811*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
341 : /*823*/ OPC_EmitInteger, MVT::i32, 1,
342 : /*826*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
343 : /*829*/ OPC_EmitInteger, MVT::i32, 0,
344 : /*832*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_SHORT_WRITE), 0|OPFL_Chain|OPFL_MemRefs,
345 : 0/*#VTs*/, 9/*#Ops*/, 2, 3, 4, 1, 5, 6, 7, 8, 9,
346 : // Src: (st i32:i32:$src1, i32:i32:$src0)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_local>> - Complexity = 4
347 : // Dst: (LDS_SHORT_WRITE i32:i32:$src0, i32:i32:$src1)
348 : /*847*/ 0, /*End of Scope*/
349 : /*848*/ /*Scope*/ 34, /*->883*/
350 : /*849*/ OPC_CheckPredicate, 9, // Predicate_store
351 : /*851*/ OPC_CheckPredicate, 10, // Predicate_global_store
352 : /*853*/ OPC_Scope, 11, /*->866*/ // 2 children in Scope
353 : /*855*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
354 : /*857*/ OPC_EmitMergeInputChains1_0,
355 : /*858*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RAT_STORE_DWORD32), 0|OPFL_Chain|OPFL_MemRefs,
356 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
357 : // Src: (st i32:i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
358 : // Dst: (RAT_STORE_DWORD32 i32:i32:$rw_gpr, i32:i32:$index_gpr)
359 : /*866*/ /*Scope*/ 15, /*->882*/
360 : /*867*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
361 : /*869*/ OPC_EmitMergeInputChains1_0,
362 : /*870*/ OPC_EmitInteger, MVT::i32, 0,
363 : /*873*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RAT_WRITE_CACHELESS_32_eg), 0|OPFL_Chain|OPFL_MemRefs,
364 : 0/*#VTs*/, 3/*#Ops*/, 1, 2, 3,
365 : // Src: (st i32:i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
366 : // Dst: (RAT_WRITE_CACHELESS_32_eg i32:i32:$rw_gpr, i32:i32:$index_gpr)
367 : /*882*/ 0, /*End of Scope*/
368 : /*883*/ 0, /*End of Scope*/
369 : /*884*/ /*Scope*/ 59, /*->944*/
370 : /*885*/ OPC_CheckChild2Type, MVT::i64,
371 : /*887*/ OPC_CheckPredicate, 3, // Predicate_unindexedstore
372 : /*889*/ OPC_Scope, 36, /*->927*/ // 2 children in Scope
373 : /*891*/ OPC_CheckPredicate, 4, // Predicate_truncstore
374 : /*893*/ OPC_Scope, 15, /*->910*/ // 2 children in Scope
375 : /*895*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
376 : /*897*/ OPC_CheckPredicate, 20, // Predicate_truncstorei8_flat
377 : /*899*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
378 : /*901*/ OPC_EmitMergeInputChains1_0,
379 : /*902*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_STORE_BYTE), 0|OPFL_Chain|OPFL_MemRefs,
380 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
381 : // Src: (st i32:i32:$value, i64:i64:$ptr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>> - Complexity = 4
382 : // Dst: (FLAT_STORE_BYTE ?:i32:$value, ?:i64:$ptr)
383 : /*910*/ /*Scope*/ 15, /*->926*/
384 : /*911*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
385 : /*913*/ OPC_CheckPredicate, 21, // Predicate_truncstorei16_flat
386 : /*915*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
387 : /*917*/ OPC_EmitMergeInputChains1_0,
388 : /*918*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_STORE_SHORT), 0|OPFL_Chain|OPFL_MemRefs,
389 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
390 : // Src: (st i32:i32:$value, i64:i64:$ptr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>> - Complexity = 4
391 : // Dst: (FLAT_STORE_SHORT ?:i32:$value, ?:i64:$ptr)
392 : /*926*/ 0, /*End of Scope*/
393 : /*927*/ /*Scope*/ 15, /*->943*/
394 : /*928*/ OPC_CheckPredicate, 9, // Predicate_store
395 : /*930*/ OPC_CheckPredicate, 22, // Predicate_flat_store
396 : /*932*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
397 : /*934*/ OPC_EmitMergeInputChains1_0,
398 : /*935*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_STORE_DWORD), 0|OPFL_Chain|OPFL_MemRefs,
399 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
400 : // Src: (st i32:i32:$value, i64:i64:$ptr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_flat_store>> - Complexity = 4
401 : // Dst: (FLAT_STORE_DWORD ?:i32:$value, ?:i64:$ptr)
402 : /*943*/ 0, /*End of Scope*/
403 : /*944*/ 0, /*End of Scope*/
404 : /*945*/ /*Scope*/ 64, /*->1010*/
405 : /*946*/ OPC_CheckChild1Type, MVT::v2i32,
406 : /*948*/ OPC_RecordChild2, // #2 = $index_gpr
407 : /*949*/ OPC_Scope, 38, /*->989*/ // 2 children in Scope
408 : /*951*/ OPC_CheckChild2Type, MVT::i32,
409 : /*953*/ OPC_CheckPredicate, 3, // Predicate_unindexedstore
410 : /*955*/ OPC_CheckPredicate, 9, // Predicate_store
411 : /*957*/ OPC_CheckPredicate, 10, // Predicate_global_store
412 : /*959*/ OPC_Scope, 11, /*->972*/ // 2 children in Scope
413 : /*961*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
414 : /*963*/ OPC_EmitMergeInputChains1_0,
415 : /*964*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RAT_STORE_DWORD64), 0|OPFL_Chain|OPFL_MemRefs,
416 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
417 : // Src: (st v2i32:v2i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
418 : // Dst: (RAT_STORE_DWORD64 v2i32:v2i32:$rw_gpr, i32:i32:$index_gpr)
419 : /*972*/ /*Scope*/ 15, /*->988*/
420 : /*973*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
421 : /*975*/ OPC_EmitMergeInputChains1_0,
422 : /*976*/ OPC_EmitInteger, MVT::i32, 0,
423 : /*979*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RAT_WRITE_CACHELESS_64_eg), 0|OPFL_Chain|OPFL_MemRefs,
424 : 0/*#VTs*/, 3/*#Ops*/, 1, 2, 3,
425 : // Src: (st v2i32:v2i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
426 : // Dst: (RAT_WRITE_CACHELESS_64_eg v2i32:v2i32:$rw_gpr, i32:i32:$index_gpr)
427 : /*988*/ 0, /*End of Scope*/
428 : /*989*/ /*Scope*/ 19, /*->1009*/
429 : /*990*/ OPC_CheckChild2Type, MVT::i64,
430 : /*992*/ OPC_CheckPredicate, 3, // Predicate_unindexedstore
431 : /*994*/ OPC_CheckPredicate, 9, // Predicate_store
432 : /*996*/ OPC_CheckPredicate, 22, // Predicate_flat_store
433 : /*998*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
434 : /*1000*/ OPC_EmitMergeInputChains1_0,
435 : /*1001*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_STORE_DWORDX2), 0|OPFL_Chain|OPFL_MemRefs,
436 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
437 : // Src: (st v2i32:v2i32:$value, i64:i64:$ptr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_flat_store>> - Complexity = 4
438 : // Dst: (FLAT_STORE_DWORDX2 ?:v2i32:$value, ?:i64:$ptr)
439 : /*1009*/ 0, /*End of Scope*/
440 : /*1010*/ /*Scope*/ 64, /*->1075*/
441 : /*1011*/ OPC_CheckChild1Type, MVT::v4i32,
442 : /*1013*/ OPC_RecordChild2, // #2 = $index_gpr
443 : /*1014*/ OPC_Scope, 38, /*->1054*/ // 2 children in Scope
444 : /*1016*/ OPC_CheckChild2Type, MVT::i32,
445 : /*1018*/ OPC_CheckPredicate, 3, // Predicate_unindexedstore
446 : /*1020*/ OPC_CheckPredicate, 9, // Predicate_store
447 : /*1022*/ OPC_CheckPredicate, 10, // Predicate_global_store
448 : /*1024*/ OPC_Scope, 11, /*->1037*/ // 2 children in Scope
449 : /*1026*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
450 : /*1028*/ OPC_EmitMergeInputChains1_0,
451 : /*1029*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RAT_STORE_DWORD128), 0|OPFL_Chain|OPFL_MemRefs,
452 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
453 : // Src: (st v4i32:v4i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
454 : // Dst: (RAT_STORE_DWORD128 v4i32:v4i32:$rw_gpr, i32:i32:$index_gpr)
455 : /*1037*/ /*Scope*/ 15, /*->1053*/
456 : /*1038*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
457 : /*1040*/ OPC_EmitMergeInputChains1_0,
458 : /*1041*/ OPC_EmitInteger, MVT::i32, 0,
459 : /*1044*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RAT_WRITE_CACHELESS_128_eg), 0|OPFL_Chain|OPFL_MemRefs,
460 : 0/*#VTs*/, 3/*#Ops*/, 1, 2, 3,
461 : // Src: (st v4i32:v4i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_global_store>> - Complexity = 4
462 : // Dst: (RAT_WRITE_CACHELESS_128_eg v4i32:v4i32:$rw_gpr, i32:i32:$index_gpr)
463 : /*1053*/ 0, /*End of Scope*/
464 : /*1054*/ /*Scope*/ 19, /*->1074*/
465 : /*1055*/ OPC_CheckChild2Type, MVT::i64,
466 : /*1057*/ OPC_CheckPredicate, 3, // Predicate_unindexedstore
467 : /*1059*/ OPC_CheckPredicate, 9, // Predicate_store
468 : /*1061*/ OPC_CheckPredicate, 22, // Predicate_flat_store
469 : /*1063*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
470 : /*1065*/ OPC_EmitMergeInputChains1_0,
471 : /*1066*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_STORE_DWORDX4), 0|OPFL_Chain|OPFL_MemRefs,
472 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
473 : // Src: (st v4i32:v4i32:$value, i64:i64:$ptr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_flat_store>> - Complexity = 4
474 : // Dst: (FLAT_STORE_DWORDX4 ?:v4i32:$value, ?:i64:$ptr)
475 : /*1074*/ 0, /*End of Scope*/
476 : /*1075*/ /*Scope*/ 22, /*->1098*/
477 : /*1076*/ OPC_CheckChild1Type, MVT::i64,
478 : /*1078*/ OPC_RecordChild2, // #2 = $ptr
479 : /*1079*/ OPC_CheckChild2Type, MVT::i64,
480 : /*1081*/ OPC_CheckPredicate, 3, // Predicate_unindexedstore
481 : /*1083*/ OPC_CheckPredicate, 9, // Predicate_store
482 : /*1085*/ OPC_CheckPredicate, 22, // Predicate_flat_store
483 : /*1087*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
484 : /*1089*/ OPC_EmitMergeInputChains1_0,
485 : /*1090*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_STORE_DWORDX2), 0|OPFL_Chain|OPFL_MemRefs,
486 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
487 : // Src: (st i64:i64:$value, i64:i64:$ptr)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_flat_store>> - Complexity = 4
488 : // Dst: (FLAT_STORE_DWORDX2 ?:i64:$value, ?:i64:$ptr)
489 : /*1098*/ 0, /*End of Scope*/
490 : /*1099*/ 0, /*End of Scope*/
491 : /*1100*/ /*SwitchOpcode*/ 64|128,6/*832*/, TARGET_VAL(ISD::INTRINSIC_W_CHAIN),// ->1936
492 : /*1104*/ OPC_RecordNode, // #0 = 'intrinsic_w_chain' chained node
493 : /*1105*/ OPC_Scope, 87|128,5/*727*/, /*->1835*/ // 6 children in Scope
494 : /*1108*/ OPC_CheckChild1Integer, 60|128,37/*4796*/,
495 : /*1111*/ OPC_RecordChild2, // #1 = $rsrc
496 : /*1112*/ OPC_CheckChild2Type, MVT::v4i32,
497 : /*1114*/ OPC_Scope, 77, /*->1193*/ // 4 children in Scope
498 : /*1116*/ OPC_MoveChild, 3,
499 : /*1118*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
500 : /*1121*/ OPC_CheckType, MVT::i32,
501 : /*1123*/ OPC_MoveParent,
502 : /*1124*/ OPC_RecordChild4, // #2 = $soffset
503 : /*1125*/ OPC_RecordChild5, // #3 = $offset
504 : /*1126*/ OPC_MoveChild, 5,
505 : /*1128*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
506 : /*1131*/ OPC_MoveParent,
507 : /*1132*/ OPC_MoveChild, 6,
508 : /*1134*/ OPC_CheckInteger, 0,
509 : /*1136*/ OPC_MoveParent,
510 : /*1137*/ OPC_MoveChild, 7,
511 : /*1139*/ OPC_CheckInteger, 0,
512 : /*1141*/ OPC_MoveParent,
513 : /*1142*/ OPC_MoveChild, 8,
514 : /*1144*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
515 : /*1147*/ OPC_RecordNode, // #4 = $glc
516 : /*1148*/ OPC_MoveParent,
517 : /*1149*/ OPC_MoveChild, 9,
518 : /*1151*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
519 : /*1154*/ OPC_RecordNode, // #5 = $slc
520 : /*1155*/ OPC_MoveParent,
521 : /*1156*/ OPC_MoveChild, 10,
522 : /*1158*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
523 : /*1161*/ OPC_RecordNode, // #6 = $tfe
524 : /*1162*/ OPC_MoveParent,
525 : /*1163*/ OPC_CheckType, MVT::i32,
526 : /*1165*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
527 : /*1167*/ OPC_EmitMergeInputChains1_0,
528 : /*1168*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
529 : /*1171*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
530 : /*1174*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
531 : /*1177*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
532 : /*1180*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain,
533 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 1, 2, 7, 8, 9, 10,
534 : // Src: (intrinsic_w_chain:i32 4796:iPTR, v4i32:v4i32:$rsrc, (imm:i32), i32:i32:$soffset, (imm:i32):$offset, 0:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 33
535 : // Dst: (BUFFER_LOAD_DWORD_OFFSET:i32 ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
536 : /*1193*/ /*Scope*/ 86|128,1/*214*/, /*->1409*/
537 : /*1195*/ OPC_RecordChild3, // #2 = $vaddr
538 : /*1196*/ OPC_Scope, 8|128,1/*136*/, /*->1335*/ // 2 children in Scope
539 : /*1199*/ OPC_CheckChild3Type, MVT::i32,
540 : /*1201*/ OPC_RecordChild4, // #3 = $soffset
541 : /*1202*/ OPC_RecordChild5, // #4 = $offset
542 : /*1203*/ OPC_MoveChild, 5,
543 : /*1205*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
544 : /*1208*/ OPC_MoveParent,
545 : /*1209*/ OPC_MoveChild, 6,
546 : /*1211*/ OPC_Scope, 60, /*->1273*/ // 2 children in Scope
547 : /*1213*/ OPC_CheckInteger, 1,
548 : /*1215*/ OPC_MoveParent,
549 : /*1216*/ OPC_MoveChild, 7,
550 : /*1218*/ OPC_CheckInteger, 0,
551 : /*1220*/ OPC_MoveParent,
552 : /*1221*/ OPC_MoveChild, 8,
553 : /*1223*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
554 : /*1226*/ OPC_RecordNode, // #5 = $glc
555 : /*1227*/ OPC_MoveParent,
556 : /*1228*/ OPC_MoveChild, 9,
557 : /*1230*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
558 : /*1233*/ OPC_RecordNode, // #6 = $slc
559 : /*1234*/ OPC_MoveParent,
560 : /*1235*/ OPC_MoveChild, 10,
561 : /*1237*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
562 : /*1240*/ OPC_RecordNode, // #7 = $tfe
563 : /*1241*/ OPC_MoveParent,
564 : /*1242*/ OPC_CheckType, MVT::i32,
565 : /*1244*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
566 : /*1246*/ OPC_EmitMergeInputChains1_0,
567 : /*1247*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
568 : /*1250*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
569 : /*1253*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
570 : /*1256*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
571 : /*1259*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), 0|OPFL_Chain,
572 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11,
573 : // Src: (intrinsic_w_chain:i32 4796:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
574 : // Dst: (BUFFER_LOAD_DWORD_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
575 : /*1273*/ /*Scope*/ 60, /*->1334*/
576 : /*1274*/ OPC_CheckInteger, 0,
577 : /*1276*/ OPC_MoveParent,
578 : /*1277*/ OPC_MoveChild, 7,
579 : /*1279*/ OPC_CheckInteger, 1,
580 : /*1281*/ OPC_MoveParent,
581 : /*1282*/ OPC_MoveChild, 8,
582 : /*1284*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
583 : /*1287*/ OPC_RecordNode, // #5 = $glc
584 : /*1288*/ OPC_MoveParent,
585 : /*1289*/ OPC_MoveChild, 9,
586 : /*1291*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
587 : /*1294*/ OPC_RecordNode, // #6 = $slc
588 : /*1295*/ OPC_MoveParent,
589 : /*1296*/ OPC_MoveChild, 10,
590 : /*1298*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
591 : /*1301*/ OPC_RecordNode, // #7 = $tfe
592 : /*1302*/ OPC_MoveParent,
593 : /*1303*/ OPC_CheckType, MVT::i32,
594 : /*1305*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
595 : /*1307*/ OPC_EmitMergeInputChains1_0,
596 : /*1308*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
597 : /*1311*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
598 : /*1314*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
599 : /*1317*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
600 : /*1320*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_IDXEN), 0|OPFL_Chain,
601 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11,
602 : // Src: (intrinsic_w_chain:i32 4796:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 0:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
603 : // Dst: (BUFFER_LOAD_DWORD_IDXEN:i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
604 : /*1334*/ 0, /*End of Scope*/
605 : /*1335*/ /*Scope*/ 72, /*->1408*/
606 : /*1336*/ OPC_CheckChild3Type, MVT::v2i32,
607 : /*1338*/ OPC_RecordChild4, // #3 = $soffset
608 : /*1339*/ OPC_RecordChild5, // #4 = $offset
609 : /*1340*/ OPC_MoveChild, 5,
610 : /*1342*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
611 : /*1345*/ OPC_MoveParent,
612 : /*1346*/ OPC_MoveChild, 6,
613 : /*1348*/ OPC_CheckInteger, 1,
614 : /*1350*/ OPC_MoveParent,
615 : /*1351*/ OPC_MoveChild, 7,
616 : /*1353*/ OPC_CheckInteger, 1,
617 : /*1355*/ OPC_MoveParent,
618 : /*1356*/ OPC_MoveChild, 8,
619 : /*1358*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
620 : /*1361*/ OPC_RecordNode, // #5 = $glc
621 : /*1362*/ OPC_MoveParent,
622 : /*1363*/ OPC_MoveChild, 9,
623 : /*1365*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
624 : /*1368*/ OPC_RecordNode, // #6 = $slc
625 : /*1369*/ OPC_MoveParent,
626 : /*1370*/ OPC_MoveChild, 10,
627 : /*1372*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
628 : /*1375*/ OPC_RecordNode, // #7 = $tfe
629 : /*1376*/ OPC_MoveParent,
630 : /*1377*/ OPC_CheckType, MVT::i32,
631 : /*1379*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
632 : /*1381*/ OPC_EmitMergeInputChains1_0,
633 : /*1382*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
634 : /*1385*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
635 : /*1388*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
636 : /*1391*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
637 : /*1394*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN), 0|OPFL_Chain,
638 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11,
639 : // Src: (intrinsic_w_chain:i32 4796:iPTR, v4i32:v4i32:$rsrc, v2i32:v2i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
640 : // Dst: (BUFFER_LOAD_DWORD_BOTHEN:i32 ?:v2i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
641 : /*1408*/ 0, /*End of Scope*/
642 : /*1409*/ /*Scope*/ 109, /*->1519*/
643 : /*1410*/ OPC_MoveChild, 3,
644 : /*1412*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
645 : /*1415*/ OPC_CheckType, MVT::i32,
646 : /*1417*/ OPC_MoveParent,
647 : /*1418*/ OPC_RecordChild4, // #2 = $soffset
648 : /*1419*/ OPC_RecordChild5, // #3 = $offset
649 : /*1420*/ OPC_MoveChild, 5,
650 : /*1422*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
651 : /*1425*/ OPC_MoveParent,
652 : /*1426*/ OPC_MoveChild, 6,
653 : /*1428*/ OPC_CheckInteger, 0,
654 : /*1430*/ OPC_MoveParent,
655 : /*1431*/ OPC_MoveChild, 7,
656 : /*1433*/ OPC_CheckInteger, 0,
657 : /*1435*/ OPC_MoveParent,
658 : /*1436*/ OPC_MoveChild, 8,
659 : /*1438*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
660 : /*1441*/ OPC_RecordNode, // #4 = $glc
661 : /*1442*/ OPC_MoveParent,
662 : /*1443*/ OPC_MoveChild, 9,
663 : /*1445*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
664 : /*1448*/ OPC_RecordNode, // #5 = $slc
665 : /*1449*/ OPC_MoveParent,
666 : /*1450*/ OPC_MoveChild, 10,
667 : /*1452*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
668 : /*1455*/ OPC_RecordNode, // #6 = $tfe
669 : /*1456*/ OPC_MoveParent,
670 : /*1457*/ OPC_SwitchType /*2 cases */, 28, MVT::v2i32,// ->1488
671 : /*1460*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
672 : /*1462*/ OPC_EmitMergeInputChains1_0,
673 : /*1463*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
674 : /*1466*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
675 : /*1469*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
676 : /*1472*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
677 : /*1475*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), 0|OPFL_Chain,
678 : 1/*#VTs*/, MVT::v2i32, 6/*#Ops*/, 1, 2, 7, 8, 9, 10,
679 : // Src: (intrinsic_w_chain:v2i32 4796:iPTR, v4i32:v4i32:$rsrc, (imm:i32), i32:i32:$soffset, (imm:i32):$offset, 0:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 33
680 : // Dst: (BUFFER_LOAD_DWORDX2_OFFSET:v2i32 ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
681 : /*1488*/ /*SwitchType*/ 28, MVT::v4i32,// ->1518
682 : /*1490*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
683 : /*1492*/ OPC_EmitMergeInputChains1_0,
684 : /*1493*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
685 : /*1496*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
686 : /*1499*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
687 : /*1502*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
688 : /*1505*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), 0|OPFL_Chain,
689 : 1/*#VTs*/, MVT::v4i32, 6/*#Ops*/, 1, 2, 7, 8, 9, 10,
690 : // Src: (intrinsic_w_chain:v4i32 4796:iPTR, v4i32:v4i32:$rsrc, (imm:i32), i32:i32:$soffset, (imm:i32):$offset, 0:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 33
691 : // Dst: (BUFFER_LOAD_DWORDX4_OFFSET:v4i32 ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
692 : /*1518*/ 0, // EndSwitchType
693 : /*1519*/ /*Scope*/ 57|128,2/*313*/, /*->1834*/
694 : /*1521*/ OPC_RecordChild3, // #2 = $vaddr
695 : /*1522*/ OPC_Scope, 74|128,1/*202*/, /*->1727*/ // 2 children in Scope
696 : /*1525*/ OPC_CheckChild3Type, MVT::i32,
697 : /*1527*/ OPC_RecordChild4, // #3 = $soffset
698 : /*1528*/ OPC_RecordChild5, // #4 = $offset
699 : /*1529*/ OPC_MoveChild, 5,
700 : /*1531*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
701 : /*1534*/ OPC_MoveParent,
702 : /*1535*/ OPC_MoveChild, 6,
703 : /*1537*/ OPC_Scope, 93, /*->1632*/ // 2 children in Scope
704 : /*1539*/ OPC_CheckInteger, 1,
705 : /*1541*/ OPC_MoveParent,
706 : /*1542*/ OPC_MoveChild, 7,
707 : /*1544*/ OPC_CheckInteger, 0,
708 : /*1546*/ OPC_MoveParent,
709 : /*1547*/ OPC_MoveChild, 8,
710 : /*1549*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
711 : /*1552*/ OPC_RecordNode, // #5 = $glc
712 : /*1553*/ OPC_MoveParent,
713 : /*1554*/ OPC_MoveChild, 9,
714 : /*1556*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
715 : /*1559*/ OPC_RecordNode, // #6 = $slc
716 : /*1560*/ OPC_MoveParent,
717 : /*1561*/ OPC_MoveChild, 10,
718 : /*1563*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
719 : /*1566*/ OPC_RecordNode, // #7 = $tfe
720 : /*1567*/ OPC_MoveParent,
721 : /*1568*/ OPC_SwitchType /*2 cases */, 29, MVT::v2i32,// ->1600
722 : /*1571*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
723 : /*1573*/ OPC_EmitMergeInputChains1_0,
724 : /*1574*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
725 : /*1577*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
726 : /*1580*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
727 : /*1583*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
728 : /*1586*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), 0|OPFL_Chain,
729 : 1/*#VTs*/, MVT::v2i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11,
730 : // Src: (intrinsic_w_chain:v2i32 4796:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
731 : // Dst: (BUFFER_LOAD_DWORDX2_OFFEN:v2i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
732 : /*1600*/ /*SwitchType*/ 29, MVT::v4i32,// ->1631
733 : /*1602*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
734 : /*1604*/ OPC_EmitMergeInputChains1_0,
735 : /*1605*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
736 : /*1608*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
737 : /*1611*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
738 : /*1614*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
739 : /*1617*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), 0|OPFL_Chain,
740 : 1/*#VTs*/, MVT::v4i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11,
741 : // Src: (intrinsic_w_chain:v4i32 4796:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 0:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
742 : // Dst: (BUFFER_LOAD_DWORDX4_OFFEN:v4i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
743 : /*1631*/ 0, // EndSwitchType
744 : /*1632*/ /*Scope*/ 93, /*->1726*/
745 : /*1633*/ OPC_CheckInteger, 0,
746 : /*1635*/ OPC_MoveParent,
747 : /*1636*/ OPC_MoveChild, 7,
748 : /*1638*/ OPC_CheckInteger, 1,
749 : /*1640*/ OPC_MoveParent,
750 : /*1641*/ OPC_MoveChild, 8,
751 : /*1643*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
752 : /*1646*/ OPC_RecordNode, // #5 = $glc
753 : /*1647*/ OPC_MoveParent,
754 : /*1648*/ OPC_MoveChild, 9,
755 : /*1650*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
756 : /*1653*/ OPC_RecordNode, // #6 = $slc
757 : /*1654*/ OPC_MoveParent,
758 : /*1655*/ OPC_MoveChild, 10,
759 : /*1657*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
760 : /*1660*/ OPC_RecordNode, // #7 = $tfe
761 : /*1661*/ OPC_MoveParent,
762 : /*1662*/ OPC_SwitchType /*2 cases */, 29, MVT::v2i32,// ->1694
763 : /*1665*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
764 : /*1667*/ OPC_EmitMergeInputChains1_0,
765 : /*1668*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
766 : /*1671*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
767 : /*1674*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
768 : /*1677*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
769 : /*1680*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN), 0|OPFL_Chain,
770 : 1/*#VTs*/, MVT::v2i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11,
771 : // Src: (intrinsic_w_chain:v2i32 4796:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 0:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
772 : // Dst: (BUFFER_LOAD_DWORDX2_IDXEN:v2i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
773 : /*1694*/ /*SwitchType*/ 29, MVT::v4i32,// ->1725
774 : /*1696*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
775 : /*1698*/ OPC_EmitMergeInputChains1_0,
776 : /*1699*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
777 : /*1702*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
778 : /*1705*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
779 : /*1708*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
780 : /*1711*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN), 0|OPFL_Chain,
781 : 1/*#VTs*/, MVT::v4i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11,
782 : // Src: (intrinsic_w_chain:v4i32 4796:iPTR, v4i32:v4i32:$rsrc, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 0:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
783 : // Dst: (BUFFER_LOAD_DWORDX4_IDXEN:v4i32 ?:i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
784 : /*1725*/ 0, // EndSwitchType
785 : /*1726*/ 0, /*End of Scope*/
786 : /*1727*/ /*Scope*/ 105, /*->1833*/
787 : /*1728*/ OPC_CheckChild3Type, MVT::v2i32,
788 : /*1730*/ OPC_RecordChild4, // #3 = $soffset
789 : /*1731*/ OPC_RecordChild5, // #4 = $offset
790 : /*1732*/ OPC_MoveChild, 5,
791 : /*1734*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
792 : /*1737*/ OPC_MoveParent,
793 : /*1738*/ OPC_MoveChild, 6,
794 : /*1740*/ OPC_CheckInteger, 1,
795 : /*1742*/ OPC_MoveParent,
796 : /*1743*/ OPC_MoveChild, 7,
797 : /*1745*/ OPC_CheckInteger, 1,
798 : /*1747*/ OPC_MoveParent,
799 : /*1748*/ OPC_MoveChild, 8,
800 : /*1750*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
801 : /*1753*/ OPC_RecordNode, // #5 = $glc
802 : /*1754*/ OPC_MoveParent,
803 : /*1755*/ OPC_MoveChild, 9,
804 : /*1757*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
805 : /*1760*/ OPC_RecordNode, // #6 = $slc
806 : /*1761*/ OPC_MoveParent,
807 : /*1762*/ OPC_MoveChild, 10,
808 : /*1764*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
809 : /*1767*/ OPC_RecordNode, // #7 = $tfe
810 : /*1768*/ OPC_MoveParent,
811 : /*1769*/ OPC_SwitchType /*2 cases */, 29, MVT::v2i32,// ->1801
812 : /*1772*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
813 : /*1774*/ OPC_EmitMergeInputChains1_0,
814 : /*1775*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
815 : /*1778*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
816 : /*1781*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
817 : /*1784*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
818 : /*1787*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN), 0|OPFL_Chain,
819 : 1/*#VTs*/, MVT::v2i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11,
820 : // Src: (intrinsic_w_chain:v2i32 4796:iPTR, v4i32:v4i32:$rsrc, v2i32:v2i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
821 : // Dst: (BUFFER_LOAD_DWORDX2_BOTHEN:v2i32 ?:v2i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
822 : /*1801*/ /*SwitchType*/ 29, MVT::v4i32,// ->1832
823 : /*1803*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
824 : /*1805*/ OPC_EmitMergeInputChains1_0,
825 : /*1806*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
826 : /*1809*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
827 : /*1812*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
828 : /*1815*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
829 : /*1818*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN), 0|OPFL_Chain,
830 : 1/*#VTs*/, MVT::v4i32, 7/*#Ops*/, 2, 1, 3, 8, 9, 10, 11,
831 : // Src: (intrinsic_w_chain:v4i32 4796:iPTR, v4i32:v4i32:$rsrc, v2i32:v2i32:$vaddr, i32:i32:$soffset, (imm:i32):$offset, 1:i32, 1:i32, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 30
832 : // Dst: (BUFFER_LOAD_DWORDX4_BOTHEN:v4i32 ?:v2i32:$vaddr, ?:v4i32:$rsrc, ?:i32:$soffset, (as_i16imm:i16 ?:i32:$offset), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe))
833 : /*1832*/ 0, // EndSwitchType
834 : /*1833*/ 0, /*End of Scope*/
835 : /*1834*/ 0, /*End of Scope*/
836 : /*1835*/ /*Scope*/ 23, /*->1859*/
837 : /*1836*/ OPC_CheckChild1Integer, 93|128,37/*4829*/,
838 : /*1839*/ OPC_RecordChild2, // #1 = $vcc
839 : /*1840*/ OPC_RecordChild3, // #2 = $target
840 : /*1841*/ OPC_MoveChild, 3,
841 : /*1843*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
842 : /*1846*/ OPC_MoveParent,
843 : /*1847*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
844 : /*1849*/ OPC_EmitMergeInputChains1_0,
845 : /*1850*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_IF), 0|OPFL_Chain,
846 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 1, 2,
847 : // Src: (intrinsic_w_chain:i64 4829:iPTR, i1:i1:$vcc, (bb:Other):$target) - Complexity = 8
848 : // Dst: (SI_IF:i64 i1:i1:$vcc, (bb:Other):$target)
849 : /*1859*/ /*Scope*/ 23, /*->1883*/
850 : /*1860*/ OPC_CheckChild1Integer, 61|128,37/*4797*/,
851 : /*1863*/ OPC_RecordChild2, // #1 = $src
852 : /*1864*/ OPC_RecordChild3, // #2 = $target
853 : /*1865*/ OPC_MoveChild, 3,
854 : /*1867*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
855 : /*1870*/ OPC_MoveParent,
856 : /*1871*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
857 : /*1873*/ OPC_EmitMergeInputChains1_0,
858 : /*1874*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_ELSE), 0|OPFL_Chain,
859 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 1, 2,
860 : // Src: (intrinsic_w_chain:i64 4797:iPTR, i64:i64:$src, (bb:Other):$target) - Complexity = 8
861 : // Dst: (SI_ELSE:i64 i64:i64:$src, (bb:Other):$target)
862 : /*1883*/ /*Scope*/ 15, /*->1899*/
863 : /*1884*/ OPC_CheckChild1Integer, 59|128,37/*4795*/,
864 : /*1887*/ OPC_RecordChild2, // #1 = $src
865 : /*1888*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
866 : /*1890*/ OPC_EmitMergeInputChains1_0,
867 : /*1891*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_BREAK), 0|OPFL_Chain,
868 : 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 1,
869 : // Src: (intrinsic_w_chain:i64 4795:iPTR, i64:i64:$src) - Complexity = 8
870 : // Dst: (SI_BREAK:i64 i64:i64:$src)
871 : /*1899*/ /*Scope*/ 17, /*->1917*/
872 : /*1900*/ OPC_CheckChild1Integer, 94|128,37/*4830*/,
873 : /*1903*/ OPC_RecordChild2, // #1 = $vcc
874 : /*1904*/ OPC_RecordChild3, // #2 = $src
875 : /*1905*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
876 : /*1907*/ OPC_EmitMergeInputChains1_0,
877 : /*1908*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_IF_BREAK), 0|OPFL_Chain,
878 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 1, 2,
879 : // Src: (intrinsic_w_chain:i64 4830:iPTR, i1:i1:$vcc, i64:i64:$src) - Complexity = 8
880 : // Dst: (SI_IF_BREAK:i64 i1:i1:$vcc, i64:i64:$src)
881 : /*1917*/ /*Scope*/ 17, /*->1935*/
882 : /*1918*/ OPC_CheckChild1Integer, 62|128,37/*4798*/,
883 : /*1921*/ OPC_RecordChild2, // #1 = $src0
884 : /*1922*/ OPC_RecordChild3, // #2 = $src1
885 : /*1923*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
886 : /*1925*/ OPC_EmitMergeInputChains1_0,
887 : /*1926*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_ELSE_BREAK), 0|OPFL_Chain,
888 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 1, 2,
889 : // Src: (intrinsic_w_chain:i64 4798:iPTR, i64:i64:$src0, i64:i64:$src1) - Complexity = 8
890 : // Dst: (SI_ELSE_BREAK:i64 i64:i64:$src0, i64:i64:$src1)
891 : /*1935*/ 0, /*End of Scope*/
892 : /*1936*/ /*SwitchOpcode*/ 72|128,3/*456*/, TARGET_VAL(AMDGPUISD::TBUFFER_STORE_FORMAT),// ->2396
893 : /*1940*/ OPC_RecordMemRef,
894 : /*1941*/ OPC_RecordNode, // #0 = 'SItbuffer_store' chained node
895 : /*1942*/ OPC_RecordChild1, // #1 = $rsrc
896 : /*1943*/ OPC_RecordChild2, // #2 = $vdata
897 : /*1944*/ OPC_Scope, 111, /*->2057*/ // 3 children in Scope
898 : /*1946*/ OPC_CheckChild2Type, MVT::i32,
899 : /*1948*/ OPC_CheckChild3Integer, 1,
900 : /*1950*/ OPC_RecordChild4, // #3 = $vaddr
901 : /*1951*/ OPC_RecordChild5, // #4 = $soffset
902 : /*1952*/ OPC_RecordChild6, // #5 = $inst_offset
903 : /*1953*/ OPC_MoveChild, 6,
904 : /*1955*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
905 : /*1958*/ OPC_MoveParent,
906 : /*1959*/ OPC_RecordChild7, // #6 = $dfmt
907 : /*1960*/ OPC_MoveChild, 7,
908 : /*1962*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
909 : /*1965*/ OPC_MoveParent,
910 : /*1966*/ OPC_MoveChild, 8,
911 : /*1968*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
912 : /*1971*/ OPC_RecordNode, // #7 = $nfmt
913 : /*1972*/ OPC_MoveParent,
914 : /*1973*/ OPC_MoveChild, 9,
915 : /*1975*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
916 : /*1978*/ OPC_RecordNode, // #8 = $offen
917 : /*1979*/ OPC_MoveParent,
918 : /*1980*/ OPC_MoveChild, 10,
919 : /*1982*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
920 : /*1985*/ OPC_RecordNode, // #9 = $idxen
921 : /*1986*/ OPC_MoveParent,
922 : /*1987*/ OPC_MoveChild, 11,
923 : /*1989*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
924 : /*1992*/ OPC_RecordNode, // #10 = $glc
925 : /*1993*/ OPC_MoveParent,
926 : /*1994*/ OPC_MoveChild, 12,
927 : /*1996*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
928 : /*1999*/ OPC_RecordNode, // #11 = $slc
929 : /*2000*/ OPC_MoveParent,
930 : /*2001*/ OPC_MoveChild, 13,
931 : /*2003*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
932 : /*2006*/ OPC_RecordNode, // #12 = $tfe
933 : /*2007*/ OPC_MoveParent,
934 : /*2008*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
935 : /*2010*/ OPC_EmitMergeInputChains1_0,
936 : /*2011*/ OPC_EmitNodeXForm, 0, 5, // as_i16imm
937 : /*2014*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
938 : /*2017*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
939 : /*2020*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
940 : /*2023*/ OPC_EmitInteger, MVT::i1, 0,
941 : /*2026*/ OPC_EmitNodeXForm, 2, 6, // as_i8imm
942 : /*2029*/ OPC_EmitNodeXForm, 2, 7, // as_i8imm
943 : /*2032*/ OPC_EmitNodeXForm, 1, 11, // as_i1imm
944 : /*2035*/ OPC_EmitNodeXForm, 1, 12, // as_i1imm
945 : /*2038*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TBUFFER_STORE_FORMAT_X), 0|OPFL_Chain|OPFL_MemRefs,
946 : 0/*#VTs*/, 13/*#Ops*/, 2, 13, 14, 15, 16, 17, 18, 19, 3, 1, 20, 21, 4,
947 : // Src: (SItbuffer_store v4i32:v4i32:$rsrc, i32:i32:$vdata, 1:i32, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$inst_offset, (imm:i32):$dfmt, (imm:i32):$nfmt, (imm:i32):$offen, (imm:i32):$idxen, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 32
948 : // Dst: (TBUFFER_STORE_FORMAT_X ?:i32:$vdata, (as_i16imm:i16 ?:i32:$inst_offset), (as_i1imm:i1 ?:i32:$offen), (as_i1imm:i1 ?:i32:$idxen), (as_i1imm:i1 ?:i32:$glc), 0:i1, (as_i8imm:i8 ?:i32:$dfmt), (as_i8imm:i8 ?:i32:$nfmt), ?:i32:$vaddr, ?:v4i32:$rsrc, (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe), ?:i32:$soffset)
949 : /*2057*/ /*Scope*/ 111, /*->2169*/
950 : /*2058*/ OPC_CheckChild2Type, MVT::v2i32,
951 : /*2060*/ OPC_CheckChild3Integer, 2,
952 : /*2062*/ OPC_RecordChild4, // #3 = $vaddr
953 : /*2063*/ OPC_RecordChild5, // #4 = $soffset
954 : /*2064*/ OPC_RecordChild6, // #5 = $inst_offset
955 : /*2065*/ OPC_MoveChild, 6,
956 : /*2067*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
957 : /*2070*/ OPC_MoveParent,
958 : /*2071*/ OPC_RecordChild7, // #6 = $dfmt
959 : /*2072*/ OPC_MoveChild, 7,
960 : /*2074*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
961 : /*2077*/ OPC_MoveParent,
962 : /*2078*/ OPC_MoveChild, 8,
963 : /*2080*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
964 : /*2083*/ OPC_RecordNode, // #7 = $nfmt
965 : /*2084*/ OPC_MoveParent,
966 : /*2085*/ OPC_MoveChild, 9,
967 : /*2087*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
968 : /*2090*/ OPC_RecordNode, // #8 = $offen
969 : /*2091*/ OPC_MoveParent,
970 : /*2092*/ OPC_MoveChild, 10,
971 : /*2094*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
972 : /*2097*/ OPC_RecordNode, // #9 = $idxen
973 : /*2098*/ OPC_MoveParent,
974 : /*2099*/ OPC_MoveChild, 11,
975 : /*2101*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
976 : /*2104*/ OPC_RecordNode, // #10 = $glc
977 : /*2105*/ OPC_MoveParent,
978 : /*2106*/ OPC_MoveChild, 12,
979 : /*2108*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
980 : /*2111*/ OPC_RecordNode, // #11 = $slc
981 : /*2112*/ OPC_MoveParent,
982 : /*2113*/ OPC_MoveChild, 13,
983 : /*2115*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
984 : /*2118*/ OPC_RecordNode, // #12 = $tfe
985 : /*2119*/ OPC_MoveParent,
986 : /*2120*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
987 : /*2122*/ OPC_EmitMergeInputChains1_0,
988 : /*2123*/ OPC_EmitNodeXForm, 0, 5, // as_i16imm
989 : /*2126*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
990 : /*2129*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
991 : /*2132*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
992 : /*2135*/ OPC_EmitInteger, MVT::i1, 0,
993 : /*2138*/ OPC_EmitNodeXForm, 2, 6, // as_i8imm
994 : /*2141*/ OPC_EmitNodeXForm, 2, 7, // as_i8imm
995 : /*2144*/ OPC_EmitNodeXForm, 1, 11, // as_i1imm
996 : /*2147*/ OPC_EmitNodeXForm, 1, 12, // as_i1imm
997 : /*2150*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TBUFFER_STORE_FORMAT_XY), 0|OPFL_Chain|OPFL_MemRefs,
998 : 0/*#VTs*/, 13/*#Ops*/, 2, 13, 14, 15, 16, 17, 18, 19, 3, 1, 20, 21, 4,
999 : // Src: (SItbuffer_store v4i32:v4i32:$rsrc, v2i32:v2i32:$vdata, 2:i32, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$inst_offset, (imm:i32):$dfmt, (imm:i32):$nfmt, (imm:i32):$offen, (imm:i32):$idxen, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 32
1000 : // Dst: (TBUFFER_STORE_FORMAT_XY ?:v2i32:$vdata, (as_i16imm:i16 ?:i32:$inst_offset), (as_i1imm:i1 ?:i32:$offen), (as_i1imm:i1 ?:i32:$idxen), (as_i1imm:i1 ?:i32:$glc), 0:i1, (as_i8imm:i8 ?:i32:$dfmt), (as_i8imm:i8 ?:i32:$nfmt), ?:i32:$vaddr, ?:v4i32:$rsrc, (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe), ?:i32:$soffset)
1001 : /*2169*/ /*Scope*/ 96|128,1/*224*/, /*->2395*/
1002 : /*2171*/ OPC_CheckChild2Type, MVT::v4i32,
1003 : /*2173*/ OPC_Scope, 109, /*->2284*/ // 2 children in Scope
1004 : /*2175*/ OPC_CheckChild3Integer, 3,
1005 : /*2177*/ OPC_RecordChild4, // #3 = $vaddr
1006 : /*2178*/ OPC_RecordChild5, // #4 = $soffset
1007 : /*2179*/ OPC_RecordChild6, // #5 = $inst_offset
1008 : /*2180*/ OPC_MoveChild, 6,
1009 : /*2182*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1010 : /*2185*/ OPC_MoveParent,
1011 : /*2186*/ OPC_RecordChild7, // #6 = $dfmt
1012 : /*2187*/ OPC_MoveChild, 7,
1013 : /*2189*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1014 : /*2192*/ OPC_MoveParent,
1015 : /*2193*/ OPC_MoveChild, 8,
1016 : /*2195*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1017 : /*2198*/ OPC_RecordNode, // #7 = $nfmt
1018 : /*2199*/ OPC_MoveParent,
1019 : /*2200*/ OPC_MoveChild, 9,
1020 : /*2202*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1021 : /*2205*/ OPC_RecordNode, // #8 = $offen
1022 : /*2206*/ OPC_MoveParent,
1023 : /*2207*/ OPC_MoveChild, 10,
1024 : /*2209*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1025 : /*2212*/ OPC_RecordNode, // #9 = $idxen
1026 : /*2213*/ OPC_MoveParent,
1027 : /*2214*/ OPC_MoveChild, 11,
1028 : /*2216*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1029 : /*2219*/ OPC_RecordNode, // #10 = $glc
1030 : /*2220*/ OPC_MoveParent,
1031 : /*2221*/ OPC_MoveChild, 12,
1032 : /*2223*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1033 : /*2226*/ OPC_RecordNode, // #11 = $slc
1034 : /*2227*/ OPC_MoveParent,
1035 : /*2228*/ OPC_MoveChild, 13,
1036 : /*2230*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1037 : /*2233*/ OPC_RecordNode, // #12 = $tfe
1038 : /*2234*/ OPC_MoveParent,
1039 : /*2235*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1040 : /*2237*/ OPC_EmitMergeInputChains1_0,
1041 : /*2238*/ OPC_EmitNodeXForm, 0, 5, // as_i16imm
1042 : /*2241*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
1043 : /*2244*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
1044 : /*2247*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
1045 : /*2250*/ OPC_EmitInteger, MVT::i1, 0,
1046 : /*2253*/ OPC_EmitNodeXForm, 2, 6, // as_i8imm
1047 : /*2256*/ OPC_EmitNodeXForm, 2, 7, // as_i8imm
1048 : /*2259*/ OPC_EmitNodeXForm, 1, 11, // as_i1imm
1049 : /*2262*/ OPC_EmitNodeXForm, 1, 12, // as_i1imm
1050 : /*2265*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TBUFFER_STORE_FORMAT_XYZ), 0|OPFL_Chain|OPFL_MemRefs,
1051 : 0/*#VTs*/, 13/*#Ops*/, 2, 13, 14, 15, 16, 17, 18, 19, 3, 1, 20, 21, 4,
1052 : // Src: (SItbuffer_store v4i32:v4i32:$rsrc, v4i32:v4i32:$vdata, 3:i32, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$inst_offset, (imm:i32):$dfmt, (imm:i32):$nfmt, (imm:i32):$offen, (imm:i32):$idxen, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 32
1053 : // Dst: (TBUFFER_STORE_FORMAT_XYZ ?:v4i32:$vdata, (as_i16imm:i16 ?:i32:$inst_offset), (as_i1imm:i1 ?:i32:$offen), (as_i1imm:i1 ?:i32:$idxen), (as_i1imm:i1 ?:i32:$glc), 0:i1, (as_i8imm:i8 ?:i32:$dfmt), (as_i8imm:i8 ?:i32:$nfmt), ?:i32:$vaddr, ?:v4i32:$rsrc, (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe), ?:i32:$soffset)
1054 : /*2284*/ /*Scope*/ 109, /*->2394*/
1055 : /*2285*/ OPC_CheckChild3Integer, 4,
1056 : /*2287*/ OPC_RecordChild4, // #3 = $vaddr
1057 : /*2288*/ OPC_RecordChild5, // #4 = $soffset
1058 : /*2289*/ OPC_RecordChild6, // #5 = $inst_offset
1059 : /*2290*/ OPC_MoveChild, 6,
1060 : /*2292*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1061 : /*2295*/ OPC_MoveParent,
1062 : /*2296*/ OPC_RecordChild7, // #6 = $dfmt
1063 : /*2297*/ OPC_MoveChild, 7,
1064 : /*2299*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1065 : /*2302*/ OPC_MoveParent,
1066 : /*2303*/ OPC_MoveChild, 8,
1067 : /*2305*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1068 : /*2308*/ OPC_RecordNode, // #7 = $nfmt
1069 : /*2309*/ OPC_MoveParent,
1070 : /*2310*/ OPC_MoveChild, 9,
1071 : /*2312*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1072 : /*2315*/ OPC_RecordNode, // #8 = $offen
1073 : /*2316*/ OPC_MoveParent,
1074 : /*2317*/ OPC_MoveChild, 10,
1075 : /*2319*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1076 : /*2322*/ OPC_RecordNode, // #9 = $idxen
1077 : /*2323*/ OPC_MoveParent,
1078 : /*2324*/ OPC_MoveChild, 11,
1079 : /*2326*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1080 : /*2329*/ OPC_RecordNode, // #10 = $glc
1081 : /*2330*/ OPC_MoveParent,
1082 : /*2331*/ OPC_MoveChild, 12,
1083 : /*2333*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1084 : /*2336*/ OPC_RecordNode, // #11 = $slc
1085 : /*2337*/ OPC_MoveParent,
1086 : /*2338*/ OPC_MoveChild, 13,
1087 : /*2340*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1088 : /*2343*/ OPC_RecordNode, // #12 = $tfe
1089 : /*2344*/ OPC_MoveParent,
1090 : /*2345*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1091 : /*2347*/ OPC_EmitMergeInputChains1_0,
1092 : /*2348*/ OPC_EmitNodeXForm, 0, 5, // as_i16imm
1093 : /*2351*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
1094 : /*2354*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
1095 : /*2357*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
1096 : /*2360*/ OPC_EmitInteger, MVT::i1, 0,
1097 : /*2363*/ OPC_EmitNodeXForm, 2, 6, // as_i8imm
1098 : /*2366*/ OPC_EmitNodeXForm, 2, 7, // as_i8imm
1099 : /*2369*/ OPC_EmitNodeXForm, 1, 11, // as_i1imm
1100 : /*2372*/ OPC_EmitNodeXForm, 1, 12, // as_i1imm
1101 : /*2375*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TBUFFER_STORE_FORMAT_XYZW), 0|OPFL_Chain|OPFL_MemRefs,
1102 : 0/*#VTs*/, 13/*#Ops*/, 2, 13, 14, 15, 16, 17, 18, 19, 3, 1, 20, 21, 4,
1103 : // Src: (SItbuffer_store v4i32:v4i32:$rsrc, v4i32:v4i32:$vdata, 4:i32, i32:i32:$vaddr, i32:i32:$soffset, (imm:i32):$inst_offset, (imm:i32):$dfmt, (imm:i32):$nfmt, (imm:i32):$offen, (imm:i32):$idxen, (imm:i32):$glc, (imm:i32):$slc, (imm:i32):$tfe) - Complexity = 32
1104 : // Dst: (TBUFFER_STORE_FORMAT_XYZW ?:v4i32:$vdata, (as_i16imm:i16 ?:i32:$inst_offset), (as_i1imm:i1 ?:i32:$offen), (as_i1imm:i1 ?:i32:$idxen), (as_i1imm:i1 ?:i32:$glc), 0:i1, (as_i8imm:i8 ?:i32:$dfmt), (as_i8imm:i8 ?:i32:$nfmt), ?:i32:$vaddr, ?:v4i32:$rsrc, (as_i1imm:i1 ?:i32:$slc), (as_i1imm:i1 ?:i32:$tfe), ?:i32:$soffset)
1105 : /*2394*/ 0, /*End of Scope*/
1106 : /*2395*/ 0, /*End of Scope*/
1107 : /*2396*/ /*SwitchOpcode*/ 106|128,22/*2922*/, TARGET_VAL(ISD::LOAD),// ->5322
1108 : /*2400*/ OPC_RecordMemRef,
1109 : /*2401*/ OPC_RecordNode, // #0 = 'ld' chained node
1110 : /*2402*/ OPC_Scope, 77|128,6/*845*/, /*->3250*/ // 12 children in Scope
1111 : /*2405*/ OPC_RecordChild1, // #1 = $MUBUFAddr64:srsrc:vaddr:soffset:offset:glc:slc:tfe
1112 : /*2406*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
1113 : /*2408*/ OPC_CheckType, MVT::i32,
1114 : /*2410*/ OPC_Scope, 26, /*->2438*/ // 21 children in Scope
1115 : /*2412*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1116 : /*2414*/ OPC_CheckPredicate, 25, // Predicate_az_extloadi8
1117 : /*2416*/ OPC_CheckPredicate, 26, // Predicate_az_extloadi8_global
1118 : /*2418*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1119 : /*2420*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1120 : /*2423*/ OPC_EmitMergeInputChains1_0,
1121 : /*2424*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1122 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1123 : // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_global>> - Complexity = 28
1124 : // Dst: (BUFFER_LOAD_UBYTE_ADDR64:i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1125 : /*2438*/ /*Scope*/ 26, /*->2465*/
1126 : /*2439*/ OPC_CheckPredicate, 27, // Predicate_sextload
1127 : /*2441*/ OPC_CheckPredicate, 28, // Predicate_sextloadi8
1128 : /*2443*/ OPC_CheckPredicate, 29, // Predicate_sextloadi8_global
1129 : /*2445*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1130 : /*2447*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1131 : /*2450*/ OPC_EmitMergeInputChains1_0,
1132 : /*2451*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1133 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1134 : // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> - Complexity = 28
1135 : // Dst: (BUFFER_LOAD_SBYTE_ADDR64:i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1136 : /*2465*/ /*Scope*/ 26, /*->2492*/
1137 : /*2466*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1138 : /*2468*/ OPC_CheckPredicate, 30, // Predicate_az_extloadi16
1139 : /*2470*/ OPC_CheckPredicate, 31, // Predicate_az_extloadi16_global
1140 : /*2472*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1141 : /*2474*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1142 : /*2477*/ OPC_EmitMergeInputChains1_0,
1143 : /*2478*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1144 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1145 : // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_az_extloadi16_global>> - Complexity = 28
1146 : // Dst: (BUFFER_LOAD_USHORT_ADDR64:i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1147 : /*2492*/ /*Scope*/ 26, /*->2519*/
1148 : /*2493*/ OPC_CheckPredicate, 27, // Predicate_sextload
1149 : /*2495*/ OPC_CheckPredicate, 32, // Predicate_sextloadi16
1150 : /*2497*/ OPC_CheckPredicate, 33, // Predicate_sextloadi16_global
1151 : /*2499*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1152 : /*2501*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1153 : /*2504*/ OPC_EmitMergeInputChains1_0,
1154 : /*2505*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1155 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1156 : // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>> - Complexity = 28
1157 : // Dst: (BUFFER_LOAD_SSHORT_ADDR64:i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1158 : /*2519*/ /*Scope*/ 24, /*->2544*/
1159 : /*2520*/ OPC_CheckPredicate, 34, // Predicate_load
1160 : /*2522*/ OPC_CheckPredicate, 35, // Predicate_global_load
1161 : /*2524*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1162 : /*2526*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1163 : /*2529*/ OPC_EmitMergeInputChains1_0,
1164 : /*2530*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1165 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1166 : // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 28
1167 : // Dst: (BUFFER_LOAD_DWORD_ADDR64:i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1168 : /*2544*/ /*Scope*/ 26, /*->2571*/
1169 : /*2545*/ OPC_CheckPredicate, 27, // Predicate_sextload
1170 : /*2547*/ OPC_CheckPredicate, 28, // Predicate_sextloadi8
1171 : /*2549*/ OPC_CheckPredicate, 36, // Predicate_sextloadi8_constant
1172 : /*2551*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1173 : /*2553*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1174 : /*2556*/ OPC_EmitMergeInputChains1_0,
1175 : /*2557*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1176 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1177 : // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>> - Complexity = 28
1178 : // Dst: (BUFFER_LOAD_SBYTE_ADDR64:i32 ?:i64:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
1179 : /*2571*/ /*Scope*/ 26, /*->2598*/
1180 : /*2572*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1181 : /*2574*/ OPC_CheckPredicate, 25, // Predicate_az_extloadi8
1182 : /*2576*/ OPC_CheckPredicate, 37, // Predicate_az_extloadi8_constant
1183 : /*2578*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1184 : /*2580*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1185 : /*2583*/ OPC_EmitMergeInputChains1_0,
1186 : /*2584*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1187 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1188 : // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_constant>> - Complexity = 28
1189 : // Dst: (BUFFER_LOAD_UBYTE_ADDR64:i32 ?:i64:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
1190 : /*2598*/ /*Scope*/ 26, /*->2625*/
1191 : /*2599*/ OPC_CheckPredicate, 27, // Predicate_sextload
1192 : /*2601*/ OPC_CheckPredicate, 32, // Predicate_sextloadi16
1193 : /*2603*/ OPC_CheckPredicate, 38, // Predicate_sextloadi16_constant
1194 : /*2605*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1195 : /*2607*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1196 : /*2610*/ OPC_EmitMergeInputChains1_0,
1197 : /*2611*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1198 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1199 : // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_constant>> - Complexity = 28
1200 : // Dst: (BUFFER_LOAD_SSHORT_ADDR64:i32 ?:i64:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
1201 : /*2625*/ /*Scope*/ 26, /*->2652*/
1202 : /*2626*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1203 : /*2628*/ OPC_CheckPredicate, 30, // Predicate_az_extloadi16
1204 : /*2630*/ OPC_CheckPredicate, 39, // Predicate_az_extloadi16_constant
1205 : /*2632*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1206 : /*2634*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1207 : /*2637*/ OPC_EmitMergeInputChains1_0,
1208 : /*2638*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1209 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1210 : // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_az_extloadi16_constant>> - Complexity = 28
1211 : // Dst: (BUFFER_LOAD_USHORT_ADDR64:i32 ?:i64:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
1212 : /*2652*/ /*Scope*/ 24, /*->2677*/
1213 : /*2653*/ OPC_CheckPredicate, 34, // Predicate_load
1214 : /*2655*/ OPC_CheckPredicate, 40, // Predicate_constant_load
1215 : /*2657*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1216 : /*2659*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1217 : /*2662*/ OPC_EmitMergeInputChains1_0,
1218 : /*2663*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1219 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1220 : // Src: (ld:i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 28
1221 : // Dst: (BUFFER_LOAD_DWORD_ADDR64:i32 ?:i64:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
1222 : /*2677*/ /*Scope*/ 25, /*->2703*/
1223 : /*2678*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1224 : /*2680*/ OPC_CheckPredicate, 25, // Predicate_az_extloadi8
1225 : /*2682*/ OPC_CheckPredicate, 26, // Predicate_az_extloadi8_global
1226 : /*2684*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1227 : /*2686*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
1228 : /*2689*/ OPC_EmitMergeInputChains1_0,
1229 : /*2690*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
1230 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
1231 : // Src: (ld:i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_global>> - Complexity = 25
1232 : // Dst: (BUFFER_LOAD_UBYTE_OFFSET:i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1233 : /*2703*/ /*Scope*/ 25, /*->2729*/
1234 : /*2704*/ OPC_CheckPredicate, 27, // Predicate_sextload
1235 : /*2706*/ OPC_CheckPredicate, 28, // Predicate_sextloadi8
1236 : /*2708*/ OPC_CheckPredicate, 29, // Predicate_sextloadi8_global
1237 : /*2710*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1238 : /*2712*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
1239 : /*2715*/ OPC_EmitMergeInputChains1_0,
1240 : /*2716*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
1241 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
1242 : // Src: (ld:i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> - Complexity = 25
1243 : // Dst: (BUFFER_LOAD_SBYTE_OFFSET:i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1244 : /*2729*/ /*Scope*/ 25, /*->2755*/
1245 : /*2730*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1246 : /*2732*/ OPC_CheckPredicate, 30, // Predicate_az_extloadi16
1247 : /*2734*/ OPC_CheckPredicate, 31, // Predicate_az_extloadi16_global
1248 : /*2736*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1249 : /*2738*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
1250 : /*2741*/ OPC_EmitMergeInputChains1_0,
1251 : /*2742*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
1252 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
1253 : // Src: (ld:i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_az_extloadi16_global>> - Complexity = 25
1254 : // Dst: (BUFFER_LOAD_USHORT_OFFSET:i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1255 : /*2755*/ /*Scope*/ 25, /*->2781*/
1256 : /*2756*/ OPC_CheckPredicate, 27, // Predicate_sextload
1257 : /*2758*/ OPC_CheckPredicate, 32, // Predicate_sextloadi16
1258 : /*2760*/ OPC_CheckPredicate, 33, // Predicate_sextloadi16_global
1259 : /*2762*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1260 : /*2764*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
1261 : /*2767*/ OPC_EmitMergeInputChains1_0,
1262 : /*2768*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
1263 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
1264 : // Src: (ld:i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>> - Complexity = 25
1265 : // Dst: (BUFFER_LOAD_SSHORT_OFFSET:i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1266 : /*2781*/ /*Scope*/ 23, /*->2805*/
1267 : /*2782*/ OPC_CheckPredicate, 34, // Predicate_load
1268 : /*2784*/ OPC_CheckPredicate, 35, // Predicate_global_load
1269 : /*2786*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1270 : /*2788*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
1271 : /*2791*/ OPC_EmitMergeInputChains1_0,
1272 : /*2792*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
1273 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
1274 : // Src: (ld:i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 25
1275 : // Dst: (BUFFER_LOAD_DWORD_OFFSET:i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1276 : /*2805*/ /*Scope*/ 35, /*->2841*/
1277 : /*2806*/ OPC_CheckPredicate, 27, // Predicate_sextload
1278 : /*2808*/ OPC_CheckPredicate, 28, // Predicate_sextloadi8
1279 : /*2810*/ OPC_CheckPredicate, 41, // Predicate_sextloadi8_private
1280 : /*2812*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1281 : /*2814*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFScratch:$ #2 #3 #4 #5
1282 : /*2817*/ OPC_EmitMergeInputChains1_0,
1283 : /*2818*/ OPC_EmitInteger, MVT::i1, 0,
1284 : /*2821*/ OPC_EmitInteger, MVT::i1, 0,
1285 : /*2824*/ OPC_EmitInteger, MVT::i1, 0,
1286 : /*2827*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
1287 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1288 : // Src: (ld:i32 (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> - Complexity = 19
1289 : // Dst: (BUFFER_LOAD_SBYTE_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
1290 : /*2841*/ /*Scope*/ 35, /*->2877*/
1291 : /*2842*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1292 : /*2844*/ OPC_CheckPredicate, 25, // Predicate_az_extloadi8
1293 : /*2846*/ OPC_CheckPredicate, 42, // Predicate_extloadi8_private
1294 : /*2848*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1295 : /*2850*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFScratch:$ #2 #3 #4 #5
1296 : /*2853*/ OPC_EmitMergeInputChains1_0,
1297 : /*2854*/ OPC_EmitInteger, MVT::i1, 0,
1298 : /*2857*/ OPC_EmitInteger, MVT::i1, 0,
1299 : /*2860*/ OPC_EmitInteger, MVT::i1, 0,
1300 : /*2863*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
1301 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1302 : // Src: (ld:i32 (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_extloadi8_private>> - Complexity = 19
1303 : // Dst: (BUFFER_LOAD_UBYTE_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
1304 : /*2877*/ /*Scope*/ 35, /*->2913*/
1305 : /*2878*/ OPC_CheckPredicate, 27, // Predicate_sextload
1306 : /*2880*/ OPC_CheckPredicate, 32, // Predicate_sextloadi16
1307 : /*2882*/ OPC_CheckPredicate, 43, // Predicate_sextloadi16_private
1308 : /*2884*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1309 : /*2886*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFScratch:$ #2 #3 #4 #5
1310 : /*2889*/ OPC_EmitMergeInputChains1_0,
1311 : /*2890*/ OPC_EmitInteger, MVT::i1, 0,
1312 : /*2893*/ OPC_EmitInteger, MVT::i1, 0,
1313 : /*2896*/ OPC_EmitInteger, MVT::i1, 0,
1314 : /*2899*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_SSHORT_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
1315 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1316 : // Src: (ld:i32 (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>> - Complexity = 19
1317 : // Dst: (BUFFER_LOAD_SSHORT_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
1318 : /*2913*/ /*Scope*/ 35, /*->2949*/
1319 : /*2914*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1320 : /*2916*/ OPC_CheckPredicate, 30, // Predicate_az_extloadi16
1321 : /*2918*/ OPC_CheckPredicate, 44, // Predicate_extloadi16_private
1322 : /*2920*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1323 : /*2922*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFScratch:$ #2 #3 #4 #5
1324 : /*2925*/ OPC_EmitMergeInputChains1_0,
1325 : /*2926*/ OPC_EmitInteger, MVT::i1, 0,
1326 : /*2929*/ OPC_EmitInteger, MVT::i1, 0,
1327 : /*2932*/ OPC_EmitInteger, MVT::i1, 0,
1328 : /*2935*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_USHORT_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
1329 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1330 : // Src: (ld:i32 (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_extloadi16_private>> - Complexity = 19
1331 : // Dst: (BUFFER_LOAD_USHORT_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
1332 : /*2949*/ /*Scope*/ 33, /*->2983*/
1333 : /*2950*/ OPC_CheckPredicate, 34, // Predicate_load
1334 : /*2952*/ OPC_CheckPredicate, 45, // Predicate_load_private
1335 : /*2954*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1336 : /*2956*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFScratch:$ #2 #3 #4 #5
1337 : /*2959*/ OPC_EmitMergeInputChains1_0,
1338 : /*2960*/ OPC_EmitInteger, MVT::i1, 0,
1339 : /*2963*/ OPC_EmitInteger, MVT::i1, 0,
1340 : /*2966*/ OPC_EmitInteger, MVT::i1, 0,
1341 : /*2969*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
1342 : 1/*#VTs*/, MVT::i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1343 : // Src: (ld:i32 (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 19
1344 : // Dst: (BUFFER_LOAD_DWORD_OFFEN:i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
1345 : /*2983*/ /*Scope*/ 8|128,2/*264*/, /*->3249*/
1346 : /*2985*/ OPC_CheckChild1Type, MVT::i32,
1347 : /*2987*/ OPC_Scope, 44, /*->3033*/ // 8 children in Scope
1348 : /*2989*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1349 : /*2991*/ OPC_Scope, 19, /*->3012*/ // 2 children in Scope
1350 : /*2993*/ OPC_CheckPredicate, 25, // Predicate_az_extloadi8
1351 : /*2995*/ OPC_CheckPredicate, 46, // Predicate_load_param_exti8
1352 : /*2997*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
1353 : /*2999*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1354 : /*3002*/ OPC_EmitMergeInputChains1_0,
1355 : /*3003*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_PARAM_8_eg), 0|OPFL_Chain|OPFL_MemRefs,
1356 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1357 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_load_param_exti8>> - Complexity = 13
1358 : // Dst: (VTX_READ_PARAM_8_eg:i32 ADDRVTX_READ:i32:$src_gpr)
1359 : /*3012*/ /*Scope*/ 19, /*->3032*/
1360 : /*3013*/ OPC_CheckPredicate, 30, // Predicate_az_extloadi16
1361 : /*3015*/ OPC_CheckPredicate, 47, // Predicate_load_param_exti16
1362 : /*3017*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
1363 : /*3019*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1364 : /*3022*/ OPC_EmitMergeInputChains1_0,
1365 : /*3023*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_PARAM_16_eg), 0|OPFL_Chain|OPFL_MemRefs,
1366 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1367 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_load_param_exti16>> - Complexity = 13
1368 : // Dst: (VTX_READ_PARAM_16_eg:i32 ADDRVTX_READ:i32:$src_gpr)
1369 : /*3032*/ 0, /*End of Scope*/
1370 : /*3033*/ /*Scope*/ 19, /*->3053*/
1371 : /*3034*/ OPC_CheckPredicate, 34, // Predicate_load
1372 : /*3036*/ OPC_CheckPredicate, 48, // Predicate_load_param
1373 : /*3038*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
1374 : /*3040*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1375 : /*3043*/ OPC_EmitMergeInputChains1_0,
1376 : /*3044*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_PARAM_32_eg), 0|OPFL_Chain|OPFL_MemRefs,
1377 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1378 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_param>> - Complexity = 13
1379 : // Dst: (VTX_READ_PARAM_32_eg:i32 ADDRVTX_READ:i32:$src_gpr)
1380 : /*3053*/ /*Scope*/ 44, /*->3098*/
1381 : /*3054*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1382 : /*3056*/ OPC_Scope, 19, /*->3077*/ // 2 children in Scope
1383 : /*3058*/ OPC_CheckPredicate, 25, // Predicate_az_extloadi8
1384 : /*3060*/ OPC_CheckPredicate, 26, // Predicate_az_extloadi8_global
1385 : /*3062*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
1386 : /*3064*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1387 : /*3067*/ OPC_EmitMergeInputChains1_0,
1388 : /*3068*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_GLOBAL_8_eg), 0|OPFL_Chain|OPFL_MemRefs,
1389 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1390 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_global>> - Complexity = 13
1391 : // Dst: (VTX_READ_GLOBAL_8_eg:i32 ADDRVTX_READ:i32:$src_gpr)
1392 : /*3077*/ /*Scope*/ 19, /*->3097*/
1393 : /*3078*/ OPC_CheckPredicate, 30, // Predicate_az_extloadi16
1394 : /*3080*/ OPC_CheckPredicate, 31, // Predicate_az_extloadi16_global
1395 : /*3082*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
1396 : /*3084*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1397 : /*3087*/ OPC_EmitMergeInputChains1_0,
1398 : /*3088*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_GLOBAL_16_eg), 0|OPFL_Chain|OPFL_MemRefs,
1399 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1400 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_az_extloadi16_global>> - Complexity = 13
1401 : // Dst: (VTX_READ_GLOBAL_16_eg:i32 ADDRVTX_READ:i32:$src_gpr)
1402 : /*3097*/ 0, /*End of Scope*/
1403 : /*3098*/ /*Scope*/ 19, /*->3118*/
1404 : /*3099*/ OPC_CheckPredicate, 34, // Predicate_load
1405 : /*3101*/ OPC_CheckPredicate, 35, // Predicate_global_load
1406 : /*3103*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
1407 : /*3105*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1408 : /*3108*/ OPC_EmitMergeInputChains1_0,
1409 : /*3109*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_GLOBAL_32_eg), 0|OPFL_Chain|OPFL_MemRefs,
1410 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1411 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 13
1412 : // Dst: (VTX_READ_GLOBAL_32_eg:i32 ADDRVTX_READ:i32:$src_gpr)
1413 : /*3118*/ /*Scope*/ 44, /*->3163*/
1414 : /*3119*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1415 : /*3121*/ OPC_Scope, 19, /*->3142*/ // 2 children in Scope
1416 : /*3123*/ OPC_CheckPredicate, 25, // Predicate_az_extloadi8
1417 : /*3125*/ OPC_CheckPredicate, 46, // Predicate_load_param_exti8
1418 : /*3127*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
1419 : /*3129*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1420 : /*3132*/ OPC_EmitMergeInputChains1_0,
1421 : /*3133*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_PARAM_8_cm), 0|OPFL_Chain|OPFL_MemRefs,
1422 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1423 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_load_param_exti8>> - Complexity = 13
1424 : // Dst: (VTX_READ_PARAM_8_cm:i32 ADDRVTX_READ:i32:$src_gpr)
1425 : /*3142*/ /*Scope*/ 19, /*->3162*/
1426 : /*3143*/ OPC_CheckPredicate, 30, // Predicate_az_extloadi16
1427 : /*3145*/ OPC_CheckPredicate, 47, // Predicate_load_param_exti16
1428 : /*3147*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
1429 : /*3149*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1430 : /*3152*/ OPC_EmitMergeInputChains1_0,
1431 : /*3153*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_PARAM_16_cm), 0|OPFL_Chain|OPFL_MemRefs,
1432 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1433 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_load_param_exti16>> - Complexity = 13
1434 : // Dst: (VTX_READ_PARAM_16_cm:i32 ADDRVTX_READ:i32:$src_gpr)
1435 : /*3162*/ 0, /*End of Scope*/
1436 : /*3163*/ /*Scope*/ 19, /*->3183*/
1437 : /*3164*/ OPC_CheckPredicate, 34, // Predicate_load
1438 : /*3166*/ OPC_CheckPredicate, 48, // Predicate_load_param
1439 : /*3168*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
1440 : /*3170*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1441 : /*3173*/ OPC_EmitMergeInputChains1_0,
1442 : /*3174*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_PARAM_32_cm), 0|OPFL_Chain|OPFL_MemRefs,
1443 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1444 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_param>> - Complexity = 13
1445 : // Dst: (VTX_READ_PARAM_32_cm:i32 ADDRVTX_READ:i32:$src_gpr)
1446 : /*3183*/ /*Scope*/ 44, /*->3228*/
1447 : /*3184*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1448 : /*3186*/ OPC_Scope, 19, /*->3207*/ // 2 children in Scope
1449 : /*3188*/ OPC_CheckPredicate, 25, // Predicate_az_extloadi8
1450 : /*3190*/ OPC_CheckPredicate, 26, // Predicate_az_extloadi8_global
1451 : /*3192*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
1452 : /*3194*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1453 : /*3197*/ OPC_EmitMergeInputChains1_0,
1454 : /*3198*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_GLOBAL_8_cm), 0|OPFL_Chain|OPFL_MemRefs,
1455 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1456 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_global>> - Complexity = 13
1457 : // Dst: (VTX_READ_GLOBAL_8_cm:i32 ADDRVTX_READ:i32:$src_gpr)
1458 : /*3207*/ /*Scope*/ 19, /*->3227*/
1459 : /*3208*/ OPC_CheckPredicate, 30, // Predicate_az_extloadi16
1460 : /*3210*/ OPC_CheckPredicate, 31, // Predicate_az_extloadi16_global
1461 : /*3212*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
1462 : /*3214*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1463 : /*3217*/ OPC_EmitMergeInputChains1_0,
1464 : /*3218*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_GLOBAL_16_cm), 0|OPFL_Chain|OPFL_MemRefs,
1465 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1466 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_az_extloadi16_global>> - Complexity = 13
1467 : // Dst: (VTX_READ_GLOBAL_16_cm:i32 ADDRVTX_READ:i32:$src_gpr)
1468 : /*3227*/ 0, /*End of Scope*/
1469 : /*3228*/ /*Scope*/ 19, /*->3248*/
1470 : /*3229*/ OPC_CheckPredicate, 34, // Predicate_load
1471 : /*3231*/ OPC_CheckPredicate, 35, // Predicate_global_load
1472 : /*3233*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
1473 : /*3235*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
1474 : /*3238*/ OPC_EmitMergeInputChains1_0,
1475 : /*3239*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_GLOBAL_32_cm), 0|OPFL_Chain|OPFL_MemRefs,
1476 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 3,
1477 : // Src: (ld:i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 13
1478 : // Dst: (VTX_READ_GLOBAL_32_cm:i32 ADDRVTX_READ:i32:$src_gpr)
1479 : /*3248*/ 0, /*End of Scope*/
1480 : /*3249*/ 0, /*End of Scope*/
1481 : /*3250*/ /*Scope*/ 13|128,1/*141*/, /*->3393*/
1482 : /*3252*/ OPC_CaptureGlueInput,
1483 : /*3253*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
1484 : /*3254*/ OPC_CheckPredicate, 49, // Predicate_si_ld_local
1485 : /*3256*/ OPC_CheckType, MVT::i32,
1486 : /*3258*/ OPC_Scope, 26, /*->3286*/ // 5 children in Scope
1487 : /*3260*/ OPC_CheckPredicate, 50, // Predicate_si_sextload_local
1488 : /*3262*/ OPC_CheckPredicate, 51, // Predicate_si_sextload_local_i8
1489 : /*3264*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1490 : /*3266*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
1491 : /*3269*/ OPC_EmitMergeInputChains1_0,
1492 : /*3270*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
1493 : /*3273*/ OPC_EmitInteger, MVT::i1, 0,
1494 : /*3276*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_READ_I8), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
1495 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 4, 5,
1496 : // Src: (SIld_local:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_sextload_local>><<P:Predicate_si_sextload_local_i8>> - Complexity = 13
1497 : // Dst: (DS_READ_I8:i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
1498 : /*3286*/ /*Scope*/ 26, /*->3313*/
1499 : /*3287*/ OPC_CheckPredicate, 52, // Predicate_si_az_extload_local
1500 : /*3289*/ OPC_CheckPredicate, 53, // Predicate_si_az_extload_local_i8
1501 : /*3291*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1502 : /*3293*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
1503 : /*3296*/ OPC_EmitMergeInputChains1_0,
1504 : /*3297*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
1505 : /*3300*/ OPC_EmitInteger, MVT::i1, 0,
1506 : /*3303*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_READ_U8), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
1507 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 4, 5,
1508 : // Src: (SIld_local:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_az_extload_local>><<P:Predicate_si_az_extload_local_i8>> - Complexity = 13
1509 : // Dst: (DS_READ_U8:i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
1510 : /*3313*/ /*Scope*/ 26, /*->3340*/
1511 : /*3314*/ OPC_CheckPredicate, 50, // Predicate_si_sextload_local
1512 : /*3316*/ OPC_CheckPredicate, 54, // Predicate_si_sextload_local_i16
1513 : /*3318*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1514 : /*3320*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
1515 : /*3323*/ OPC_EmitMergeInputChains1_0,
1516 : /*3324*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
1517 : /*3327*/ OPC_EmitInteger, MVT::i1, 0,
1518 : /*3330*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_READ_I16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
1519 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 4, 5,
1520 : // Src: (SIld_local:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_sextload_local>><<P:Predicate_si_sextload_local_i16>> - Complexity = 13
1521 : // Dst: (DS_READ_I16:i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
1522 : /*3340*/ /*Scope*/ 26, /*->3367*/
1523 : /*3341*/ OPC_CheckPredicate, 52, // Predicate_si_az_extload_local
1524 : /*3343*/ OPC_CheckPredicate, 55, // Predicate_si_az_extload_local_i16
1525 : /*3345*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1526 : /*3347*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
1527 : /*3350*/ OPC_EmitMergeInputChains1_0,
1528 : /*3351*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
1529 : /*3354*/ OPC_EmitInteger, MVT::i1, 0,
1530 : /*3357*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_READ_U16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
1531 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 4, 5,
1532 : // Src: (SIld_local:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_az_extload_local>><<P:Predicate_si_az_extload_local_i16>> - Complexity = 13
1533 : // Dst: (DS_READ_U16:i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
1534 : /*3367*/ /*Scope*/ 24, /*->3392*/
1535 : /*3368*/ OPC_CheckPredicate, 56, // Predicate_si_load_local
1536 : /*3370*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1537 : /*3372*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
1538 : /*3375*/ OPC_EmitMergeInputChains1_0,
1539 : /*3376*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
1540 : /*3379*/ OPC_EmitInteger, MVT::i1, 0,
1541 : /*3382*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_READ_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
1542 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 4, 5,
1543 : // Src: (SIld_local:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_load_local>> - Complexity = 13
1544 : // Dst: (DS_READ_B32:i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
1545 : /*3392*/ 0, /*End of Scope*/
1546 : /*3393*/ /*Scope*/ 11|128,1/*139*/, /*->3534*/
1547 : /*3395*/ OPC_MoveChild, 1,
1548 : /*3397*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
1549 : /*3400*/ OPC_RecordChild0, // #1 = $sbase
1550 : /*3401*/ OPC_RecordChild1, // #2 = $offset
1551 : /*3402*/ OPC_MoveChild, 1,
1552 : /*3404*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1553 : /*3407*/ OPC_Scope, 29, /*->3438*/ // 3 children in Scope
1554 : /*3409*/ OPC_CheckPredicate, 57, // Predicate_IMM8bitDWORD
1555 : /*3411*/ OPC_MoveParent,
1556 : /*3412*/ OPC_CheckType, MVT::i64,
1557 : /*3414*/ OPC_MoveParent,
1558 : /*3415*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
1559 : /*3417*/ OPC_CheckPredicate, 34, // Predicate_load
1560 : /*3419*/ OPC_CheckPredicate, 40, // Predicate_constant_load
1561 : /*3421*/ OPC_CheckType, MVT::i32,
1562 : /*3423*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1563 : /*3425*/ OPC_EmitMergeInputChains1_0,
1564 : /*3426*/ OPC_EmitNodeXForm, 3, 2, // as_dword_i32imm
1565 : /*3429*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_IMM), 0|OPFL_Chain|OPFL_MemRefs,
1566 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 3,
1567 : // Src: (ld:i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM8bitDWORD>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
1568 : // Dst: (S_LOAD_DWORD_IMM:i32 ?:i64:$sbase, (as_dword_i32imm:i32 ?:i64:$offset))
1569 : /*3438*/ /*Scope*/ 29, /*->3468*/
1570 : /*3439*/ OPC_CheckPredicate, 58, // Predicate_IMM20bit
1571 : /*3441*/ OPC_MoveParent,
1572 : /*3442*/ OPC_CheckType, MVT::i64,
1573 : /*3444*/ OPC_MoveParent,
1574 : /*3445*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
1575 : /*3447*/ OPC_CheckPredicate, 34, // Predicate_load
1576 : /*3449*/ OPC_CheckPredicate, 40, // Predicate_constant_load
1577 : /*3451*/ OPC_CheckType, MVT::i32,
1578 : /*3453*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1579 : /*3455*/ OPC_EmitMergeInputChains1_0,
1580 : /*3456*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
1581 : /*3459*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_IMM), 0|OPFL_Chain|OPFL_MemRefs,
1582 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 3,
1583 : // Src: (ld:i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM20bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
1584 : // Dst: (S_LOAD_DWORD_IMM:i32 ?:i64:$sbase, (as_i32imm:i32 ?:i64:$offset))
1585 : /*3468*/ /*Scope*/ 64, /*->3533*/
1586 : /*3469*/ OPC_CheckPredicate, 59, // Predicate_IMM32bit
1587 : /*3471*/ OPC_MoveParent,
1588 : /*3472*/ OPC_CheckType, MVT::i64,
1589 : /*3474*/ OPC_MoveParent,
1590 : /*3475*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
1591 : /*3477*/ OPC_CheckPredicate, 34, // Predicate_load
1592 : /*3479*/ OPC_CheckPredicate, 40, // Predicate_constant_load
1593 : /*3481*/ OPC_CheckType, MVT::i32,
1594 : /*3483*/ OPC_Scope, 23, /*->3508*/ // 2 children in Scope
1595 : /*3485*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1596 : /*3487*/ OPC_EmitMergeInputChains1_0,
1597 : /*3488*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
1598 : /*3491*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
1599 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
1600 : /*3499*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
1601 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 4,
1602 : // Src: (ld:i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
1603 : // Dst: (S_LOAD_DWORD_SGPR:i32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
1604 : /*3508*/ /*Scope*/ 23, /*->3532*/
1605 : /*3509*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1606 : /*3511*/ OPC_EmitMergeInputChains1_0,
1607 : /*3512*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
1608 : /*3515*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
1609 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
1610 : /*3523*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
1611 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 4,
1612 : // Src: (ld:i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
1613 : // Dst: (S_LOAD_DWORD_SGPR:i32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
1614 : /*3532*/ 0, /*End of Scope*/
1615 : /*3533*/ 0, /*End of Scope*/
1616 : /*3534*/ /*Scope*/ 44|128,3/*428*/, /*->3964*/
1617 : /*3536*/ OPC_RecordChild1, // #1 = $sbase
1618 : /*3537*/ OPC_Scope, 52|128,1/*180*/, /*->3720*/ // 2 children in Scope
1619 : /*3540*/ OPC_CheckChild1Type, MVT::i64,
1620 : /*3542*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
1621 : /*3544*/ OPC_Scope, 40, /*->3586*/ // 7 children in Scope
1622 : /*3546*/ OPC_CheckPredicate, 34, // Predicate_load
1623 : /*3548*/ OPC_CheckPredicate, 40, // Predicate_constant_load
1624 : /*3550*/ OPC_CheckType, MVT::i32,
1625 : /*3552*/ OPC_Scope, 15, /*->3569*/ // 2 children in Scope
1626 : /*3554*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1627 : /*3556*/ OPC_EmitMergeInputChains1_0,
1628 : /*3557*/ OPC_EmitInteger, MVT::i32, 0,
1629 : /*3560*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_IMM), 0|OPFL_Chain|OPFL_MemRefs,
1630 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 2,
1631 : // Src: (ld:i32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
1632 : // Dst: (S_LOAD_DWORD_IMM:i32 ?:i64:$sbase, 0:i32)
1633 : /*3569*/ /*Scope*/ 15, /*->3585*/
1634 : /*3570*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1635 : /*3572*/ OPC_EmitMergeInputChains1_0,
1636 : /*3573*/ OPC_EmitInteger, MVT::i32, 0,
1637 : /*3576*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_IMM), 0|OPFL_Chain|OPFL_MemRefs,
1638 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 2,
1639 : // Src: (ld:i32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
1640 : // Dst: (S_LOAD_DWORD_IMM:i32 ?:i64:$sbase, 0:i32)
1641 : /*3585*/ 0, /*End of Scope*/
1642 : /*3586*/ /*Scope*/ 19, /*->3606*/
1643 : /*3587*/ OPC_CheckPredicate, 27, // Predicate_sextload
1644 : /*3589*/ OPC_CheckPredicate, 28, // Predicate_sextloadi8
1645 : /*3591*/ OPC_CheckPredicate, 60, // Predicate_sextloadi8_flat
1646 : /*3593*/ OPC_CheckType, MVT::i32,
1647 : /*3595*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
1648 : /*3597*/ OPC_EmitMergeInputChains1_0,
1649 : /*3598*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_LOAD_SBYTE), 0|OPFL_Chain|OPFL_MemRefs,
1650 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1,
1651 : // Src: (ld:i32 i64:i64:$ptr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>> - Complexity = 4
1652 : // Dst: (FLAT_LOAD_SBYTE:i32 ?:i64:$ptr)
1653 : /*3606*/ /*Scope*/ 19, /*->3626*/
1654 : /*3607*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1655 : /*3609*/ OPC_CheckPredicate, 25, // Predicate_az_extloadi8
1656 : /*3611*/ OPC_CheckPredicate, 61, // Predicate_az_extloadi8_flat
1657 : /*3613*/ OPC_CheckType, MVT::i32,
1658 : /*3615*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
1659 : /*3617*/ OPC_EmitMergeInputChains1_0,
1660 : /*3618*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_LOAD_UBYTE), 0|OPFL_Chain|OPFL_MemRefs,
1661 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1,
1662 : // Src: (ld:i32 i64:i64:$ptr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_flat>> - Complexity = 4
1663 : // Dst: (FLAT_LOAD_UBYTE:i32 ?:i64:$ptr)
1664 : /*3626*/ /*Scope*/ 19, /*->3646*/
1665 : /*3627*/ OPC_CheckPredicate, 27, // Predicate_sextload
1666 : /*3629*/ OPC_CheckPredicate, 32, // Predicate_sextloadi16
1667 : /*3631*/ OPC_CheckPredicate, 62, // Predicate_sextloadi16_flat
1668 : /*3633*/ OPC_CheckType, MVT::i32,
1669 : /*3635*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
1670 : /*3637*/ OPC_EmitMergeInputChains1_0,
1671 : /*3638*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_LOAD_SSHORT), 0|OPFL_Chain|OPFL_MemRefs,
1672 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1,
1673 : // Src: (ld:i32 i64:i64:$ptr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>> - Complexity = 4
1674 : // Dst: (FLAT_LOAD_SSHORT:i32 ?:i64:$ptr)
1675 : /*3646*/ /*Scope*/ 19, /*->3666*/
1676 : /*3647*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1677 : /*3649*/ OPC_CheckPredicate, 30, // Predicate_az_extloadi16
1678 : /*3651*/ OPC_CheckPredicate, 63, // Predicate_az_extloadi16_flat
1679 : /*3653*/ OPC_CheckType, MVT::i32,
1680 : /*3655*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
1681 : /*3657*/ OPC_EmitMergeInputChains1_0,
1682 : /*3658*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_LOAD_USHORT), 0|OPFL_Chain|OPFL_MemRefs,
1683 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1,
1684 : // Src: (ld:i32 i64:i64:$ptr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_az_extloadi16_flat>> - Complexity = 4
1685 : // Dst: (FLAT_LOAD_USHORT:i32 ?:i64:$ptr)
1686 : /*3666*/ /*Scope*/ 32, /*->3699*/
1687 : /*3667*/ OPC_CheckPredicate, 34, // Predicate_load
1688 : /*3669*/ OPC_CheckPredicate, 64, // Predicate_flat_load
1689 : /*3671*/ OPC_SwitchType /*2 cases */, 11, MVT::i32,// ->3685
1690 : /*3674*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
1691 : /*3676*/ OPC_EmitMergeInputChains1_0,
1692 : /*3677*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_LOAD_DWORD), 0|OPFL_Chain|OPFL_MemRefs,
1693 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1,
1694 : // Src: (ld:i32 i64:i64:$ptr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_flat_load>> - Complexity = 4
1695 : // Dst: (FLAT_LOAD_DWORD:i32 ?:i64:$ptr)
1696 : /*3685*/ /*SwitchType*/ 11, MVT::i64,// ->3698
1697 : /*3687*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
1698 : /*3689*/ OPC_EmitMergeInputChains1_0,
1699 : /*3690*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_LOAD_DWORDX2), 0|OPFL_Chain|OPFL_MemRefs,
1700 : 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 1,
1701 : // Src: (ld:i64 i64:i64:$ptr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_flat_load>> - Complexity = 4
1702 : // Dst: (FLAT_LOAD_DWORDX2:i64 ?:i64:$ptr)
1703 : /*3698*/ 0, // EndSwitchType
1704 : /*3699*/ /*Scope*/ 19, /*->3719*/
1705 : /*3700*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1706 : /*3702*/ OPC_CheckPredicate, 65, // Predicate_az_extloadi32
1707 : /*3704*/ OPC_CheckPredicate, 66, // Predicate_az_extloadi32_flat
1708 : /*3706*/ OPC_CheckType, MVT::i64,
1709 : /*3708*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
1710 : /*3710*/ OPC_EmitMergeInputChains1_0,
1711 : /*3711*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_LOAD_DWORDX2), 0|OPFL_Chain|OPFL_MemRefs,
1712 : 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 1,
1713 : // Src: (ld:i64 i64:i64:$ptr)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi32>><<P:Predicate_az_extloadi32_flat>> - Complexity = 4
1714 : // Dst: (FLAT_LOAD_DWORDX2:i64 ?:i64:$ptr)
1715 : /*3719*/ 0, /*End of Scope*/
1716 : /*3720*/ /*Scope*/ 113|128,1/*241*/, /*->3963*/
1717 : /*3722*/ OPC_CheckChild1Type, MVT::i32,
1718 : /*3724*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
1719 : /*3726*/ OPC_CheckType, MVT::i32,
1720 : /*3728*/ OPC_Scope, 44, /*->3774*/ // 5 children in Scope
1721 : /*3730*/ OPC_CheckPredicate, 34, // Predicate_load
1722 : /*3732*/ OPC_CheckPredicate, 67, // Predicate_local_load
1723 : /*3734*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
1724 : /*3736*/ OPC_EmitMergeInputChains1_0,
1725 : /*3737*/ OPC_EmitInteger, MVT::i32, 0,
1726 : /*3740*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
1727 : /*3752*/ OPC_EmitInteger, MVT::i32, 1,
1728 : /*3755*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
1729 : /*3758*/ OPC_EmitInteger, MVT::i32, 0,
1730 : /*3761*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_READ_RET), 0|OPFL_Chain|OPFL_MemRefs,
1731 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 1, 2, 3, 4, 5, 6,
1732 : // Src: (ld:i32 R600_Reg32:i32:$src0)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_local_load>> - Complexity = 4
1733 : // Dst: (LDS_READ_RET:i32 R600_Reg32:i32:$src0)
1734 : /*3774*/ /*Scope*/ 46, /*->3821*/
1735 : /*3775*/ OPC_CheckPredicate, 27, // Predicate_sextload
1736 : /*3777*/ OPC_CheckPredicate, 28, // Predicate_sextloadi8
1737 : /*3779*/ OPC_CheckPredicate, 68, // Predicate_sextloadi8_local
1738 : /*3781*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
1739 : /*3783*/ OPC_EmitMergeInputChains1_0,
1740 : /*3784*/ OPC_EmitInteger, MVT::i32, 0,
1741 : /*3787*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
1742 : /*3799*/ OPC_EmitInteger, MVT::i32, 1,
1743 : /*3802*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
1744 : /*3805*/ OPC_EmitInteger, MVT::i32, 0,
1745 : /*3808*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_BYTE_READ_RET), 0|OPFL_Chain|OPFL_MemRefs,
1746 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 1, 2, 3, 4, 5, 6,
1747 : // Src: (ld:i32 i32:i32:$src0)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>> - Complexity = 4
1748 : // Dst: (LDS_BYTE_READ_RET:i32 i32:i32:$src0)
1749 : /*3821*/ /*Scope*/ 46, /*->3868*/
1750 : /*3822*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1751 : /*3824*/ OPC_CheckPredicate, 25, // Predicate_az_extloadi8
1752 : /*3826*/ OPC_CheckPredicate, 69, // Predicate_az_extloadi8_local
1753 : /*3828*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
1754 : /*3830*/ OPC_EmitMergeInputChains1_0,
1755 : /*3831*/ OPC_EmitInteger, MVT::i32, 0,
1756 : /*3834*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
1757 : /*3846*/ OPC_EmitInteger, MVT::i32, 1,
1758 : /*3849*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
1759 : /*3852*/ OPC_EmitInteger, MVT::i32, 0,
1760 : /*3855*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_UBYTE_READ_RET), 0|OPFL_Chain|OPFL_MemRefs,
1761 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 1, 2, 3, 4, 5, 6,
1762 : // Src: (ld:i32 i32:i32:$src0)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi8>><<P:Predicate_az_extloadi8_local>> - Complexity = 4
1763 : // Dst: (LDS_UBYTE_READ_RET:i32 i32:i32:$src0)
1764 : /*3868*/ /*Scope*/ 46, /*->3915*/
1765 : /*3869*/ OPC_CheckPredicate, 27, // Predicate_sextload
1766 : /*3871*/ OPC_CheckPredicate, 32, // Predicate_sextloadi16
1767 : /*3873*/ OPC_CheckPredicate, 70, // Predicate_sextloadi16_local
1768 : /*3875*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
1769 : /*3877*/ OPC_EmitMergeInputChains1_0,
1770 : /*3878*/ OPC_EmitInteger, MVT::i32, 0,
1771 : /*3881*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
1772 : /*3893*/ OPC_EmitInteger, MVT::i32, 1,
1773 : /*3896*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
1774 : /*3899*/ OPC_EmitInteger, MVT::i32, 0,
1775 : /*3902*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_SHORT_READ_RET), 0|OPFL_Chain|OPFL_MemRefs,
1776 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 1, 2, 3, 4, 5, 6,
1777 : // Src: (ld:i32 i32:i32:$src0)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_local>> - Complexity = 4
1778 : // Dst: (LDS_SHORT_READ_RET:i32 i32:i32:$src0)
1779 : /*3915*/ /*Scope*/ 46, /*->3962*/
1780 : /*3916*/ OPC_CheckPredicate, 24, // Predicate_az_extload
1781 : /*3918*/ OPC_CheckPredicate, 30, // Predicate_az_extloadi16
1782 : /*3920*/ OPC_CheckPredicate, 71, // Predicate_az_extloadi16_local
1783 : /*3922*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
1784 : /*3924*/ OPC_EmitMergeInputChains1_0,
1785 : /*3925*/ OPC_EmitInteger, MVT::i32, 0,
1786 : /*3928*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
1787 : /*3940*/ OPC_EmitInteger, MVT::i32, 1,
1788 : /*3943*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
1789 : /*3946*/ OPC_EmitInteger, MVT::i32, 0,
1790 : /*3949*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_USHORT_READ_RET), 0|OPFL_Chain|OPFL_MemRefs,
1791 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 1, 2, 3, 4, 5, 6,
1792 : // Src: (ld:i32 i32:i32:$src0)<<P:Predicate_unindexedload>><<P:Predicate_az_extload>><<P:Predicate_az_extloadi16>><<P:Predicate_az_extloadi16_local>> - Complexity = 4
1793 : // Dst: (LDS_USHORT_READ_RET:i32 i32:i32:$src0)
1794 : /*3962*/ 0, /*End of Scope*/
1795 : /*3963*/ 0, /*End of Scope*/
1796 : /*3964*/ /*Scope*/ 11|128,1/*139*/, /*->4105*/
1797 : /*3966*/ OPC_MoveChild, 1,
1798 : /*3968*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
1799 : /*3971*/ OPC_RecordChild0, // #1 = $sbase
1800 : /*3972*/ OPC_RecordChild1, // #2 = $offset
1801 : /*3973*/ OPC_MoveChild, 1,
1802 : /*3975*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
1803 : /*3978*/ OPC_Scope, 29, /*->4009*/ // 3 children in Scope
1804 : /*3980*/ OPC_CheckPredicate, 57, // Predicate_IMM8bitDWORD
1805 : /*3982*/ OPC_MoveParent,
1806 : /*3983*/ OPC_CheckType, MVT::i64,
1807 : /*3985*/ OPC_MoveParent,
1808 : /*3986*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
1809 : /*3988*/ OPC_CheckPredicate, 34, // Predicate_load
1810 : /*3990*/ OPC_CheckPredicate, 40, // Predicate_constant_load
1811 : /*3992*/ OPC_CheckType, MVT::f32,
1812 : /*3994*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1813 : /*3996*/ OPC_EmitMergeInputChains1_0,
1814 : /*3997*/ OPC_EmitNodeXForm, 3, 2, // as_dword_i32imm
1815 : /*4000*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_IMM), 0|OPFL_Chain|OPFL_MemRefs,
1816 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 1, 3,
1817 : // Src: (ld:f32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM8bitDWORD>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
1818 : // Dst: (S_LOAD_DWORD_IMM:f32 ?:i64:$sbase, (as_dword_i32imm:i32 ?:i64:$offset))
1819 : /*4009*/ /*Scope*/ 29, /*->4039*/
1820 : /*4010*/ OPC_CheckPredicate, 58, // Predicate_IMM20bit
1821 : /*4012*/ OPC_MoveParent,
1822 : /*4013*/ OPC_CheckType, MVT::i64,
1823 : /*4015*/ OPC_MoveParent,
1824 : /*4016*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
1825 : /*4018*/ OPC_CheckPredicate, 34, // Predicate_load
1826 : /*4020*/ OPC_CheckPredicate, 40, // Predicate_constant_load
1827 : /*4022*/ OPC_CheckType, MVT::f32,
1828 : /*4024*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1829 : /*4026*/ OPC_EmitMergeInputChains1_0,
1830 : /*4027*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
1831 : /*4030*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_IMM), 0|OPFL_Chain|OPFL_MemRefs,
1832 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 1, 3,
1833 : // Src: (ld:f32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM20bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
1834 : // Dst: (S_LOAD_DWORD_IMM:f32 ?:i64:$sbase, (as_i32imm:i32 ?:i64:$offset))
1835 : /*4039*/ /*Scope*/ 64, /*->4104*/
1836 : /*4040*/ OPC_CheckPredicate, 59, // Predicate_IMM32bit
1837 : /*4042*/ OPC_MoveParent,
1838 : /*4043*/ OPC_CheckType, MVT::i64,
1839 : /*4045*/ OPC_MoveParent,
1840 : /*4046*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
1841 : /*4048*/ OPC_CheckPredicate, 34, // Predicate_load
1842 : /*4050*/ OPC_CheckPredicate, 40, // Predicate_constant_load
1843 : /*4052*/ OPC_CheckType, MVT::f32,
1844 : /*4054*/ OPC_Scope, 23, /*->4079*/ // 2 children in Scope
1845 : /*4056*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1846 : /*4058*/ OPC_EmitMergeInputChains1_0,
1847 : /*4059*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
1848 : /*4062*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
1849 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
1850 : /*4070*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
1851 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 1, 4,
1852 : // Src: (ld:f32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
1853 : // Dst: (S_LOAD_DWORD_SGPR:f32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
1854 : /*4079*/ /*Scope*/ 23, /*->4103*/
1855 : /*4080*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1856 : /*4082*/ OPC_EmitMergeInputChains1_0,
1857 : /*4083*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
1858 : /*4086*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
1859 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
1860 : /*4094*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
1861 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 1, 4,
1862 : // Src: (ld:f32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
1863 : // Dst: (S_LOAD_DWORD_SGPR:f32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
1864 : /*4103*/ 0, /*End of Scope*/
1865 : /*4104*/ 0, /*End of Scope*/
1866 : /*4105*/ /*Scope*/ 45, /*->4151*/
1867 : /*4106*/ OPC_RecordChild1, // #1 = $sbase
1868 : /*4107*/ OPC_CheckChild1Type, MVT::i64,
1869 : /*4109*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
1870 : /*4111*/ OPC_CheckPredicate, 34, // Predicate_load
1871 : /*4113*/ OPC_CheckPredicate, 40, // Predicate_constant_load
1872 : /*4115*/ OPC_CheckType, MVT::f32,
1873 : /*4117*/ OPC_Scope, 15, /*->4134*/ // 2 children in Scope
1874 : /*4119*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1875 : /*4121*/ OPC_EmitMergeInputChains1_0,
1876 : /*4122*/ OPC_EmitInteger, MVT::i32, 0,
1877 : /*4125*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_IMM), 0|OPFL_Chain|OPFL_MemRefs,
1878 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 1, 2,
1879 : // Src: (ld:f32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
1880 : // Dst: (S_LOAD_DWORD_IMM:f32 ?:i64:$sbase, 0:i32)
1881 : /*4134*/ /*Scope*/ 15, /*->4150*/
1882 : /*4135*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1883 : /*4137*/ OPC_EmitMergeInputChains1_0,
1884 : /*4138*/ OPC_EmitInteger, MVT::i32, 0,
1885 : /*4141*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORD_IMM), 0|OPFL_Chain|OPFL_MemRefs,
1886 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 1, 2,
1887 : // Src: (ld:f32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
1888 : // Dst: (S_LOAD_DWORD_IMM:f32 ?:i64:$sbase, 0:i32)
1889 : /*4150*/ 0, /*End of Scope*/
1890 : /*4151*/ /*Scope*/ 32, /*->4184*/
1891 : /*4152*/ OPC_CaptureGlueInput,
1892 : /*4153*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
1893 : /*4154*/ OPC_CheckPredicate, 49, // Predicate_si_ld_local
1894 : /*4156*/ OPC_CheckPredicate, 56, // Predicate_si_load_local
1895 : /*4158*/ OPC_CheckPredicate, 72, // Predicate_si_load_local_align8
1896 : /*4160*/ OPC_CheckType, MVT::v2i32,
1897 : /*4162*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1898 : /*4164*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
1899 : /*4167*/ OPC_EmitMergeInputChains1_0,
1900 : /*4168*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
1901 : /*4171*/ OPC_EmitInteger, MVT::i1, 0,
1902 : /*4174*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_READ_B64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
1903 : 1/*#VTs*/, MVT::v2i32, 3/*#Ops*/, 2, 4, 5,
1904 : // Src: (SIld_local:v2i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset))<<P:Predicate_si_ld_local>><<P:Predicate_si_load_local>><<P:Predicate_si_load_local_align8>> - Complexity = 113
1905 : // Dst: (DS_READ_B64:v2i32 ?:i32:$ptr, (as_i16imm:i16 ?:i32:$offset), 0:i1)
1906 : /*4184*/ /*Scope*/ 91|128,1/*219*/, /*->4405*/
1907 : /*4186*/ OPC_RecordChild1, // #1 = $MUBUFAddr64:srsrc:vaddr:soffset:offset:glc:slc:tfe
1908 : /*4187*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
1909 : /*4189*/ OPC_CheckPredicate, 34, // Predicate_load
1910 : /*4191*/ OPC_Scope, 48, /*->4241*/ // 4 children in Scope
1911 : /*4193*/ OPC_CheckPredicate, 35, // Predicate_global_load
1912 : /*4195*/ OPC_SwitchType /*2 cases */, 20, MVT::v2i32,// ->4218
1913 : /*4198*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1914 : /*4200*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1915 : /*4203*/ OPC_EmitMergeInputChains1_0,
1916 : /*4204*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1917 : 1/*#VTs*/, MVT::v2i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1918 : // Src: (ld:v2i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 28
1919 : // Dst: (BUFFER_LOAD_DWORDX2_ADDR64:v2i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1920 : /*4218*/ /*SwitchType*/ 20, MVT::v4i32,// ->4240
1921 : /*4220*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1922 : /*4222*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1923 : /*4225*/ OPC_EmitMergeInputChains1_0,
1924 : /*4226*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1925 : 1/*#VTs*/, MVT::v4i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1926 : // Src: (ld:v4i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 28
1927 : // Dst: (BUFFER_LOAD_DWORDX4_ADDR64:v4i32 i64:i64:$vaddr, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1928 : /*4240*/ 0, // EndSwitchType
1929 : /*4241*/ /*Scope*/ 48, /*->4290*/
1930 : /*4242*/ OPC_CheckPredicate, 40, // Predicate_constant_load
1931 : /*4244*/ OPC_SwitchType /*2 cases */, 20, MVT::v2i32,// ->4267
1932 : /*4247*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1933 : /*4249*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1934 : /*4252*/ OPC_EmitMergeInputChains1_0,
1935 : /*4253*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1936 : 1/*#VTs*/, MVT::v2i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1937 : // Src: (ld:v2i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 28
1938 : // Dst: (BUFFER_LOAD_DWORDX2_ADDR64:v2i32 ?:i64:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
1939 : /*4267*/ /*SwitchType*/ 20, MVT::v4i32,// ->4289
1940 : /*4269*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
1941 : /*4271*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // SelectMUBUFAddr64:$ #2 #3 #4 #5 #6 #7 #8
1942 : /*4274*/ OPC_EmitMergeInputChains1_0,
1943 : /*4275*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
1944 : 1/*#VTs*/, MVT::v4i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1945 : // Src: (ld:v4i32 (MUBUFAddr64:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 28
1946 : // Dst: (BUFFER_LOAD_DWORDX4_ADDR64:v4i32 ?:i64:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, ?:i1:$glc, ?:i1:$slc, ?:i1:$tfe)
1947 : /*4289*/ 0, // EndSwitchType
1948 : /*4290*/ /*Scope*/ 46, /*->4337*/
1949 : /*4291*/ OPC_CheckPredicate, 35, // Predicate_global_load
1950 : /*4293*/ OPC_SwitchType /*2 cases */, 19, MVT::v2i32,// ->4315
1951 : /*4296*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1952 : /*4298*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
1953 : /*4301*/ OPC_EmitMergeInputChains1_0,
1954 : /*4302*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
1955 : 1/*#VTs*/, MVT::v2i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
1956 : // Src: (ld:v2i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 25
1957 : // Dst: (BUFFER_LOAD_DWORDX2_OFFSET:v2i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1958 : /*4315*/ /*SwitchType*/ 19, MVT::v4i32,// ->4336
1959 : /*4317*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
1960 : /*4319*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // SelectMUBUFOffset:$ #2 #3 #4 #5 #6 #7
1961 : /*4322*/ OPC_EmitMergeInputChains1_0,
1962 : /*4323*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
1963 : 1/*#VTs*/, MVT::v4i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
1964 : // Src: (ld:v4i32 (MUBUFOffset:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 25
1965 : // Dst: (BUFFER_LOAD_DWORDX4_OFFSET:v4i32 v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$glc, i1:i1:$slc, i1:i1:$tfe)
1966 : /*4336*/ 0, // EndSwitchType
1967 : /*4337*/ /*Scope*/ 66, /*->4404*/
1968 : /*4338*/ OPC_CheckPredicate, 45, // Predicate_load_private
1969 : /*4340*/ OPC_SwitchType /*2 cases */, 29, MVT::v2i32,// ->4372
1970 : /*4343*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1971 : /*4345*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFScratch:$ #2 #3 #4 #5
1972 : /*4348*/ OPC_EmitMergeInputChains1_0,
1973 : /*4349*/ OPC_EmitInteger, MVT::i1, 0,
1974 : /*4352*/ OPC_EmitInteger, MVT::i1, 0,
1975 : /*4355*/ OPC_EmitInteger, MVT::i1, 0,
1976 : /*4358*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
1977 : 1/*#VTs*/, MVT::v2i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1978 : // Src: (ld:v2i32 (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 19
1979 : // Dst: (BUFFER_LOAD_DWORDX2_OFFEN:v2i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
1980 : /*4372*/ /*SwitchType*/ 29, MVT::v4i32,// ->4403
1981 : /*4374*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
1982 : /*4376*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // SelectMUBUFScratch:$ #2 #3 #4 #5
1983 : /*4379*/ OPC_EmitMergeInputChains1_0,
1984 : /*4380*/ OPC_EmitInteger, MVT::i1, 0,
1985 : /*4383*/ OPC_EmitInteger, MVT::i1, 0,
1986 : /*4386*/ OPC_EmitInteger, MVT::i1, 0,
1987 : /*4389*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), 0|OPFL_Chain|OPFL_MemRefs,
1988 : 1/*#VTs*/, MVT::v4i32, 7/*#Ops*/, 3, 2, 4, 5, 6, 7, 8,
1989 : // Src: (ld:v4i32 (MUBUFScratch:iPTR v4i32:v4i32:$srsrc, i32:i32:$vaddr, i32:i32:$soffset, u16imm:i16:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_private>> - Complexity = 19
1990 : // Dst: (BUFFER_LOAD_DWORDX4_OFFEN:v4i32 ?:i32:$vaddr, ?:v4i32:$srsrc, ?:i32:$soffset, ?:i16:$offset, 0:i1, 0:i1, 0:i1)
1991 : /*4403*/ 0, // EndSwitchType
1992 : /*4404*/ 0, /*End of Scope*/
1993 : /*4405*/ /*Scope*/ 28, /*->4434*/
1994 : /*4406*/ OPC_CaptureGlueInput,
1995 : /*4407*/ OPC_RecordChild1, // #1 = $DS64Bit4ByteAligned:ptr:offset0:offset1
1996 : /*4408*/ OPC_CheckPredicate, 49, // Predicate_si_ld_local
1997 : /*4410*/ OPC_CheckPredicate, 56, // Predicate_si_load_local
1998 : /*4412*/ OPC_CheckType, MVT::v2i32,
1999 : /*4414*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
2000 : /*4416*/ OPC_CheckComplexPat, /*CP*/4, /*#*/1, // SelectDS64Bit4ByteAligned:$ #2 #3 #4
2001 : /*4419*/ OPC_EmitMergeInputChains1_0,
2002 : /*4420*/ OPC_EmitInteger, MVT::i1, 0,
2003 : /*4423*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_READ2_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
2004 : 1/*#VTs*/, MVT::v2i32, 4/*#Ops*/, 2, 3, 4, 5,
2005 : // Src: (SIld_local:v2i32 (DS64Bit4ByteAligned:iPTR i32:i32:$ptr, i8:i8:$offset0, i8:i8:$offset1))<<P:Predicate_si_ld_local>><<P:Predicate_si_load_local>> - Complexity = 16
2006 : // Dst: (DS_READ2_B32:v2i32 ?:i32:$ptr, ?:i8:$offset0, ?:i8:$offset1, 0:i1)
2007 : /*4434*/ /*Scope*/ 37|128,1/*165*/, /*->4601*/
2008 : /*4436*/ OPC_RecordChild1, // #1 = $src_gpr
2009 : /*4437*/ OPC_CheckChild1Type, MVT::i32,
2010 : /*4439*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
2011 : /*4441*/ OPC_CheckPredicate, 34, // Predicate_load
2012 : /*4443*/ OPC_Scope, 38, /*->4483*/ // 4 children in Scope
2013 : /*4445*/ OPC_CheckPredicate, 48, // Predicate_load_param
2014 : /*4447*/ OPC_SwitchType /*2 cases */, 15, MVT::v2i32,// ->4465
2015 : /*4450*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
2016 : /*4452*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
2017 : /*4455*/ OPC_EmitMergeInputChains1_0,
2018 : /*4456*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_PARAM_64_eg), 0|OPFL_Chain|OPFL_MemRefs,
2019 : 1/*#VTs*/, MVT::v2i32, 2/*#Ops*/, 2, 3,
2020 : // Src: (ld:v2i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_param>> - Complexity = 13
2021 : // Dst: (VTX_READ_PARAM_64_eg:v2i32 ADDRVTX_READ:i32:$src_gpr)
2022 : /*4465*/ /*SwitchType*/ 15, MVT::v4i32,// ->4482
2023 : /*4467*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
2024 : /*4469*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
2025 : /*4472*/ OPC_EmitMergeInputChains1_0,
2026 : /*4473*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_PARAM_128_eg), 0|OPFL_Chain|OPFL_MemRefs,
2027 : 1/*#VTs*/, MVT::v4i32, 2/*#Ops*/, 2, 3,
2028 : // Src: (ld:v4i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_param>> - Complexity = 13
2029 : // Dst: (VTX_READ_PARAM_128_eg:v4i32 ADDRVTX_READ:i32:$src_gpr)
2030 : /*4482*/ 0, // EndSwitchType
2031 : /*4483*/ /*Scope*/ 38, /*->4522*/
2032 : /*4484*/ OPC_CheckPredicate, 35, // Predicate_global_load
2033 : /*4486*/ OPC_SwitchType /*2 cases */, 15, MVT::v2i32,// ->4504
2034 : /*4489*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
2035 : /*4491*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
2036 : /*4494*/ OPC_EmitMergeInputChains1_0,
2037 : /*4495*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_GLOBAL_64_eg), 0|OPFL_Chain|OPFL_MemRefs,
2038 : 1/*#VTs*/, MVT::v2i32, 2/*#Ops*/, 2, 3,
2039 : // Src: (ld:v2i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 13
2040 : // Dst: (VTX_READ_GLOBAL_64_eg:v2i32 ADDRVTX_READ:i32:$src_gpr)
2041 : /*4504*/ /*SwitchType*/ 15, MVT::v4i32,// ->4521
2042 : /*4506*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
2043 : /*4508*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
2044 : /*4511*/ OPC_EmitMergeInputChains1_0,
2045 : /*4512*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_GLOBAL_128_eg), 0|OPFL_Chain|OPFL_MemRefs,
2046 : 1/*#VTs*/, MVT::v4i32, 2/*#Ops*/, 2, 3,
2047 : // Src: (ld:v4i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 13
2048 : // Dst: (VTX_READ_GLOBAL_128_eg:v4i32 ADDRVTX_READ:i32:$src_gpr)
2049 : /*4521*/ 0, // EndSwitchType
2050 : /*4522*/ /*Scope*/ 38, /*->4561*/
2051 : /*4523*/ OPC_CheckPredicate, 48, // Predicate_load_param
2052 : /*4525*/ OPC_SwitchType /*2 cases */, 15, MVT::v2i32,// ->4543
2053 : /*4528*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
2054 : /*4530*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
2055 : /*4533*/ OPC_EmitMergeInputChains1_0,
2056 : /*4534*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_PARAM_64_cm), 0|OPFL_Chain|OPFL_MemRefs,
2057 : 1/*#VTs*/, MVT::v2i32, 2/*#Ops*/, 2, 3,
2058 : // Src: (ld:v2i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_param>> - Complexity = 13
2059 : // Dst: (VTX_READ_PARAM_64_cm:v2i32 ADDRVTX_READ:i32:$src_gpr)
2060 : /*4543*/ /*SwitchType*/ 15, MVT::v4i32,// ->4560
2061 : /*4545*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
2062 : /*4547*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
2063 : /*4550*/ OPC_EmitMergeInputChains1_0,
2064 : /*4551*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_PARAM_128_cm), 0|OPFL_Chain|OPFL_MemRefs,
2065 : 1/*#VTs*/, MVT::v4i32, 2/*#Ops*/, 2, 3,
2066 : // Src: (ld:v4i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_load_param>> - Complexity = 13
2067 : // Dst: (VTX_READ_PARAM_128_cm:v4i32 ADDRVTX_READ:i32:$src_gpr)
2068 : /*4560*/ 0, // EndSwitchType
2069 : /*4561*/ /*Scope*/ 38, /*->4600*/
2070 : /*4562*/ OPC_CheckPredicate, 35, // Predicate_global_load
2071 : /*4564*/ OPC_SwitchType /*2 cases */, 15, MVT::v2i32,// ->4582
2072 : /*4567*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
2073 : /*4569*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
2074 : /*4572*/ OPC_EmitMergeInputChains1_0,
2075 : /*4573*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_GLOBAL_64_cm), 0|OPFL_Chain|OPFL_MemRefs,
2076 : 1/*#VTs*/, MVT::v2i32, 2/*#Ops*/, 2, 3,
2077 : // Src: (ld:v2i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 13
2078 : // Dst: (VTX_READ_GLOBAL_64_cm:v2i32 ADDRVTX_READ:i32:$src_gpr)
2079 : /*4582*/ /*SwitchType*/ 15, MVT::v4i32,// ->4599
2080 : /*4584*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
2081 : /*4586*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // SelectADDRVTX_READ:$src_gpr #2 #3
2082 : /*4589*/ OPC_EmitMergeInputChains1_0,
2083 : /*4590*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::VTX_READ_GLOBAL_128_cm), 0|OPFL_Chain|OPFL_MemRefs,
2084 : 1/*#VTs*/, MVT::v4i32, 2/*#Ops*/, 2, 3,
2085 : // Src: (ld:v4i32 ADDRVTX_READ:i32:$src_gpr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_global_load>> - Complexity = 13
2086 : // Dst: (VTX_READ_GLOBAL_128_cm:v4i32 ADDRVTX_READ:i32:$src_gpr)
2087 : /*4599*/ 0, // EndSwitchType
2088 : /*4600*/ 0, /*End of Scope*/
2089 : /*4601*/ /*Scope*/ 106|128,3/*490*/, /*->5093*/
2090 : /*4603*/ OPC_MoveChild, 1,
2091 : /*4605*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
2092 : /*4608*/ OPC_RecordChild0, // #1 = $sbase
2093 : /*4609*/ OPC_RecordChild1, // #2 = $offset
2094 : /*4610*/ OPC_MoveChild, 1,
2095 : /*4612*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2096 : /*4615*/ OPC_Scope, 99, /*->4716*/ // 3 children in Scope
2097 : /*4617*/ OPC_CheckPredicate, 57, // Predicate_IMM8bitDWORD
2098 : /*4619*/ OPC_MoveParent,
2099 : /*4620*/ OPC_CheckType, MVT::i64,
2100 : /*4622*/ OPC_MoveParent,
2101 : /*4623*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
2102 : /*4625*/ OPC_CheckPredicate, 34, // Predicate_load
2103 : /*4627*/ OPC_CheckPredicate, 40, // Predicate_constant_load
2104 : /*4629*/ OPC_SwitchType /*5 cases */, 15, MVT::v2i32,// ->4647
2105 : /*4632*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2106 : /*4634*/ OPC_EmitMergeInputChains1_0,
2107 : /*4635*/ OPC_EmitNodeXForm, 3, 2, // as_dword_i32imm
2108 : /*4638*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX2_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2109 : 1/*#VTs*/, MVT::v2i32, 2/*#Ops*/, 1, 3,
2110 : // Src: (ld:v2i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM8bitDWORD>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2111 : // Dst: (S_LOAD_DWORDX2_IMM:v2i32 ?:i64:$sbase, (as_dword_i32imm:i32 ?:i64:$offset))
2112 : /*4647*/ /*SwitchType*/ 15, MVT::v4i32,// ->4664
2113 : /*4649*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2114 : /*4651*/ OPC_EmitMergeInputChains1_0,
2115 : /*4652*/ OPC_EmitNodeXForm, 3, 2, // as_dword_i32imm
2116 : /*4655*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX4_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2117 : 1/*#VTs*/, MVT::v4i32, 2/*#Ops*/, 1, 3,
2118 : // Src: (ld:v4i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM8bitDWORD>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2119 : // Dst: (S_LOAD_DWORDX4_IMM:v4i32 ?:i64:$sbase, (as_dword_i32imm:i32 ?:i64:$offset))
2120 : /*4664*/ /*SwitchType*/ 15, MVT::v32i8,// ->4681
2121 : /*4666*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2122 : /*4668*/ OPC_EmitMergeInputChains1_0,
2123 : /*4669*/ OPC_EmitNodeXForm, 3, 2, // as_dword_i32imm
2124 : /*4672*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2125 : 1/*#VTs*/, MVT::v32i8, 2/*#Ops*/, 1, 3,
2126 : // Src: (ld:v32i8 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM8bitDWORD>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2127 : // Dst: (S_LOAD_DWORDX8_IMM:v32i8 ?:i64:$sbase, (as_dword_i32imm:i32 ?:i64:$offset))
2128 : /*4681*/ /*SwitchType*/ 15, MVT::v8i32,// ->4698
2129 : /*4683*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2130 : /*4685*/ OPC_EmitMergeInputChains1_0,
2131 : /*4686*/ OPC_EmitNodeXForm, 3, 2, // as_dword_i32imm
2132 : /*4689*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2133 : 1/*#VTs*/, MVT::v8i32, 2/*#Ops*/, 1, 3,
2134 : // Src: (ld:v8i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM8bitDWORD>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2135 : // Dst: (S_LOAD_DWORDX8_IMM:v8i32 ?:i64:$sbase, (as_dword_i32imm:i32 ?:i64:$offset))
2136 : /*4698*/ /*SwitchType*/ 15, MVT::v16i32,// ->4715
2137 : /*4700*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2138 : /*4702*/ OPC_EmitMergeInputChains1_0,
2139 : /*4703*/ OPC_EmitNodeXForm, 3, 2, // as_dword_i32imm
2140 : /*4706*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX16_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2141 : 1/*#VTs*/, MVT::v16i32, 2/*#Ops*/, 1, 3,
2142 : // Src: (ld:v16i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM8bitDWORD>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2143 : // Dst: (S_LOAD_DWORDX16_IMM:v16i32 ?:i64:$sbase, (as_dword_i32imm:i32 ?:i64:$offset))
2144 : /*4715*/ 0, // EndSwitchType
2145 : /*4716*/ /*Scope*/ 99, /*->4816*/
2146 : /*4717*/ OPC_CheckPredicate, 58, // Predicate_IMM20bit
2147 : /*4719*/ OPC_MoveParent,
2148 : /*4720*/ OPC_CheckType, MVT::i64,
2149 : /*4722*/ OPC_MoveParent,
2150 : /*4723*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
2151 : /*4725*/ OPC_CheckPredicate, 34, // Predicate_load
2152 : /*4727*/ OPC_CheckPredicate, 40, // Predicate_constant_load
2153 : /*4729*/ OPC_SwitchType /*5 cases */, 15, MVT::v2i32,// ->4747
2154 : /*4732*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2155 : /*4734*/ OPC_EmitMergeInputChains1_0,
2156 : /*4735*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2157 : /*4738*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX2_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2158 : 1/*#VTs*/, MVT::v2i32, 2/*#Ops*/, 1, 3,
2159 : // Src: (ld:v2i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM20bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2160 : // Dst: (S_LOAD_DWORDX2_IMM:v2i32 ?:i64:$sbase, (as_i32imm:i32 ?:i64:$offset))
2161 : /*4747*/ /*SwitchType*/ 15, MVT::v4i32,// ->4764
2162 : /*4749*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2163 : /*4751*/ OPC_EmitMergeInputChains1_0,
2164 : /*4752*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2165 : /*4755*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX4_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2166 : 1/*#VTs*/, MVT::v4i32, 2/*#Ops*/, 1, 3,
2167 : // Src: (ld:v4i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM20bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2168 : // Dst: (S_LOAD_DWORDX4_IMM:v4i32 ?:i64:$sbase, (as_i32imm:i32 ?:i64:$offset))
2169 : /*4764*/ /*SwitchType*/ 15, MVT::v32i8,// ->4781
2170 : /*4766*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2171 : /*4768*/ OPC_EmitMergeInputChains1_0,
2172 : /*4769*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2173 : /*4772*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2174 : 1/*#VTs*/, MVT::v32i8, 2/*#Ops*/, 1, 3,
2175 : // Src: (ld:v32i8 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM20bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2176 : // Dst: (S_LOAD_DWORDX8_IMM:v32i8 ?:i64:$sbase, (as_i32imm:i32 ?:i64:$offset))
2177 : /*4781*/ /*SwitchType*/ 15, MVT::v8i32,// ->4798
2178 : /*4783*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2179 : /*4785*/ OPC_EmitMergeInputChains1_0,
2180 : /*4786*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2181 : /*4789*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2182 : 1/*#VTs*/, MVT::v8i32, 2/*#Ops*/, 1, 3,
2183 : // Src: (ld:v8i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM20bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2184 : // Dst: (S_LOAD_DWORDX8_IMM:v8i32 ?:i64:$sbase, (as_i32imm:i32 ?:i64:$offset))
2185 : /*4798*/ /*SwitchType*/ 15, MVT::v16i32,// ->4815
2186 : /*4800*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2187 : /*4802*/ OPC_EmitMergeInputChains1_0,
2188 : /*4803*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2189 : /*4806*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX16_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2190 : 1/*#VTs*/, MVT::v16i32, 2/*#Ops*/, 1, 3,
2191 : // Src: (ld:v16i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM20bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2192 : // Dst: (S_LOAD_DWORDX16_IMM:v16i32 ?:i64:$sbase, (as_i32imm:i32 ?:i64:$offset))
2193 : /*4815*/ 0, // EndSwitchType
2194 : /*4816*/ /*Scope*/ 18|128,2/*274*/, /*->5092*/
2195 : /*4818*/ OPC_CheckPredicate, 59, // Predicate_IMM32bit
2196 : /*4820*/ OPC_MoveParent,
2197 : /*4821*/ OPC_CheckType, MVT::i64,
2198 : /*4823*/ OPC_MoveParent,
2199 : /*4824*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
2200 : /*4826*/ OPC_CheckPredicate, 34, // Predicate_load
2201 : /*4828*/ OPC_CheckPredicate, 40, // Predicate_constant_load
2202 : /*4830*/ OPC_SwitchType /*5 cases */, 50, MVT::v2i32,// ->4883
2203 : /*4833*/ OPC_Scope, 23, /*->4858*/ // 2 children in Scope
2204 : /*4835*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2205 : /*4837*/ OPC_EmitMergeInputChains1_0,
2206 : /*4838*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2207 : /*4841*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
2208 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
2209 : /*4849*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX2_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
2210 : 1/*#VTs*/, MVT::v2i32, 2/*#Ops*/, 1, 4,
2211 : // Src: (ld:v2i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2212 : // Dst: (S_LOAD_DWORDX2_SGPR:v2i32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
2213 : /*4858*/ /*Scope*/ 23, /*->4882*/
2214 : /*4859*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2215 : /*4861*/ OPC_EmitMergeInputChains1_0,
2216 : /*4862*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2217 : /*4865*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
2218 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
2219 : /*4873*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX2_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
2220 : 1/*#VTs*/, MVT::v2i32, 2/*#Ops*/, 1, 4,
2221 : // Src: (ld:v2i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2222 : // Dst: (S_LOAD_DWORDX2_SGPR:v2i32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
2223 : /*4882*/ 0, /*End of Scope*/
2224 : /*4883*/ /*SwitchType*/ 50, MVT::v4i32,// ->4935
2225 : /*4885*/ OPC_Scope, 23, /*->4910*/ // 2 children in Scope
2226 : /*4887*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2227 : /*4889*/ OPC_EmitMergeInputChains1_0,
2228 : /*4890*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2229 : /*4893*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
2230 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
2231 : /*4901*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX4_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
2232 : 1/*#VTs*/, MVT::v4i32, 2/*#Ops*/, 1, 4,
2233 : // Src: (ld:v4i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2234 : // Dst: (S_LOAD_DWORDX4_SGPR:v4i32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
2235 : /*4910*/ /*Scope*/ 23, /*->4934*/
2236 : /*4911*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2237 : /*4913*/ OPC_EmitMergeInputChains1_0,
2238 : /*4914*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2239 : /*4917*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
2240 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
2241 : /*4925*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX4_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
2242 : 1/*#VTs*/, MVT::v4i32, 2/*#Ops*/, 1, 4,
2243 : // Src: (ld:v4i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2244 : // Dst: (S_LOAD_DWORDX4_SGPR:v4i32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
2245 : /*4934*/ 0, /*End of Scope*/
2246 : /*4935*/ /*SwitchType*/ 50, MVT::v32i8,// ->4987
2247 : /*4937*/ OPC_Scope, 23, /*->4962*/ // 2 children in Scope
2248 : /*4939*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2249 : /*4941*/ OPC_EmitMergeInputChains1_0,
2250 : /*4942*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2251 : /*4945*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
2252 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
2253 : /*4953*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
2254 : 1/*#VTs*/, MVT::v32i8, 2/*#Ops*/, 1, 4,
2255 : // Src: (ld:v32i8 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2256 : // Dst: (S_LOAD_DWORDX8_SGPR:v32i8 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
2257 : /*4962*/ /*Scope*/ 23, /*->4986*/
2258 : /*4963*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2259 : /*4965*/ OPC_EmitMergeInputChains1_0,
2260 : /*4966*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2261 : /*4969*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
2262 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
2263 : /*4977*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
2264 : 1/*#VTs*/, MVT::v32i8, 2/*#Ops*/, 1, 4,
2265 : // Src: (ld:v32i8 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2266 : // Dst: (S_LOAD_DWORDX8_SGPR:v32i8 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
2267 : /*4986*/ 0, /*End of Scope*/
2268 : /*4987*/ /*SwitchType*/ 50, MVT::v8i32,// ->5039
2269 : /*4989*/ OPC_Scope, 23, /*->5014*/ // 2 children in Scope
2270 : /*4991*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2271 : /*4993*/ OPC_EmitMergeInputChains1_0,
2272 : /*4994*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2273 : /*4997*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
2274 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
2275 : /*5005*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
2276 : 1/*#VTs*/, MVT::v8i32, 2/*#Ops*/, 1, 4,
2277 : // Src: (ld:v8i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2278 : // Dst: (S_LOAD_DWORDX8_SGPR:v8i32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
2279 : /*5014*/ /*Scope*/ 23, /*->5038*/
2280 : /*5015*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2281 : /*5017*/ OPC_EmitMergeInputChains1_0,
2282 : /*5018*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2283 : /*5021*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
2284 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
2285 : /*5029*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
2286 : 1/*#VTs*/, MVT::v8i32, 2/*#Ops*/, 1, 4,
2287 : // Src: (ld:v8i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2288 : // Dst: (S_LOAD_DWORDX8_SGPR:v8i32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
2289 : /*5038*/ 0, /*End of Scope*/
2290 : /*5039*/ /*SwitchType*/ 50, MVT::v16i32,// ->5091
2291 : /*5041*/ OPC_Scope, 23, /*->5066*/ // 2 children in Scope
2292 : /*5043*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2293 : /*5045*/ OPC_EmitMergeInputChains1_0,
2294 : /*5046*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2295 : /*5049*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
2296 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
2297 : /*5057*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX16_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
2298 : 1/*#VTs*/, MVT::v16i32, 2/*#Ops*/, 1, 4,
2299 : // Src: (ld:v16i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2300 : // Dst: (S_LOAD_DWORDX16_SGPR:v16i32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
2301 : /*5066*/ /*Scope*/ 23, /*->5090*/
2302 : /*5067*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2303 : /*5069*/ OPC_EmitMergeInputChains1_0,
2304 : /*5070*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
2305 : /*5073*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
2306 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
2307 : /*5081*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX16_SGPR), 0|OPFL_Chain|OPFL_MemRefs,
2308 : 1/*#VTs*/, MVT::v16i32, 2/*#Ops*/, 1, 4,
2309 : // Src: (ld:v16i32 (add:i64 i64:i64:$sbase, (imm:i64)<<P:Predicate_IMM32bit>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 11
2310 : // Dst: (S_LOAD_DWORDX16_SGPR:v16i32 ?:i64:$sbase, (S_MOV_B32:i32 (as_i32imm:i32 ?:i64:$offset)))
2311 : /*5090*/ 0, /*End of Scope*/
2312 : /*5091*/ 0, // EndSwitchType
2313 : /*5092*/ 0, /*End of Scope*/
2314 : /*5093*/ /*Scope*/ 98|128,1/*226*/, /*->5321*/
2315 : /*5095*/ OPC_RecordChild1, // #1 = $sbase
2316 : /*5096*/ OPC_CheckChild1Type, MVT::i64,
2317 : /*5098*/ OPC_CheckPredicate, 23, // Predicate_unindexedload
2318 : /*5100*/ OPC_CheckPredicate, 34, // Predicate_load
2319 : /*5102*/ OPC_Scope, 56|128,1/*184*/, /*->5289*/ // 2 children in Scope
2320 : /*5105*/ OPC_CheckPredicate, 40, // Predicate_constant_load
2321 : /*5107*/ OPC_SwitchType /*5 cases */, 34, MVT::v2i32,// ->5144
2322 : /*5110*/ OPC_Scope, 15, /*->5127*/ // 2 children in Scope
2323 : /*5112*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2324 : /*5114*/ OPC_EmitMergeInputChains1_0,
2325 : /*5115*/ OPC_EmitInteger, MVT::i32, 0,
2326 : /*5118*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX2_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2327 : 1/*#VTs*/, MVT::v2i32, 2/*#Ops*/, 1, 2,
2328 : // Src: (ld:v2i32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
2329 : // Dst: (S_LOAD_DWORDX2_IMM:v2i32 ?:i64:$sbase, 0:i32)
2330 : /*5127*/ /*Scope*/ 15, /*->5143*/
2331 : /*5128*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2332 : /*5130*/ OPC_EmitMergeInputChains1_0,
2333 : /*5131*/ OPC_EmitInteger, MVT::i32, 0,
2334 : /*5134*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX2_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2335 : 1/*#VTs*/, MVT::v2i32, 2/*#Ops*/, 1, 2,
2336 : // Src: (ld:v2i32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
2337 : // Dst: (S_LOAD_DWORDX2_IMM:v2i32 ?:i64:$sbase, 0:i32)
2338 : /*5143*/ 0, /*End of Scope*/
2339 : /*5144*/ /*SwitchType*/ 34, MVT::v4i32,// ->5180
2340 : /*5146*/ OPC_Scope, 15, /*->5163*/ // 2 children in Scope
2341 : /*5148*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2342 : /*5150*/ OPC_EmitMergeInputChains1_0,
2343 : /*5151*/ OPC_EmitInteger, MVT::i32, 0,
2344 : /*5154*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX4_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2345 : 1/*#VTs*/, MVT::v4i32, 2/*#Ops*/, 1, 2,
2346 : // Src: (ld:v4i32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
2347 : // Dst: (S_LOAD_DWORDX4_IMM:v4i32 ?:i64:$sbase, 0:i32)
2348 : /*5163*/ /*Scope*/ 15, /*->5179*/
2349 : /*5164*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2350 : /*5166*/ OPC_EmitMergeInputChains1_0,
2351 : /*5167*/ OPC_EmitInteger, MVT::i32, 0,
2352 : /*5170*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX4_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2353 : 1/*#VTs*/, MVT::v4i32, 2/*#Ops*/, 1, 2,
2354 : // Src: (ld:v4i32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
2355 : // Dst: (S_LOAD_DWORDX4_IMM:v4i32 ?:i64:$sbase, 0:i32)
2356 : /*5179*/ 0, /*End of Scope*/
2357 : /*5180*/ /*SwitchType*/ 34, MVT::v32i8,// ->5216
2358 : /*5182*/ OPC_Scope, 15, /*->5199*/ // 2 children in Scope
2359 : /*5184*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2360 : /*5186*/ OPC_EmitMergeInputChains1_0,
2361 : /*5187*/ OPC_EmitInteger, MVT::i32, 0,
2362 : /*5190*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2363 : 1/*#VTs*/, MVT::v32i8, 2/*#Ops*/, 1, 2,
2364 : // Src: (ld:v32i8 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
2365 : // Dst: (S_LOAD_DWORDX8_IMM:v32i8 ?:i64:$sbase, 0:i32)
2366 : /*5199*/ /*Scope*/ 15, /*->5215*/
2367 : /*5200*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2368 : /*5202*/ OPC_EmitMergeInputChains1_0,
2369 : /*5203*/ OPC_EmitInteger, MVT::i32, 0,
2370 : /*5206*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2371 : 1/*#VTs*/, MVT::v32i8, 2/*#Ops*/, 1, 2,
2372 : // Src: (ld:v32i8 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
2373 : // Dst: (S_LOAD_DWORDX8_IMM:v32i8 ?:i64:$sbase, 0:i32)
2374 : /*5215*/ 0, /*End of Scope*/
2375 : /*5216*/ /*SwitchType*/ 34, MVT::v8i32,// ->5252
2376 : /*5218*/ OPC_Scope, 15, /*->5235*/ // 2 children in Scope
2377 : /*5220*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2378 : /*5222*/ OPC_EmitMergeInputChains1_0,
2379 : /*5223*/ OPC_EmitInteger, MVT::i32, 0,
2380 : /*5226*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2381 : 1/*#VTs*/, MVT::v8i32, 2/*#Ops*/, 1, 2,
2382 : // Src: (ld:v8i32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
2383 : // Dst: (S_LOAD_DWORDX8_IMM:v8i32 ?:i64:$sbase, 0:i32)
2384 : /*5235*/ /*Scope*/ 15, /*->5251*/
2385 : /*5236*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2386 : /*5238*/ OPC_EmitMergeInputChains1_0,
2387 : /*5239*/ OPC_EmitInteger, MVT::i32, 0,
2388 : /*5242*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX8_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2389 : 1/*#VTs*/, MVT::v8i32, 2/*#Ops*/, 1, 2,
2390 : // Src: (ld:v8i32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
2391 : // Dst: (S_LOAD_DWORDX8_IMM:v8i32 ?:i64:$sbase, 0:i32)
2392 : /*5251*/ 0, /*End of Scope*/
2393 : /*5252*/ /*SwitchType*/ 34, MVT::v16i32,// ->5288
2394 : /*5254*/ OPC_Scope, 15, /*->5271*/ // 2 children in Scope
2395 : /*5256*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
2396 : /*5258*/ OPC_EmitMergeInputChains1_0,
2397 : /*5259*/ OPC_EmitInteger, MVT::i32, 0,
2398 : /*5262*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX16_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2399 : 1/*#VTs*/, MVT::v16i32, 2/*#Ops*/, 1, 2,
2400 : // Src: (ld:v16i32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
2401 : // Dst: (S_LOAD_DWORDX16_IMM:v16i32 ?:i64:$sbase, 0:i32)
2402 : /*5271*/ /*Scope*/ 15, /*->5287*/
2403 : /*5272*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2404 : /*5274*/ OPC_EmitMergeInputChains1_0,
2405 : /*5275*/ OPC_EmitInteger, MVT::i32, 0,
2406 : /*5278*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LOAD_DWORDX16_IMM), 0|OPFL_Chain|OPFL_MemRefs,
2407 : 1/*#VTs*/, MVT::v16i32, 2/*#Ops*/, 1, 2,
2408 : // Src: (ld:v16i32 i64:i64:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_constant_load>> - Complexity = 4
2409 : // Dst: (S_LOAD_DWORDX16_IMM:v16i32 ?:i64:$sbase, 0:i32)
2410 : /*5287*/ 0, /*End of Scope*/
2411 : /*5288*/ 0, // EndSwitchType
2412 : /*5289*/ /*Scope*/ 30, /*->5320*/
2413 : /*5290*/ OPC_CheckPredicate, 64, // Predicate_flat_load
2414 : /*5292*/ OPC_SwitchType /*2 cases */, 11, MVT::v2i32,// ->5306
2415 : /*5295*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
2416 : /*5297*/ OPC_EmitMergeInputChains1_0,
2417 : /*5298*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_LOAD_DWORDX2), 0|OPFL_Chain|OPFL_MemRefs,
2418 : 1/*#VTs*/, MVT::v2i32, 1/*#Ops*/, 1,
2419 : // Src: (ld:v2i32 i64:i64:$ptr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_flat_load>> - Complexity = 4
2420 : // Dst: (FLAT_LOAD_DWORDX2:v2i32 ?:i64:$ptr)
2421 : /*5306*/ /*SwitchType*/ 11, MVT::v4i32,// ->5319
2422 : /*5308*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasFlatAddressSpace())
2423 : /*5310*/ OPC_EmitMergeInputChains1_0,
2424 : /*5311*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLAT_LOAD_DWORDX4), 0|OPFL_Chain|OPFL_MemRefs,
2425 : 1/*#VTs*/, MVT::v4i32, 1/*#Ops*/, 1,
2426 : // Src: (ld:v4i32 i64:i64:$ptr)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_flat_load>> - Complexity = 4
2427 : // Dst: (FLAT_LOAD_DWORDX4:v4i32 ?:i64:$ptr)
2428 : /*5319*/ 0, // EndSwitchType
2429 : /*5320*/ 0, /*End of Scope*/
2430 : /*5321*/ 0, /*End of Scope*/
2431 : /*5322*/ /*SwitchOpcode*/ 117|128,9/*1269*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->6595
2432 : /*5326*/ OPC_RecordNode, // #0 = 'intrinsic_void' chained node
2433 : /*5327*/ OPC_Scope, 79, /*->5408*/ // 11 children in Scope
2434 : /*5329*/ OPC_CheckChild1Integer, 64|128,37/*4800*/,
2435 : /*5332*/ OPC_RecordChild2, // #1 = $en
2436 : /*5333*/ OPC_MoveChild, 2,
2437 : /*5335*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2438 : /*5338*/ OPC_MoveParent,
2439 : /*5339*/ OPC_RecordChild3, // #2 = $vm
2440 : /*5340*/ OPC_MoveChild, 3,
2441 : /*5342*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2442 : /*5345*/ OPC_MoveParent,
2443 : /*5346*/ OPC_RecordChild4, // #3 = $done
2444 : /*5347*/ OPC_MoveChild, 4,
2445 : /*5349*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2446 : /*5352*/ OPC_MoveParent,
2447 : /*5353*/ OPC_RecordChild5, // #4 = $tgt
2448 : /*5354*/ OPC_MoveChild, 5,
2449 : /*5356*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2450 : /*5359*/ OPC_MoveParent,
2451 : /*5360*/ OPC_RecordChild6, // #5 = $compr
2452 : /*5361*/ OPC_MoveChild, 6,
2453 : /*5363*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2454 : /*5366*/ OPC_MoveParent,
2455 : /*5367*/ OPC_RecordChild7, // #6 = $src0
2456 : /*5368*/ OPC_MoveChild, 8,
2457 : /*5370*/ OPC_RecordNode, // #7 = $src1
2458 : /*5371*/ OPC_MoveParent,
2459 : /*5372*/ OPC_MoveChild, 9,
2460 : /*5374*/ OPC_RecordNode, // #8 = $src2
2461 : /*5375*/ OPC_MoveParent,
2462 : /*5376*/ OPC_MoveChild, 10,
2463 : /*5378*/ OPC_RecordNode, // #9 = $src3
2464 : /*5379*/ OPC_MoveParent,
2465 : /*5380*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
2466 : /*5382*/ OPC_EmitMergeInputChains1_0,
2467 : /*5383*/ OPC_EmitConvertToTarget, 1,
2468 : /*5385*/ OPC_EmitConvertToTarget, 4,
2469 : /*5387*/ OPC_EmitConvertToTarget, 5,
2470 : /*5389*/ OPC_EmitConvertToTarget, 3,
2471 : /*5391*/ OPC_EmitConvertToTarget, 2,
2472 : /*5393*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EXP), 0|OPFL_Chain,
2473 : 0/*#VTs*/, 9/*#Ops*/, 10, 11, 12, 13, 14, 6, 7, 8, 9,
2474 : // Src: (intrinsic_void 4800:iPTR, (imm:i32):$en, (imm:i32):$vm, (imm:i32):$done, (imm:i32):$tgt, (imm:i32):$compr, f32:f32:$src0, f32:f32:$src1, f32:f32:$src2, f32:f32:$src3) - Complexity = 23
2475 : // Dst: (EXP (imm:i32):$en, (imm:i32):$tgt, (imm:i32):$compr, (imm:i32):$done, (imm:i32):$vm, ?:f32:$src0, ?:f32:$src1, ?:f32:$src2, ?:f32:$src3)
2476 : /*5408*/ /*Scope*/ 77|128,2/*333*/, /*->5743*/
2477 : /*5410*/ OPC_CheckChild1Integer, 49|128,37/*4785*/,
2478 : /*5413*/ OPC_RecordChild2, // #1 = $src
2479 : /*5414*/ OPC_RecordChild3, // #2 = $arraybase
2480 : /*5415*/ OPC_MoveChild, 3,
2481 : /*5417*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2482 : /*5420*/ OPC_MoveParent,
2483 : /*5421*/ OPC_Scope, 79, /*->5502*/ // 4 children in Scope
2484 : /*5423*/ OPC_CheckChild4Integer, 0,
2485 : /*5425*/ OPC_RecordChild5, // #3 = $mask
2486 : /*5426*/ OPC_MoveChild, 5,
2487 : /*5428*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2488 : /*5431*/ OPC_MoveParent,
2489 : /*5432*/ OPC_Scope, 33, /*->5467*/ // 2 children in Scope
2490 : /*5434*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
2491 : /*5436*/ OPC_EmitMergeInputChains1_0,
2492 : /*5437*/ OPC_EmitInteger, MVT::i32, 0,
2493 : /*5440*/ OPC_EmitConvertToTarget, 2,
2494 : /*5442*/ OPC_EmitInteger, MVT::i32, 127|128,31/*4095*/,
2495 : /*5446*/ OPC_EmitConvertToTarget, 3,
2496 : /*5448*/ OPC_EmitInteger, MVT::i32, 32,
2497 : /*5451*/ OPC_EmitInteger, MVT::i32, 0,
2498 : /*5454*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_ExportBuf), 0|OPFL_Chain,
2499 : 0/*#VTs*/, 7/*#Ops*/, 1, 4, 5, 6, 7, 8, 9,
2500 : // Src: (intrinsic_void 4785:iPTR, R600_Reg128:v4f32:$src, (imm:i32):$arraybase, 0:i32, (imm:i32):$mask) - Complexity = 19
2501 : // Dst: (R600_ExportBuf R600_Reg128:v4f32:$src, 0:i32, (imm:i32):$arraybase, 4095:i32, (imm:i32):$mask, 32:i32, 0:i32)
2502 : /*5467*/ /*Scope*/ 33, /*->5501*/
2503 : /*5468*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
2504 : /*5470*/ OPC_EmitMergeInputChains1_0,
2505 : /*5471*/ OPC_EmitInteger, MVT::i32, 0,
2506 : /*5474*/ OPC_EmitConvertToTarget, 2,
2507 : /*5476*/ OPC_EmitInteger, MVT::i32, 127|128,31/*4095*/,
2508 : /*5480*/ OPC_EmitConvertToTarget, 3,
2509 : /*5482*/ OPC_EmitInteger, MVT::i32, 64,
2510 : /*5485*/ OPC_EmitInteger, MVT::i32, 0,
2511 : /*5488*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EG_ExportBuf), 0|OPFL_Chain,
2512 : 0/*#VTs*/, 7/*#Ops*/, 1, 4, 5, 6, 7, 8, 9,
2513 : // Src: (intrinsic_void 4785:iPTR, R600_Reg128:v4f32:$src, (imm:i32):$arraybase, 0:i32, (imm:i32):$mask) - Complexity = 19
2514 : // Dst: (EG_ExportBuf R600_Reg128:v4f32:$src, 0:i32, (imm:i32):$arraybase, 4095:i32, (imm:i32):$mask, 64:i32, 0:i32)
2515 : /*5501*/ 0, /*End of Scope*/
2516 : /*5502*/ /*Scope*/ 79, /*->5582*/
2517 : /*5503*/ OPC_CheckChild4Integer, 1,
2518 : /*5505*/ OPC_RecordChild5, // #3 = $mask
2519 : /*5506*/ OPC_MoveChild, 5,
2520 : /*5508*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2521 : /*5511*/ OPC_MoveParent,
2522 : /*5512*/ OPC_Scope, 33, /*->5547*/ // 2 children in Scope
2523 : /*5514*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
2524 : /*5516*/ OPC_EmitMergeInputChains1_0,
2525 : /*5517*/ OPC_EmitInteger, MVT::i32, 0,
2526 : /*5520*/ OPC_EmitConvertToTarget, 2,
2527 : /*5522*/ OPC_EmitInteger, MVT::i32, 127|128,31/*4095*/,
2528 : /*5526*/ OPC_EmitConvertToTarget, 3,
2529 : /*5528*/ OPC_EmitInteger, MVT::i32, 33,
2530 : /*5531*/ OPC_EmitInteger, MVT::i32, 0,
2531 : /*5534*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_ExportBuf), 0|OPFL_Chain,
2532 : 0/*#VTs*/, 7/*#Ops*/, 1, 4, 5, 6, 7, 8, 9,
2533 : // Src: (intrinsic_void 4785:iPTR, R600_Reg128:v4f32:$src, (imm:i32):$arraybase, 1:i32, (imm:i32):$mask) - Complexity = 19
2534 : // Dst: (R600_ExportBuf ?:v4f32:$src, 0:i32, (imm:i32):$arraybase, 4095:i32, (imm:i32):$mask, 33:i32, 0:i32)
2535 : /*5547*/ /*Scope*/ 33, /*->5581*/
2536 : /*5548*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
2537 : /*5550*/ OPC_EmitMergeInputChains1_0,
2538 : /*5551*/ OPC_EmitInteger, MVT::i32, 0,
2539 : /*5554*/ OPC_EmitConvertToTarget, 2,
2540 : /*5556*/ OPC_EmitInteger, MVT::i32, 127|128,31/*4095*/,
2541 : /*5560*/ OPC_EmitConvertToTarget, 3,
2542 : /*5562*/ OPC_EmitInteger, MVT::i32, 65,
2543 : /*5565*/ OPC_EmitInteger, MVT::i32, 0,
2544 : /*5568*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EG_ExportBuf), 0|OPFL_Chain,
2545 : 0/*#VTs*/, 7/*#Ops*/, 1, 4, 5, 6, 7, 8, 9,
2546 : // Src: (intrinsic_void 4785:iPTR, R600_Reg128:v4f32:$src, (imm:i32):$arraybase, 1:i32, (imm:i32):$mask) - Complexity = 19
2547 : // Dst: (EG_ExportBuf ?:v4f32:$src, 0:i32, (imm:i32):$arraybase, 4095:i32, (imm:i32):$mask, 65:i32, 0:i32)
2548 : /*5581*/ 0, /*End of Scope*/
2549 : /*5582*/ /*Scope*/ 79, /*->5662*/
2550 : /*5583*/ OPC_CheckChild4Integer, 2,
2551 : /*5585*/ OPC_RecordChild5, // #3 = $mask
2552 : /*5586*/ OPC_MoveChild, 5,
2553 : /*5588*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2554 : /*5591*/ OPC_MoveParent,
2555 : /*5592*/ OPC_Scope, 33, /*->5627*/ // 2 children in Scope
2556 : /*5594*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
2557 : /*5596*/ OPC_EmitMergeInputChains1_0,
2558 : /*5597*/ OPC_EmitInteger, MVT::i32, 0,
2559 : /*5600*/ OPC_EmitConvertToTarget, 2,
2560 : /*5602*/ OPC_EmitInteger, MVT::i32, 127|128,31/*4095*/,
2561 : /*5606*/ OPC_EmitConvertToTarget, 3,
2562 : /*5608*/ OPC_EmitInteger, MVT::i32, 34,
2563 : /*5611*/ OPC_EmitInteger, MVT::i32, 0,
2564 : /*5614*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_ExportBuf), 0|OPFL_Chain,
2565 : 0/*#VTs*/, 7/*#Ops*/, 1, 4, 5, 6, 7, 8, 9,
2566 : // Src: (intrinsic_void 4785:iPTR, R600_Reg128:v4f32:$src, (imm:i32):$arraybase, 2:i32, (imm:i32):$mask) - Complexity = 19
2567 : // Dst: (R600_ExportBuf ?:v4f32:$src, 0:i32, (imm:i32):$arraybase, 4095:i32, (imm:i32):$mask, 34:i32, 0:i32)
2568 : /*5627*/ /*Scope*/ 33, /*->5661*/
2569 : /*5628*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
2570 : /*5630*/ OPC_EmitMergeInputChains1_0,
2571 : /*5631*/ OPC_EmitInteger, MVT::i32, 0,
2572 : /*5634*/ OPC_EmitConvertToTarget, 2,
2573 : /*5636*/ OPC_EmitInteger, MVT::i32, 127|128,31/*4095*/,
2574 : /*5640*/ OPC_EmitConvertToTarget, 3,
2575 : /*5642*/ OPC_EmitInteger, MVT::i32, 66,
2576 : /*5645*/ OPC_EmitInteger, MVT::i32, 0,
2577 : /*5648*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EG_ExportBuf), 0|OPFL_Chain,
2578 : 0/*#VTs*/, 7/*#Ops*/, 1, 4, 5, 6, 7, 8, 9,
2579 : // Src: (intrinsic_void 4785:iPTR, R600_Reg128:v4f32:$src, (imm:i32):$arraybase, 2:i32, (imm:i32):$mask) - Complexity = 19
2580 : // Dst: (EG_ExportBuf ?:v4f32:$src, 0:i32, (imm:i32):$arraybase, 4095:i32, (imm:i32):$mask, 66:i32, 0:i32)
2581 : /*5661*/ 0, /*End of Scope*/
2582 : /*5662*/ /*Scope*/ 79, /*->5742*/
2583 : /*5663*/ OPC_CheckChild4Integer, 3,
2584 : /*5665*/ OPC_RecordChild5, // #3 = $mask
2585 : /*5666*/ OPC_MoveChild, 5,
2586 : /*5668*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2587 : /*5671*/ OPC_MoveParent,
2588 : /*5672*/ OPC_Scope, 33, /*->5707*/ // 2 children in Scope
2589 : /*5674*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
2590 : /*5676*/ OPC_EmitMergeInputChains1_0,
2591 : /*5677*/ OPC_EmitInteger, MVT::i32, 0,
2592 : /*5680*/ OPC_EmitConvertToTarget, 2,
2593 : /*5682*/ OPC_EmitInteger, MVT::i32, 127|128,31/*4095*/,
2594 : /*5686*/ OPC_EmitConvertToTarget, 3,
2595 : /*5688*/ OPC_EmitInteger, MVT::i32, 35,
2596 : /*5691*/ OPC_EmitInteger, MVT::i32, 0,
2597 : /*5694*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_ExportBuf), 0|OPFL_Chain,
2598 : 0/*#VTs*/, 7/*#Ops*/, 1, 4, 5, 6, 7, 8, 9,
2599 : // Src: (intrinsic_void 4785:iPTR, R600_Reg128:v4f32:$src, (imm:i32):$arraybase, 3:i32, (imm:i32):$mask) - Complexity = 19
2600 : // Dst: (R600_ExportBuf ?:v4f32:$src, 0:i32, (imm:i32):$arraybase, 4095:i32, (imm:i32):$mask, 35:i32, 0:i32)
2601 : /*5707*/ /*Scope*/ 33, /*->5741*/
2602 : /*5708*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
2603 : /*5710*/ OPC_EmitMergeInputChains1_0,
2604 : /*5711*/ OPC_EmitInteger, MVT::i32, 0,
2605 : /*5714*/ OPC_EmitConvertToTarget, 2,
2606 : /*5716*/ OPC_EmitInteger, MVT::i32, 127|128,31/*4095*/,
2607 : /*5720*/ OPC_EmitConvertToTarget, 3,
2608 : /*5722*/ OPC_EmitInteger, MVT::i32, 67,
2609 : /*5725*/ OPC_EmitInteger, MVT::i32, 0,
2610 : /*5728*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EG_ExportBuf), 0|OPFL_Chain,
2611 : 0/*#VTs*/, 7/*#Ops*/, 1, 4, 5, 6, 7, 8, 9,
2612 : // Src: (intrinsic_void 4785:iPTR, R600_Reg128:v4f32:$src, (imm:i32):$arraybase, 3:i32, (imm:i32):$mask) - Complexity = 19
2613 : // Dst: (EG_ExportBuf ?:v4f32:$src, 0:i32, (imm:i32):$arraybase, 4095:i32, (imm:i32):$mask, 67:i32, 0:i32)
2614 : /*5741*/ 0, /*End of Scope*/
2615 : /*5742*/ 0, /*End of Scope*/
2616 : /*5743*/ /*Scope*/ 90|128,1/*218*/, /*->5963*/
2617 : /*5745*/ OPC_CheckChild1Integer, 46|128,37/*4782*/,
2618 : /*5748*/ OPC_Scope, 104, /*->5854*/ // 2 children in Scope
2619 : /*5750*/ OPC_CheckChild2Integer, 1,
2620 : /*5752*/ OPC_Scope, 49, /*->5803*/ // 2 children in Scope
2621 : /*5754*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
2622 : /*5756*/ OPC_EmitMergeInputChains1_0,
2623 : /*5757*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
2624 : 1/*#VTs*/, MVT::v4f32, 0/*#Ops*/, // Results = #1
2625 : /*5764*/ OPC_EmitInteger, MVT::i32, 1,
2626 : /*5767*/ OPC_EmitInteger, MVT::i32, 60,
2627 : /*5770*/ OPC_EmitInteger, MVT::i32, 7,
2628 : /*5773*/ OPC_EmitInteger, MVT::i32, 7,
2629 : /*5776*/ OPC_EmitInteger, MVT::i32, 7,
2630 : /*5779*/ OPC_EmitInteger, MVT::i32, 7,
2631 : /*5782*/ OPC_EmitInteger, MVT::i32, 39,
2632 : /*5785*/ OPC_EmitInteger, MVT::i32, 0,
2633 : /*5788*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_ExportSwz), 0|OPFL_Chain,
2634 : 0/*#VTs*/, 9/*#Ops*/, 1, 2, 3, 4, 5, 6, 7, 8, 9,
2635 : // Src: (intrinsic_void 4782:iPTR, 1:i32) - Complexity = 13
2636 : // Dst: (R600_ExportSwz (IMPLICIT_DEF:v4f32), 1:i32, 60:i32, 7:i32, 7:i32, 7:i32, 7:i32, 39:i32, 0:i32)
2637 : /*5803*/ /*Scope*/ 49, /*->5853*/
2638 : /*5804*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
2639 : /*5806*/ OPC_EmitMergeInputChains1_0,
2640 : /*5807*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
2641 : 1/*#VTs*/, MVT::v4f32, 0/*#Ops*/, // Results = #1
2642 : /*5814*/ OPC_EmitInteger, MVT::i32, 1,
2643 : /*5817*/ OPC_EmitInteger, MVT::i32, 60,
2644 : /*5820*/ OPC_EmitInteger, MVT::i32, 7,
2645 : /*5823*/ OPC_EmitInteger, MVT::i32, 7,
2646 : /*5826*/ OPC_EmitInteger, MVT::i32, 7,
2647 : /*5829*/ OPC_EmitInteger, MVT::i32, 7,
2648 : /*5832*/ OPC_EmitInteger, MVT::i32, 83,
2649 : /*5835*/ OPC_EmitInteger, MVT::i32, 0,
2650 : /*5838*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EG_ExportSwz), 0|OPFL_Chain,
2651 : 0/*#VTs*/, 9/*#Ops*/, 1, 2, 3, 4, 5, 6, 7, 8, 9,
2652 : // Src: (intrinsic_void 4782:iPTR, 1:i32) - Complexity = 13
2653 : // Dst: (EG_ExportSwz (IMPLICIT_DEF:v4f32), 1:i32, 60:i32, 7:i32, 7:i32, 7:i32, 7:i32, 83:i32, 0:i32)
2654 : /*5853*/ 0, /*End of Scope*/
2655 : /*5854*/ /*Scope*/ 107, /*->5962*/
2656 : /*5855*/ OPC_RecordChild2, // #1 = $type
2657 : /*5856*/ OPC_MoveChild, 2,
2658 : /*5858*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
2659 : /*5861*/ OPC_MoveParent,
2660 : /*5862*/ OPC_Scope, 48, /*->5912*/ // 2 children in Scope
2661 : /*5864*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
2662 : /*5866*/ OPC_EmitMergeInputChains1_0,
2663 : /*5867*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
2664 : 1/*#VTs*/, MVT::v4f32, 0/*#Ops*/, // Results = #2
2665 : /*5874*/ OPC_EmitConvertToTarget, 1,
2666 : /*5876*/ OPC_EmitInteger, MVT::i32, 0,
2667 : /*5879*/ OPC_EmitInteger, MVT::i32, 7,
2668 : /*5882*/ OPC_EmitInteger, MVT::i32, 7,
2669 : /*5885*/ OPC_EmitInteger, MVT::i32, 7,
2670 : /*5888*/ OPC_EmitInteger, MVT::i32, 7,
2671 : /*5891*/ OPC_EmitInteger, MVT::i32, 39,
2672 : /*5894*/ OPC_EmitInteger, MVT::i32, 0,
2673 : /*5897*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_ExportSwz), 0|OPFL_Chain,
2674 : 0/*#VTs*/, 9/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 10,
2675 : // Src: (intrinsic_void 4782:iPTR, (imm:i32):$type) - Complexity = 11
2676 : // Dst: (R600_ExportSwz (IMPLICIT_DEF:v4f32), (imm:i32):$type, 0:i32, 7:i32, 7:i32, 7:i32, 7:i32, 39:i32, 0:i32)
2677 : /*5912*/ /*Scope*/ 48, /*->5961*/
2678 : /*5913*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
2679 : /*5915*/ OPC_EmitMergeInputChains1_0,
2680 : /*5916*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
2681 : 1/*#VTs*/, MVT::v4f32, 0/*#Ops*/, // Results = #2
2682 : /*5923*/ OPC_EmitConvertToTarget, 1,
2683 : /*5925*/ OPC_EmitInteger, MVT::i32, 0,
2684 : /*5928*/ OPC_EmitInteger, MVT::i32, 7,
2685 : /*5931*/ OPC_EmitInteger, MVT::i32, 7,
2686 : /*5934*/ OPC_EmitInteger, MVT::i32, 7,
2687 : /*5937*/ OPC_EmitInteger, MVT::i32, 7,
2688 : /*5940*/ OPC_EmitInteger, MVT::i32, 83,
2689 : /*5943*/ OPC_EmitInteger, MVT::i32, 0,
2690 : /*5946*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EG_ExportSwz), 0|OPFL_Chain,
2691 : 0/*#VTs*/, 9/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 10,
2692 : // Src: (intrinsic_void 4782:iPTR, (imm:i32):$type) - Complexity = 11
2693 : // Dst: (EG_ExportSwz (IMPLICIT_DEF:v4f32), (imm:i32):$type, 0:i32, 7:i32, 7:i32, 7:i32, 7:i32, 83:i32, 0:i32)
2694 : /*5961*/ 0, /*End of Scope*/
2695 : /*5962*/ 0, /*End of Scope*/
2696 : /*5963*/ /*Scope*/ 25, /*->5989*/
2697 : /*5964*/ OPC_CheckChild1Integer, 112|128,36/*4720*/,
2698 : /*5967*/ OPC_Scope, 9, /*->5978*/ // 2 children in Scope
2699 : /*5969*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
2700 : /*5971*/ OPC_EmitMergeInputChains1_0,
2701 : /*5972*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::GROUP_BARRIER), 0|OPFL_Chain,
2702 : 0/*#VTs*/, 0/*#Ops*/,
2703 : // Src: (intrinsic_void 4720:iPTR) - Complexity = 8
2704 : // Dst: (GROUP_BARRIER)
2705 : /*5978*/ /*Scope*/ 9, /*->5988*/
2706 : /*5979*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
2707 : /*5981*/ OPC_EmitMergeInputChains1_0,
2708 : /*5982*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BARRIER), 0|OPFL_Chain,
2709 : 0/*#VTs*/, 0/*#Ops*/,
2710 : // Src: (intrinsic_void 4720:iPTR) - Complexity = 8
2711 : // Dst: (S_BARRIER)
2712 : /*5988*/ 0, /*End of Scope*/
2713 : /*5989*/ /*Scope*/ 25, /*->6015*/
2714 : /*5990*/ OPC_CheckChild1Integer, 111|128,36/*4719*/,
2715 : /*5993*/ OPC_Scope, 9, /*->6004*/ // 2 children in Scope
2716 : /*5995*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
2717 : /*5997*/ OPC_EmitMergeInputChains1_0,
2718 : /*5998*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::GROUP_BARRIER), 0|OPFL_Chain,
2719 : 0/*#VTs*/, 0/*#Ops*/,
2720 : // Src: (intrinsic_void 4719:iPTR) - Complexity = 8
2721 : // Dst: (GROUP_BARRIER)
2722 : /*6004*/ /*Scope*/ 9, /*->6014*/
2723 : /*6005*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
2724 : /*6007*/ OPC_EmitMergeInputChains1_0,
2725 : /*6008*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BARRIER), 0|OPFL_Chain,
2726 : 0/*#VTs*/, 0/*#Ops*/,
2727 : // Src: (intrinsic_void 4719:iPTR) - Complexity = 8
2728 : // Dst: (S_BARRIER)
2729 : /*6014*/ 0, /*End of Scope*/
2730 : /*6015*/ /*Scope*/ 22, /*->6038*/
2731 : /*6016*/ OPC_CheckChild1Integer, 11|128,38/*4875*/,
2732 : /*6019*/ OPC_RecordChild2, // #1 = $saved
2733 : /*6020*/ OPC_RecordChild3, // #2 = $target
2734 : /*6021*/ OPC_MoveChild, 3,
2735 : /*6023*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
2736 : /*6026*/ OPC_MoveParent,
2737 : /*6027*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
2738 : /*6029*/ OPC_EmitMergeInputChains1_0,
2739 : /*6030*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_LOOP), 0|OPFL_Chain,
2740 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
2741 : // Src: (intrinsic_void 4875:iPTR, i64:i64:$saved, (bb:Other):$target) - Complexity = 8
2742 : // Dst: (SI_LOOP i64:i64:$saved, (bb:Other):$target)
2743 : /*6038*/ /*Scope*/ 14, /*->6053*/
2744 : /*6039*/ OPC_CheckChild1Integer, 63|128,37/*4799*/,
2745 : /*6042*/ OPC_RecordChild2, // #1 = $saved
2746 : /*6043*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
2747 : /*6045*/ OPC_EmitMergeInputChains1_0,
2748 : /*6046*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_END_CF), 0|OPFL_Chain,
2749 : 0/*#VTs*/, 1/*#Ops*/, 1,
2750 : // Src: (intrinsic_void 4799:iPTR, i64:i64:$saved) - Complexity = 8
2751 : // Dst: (SI_END_CF i64:i64:$saved)
2752 : /*6053*/ /*Scope*/ 2|128,1/*130*/, /*->6185*/
2753 : /*6055*/ OPC_CheckChild1Integer, 7|128,37/*4743*/,
2754 : /*6058*/ OPC_RecordChild2, // #1 = $src
2755 : /*6059*/ OPC_Scope, 10, /*->6071*/ // 2 children in Scope
2756 : /*6061*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
2757 : /*6063*/ OPC_EmitMergeInputChains1_0,
2758 : /*6064*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_KILL), 0|OPFL_Chain,
2759 : 0/*#VTs*/, 1/*#Ops*/, 1,
2760 : // Src: (intrinsic_void 4743:iPTR, f32:f32:$src) - Complexity = 8
2761 : // Dst: (SI_KILL f32:f32:$src)
2762 : /*6071*/ /*Scope*/ 112, /*->6184*/
2763 : /*6072*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
2764 : /*6074*/ OPC_EmitMergeInputChains1_0,
2765 : /*6075*/ OPC_EmitInteger, MVT::i32, 0,
2766 : /*6078*/ OPC_EmitInteger, MVT::i32, 0,
2767 : /*6081*/ OPC_EmitInteger, MVT::i32, 1,
2768 : /*6084*/ OPC_EmitInteger, MVT::i32, 0,
2769 : /*6087*/ OPC_EmitInteger, MVT::i32, 0,
2770 : /*6090*/ OPC_EmitInteger, MVT::i32, 0,
2771 : /*6093*/ OPC_EmitRegister, MVT::f32, AMDGPU::ZERO,
2772 : /*6096*/ OPC_EmitInteger, MVT::i32, 0,
2773 : /*6099*/ OPC_EmitInteger, MVT::i32, 0,
2774 : /*6102*/ OPC_EmitInteger, MVT::i32, 0,
2775 : /*6105*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
2776 : /*6117*/ OPC_EmitInteger, MVT::i32, 0,
2777 : /*6120*/ OPC_EmitInteger, MVT::i32, 0,
2778 : /*6123*/ OPC_EmitInteger, MVT::i32, 0,
2779 : /*6126*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
2780 : /*6138*/ OPC_EmitInteger, MVT::i32, 1,
2781 : /*6141*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
2782 : /*6144*/ OPC_EmitInteger, MVT::i32, 0,
2783 : /*6147*/ OPC_EmitInteger, MVT::i32, 0,
2784 : /*6150*/ OPC_EmitNode, TARGET_VAL(AMDGPU::KILLGT), 0|OPFL_Chain,
2785 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1, 13, 14, 15, 16, 17, 18, 19, 20, // Results = #21
2786 : /*6177*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MASK_WRITE), 0|OPFL_Chain,
2787 : 0/*#VTs*/, 1/*#Ops*/, 21,
2788 : // Src: (intrinsic_void 4743:iPTR, f32:f32:$src0) - Complexity = 8
2789 : // Dst: (MASK_WRITE (KILLGT:i32 ZERO:f32, ?:f32:$src0))
2790 : /*6184*/ 0, /*End of Scope*/
2791 : /*6185*/ /*Scope*/ 11|128,1/*139*/, /*->6326*/
2792 : /*6187*/ OPC_CheckChild1Integer, 8|128,37/*4744*/,
2793 : /*6190*/ OPC_Scope, 17, /*->6209*/ // 2 children in Scope
2794 : /*6192*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
2795 : /*6194*/ OPC_EmitMergeInputChains1_0,
2796 : /*6195*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,0|128,124|128,11/*3212836864*/,
2797 : /*6202*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_KILL), 0|OPFL_Chain,
2798 : 0/*#VTs*/, 1/*#Ops*/, 1,
2799 : // Src: (intrinsic_void 4744:iPTR) - Complexity = 8
2800 : // Dst: (SI_KILL 3212836864:i32)
2801 : /*6209*/ /*Scope*/ 115, /*->6325*/
2802 : /*6210*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
2803 : /*6212*/ OPC_EmitMergeInputChains1_0,
2804 : /*6213*/ OPC_EmitInteger, MVT::i32, 0,
2805 : /*6216*/ OPC_EmitInteger, MVT::i32, 0,
2806 : /*6219*/ OPC_EmitInteger, MVT::i32, 1,
2807 : /*6222*/ OPC_EmitInteger, MVT::i32, 0,
2808 : /*6225*/ OPC_EmitInteger, MVT::i32, 0,
2809 : /*6228*/ OPC_EmitInteger, MVT::i32, 0,
2810 : /*6231*/ OPC_EmitRegister, MVT::f32, AMDGPU::ONE,
2811 : /*6234*/ OPC_EmitInteger, MVT::i32, 0,
2812 : /*6237*/ OPC_EmitInteger, MVT::i32, 0,
2813 : /*6240*/ OPC_EmitInteger, MVT::i32, 0,
2814 : /*6243*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
2815 : /*6255*/ OPC_EmitRegister, MVT::f32, AMDGPU::ZERO,
2816 : /*6258*/ OPC_EmitInteger, MVT::i32, 0,
2817 : /*6261*/ OPC_EmitInteger, MVT::i32, 0,
2818 : /*6264*/ OPC_EmitInteger, MVT::i32, 0,
2819 : /*6267*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
2820 : /*6279*/ OPC_EmitInteger, MVT::i32, 1,
2821 : /*6282*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
2822 : /*6285*/ OPC_EmitInteger, MVT::i32, 0,
2823 : /*6288*/ OPC_EmitInteger, MVT::i32, 0,
2824 : /*6291*/ OPC_EmitNode, TARGET_VAL(AMDGPU::KILLGT), 0|OPFL_Chain,
2825 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, // Results = #21
2826 : /*6318*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MASK_WRITE), 0|OPFL_Chain,
2827 : 0/*#VTs*/, 1/*#Ops*/, 21,
2828 : // Src: (intrinsic_void 4744:iPTR) - Complexity = 8
2829 : // Dst: (MASK_WRITE (KILLGT:i32 ONE:f32, ZERO:f32))
2830 : /*6325*/ 0, /*End of Scope*/
2831 : /*6326*/ /*Scope*/ 4|128,1/*132*/, /*->6460*/
2832 : /*6328*/ OPC_CheckChild1Integer, 47|128,37/*4783*/,
2833 : /*6331*/ OPC_RecordChild2, // #1 = $reg
2834 : /*6332*/ OPC_Scope, 62, /*->6396*/ // 2 children in Scope
2835 : /*6334*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
2836 : /*6336*/ OPC_EmitMergeInputChains1_0,
2837 : /*6337*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
2838 : 1/*#VTs*/, MVT::v4f32, 0/*#Ops*/, // Results = #2
2839 : /*6344*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
2840 : /*6347*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
2841 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 2, 1, 3, // Results = #4
2842 : /*6357*/ OPC_EmitInteger, MVT::i32, 0,
2843 : /*6360*/ OPC_EmitInteger, MVT::i32, 61,
2844 : /*6363*/ OPC_EmitInteger, MVT::i32, 0,
2845 : /*6366*/ OPC_EmitInteger, MVT::i32, 7,
2846 : /*6369*/ OPC_EmitInteger, MVT::i32, 7,
2847 : /*6372*/ OPC_EmitInteger, MVT::i32, 7,
2848 : /*6375*/ OPC_EmitInteger, MVT::i32, 39,
2849 : /*6378*/ OPC_EmitInteger, MVT::i32, 0,
2850 : /*6381*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_ExportSwz), 0|OPFL_Chain,
2851 : 0/*#VTs*/, 9/*#Ops*/, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2852 : // Src: (intrinsic_void 4783:iPTR, R600_Reg32:f32:$reg) - Complexity = 8
2853 : // Dst: (R600_ExportSwz (INSERT_SUBREG:v4f32 (IMPLICIT_DEF:v4f32), ?:f32:$reg, sub0:i32), 0:i32, 61:i32, 0:i32, 7:i32, 7:i32, 7:i32, 39:i32, 0:i32)
2854 : /*6396*/ /*Scope*/ 62, /*->6459*/
2855 : /*6397*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
2856 : /*6399*/ OPC_EmitMergeInputChains1_0,
2857 : /*6400*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
2858 : 1/*#VTs*/, MVT::v4f32, 0/*#Ops*/, // Results = #2
2859 : /*6407*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
2860 : /*6410*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
2861 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 2, 1, 3, // Results = #4
2862 : /*6420*/ OPC_EmitInteger, MVT::i32, 0,
2863 : /*6423*/ OPC_EmitInteger, MVT::i32, 61,
2864 : /*6426*/ OPC_EmitInteger, MVT::i32, 0,
2865 : /*6429*/ OPC_EmitInteger, MVT::i32, 7,
2866 : /*6432*/ OPC_EmitInteger, MVT::i32, 7,
2867 : /*6435*/ OPC_EmitInteger, MVT::i32, 7,
2868 : /*6438*/ OPC_EmitInteger, MVT::i32, 83,
2869 : /*6441*/ OPC_EmitInteger, MVT::i32, 0,
2870 : /*6444*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EG_ExportSwz), 0|OPFL_Chain,
2871 : 0/*#VTs*/, 9/*#Ops*/, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2872 : // Src: (intrinsic_void 4783:iPTR, R600_Reg32:f32:$reg) - Complexity = 8
2873 : // Dst: (EG_ExportSwz (INSERT_SUBREG:v4f32 (IMPLICIT_DEF:v4f32), ?:f32:$reg, sub0:i32), 0:i32, 61:i32, 0:i32, 7:i32, 7:i32, 7:i32, 83:i32, 0:i32)
2874 : /*6459*/ 0, /*End of Scope*/
2875 : /*6460*/ /*Scope*/ 4|128,1/*132*/, /*->6594*/
2876 : /*6462*/ OPC_CheckChild1Integer, 48|128,37/*4784*/,
2877 : /*6465*/ OPC_RecordChild2, // #1 = $reg
2878 : /*6466*/ OPC_Scope, 62, /*->6530*/ // 2 children in Scope
2879 : /*6468*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
2880 : /*6470*/ OPC_EmitMergeInputChains1_0,
2881 : /*6471*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
2882 : 1/*#VTs*/, MVT::v4f32, 0/*#Ops*/, // Results = #2
2883 : /*6478*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
2884 : /*6481*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
2885 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 2, 1, 3, // Results = #4
2886 : /*6491*/ OPC_EmitInteger, MVT::i32, 0,
2887 : /*6494*/ OPC_EmitInteger, MVT::i32, 61,
2888 : /*6497*/ OPC_EmitInteger, MVT::i32, 7,
2889 : /*6500*/ OPC_EmitInteger, MVT::i32, 0,
2890 : /*6503*/ OPC_EmitInteger, MVT::i32, 7,
2891 : /*6506*/ OPC_EmitInteger, MVT::i32, 7,
2892 : /*6509*/ OPC_EmitInteger, MVT::i32, 39,
2893 : /*6512*/ OPC_EmitInteger, MVT::i32, 0,
2894 : /*6515*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_ExportSwz), 0|OPFL_Chain,
2895 : 0/*#VTs*/, 9/*#Ops*/, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2896 : // Src: (intrinsic_void 4784:iPTR, R600_Reg32:f32:$reg) - Complexity = 8
2897 : // Dst: (R600_ExportSwz (INSERT_SUBREG:v4f32 (IMPLICIT_DEF:v4f32), ?:f32:$reg, sub0:i32), 0:i32, 61:i32, 7:i32, 0:i32, 7:i32, 7:i32, 39:i32, 0:i32)
2898 : /*6530*/ /*Scope*/ 62, /*->6593*/
2899 : /*6531*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
2900 : /*6533*/ OPC_EmitMergeInputChains1_0,
2901 : /*6534*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
2902 : 1/*#VTs*/, MVT::v4f32, 0/*#Ops*/, // Results = #2
2903 : /*6541*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
2904 : /*6544*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
2905 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 2, 1, 3, // Results = #4
2906 : /*6554*/ OPC_EmitInteger, MVT::i32, 0,
2907 : /*6557*/ OPC_EmitInteger, MVT::i32, 61,
2908 : /*6560*/ OPC_EmitInteger, MVT::i32, 7,
2909 : /*6563*/ OPC_EmitInteger, MVT::i32, 0,
2910 : /*6566*/ OPC_EmitInteger, MVT::i32, 7,
2911 : /*6569*/ OPC_EmitInteger, MVT::i32, 7,
2912 : /*6572*/ OPC_EmitInteger, MVT::i32, 83,
2913 : /*6575*/ OPC_EmitInteger, MVT::i32, 0,
2914 : /*6578*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EG_ExportSwz), 0|OPFL_Chain,
2915 : 0/*#VTs*/, 9/*#Ops*/, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2916 : // Src: (intrinsic_void 4784:iPTR, R600_Reg32:f32:$reg) - Complexity = 8
2917 : // Dst: (EG_ExportSwz (INSERT_SUBREG:v4f32 (IMPLICIT_DEF:v4f32), ?:f32:$reg, sub0:i32), 0:i32, 61:i32, 7:i32, 0:i32, 7:i32, 7:i32, 83:i32, 0:i32)
2918 : /*6593*/ 0, /*End of Scope*/
2919 : /*6594*/ 0, /*End of Scope*/
2920 : /*6595*/ /*SwitchOpcode*/ 47|128,1/*175*/, TARGET_VAL(ISD::ATOMIC_SWAP),// ->6774
2921 : /*6599*/ OPC_RecordMemRef,
2922 : /*6600*/ OPC_RecordNode, // #0 = 'atomic_swap' chained node
2923 : /*6601*/ OPC_Scope, 45, /*->6648*/ // 3 children in Scope
2924 : /*6603*/ OPC_RecordChild1, // #1 = $MUBUFAddr64Atomic:srsrc:vaddr:soffset:offset:slc
2925 : /*6604*/ OPC_RecordChild2, // #2 = $vdata_in
2926 : /*6605*/ OPC_CheckPredicate, 73, // Predicate_atomic_swap_global
2927 : /*6607*/ OPC_CheckType, MVT::i32,
2928 : /*6609*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
2929 : /*6611*/ OPC_Scope, 17, /*->6630*/ // 2 children in Scope
2930 : /*6613*/ OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7
2931 : /*6616*/ OPC_EmitMergeInputChains1_0,
2932 : /*6617*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SWAP_RTN_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
2933 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
2934 : // Src: (atomic_swap:i32 (MUBUFAddr64Atomic:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_swap_global>> - Complexity = 22
2935 : // Dst: (BUFFER_ATOMIC_SWAP_RTN_ADDR64:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
2936 : /*6630*/ /*Scope*/ 16, /*->6647*/
2937 : /*6631*/ OPC_CheckComplexPat, /*CP*/7, /*#*/1, // SelectMUBUFOffset:$ #3 #4 #5 #6
2938 : /*6634*/ OPC_EmitMergeInputChains1_0,
2939 : /*6635*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SWAP_RTN_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
2940 : 1/*#VTs*/, MVT::i32, 5/*#Ops*/, 2, 3, 4, 5, 6,
2941 : // Src: (atomic_swap:i32 (MUBUFOffsetAtomic:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_swap_global>> - Complexity = 19
2942 : // Dst: (BUFFER_ATOMIC_SWAP_RTN_OFFSET:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
2943 : /*6647*/ 0, /*End of Scope*/
2944 : /*6648*/ /*Scope*/ 57, /*->6706*/
2945 : /*6649*/ OPC_CaptureGlueInput,
2946 : /*6650*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
2947 : /*6651*/ OPC_RecordChild2, // #2 = $value
2948 : /*6652*/ OPC_CheckPredicate, 74, // Predicate_si_atomic_swap_local
2949 : /*6654*/ OPC_SwitchType /*2 cases */, 23, MVT::i32,// ->6680
2950 : /*6657*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
2951 : /*6659*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
2952 : /*6662*/ OPC_EmitMergeInputChains1_0,
2953 : /*6663*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
2954 : /*6666*/ OPC_EmitInteger, MVT::i1, 0,
2955 : /*6669*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_WRXCHG_RTN_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
2956 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 3, 2, 5, 6,
2957 : // Src: (si_atomic_swap_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i32:i32:$value)<<P:Predicate_si_atomic_swap_local>> - Complexity = 13
2958 : // Dst: (DS_WRXCHG_RTN_B32:i32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
2959 : /*6680*/ /*SwitchType*/ 23, MVT::i64,// ->6705
2960 : /*6682*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
2961 : /*6684*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
2962 : /*6687*/ OPC_EmitMergeInputChains1_0,
2963 : /*6688*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
2964 : /*6691*/ OPC_EmitInteger, MVT::i1, 0,
2965 : /*6694*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_WRXCHG_RTN_B64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
2966 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 3, 2, 5, 6,
2967 : // Src: (si_atomic_swap_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i64:i64:$value)<<P:Predicate_si_atomic_swap_local>> - Complexity = 13
2968 : // Dst: (DS_WRXCHG_RTN_B64:i64 ?:i32:$ptr, ?:i64:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
2969 : /*6705*/ 0, // EndSwitchType
2970 : /*6706*/ /*Scope*/ 66, /*->6773*/
2971 : /*6707*/ OPC_RecordChild1, // #1 = $src0
2972 : /*6708*/ OPC_CheckChild1Type, MVT::i32,
2973 : /*6710*/ OPC_RecordChild2, // #2 = $src1
2974 : /*6711*/ OPC_CheckPredicate, 75, // Predicate_atomic_swap_local
2975 : /*6713*/ OPC_CheckType, MVT::i32,
2976 : /*6715*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
2977 : /*6717*/ OPC_EmitMergeInputChains1_0,
2978 : /*6718*/ OPC_EmitInteger, MVT::i32, 0,
2979 : /*6721*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
2980 : /*6733*/ OPC_EmitInteger, MVT::i32, 0,
2981 : /*6736*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
2982 : /*6748*/ OPC_EmitInteger, MVT::i32, 1,
2983 : /*6751*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
2984 : /*6754*/ OPC_EmitInteger, MVT::i32, 0,
2985 : /*6757*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_WRXCHG_RET), 0|OPFL_Chain|OPFL_MemRefs,
2986 : 1/*#VTs*/, MVT::i32, 9/*#Ops*/, 1, 3, 4, 2, 5, 6, 7, 8, 9,
2987 : // Src: (atomic_swap:i32 i32:i32:$src0, i32:i32:$src1)<<P:Predicate_atomic_swap_local>> - Complexity = 4
2988 : // Dst: (LDS_WRXCHG_RET:i32 i32:i32:$src0, i32:i32:$src1)
2989 : /*6773*/ 0, /*End of Scope*/
2990 : /*6774*/ /*SwitchOpcode*/ 20|128,2/*276*/, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->7054
2991 : /*6778*/ OPC_RecordMemRef,
2992 : /*6779*/ OPC_RecordNode, // #0 = 'atomic_load_add' chained node
2993 : /*6780*/ OPC_Scope, 45, /*->6827*/ // 3 children in Scope
2994 : /*6782*/ OPC_RecordChild1, // #1 = $MUBUFAddr64Atomic:srsrc:vaddr:soffset:offset:slc
2995 : /*6783*/ OPC_RecordChild2, // #2 = $vdata_in
2996 : /*6784*/ OPC_CheckPredicate, 76, // Predicate_atomic_add_global
2997 : /*6786*/ OPC_CheckType, MVT::i32,
2998 : /*6788*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
2999 : /*6790*/ OPC_Scope, 17, /*->6809*/ // 2 children in Scope
3000 : /*6792*/ OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7
3001 : /*6795*/ OPC_EmitMergeInputChains1_0,
3002 : /*6796*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_ADD_RTN_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
3003 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
3004 : // Src: (atomic_load_add:i32 (MUBUFAddr64Atomic:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_add_global>> - Complexity = 22
3005 : // Dst: (BUFFER_ATOMIC_ADD_RTN_ADDR64:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3006 : /*6809*/ /*Scope*/ 16, /*->6826*/
3007 : /*6810*/ OPC_CheckComplexPat, /*CP*/7, /*#*/1, // SelectMUBUFOffset:$ #3 #4 #5 #6
3008 : /*6813*/ OPC_EmitMergeInputChains1_0,
3009 : /*6814*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_ADD_RTN_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
3010 : 1/*#VTs*/, MVT::i32, 5/*#Ops*/, 2, 3, 4, 5, 6,
3011 : // Src: (atomic_load_add:i32 (MUBUFOffsetAtomic:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_add_global>> - Complexity = 19
3012 : // Dst: (BUFFER_ATOMIC_ADD_RTN_OFFSET:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3013 : /*6826*/ 0, /*End of Scope*/
3014 : /*6827*/ /*Scope*/ 29|128,1/*157*/, /*->6986*/
3015 : /*6829*/ OPC_CaptureGlueInput,
3016 : /*6830*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
3017 : /*6831*/ OPC_Scope, 96, /*->6929*/ // 2 children in Scope
3018 : /*6833*/ OPC_CheckChild2Integer, 1,
3019 : /*6835*/ OPC_CheckPredicate, 77, // Predicate_si_atomic_load_add_local
3020 : /*6837*/ OPC_SwitchType /*2 cases */, 43, MVT::i32,// ->6883
3021 : /*6840*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3022 : /*6842*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
3023 : /*6845*/ OPC_EmitMergeInputChains1_0,
3024 : /*6846*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3025 : /*6858*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
3026 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 4, // Results = #5
3027 : /*6866*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
3028 : /*6869*/ OPC_EmitInteger, MVT::i1, 0,
3029 : /*6872*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_INC_RTN_U32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3030 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 2, 5, 6, 7,
3031 : // Src: (si_atomic_load_add_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), 1:i32)<<P:Predicate_si_atomic_load_add_local>> - Complexity = 18
3032 : // Dst: (DS_INC_RTN_U32:i32 ?:i32:$ptr, (S_MOV_B32:i32 -1:i32), (as_i16imm:i16 ?:i32:$offset), 0:i1)
3033 : /*6883*/ /*SwitchType*/ 43, MVT::i64,// ->6928
3034 : /*6885*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3035 : /*6887*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
3036 : /*6890*/ OPC_EmitMergeInputChains1_0,
3037 : /*6891*/ OPC_EmitInteger, MVT::i64, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3038 : /*6903*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B64), 0,
3039 : 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 4, // Results = #5
3040 : /*6911*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
3041 : /*6914*/ OPC_EmitInteger, MVT::i1, 0,
3042 : /*6917*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_INC_RTN_U64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3043 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 2, 5, 6, 7,
3044 : // Src: (si_atomic_load_add_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), 1:i64)<<P:Predicate_si_atomic_load_add_local>> - Complexity = 18
3045 : // Dst: (DS_INC_RTN_U64:i64 ?:i32:$ptr, (S_MOV_B64:i64 -1:i64), (as_i16imm:i16 ?:i32:$offset), 0:i1)
3046 : /*6928*/ 0, // EndSwitchType
3047 : /*6929*/ /*Scope*/ 55, /*->6985*/
3048 : /*6930*/ OPC_RecordChild2, // #2 = $value
3049 : /*6931*/ OPC_CheckPredicate, 77, // Predicate_si_atomic_load_add_local
3050 : /*6933*/ OPC_SwitchType /*2 cases */, 23, MVT::i32,// ->6959
3051 : /*6936*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3052 : /*6938*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3053 : /*6941*/ OPC_EmitMergeInputChains1_0,
3054 : /*6942*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3055 : /*6945*/ OPC_EmitInteger, MVT::i1, 0,
3056 : /*6948*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_ADD_RTN_U32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3057 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 3, 2, 5, 6,
3058 : // Src: (si_atomic_load_add_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i32:i32:$value)<<P:Predicate_si_atomic_load_add_local>> - Complexity = 13
3059 : // Dst: (DS_ADD_RTN_U32:i32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3060 : /*6959*/ /*SwitchType*/ 23, MVT::i64,// ->6984
3061 : /*6961*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3062 : /*6963*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3063 : /*6966*/ OPC_EmitMergeInputChains1_0,
3064 : /*6967*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3065 : /*6970*/ OPC_EmitInteger, MVT::i1, 0,
3066 : /*6973*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_ADD_RTN_U64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3067 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 3, 2, 5, 6,
3068 : // Src: (si_atomic_load_add_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i64:i64:$value)<<P:Predicate_si_atomic_load_add_local>> - Complexity = 13
3069 : // Dst: (DS_ADD_RTN_U64:i64 ?:i32:$ptr, ?:i64:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3070 : /*6984*/ 0, // EndSwitchType
3071 : /*6985*/ 0, /*End of Scope*/
3072 : /*6986*/ /*Scope*/ 66, /*->7053*/
3073 : /*6987*/ OPC_RecordChild1, // #1 = $src0
3074 : /*6988*/ OPC_CheckChild1Type, MVT::i32,
3075 : /*6990*/ OPC_RecordChild2, // #2 = $src1
3076 : /*6991*/ OPC_CheckPredicate, 78, // Predicate_atomic_load_add_local
3077 : /*6993*/ OPC_CheckType, MVT::i32,
3078 : /*6995*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3079 : /*6997*/ OPC_EmitMergeInputChains1_0,
3080 : /*6998*/ OPC_EmitInteger, MVT::i32, 0,
3081 : /*7001*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3082 : /*7013*/ OPC_EmitInteger, MVT::i32, 0,
3083 : /*7016*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3084 : /*7028*/ OPC_EmitInteger, MVT::i32, 1,
3085 : /*7031*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3086 : /*7034*/ OPC_EmitInteger, MVT::i32, 0,
3087 : /*7037*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_ADD_RET), 0|OPFL_Chain|OPFL_MemRefs,
3088 : 1/*#VTs*/, MVT::i32, 9/*#Ops*/, 1, 3, 4, 2, 5, 6, 7, 8, 9,
3089 : // Src: (atomic_load_add:i32 i32:i32:$src0, i32:i32:$src1)<<P:Predicate_atomic_load_add_local>> - Complexity = 4
3090 : // Dst: (LDS_ADD_RET:i32 i32:i32:$src0, i32:i32:$src1)
3091 : /*7053*/ 0, /*End of Scope*/
3092 : /*7054*/ /*SwitchOpcode*/ 20|128,2/*276*/, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->7334
3093 : /*7058*/ OPC_RecordMemRef,
3094 : /*7059*/ OPC_RecordNode, // #0 = 'atomic_load_sub' chained node
3095 : /*7060*/ OPC_Scope, 45, /*->7107*/ // 3 children in Scope
3096 : /*7062*/ OPC_RecordChild1, // #1 = $MUBUFAddr64Atomic:srsrc:vaddr:soffset:offset:slc
3097 : /*7063*/ OPC_RecordChild2, // #2 = $vdata_in
3098 : /*7064*/ OPC_CheckPredicate, 79, // Predicate_atomic_sub_global
3099 : /*7066*/ OPC_CheckType, MVT::i32,
3100 : /*7068*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
3101 : /*7070*/ OPC_Scope, 17, /*->7089*/ // 2 children in Scope
3102 : /*7072*/ OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7
3103 : /*7075*/ OPC_EmitMergeInputChains1_0,
3104 : /*7076*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SUB_RTN_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
3105 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
3106 : // Src: (atomic_load_sub:i32 (MUBUFAddr64Atomic:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_sub_global>> - Complexity = 22
3107 : // Dst: (BUFFER_ATOMIC_SUB_RTN_ADDR64:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3108 : /*7089*/ /*Scope*/ 16, /*->7106*/
3109 : /*7090*/ OPC_CheckComplexPat, /*CP*/7, /*#*/1, // SelectMUBUFOffset:$ #3 #4 #5 #6
3110 : /*7093*/ OPC_EmitMergeInputChains1_0,
3111 : /*7094*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SUB_RTN_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
3112 : 1/*#VTs*/, MVT::i32, 5/*#Ops*/, 2, 3, 4, 5, 6,
3113 : // Src: (atomic_load_sub:i32 (MUBUFOffsetAtomic:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_sub_global>> - Complexity = 19
3114 : // Dst: (BUFFER_ATOMIC_SUB_RTN_OFFSET:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3115 : /*7106*/ 0, /*End of Scope*/
3116 : /*7107*/ /*Scope*/ 29|128,1/*157*/, /*->7266*/
3117 : /*7109*/ OPC_CaptureGlueInput,
3118 : /*7110*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
3119 : /*7111*/ OPC_Scope, 96, /*->7209*/ // 2 children in Scope
3120 : /*7113*/ OPC_CheckChild2Integer, 1,
3121 : /*7115*/ OPC_CheckPredicate, 80, // Predicate_si_atomic_load_sub_local
3122 : /*7117*/ OPC_SwitchType /*2 cases */, 43, MVT::i32,// ->7163
3123 : /*7120*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3124 : /*7122*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
3125 : /*7125*/ OPC_EmitMergeInputChains1_0,
3126 : /*7126*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3127 : /*7138*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
3128 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 4, // Results = #5
3129 : /*7146*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
3130 : /*7149*/ OPC_EmitInteger, MVT::i1, 0,
3131 : /*7152*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_DEC_RTN_U32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3132 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 2, 5, 6, 7,
3133 : // Src: (si_atomic_load_sub_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), 1:i32)<<P:Predicate_si_atomic_load_sub_local>> - Complexity = 18
3134 : // Dst: (DS_DEC_RTN_U32:i32 ?:i32:$ptr, (S_MOV_B32:i32 -1:i32), (as_i16imm:i16 ?:i32:$offset), 0:i1)
3135 : /*7163*/ /*SwitchType*/ 43, MVT::i64,// ->7208
3136 : /*7165*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3137 : /*7167*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #2 #3
3138 : /*7170*/ OPC_EmitMergeInputChains1_0,
3139 : /*7171*/ OPC_EmitInteger, MVT::i64, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3140 : /*7183*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B64), 0,
3141 : 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 4, // Results = #5
3142 : /*7191*/ OPC_EmitNodeXForm, 0, 3, // as_i16imm
3143 : /*7194*/ OPC_EmitInteger, MVT::i1, 0,
3144 : /*7197*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_DEC_RTN_U64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3145 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 2, 5, 6, 7,
3146 : // Src: (si_atomic_load_sub_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), 1:i64)<<P:Predicate_si_atomic_load_sub_local>> - Complexity = 18
3147 : // Dst: (DS_DEC_RTN_U64:i64 ?:i32:$ptr, (S_MOV_B64:i64 -1:i64), (as_i16imm:i16 ?:i32:$offset), 0:i1)
3148 : /*7208*/ 0, // EndSwitchType
3149 : /*7209*/ /*Scope*/ 55, /*->7265*/
3150 : /*7210*/ OPC_RecordChild2, // #2 = $value
3151 : /*7211*/ OPC_CheckPredicate, 80, // Predicate_si_atomic_load_sub_local
3152 : /*7213*/ OPC_SwitchType /*2 cases */, 23, MVT::i32,// ->7239
3153 : /*7216*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3154 : /*7218*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3155 : /*7221*/ OPC_EmitMergeInputChains1_0,
3156 : /*7222*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3157 : /*7225*/ OPC_EmitInteger, MVT::i1, 0,
3158 : /*7228*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_SUB_RTN_U32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3159 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 3, 2, 5, 6,
3160 : // Src: (si_atomic_load_sub_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i32:i32:$value)<<P:Predicate_si_atomic_load_sub_local>> - Complexity = 13
3161 : // Dst: (DS_SUB_RTN_U32:i32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3162 : /*7239*/ /*SwitchType*/ 23, MVT::i64,// ->7264
3163 : /*7241*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3164 : /*7243*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3165 : /*7246*/ OPC_EmitMergeInputChains1_0,
3166 : /*7247*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3167 : /*7250*/ OPC_EmitInteger, MVT::i1, 0,
3168 : /*7253*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_SUB_RTN_U64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3169 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 3, 2, 5, 6,
3170 : // Src: (si_atomic_load_sub_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i64:i64:$value)<<P:Predicate_si_atomic_load_sub_local>> - Complexity = 13
3171 : // Dst: (DS_SUB_RTN_U64:i64 ?:i32:$ptr, ?:i64:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3172 : /*7264*/ 0, // EndSwitchType
3173 : /*7265*/ 0, /*End of Scope*/
3174 : /*7266*/ /*Scope*/ 66, /*->7333*/
3175 : /*7267*/ OPC_RecordChild1, // #1 = $src0
3176 : /*7268*/ OPC_CheckChild1Type, MVT::i32,
3177 : /*7270*/ OPC_RecordChild2, // #2 = $src1
3178 : /*7271*/ OPC_CheckPredicate, 81, // Predicate_atomic_load_sub_local
3179 : /*7273*/ OPC_CheckType, MVT::i32,
3180 : /*7275*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3181 : /*7277*/ OPC_EmitMergeInputChains1_0,
3182 : /*7278*/ OPC_EmitInteger, MVT::i32, 0,
3183 : /*7281*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3184 : /*7293*/ OPC_EmitInteger, MVT::i32, 0,
3185 : /*7296*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3186 : /*7308*/ OPC_EmitInteger, MVT::i32, 1,
3187 : /*7311*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3188 : /*7314*/ OPC_EmitInteger, MVT::i32, 0,
3189 : /*7317*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_SUB_RET), 0|OPFL_Chain|OPFL_MemRefs,
3190 : 1/*#VTs*/, MVT::i32, 9/*#Ops*/, 1, 3, 4, 2, 5, 6, 7, 8, 9,
3191 : // Src: (atomic_load_sub:i32 i32:i32:$src0, i32:i32:$src1)<<P:Predicate_atomic_load_sub_local>> - Complexity = 4
3192 : // Dst: (LDS_SUB_RET:i32 i32:i32:$src0, i32:i32:$src1)
3193 : /*7333*/ 0, /*End of Scope*/
3194 : /*7334*/ /*SwitchOpcode*/ 47|128,1/*175*/, TARGET_VAL(ISD::ATOMIC_LOAD_MIN),// ->7513
3195 : /*7338*/ OPC_RecordMemRef,
3196 : /*7339*/ OPC_RecordNode, // #0 = 'atomic_load_min' chained node
3197 : /*7340*/ OPC_Scope, 45, /*->7387*/ // 3 children in Scope
3198 : /*7342*/ OPC_RecordChild1, // #1 = $MUBUFAddr64Atomic:srsrc:vaddr:soffset:offset:slc
3199 : /*7343*/ OPC_RecordChild2, // #2 = $vdata_in
3200 : /*7344*/ OPC_CheckPredicate, 82, // Predicate_atomic_min_global
3201 : /*7346*/ OPC_CheckType, MVT::i32,
3202 : /*7348*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
3203 : /*7350*/ OPC_Scope, 17, /*->7369*/ // 2 children in Scope
3204 : /*7352*/ OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7
3205 : /*7355*/ OPC_EmitMergeInputChains1_0,
3206 : /*7356*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMIN_RTN_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
3207 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
3208 : // Src: (atomic_load_min:i32 (MUBUFAddr64Atomic:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_min_global>> - Complexity = 22
3209 : // Dst: (BUFFER_ATOMIC_SMIN_RTN_ADDR64:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3210 : /*7369*/ /*Scope*/ 16, /*->7386*/
3211 : /*7370*/ OPC_CheckComplexPat, /*CP*/7, /*#*/1, // SelectMUBUFOffset:$ #3 #4 #5 #6
3212 : /*7373*/ OPC_EmitMergeInputChains1_0,
3213 : /*7374*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMIN_RTN_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
3214 : 1/*#VTs*/, MVT::i32, 5/*#Ops*/, 2, 3, 4, 5, 6,
3215 : // Src: (atomic_load_min:i32 (MUBUFOffsetAtomic:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_min_global>> - Complexity = 19
3216 : // Dst: (BUFFER_ATOMIC_SMIN_RTN_OFFSET:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3217 : /*7386*/ 0, /*End of Scope*/
3218 : /*7387*/ /*Scope*/ 57, /*->7445*/
3219 : /*7388*/ OPC_CaptureGlueInput,
3220 : /*7389*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
3221 : /*7390*/ OPC_RecordChild2, // #2 = $value
3222 : /*7391*/ OPC_CheckPredicate, 83, // Predicate_si_atomic_load_min_local
3223 : /*7393*/ OPC_SwitchType /*2 cases */, 23, MVT::i32,// ->7419
3224 : /*7396*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3225 : /*7398*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3226 : /*7401*/ OPC_EmitMergeInputChains1_0,
3227 : /*7402*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3228 : /*7405*/ OPC_EmitInteger, MVT::i1, 0,
3229 : /*7408*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_MIN_RTN_I32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3230 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 3, 2, 5, 6,
3231 : // Src: (si_atomic_load_min_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i32:i32:$value)<<P:Predicate_si_atomic_load_min_local>> - Complexity = 13
3232 : // Dst: (DS_MIN_RTN_I32:i32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3233 : /*7419*/ /*SwitchType*/ 23, MVT::i64,// ->7444
3234 : /*7421*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3235 : /*7423*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3236 : /*7426*/ OPC_EmitMergeInputChains1_0,
3237 : /*7427*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3238 : /*7430*/ OPC_EmitInteger, MVT::i1, 0,
3239 : /*7433*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_MIN_RTN_I64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3240 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 3, 2, 5, 6,
3241 : // Src: (si_atomic_load_min_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i64:i64:$value)<<P:Predicate_si_atomic_load_min_local>> - Complexity = 13
3242 : // Dst: (DS_MIN_RTN_I64:i64 ?:i32:$ptr, ?:i64:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3243 : /*7444*/ 0, // EndSwitchType
3244 : /*7445*/ /*Scope*/ 66, /*->7512*/
3245 : /*7446*/ OPC_RecordChild1, // #1 = $src0
3246 : /*7447*/ OPC_CheckChild1Type, MVT::i32,
3247 : /*7449*/ OPC_RecordChild2, // #2 = $src1
3248 : /*7450*/ OPC_CheckPredicate, 84, // Predicate_atomic_load_min_local
3249 : /*7452*/ OPC_CheckType, MVT::i32,
3250 : /*7454*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3251 : /*7456*/ OPC_EmitMergeInputChains1_0,
3252 : /*7457*/ OPC_EmitInteger, MVT::i32, 0,
3253 : /*7460*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3254 : /*7472*/ OPC_EmitInteger, MVT::i32, 0,
3255 : /*7475*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3256 : /*7487*/ OPC_EmitInteger, MVT::i32, 1,
3257 : /*7490*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3258 : /*7493*/ OPC_EmitInteger, MVT::i32, 0,
3259 : /*7496*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_MIN_INT_RET), 0|OPFL_Chain|OPFL_MemRefs,
3260 : 1/*#VTs*/, MVT::i32, 9/*#Ops*/, 1, 3, 4, 2, 5, 6, 7, 8, 9,
3261 : // Src: (atomic_load_min:i32 i32:i32:$src0, i32:i32:$src1)<<P:Predicate_atomic_load_min_local>> - Complexity = 4
3262 : // Dst: (LDS_MIN_INT_RET:i32 i32:i32:$src0, i32:i32:$src1)
3263 : /*7512*/ 0, /*End of Scope*/
3264 : /*7513*/ /*SwitchOpcode*/ 47|128,1/*175*/, TARGET_VAL(ISD::ATOMIC_LOAD_UMIN),// ->7692
3265 : /*7517*/ OPC_RecordMemRef,
3266 : /*7518*/ OPC_RecordNode, // #0 = 'atomic_load_umin' chained node
3267 : /*7519*/ OPC_Scope, 45, /*->7566*/ // 3 children in Scope
3268 : /*7521*/ OPC_RecordChild1, // #1 = $MUBUFAddr64Atomic:srsrc:vaddr:soffset:offset:slc
3269 : /*7522*/ OPC_RecordChild2, // #2 = $vdata_in
3270 : /*7523*/ OPC_CheckPredicate, 85, // Predicate_atomic_umin_global
3271 : /*7525*/ OPC_CheckType, MVT::i32,
3272 : /*7527*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
3273 : /*7529*/ OPC_Scope, 17, /*->7548*/ // 2 children in Scope
3274 : /*7531*/ OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7
3275 : /*7534*/ OPC_EmitMergeInputChains1_0,
3276 : /*7535*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMIN_RTN_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
3277 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
3278 : // Src: (atomic_load_umin:i32 (MUBUFAddr64Atomic:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_umin_global>> - Complexity = 22
3279 : // Dst: (BUFFER_ATOMIC_UMIN_RTN_ADDR64:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3280 : /*7548*/ /*Scope*/ 16, /*->7565*/
3281 : /*7549*/ OPC_CheckComplexPat, /*CP*/7, /*#*/1, // SelectMUBUFOffset:$ #3 #4 #5 #6
3282 : /*7552*/ OPC_EmitMergeInputChains1_0,
3283 : /*7553*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMIN_RTN_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
3284 : 1/*#VTs*/, MVT::i32, 5/*#Ops*/, 2, 3, 4, 5, 6,
3285 : // Src: (atomic_load_umin:i32 (MUBUFOffsetAtomic:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_umin_global>> - Complexity = 19
3286 : // Dst: (BUFFER_ATOMIC_UMIN_RTN_OFFSET:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3287 : /*7565*/ 0, /*End of Scope*/
3288 : /*7566*/ /*Scope*/ 57, /*->7624*/
3289 : /*7567*/ OPC_CaptureGlueInput,
3290 : /*7568*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
3291 : /*7569*/ OPC_RecordChild2, // #2 = $value
3292 : /*7570*/ OPC_CheckPredicate, 86, // Predicate_si_atomic_load_umin_local
3293 : /*7572*/ OPC_SwitchType /*2 cases */, 23, MVT::i32,// ->7598
3294 : /*7575*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3295 : /*7577*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3296 : /*7580*/ OPC_EmitMergeInputChains1_0,
3297 : /*7581*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3298 : /*7584*/ OPC_EmitInteger, MVT::i1, 0,
3299 : /*7587*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_MIN_RTN_U32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3300 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 3, 2, 5, 6,
3301 : // Src: (si_atomic_load_umin_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i32:i32:$value)<<P:Predicate_si_atomic_load_umin_local>> - Complexity = 13
3302 : // Dst: (DS_MIN_RTN_U32:i32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3303 : /*7598*/ /*SwitchType*/ 23, MVT::i64,// ->7623
3304 : /*7600*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3305 : /*7602*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3306 : /*7605*/ OPC_EmitMergeInputChains1_0,
3307 : /*7606*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3308 : /*7609*/ OPC_EmitInteger, MVT::i1, 0,
3309 : /*7612*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_MIN_RTN_U64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3310 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 3, 2, 5, 6,
3311 : // Src: (si_atomic_load_umin_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i64:i64:$value)<<P:Predicate_si_atomic_load_umin_local>> - Complexity = 13
3312 : // Dst: (DS_MIN_RTN_U64:i64 ?:i32:$ptr, ?:i64:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3313 : /*7623*/ 0, // EndSwitchType
3314 : /*7624*/ /*Scope*/ 66, /*->7691*/
3315 : /*7625*/ OPC_RecordChild1, // #1 = $src0
3316 : /*7626*/ OPC_CheckChild1Type, MVT::i32,
3317 : /*7628*/ OPC_RecordChild2, // #2 = $src1
3318 : /*7629*/ OPC_CheckPredicate, 87, // Predicate_atomic_load_umin_local
3319 : /*7631*/ OPC_CheckType, MVT::i32,
3320 : /*7633*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3321 : /*7635*/ OPC_EmitMergeInputChains1_0,
3322 : /*7636*/ OPC_EmitInteger, MVT::i32, 0,
3323 : /*7639*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3324 : /*7651*/ OPC_EmitInteger, MVT::i32, 0,
3325 : /*7654*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3326 : /*7666*/ OPC_EmitInteger, MVT::i32, 1,
3327 : /*7669*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3328 : /*7672*/ OPC_EmitInteger, MVT::i32, 0,
3329 : /*7675*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_MIN_UINT_RET), 0|OPFL_Chain|OPFL_MemRefs,
3330 : 1/*#VTs*/, MVT::i32, 9/*#Ops*/, 1, 3, 4, 2, 5, 6, 7, 8, 9,
3331 : // Src: (atomic_load_umin:i32 i32:i32:$src0, i32:i32:$src1)<<P:Predicate_atomic_load_umin_local>> - Complexity = 4
3332 : // Dst: (LDS_MIN_UINT_RET:i32 i32:i32:$src0, i32:i32:$src1)
3333 : /*7691*/ 0, /*End of Scope*/
3334 : /*7692*/ /*SwitchOpcode*/ 47|128,1/*175*/, TARGET_VAL(ISD::ATOMIC_LOAD_MAX),// ->7871
3335 : /*7696*/ OPC_RecordMemRef,
3336 : /*7697*/ OPC_RecordNode, // #0 = 'atomic_load_max' chained node
3337 : /*7698*/ OPC_Scope, 45, /*->7745*/ // 3 children in Scope
3338 : /*7700*/ OPC_RecordChild1, // #1 = $MUBUFAddr64Atomic:srsrc:vaddr:soffset:offset:slc
3339 : /*7701*/ OPC_RecordChild2, // #2 = $vdata_in
3340 : /*7702*/ OPC_CheckPredicate, 88, // Predicate_atomic_max_global
3341 : /*7704*/ OPC_CheckType, MVT::i32,
3342 : /*7706*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
3343 : /*7708*/ OPC_Scope, 17, /*->7727*/ // 2 children in Scope
3344 : /*7710*/ OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7
3345 : /*7713*/ OPC_EmitMergeInputChains1_0,
3346 : /*7714*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMAX_RTN_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
3347 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
3348 : // Src: (atomic_load_max:i32 (MUBUFAddr64Atomic:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_max_global>> - Complexity = 22
3349 : // Dst: (BUFFER_ATOMIC_SMAX_RTN_ADDR64:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3350 : /*7727*/ /*Scope*/ 16, /*->7744*/
3351 : /*7728*/ OPC_CheckComplexPat, /*CP*/7, /*#*/1, // SelectMUBUFOffset:$ #3 #4 #5 #6
3352 : /*7731*/ OPC_EmitMergeInputChains1_0,
3353 : /*7732*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_SMAX_RTN_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
3354 : 1/*#VTs*/, MVT::i32, 5/*#Ops*/, 2, 3, 4, 5, 6,
3355 : // Src: (atomic_load_max:i32 (MUBUFOffsetAtomic:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_max_global>> - Complexity = 19
3356 : // Dst: (BUFFER_ATOMIC_SMAX_RTN_OFFSET:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3357 : /*7744*/ 0, /*End of Scope*/
3358 : /*7745*/ /*Scope*/ 57, /*->7803*/
3359 : /*7746*/ OPC_CaptureGlueInput,
3360 : /*7747*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
3361 : /*7748*/ OPC_RecordChild2, // #2 = $value
3362 : /*7749*/ OPC_CheckPredicate, 89, // Predicate_si_atomic_load_max_local
3363 : /*7751*/ OPC_SwitchType /*2 cases */, 23, MVT::i32,// ->7777
3364 : /*7754*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3365 : /*7756*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3366 : /*7759*/ OPC_EmitMergeInputChains1_0,
3367 : /*7760*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3368 : /*7763*/ OPC_EmitInteger, MVT::i1, 0,
3369 : /*7766*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_MAX_RTN_I32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3370 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 3, 2, 5, 6,
3371 : // Src: (si_atomic_load_max_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i32:i32:$value)<<P:Predicate_si_atomic_load_max_local>> - Complexity = 13
3372 : // Dst: (DS_MAX_RTN_I32:i32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3373 : /*7777*/ /*SwitchType*/ 23, MVT::i64,// ->7802
3374 : /*7779*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3375 : /*7781*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3376 : /*7784*/ OPC_EmitMergeInputChains1_0,
3377 : /*7785*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3378 : /*7788*/ OPC_EmitInteger, MVT::i1, 0,
3379 : /*7791*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_MAX_RTN_I64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3380 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 3, 2, 5, 6,
3381 : // Src: (si_atomic_load_max_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i64:i64:$value)<<P:Predicate_si_atomic_load_max_local>> - Complexity = 13
3382 : // Dst: (DS_MAX_RTN_I64:i64 ?:i32:$ptr, ?:i64:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3383 : /*7802*/ 0, // EndSwitchType
3384 : /*7803*/ /*Scope*/ 66, /*->7870*/
3385 : /*7804*/ OPC_RecordChild1, // #1 = $src0
3386 : /*7805*/ OPC_CheckChild1Type, MVT::i32,
3387 : /*7807*/ OPC_RecordChild2, // #2 = $src1
3388 : /*7808*/ OPC_CheckPredicate, 90, // Predicate_atomic_load_max_local
3389 : /*7810*/ OPC_CheckType, MVT::i32,
3390 : /*7812*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3391 : /*7814*/ OPC_EmitMergeInputChains1_0,
3392 : /*7815*/ OPC_EmitInteger, MVT::i32, 0,
3393 : /*7818*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3394 : /*7830*/ OPC_EmitInteger, MVT::i32, 0,
3395 : /*7833*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3396 : /*7845*/ OPC_EmitInteger, MVT::i32, 1,
3397 : /*7848*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3398 : /*7851*/ OPC_EmitInteger, MVT::i32, 0,
3399 : /*7854*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_MAX_INT_RET), 0|OPFL_Chain|OPFL_MemRefs,
3400 : 1/*#VTs*/, MVT::i32, 9/*#Ops*/, 1, 3, 4, 2, 5, 6, 7, 8, 9,
3401 : // Src: (atomic_load_max:i32 i32:i32:$src0, i32:i32:$src1)<<P:Predicate_atomic_load_max_local>> - Complexity = 4
3402 : // Dst: (LDS_MAX_INT_RET:i32 i32:i32:$src0, i32:i32:$src1)
3403 : /*7870*/ 0, /*End of Scope*/
3404 : /*7871*/ /*SwitchOpcode*/ 47|128,1/*175*/, TARGET_VAL(ISD::ATOMIC_LOAD_UMAX),// ->8050
3405 : /*7875*/ OPC_RecordMemRef,
3406 : /*7876*/ OPC_RecordNode, // #0 = 'atomic_load_umax' chained node
3407 : /*7877*/ OPC_Scope, 45, /*->7924*/ // 3 children in Scope
3408 : /*7879*/ OPC_RecordChild1, // #1 = $MUBUFAddr64Atomic:srsrc:vaddr:soffset:offset:slc
3409 : /*7880*/ OPC_RecordChild2, // #2 = $vdata_in
3410 : /*7881*/ OPC_CheckPredicate, 91, // Predicate_atomic_umax_global
3411 : /*7883*/ OPC_CheckType, MVT::i32,
3412 : /*7885*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
3413 : /*7887*/ OPC_Scope, 17, /*->7906*/ // 2 children in Scope
3414 : /*7889*/ OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7
3415 : /*7892*/ OPC_EmitMergeInputChains1_0,
3416 : /*7893*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMAX_RTN_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
3417 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
3418 : // Src: (atomic_load_umax:i32 (MUBUFAddr64Atomic:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_umax_global>> - Complexity = 22
3419 : // Dst: (BUFFER_ATOMIC_UMAX_RTN_ADDR64:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3420 : /*7906*/ /*Scope*/ 16, /*->7923*/
3421 : /*7907*/ OPC_CheckComplexPat, /*CP*/7, /*#*/1, // SelectMUBUFOffset:$ #3 #4 #5 #6
3422 : /*7910*/ OPC_EmitMergeInputChains1_0,
3423 : /*7911*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_UMAX_RTN_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
3424 : 1/*#VTs*/, MVT::i32, 5/*#Ops*/, 2, 3, 4, 5, 6,
3425 : // Src: (atomic_load_umax:i32 (MUBUFOffsetAtomic:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_umax_global>> - Complexity = 19
3426 : // Dst: (BUFFER_ATOMIC_UMAX_RTN_OFFSET:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3427 : /*7923*/ 0, /*End of Scope*/
3428 : /*7924*/ /*Scope*/ 57, /*->7982*/
3429 : /*7925*/ OPC_CaptureGlueInput,
3430 : /*7926*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
3431 : /*7927*/ OPC_RecordChild2, // #2 = $value
3432 : /*7928*/ OPC_CheckPredicate, 92, // Predicate_si_atomic_load_umax_local
3433 : /*7930*/ OPC_SwitchType /*2 cases */, 23, MVT::i32,// ->7956
3434 : /*7933*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3435 : /*7935*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3436 : /*7938*/ OPC_EmitMergeInputChains1_0,
3437 : /*7939*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3438 : /*7942*/ OPC_EmitInteger, MVT::i1, 0,
3439 : /*7945*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_MAX_RTN_U32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3440 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 3, 2, 5, 6,
3441 : // Src: (si_atomic_load_umax_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i32:i32:$value)<<P:Predicate_si_atomic_load_umax_local>> - Complexity = 13
3442 : // Dst: (DS_MAX_RTN_U32:i32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3443 : /*7956*/ /*SwitchType*/ 23, MVT::i64,// ->7981
3444 : /*7958*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3445 : /*7960*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3446 : /*7963*/ OPC_EmitMergeInputChains1_0,
3447 : /*7964*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3448 : /*7967*/ OPC_EmitInteger, MVT::i1, 0,
3449 : /*7970*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_MAX_RTN_U64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3450 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 3, 2, 5, 6,
3451 : // Src: (si_atomic_load_umax_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i64:i64:$value)<<P:Predicate_si_atomic_load_umax_local>> - Complexity = 13
3452 : // Dst: (DS_MAX_RTN_U64:i64 ?:i32:$ptr, ?:i64:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3453 : /*7981*/ 0, // EndSwitchType
3454 : /*7982*/ /*Scope*/ 66, /*->8049*/
3455 : /*7983*/ OPC_RecordChild1, // #1 = $src0
3456 : /*7984*/ OPC_CheckChild1Type, MVT::i32,
3457 : /*7986*/ OPC_RecordChild2, // #2 = $src1
3458 : /*7987*/ OPC_CheckPredicate, 93, // Predicate_atomic_load_umax_local
3459 : /*7989*/ OPC_CheckType, MVT::i32,
3460 : /*7991*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3461 : /*7993*/ OPC_EmitMergeInputChains1_0,
3462 : /*7994*/ OPC_EmitInteger, MVT::i32, 0,
3463 : /*7997*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3464 : /*8009*/ OPC_EmitInteger, MVT::i32, 0,
3465 : /*8012*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3466 : /*8024*/ OPC_EmitInteger, MVT::i32, 1,
3467 : /*8027*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3468 : /*8030*/ OPC_EmitInteger, MVT::i32, 0,
3469 : /*8033*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_MAX_UINT_RET), 0|OPFL_Chain|OPFL_MemRefs,
3470 : 1/*#VTs*/, MVT::i32, 9/*#Ops*/, 1, 3, 4, 2, 5, 6, 7, 8, 9,
3471 : // Src: (atomic_load_umax:i32 i32:i32:$src0, i32:i32:$src1)<<P:Predicate_atomic_load_umax_local>> - Complexity = 4
3472 : // Dst: (LDS_MAX_UINT_RET:i32 i32:i32:$src0, i32:i32:$src1)
3473 : /*8049*/ 0, /*End of Scope*/
3474 : /*8050*/ /*SwitchOpcode*/ 47|128,1/*175*/, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->8229
3475 : /*8054*/ OPC_RecordMemRef,
3476 : /*8055*/ OPC_RecordNode, // #0 = 'atomic_load_and' chained node
3477 : /*8056*/ OPC_Scope, 45, /*->8103*/ // 3 children in Scope
3478 : /*8058*/ OPC_RecordChild1, // #1 = $MUBUFAddr64Atomic:srsrc:vaddr:soffset:offset:slc
3479 : /*8059*/ OPC_RecordChild2, // #2 = $vdata_in
3480 : /*8060*/ OPC_CheckPredicate, 94, // Predicate_atomic_and_global
3481 : /*8062*/ OPC_CheckType, MVT::i32,
3482 : /*8064*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
3483 : /*8066*/ OPC_Scope, 17, /*->8085*/ // 2 children in Scope
3484 : /*8068*/ OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7
3485 : /*8071*/ OPC_EmitMergeInputChains1_0,
3486 : /*8072*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_AND_RTN_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
3487 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
3488 : // Src: (atomic_load_and:i32 (MUBUFAddr64Atomic:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_and_global>> - Complexity = 22
3489 : // Dst: (BUFFER_ATOMIC_AND_RTN_ADDR64:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3490 : /*8085*/ /*Scope*/ 16, /*->8102*/
3491 : /*8086*/ OPC_CheckComplexPat, /*CP*/7, /*#*/1, // SelectMUBUFOffset:$ #3 #4 #5 #6
3492 : /*8089*/ OPC_EmitMergeInputChains1_0,
3493 : /*8090*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_AND_RTN_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
3494 : 1/*#VTs*/, MVT::i32, 5/*#Ops*/, 2, 3, 4, 5, 6,
3495 : // Src: (atomic_load_and:i32 (MUBUFOffsetAtomic:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_and_global>> - Complexity = 19
3496 : // Dst: (BUFFER_ATOMIC_AND_RTN_OFFSET:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3497 : /*8102*/ 0, /*End of Scope*/
3498 : /*8103*/ /*Scope*/ 57, /*->8161*/
3499 : /*8104*/ OPC_CaptureGlueInput,
3500 : /*8105*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
3501 : /*8106*/ OPC_RecordChild2, // #2 = $value
3502 : /*8107*/ OPC_CheckPredicate, 95, // Predicate_si_atomic_load_and_local
3503 : /*8109*/ OPC_SwitchType /*2 cases */, 23, MVT::i32,// ->8135
3504 : /*8112*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3505 : /*8114*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3506 : /*8117*/ OPC_EmitMergeInputChains1_0,
3507 : /*8118*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3508 : /*8121*/ OPC_EmitInteger, MVT::i1, 0,
3509 : /*8124*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_AND_RTN_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3510 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 3, 2, 5, 6,
3511 : // Src: (si_atomic_load_and_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i32:i32:$value)<<P:Predicate_si_atomic_load_and_local>> - Complexity = 13
3512 : // Dst: (DS_AND_RTN_B32:i32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3513 : /*8135*/ /*SwitchType*/ 23, MVT::i64,// ->8160
3514 : /*8137*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3515 : /*8139*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3516 : /*8142*/ OPC_EmitMergeInputChains1_0,
3517 : /*8143*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3518 : /*8146*/ OPC_EmitInteger, MVT::i1, 0,
3519 : /*8149*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_AND_RTN_B64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3520 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 3, 2, 5, 6,
3521 : // Src: (si_atomic_load_and_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i64:i64:$value)<<P:Predicate_si_atomic_load_and_local>> - Complexity = 13
3522 : // Dst: (DS_AND_RTN_B64:i64 ?:i32:$ptr, ?:i64:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3523 : /*8160*/ 0, // EndSwitchType
3524 : /*8161*/ /*Scope*/ 66, /*->8228*/
3525 : /*8162*/ OPC_RecordChild1, // #1 = $src0
3526 : /*8163*/ OPC_CheckChild1Type, MVT::i32,
3527 : /*8165*/ OPC_RecordChild2, // #2 = $src1
3528 : /*8166*/ OPC_CheckPredicate, 96, // Predicate_atomic_load_and_local
3529 : /*8168*/ OPC_CheckType, MVT::i32,
3530 : /*8170*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3531 : /*8172*/ OPC_EmitMergeInputChains1_0,
3532 : /*8173*/ OPC_EmitInteger, MVT::i32, 0,
3533 : /*8176*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3534 : /*8188*/ OPC_EmitInteger, MVT::i32, 0,
3535 : /*8191*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3536 : /*8203*/ OPC_EmitInteger, MVT::i32, 1,
3537 : /*8206*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3538 : /*8209*/ OPC_EmitInteger, MVT::i32, 0,
3539 : /*8212*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_AND_RET), 0|OPFL_Chain|OPFL_MemRefs,
3540 : 1/*#VTs*/, MVT::i32, 9/*#Ops*/, 1, 3, 4, 2, 5, 6, 7, 8, 9,
3541 : // Src: (atomic_load_and:i32 i32:i32:$src0, i32:i32:$src1)<<P:Predicate_atomic_load_and_local>> - Complexity = 4
3542 : // Dst: (LDS_AND_RET:i32 i32:i32:$src0, i32:i32:$src1)
3543 : /*8228*/ 0, /*End of Scope*/
3544 : /*8229*/ /*SwitchOpcode*/ 47|128,1/*175*/, TARGET_VAL(ISD::ATOMIC_LOAD_OR),// ->8408
3545 : /*8233*/ OPC_RecordMemRef,
3546 : /*8234*/ OPC_RecordNode, // #0 = 'atomic_load_or' chained node
3547 : /*8235*/ OPC_Scope, 45, /*->8282*/ // 3 children in Scope
3548 : /*8237*/ OPC_RecordChild1, // #1 = $MUBUFAddr64Atomic:srsrc:vaddr:soffset:offset:slc
3549 : /*8238*/ OPC_RecordChild2, // #2 = $vdata_in
3550 : /*8239*/ OPC_CheckPredicate, 97, // Predicate_atomic_or_global
3551 : /*8241*/ OPC_CheckType, MVT::i32,
3552 : /*8243*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
3553 : /*8245*/ OPC_Scope, 17, /*->8264*/ // 2 children in Scope
3554 : /*8247*/ OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7
3555 : /*8250*/ OPC_EmitMergeInputChains1_0,
3556 : /*8251*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_OR_RTN_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
3557 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
3558 : // Src: (atomic_load_or:i32 (MUBUFAddr64Atomic:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_or_global>> - Complexity = 22
3559 : // Dst: (BUFFER_ATOMIC_OR_RTN_ADDR64:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3560 : /*8264*/ /*Scope*/ 16, /*->8281*/
3561 : /*8265*/ OPC_CheckComplexPat, /*CP*/7, /*#*/1, // SelectMUBUFOffset:$ #3 #4 #5 #6
3562 : /*8268*/ OPC_EmitMergeInputChains1_0,
3563 : /*8269*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_OR_RTN_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
3564 : 1/*#VTs*/, MVT::i32, 5/*#Ops*/, 2, 3, 4, 5, 6,
3565 : // Src: (atomic_load_or:i32 (MUBUFOffsetAtomic:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_or_global>> - Complexity = 19
3566 : // Dst: (BUFFER_ATOMIC_OR_RTN_OFFSET:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3567 : /*8281*/ 0, /*End of Scope*/
3568 : /*8282*/ /*Scope*/ 57, /*->8340*/
3569 : /*8283*/ OPC_CaptureGlueInput,
3570 : /*8284*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
3571 : /*8285*/ OPC_RecordChild2, // #2 = $value
3572 : /*8286*/ OPC_CheckPredicate, 98, // Predicate_si_atomic_load_or_local
3573 : /*8288*/ OPC_SwitchType /*2 cases */, 23, MVT::i32,// ->8314
3574 : /*8291*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3575 : /*8293*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3576 : /*8296*/ OPC_EmitMergeInputChains1_0,
3577 : /*8297*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3578 : /*8300*/ OPC_EmitInteger, MVT::i1, 0,
3579 : /*8303*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_OR_RTN_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3580 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 3, 2, 5, 6,
3581 : // Src: (si_atomic_load_or_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i32:i32:$value)<<P:Predicate_si_atomic_load_or_local>> - Complexity = 13
3582 : // Dst: (DS_OR_RTN_B32:i32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3583 : /*8314*/ /*SwitchType*/ 23, MVT::i64,// ->8339
3584 : /*8316*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3585 : /*8318*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3586 : /*8321*/ OPC_EmitMergeInputChains1_0,
3587 : /*8322*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3588 : /*8325*/ OPC_EmitInteger, MVT::i1, 0,
3589 : /*8328*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_OR_RTN_B64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3590 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 3, 2, 5, 6,
3591 : // Src: (si_atomic_load_or_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i64:i64:$value)<<P:Predicate_si_atomic_load_or_local>> - Complexity = 13
3592 : // Dst: (DS_OR_RTN_B64:i64 ?:i32:$ptr, ?:i64:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3593 : /*8339*/ 0, // EndSwitchType
3594 : /*8340*/ /*Scope*/ 66, /*->8407*/
3595 : /*8341*/ OPC_RecordChild1, // #1 = $src0
3596 : /*8342*/ OPC_CheckChild1Type, MVT::i32,
3597 : /*8344*/ OPC_RecordChild2, // #2 = $src1
3598 : /*8345*/ OPC_CheckPredicate, 99, // Predicate_atomic_load_or_local
3599 : /*8347*/ OPC_CheckType, MVT::i32,
3600 : /*8349*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3601 : /*8351*/ OPC_EmitMergeInputChains1_0,
3602 : /*8352*/ OPC_EmitInteger, MVT::i32, 0,
3603 : /*8355*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3604 : /*8367*/ OPC_EmitInteger, MVT::i32, 0,
3605 : /*8370*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3606 : /*8382*/ OPC_EmitInteger, MVT::i32, 1,
3607 : /*8385*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3608 : /*8388*/ OPC_EmitInteger, MVT::i32, 0,
3609 : /*8391*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_OR_RET), 0|OPFL_Chain|OPFL_MemRefs,
3610 : 1/*#VTs*/, MVT::i32, 9/*#Ops*/, 1, 3, 4, 2, 5, 6, 7, 8, 9,
3611 : // Src: (atomic_load_or:i32 i32:i32:$src0, i32:i32:$src1)<<P:Predicate_atomic_load_or_local>> - Complexity = 4
3612 : // Dst: (LDS_OR_RET:i32 i32:i32:$src0, i32:i32:$src1)
3613 : /*8407*/ 0, /*End of Scope*/
3614 : /*8408*/ /*SwitchOpcode*/ 47|128,1/*175*/, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->8587
3615 : /*8412*/ OPC_RecordMemRef,
3616 : /*8413*/ OPC_RecordNode, // #0 = 'atomic_load_xor' chained node
3617 : /*8414*/ OPC_Scope, 45, /*->8461*/ // 3 children in Scope
3618 : /*8416*/ OPC_RecordChild1, // #1 = $MUBUFAddr64Atomic:srsrc:vaddr:soffset:offset:slc
3619 : /*8417*/ OPC_RecordChild2, // #2 = $vdata_in
3620 : /*8418*/ OPC_CheckPredicate, 100, // Predicate_atomic_xor_global
3621 : /*8420*/ OPC_CheckType, MVT::i32,
3622 : /*8422*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
3623 : /*8424*/ OPC_Scope, 17, /*->8443*/ // 2 children in Scope
3624 : /*8426*/ OPC_CheckComplexPat, /*CP*/6, /*#*/1, // SelectMUBUFAddr64:$ #3 #4 #5 #6 #7
3625 : /*8429*/ OPC_EmitMergeInputChains1_0,
3626 : /*8430*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_XOR_RTN_ADDR64), 0|OPFL_Chain|OPFL_MemRefs,
3627 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 2, 3, 4, 5, 6, 7,
3628 : // Src: (atomic_load_xor:i32 (MUBUFAddr64Atomic:iPTR v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_xor_global>> - Complexity = 22
3629 : // Dst: (BUFFER_ATOMIC_XOR_RTN_ADDR64:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i64:i64:$vaddr, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3630 : /*8443*/ /*Scope*/ 16, /*->8460*/
3631 : /*8444*/ OPC_CheckComplexPat, /*CP*/7, /*#*/1, // SelectMUBUFOffset:$ #3 #4 #5 #6
3632 : /*8447*/ OPC_EmitMergeInputChains1_0,
3633 : /*8448*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_ATOMIC_XOR_RTN_OFFSET), 0|OPFL_Chain|OPFL_MemRefs,
3634 : 1/*#VTs*/, MVT::i32, 5/*#Ops*/, 2, 3, 4, 5, 6,
3635 : // Src: (atomic_load_xor:i32 (MUBUFOffsetAtomic:iPTR v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc), i32:i32:$vdata_in)<<P:Predicate_atomic_xor_global>> - Complexity = 19
3636 : // Dst: (BUFFER_ATOMIC_XOR_RTN_OFFSET:i32 i32:i32:$vdata_in, v4i32:v4i32:$srsrc, i32:i32:$soffset, i16:i16:$offset, i1:i1:$slc)
3637 : /*8460*/ 0, /*End of Scope*/
3638 : /*8461*/ /*Scope*/ 57, /*->8519*/
3639 : /*8462*/ OPC_CaptureGlueInput,
3640 : /*8463*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
3641 : /*8464*/ OPC_RecordChild2, // #2 = $value
3642 : /*8465*/ OPC_CheckPredicate, 101, // Predicate_si_atomic_load_xor_local
3643 : /*8467*/ OPC_SwitchType /*2 cases */, 23, MVT::i32,// ->8493
3644 : /*8470*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3645 : /*8472*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3646 : /*8475*/ OPC_EmitMergeInputChains1_0,
3647 : /*8476*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3648 : /*8479*/ OPC_EmitInteger, MVT::i1, 0,
3649 : /*8482*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_XOR_RTN_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3650 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 3, 2, 5, 6,
3651 : // Src: (si_atomic_load_xor_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i32:i32:$value)<<P:Predicate_si_atomic_load_xor_local>> - Complexity = 13
3652 : // Dst: (DS_XOR_RTN_B32:i32 ?:i32:$ptr, ?:i32:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3653 : /*8493*/ /*SwitchType*/ 23, MVT::i64,// ->8518
3654 : /*8495*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3655 : /*8497*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #3 #4
3656 : /*8500*/ OPC_EmitMergeInputChains1_0,
3657 : /*8501*/ OPC_EmitNodeXForm, 0, 4, // as_i16imm
3658 : /*8504*/ OPC_EmitInteger, MVT::i1, 0,
3659 : /*8507*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_XOR_RTN_B64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
3660 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 3, 2, 5, 6,
3661 : // Src: (si_atomic_load_xor_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i64:i64:$value)<<P:Predicate_si_atomic_load_xor_local>> - Complexity = 13
3662 : // Dst: (DS_XOR_RTN_B64:i64 ?:i32:$ptr, ?:i64:$value, (as_i16imm:i16 ?:i32:$offset), 0:i1)
3663 : /*8518*/ 0, // EndSwitchType
3664 : /*8519*/ /*Scope*/ 66, /*->8586*/
3665 : /*8520*/ OPC_RecordChild1, // #1 = $src0
3666 : /*8521*/ OPC_CheckChild1Type, MVT::i32,
3667 : /*8523*/ OPC_RecordChild2, // #2 = $src1
3668 : /*8524*/ OPC_CheckPredicate, 102, // Predicate_atomic_load_xor_local
3669 : /*8526*/ OPC_CheckType, MVT::i32,
3670 : /*8528*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3671 : /*8530*/ OPC_EmitMergeInputChains1_0,
3672 : /*8531*/ OPC_EmitInteger, MVT::i32, 0,
3673 : /*8534*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3674 : /*8546*/ OPC_EmitInteger, MVT::i32, 0,
3675 : /*8549*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3676 : /*8561*/ OPC_EmitInteger, MVT::i32, 1,
3677 : /*8564*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3678 : /*8567*/ OPC_EmitInteger, MVT::i32, 0,
3679 : /*8570*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_XOR_RET), 0|OPFL_Chain|OPFL_MemRefs,
3680 : 1/*#VTs*/, MVT::i32, 9/*#Ops*/, 1, 3, 4, 2, 5, 6, 7, 8, 9,
3681 : // Src: (atomic_load_xor:i32 i32:i32:$src0, i32:i32:$src1)<<P:Predicate_atomic_load_xor_local>> - Complexity = 4
3682 : // Dst: (LDS_XOR_RET:i32 i32:i32:$src0, i32:i32:$src1)
3683 : /*8586*/ 0, /*End of Scope*/
3684 : /*8587*/ /*SwitchOpcode*/ 6|128,1/*134*/, TARGET_VAL(AMDGPUISD::EXPORT),// ->8725
3685 : /*8591*/ OPC_RecordNode, // #0 = 'EXPORT' chained node
3686 : /*8592*/ OPC_RecordChild1, // #1 = $src
3687 : /*8593*/ OPC_CheckChild1Type, MVT::v4f32,
3688 : /*8595*/ OPC_RecordChild2, // #2 = $base
3689 : /*8596*/ OPC_MoveChild, 2,
3690 : /*8598*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
3691 : /*8601*/ OPC_CheckType, MVT::i32,
3692 : /*8603*/ OPC_MoveParent,
3693 : /*8604*/ OPC_RecordChild3, // #3 = $type
3694 : /*8605*/ OPC_MoveChild, 3,
3695 : /*8607*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
3696 : /*8610*/ OPC_CheckType, MVT::i32,
3697 : /*8612*/ OPC_MoveParent,
3698 : /*8613*/ OPC_RecordChild4, // #4 = $swz_x
3699 : /*8614*/ OPC_MoveChild, 4,
3700 : /*8616*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
3701 : /*8619*/ OPC_CheckType, MVT::i32,
3702 : /*8621*/ OPC_MoveParent,
3703 : /*8622*/ OPC_RecordChild5, // #5 = $swz_y
3704 : /*8623*/ OPC_MoveChild, 5,
3705 : /*8625*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
3706 : /*8628*/ OPC_CheckType, MVT::i32,
3707 : /*8630*/ OPC_MoveParent,
3708 : /*8631*/ OPC_RecordChild6, // #6 = $swz_z
3709 : /*8632*/ OPC_MoveChild, 6,
3710 : /*8634*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
3711 : /*8637*/ OPC_CheckType, MVT::i32,
3712 : /*8639*/ OPC_MoveParent,
3713 : /*8640*/ OPC_RecordChild7, // #7 = $swz_w
3714 : /*8641*/ OPC_MoveChild, 7,
3715 : /*8643*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
3716 : /*8646*/ OPC_CheckType, MVT::i32,
3717 : /*8648*/ OPC_MoveParent,
3718 : /*8649*/ OPC_Scope, 36, /*->8687*/ // 2 children in Scope
3719 : /*8651*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
3720 : /*8653*/ OPC_EmitMergeInputChains1_0,
3721 : /*8654*/ OPC_EmitConvertToTarget, 3,
3722 : /*8656*/ OPC_EmitConvertToTarget, 2,
3723 : /*8658*/ OPC_EmitConvertToTarget, 4,
3724 : /*8660*/ OPC_EmitConvertToTarget, 5,
3725 : /*8662*/ OPC_EmitConvertToTarget, 6,
3726 : /*8664*/ OPC_EmitConvertToTarget, 7,
3727 : /*8666*/ OPC_EmitInteger, MVT::i32, 39,
3728 : /*8669*/ OPC_EmitInteger, MVT::i32, 0,
3729 : /*8672*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_ExportSwz), 0|OPFL_Chain,
3730 : 0/*#VTs*/, 9/*#Ops*/, 1, 8, 9, 10, 11, 12, 13, 14, 15,
3731 : // Src: (EXPORT R600_Reg128:v4f32:$src, (imm:i32):$base, (imm:i32):$type, (imm:i32):$swz_x, (imm:i32):$swz_y, (imm:i32):$swz_z, (imm:i32):$swz_w) - Complexity = 21
3732 : // Dst: (R600_ExportSwz R600_Reg128:v4f32:$src, (imm:i32):$type, (imm:i32):$base, (imm:i32):$swz_x, (imm:i32):$swz_y, (imm:i32):$swz_z, (imm:i32):$swz_w, 39:i32, 0:i32)
3733 : /*8687*/ /*Scope*/ 36, /*->8724*/
3734 : /*8688*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3735 : /*8690*/ OPC_EmitMergeInputChains1_0,
3736 : /*8691*/ OPC_EmitConvertToTarget, 3,
3737 : /*8693*/ OPC_EmitConvertToTarget, 2,
3738 : /*8695*/ OPC_EmitConvertToTarget, 4,
3739 : /*8697*/ OPC_EmitConvertToTarget, 5,
3740 : /*8699*/ OPC_EmitConvertToTarget, 6,
3741 : /*8701*/ OPC_EmitConvertToTarget, 7,
3742 : /*8703*/ OPC_EmitInteger, MVT::i32, 83,
3743 : /*8706*/ OPC_EmitInteger, MVT::i32, 0,
3744 : /*8709*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EG_ExportSwz), 0|OPFL_Chain,
3745 : 0/*#VTs*/, 9/*#Ops*/, 1, 8, 9, 10, 11, 12, 13, 14, 15,
3746 : // Src: (EXPORT R600_Reg128:v4f32:$src, (imm:i32):$base, (imm:i32):$type, (imm:i32):$swz_x, (imm:i32):$swz_y, (imm:i32):$swz_z, (imm:i32):$swz_w) - Complexity = 21
3747 : // Dst: (EG_ExportSwz R600_Reg128:v4f32:$src, (imm:i32):$type, (imm:i32):$base, (imm:i32):$swz_x, (imm:i32):$swz_y, (imm:i32):$swz_z, (imm:i32):$swz_w, 83:i32, 0:i32)
3748 : /*8724*/ 0, /*End of Scope*/
3749 : /*8725*/ /*SwitchOpcode*/ 33|128,2/*289*/, TARGET_VAL(ISD::SHL),// ->9018
3750 : /*8729*/ OPC_Scope, 44, /*->8775*/ // 2 children in Scope
3751 : /*8731*/ OPC_MoveChild, 0,
3752 : /*8733*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
3753 : /*8736*/ OPC_MoveChild, 0,
3754 : /*8738*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
3755 : /*8741*/ OPC_CheckChild0Integer, 1,
3756 : /*8743*/ OPC_RecordChild1, // #0 = $a
3757 : /*8744*/ OPC_CheckChild1Type, MVT::i32,
3758 : /*8746*/ OPC_MoveParent,
3759 : /*8747*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3760 : /*8758*/ OPC_MoveParent,
3761 : /*8759*/ OPC_RecordChild1, // #1 = $b
3762 : /*8760*/ OPC_CheckChild1Type, MVT::i32,
3763 : /*8762*/ OPC_CheckType, MVT::i32,
3764 : /*8764*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3765 : /*8766*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BFM_B32), 0,
3766 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
3767 : // Src: (shl:i32 (add:i32 (shl:i32 1:i32, i32:i32:$a), -1:i32), i32:i32:$b) - Complexity = 19
3768 : // Dst: (S_BFM_B32:i32 ?:i32:$a, ?:i32:$b)
3769 : /*8775*/ /*Scope*/ 112|128,1/*240*/, /*->9017*/
3770 : /*8777*/ OPC_RecordChild0, // #0 = $src0
3771 : /*8778*/ OPC_RecordChild1, // #1 = $src1
3772 : /*8779*/ OPC_CheckChild1Type, MVT::i32,
3773 : /*8781*/ OPC_SwitchType /*2 cases */, 90|128,1/*218*/, MVT::i32,// ->9003
3774 : /*8785*/ OPC_Scope, 11, /*->8798*/ // 3 children in Scope
3775 : /*8787*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
3776 : /*8789*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LSHL_B32), 0,
3777 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
3778 : // Src: (shl:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 4
3779 : // Dst: (S_LSHL_B32:i32 i32:i32:$src0, i32:i32:$src1)
3780 : /*8798*/ /*Scope*/ 101, /*->8900*/
3781 : /*8799*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
3782 : /*8801*/ OPC_EmitInteger, MVT::i32, 0,
3783 : /*8804*/ OPC_EmitInteger, MVT::i32, 0,
3784 : /*8807*/ OPC_EmitInteger, MVT::i32, 1,
3785 : /*8810*/ OPC_EmitInteger, MVT::i32, 0,
3786 : /*8813*/ OPC_EmitInteger, MVT::i32, 0,
3787 : /*8816*/ OPC_EmitInteger, MVT::i32, 0,
3788 : /*8819*/ OPC_EmitInteger, MVT::i32, 0,
3789 : /*8822*/ OPC_EmitInteger, MVT::i32, 0,
3790 : /*8825*/ OPC_EmitInteger, MVT::i32, 0,
3791 : /*8828*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3792 : /*8840*/ OPC_EmitInteger, MVT::i32, 0,
3793 : /*8843*/ OPC_EmitInteger, MVT::i32, 0,
3794 : /*8846*/ OPC_EmitInteger, MVT::i32, 0,
3795 : /*8849*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3796 : /*8861*/ OPC_EmitInteger, MVT::i32, 1,
3797 : /*8864*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3798 : /*8867*/ OPC_EmitInteger, MVT::i32, 0,
3799 : /*8870*/ OPC_EmitInteger, MVT::i32, 0,
3800 : /*8873*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LSHL_r600), 0,
3801 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
3802 : // Src: (shl:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
3803 : // Dst: (LSHL_r600:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
3804 : /*8900*/ /*Scope*/ 101, /*->9002*/
3805 : /*8901*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3806 : /*8903*/ OPC_EmitInteger, MVT::i32, 0,
3807 : /*8906*/ OPC_EmitInteger, MVT::i32, 0,
3808 : /*8909*/ OPC_EmitInteger, MVT::i32, 1,
3809 : /*8912*/ OPC_EmitInteger, MVT::i32, 0,
3810 : /*8915*/ OPC_EmitInteger, MVT::i32, 0,
3811 : /*8918*/ OPC_EmitInteger, MVT::i32, 0,
3812 : /*8921*/ OPC_EmitInteger, MVT::i32, 0,
3813 : /*8924*/ OPC_EmitInteger, MVT::i32, 0,
3814 : /*8927*/ OPC_EmitInteger, MVT::i32, 0,
3815 : /*8930*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3816 : /*8942*/ OPC_EmitInteger, MVT::i32, 0,
3817 : /*8945*/ OPC_EmitInteger, MVT::i32, 0,
3818 : /*8948*/ OPC_EmitInteger, MVT::i32, 0,
3819 : /*8951*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3820 : /*8963*/ OPC_EmitInteger, MVT::i32, 1,
3821 : /*8966*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3822 : /*8969*/ OPC_EmitInteger, MVT::i32, 0,
3823 : /*8972*/ OPC_EmitInteger, MVT::i32, 0,
3824 : /*8975*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LSHL_eg), 0,
3825 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
3826 : // Src: (shl:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
3827 : // Dst: (LSHL_eg:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
3828 : /*9002*/ 0, /*End of Scope*/
3829 : /*9003*/ /*SwitchType*/ 11, MVT::i64,// ->9016
3830 : /*9005*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
3831 : /*9007*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LSHL_B64), 0,
3832 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 0, 1,
3833 : // Src: (shl:i64 i64:i64:$src0, i32:i32:$src1) - Complexity = 4
3834 : // Dst: (S_LSHL_B64:i64 i64:i64:$src0, i32:i32:$src1)
3835 : /*9016*/ 0, // EndSwitchType
3836 : /*9017*/ 0, /*End of Scope*/
3837 : /*9018*/ /*SwitchOpcode*/ 89|128,40/*5209*/, TARGET_VAL(ISD::OR),// ->14231
3838 : /*9022*/ OPC_Scope, 63|128,39/*5055*/, /*->14080*/ // 2 children in Scope
3839 : /*9025*/ OPC_MoveChild, 0,
3840 : /*9027*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
3841 : /*9030*/ OPC_Scope, 71|128,2/*327*/, /*->9360*/ // 8 children in Scope
3842 : /*9033*/ OPC_RecordChild0, // #0 = $y
3843 : /*9034*/ OPC_Scope, 1|128,2/*257*/, /*->9294*/ // 2 children in Scope
3844 : /*9037*/ OPC_RecordChild1, // #1 = $x
3845 : /*9038*/ OPC_MoveParent,
3846 : /*9039*/ OPC_MoveChild, 1,
3847 : /*9041*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
3848 : /*9044*/ OPC_Scope, 10|128,1/*138*/, /*->9185*/ // 4 children in Scope
3849 : /*9047*/ OPC_RecordChild0, // #2 = $z
3850 : /*9048*/ OPC_MoveChild, 1,
3851 : /*9050*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
3852 : /*9053*/ OPC_CheckChild0Same, 1,
3853 : /*9055*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3854 : /*9066*/ OPC_MoveParent,
3855 : /*9067*/ OPC_MoveParent,
3856 : /*9068*/ OPC_CheckType, MVT::i32,
3857 : /*9070*/ OPC_Scope, 99, /*->9171*/ // 2 children in Scope
3858 : /*9072*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
3859 : /*9074*/ OPC_EmitInteger, MVT::i32, 0,
3860 : /*9077*/ OPC_EmitInteger, MVT::i32, 0,
3861 : /*9080*/ OPC_EmitInteger, MVT::i32, 0,
3862 : /*9083*/ OPC_EmitInteger, MVT::i32, 0,
3863 : /*9086*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3864 : /*9098*/ OPC_EmitInteger, MVT::i32, 0,
3865 : /*9101*/ OPC_EmitInteger, MVT::i32, 0,
3866 : /*9104*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3867 : /*9116*/ OPC_EmitInteger, MVT::i32, 0,
3868 : /*9119*/ OPC_EmitInteger, MVT::i32, 0,
3869 : /*9122*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3870 : /*9134*/ OPC_EmitInteger, MVT::i32, 1,
3871 : /*9137*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
3872 : /*9140*/ OPC_EmitInteger, MVT::i32, 0,
3873 : /*9143*/ OPC_EmitInteger, MVT::i32, 0,
3874 : /*9146*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
3875 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 1, 5, 6, 7, 0, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
3876 : // Src: (or:i32 (and:i32 i32:i32:$y, i32:i32:$x), (and:i32 i32:i32:$z, (xor:i32 i32:i32:$x, -1:i32))) - Complexity = 17
3877 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
3878 : /*9171*/ /*Scope*/ 12, /*->9184*/
3879 : /*9172*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3880 : /*9174*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
3881 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 0, 2,
3882 : // Src: (or:i32 (and:i32 i32:i32:$y, i32:i32:$x), (and:i32 i32:i32:$z, (xor:i32 i32:i32:$x, -1:i32))) - Complexity = 17
3883 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
3884 : /*9184*/ 0, /*End of Scope*/
3885 : /*9185*/ /*Scope*/ 35, /*->9221*/
3886 : /*9186*/ OPC_MoveChild, 0,
3887 : /*9188*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
3888 : /*9191*/ OPC_CheckChild0Same, 1,
3889 : /*9193*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3890 : /*9204*/ OPC_MoveParent,
3891 : /*9205*/ OPC_RecordChild1, // #2 = $z
3892 : /*9206*/ OPC_MoveParent,
3893 : /*9207*/ OPC_CheckType, MVT::i32,
3894 : /*9209*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3895 : /*9211*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
3896 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 0, 2,
3897 : // Src: (or:i32 (and:i32 i32:i32:$y, i32:i32:$x), (and:i32 (xor:i32 i32:i32:$x, -1:i32), i32:i32:$z)) - Complexity = 17
3898 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
3899 : /*9221*/ /*Scope*/ 35, /*->9257*/
3900 : /*9222*/ OPC_RecordChild0, // #2 = $z
3901 : /*9223*/ OPC_MoveChild, 1,
3902 : /*9225*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
3903 : /*9228*/ OPC_CheckChild0Same, 0,
3904 : /*9230*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3905 : /*9241*/ OPC_MoveParent,
3906 : /*9242*/ OPC_MoveParent,
3907 : /*9243*/ OPC_CheckType, MVT::i32,
3908 : /*9245*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3909 : /*9247*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
3910 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
3911 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$y), (and:i32 i32:i32:$z, (xor:i32 i32:i32:$x, -1:i32))) - Complexity = 17
3912 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
3913 : /*9257*/ /*Scope*/ 35, /*->9293*/
3914 : /*9258*/ OPC_MoveChild, 0,
3915 : /*9260*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
3916 : /*9263*/ OPC_CheckChild0Same, 0,
3917 : /*9265*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3918 : /*9276*/ OPC_MoveParent,
3919 : /*9277*/ OPC_RecordChild1, // #2 = $z
3920 : /*9278*/ OPC_MoveParent,
3921 : /*9279*/ OPC_CheckType, MVT::i32,
3922 : /*9281*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3923 : /*9283*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
3924 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
3925 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$y), (and:i32 (xor:i32 i32:i32:$x, -1:i32), i32:i32:$z)) - Complexity = 17
3926 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
3927 : /*9293*/ 0, /*End of Scope*/
3928 : /*9294*/ /*Scope*/ 64, /*->9359*/
3929 : /*9295*/ OPC_MoveChild, 1,
3930 : /*9297*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
3931 : /*9300*/ OPC_RecordChild0, // #1 = $x
3932 : /*9301*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3933 : /*9312*/ OPC_MoveParent,
3934 : /*9313*/ OPC_MoveParent,
3935 : /*9314*/ OPC_MoveChild, 1,
3936 : /*9316*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
3937 : /*9319*/ OPC_Scope, 18, /*->9339*/ // 2 children in Scope
3938 : /*9321*/ OPC_RecordChild0, // #2 = $y
3939 : /*9322*/ OPC_CheckChild1Same, 1,
3940 : /*9324*/ OPC_MoveParent,
3941 : /*9325*/ OPC_CheckType, MVT::i32,
3942 : /*9327*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3943 : /*9329*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
3944 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 2, 0,
3945 : // Src: (or:i32 (and:i32 i32:i32:$z, (xor:i32 i32:i32:$x, -1:i32)), (and:i32 i32:i32:$y, i32:i32:$x)) - Complexity = 17
3946 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
3947 : /*9339*/ /*Scope*/ 18, /*->9358*/
3948 : /*9340*/ OPC_CheckChild0Same, 1,
3949 : /*9342*/ OPC_RecordChild1, // #2 = $y
3950 : /*9343*/ OPC_MoveParent,
3951 : /*9344*/ OPC_CheckType, MVT::i32,
3952 : /*9346*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3953 : /*9348*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
3954 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 2, 0,
3955 : // Src: (or:i32 (and:i32 i32:i32:$z, (xor:i32 i32:i32:$x, -1:i32)), (and:i32 i32:i32:$x, i32:i32:$y)) - Complexity = 17
3956 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
3957 : /*9358*/ 0, /*End of Scope*/
3958 : /*9359*/ 0, /*End of Scope*/
3959 : /*9360*/ /*Scope*/ 65, /*->9426*/
3960 : /*9361*/ OPC_MoveChild, 0,
3961 : /*9363*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
3962 : /*9366*/ OPC_RecordChild0, // #0 = $x
3963 : /*9367*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
3964 : /*9378*/ OPC_MoveParent,
3965 : /*9379*/ OPC_RecordChild1, // #1 = $z
3966 : /*9380*/ OPC_MoveParent,
3967 : /*9381*/ OPC_MoveChild, 1,
3968 : /*9383*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
3969 : /*9386*/ OPC_Scope, 18, /*->9406*/ // 2 children in Scope
3970 : /*9388*/ OPC_RecordChild0, // #2 = $y
3971 : /*9389*/ OPC_CheckChild1Same, 0,
3972 : /*9391*/ OPC_MoveParent,
3973 : /*9392*/ OPC_CheckType, MVT::i32,
3974 : /*9394*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3975 : /*9396*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
3976 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 2, 1,
3977 : // Src: (or:i32 (and:i32 (xor:i32 i32:i32:$x, -1:i32), i32:i32:$z), (and:i32 i32:i32:$y, i32:i32:$x)) - Complexity = 17
3978 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
3979 : /*9406*/ /*Scope*/ 18, /*->9425*/
3980 : /*9407*/ OPC_CheckChild0Same, 0,
3981 : /*9409*/ OPC_RecordChild1, // #2 = $y
3982 : /*9410*/ OPC_MoveParent,
3983 : /*9411*/ OPC_CheckType, MVT::i32,
3984 : /*9413*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
3985 : /*9415*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
3986 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 2, 1,
3987 : // Src: (or:i32 (and:i32 (xor:i32 i32:i32:$x, -1:i32), i32:i32:$z), (and:i32 i32:i32:$x, i32:i32:$y)) - Complexity = 17
3988 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
3989 : /*9425*/ 0, /*End of Scope*/
3990 : /*9426*/ /*Scope*/ 111|128,4/*623*/, /*->10051*/
3991 : /*9428*/ OPC_RecordChild0, // #0 = $y
3992 : /*9429*/ OPC_Scope, 122|128,2/*378*/, /*->9810*/ // 2 children in Scope
3993 : /*9432*/ OPC_RecordChild1, // #1 = $x
3994 : /*9433*/ OPC_MoveParent,
3995 : /*9434*/ OPC_MoveChild, 1,
3996 : /*9436*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
3997 : /*9439*/ OPC_Scope, 122, /*->9563*/ // 3 children in Scope
3998 : /*9441*/ OPC_MoveChild, 0,
3999 : /*9443*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
4000 : /*9446*/ OPC_CheckChild0Same, 1,
4001 : /*9448*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4002 : /*9459*/ OPC_MoveParent,
4003 : /*9460*/ OPC_RecordChild1, // #2 = $z
4004 : /*9461*/ OPC_MoveParent,
4005 : /*9462*/ OPC_CheckType, MVT::i32,
4006 : /*9464*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4007 : /*9466*/ OPC_EmitInteger, MVT::i32, 0,
4008 : /*9469*/ OPC_EmitInteger, MVT::i32, 0,
4009 : /*9472*/ OPC_EmitInteger, MVT::i32, 0,
4010 : /*9475*/ OPC_EmitInteger, MVT::i32, 0,
4011 : /*9478*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4012 : /*9490*/ OPC_EmitInteger, MVT::i32, 0,
4013 : /*9493*/ OPC_EmitInteger, MVT::i32, 0,
4014 : /*9496*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4015 : /*9508*/ OPC_EmitInteger, MVT::i32, 0,
4016 : /*9511*/ OPC_EmitInteger, MVT::i32, 0,
4017 : /*9514*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4018 : /*9526*/ OPC_EmitInteger, MVT::i32, 1,
4019 : /*9529*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4020 : /*9532*/ OPC_EmitInteger, MVT::i32, 0,
4021 : /*9535*/ OPC_EmitInteger, MVT::i32, 0,
4022 : /*9538*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4023 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 1, 5, 6, 7, 0, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4024 : // Src: (or:i32 (and:i32 i32:i32:$y, i32:i32:$x), (and:i32 (xor:i32 i32:i32:$x, -1:i32), i32:i32:$z)) - Complexity = 17
4025 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
4026 : /*9563*/ /*Scope*/ 122, /*->9686*/
4027 : /*9564*/ OPC_RecordChild0, // #2 = $z
4028 : /*9565*/ OPC_MoveChild, 1,
4029 : /*9567*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
4030 : /*9570*/ OPC_CheckChild0Same, 0,
4031 : /*9572*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4032 : /*9583*/ OPC_MoveParent,
4033 : /*9584*/ OPC_MoveParent,
4034 : /*9585*/ OPC_CheckType, MVT::i32,
4035 : /*9587*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4036 : /*9589*/ OPC_EmitInteger, MVT::i32, 0,
4037 : /*9592*/ OPC_EmitInteger, MVT::i32, 0,
4038 : /*9595*/ OPC_EmitInteger, MVT::i32, 0,
4039 : /*9598*/ OPC_EmitInteger, MVT::i32, 0,
4040 : /*9601*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4041 : /*9613*/ OPC_EmitInteger, MVT::i32, 0,
4042 : /*9616*/ OPC_EmitInteger, MVT::i32, 0,
4043 : /*9619*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4044 : /*9631*/ OPC_EmitInteger, MVT::i32, 0,
4045 : /*9634*/ OPC_EmitInteger, MVT::i32, 0,
4046 : /*9637*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4047 : /*9649*/ OPC_EmitInteger, MVT::i32, 1,
4048 : /*9652*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4049 : /*9655*/ OPC_EmitInteger, MVT::i32, 0,
4050 : /*9658*/ OPC_EmitInteger, MVT::i32, 0,
4051 : /*9661*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4052 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4053 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$y), (and:i32 i32:i32:$z, (xor:i32 i32:i32:$x, -1:i32))) - Complexity = 17
4054 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
4055 : /*9686*/ /*Scope*/ 122, /*->9809*/
4056 : /*9687*/ OPC_MoveChild, 0,
4057 : /*9689*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
4058 : /*9692*/ OPC_CheckChild0Same, 0,
4059 : /*9694*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4060 : /*9705*/ OPC_MoveParent,
4061 : /*9706*/ OPC_RecordChild1, // #2 = $z
4062 : /*9707*/ OPC_MoveParent,
4063 : /*9708*/ OPC_CheckType, MVT::i32,
4064 : /*9710*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4065 : /*9712*/ OPC_EmitInteger, MVT::i32, 0,
4066 : /*9715*/ OPC_EmitInteger, MVT::i32, 0,
4067 : /*9718*/ OPC_EmitInteger, MVT::i32, 0,
4068 : /*9721*/ OPC_EmitInteger, MVT::i32, 0,
4069 : /*9724*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4070 : /*9736*/ OPC_EmitInteger, MVT::i32, 0,
4071 : /*9739*/ OPC_EmitInteger, MVT::i32, 0,
4072 : /*9742*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4073 : /*9754*/ OPC_EmitInteger, MVT::i32, 0,
4074 : /*9757*/ OPC_EmitInteger, MVT::i32, 0,
4075 : /*9760*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4076 : /*9772*/ OPC_EmitInteger, MVT::i32, 1,
4077 : /*9775*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4078 : /*9778*/ OPC_EmitInteger, MVT::i32, 0,
4079 : /*9781*/ OPC_EmitInteger, MVT::i32, 0,
4080 : /*9784*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4081 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
4082 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$y), (and:i32 (xor:i32 i32:i32:$x, -1:i32), i32:i32:$z)) - Complexity = 17
4083 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
4084 : /*9809*/ 0, /*End of Scope*/
4085 : /*9810*/ /*Scope*/ 110|128,1/*238*/, /*->10050*/
4086 : /*9812*/ OPC_MoveChild, 1,
4087 : /*9814*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
4088 : /*9817*/ OPC_RecordChild0, // #1 = $x
4089 : /*9818*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4090 : /*9829*/ OPC_MoveParent,
4091 : /*9830*/ OPC_MoveParent,
4092 : /*9831*/ OPC_MoveChild, 1,
4093 : /*9833*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
4094 : /*9836*/ OPC_Scope, 105, /*->9943*/ // 2 children in Scope
4095 : /*9838*/ OPC_RecordChild0, // #2 = $y
4096 : /*9839*/ OPC_CheckChild1Same, 1,
4097 : /*9841*/ OPC_MoveParent,
4098 : /*9842*/ OPC_CheckType, MVT::i32,
4099 : /*9844*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4100 : /*9846*/ OPC_EmitInteger, MVT::i32, 0,
4101 : /*9849*/ OPC_EmitInteger, MVT::i32, 0,
4102 : /*9852*/ OPC_EmitInteger, MVT::i32, 0,
4103 : /*9855*/ OPC_EmitInteger, MVT::i32, 0,
4104 : /*9858*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4105 : /*9870*/ OPC_EmitInteger, MVT::i32, 0,
4106 : /*9873*/ OPC_EmitInteger, MVT::i32, 0,
4107 : /*9876*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4108 : /*9888*/ OPC_EmitInteger, MVT::i32, 0,
4109 : /*9891*/ OPC_EmitInteger, MVT::i32, 0,
4110 : /*9894*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4111 : /*9906*/ OPC_EmitInteger, MVT::i32, 1,
4112 : /*9909*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4113 : /*9912*/ OPC_EmitInteger, MVT::i32, 0,
4114 : /*9915*/ OPC_EmitInteger, MVT::i32, 0,
4115 : /*9918*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4116 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 1, 5, 6, 7, 2, 8, 9, 10, 0, 11, 12, 13, 14, 15, 16, 17,
4117 : // Src: (or:i32 (and:i32 i32:i32:$z, (xor:i32 i32:i32:$x, -1:i32)), (and:i32 i32:i32:$y, i32:i32:$x)) - Complexity = 17
4118 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
4119 : /*9943*/ /*Scope*/ 105, /*->10049*/
4120 : /*9944*/ OPC_CheckChild0Same, 1,
4121 : /*9946*/ OPC_RecordChild1, // #2 = $y
4122 : /*9947*/ OPC_MoveParent,
4123 : /*9948*/ OPC_CheckType, MVT::i32,
4124 : /*9950*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4125 : /*9952*/ OPC_EmitInteger, MVT::i32, 0,
4126 : /*9955*/ OPC_EmitInteger, MVT::i32, 0,
4127 : /*9958*/ OPC_EmitInteger, MVT::i32, 0,
4128 : /*9961*/ OPC_EmitInteger, MVT::i32, 0,
4129 : /*9964*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4130 : /*9976*/ OPC_EmitInteger, MVT::i32, 0,
4131 : /*9979*/ OPC_EmitInteger, MVT::i32, 0,
4132 : /*9982*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4133 : /*9994*/ OPC_EmitInteger, MVT::i32, 0,
4134 : /*9997*/ OPC_EmitInteger, MVT::i32, 0,
4135 : /*10000*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4136 : /*10012*/ OPC_EmitInteger, MVT::i32, 1,
4137 : /*10015*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4138 : /*10018*/ OPC_EmitInteger, MVT::i32, 0,
4139 : /*10021*/ OPC_EmitInteger, MVT::i32, 0,
4140 : /*10024*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4141 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 1, 5, 6, 7, 2, 8, 9, 10, 0, 11, 12, 13, 14, 15, 16, 17,
4142 : // Src: (or:i32 (and:i32 i32:i32:$z, (xor:i32 i32:i32:$x, -1:i32)), (and:i32 i32:i32:$x, i32:i32:$y)) - Complexity = 17
4143 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
4144 : /*10049*/ 0, /*End of Scope*/
4145 : /*10050*/ 0, /*End of Scope*/
4146 : /*10051*/ /*Scope*/ 111|128,1/*239*/, /*->10292*/
4147 : /*10053*/ OPC_MoveChild, 0,
4148 : /*10055*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
4149 : /*10058*/ OPC_RecordChild0, // #0 = $x
4150 : /*10059*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4151 : /*10070*/ OPC_MoveParent,
4152 : /*10071*/ OPC_RecordChild1, // #1 = $z
4153 : /*10072*/ OPC_MoveParent,
4154 : /*10073*/ OPC_MoveChild, 1,
4155 : /*10075*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
4156 : /*10078*/ OPC_Scope, 105, /*->10185*/ // 2 children in Scope
4157 : /*10080*/ OPC_RecordChild0, // #2 = $y
4158 : /*10081*/ OPC_CheckChild1Same, 0,
4159 : /*10083*/ OPC_MoveParent,
4160 : /*10084*/ OPC_CheckType, MVT::i32,
4161 : /*10086*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4162 : /*10088*/ OPC_EmitInteger, MVT::i32, 0,
4163 : /*10091*/ OPC_EmitInteger, MVT::i32, 0,
4164 : /*10094*/ OPC_EmitInteger, MVT::i32, 0,
4165 : /*10097*/ OPC_EmitInteger, MVT::i32, 0,
4166 : /*10100*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4167 : /*10112*/ OPC_EmitInteger, MVT::i32, 0,
4168 : /*10115*/ OPC_EmitInteger, MVT::i32, 0,
4169 : /*10118*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4170 : /*10130*/ OPC_EmitInteger, MVT::i32, 0,
4171 : /*10133*/ OPC_EmitInteger, MVT::i32, 0,
4172 : /*10136*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4173 : /*10148*/ OPC_EmitInteger, MVT::i32, 1,
4174 : /*10151*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4175 : /*10154*/ OPC_EmitInteger, MVT::i32, 0,
4176 : /*10157*/ OPC_EmitInteger, MVT::i32, 0,
4177 : /*10160*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4178 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 2, 8, 9, 10, 1, 11, 12, 13, 14, 15, 16, 17,
4179 : // Src: (or:i32 (and:i32 (xor:i32 i32:i32:$x, -1:i32), i32:i32:$z), (and:i32 i32:i32:$y, i32:i32:$x)) - Complexity = 17
4180 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
4181 : /*10185*/ /*Scope*/ 105, /*->10291*/
4182 : /*10186*/ OPC_CheckChild0Same, 0,
4183 : /*10188*/ OPC_RecordChild1, // #2 = $y
4184 : /*10189*/ OPC_MoveParent,
4185 : /*10190*/ OPC_CheckType, MVT::i32,
4186 : /*10192*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4187 : /*10194*/ OPC_EmitInteger, MVT::i32, 0,
4188 : /*10197*/ OPC_EmitInteger, MVT::i32, 0,
4189 : /*10200*/ OPC_EmitInteger, MVT::i32, 0,
4190 : /*10203*/ OPC_EmitInteger, MVT::i32, 0,
4191 : /*10206*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4192 : /*10218*/ OPC_EmitInteger, MVT::i32, 0,
4193 : /*10221*/ OPC_EmitInteger, MVT::i32, 0,
4194 : /*10224*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4195 : /*10236*/ OPC_EmitInteger, MVT::i32, 0,
4196 : /*10239*/ OPC_EmitInteger, MVT::i32, 0,
4197 : /*10242*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4198 : /*10254*/ OPC_EmitInteger, MVT::i32, 1,
4199 : /*10257*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4200 : /*10260*/ OPC_EmitInteger, MVT::i32, 0,
4201 : /*10263*/ OPC_EmitInteger, MVT::i32, 0,
4202 : /*10266*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4203 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 2, 8, 9, 10, 1, 11, 12, 13, 14, 15, 16, 17,
4204 : // Src: (or:i32 (and:i32 (xor:i32 i32:i32:$x, -1:i32), i32:i32:$z), (and:i32 i32:i32:$x, i32:i32:$y)) - Complexity = 17
4205 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
4206 : /*10291*/ 0, /*End of Scope*/
4207 : /*10292*/ /*Scope*/ 112|128,4/*624*/, /*->10918*/
4208 : /*10294*/ OPC_RecordChild0, // #0 = $x
4209 : /*10295*/ OPC_Scope, 108|128,3/*492*/, /*->10790*/ // 2 children in Scope
4210 : /*10298*/ OPC_RecordChild1, // #1 = $z
4211 : /*10299*/ OPC_MoveParent,
4212 : /*10300*/ OPC_MoveChild, 1,
4213 : /*10302*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
4214 : /*10305*/ OPC_Scope, 16|128,2/*272*/, /*->10580*/ // 4 children in Scope
4215 : /*10308*/ OPC_RecordChild0, // #2 = $y
4216 : /*10309*/ OPC_MoveChild, 1,
4217 : /*10311*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4218 : /*10314*/ OPC_Scope, 104|128,1/*232*/, /*->10549*/ // 2 children in Scope
4219 : /*10317*/ OPC_CheckChild0Same, 0,
4220 : /*10319*/ OPC_CheckChild1Same, 1,
4221 : /*10321*/ OPC_MoveParent,
4222 : /*10322*/ OPC_MoveParent,
4223 : /*10323*/ OPC_CheckType, MVT::i32,
4224 : /*10325*/ OPC_Scope, 70|128,1/*198*/, /*->10526*/ // 2 children in Scope
4225 : /*10328*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4226 : /*10330*/ OPC_EmitInteger, MVT::i32, 0,
4227 : /*10333*/ OPC_EmitInteger, MVT::i32, 0,
4228 : /*10336*/ OPC_EmitInteger, MVT::i32, 0,
4229 : /*10339*/ OPC_EmitInteger, MVT::i32, 0,
4230 : /*10342*/ OPC_EmitInteger, MVT::i32, 1,
4231 : /*10345*/ OPC_EmitInteger, MVT::i32, 0,
4232 : /*10348*/ OPC_EmitInteger, MVT::i32, 0,
4233 : /*10351*/ OPC_EmitInteger, MVT::i32, 0,
4234 : /*10354*/ OPC_EmitInteger, MVT::i32, 0,
4235 : /*10357*/ OPC_EmitInteger, MVT::i32, 0,
4236 : /*10360*/ OPC_EmitInteger, MVT::i32, 0,
4237 : /*10363*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4238 : /*10375*/ OPC_EmitInteger, MVT::i32, 0,
4239 : /*10378*/ OPC_EmitInteger, MVT::i32, 0,
4240 : /*10381*/ OPC_EmitInteger, MVT::i32, 0,
4241 : /*10384*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4242 : /*10396*/ OPC_EmitInteger, MVT::i32, 1,
4243 : /*10399*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4244 : /*10402*/ OPC_EmitInteger, MVT::i32, 0,
4245 : /*10405*/ OPC_EmitInteger, MVT::i32, 0,
4246 : /*10408*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4247 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 0, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4248 : /*10435*/ OPC_EmitInteger, MVT::i32, 0,
4249 : /*10438*/ OPC_EmitInteger, MVT::i32, 0,
4250 : /*10441*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4251 : /*10453*/ OPC_EmitInteger, MVT::i32, 0,
4252 : /*10456*/ OPC_EmitInteger, MVT::i32, 0,
4253 : /*10459*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4254 : /*10471*/ OPC_EmitInteger, MVT::i32, 0,
4255 : /*10474*/ OPC_EmitInteger, MVT::i32, 0,
4256 : /*10477*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4257 : /*10489*/ OPC_EmitInteger, MVT::i32, 1,
4258 : /*10492*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4259 : /*10495*/ OPC_EmitInteger, MVT::i32, 0,
4260 : /*10498*/ OPC_EmitInteger, MVT::i32, 0,
4261 : /*10501*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4262 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 1, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
4263 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$z), (and:i32 i32:i32:$y, (or:i32 i32:i32:$x, i32:i32:$z))) - Complexity = 12
4264 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4265 : /*10526*/ /*Scope*/ 21, /*->10548*/
4266 : /*10527*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4267 : /*10529*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4268 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
4269 : /*10538*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4270 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 1, 2,
4271 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$z), (and:i32 i32:i32:$y, (or:i32 i32:i32:$x, i32:i32:$z))) - Complexity = 12
4272 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4273 : /*10548*/ 0, /*End of Scope*/
4274 : /*10549*/ /*Scope*/ 29, /*->10579*/
4275 : /*10550*/ OPC_CheckChild0Same, 1,
4276 : /*10552*/ OPC_CheckChild1Same, 0,
4277 : /*10554*/ OPC_MoveParent,
4278 : /*10555*/ OPC_MoveParent,
4279 : /*10556*/ OPC_CheckType, MVT::i32,
4280 : /*10558*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4281 : /*10560*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4282 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
4283 : /*10569*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4284 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 1, 2,
4285 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$z), (and:i32 i32:i32:$y, (or:i32 i32:i32:$z, i32:i32:$x))) - Complexity = 12
4286 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4287 : /*10579*/ 0, /*End of Scope*/
4288 : /*10580*/ /*Scope*/ 69, /*->10650*/
4289 : /*10581*/ OPC_MoveChild, 0,
4290 : /*10583*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4291 : /*10586*/ OPC_Scope, 30, /*->10618*/ // 2 children in Scope
4292 : /*10588*/ OPC_CheckChild0Same, 0,
4293 : /*10590*/ OPC_CheckChild1Same, 1,
4294 : /*10592*/ OPC_MoveParent,
4295 : /*10593*/ OPC_RecordChild1, // #2 = $y
4296 : /*10594*/ OPC_MoveParent,
4297 : /*10595*/ OPC_CheckType, MVT::i32,
4298 : /*10597*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4299 : /*10599*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4300 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
4301 : /*10608*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4302 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 1, 2,
4303 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$z), (and:i32 (or:i32 i32:i32:$x, i32:i32:$z), i32:i32:$y)) - Complexity = 12
4304 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4305 : /*10618*/ /*Scope*/ 30, /*->10649*/
4306 : /*10619*/ OPC_CheckChild0Same, 1,
4307 : /*10621*/ OPC_CheckChild1Same, 0,
4308 : /*10623*/ OPC_MoveParent,
4309 : /*10624*/ OPC_RecordChild1, // #2 = $y
4310 : /*10625*/ OPC_MoveParent,
4311 : /*10626*/ OPC_CheckType, MVT::i32,
4312 : /*10628*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4313 : /*10630*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4314 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
4315 : /*10639*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4316 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 1, 2,
4317 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$z), (and:i32 (or:i32 i32:i32:$z, i32:i32:$x), i32:i32:$y)) - Complexity = 12
4318 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4319 : /*10649*/ 0, /*End of Scope*/
4320 : /*10650*/ /*Scope*/ 68, /*->10719*/
4321 : /*10651*/ OPC_RecordChild0, // #2 = $y
4322 : /*10652*/ OPC_MoveChild, 1,
4323 : /*10654*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4324 : /*10657*/ OPC_Scope, 29, /*->10688*/ // 2 children in Scope
4325 : /*10659*/ OPC_CheckChild0Same, 1,
4326 : /*10661*/ OPC_CheckChild1Same, 0,
4327 : /*10663*/ OPC_MoveParent,
4328 : /*10664*/ OPC_MoveParent,
4329 : /*10665*/ OPC_CheckType, MVT::i32,
4330 : /*10667*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4331 : /*10669*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4332 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
4333 : /*10678*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4334 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 0, 2,
4335 : // Src: (or:i32 (and:i32 i32:i32:$z, i32:i32:$x), (and:i32 i32:i32:$y, (or:i32 i32:i32:$x, i32:i32:$z))) - Complexity = 12
4336 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4337 : /*10688*/ /*Scope*/ 29, /*->10718*/
4338 : /*10689*/ OPC_CheckChild0Same, 0,
4339 : /*10691*/ OPC_CheckChild1Same, 1,
4340 : /*10693*/ OPC_MoveParent,
4341 : /*10694*/ OPC_MoveParent,
4342 : /*10695*/ OPC_CheckType, MVT::i32,
4343 : /*10697*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4344 : /*10699*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4345 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
4346 : /*10708*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4347 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 0, 2,
4348 : // Src: (or:i32 (and:i32 i32:i32:$z, i32:i32:$x), (and:i32 i32:i32:$y, (or:i32 i32:i32:$z, i32:i32:$x))) - Complexity = 12
4349 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4350 : /*10718*/ 0, /*End of Scope*/
4351 : /*10719*/ /*Scope*/ 69, /*->10789*/
4352 : /*10720*/ OPC_MoveChild, 0,
4353 : /*10722*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4354 : /*10725*/ OPC_Scope, 30, /*->10757*/ // 2 children in Scope
4355 : /*10727*/ OPC_CheckChild0Same, 1,
4356 : /*10729*/ OPC_CheckChild1Same, 0,
4357 : /*10731*/ OPC_MoveParent,
4358 : /*10732*/ OPC_RecordChild1, // #2 = $y
4359 : /*10733*/ OPC_MoveParent,
4360 : /*10734*/ OPC_CheckType, MVT::i32,
4361 : /*10736*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4362 : /*10738*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4363 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
4364 : /*10747*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4365 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 0, 2,
4366 : // Src: (or:i32 (and:i32 i32:i32:$z, i32:i32:$x), (and:i32 (or:i32 i32:i32:$x, i32:i32:$z), i32:i32:$y)) - Complexity = 12
4367 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4368 : /*10757*/ /*Scope*/ 30, /*->10788*/
4369 : /*10758*/ OPC_CheckChild0Same, 0,
4370 : /*10760*/ OPC_CheckChild1Same, 1,
4371 : /*10762*/ OPC_MoveParent,
4372 : /*10763*/ OPC_RecordChild1, // #2 = $y
4373 : /*10764*/ OPC_MoveParent,
4374 : /*10765*/ OPC_CheckType, MVT::i32,
4375 : /*10767*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4376 : /*10769*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4377 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
4378 : /*10778*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4379 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 0, 2,
4380 : // Src: (or:i32 (and:i32 i32:i32:$z, i32:i32:$x), (and:i32 (or:i32 i32:i32:$z, i32:i32:$x), i32:i32:$y)) - Complexity = 12
4381 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4382 : /*10788*/ 0, /*End of Scope*/
4383 : /*10789*/ 0, /*End of Scope*/
4384 : /*10790*/ /*Scope*/ 126, /*->10917*/
4385 : /*10791*/ OPC_MoveChild, 1,
4386 : /*10793*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4387 : /*10796*/ OPC_RecordChild0, // #1 = $x
4388 : /*10797*/ OPC_RecordChild1, // #2 = $z
4389 : /*10798*/ OPC_MoveParent,
4390 : /*10799*/ OPC_MoveParent,
4391 : /*10800*/ OPC_MoveChild, 1,
4392 : /*10802*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
4393 : /*10805*/ OPC_Scope, 28, /*->10835*/ // 3 children in Scope
4394 : /*10807*/ OPC_CheckChild0Same, 1,
4395 : /*10809*/ OPC_CheckChild1Same, 2,
4396 : /*10811*/ OPC_MoveParent,
4397 : /*10812*/ OPC_CheckType, MVT::i32,
4398 : /*10814*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4399 : /*10816*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4400 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 0, // Results = #3
4401 : /*10825*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4402 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 2, 0,
4403 : // Src: (or:i32 (and:i32 i32:i32:$y, (or:i32 i32:i32:$x, i32:i32:$z)), (and:i32 i32:i32:$x, i32:i32:$z)) - Complexity = 12
4404 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4405 : /*10835*/ /*Scope*/ 51, /*->10887*/
4406 : /*10836*/ OPC_CheckChild0Same, 2,
4407 : /*10838*/ OPC_CheckChild1Same, 1,
4408 : /*10840*/ OPC_MoveParent,
4409 : /*10841*/ OPC_CheckType, MVT::i32,
4410 : /*10843*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4411 : /*10845*/ OPC_Scope, 19, /*->10866*/ // 2 children in Scope
4412 : /*10847*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4413 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 0, // Results = #3
4414 : /*10856*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4415 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 2, 0,
4416 : // Src: (or:i32 (and:i32 i32:i32:$y, (or:i32 i32:i32:$x, i32:i32:$z)), (and:i32 i32:i32:$z, i32:i32:$x)) - Complexity = 12
4417 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4418 : /*10866*/ /*Scope*/ 19, /*->10886*/
4419 : /*10867*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4420 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 0, // Results = #3
4421 : /*10876*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4422 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 1, 0,
4423 : // Src: (or:i32 (and:i32 i32:i32:$y, (or:i32 i32:i32:$z, i32:i32:$x)), (and:i32 i32:i32:$x, i32:i32:$z)) - Complexity = 12
4424 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4425 : /*10886*/ 0, /*End of Scope*/
4426 : /*10887*/ /*Scope*/ 28, /*->10916*/
4427 : /*10888*/ OPC_CheckChild0Same, 1,
4428 : /*10890*/ OPC_CheckChild1Same, 2,
4429 : /*10892*/ OPC_MoveParent,
4430 : /*10893*/ OPC_CheckType, MVT::i32,
4431 : /*10895*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4432 : /*10897*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4433 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 2, 0, // Results = #3
4434 : /*10906*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4435 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 1, 0,
4436 : // Src: (or:i32 (and:i32 i32:i32:$y, (or:i32 i32:i32:$z, i32:i32:$x)), (and:i32 i32:i32:$z, i32:i32:$x)) - Complexity = 12
4437 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4438 : /*10916*/ 0, /*End of Scope*/
4439 : /*10917*/ 0, /*End of Scope*/
4440 : /*10918*/ /*Scope*/ 127, /*->11046*/
4441 : /*10919*/ OPC_MoveChild, 0,
4442 : /*10921*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4443 : /*10924*/ OPC_RecordChild0, // #0 = $x
4444 : /*10925*/ OPC_RecordChild1, // #1 = $z
4445 : /*10926*/ OPC_MoveParent,
4446 : /*10927*/ OPC_RecordChild1, // #2 = $y
4447 : /*10928*/ OPC_MoveParent,
4448 : /*10929*/ OPC_MoveChild, 1,
4449 : /*10931*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
4450 : /*10934*/ OPC_Scope, 28, /*->10964*/ // 3 children in Scope
4451 : /*10936*/ OPC_CheckChild0Same, 0,
4452 : /*10938*/ OPC_CheckChild1Same, 1,
4453 : /*10940*/ OPC_MoveParent,
4454 : /*10941*/ OPC_CheckType, MVT::i32,
4455 : /*10943*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4456 : /*10945*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4457 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
4458 : /*10954*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4459 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 1, 2,
4460 : // Src: (or:i32 (and:i32 (or:i32 i32:i32:$x, i32:i32:$z), i32:i32:$y), (and:i32 i32:i32:$x, i32:i32:$z)) - Complexity = 12
4461 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4462 : /*10964*/ /*Scope*/ 51, /*->11016*/
4463 : /*10965*/ OPC_CheckChild0Same, 1,
4464 : /*10967*/ OPC_CheckChild1Same, 0,
4465 : /*10969*/ OPC_MoveParent,
4466 : /*10970*/ OPC_CheckType, MVT::i32,
4467 : /*10972*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4468 : /*10974*/ OPC_Scope, 19, /*->10995*/ // 2 children in Scope
4469 : /*10976*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4470 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
4471 : /*10985*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4472 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 1, 2,
4473 : // Src: (or:i32 (and:i32 (or:i32 i32:i32:$x, i32:i32:$z), i32:i32:$y), (and:i32 i32:i32:$z, i32:i32:$x)) - Complexity = 12
4474 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4475 : /*10995*/ /*Scope*/ 19, /*->11015*/
4476 : /*10996*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4477 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
4478 : /*11005*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4479 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 0, 2,
4480 : // Src: (or:i32 (and:i32 (or:i32 i32:i32:$z, i32:i32:$x), i32:i32:$y), (and:i32 i32:i32:$x, i32:i32:$z)) - Complexity = 12
4481 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4482 : /*11015*/ 0, /*End of Scope*/
4483 : /*11016*/ /*Scope*/ 28, /*->11045*/
4484 : /*11017*/ OPC_CheckChild0Same, 0,
4485 : /*11019*/ OPC_CheckChild1Same, 1,
4486 : /*11021*/ OPC_MoveParent,
4487 : /*11022*/ OPC_CheckType, MVT::i32,
4488 : /*11024*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
4489 : /*11026*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e64), 0,
4490 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
4491 : /*11035*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
4492 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 0, 2,
4493 : // Src: (or:i32 (and:i32 (or:i32 i32:i32:$z, i32:i32:$x), i32:i32:$y), (and:i32 i32:i32:$z, i32:i32:$x)) - Complexity = 12
4494 : // Dst: (V_BFI_B32:i32 (V_XOR_B32_e64:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4495 : /*11045*/ 0, /*End of Scope*/
4496 : /*11046*/ /*Scope*/ 93|128,17/*2269*/, /*->13317*/
4497 : /*11048*/ OPC_RecordChild0, // #0 = $x
4498 : /*11049*/ OPC_Scope, 95|128,11/*1503*/, /*->12555*/ // 2 children in Scope
4499 : /*11052*/ OPC_RecordChild1, // #1 = $z
4500 : /*11053*/ OPC_MoveParent,
4501 : /*11054*/ OPC_MoveChild, 1,
4502 : /*11056*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
4503 : /*11059*/ OPC_Scope, 84|128,1/*212*/, /*->11274*/ // 4 children in Scope
4504 : /*11062*/ OPC_RecordChild0, // #2 = $y
4505 : /*11063*/ OPC_MoveChild, 1,
4506 : /*11065*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4507 : /*11068*/ OPC_CheckChild0Same, 1,
4508 : /*11070*/ OPC_CheckChild1Same, 0,
4509 : /*11072*/ OPC_MoveParent,
4510 : /*11073*/ OPC_MoveParent,
4511 : /*11074*/ OPC_CheckType, MVT::i32,
4512 : /*11076*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4513 : /*11078*/ OPC_EmitInteger, MVT::i32, 0,
4514 : /*11081*/ OPC_EmitInteger, MVT::i32, 0,
4515 : /*11084*/ OPC_EmitInteger, MVT::i32, 0,
4516 : /*11087*/ OPC_EmitInteger, MVT::i32, 0,
4517 : /*11090*/ OPC_EmitInteger, MVT::i32, 1,
4518 : /*11093*/ OPC_EmitInteger, MVT::i32, 0,
4519 : /*11096*/ OPC_EmitInteger, MVT::i32, 0,
4520 : /*11099*/ OPC_EmitInteger, MVT::i32, 0,
4521 : /*11102*/ OPC_EmitInteger, MVT::i32, 0,
4522 : /*11105*/ OPC_EmitInteger, MVT::i32, 0,
4523 : /*11108*/ OPC_EmitInteger, MVT::i32, 0,
4524 : /*11111*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4525 : /*11123*/ OPC_EmitInteger, MVT::i32, 0,
4526 : /*11126*/ OPC_EmitInteger, MVT::i32, 0,
4527 : /*11129*/ OPC_EmitInteger, MVT::i32, 0,
4528 : /*11132*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4529 : /*11144*/ OPC_EmitInteger, MVT::i32, 1,
4530 : /*11147*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4531 : /*11150*/ OPC_EmitInteger, MVT::i32, 0,
4532 : /*11153*/ OPC_EmitInteger, MVT::i32, 0,
4533 : /*11156*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4534 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 0, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4535 : /*11183*/ OPC_EmitInteger, MVT::i32, 0,
4536 : /*11186*/ OPC_EmitInteger, MVT::i32, 0,
4537 : /*11189*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4538 : /*11201*/ OPC_EmitInteger, MVT::i32, 0,
4539 : /*11204*/ OPC_EmitInteger, MVT::i32, 0,
4540 : /*11207*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4541 : /*11219*/ OPC_EmitInteger, MVT::i32, 0,
4542 : /*11222*/ OPC_EmitInteger, MVT::i32, 0,
4543 : /*11225*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4544 : /*11237*/ OPC_EmitInteger, MVT::i32, 1,
4545 : /*11240*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4546 : /*11243*/ OPC_EmitInteger, MVT::i32, 0,
4547 : /*11246*/ OPC_EmitInteger, MVT::i32, 0,
4548 : /*11249*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4549 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 1, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
4550 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$z), (and:i32 i32:i32:$y, (or:i32 i32:i32:$z, i32:i32:$x))) - Complexity = 12
4551 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4552 : /*11274*/ /*Scope*/ 41|128,3/*425*/, /*->11701*/
4553 : /*11276*/ OPC_MoveChild, 0,
4554 : /*11278*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4555 : /*11281*/ OPC_Scope, 79|128,1/*207*/, /*->11491*/ // 2 children in Scope
4556 : /*11284*/ OPC_CheckChild0Same, 0,
4557 : /*11286*/ OPC_CheckChild1Same, 1,
4558 : /*11288*/ OPC_MoveParent,
4559 : /*11289*/ OPC_RecordChild1, // #2 = $y
4560 : /*11290*/ OPC_MoveParent,
4561 : /*11291*/ OPC_CheckType, MVT::i32,
4562 : /*11293*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4563 : /*11295*/ OPC_EmitInteger, MVT::i32, 0,
4564 : /*11298*/ OPC_EmitInteger, MVT::i32, 0,
4565 : /*11301*/ OPC_EmitInteger, MVT::i32, 0,
4566 : /*11304*/ OPC_EmitInteger, MVT::i32, 0,
4567 : /*11307*/ OPC_EmitInteger, MVT::i32, 1,
4568 : /*11310*/ OPC_EmitInteger, MVT::i32, 0,
4569 : /*11313*/ OPC_EmitInteger, MVT::i32, 0,
4570 : /*11316*/ OPC_EmitInteger, MVT::i32, 0,
4571 : /*11319*/ OPC_EmitInteger, MVT::i32, 0,
4572 : /*11322*/ OPC_EmitInteger, MVT::i32, 0,
4573 : /*11325*/ OPC_EmitInteger, MVT::i32, 0,
4574 : /*11328*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4575 : /*11340*/ OPC_EmitInteger, MVT::i32, 0,
4576 : /*11343*/ OPC_EmitInteger, MVT::i32, 0,
4577 : /*11346*/ OPC_EmitInteger, MVT::i32, 0,
4578 : /*11349*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4579 : /*11361*/ OPC_EmitInteger, MVT::i32, 1,
4580 : /*11364*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4581 : /*11367*/ OPC_EmitInteger, MVT::i32, 0,
4582 : /*11370*/ OPC_EmitInteger, MVT::i32, 0,
4583 : /*11373*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4584 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 0, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4585 : /*11400*/ OPC_EmitInteger, MVT::i32, 0,
4586 : /*11403*/ OPC_EmitInteger, MVT::i32, 0,
4587 : /*11406*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4588 : /*11418*/ OPC_EmitInteger, MVT::i32, 0,
4589 : /*11421*/ OPC_EmitInteger, MVT::i32, 0,
4590 : /*11424*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4591 : /*11436*/ OPC_EmitInteger, MVT::i32, 0,
4592 : /*11439*/ OPC_EmitInteger, MVT::i32, 0,
4593 : /*11442*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4594 : /*11454*/ OPC_EmitInteger, MVT::i32, 1,
4595 : /*11457*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4596 : /*11460*/ OPC_EmitInteger, MVT::i32, 0,
4597 : /*11463*/ OPC_EmitInteger, MVT::i32, 0,
4598 : /*11466*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4599 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 1, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
4600 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$z), (and:i32 (or:i32 i32:i32:$x, i32:i32:$z), i32:i32:$y)) - Complexity = 12
4601 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4602 : /*11491*/ /*Scope*/ 79|128,1/*207*/, /*->11700*/
4603 : /*11493*/ OPC_CheckChild0Same, 1,
4604 : /*11495*/ OPC_CheckChild1Same, 0,
4605 : /*11497*/ OPC_MoveParent,
4606 : /*11498*/ OPC_RecordChild1, // #2 = $y
4607 : /*11499*/ OPC_MoveParent,
4608 : /*11500*/ OPC_CheckType, MVT::i32,
4609 : /*11502*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4610 : /*11504*/ OPC_EmitInteger, MVT::i32, 0,
4611 : /*11507*/ OPC_EmitInteger, MVT::i32, 0,
4612 : /*11510*/ OPC_EmitInteger, MVT::i32, 0,
4613 : /*11513*/ OPC_EmitInteger, MVT::i32, 0,
4614 : /*11516*/ OPC_EmitInteger, MVT::i32, 1,
4615 : /*11519*/ OPC_EmitInteger, MVT::i32, 0,
4616 : /*11522*/ OPC_EmitInteger, MVT::i32, 0,
4617 : /*11525*/ OPC_EmitInteger, MVT::i32, 0,
4618 : /*11528*/ OPC_EmitInteger, MVT::i32, 0,
4619 : /*11531*/ OPC_EmitInteger, MVT::i32, 0,
4620 : /*11534*/ OPC_EmitInteger, MVT::i32, 0,
4621 : /*11537*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4622 : /*11549*/ OPC_EmitInteger, MVT::i32, 0,
4623 : /*11552*/ OPC_EmitInteger, MVT::i32, 0,
4624 : /*11555*/ OPC_EmitInteger, MVT::i32, 0,
4625 : /*11558*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4626 : /*11570*/ OPC_EmitInteger, MVT::i32, 1,
4627 : /*11573*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4628 : /*11576*/ OPC_EmitInteger, MVT::i32, 0,
4629 : /*11579*/ OPC_EmitInteger, MVT::i32, 0,
4630 : /*11582*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4631 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 0, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4632 : /*11609*/ OPC_EmitInteger, MVT::i32, 0,
4633 : /*11612*/ OPC_EmitInteger, MVT::i32, 0,
4634 : /*11615*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4635 : /*11627*/ OPC_EmitInteger, MVT::i32, 0,
4636 : /*11630*/ OPC_EmitInteger, MVT::i32, 0,
4637 : /*11633*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4638 : /*11645*/ OPC_EmitInteger, MVT::i32, 0,
4639 : /*11648*/ OPC_EmitInteger, MVT::i32, 0,
4640 : /*11651*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4641 : /*11663*/ OPC_EmitInteger, MVT::i32, 1,
4642 : /*11666*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4643 : /*11669*/ OPC_EmitInteger, MVT::i32, 0,
4644 : /*11672*/ OPC_EmitInteger, MVT::i32, 0,
4645 : /*11675*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4646 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 1, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
4647 : // Src: (or:i32 (and:i32 i32:i32:$x, i32:i32:$z), (and:i32 (or:i32 i32:i32:$z, i32:i32:$x), i32:i32:$y)) - Complexity = 12
4648 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4649 : /*11700*/ 0, /*End of Scope*/
4650 : /*11701*/ /*Scope*/ 40|128,3/*424*/, /*->12127*/
4651 : /*11703*/ OPC_RecordChild0, // #2 = $y
4652 : /*11704*/ OPC_MoveChild, 1,
4653 : /*11706*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4654 : /*11709*/ OPC_Scope, 78|128,1/*206*/, /*->11918*/ // 2 children in Scope
4655 : /*11712*/ OPC_CheckChild0Same, 1,
4656 : /*11714*/ OPC_CheckChild1Same, 0,
4657 : /*11716*/ OPC_MoveParent,
4658 : /*11717*/ OPC_MoveParent,
4659 : /*11718*/ OPC_CheckType, MVT::i32,
4660 : /*11720*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4661 : /*11722*/ OPC_EmitInteger, MVT::i32, 0,
4662 : /*11725*/ OPC_EmitInteger, MVT::i32, 0,
4663 : /*11728*/ OPC_EmitInteger, MVT::i32, 0,
4664 : /*11731*/ OPC_EmitInteger, MVT::i32, 0,
4665 : /*11734*/ OPC_EmitInteger, MVT::i32, 1,
4666 : /*11737*/ OPC_EmitInteger, MVT::i32, 0,
4667 : /*11740*/ OPC_EmitInteger, MVT::i32, 0,
4668 : /*11743*/ OPC_EmitInteger, MVT::i32, 0,
4669 : /*11746*/ OPC_EmitInteger, MVT::i32, 0,
4670 : /*11749*/ OPC_EmitInteger, MVT::i32, 0,
4671 : /*11752*/ OPC_EmitInteger, MVT::i32, 0,
4672 : /*11755*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4673 : /*11767*/ OPC_EmitInteger, MVT::i32, 0,
4674 : /*11770*/ OPC_EmitInteger, MVT::i32, 0,
4675 : /*11773*/ OPC_EmitInteger, MVT::i32, 0,
4676 : /*11776*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4677 : /*11788*/ OPC_EmitInteger, MVT::i32, 1,
4678 : /*11791*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4679 : /*11794*/ OPC_EmitInteger, MVT::i32, 0,
4680 : /*11797*/ OPC_EmitInteger, MVT::i32, 0,
4681 : /*11800*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4682 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 1, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4683 : /*11827*/ OPC_EmitInteger, MVT::i32, 0,
4684 : /*11830*/ OPC_EmitInteger, MVT::i32, 0,
4685 : /*11833*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4686 : /*11845*/ OPC_EmitInteger, MVT::i32, 0,
4687 : /*11848*/ OPC_EmitInteger, MVT::i32, 0,
4688 : /*11851*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4689 : /*11863*/ OPC_EmitInteger, MVT::i32, 0,
4690 : /*11866*/ OPC_EmitInteger, MVT::i32, 0,
4691 : /*11869*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4692 : /*11881*/ OPC_EmitInteger, MVT::i32, 1,
4693 : /*11884*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4694 : /*11887*/ OPC_EmitInteger, MVT::i32, 0,
4695 : /*11890*/ OPC_EmitInteger, MVT::i32, 0,
4696 : /*11893*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4697 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 0, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
4698 : // Src: (or:i32 (and:i32 i32:i32:$z, i32:i32:$x), (and:i32 i32:i32:$y, (or:i32 i32:i32:$x, i32:i32:$z))) - Complexity = 12
4699 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4700 : /*11918*/ /*Scope*/ 78|128,1/*206*/, /*->12126*/
4701 : /*11920*/ OPC_CheckChild0Same, 0,
4702 : /*11922*/ OPC_CheckChild1Same, 1,
4703 : /*11924*/ OPC_MoveParent,
4704 : /*11925*/ OPC_MoveParent,
4705 : /*11926*/ OPC_CheckType, MVT::i32,
4706 : /*11928*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4707 : /*11930*/ OPC_EmitInteger, MVT::i32, 0,
4708 : /*11933*/ OPC_EmitInteger, MVT::i32, 0,
4709 : /*11936*/ OPC_EmitInteger, MVT::i32, 0,
4710 : /*11939*/ OPC_EmitInteger, MVT::i32, 0,
4711 : /*11942*/ OPC_EmitInteger, MVT::i32, 1,
4712 : /*11945*/ OPC_EmitInteger, MVT::i32, 0,
4713 : /*11948*/ OPC_EmitInteger, MVT::i32, 0,
4714 : /*11951*/ OPC_EmitInteger, MVT::i32, 0,
4715 : /*11954*/ OPC_EmitInteger, MVT::i32, 0,
4716 : /*11957*/ OPC_EmitInteger, MVT::i32, 0,
4717 : /*11960*/ OPC_EmitInteger, MVT::i32, 0,
4718 : /*11963*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4719 : /*11975*/ OPC_EmitInteger, MVT::i32, 0,
4720 : /*11978*/ OPC_EmitInteger, MVT::i32, 0,
4721 : /*11981*/ OPC_EmitInteger, MVT::i32, 0,
4722 : /*11984*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4723 : /*11996*/ OPC_EmitInteger, MVT::i32, 1,
4724 : /*11999*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4725 : /*12002*/ OPC_EmitInteger, MVT::i32, 0,
4726 : /*12005*/ OPC_EmitInteger, MVT::i32, 0,
4727 : /*12008*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4728 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 1, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4729 : /*12035*/ OPC_EmitInteger, MVT::i32, 0,
4730 : /*12038*/ OPC_EmitInteger, MVT::i32, 0,
4731 : /*12041*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4732 : /*12053*/ OPC_EmitInteger, MVT::i32, 0,
4733 : /*12056*/ OPC_EmitInteger, MVT::i32, 0,
4734 : /*12059*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4735 : /*12071*/ OPC_EmitInteger, MVT::i32, 0,
4736 : /*12074*/ OPC_EmitInteger, MVT::i32, 0,
4737 : /*12077*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4738 : /*12089*/ OPC_EmitInteger, MVT::i32, 1,
4739 : /*12092*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4740 : /*12095*/ OPC_EmitInteger, MVT::i32, 0,
4741 : /*12098*/ OPC_EmitInteger, MVT::i32, 0,
4742 : /*12101*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4743 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 0, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
4744 : // Src: (or:i32 (and:i32 i32:i32:$z, i32:i32:$x), (and:i32 i32:i32:$y, (or:i32 i32:i32:$z, i32:i32:$x))) - Complexity = 12
4745 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4746 : /*12126*/ 0, /*End of Scope*/
4747 : /*12127*/ /*Scope*/ 41|128,3/*425*/, /*->12554*/
4748 : /*12129*/ OPC_MoveChild, 0,
4749 : /*12131*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4750 : /*12134*/ OPC_Scope, 79|128,1/*207*/, /*->12344*/ // 2 children in Scope
4751 : /*12137*/ OPC_CheckChild0Same, 1,
4752 : /*12139*/ OPC_CheckChild1Same, 0,
4753 : /*12141*/ OPC_MoveParent,
4754 : /*12142*/ OPC_RecordChild1, // #2 = $y
4755 : /*12143*/ OPC_MoveParent,
4756 : /*12144*/ OPC_CheckType, MVT::i32,
4757 : /*12146*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4758 : /*12148*/ OPC_EmitInteger, MVT::i32, 0,
4759 : /*12151*/ OPC_EmitInteger, MVT::i32, 0,
4760 : /*12154*/ OPC_EmitInteger, MVT::i32, 0,
4761 : /*12157*/ OPC_EmitInteger, MVT::i32, 0,
4762 : /*12160*/ OPC_EmitInteger, MVT::i32, 1,
4763 : /*12163*/ OPC_EmitInteger, MVT::i32, 0,
4764 : /*12166*/ OPC_EmitInteger, MVT::i32, 0,
4765 : /*12169*/ OPC_EmitInteger, MVT::i32, 0,
4766 : /*12172*/ OPC_EmitInteger, MVT::i32, 0,
4767 : /*12175*/ OPC_EmitInteger, MVT::i32, 0,
4768 : /*12178*/ OPC_EmitInteger, MVT::i32, 0,
4769 : /*12181*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4770 : /*12193*/ OPC_EmitInteger, MVT::i32, 0,
4771 : /*12196*/ OPC_EmitInteger, MVT::i32, 0,
4772 : /*12199*/ OPC_EmitInteger, MVT::i32, 0,
4773 : /*12202*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4774 : /*12214*/ OPC_EmitInteger, MVT::i32, 1,
4775 : /*12217*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4776 : /*12220*/ OPC_EmitInteger, MVT::i32, 0,
4777 : /*12223*/ OPC_EmitInteger, MVT::i32, 0,
4778 : /*12226*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4779 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 1, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4780 : /*12253*/ OPC_EmitInteger, MVT::i32, 0,
4781 : /*12256*/ OPC_EmitInteger, MVT::i32, 0,
4782 : /*12259*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4783 : /*12271*/ OPC_EmitInteger, MVT::i32, 0,
4784 : /*12274*/ OPC_EmitInteger, MVT::i32, 0,
4785 : /*12277*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4786 : /*12289*/ OPC_EmitInteger, MVT::i32, 0,
4787 : /*12292*/ OPC_EmitInteger, MVT::i32, 0,
4788 : /*12295*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4789 : /*12307*/ OPC_EmitInteger, MVT::i32, 1,
4790 : /*12310*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4791 : /*12313*/ OPC_EmitInteger, MVT::i32, 0,
4792 : /*12316*/ OPC_EmitInteger, MVT::i32, 0,
4793 : /*12319*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4794 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 0, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
4795 : // Src: (or:i32 (and:i32 i32:i32:$z, i32:i32:$x), (and:i32 (or:i32 i32:i32:$x, i32:i32:$z), i32:i32:$y)) - Complexity = 12
4796 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4797 : /*12344*/ /*Scope*/ 79|128,1/*207*/, /*->12553*/
4798 : /*12346*/ OPC_CheckChild0Same, 0,
4799 : /*12348*/ OPC_CheckChild1Same, 1,
4800 : /*12350*/ OPC_MoveParent,
4801 : /*12351*/ OPC_RecordChild1, // #2 = $y
4802 : /*12352*/ OPC_MoveParent,
4803 : /*12353*/ OPC_CheckType, MVT::i32,
4804 : /*12355*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4805 : /*12357*/ OPC_EmitInteger, MVT::i32, 0,
4806 : /*12360*/ OPC_EmitInteger, MVT::i32, 0,
4807 : /*12363*/ OPC_EmitInteger, MVT::i32, 0,
4808 : /*12366*/ OPC_EmitInteger, MVT::i32, 0,
4809 : /*12369*/ OPC_EmitInteger, MVT::i32, 1,
4810 : /*12372*/ OPC_EmitInteger, MVT::i32, 0,
4811 : /*12375*/ OPC_EmitInteger, MVT::i32, 0,
4812 : /*12378*/ OPC_EmitInteger, MVT::i32, 0,
4813 : /*12381*/ OPC_EmitInteger, MVT::i32, 0,
4814 : /*12384*/ OPC_EmitInteger, MVT::i32, 0,
4815 : /*12387*/ OPC_EmitInteger, MVT::i32, 0,
4816 : /*12390*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4817 : /*12402*/ OPC_EmitInteger, MVT::i32, 0,
4818 : /*12405*/ OPC_EmitInteger, MVT::i32, 0,
4819 : /*12408*/ OPC_EmitInteger, MVT::i32, 0,
4820 : /*12411*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4821 : /*12423*/ OPC_EmitInteger, MVT::i32, 1,
4822 : /*12426*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4823 : /*12429*/ OPC_EmitInteger, MVT::i32, 0,
4824 : /*12432*/ OPC_EmitInteger, MVT::i32, 0,
4825 : /*12435*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4826 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 1, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4827 : /*12462*/ OPC_EmitInteger, MVT::i32, 0,
4828 : /*12465*/ OPC_EmitInteger, MVT::i32, 0,
4829 : /*12468*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4830 : /*12480*/ OPC_EmitInteger, MVT::i32, 0,
4831 : /*12483*/ OPC_EmitInteger, MVT::i32, 0,
4832 : /*12486*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4833 : /*12498*/ OPC_EmitInteger, MVT::i32, 0,
4834 : /*12501*/ OPC_EmitInteger, MVT::i32, 0,
4835 : /*12504*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4836 : /*12516*/ OPC_EmitInteger, MVT::i32, 1,
4837 : /*12519*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4838 : /*12522*/ OPC_EmitInteger, MVT::i32, 0,
4839 : /*12525*/ OPC_EmitInteger, MVT::i32, 0,
4840 : /*12528*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4841 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 0, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
4842 : // Src: (or:i32 (and:i32 i32:i32:$z, i32:i32:$x), (and:i32 (or:i32 i32:i32:$z, i32:i32:$x), i32:i32:$y)) - Complexity = 12
4843 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4844 : /*12553*/ 0, /*End of Scope*/
4845 : /*12554*/ 0, /*End of Scope*/
4846 : /*12555*/ /*Scope*/ 119|128,5/*759*/, /*->13316*/
4847 : /*12557*/ OPC_MoveChild, 1,
4848 : /*12559*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4849 : /*12562*/ OPC_RecordChild0, // #1 = $x
4850 : /*12563*/ OPC_RecordChild1, // #2 = $z
4851 : /*12564*/ OPC_MoveParent,
4852 : /*12565*/ OPC_MoveParent,
4853 : /*12566*/ OPC_MoveChild, 1,
4854 : /*12568*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
4855 : /*12571*/ OPC_Scope, 77|128,1/*205*/, /*->12779*/ // 3 children in Scope
4856 : /*12574*/ OPC_CheckChild0Same, 1,
4857 : /*12576*/ OPC_CheckChild1Same, 2,
4858 : /*12578*/ OPC_MoveParent,
4859 : /*12579*/ OPC_CheckType, MVT::i32,
4860 : /*12581*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4861 : /*12583*/ OPC_EmitInteger, MVT::i32, 0,
4862 : /*12586*/ OPC_EmitInteger, MVT::i32, 0,
4863 : /*12589*/ OPC_EmitInteger, MVT::i32, 0,
4864 : /*12592*/ OPC_EmitInteger, MVT::i32, 0,
4865 : /*12595*/ OPC_EmitInteger, MVT::i32, 1,
4866 : /*12598*/ OPC_EmitInteger, MVT::i32, 0,
4867 : /*12601*/ OPC_EmitInteger, MVT::i32, 0,
4868 : /*12604*/ OPC_EmitInteger, MVT::i32, 0,
4869 : /*12607*/ OPC_EmitInteger, MVT::i32, 0,
4870 : /*12610*/ OPC_EmitInteger, MVT::i32, 0,
4871 : /*12613*/ OPC_EmitInteger, MVT::i32, 0,
4872 : /*12616*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4873 : /*12628*/ OPC_EmitInteger, MVT::i32, 0,
4874 : /*12631*/ OPC_EmitInteger, MVT::i32, 0,
4875 : /*12634*/ OPC_EmitInteger, MVT::i32, 0,
4876 : /*12637*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4877 : /*12649*/ OPC_EmitInteger, MVT::i32, 1,
4878 : /*12652*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4879 : /*12655*/ OPC_EmitInteger, MVT::i32, 0,
4880 : /*12658*/ OPC_EmitInteger, MVT::i32, 0,
4881 : /*12661*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4882 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 1, 11, 12, 13, 14, 0, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4883 : /*12688*/ OPC_EmitInteger, MVT::i32, 0,
4884 : /*12691*/ OPC_EmitInteger, MVT::i32, 0,
4885 : /*12694*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4886 : /*12706*/ OPC_EmitInteger, MVT::i32, 0,
4887 : /*12709*/ OPC_EmitInteger, MVT::i32, 0,
4888 : /*12712*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4889 : /*12724*/ OPC_EmitInteger, MVT::i32, 0,
4890 : /*12727*/ OPC_EmitInteger, MVT::i32, 0,
4891 : /*12730*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4892 : /*12742*/ OPC_EmitInteger, MVT::i32, 1,
4893 : /*12745*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4894 : /*12748*/ OPC_EmitInteger, MVT::i32, 0,
4895 : /*12751*/ OPC_EmitInteger, MVT::i32, 0,
4896 : /*12754*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4897 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 2, 27, 28, 29, 0, 30, 31, 32, 33, 34, 35, 36,
4898 : // Src: (or:i32 (and:i32 i32:i32:$y, (or:i32 i32:i32:$x, i32:i32:$z)), (and:i32 i32:i32:$x, i32:i32:$z)) - Complexity = 12
4899 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4900 : /*12779*/ /*Scope*/ 71|128,2/*327*/, /*->13108*/
4901 : /*12781*/ OPC_CheckChild0Same, 2,
4902 : /*12783*/ OPC_CheckChild1Same, 1,
4903 : /*12785*/ OPC_MoveParent,
4904 : /*12786*/ OPC_CheckType, MVT::i32,
4905 : /*12788*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4906 : /*12790*/ OPC_EmitInteger, MVT::i32, 0,
4907 : /*12793*/ OPC_EmitInteger, MVT::i32, 0,
4908 : /*12796*/ OPC_EmitInteger, MVT::i32, 0,
4909 : /*12799*/ OPC_EmitInteger, MVT::i32, 0,
4910 : /*12802*/ OPC_EmitInteger, MVT::i32, 1,
4911 : /*12805*/ OPC_EmitInteger, MVT::i32, 0,
4912 : /*12808*/ OPC_EmitInteger, MVT::i32, 0,
4913 : /*12811*/ OPC_EmitInteger, MVT::i32, 0,
4914 : /*12814*/ OPC_EmitInteger, MVT::i32, 0,
4915 : /*12817*/ OPC_EmitInteger, MVT::i32, 0,
4916 : /*12820*/ OPC_EmitInteger, MVT::i32, 0,
4917 : /*12823*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4918 : /*12835*/ OPC_EmitInteger, MVT::i32, 0,
4919 : /*12838*/ OPC_EmitInteger, MVT::i32, 0,
4920 : /*12841*/ OPC_EmitInteger, MVT::i32, 0,
4921 : /*12844*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4922 : /*12856*/ OPC_EmitInteger, MVT::i32, 1,
4923 : /*12859*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4924 : /*12862*/ OPC_EmitInteger, MVT::i32, 0,
4925 : /*12865*/ OPC_EmitInteger, MVT::i32, 0,
4926 : /*12868*/ OPC_Scope, 118, /*->12988*/ // 2 children in Scope
4927 : /*12870*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4928 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 1, 11, 12, 13, 14, 0, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4929 : /*12897*/ OPC_EmitInteger, MVT::i32, 0,
4930 : /*12900*/ OPC_EmitInteger, MVT::i32, 0,
4931 : /*12903*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4932 : /*12915*/ OPC_EmitInteger, MVT::i32, 0,
4933 : /*12918*/ OPC_EmitInteger, MVT::i32, 0,
4934 : /*12921*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4935 : /*12933*/ OPC_EmitInteger, MVT::i32, 0,
4936 : /*12936*/ OPC_EmitInteger, MVT::i32, 0,
4937 : /*12939*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4938 : /*12951*/ OPC_EmitInteger, MVT::i32, 1,
4939 : /*12954*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4940 : /*12957*/ OPC_EmitInteger, MVT::i32, 0,
4941 : /*12960*/ OPC_EmitInteger, MVT::i32, 0,
4942 : /*12963*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4943 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 2, 27, 28, 29, 0, 30, 31, 32, 33, 34, 35, 36,
4944 : // Src: (or:i32 (and:i32 i32:i32:$y, (or:i32 i32:i32:$x, i32:i32:$z)), (and:i32 i32:i32:$z, i32:i32:$x)) - Complexity = 12
4945 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4946 : /*12988*/ /*Scope*/ 118, /*->13107*/
4947 : /*12989*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4948 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 2, 11, 12, 13, 14, 0, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4949 : /*13016*/ OPC_EmitInteger, MVT::i32, 0,
4950 : /*13019*/ OPC_EmitInteger, MVT::i32, 0,
4951 : /*13022*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4952 : /*13034*/ OPC_EmitInteger, MVT::i32, 0,
4953 : /*13037*/ OPC_EmitInteger, MVT::i32, 0,
4954 : /*13040*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4955 : /*13052*/ OPC_EmitInteger, MVT::i32, 0,
4956 : /*13055*/ OPC_EmitInteger, MVT::i32, 0,
4957 : /*13058*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4958 : /*13070*/ OPC_EmitInteger, MVT::i32, 1,
4959 : /*13073*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4960 : /*13076*/ OPC_EmitInteger, MVT::i32, 0,
4961 : /*13079*/ OPC_EmitInteger, MVT::i32, 0,
4962 : /*13082*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
4963 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 1, 27, 28, 29, 0, 30, 31, 32, 33, 34, 35, 36,
4964 : // Src: (or:i32 (and:i32 i32:i32:$y, (or:i32 i32:i32:$z, i32:i32:$x)), (and:i32 i32:i32:$x, i32:i32:$z)) - Complexity = 12
4965 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
4966 : /*13107*/ 0, /*End of Scope*/
4967 : /*13108*/ /*Scope*/ 77|128,1/*205*/, /*->13315*/
4968 : /*13110*/ OPC_CheckChild0Same, 1,
4969 : /*13112*/ OPC_CheckChild1Same, 2,
4970 : /*13114*/ OPC_MoveParent,
4971 : /*13115*/ OPC_CheckType, MVT::i32,
4972 : /*13117*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
4973 : /*13119*/ OPC_EmitInteger, MVT::i32, 0,
4974 : /*13122*/ OPC_EmitInteger, MVT::i32, 0,
4975 : /*13125*/ OPC_EmitInteger, MVT::i32, 0,
4976 : /*13128*/ OPC_EmitInteger, MVT::i32, 0,
4977 : /*13131*/ OPC_EmitInteger, MVT::i32, 1,
4978 : /*13134*/ OPC_EmitInteger, MVT::i32, 0,
4979 : /*13137*/ OPC_EmitInteger, MVT::i32, 0,
4980 : /*13140*/ OPC_EmitInteger, MVT::i32, 0,
4981 : /*13143*/ OPC_EmitInteger, MVT::i32, 0,
4982 : /*13146*/ OPC_EmitInteger, MVT::i32, 0,
4983 : /*13149*/ OPC_EmitInteger, MVT::i32, 0,
4984 : /*13152*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4985 : /*13164*/ OPC_EmitInteger, MVT::i32, 0,
4986 : /*13167*/ OPC_EmitInteger, MVT::i32, 0,
4987 : /*13170*/ OPC_EmitInteger, MVT::i32, 0,
4988 : /*13173*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4989 : /*13185*/ OPC_EmitInteger, MVT::i32, 1,
4990 : /*13188*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
4991 : /*13191*/ OPC_EmitInteger, MVT::i32, 0,
4992 : /*13194*/ OPC_EmitInteger, MVT::i32, 0,
4993 : /*13197*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
4994 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 2, 11, 12, 13, 14, 0, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
4995 : /*13224*/ OPC_EmitInteger, MVT::i32, 0,
4996 : /*13227*/ OPC_EmitInteger, MVT::i32, 0,
4997 : /*13230*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
4998 : /*13242*/ OPC_EmitInteger, MVT::i32, 0,
4999 : /*13245*/ OPC_EmitInteger, MVT::i32, 0,
5000 : /*13248*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5001 : /*13260*/ OPC_EmitInteger, MVT::i32, 0,
5002 : /*13263*/ OPC_EmitInteger, MVT::i32, 0,
5003 : /*13266*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5004 : /*13278*/ OPC_EmitInteger, MVT::i32, 1,
5005 : /*13281*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5006 : /*13284*/ OPC_EmitInteger, MVT::i32, 0,
5007 : /*13287*/ OPC_EmitInteger, MVT::i32, 0,
5008 : /*13290*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
5009 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 1, 27, 28, 29, 0, 30, 31, 32, 33, 34, 35, 36,
5010 : // Src: (or:i32 (and:i32 i32:i32:$y, (or:i32 i32:i32:$z, i32:i32:$x)), (and:i32 i32:i32:$z, i32:i32:$x)) - Complexity = 12
5011 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
5012 : /*13315*/ 0, /*End of Scope*/
5013 : /*13316*/ 0, /*End of Scope*/
5014 : /*13317*/ /*Scope*/ 120|128,5/*760*/, /*->14079*/
5015 : /*13319*/ OPC_MoveChild, 0,
5016 : /*13321*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
5017 : /*13324*/ OPC_RecordChild0, // #0 = $x
5018 : /*13325*/ OPC_RecordChild1, // #1 = $z
5019 : /*13326*/ OPC_MoveParent,
5020 : /*13327*/ OPC_RecordChild1, // #2 = $y
5021 : /*13328*/ OPC_MoveParent,
5022 : /*13329*/ OPC_MoveChild, 1,
5023 : /*13331*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
5024 : /*13334*/ OPC_Scope, 77|128,1/*205*/, /*->13542*/ // 3 children in Scope
5025 : /*13337*/ OPC_CheckChild0Same, 0,
5026 : /*13339*/ OPC_CheckChild1Same, 1,
5027 : /*13341*/ OPC_MoveParent,
5028 : /*13342*/ OPC_CheckType, MVT::i32,
5029 : /*13344*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
5030 : /*13346*/ OPC_EmitInteger, MVT::i32, 0,
5031 : /*13349*/ OPC_EmitInteger, MVT::i32, 0,
5032 : /*13352*/ OPC_EmitInteger, MVT::i32, 0,
5033 : /*13355*/ OPC_EmitInteger, MVT::i32, 0,
5034 : /*13358*/ OPC_EmitInteger, MVT::i32, 1,
5035 : /*13361*/ OPC_EmitInteger, MVT::i32, 0,
5036 : /*13364*/ OPC_EmitInteger, MVT::i32, 0,
5037 : /*13367*/ OPC_EmitInteger, MVT::i32, 0,
5038 : /*13370*/ OPC_EmitInteger, MVT::i32, 0,
5039 : /*13373*/ OPC_EmitInteger, MVT::i32, 0,
5040 : /*13376*/ OPC_EmitInteger, MVT::i32, 0,
5041 : /*13379*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5042 : /*13391*/ OPC_EmitInteger, MVT::i32, 0,
5043 : /*13394*/ OPC_EmitInteger, MVT::i32, 0,
5044 : /*13397*/ OPC_EmitInteger, MVT::i32, 0,
5045 : /*13400*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5046 : /*13412*/ OPC_EmitInteger, MVT::i32, 1,
5047 : /*13415*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5048 : /*13418*/ OPC_EmitInteger, MVT::i32, 0,
5049 : /*13421*/ OPC_EmitInteger, MVT::i32, 0,
5050 : /*13424*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
5051 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 0, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
5052 : /*13451*/ OPC_EmitInteger, MVT::i32, 0,
5053 : /*13454*/ OPC_EmitInteger, MVT::i32, 0,
5054 : /*13457*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5055 : /*13469*/ OPC_EmitInteger, MVT::i32, 0,
5056 : /*13472*/ OPC_EmitInteger, MVT::i32, 0,
5057 : /*13475*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5058 : /*13487*/ OPC_EmitInteger, MVT::i32, 0,
5059 : /*13490*/ OPC_EmitInteger, MVT::i32, 0,
5060 : /*13493*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5061 : /*13505*/ OPC_EmitInteger, MVT::i32, 1,
5062 : /*13508*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5063 : /*13511*/ OPC_EmitInteger, MVT::i32, 0,
5064 : /*13514*/ OPC_EmitInteger, MVT::i32, 0,
5065 : /*13517*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
5066 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 1, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
5067 : // Src: (or:i32 (and:i32 (or:i32 i32:i32:$x, i32:i32:$z), i32:i32:$y), (and:i32 i32:i32:$x, i32:i32:$z)) - Complexity = 12
5068 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
5069 : /*13542*/ /*Scope*/ 71|128,2/*327*/, /*->13871*/
5070 : /*13544*/ OPC_CheckChild0Same, 1,
5071 : /*13546*/ OPC_CheckChild1Same, 0,
5072 : /*13548*/ OPC_MoveParent,
5073 : /*13549*/ OPC_CheckType, MVT::i32,
5074 : /*13551*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
5075 : /*13553*/ OPC_EmitInteger, MVT::i32, 0,
5076 : /*13556*/ OPC_EmitInteger, MVT::i32, 0,
5077 : /*13559*/ OPC_EmitInteger, MVT::i32, 0,
5078 : /*13562*/ OPC_EmitInteger, MVT::i32, 0,
5079 : /*13565*/ OPC_EmitInteger, MVT::i32, 1,
5080 : /*13568*/ OPC_EmitInteger, MVT::i32, 0,
5081 : /*13571*/ OPC_EmitInteger, MVT::i32, 0,
5082 : /*13574*/ OPC_EmitInteger, MVT::i32, 0,
5083 : /*13577*/ OPC_EmitInteger, MVT::i32, 0,
5084 : /*13580*/ OPC_EmitInteger, MVT::i32, 0,
5085 : /*13583*/ OPC_EmitInteger, MVT::i32, 0,
5086 : /*13586*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5087 : /*13598*/ OPC_EmitInteger, MVT::i32, 0,
5088 : /*13601*/ OPC_EmitInteger, MVT::i32, 0,
5089 : /*13604*/ OPC_EmitInteger, MVT::i32, 0,
5090 : /*13607*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5091 : /*13619*/ OPC_EmitInteger, MVT::i32, 1,
5092 : /*13622*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5093 : /*13625*/ OPC_EmitInteger, MVT::i32, 0,
5094 : /*13628*/ OPC_EmitInteger, MVT::i32, 0,
5095 : /*13631*/ OPC_Scope, 118, /*->13751*/ // 2 children in Scope
5096 : /*13633*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
5097 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 0, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
5098 : /*13660*/ OPC_EmitInteger, MVT::i32, 0,
5099 : /*13663*/ OPC_EmitInteger, MVT::i32, 0,
5100 : /*13666*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5101 : /*13678*/ OPC_EmitInteger, MVT::i32, 0,
5102 : /*13681*/ OPC_EmitInteger, MVT::i32, 0,
5103 : /*13684*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5104 : /*13696*/ OPC_EmitInteger, MVT::i32, 0,
5105 : /*13699*/ OPC_EmitInteger, MVT::i32, 0,
5106 : /*13702*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5107 : /*13714*/ OPC_EmitInteger, MVT::i32, 1,
5108 : /*13717*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5109 : /*13720*/ OPC_EmitInteger, MVT::i32, 0,
5110 : /*13723*/ OPC_EmitInteger, MVT::i32, 0,
5111 : /*13726*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
5112 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 1, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
5113 : // Src: (or:i32 (and:i32 (or:i32 i32:i32:$x, i32:i32:$z), i32:i32:$y), (and:i32 i32:i32:$z, i32:i32:$x)) - Complexity = 12
5114 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
5115 : /*13751*/ /*Scope*/ 118, /*->13870*/
5116 : /*13752*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
5117 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 1, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
5118 : /*13779*/ OPC_EmitInteger, MVT::i32, 0,
5119 : /*13782*/ OPC_EmitInteger, MVT::i32, 0,
5120 : /*13785*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5121 : /*13797*/ OPC_EmitInteger, MVT::i32, 0,
5122 : /*13800*/ OPC_EmitInteger, MVT::i32, 0,
5123 : /*13803*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5124 : /*13815*/ OPC_EmitInteger, MVT::i32, 0,
5125 : /*13818*/ OPC_EmitInteger, MVT::i32, 0,
5126 : /*13821*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5127 : /*13833*/ OPC_EmitInteger, MVT::i32, 1,
5128 : /*13836*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5129 : /*13839*/ OPC_EmitInteger, MVT::i32, 0,
5130 : /*13842*/ OPC_EmitInteger, MVT::i32, 0,
5131 : /*13845*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
5132 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 0, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
5133 : // Src: (or:i32 (and:i32 (or:i32 i32:i32:$z, i32:i32:$x), i32:i32:$y), (and:i32 i32:i32:$x, i32:i32:$z)) - Complexity = 12
5134 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
5135 : /*13870*/ 0, /*End of Scope*/
5136 : /*13871*/ /*Scope*/ 77|128,1/*205*/, /*->14078*/
5137 : /*13873*/ OPC_CheckChild0Same, 0,
5138 : /*13875*/ OPC_CheckChild1Same, 1,
5139 : /*13877*/ OPC_MoveParent,
5140 : /*13878*/ OPC_CheckType, MVT::i32,
5141 : /*13880*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
5142 : /*13882*/ OPC_EmitInteger, MVT::i32, 0,
5143 : /*13885*/ OPC_EmitInteger, MVT::i32, 0,
5144 : /*13888*/ OPC_EmitInteger, MVT::i32, 0,
5145 : /*13891*/ OPC_EmitInteger, MVT::i32, 0,
5146 : /*13894*/ OPC_EmitInteger, MVT::i32, 1,
5147 : /*13897*/ OPC_EmitInteger, MVT::i32, 0,
5148 : /*13900*/ OPC_EmitInteger, MVT::i32, 0,
5149 : /*13903*/ OPC_EmitInteger, MVT::i32, 0,
5150 : /*13906*/ OPC_EmitInteger, MVT::i32, 0,
5151 : /*13909*/ OPC_EmitInteger, MVT::i32, 0,
5152 : /*13912*/ OPC_EmitInteger, MVT::i32, 0,
5153 : /*13915*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5154 : /*13927*/ OPC_EmitInteger, MVT::i32, 0,
5155 : /*13930*/ OPC_EmitInteger, MVT::i32, 0,
5156 : /*13933*/ OPC_EmitInteger, MVT::i32, 0,
5157 : /*13936*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5158 : /*13948*/ OPC_EmitInteger, MVT::i32, 1,
5159 : /*13951*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5160 : /*13954*/ OPC_EmitInteger, MVT::i32, 0,
5161 : /*13957*/ OPC_EmitInteger, MVT::i32, 0,
5162 : /*13960*/ OPC_EmitNode, TARGET_VAL(AMDGPU::XOR_INT), 0,
5163 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 1, 11, 12, 13, 14, 2, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
5164 : /*13987*/ OPC_EmitInteger, MVT::i32, 0,
5165 : /*13990*/ OPC_EmitInteger, MVT::i32, 0,
5166 : /*13993*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5167 : /*14005*/ OPC_EmitInteger, MVT::i32, 0,
5168 : /*14008*/ OPC_EmitInteger, MVT::i32, 0,
5169 : /*14011*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5170 : /*14023*/ OPC_EmitInteger, MVT::i32, 0,
5171 : /*14026*/ OPC_EmitInteger, MVT::i32, 0,
5172 : /*14029*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5173 : /*14041*/ OPC_EmitInteger, MVT::i32, 1,
5174 : /*14044*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5175 : /*14047*/ OPC_EmitInteger, MVT::i32, 0,
5176 : /*14050*/ OPC_EmitInteger, MVT::i32, 0,
5177 : /*14053*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
5178 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 23, 24, 25, 26, 0, 27, 28, 29, 2, 30, 31, 32, 33, 34, 35, 36,
5179 : // Src: (or:i32 (and:i32 (or:i32 i32:i32:$z, i32:i32:$x), i32:i32:$y), (and:i32 i32:i32:$z, i32:i32:$x)) - Complexity = 12
5180 : // Dst: (BFI_INT_eg:i32 (XOR_INT:i32 i32:i32:$x, i32:i32:$y), i32:i32:$z, i32:i32:$y)
5181 : /*14078*/ 0, /*End of Scope*/
5182 : /*14079*/ 0, /*End of Scope*/
5183 : /*14080*/ /*Scope*/ 20|128,1/*148*/, /*->14230*/
5184 : /*14082*/ OPC_RecordChild0, // #0 = $src0
5185 : /*14083*/ OPC_RecordChild1, // #1 = $src1
5186 : /*14084*/ OPC_SwitchType /*3 cases */, 116, MVT::i32,// ->14203
5187 : /*14087*/ OPC_Scope, 101, /*->14190*/ // 2 children in Scope
5188 : /*14089*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5189 : /*14091*/ OPC_EmitInteger, MVT::i32, 0,
5190 : /*14094*/ OPC_EmitInteger, MVT::i32, 0,
5191 : /*14097*/ OPC_EmitInteger, MVT::i32, 1,
5192 : /*14100*/ OPC_EmitInteger, MVT::i32, 0,
5193 : /*14103*/ OPC_EmitInteger, MVT::i32, 0,
5194 : /*14106*/ OPC_EmitInteger, MVT::i32, 0,
5195 : /*14109*/ OPC_EmitInteger, MVT::i32, 0,
5196 : /*14112*/ OPC_EmitInteger, MVT::i32, 0,
5197 : /*14115*/ OPC_EmitInteger, MVT::i32, 0,
5198 : /*14118*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5199 : /*14130*/ OPC_EmitInteger, MVT::i32, 0,
5200 : /*14133*/ OPC_EmitInteger, MVT::i32, 0,
5201 : /*14136*/ OPC_EmitInteger, MVT::i32, 0,
5202 : /*14139*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5203 : /*14151*/ OPC_EmitInteger, MVT::i32, 1,
5204 : /*14154*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5205 : /*14157*/ OPC_EmitInteger, MVT::i32, 0,
5206 : /*14160*/ OPC_EmitInteger, MVT::i32, 0,
5207 : /*14163*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::OR_INT), 0,
5208 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5209 : // Src: (or:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
5210 : // Dst: (OR_INT:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
5211 : /*14190*/ /*Scope*/ 11, /*->14202*/
5212 : /*14191*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
5213 : /*14193*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_OR_B32), 0,
5214 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
5215 : // Src: (or:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
5216 : // Dst: (S_OR_B32:i32 i32:i32:$src0, i32:i32:$src1)
5217 : /*14202*/ 0, /*End of Scope*/
5218 : /*14203*/ /*SwitchType*/ 11, MVT::i64,// ->14216
5219 : /*14205*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
5220 : /*14207*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_OR_B64), 0,
5221 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 0, 1,
5222 : // Src: (or:i64 i64:i64:$src0, i64:i64:$src1) - Complexity = 3
5223 : // Dst: (S_OR_B64:i64 i64:i64:$src0, i64:i64:$src1)
5224 : /*14216*/ /*SwitchType*/ 11, MVT::i1,// ->14229
5225 : /*14218*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
5226 : /*14220*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_OR_B64), 0,
5227 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
5228 : // Src: (or:i1 i1:i1:$src0, i1:i1:$src1) - Complexity = 3
5229 : // Dst: (S_OR_B64:i1 ?:i1:$src0, ?:i1:$src1)
5230 : /*14229*/ 0, // EndSwitchType
5231 : /*14230*/ 0, /*End of Scope*/
5232 : /*14231*/ /*SwitchOpcode*/ 85|128,5/*725*/, TARGET_VAL(ISD::ADD),// ->14960
5233 : /*14235*/ OPC_Scope, 59|128,2/*315*/, /*->14553*/ // 2 children in Scope
5234 : /*14238*/ OPC_MoveChild, 0,
5235 : /*14240*/ OPC_SwitchOpcode /*4 cases */, 41, TARGET_VAL(ISD::SHL),// ->14285
5236 : /*14244*/ OPC_CheckChild0Integer, 1,
5237 : /*14246*/ OPC_RecordChild1, // #0 = $a
5238 : /*14247*/ OPC_CheckChild1Type, MVT::i32,
5239 : /*14249*/ OPC_MoveParent,
5240 : /*14250*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5241 : /*14261*/ OPC_CheckType, MVT::i32,
5242 : /*14263*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
5243 : /*14265*/ OPC_EmitInteger, MVT::i32, 0,
5244 : /*14268*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
5245 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1, // Results = #2
5246 : /*14276*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BFM_B32), 0,
5247 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2,
5248 : // Src: (add:i32 (shl:i32 1:i32, i32:i32:$a), -1:i32) - Complexity = 16
5249 : // Dst: (S_BFM_B32:i32 ?:i32:$a, (S_MOV_B32:i32 0:i32))
5250 : /*14285*/ /*SwitchOpcode*/ 121, TARGET_VAL(AMDGPUISD::MUL_U24),// ->14409
5251 : /*14288*/ OPC_RecordChild0, // #0 = $src0
5252 : /*14289*/ OPC_RecordChild1, // #1 = $src1
5253 : /*14290*/ OPC_MoveParent,
5254 : /*14291*/ OPC_RecordChild1, // #2 = $src2
5255 : /*14292*/ OPC_CheckType, MVT::i32,
5256 : /*14294*/ OPC_Scope, 99, /*->14395*/ // 2 children in Scope
5257 : /*14296*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
5258 : /*14298*/ OPC_EmitInteger, MVT::i32, 0,
5259 : /*14301*/ OPC_EmitInteger, MVT::i32, 0,
5260 : /*14304*/ OPC_EmitInteger, MVT::i32, 0,
5261 : /*14307*/ OPC_EmitInteger, MVT::i32, 0,
5262 : /*14310*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5263 : /*14322*/ OPC_EmitInteger, MVT::i32, 0,
5264 : /*14325*/ OPC_EmitInteger, MVT::i32, 0,
5265 : /*14328*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5266 : /*14340*/ OPC_EmitInteger, MVT::i32, 0,
5267 : /*14343*/ OPC_EmitInteger, MVT::i32, 0,
5268 : /*14346*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5269 : /*14358*/ OPC_EmitInteger, MVT::i32, 1,
5270 : /*14361*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5271 : /*14364*/ OPC_EmitInteger, MVT::i32, 0,
5272 : /*14367*/ OPC_EmitInteger, MVT::i32, 0,
5273 : /*14370*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULADD_UINT24_eg), 0,
5274 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
5275 : // Src: (add:i32 (AMDGPUmul_u24:i32 i32:i32:$src0, i32:i32:$src1), i32:i32:$src2) - Complexity = 6
5276 : // Dst: (MULADD_UINT24_eg:i32 ?:i32:$src0, ?:i32:$src1, ?:i32:$src2)
5277 : /*14395*/ /*Scope*/ 12, /*->14408*/
5278 : /*14396*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
5279 : /*14398*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAD_U32_U24), 0,
5280 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
5281 : // Src: (add:i32 (AMDGPUmul_u24:i32 i32:i32:$src0, i32:i32:$src1), i32:i32:$src2) - Complexity = 6
5282 : // Dst: (V_MAD_U32_U24:i32 ?:i32:$src0, ?:i32:$src1, ?:i32:$src2)
5283 : /*14408*/ 0, /*End of Scope*/
5284 : /*14409*/ /*SwitchOpcode*/ 121, TARGET_VAL(AMDGPUISD::MUL_I24),// ->14533
5285 : /*14412*/ OPC_RecordChild0, // #0 = $src0
5286 : /*14413*/ OPC_RecordChild1, // #1 = $src1
5287 : /*14414*/ OPC_MoveParent,
5288 : /*14415*/ OPC_RecordChild1, // #2 = $src2
5289 : /*14416*/ OPC_CheckType, MVT::i32,
5290 : /*14418*/ OPC_Scope, 99, /*->14519*/ // 2 children in Scope
5291 : /*14420*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
5292 : /*14422*/ OPC_EmitInteger, MVT::i32, 0,
5293 : /*14425*/ OPC_EmitInteger, MVT::i32, 0,
5294 : /*14428*/ OPC_EmitInteger, MVT::i32, 0,
5295 : /*14431*/ OPC_EmitInteger, MVT::i32, 0,
5296 : /*14434*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5297 : /*14446*/ OPC_EmitInteger, MVT::i32, 0,
5298 : /*14449*/ OPC_EmitInteger, MVT::i32, 0,
5299 : /*14452*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5300 : /*14464*/ OPC_EmitInteger, MVT::i32, 0,
5301 : /*14467*/ OPC_EmitInteger, MVT::i32, 0,
5302 : /*14470*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5303 : /*14482*/ OPC_EmitInteger, MVT::i32, 1,
5304 : /*14485*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5305 : /*14488*/ OPC_EmitInteger, MVT::i32, 0,
5306 : /*14491*/ OPC_EmitInteger, MVT::i32, 0,
5307 : /*14494*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULADD_INT24_cm), 0,
5308 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
5309 : // Src: (add:i32 (AMDGPUmul_i24:i32 i32:i32:$src0, i32:i32:$src1), i32:i32:$src2) - Complexity = 6
5310 : // Dst: (MULADD_INT24_cm:i32 ?:i32:$src0, ?:i32:$src1, ?:i32:$src2)
5311 : /*14519*/ /*Scope*/ 12, /*->14532*/
5312 : /*14520*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
5313 : /*14522*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAD_I32_I24), 0,
5314 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
5315 : // Src: (add:i32 (AMDGPUmul_i24:i32 i32:i32:$src0, i32:i32:$src1), i32:i32:$src2) - Complexity = 6
5316 : // Dst: (V_MAD_I32_I24:i32 ?:i32:$src0, ?:i32:$src1, ?:i32:$src2)
5317 : /*14532*/ 0, /*End of Scope*/
5318 : /*14533*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::CTPOP),// ->14552
5319 : /*14536*/ OPC_RecordChild0, // #0 = $popcnt
5320 : /*14537*/ OPC_MoveParent,
5321 : /*14538*/ OPC_RecordChild1, // #1 = $val
5322 : /*14539*/ OPC_CheckType, MVT::i32,
5323 : /*14541*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
5324 : /*14543*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BCNT_U32_B32_e64), 0,
5325 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
5326 : // Src: (add:i32 (ctpop:i32 i32:i32:$popcnt), i32:i32:$val) - Complexity = 6
5327 : // Dst: (V_BCNT_U32_B32_e64:i32 ?:i32:$popcnt, ?:i32:$val)
5328 : /*14552*/ 0, // EndSwitchOpcode
5329 : /*14553*/ /*Scope*/ 20|128,3/*404*/, /*->14959*/
5330 : /*14555*/ OPC_RecordChild0, // #0 = $val
5331 : /*14556*/ OPC_Scope, 12|128,2/*268*/, /*->14827*/ // 2 children in Scope
5332 : /*14559*/ OPC_MoveChild, 1,
5333 : /*14561*/ OPC_SwitchOpcode /*3 cases */, 15, TARGET_VAL(ISD::CTPOP),// ->14580
5334 : /*14565*/ OPC_RecordChild0, // #1 = $popcnt
5335 : /*14566*/ OPC_MoveParent,
5336 : /*14567*/ OPC_CheckType, MVT::i32,
5337 : /*14569*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
5338 : /*14571*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BCNT_U32_B32_e64), 0,
5339 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 0,
5340 : // Src: (add:i32 i32:i32:$val, (ctpop:i32 i32:i32:$popcnt)) - Complexity = 6
5341 : // Dst: (V_BCNT_U32_B32_e64:i32 ?:i32:$popcnt, ?:i32:$val)
5342 : /*14580*/ /*SwitchOpcode*/ 120, TARGET_VAL(AMDGPUISD::MUL_I24),// ->14703
5343 : /*14583*/ OPC_RecordChild0, // #1 = $src0
5344 : /*14584*/ OPC_RecordChild1, // #2 = $src1
5345 : /*14585*/ OPC_MoveParent,
5346 : /*14586*/ OPC_CheckType, MVT::i32,
5347 : /*14588*/ OPC_Scope, 12, /*->14602*/ // 2 children in Scope
5348 : /*14590*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
5349 : /*14592*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAD_I32_I24), 0,
5350 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 2, 0,
5351 : // Src: (add:i32 i32:i32:$src2, (AMDGPUmul_i24:i32 i32:i32:$src0, i32:i32:$src1)) - Complexity = 6
5352 : // Dst: (V_MAD_I32_I24:i32 ?:i32:$src0, ?:i32:$src1, ?:i32:$src2)
5353 : /*14602*/ /*Scope*/ 99, /*->14702*/
5354 : /*14603*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
5355 : /*14605*/ OPC_EmitInteger, MVT::i32, 0,
5356 : /*14608*/ OPC_EmitInteger, MVT::i32, 0,
5357 : /*14611*/ OPC_EmitInteger, MVT::i32, 0,
5358 : /*14614*/ OPC_EmitInteger, MVT::i32, 0,
5359 : /*14617*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5360 : /*14629*/ OPC_EmitInteger, MVT::i32, 0,
5361 : /*14632*/ OPC_EmitInteger, MVT::i32, 0,
5362 : /*14635*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5363 : /*14647*/ OPC_EmitInteger, MVT::i32, 0,
5364 : /*14650*/ OPC_EmitInteger, MVT::i32, 0,
5365 : /*14653*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5366 : /*14665*/ OPC_EmitInteger, MVT::i32, 1,
5367 : /*14668*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5368 : /*14671*/ OPC_EmitInteger, MVT::i32, 0,
5369 : /*14674*/ OPC_EmitInteger, MVT::i32, 0,
5370 : /*14677*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULADD_INT24_cm), 0,
5371 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 1, 5, 6, 7, 2, 8, 9, 10, 0, 11, 12, 13, 14, 15, 16, 17,
5372 : // Src: (add:i32 i32:i32:$src2, (AMDGPUmul_i24:i32 i32:i32:$src0, i32:i32:$src1)) - Complexity = 6
5373 : // Dst: (MULADD_INT24_cm:i32 ?:i32:$src0, ?:i32:$src1, ?:i32:$src2)
5374 : /*14702*/ 0, /*End of Scope*/
5375 : /*14703*/ /*SwitchOpcode*/ 120, TARGET_VAL(AMDGPUISD::MUL_U24),// ->14826
5376 : /*14706*/ OPC_RecordChild0, // #1 = $src0
5377 : /*14707*/ OPC_RecordChild1, // #2 = $src1
5378 : /*14708*/ OPC_MoveParent,
5379 : /*14709*/ OPC_CheckType, MVT::i32,
5380 : /*14711*/ OPC_Scope, 12, /*->14725*/ // 2 children in Scope
5381 : /*14713*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
5382 : /*14715*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAD_U32_U24), 0,
5383 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 2, 0,
5384 : // Src: (add:i32 i32:i32:$src2, (AMDGPUmul_u24:i32 i32:i32:$src0, i32:i32:$src1)) - Complexity = 6
5385 : // Dst: (V_MAD_U32_U24:i32 ?:i32:$src0, ?:i32:$src1, ?:i32:$src2)
5386 : /*14725*/ /*Scope*/ 99, /*->14825*/
5387 : /*14726*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
5388 : /*14728*/ OPC_EmitInteger, MVT::i32, 0,
5389 : /*14731*/ OPC_EmitInteger, MVT::i32, 0,
5390 : /*14734*/ OPC_EmitInteger, MVT::i32, 0,
5391 : /*14737*/ OPC_EmitInteger, MVT::i32, 0,
5392 : /*14740*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5393 : /*14752*/ OPC_EmitInteger, MVT::i32, 0,
5394 : /*14755*/ OPC_EmitInteger, MVT::i32, 0,
5395 : /*14758*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5396 : /*14770*/ OPC_EmitInteger, MVT::i32, 0,
5397 : /*14773*/ OPC_EmitInteger, MVT::i32, 0,
5398 : /*14776*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5399 : /*14788*/ OPC_EmitInteger, MVT::i32, 1,
5400 : /*14791*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5401 : /*14794*/ OPC_EmitInteger, MVT::i32, 0,
5402 : /*14797*/ OPC_EmitInteger, MVT::i32, 0,
5403 : /*14800*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULADD_UINT24_eg), 0,
5404 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 1, 5, 6, 7, 2, 8, 9, 10, 0, 11, 12, 13, 14, 15, 16, 17,
5405 : // Src: (add:i32 i32:i32:$src2, (AMDGPUmul_u24:i32 i32:i32:$src0, i32:i32:$src1)) - Complexity = 6
5406 : // Dst: (MULADD_UINT24_eg:i32 ?:i32:$src0, ?:i32:$src1, ?:i32:$src2)
5407 : /*14825*/ 0, /*End of Scope*/
5408 : /*14826*/ 0, // EndSwitchOpcode
5409 : /*14827*/ /*Scope*/ 1|128,1/*129*/, /*->14958*/
5410 : /*14829*/ OPC_RecordChild1, // #1 = $src1
5411 : /*14830*/ OPC_CheckType, MVT::i32,
5412 : /*14832*/ OPC_Scope, 101, /*->14935*/ // 3 children in Scope
5413 : /*14834*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5414 : /*14836*/ OPC_EmitInteger, MVT::i32, 0,
5415 : /*14839*/ OPC_EmitInteger, MVT::i32, 0,
5416 : /*14842*/ OPC_EmitInteger, MVT::i32, 1,
5417 : /*14845*/ OPC_EmitInteger, MVT::i32, 0,
5418 : /*14848*/ OPC_EmitInteger, MVT::i32, 0,
5419 : /*14851*/ OPC_EmitInteger, MVT::i32, 0,
5420 : /*14854*/ OPC_EmitInteger, MVT::i32, 0,
5421 : /*14857*/ OPC_EmitInteger, MVT::i32, 0,
5422 : /*14860*/ OPC_EmitInteger, MVT::i32, 0,
5423 : /*14863*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5424 : /*14875*/ OPC_EmitInteger, MVT::i32, 0,
5425 : /*14878*/ OPC_EmitInteger, MVT::i32, 0,
5426 : /*14881*/ OPC_EmitInteger, MVT::i32, 0,
5427 : /*14884*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5428 : /*14896*/ OPC_EmitInteger, MVT::i32, 1,
5429 : /*14899*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5430 : /*14902*/ OPC_EmitInteger, MVT::i32, 0,
5431 : /*14905*/ OPC_EmitInteger, MVT::i32, 0,
5432 : /*14908*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::ADD_INT), 0,
5433 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5434 : // Src: (add:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
5435 : // Dst: (ADD_INT:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
5436 : /*14935*/ /*Scope*/ 11, /*->14947*/
5437 : /*14936*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
5438 : /*14938*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_ADD_I32), 0,
5439 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
5440 : // Src: (add:i32 SSrc_32:i32:$src0, SSrc_32:i32:$src1) - Complexity = 3
5441 : // Dst: (S_ADD_I32:i32 SSrc_32:i32:$src0, SSrc_32:i32:$src1)
5442 : /*14947*/ /*Scope*/ 9, /*->14957*/
5443 : /*14948*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_ADD_I32_e64), 0,
5444 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
5445 : // Src: (add:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = -997
5446 : // Dst: (V_ADD_I32_e64:i32 i32:i32:$src0, i32:i32:$src1)
5447 : /*14957*/ 0, /*End of Scope*/
5448 : /*14958*/ 0, /*End of Scope*/
5449 : /*14959*/ 0, /*End of Scope*/
5450 : /*14960*/ /*SwitchOpcode*/ 29, TARGET_VAL(AMDGPUISD::REGISTER_LOAD),// ->14992
5451 : /*14963*/ OPC_RecordNode, // #0 = 'AMDGPUregister_load' chained node
5452 : /*14964*/ OPC_RecordChild1, // #1 = $addr
5453 : /*14965*/ OPC_RecordChild2, // #2 = $chan
5454 : /*14966*/ OPC_MoveChild, 2,
5455 : /*14968*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
5456 : /*14971*/ OPC_CheckType, MVT::i32,
5457 : /*14973*/ OPC_MoveParent,
5458 : /*14974*/ OPC_CheckType, MVT::i32,
5459 : /*14976*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5460 : /*14978*/ OPC_CheckComplexPat, /*CP*/8, /*#*/1, // SelectADDRIndirect:$addr #3 #4
5461 : /*14981*/ OPC_EmitMergeInputChains1_0,
5462 : /*14982*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_RegisterLoad), 0|OPFL_Chain,
5463 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 3, 4, 2,
5464 : // Src: (AMDGPUregister_load:i32 ADDRIndirect:iPTR:$addr, (timm:i32):$chan) - Complexity = 15
5465 : // Dst: (R600_RegisterLoad:i32 ADDRIndirect:iPTR:$addr, (timm:i32):$chan)
5466 : /*14992*/ /*SwitchOpcode*/ 30, TARGET_VAL(AMDGPUISD::REGISTER_STORE),// ->15025
5467 : /*14995*/ OPC_RecordNode, // #0 = 'AMDGPUregister_store' chained node
5468 : /*14996*/ OPC_RecordChild1, // #1 = $val
5469 : /*14997*/ OPC_CheckChild1Type, MVT::i32,
5470 : /*14999*/ OPC_RecordChild2, // #2 = $addr
5471 : /*15000*/ OPC_RecordChild3, // #3 = $chan
5472 : /*15001*/ OPC_MoveChild, 3,
5473 : /*15003*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
5474 : /*15006*/ OPC_CheckType, MVT::i32,
5475 : /*15008*/ OPC_MoveParent,
5476 : /*15009*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5477 : /*15011*/ OPC_CheckComplexPat, /*CP*/8, /*#*/2, // SelectADDRIndirect:$addr #4 #5
5478 : /*15014*/ OPC_EmitMergeInputChains1_0,
5479 : /*15015*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_RegisterStore), 0|OPFL_Chain,
5480 : 0/*#VTs*/, 4/*#Ops*/, 1, 4, 5, 3,
5481 : // Src: (AMDGPUregister_store i32:i32:$val, ADDRIndirect:iPTR:$addr, (timm:i32):$chan) - Complexity = 15
5482 : // Dst: (R600_RegisterStore i32:i32:$val, ADDRIndirect:iPTR:$addr, (timm:i32):$chan)
5483 : /*15025*/ /*SwitchOpcode*/ 60|128,23/*3004*/, TARGET_VAL(ISD::SELECT_CC),// ->18033
5484 : /*15029*/ OPC_RecordChild0, // #0 = $src0
5485 : /*15030*/ OPC_Scope, 25|128,12/*1561*/, /*->16594*/ // 2 children in Scope
5486 : /*15033*/ OPC_CheckChild0Type, MVT::f32,
5487 : /*15035*/ OPC_Scope, 10|128,7/*906*/, /*->15944*/ // 2 children in Scope
5488 : /*15038*/ OPC_RecordChild1, // #1 = $src1
5489 : /*15039*/ OPC_Scope, 64|128,3/*448*/, /*->15490*/ // 2 children in Scope
5490 : /*15042*/ OPC_CheckChild2Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5491 : /*15053*/ OPC_CheckChild3Integer, 0,
5492 : /*15055*/ OPC_MoveChild, 4,
5493 : /*15057*/ OPC_CheckOpcode, TARGET_VAL(ISD::CONDCODE),
5494 : /*15060*/ OPC_Scope, 106, /*->15168*/ // 4 children in Scope
5495 : /*15062*/ OPC_CheckPredicate, 103, // Predicate_COND_OEQ
5496 : /*15064*/ OPC_MoveParent,
5497 : /*15065*/ OPC_CheckType, MVT::i32,
5498 : /*15067*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5499 : /*15069*/ OPC_EmitInteger, MVT::i32, 0,
5500 : /*15072*/ OPC_EmitInteger, MVT::i32, 0,
5501 : /*15075*/ OPC_EmitInteger, MVT::i32, 1,
5502 : /*15078*/ OPC_EmitInteger, MVT::i32, 0,
5503 : /*15081*/ OPC_EmitInteger, MVT::i32, 0,
5504 : /*15084*/ OPC_EmitInteger, MVT::i32, 0,
5505 : /*15087*/ OPC_EmitInteger, MVT::i32, 0,
5506 : /*15090*/ OPC_EmitInteger, MVT::i32, 0,
5507 : /*15093*/ OPC_EmitInteger, MVT::i32, 0,
5508 : /*15096*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5509 : /*15108*/ OPC_EmitInteger, MVT::i32, 0,
5510 : /*15111*/ OPC_EmitInteger, MVT::i32, 0,
5511 : /*15114*/ OPC_EmitInteger, MVT::i32, 0,
5512 : /*15117*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5513 : /*15129*/ OPC_EmitInteger, MVT::i32, 1,
5514 : /*15132*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5515 : /*15135*/ OPC_EmitInteger, MVT::i32, 0,
5516 : /*15138*/ OPC_EmitInteger, MVT::i32, 0,
5517 : /*15141*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SETE_DX10), 0,
5518 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5519 : // Src: (selectcc:i32 f32:f32:$src0, f32:f32:$src1, -1:i32, 0:i32, (cond:Other)<<P:Predicate_COND_OEQ>>) - Complexity = 13
5520 : // Dst: (SETE_DX10:i32 f32:f32:$src0, f32:f32:$src1)
5521 : /*15168*/ /*Scope*/ 106, /*->15275*/
5522 : /*15169*/ OPC_CheckPredicate, 104, // Predicate_COND_OGT
5523 : /*15171*/ OPC_MoveParent,
5524 : /*15172*/ OPC_CheckType, MVT::i32,
5525 : /*15174*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5526 : /*15176*/ OPC_EmitInteger, MVT::i32, 0,
5527 : /*15179*/ OPC_EmitInteger, MVT::i32, 0,
5528 : /*15182*/ OPC_EmitInteger, MVT::i32, 1,
5529 : /*15185*/ OPC_EmitInteger, MVT::i32, 0,
5530 : /*15188*/ OPC_EmitInteger, MVT::i32, 0,
5531 : /*15191*/ OPC_EmitInteger, MVT::i32, 0,
5532 : /*15194*/ OPC_EmitInteger, MVT::i32, 0,
5533 : /*15197*/ OPC_EmitInteger, MVT::i32, 0,
5534 : /*15200*/ OPC_EmitInteger, MVT::i32, 0,
5535 : /*15203*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5536 : /*15215*/ OPC_EmitInteger, MVT::i32, 0,
5537 : /*15218*/ OPC_EmitInteger, MVT::i32, 0,
5538 : /*15221*/ OPC_EmitInteger, MVT::i32, 0,
5539 : /*15224*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5540 : /*15236*/ OPC_EmitInteger, MVT::i32, 1,
5541 : /*15239*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5542 : /*15242*/ OPC_EmitInteger, MVT::i32, 0,
5543 : /*15245*/ OPC_EmitInteger, MVT::i32, 0,
5544 : /*15248*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SETGT_DX10), 0,
5545 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5546 : // Src: (selectcc:i32 f32:f32:$src0, f32:f32:$src1, -1:i32, 0:i32, (cond:Other)<<P:Predicate_COND_OGT>>) - Complexity = 13
5547 : // Dst: (SETGT_DX10:i32 f32:f32:$src0, f32:f32:$src1)
5548 : /*15275*/ /*Scope*/ 106, /*->15382*/
5549 : /*15276*/ OPC_CheckPredicate, 105, // Predicate_COND_OGE
5550 : /*15278*/ OPC_MoveParent,
5551 : /*15279*/ OPC_CheckType, MVT::i32,
5552 : /*15281*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5553 : /*15283*/ OPC_EmitInteger, MVT::i32, 0,
5554 : /*15286*/ OPC_EmitInteger, MVT::i32, 0,
5555 : /*15289*/ OPC_EmitInteger, MVT::i32, 1,
5556 : /*15292*/ OPC_EmitInteger, MVT::i32, 0,
5557 : /*15295*/ OPC_EmitInteger, MVT::i32, 0,
5558 : /*15298*/ OPC_EmitInteger, MVT::i32, 0,
5559 : /*15301*/ OPC_EmitInteger, MVT::i32, 0,
5560 : /*15304*/ OPC_EmitInteger, MVT::i32, 0,
5561 : /*15307*/ OPC_EmitInteger, MVT::i32, 0,
5562 : /*15310*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5563 : /*15322*/ OPC_EmitInteger, MVT::i32, 0,
5564 : /*15325*/ OPC_EmitInteger, MVT::i32, 0,
5565 : /*15328*/ OPC_EmitInteger, MVT::i32, 0,
5566 : /*15331*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5567 : /*15343*/ OPC_EmitInteger, MVT::i32, 1,
5568 : /*15346*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5569 : /*15349*/ OPC_EmitInteger, MVT::i32, 0,
5570 : /*15352*/ OPC_EmitInteger, MVT::i32, 0,
5571 : /*15355*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SETGE_DX10), 0,
5572 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5573 : // Src: (selectcc:i32 f32:f32:$src0, f32:f32:$src1, -1:i32, 0:i32, (cond:Other)<<P:Predicate_COND_OGE>>) - Complexity = 13
5574 : // Dst: (SETGE_DX10:i32 f32:f32:$src0, f32:f32:$src1)
5575 : /*15382*/ /*Scope*/ 106, /*->15489*/
5576 : /*15383*/ OPC_CheckPredicate, 106, // Predicate_COND_UNE_NE
5577 : /*15385*/ OPC_MoveParent,
5578 : /*15386*/ OPC_CheckType, MVT::i32,
5579 : /*15388*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5580 : /*15390*/ OPC_EmitInteger, MVT::i32, 0,
5581 : /*15393*/ OPC_EmitInteger, MVT::i32, 0,
5582 : /*15396*/ OPC_EmitInteger, MVT::i32, 1,
5583 : /*15399*/ OPC_EmitInteger, MVT::i32, 0,
5584 : /*15402*/ OPC_EmitInteger, MVT::i32, 0,
5585 : /*15405*/ OPC_EmitInteger, MVT::i32, 0,
5586 : /*15408*/ OPC_EmitInteger, MVT::i32, 0,
5587 : /*15411*/ OPC_EmitInteger, MVT::i32, 0,
5588 : /*15414*/ OPC_EmitInteger, MVT::i32, 0,
5589 : /*15417*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5590 : /*15429*/ OPC_EmitInteger, MVT::i32, 0,
5591 : /*15432*/ OPC_EmitInteger, MVT::i32, 0,
5592 : /*15435*/ OPC_EmitInteger, MVT::i32, 0,
5593 : /*15438*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5594 : /*15450*/ OPC_EmitInteger, MVT::i32, 1,
5595 : /*15453*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5596 : /*15456*/ OPC_EmitInteger, MVT::i32, 0,
5597 : /*15459*/ OPC_EmitInteger, MVT::i32, 0,
5598 : /*15462*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SETNE_DX10), 0,
5599 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5600 : // Src: (selectcc:i32 f32:f32:$src0, f32:f32:$src1, -1:i32, 0:i32, (cond:Other)<<P:Predicate_COND_UNE_NE>>) - Complexity = 13
5601 : // Dst: (SETNE_DX10:i32 f32:f32:$src0, f32:f32:$src1)
5602 : /*15489*/ 0, /*End of Scope*/
5603 : /*15490*/ /*Scope*/ 67|128,3/*451*/, /*->15943*/
5604 : /*15492*/ OPC_MoveChild, 2,
5605 : /*15494*/ OPC_CheckOpcode, TARGET_VAL(ISD::ConstantFP),
5606 : /*15497*/ OPC_CheckPredicate, 107, // Predicate_FP_ONE
5607 : /*15499*/ OPC_MoveParent,
5608 : /*15500*/ OPC_MoveChild, 3,
5609 : /*15502*/ OPC_CheckOpcode, TARGET_VAL(ISD::ConstantFP),
5610 : /*15505*/ OPC_CheckPredicate, 108, // Predicate_FP_ZERO
5611 : /*15507*/ OPC_MoveParent,
5612 : /*15508*/ OPC_MoveChild, 4,
5613 : /*15510*/ OPC_CheckOpcode, TARGET_VAL(ISD::CONDCODE),
5614 : /*15513*/ OPC_Scope, 106, /*->15621*/ // 4 children in Scope
5615 : /*15515*/ OPC_CheckPredicate, 103, // Predicate_COND_OEQ
5616 : /*15517*/ OPC_MoveParent,
5617 : /*15518*/ OPC_CheckType, MVT::f32,
5618 : /*15520*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5619 : /*15522*/ OPC_EmitInteger, MVT::i32, 0,
5620 : /*15525*/ OPC_EmitInteger, MVT::i32, 0,
5621 : /*15528*/ OPC_EmitInteger, MVT::i32, 1,
5622 : /*15531*/ OPC_EmitInteger, MVT::i32, 0,
5623 : /*15534*/ OPC_EmitInteger, MVT::i32, 0,
5624 : /*15537*/ OPC_EmitInteger, MVT::i32, 0,
5625 : /*15540*/ OPC_EmitInteger, MVT::i32, 0,
5626 : /*15543*/ OPC_EmitInteger, MVT::i32, 0,
5627 : /*15546*/ OPC_EmitInteger, MVT::i32, 0,
5628 : /*15549*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5629 : /*15561*/ OPC_EmitInteger, MVT::i32, 0,
5630 : /*15564*/ OPC_EmitInteger, MVT::i32, 0,
5631 : /*15567*/ OPC_EmitInteger, MVT::i32, 0,
5632 : /*15570*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5633 : /*15582*/ OPC_EmitInteger, MVT::i32, 1,
5634 : /*15585*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5635 : /*15588*/ OPC_EmitInteger, MVT::i32, 0,
5636 : /*15591*/ OPC_EmitInteger, MVT::i32, 0,
5637 : /*15594*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SETE), 0,
5638 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5639 : // Src: (selectcc:f32 f32:f32:$src0, f32:f32:$src1, (fpimm:f32)<<P:Predicate_FP_ONE>>, (fpimm:f32)<<P:Predicate_FP_ZERO>>, (cond:Other)<<P:Predicate_COND_OEQ>>) - Complexity = 11
5640 : // Dst: (SETE:f32 f32:f32:$src0, f32:f32:$src1)
5641 : /*15621*/ /*Scope*/ 106, /*->15728*/
5642 : /*15622*/ OPC_CheckPredicate, 104, // Predicate_COND_OGT
5643 : /*15624*/ OPC_MoveParent,
5644 : /*15625*/ OPC_CheckType, MVT::f32,
5645 : /*15627*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5646 : /*15629*/ OPC_EmitInteger, MVT::i32, 0,
5647 : /*15632*/ OPC_EmitInteger, MVT::i32, 0,
5648 : /*15635*/ OPC_EmitInteger, MVT::i32, 1,
5649 : /*15638*/ OPC_EmitInteger, MVT::i32, 0,
5650 : /*15641*/ OPC_EmitInteger, MVT::i32, 0,
5651 : /*15644*/ OPC_EmitInteger, MVT::i32, 0,
5652 : /*15647*/ OPC_EmitInteger, MVT::i32, 0,
5653 : /*15650*/ OPC_EmitInteger, MVT::i32, 0,
5654 : /*15653*/ OPC_EmitInteger, MVT::i32, 0,
5655 : /*15656*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5656 : /*15668*/ OPC_EmitInteger, MVT::i32, 0,
5657 : /*15671*/ OPC_EmitInteger, MVT::i32, 0,
5658 : /*15674*/ OPC_EmitInteger, MVT::i32, 0,
5659 : /*15677*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5660 : /*15689*/ OPC_EmitInteger, MVT::i32, 1,
5661 : /*15692*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5662 : /*15695*/ OPC_EmitInteger, MVT::i32, 0,
5663 : /*15698*/ OPC_EmitInteger, MVT::i32, 0,
5664 : /*15701*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SGT), 0,
5665 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5666 : // Src: (selectcc:f32 f32:f32:$src0, f32:f32:$src1, (fpimm:f32)<<P:Predicate_FP_ONE>>, (fpimm:f32)<<P:Predicate_FP_ZERO>>, (cond:Other)<<P:Predicate_COND_OGT>>) - Complexity = 11
5667 : // Dst: (SGT:f32 f32:f32:$src0, f32:f32:$src1)
5668 : /*15728*/ /*Scope*/ 106, /*->15835*/
5669 : /*15729*/ OPC_CheckPredicate, 105, // Predicate_COND_OGE
5670 : /*15731*/ OPC_MoveParent,
5671 : /*15732*/ OPC_CheckType, MVT::f32,
5672 : /*15734*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5673 : /*15736*/ OPC_EmitInteger, MVT::i32, 0,
5674 : /*15739*/ OPC_EmitInteger, MVT::i32, 0,
5675 : /*15742*/ OPC_EmitInteger, MVT::i32, 1,
5676 : /*15745*/ OPC_EmitInteger, MVT::i32, 0,
5677 : /*15748*/ OPC_EmitInteger, MVT::i32, 0,
5678 : /*15751*/ OPC_EmitInteger, MVT::i32, 0,
5679 : /*15754*/ OPC_EmitInteger, MVT::i32, 0,
5680 : /*15757*/ OPC_EmitInteger, MVT::i32, 0,
5681 : /*15760*/ OPC_EmitInteger, MVT::i32, 0,
5682 : /*15763*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5683 : /*15775*/ OPC_EmitInteger, MVT::i32, 0,
5684 : /*15778*/ OPC_EmitInteger, MVT::i32, 0,
5685 : /*15781*/ OPC_EmitInteger, MVT::i32, 0,
5686 : /*15784*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5687 : /*15796*/ OPC_EmitInteger, MVT::i32, 1,
5688 : /*15799*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5689 : /*15802*/ OPC_EmitInteger, MVT::i32, 0,
5690 : /*15805*/ OPC_EmitInteger, MVT::i32, 0,
5691 : /*15808*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SGE), 0,
5692 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5693 : // Src: (selectcc:f32 f32:f32:$src0, f32:f32:$src1, (fpimm:f32)<<P:Predicate_FP_ONE>>, (fpimm:f32)<<P:Predicate_FP_ZERO>>, (cond:Other)<<P:Predicate_COND_OGE>>) - Complexity = 11
5694 : // Dst: (SGE:f32 f32:f32:$src0, f32:f32:$src1)
5695 : /*15835*/ /*Scope*/ 106, /*->15942*/
5696 : /*15836*/ OPC_CheckPredicate, 106, // Predicate_COND_UNE_NE
5697 : /*15838*/ OPC_MoveParent,
5698 : /*15839*/ OPC_CheckType, MVT::f32,
5699 : /*15841*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5700 : /*15843*/ OPC_EmitInteger, MVT::i32, 0,
5701 : /*15846*/ OPC_EmitInteger, MVT::i32, 0,
5702 : /*15849*/ OPC_EmitInteger, MVT::i32, 1,
5703 : /*15852*/ OPC_EmitInteger, MVT::i32, 0,
5704 : /*15855*/ OPC_EmitInteger, MVT::i32, 0,
5705 : /*15858*/ OPC_EmitInteger, MVT::i32, 0,
5706 : /*15861*/ OPC_EmitInteger, MVT::i32, 0,
5707 : /*15864*/ OPC_EmitInteger, MVT::i32, 0,
5708 : /*15867*/ OPC_EmitInteger, MVT::i32, 0,
5709 : /*15870*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5710 : /*15882*/ OPC_EmitInteger, MVT::i32, 0,
5711 : /*15885*/ OPC_EmitInteger, MVT::i32, 0,
5712 : /*15888*/ OPC_EmitInteger, MVT::i32, 0,
5713 : /*15891*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5714 : /*15903*/ OPC_EmitInteger, MVT::i32, 1,
5715 : /*15906*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5716 : /*15909*/ OPC_EmitInteger, MVT::i32, 0,
5717 : /*15912*/ OPC_EmitInteger, MVT::i32, 0,
5718 : /*15915*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SNE), 0,
5719 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5720 : // Src: (selectcc:f32 f32:f32:$src0, f32:f32:$src1, (fpimm:f32)<<P:Predicate_FP_ONE>>, (fpimm:f32)<<P:Predicate_FP_ZERO>>, (cond:Other)<<P:Predicate_COND_UNE_NE>>) - Complexity = 11
5721 : // Dst: (SNE:f32 f32:f32:$src0, f32:f32:$src1)
5722 : /*15942*/ 0, /*End of Scope*/
5723 : /*15943*/ 0, /*End of Scope*/
5724 : /*15944*/ /*Scope*/ 7|128,5/*647*/, /*->16593*/
5725 : /*15946*/ OPC_MoveChild, 1,
5726 : /*15948*/ OPC_CheckOpcode, TARGET_VAL(ISD::ConstantFP),
5727 : /*15951*/ OPC_CheckPredicate, 108, // Predicate_FP_ZERO
5728 : /*15953*/ OPC_MoveParent,
5729 : /*15954*/ OPC_RecordChild2, // #1 = $src1
5730 : /*15955*/ OPC_RecordChild3, // #2 = $src2
5731 : /*15956*/ OPC_MoveChild, 4,
5732 : /*15958*/ OPC_CheckOpcode, TARGET_VAL(ISD::CONDCODE),
5733 : /*15961*/ OPC_Scope, 104, /*->16067*/ // 6 children in Scope
5734 : /*15963*/ OPC_CheckPredicate, 103, // Predicate_COND_OEQ
5735 : /*15965*/ OPC_MoveParent,
5736 : /*15966*/ OPC_CheckType, MVT::f32,
5737 : /*15968*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
5738 : /*15970*/ OPC_EmitInteger, MVT::i32, 0,
5739 : /*15973*/ OPC_EmitInteger, MVT::i32, 0,
5740 : /*15976*/ OPC_EmitInteger, MVT::i32, 0,
5741 : /*15979*/ OPC_EmitInteger, MVT::i32, 0,
5742 : /*15982*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5743 : /*15994*/ OPC_EmitInteger, MVT::i32, 0,
5744 : /*15997*/ OPC_EmitInteger, MVT::i32, 0,
5745 : /*16000*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5746 : /*16012*/ OPC_EmitInteger, MVT::i32, 0,
5747 : /*16015*/ OPC_EmitInteger, MVT::i32, 0,
5748 : /*16018*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5749 : /*16030*/ OPC_EmitInteger, MVT::i32, 1,
5750 : /*16033*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5751 : /*16036*/ OPC_EmitInteger, MVT::i32, 0,
5752 : /*16039*/ OPC_EmitInteger, MVT::i32, 0,
5753 : /*16042*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDE_r600), 0,
5754 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
5755 : // Src: (selectcc:f32 f32:f32:$src0, (fpimm:f32)<<P:Predicate_FP_ZERO>>, f32:f32:$src1, f32:f32:$src2, (cond:Other)<<P:Predicate_COND_OEQ>>) - Complexity = 7
5756 : // Dst: (CNDE_r600:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2)
5757 : /*16067*/ /*Scope*/ 104, /*->16172*/
5758 : /*16068*/ OPC_CheckPredicate, 104, // Predicate_COND_OGT
5759 : /*16070*/ OPC_MoveParent,
5760 : /*16071*/ OPC_CheckType, MVT::f32,
5761 : /*16073*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
5762 : /*16075*/ OPC_EmitInteger, MVT::i32, 0,
5763 : /*16078*/ OPC_EmitInteger, MVT::i32, 0,
5764 : /*16081*/ OPC_EmitInteger, MVT::i32, 0,
5765 : /*16084*/ OPC_EmitInteger, MVT::i32, 0,
5766 : /*16087*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5767 : /*16099*/ OPC_EmitInteger, MVT::i32, 0,
5768 : /*16102*/ OPC_EmitInteger, MVT::i32, 0,
5769 : /*16105*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5770 : /*16117*/ OPC_EmitInteger, MVT::i32, 0,
5771 : /*16120*/ OPC_EmitInteger, MVT::i32, 0,
5772 : /*16123*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5773 : /*16135*/ OPC_EmitInteger, MVT::i32, 1,
5774 : /*16138*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5775 : /*16141*/ OPC_EmitInteger, MVT::i32, 0,
5776 : /*16144*/ OPC_EmitInteger, MVT::i32, 0,
5777 : /*16147*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDGT_r600), 0,
5778 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
5779 : // Src: (selectcc:f32 f32:f32:$src0, (fpimm:f32)<<P:Predicate_FP_ZERO>>, f32:f32:$src1, f32:f32:$src2, (cond:Other)<<P:Predicate_COND_OGT>>) - Complexity = 7
5780 : // Dst: (CNDGT_r600:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2)
5781 : /*16172*/ /*Scope*/ 104, /*->16277*/
5782 : /*16173*/ OPC_CheckPredicate, 105, // Predicate_COND_OGE
5783 : /*16175*/ OPC_MoveParent,
5784 : /*16176*/ OPC_CheckType, MVT::f32,
5785 : /*16178*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
5786 : /*16180*/ OPC_EmitInteger, MVT::i32, 0,
5787 : /*16183*/ OPC_EmitInteger, MVT::i32, 0,
5788 : /*16186*/ OPC_EmitInteger, MVT::i32, 0,
5789 : /*16189*/ OPC_EmitInteger, MVT::i32, 0,
5790 : /*16192*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5791 : /*16204*/ OPC_EmitInteger, MVT::i32, 0,
5792 : /*16207*/ OPC_EmitInteger, MVT::i32, 0,
5793 : /*16210*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5794 : /*16222*/ OPC_EmitInteger, MVT::i32, 0,
5795 : /*16225*/ OPC_EmitInteger, MVT::i32, 0,
5796 : /*16228*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5797 : /*16240*/ OPC_EmitInteger, MVT::i32, 1,
5798 : /*16243*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5799 : /*16246*/ OPC_EmitInteger, MVT::i32, 0,
5800 : /*16249*/ OPC_EmitInteger, MVT::i32, 0,
5801 : /*16252*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDGE_r600), 0,
5802 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
5803 : // Src: (selectcc:f32 f32:f32:$src0, (fpimm:f32)<<P:Predicate_FP_ZERO>>, f32:f32:$src1, f32:f32:$src2, (cond:Other)<<P:Predicate_COND_OGE>>) - Complexity = 7
5804 : // Dst: (CNDGE_r600:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2)
5805 : /*16277*/ /*Scope*/ 104, /*->16382*/
5806 : /*16278*/ OPC_CheckPredicate, 103, // Predicate_COND_OEQ
5807 : /*16280*/ OPC_MoveParent,
5808 : /*16281*/ OPC_CheckType, MVT::f32,
5809 : /*16283*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
5810 : /*16285*/ OPC_EmitInteger, MVT::i32, 0,
5811 : /*16288*/ OPC_EmitInteger, MVT::i32, 0,
5812 : /*16291*/ OPC_EmitInteger, MVT::i32, 0,
5813 : /*16294*/ OPC_EmitInteger, MVT::i32, 0,
5814 : /*16297*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5815 : /*16309*/ OPC_EmitInteger, MVT::i32, 0,
5816 : /*16312*/ OPC_EmitInteger, MVT::i32, 0,
5817 : /*16315*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5818 : /*16327*/ OPC_EmitInteger, MVT::i32, 0,
5819 : /*16330*/ OPC_EmitInteger, MVT::i32, 0,
5820 : /*16333*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5821 : /*16345*/ OPC_EmitInteger, MVT::i32, 1,
5822 : /*16348*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5823 : /*16351*/ OPC_EmitInteger, MVT::i32, 0,
5824 : /*16354*/ OPC_EmitInteger, MVT::i32, 0,
5825 : /*16357*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDE_eg), 0,
5826 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
5827 : // Src: (selectcc:f32 f32:f32:$src0, (fpimm:f32)<<P:Predicate_FP_ZERO>>, f32:f32:$src1, f32:f32:$src2, (cond:Other)<<P:Predicate_COND_OEQ>>) - Complexity = 7
5828 : // Dst: (CNDE_eg:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2)
5829 : /*16382*/ /*Scope*/ 104, /*->16487*/
5830 : /*16383*/ OPC_CheckPredicate, 104, // Predicate_COND_OGT
5831 : /*16385*/ OPC_MoveParent,
5832 : /*16386*/ OPC_CheckType, MVT::f32,
5833 : /*16388*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
5834 : /*16390*/ OPC_EmitInteger, MVT::i32, 0,
5835 : /*16393*/ OPC_EmitInteger, MVT::i32, 0,
5836 : /*16396*/ OPC_EmitInteger, MVT::i32, 0,
5837 : /*16399*/ OPC_EmitInteger, MVT::i32, 0,
5838 : /*16402*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5839 : /*16414*/ OPC_EmitInteger, MVT::i32, 0,
5840 : /*16417*/ OPC_EmitInteger, MVT::i32, 0,
5841 : /*16420*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5842 : /*16432*/ OPC_EmitInteger, MVT::i32, 0,
5843 : /*16435*/ OPC_EmitInteger, MVT::i32, 0,
5844 : /*16438*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5845 : /*16450*/ OPC_EmitInteger, MVT::i32, 1,
5846 : /*16453*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5847 : /*16456*/ OPC_EmitInteger, MVT::i32, 0,
5848 : /*16459*/ OPC_EmitInteger, MVT::i32, 0,
5849 : /*16462*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDGT_eg), 0,
5850 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
5851 : // Src: (selectcc:f32 f32:f32:$src0, (fpimm:f32)<<P:Predicate_FP_ZERO>>, f32:f32:$src1, f32:f32:$src2, (cond:Other)<<P:Predicate_COND_OGT>>) - Complexity = 7
5852 : // Dst: (CNDGT_eg:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2)
5853 : /*16487*/ /*Scope*/ 104, /*->16592*/
5854 : /*16488*/ OPC_CheckPredicate, 105, // Predicate_COND_OGE
5855 : /*16490*/ OPC_MoveParent,
5856 : /*16491*/ OPC_CheckType, MVT::f32,
5857 : /*16493*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
5858 : /*16495*/ OPC_EmitInteger, MVT::i32, 0,
5859 : /*16498*/ OPC_EmitInteger, MVT::i32, 0,
5860 : /*16501*/ OPC_EmitInteger, MVT::i32, 0,
5861 : /*16504*/ OPC_EmitInteger, MVT::i32, 0,
5862 : /*16507*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5863 : /*16519*/ OPC_EmitInteger, MVT::i32, 0,
5864 : /*16522*/ OPC_EmitInteger, MVT::i32, 0,
5865 : /*16525*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5866 : /*16537*/ OPC_EmitInteger, MVT::i32, 0,
5867 : /*16540*/ OPC_EmitInteger, MVT::i32, 0,
5868 : /*16543*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5869 : /*16555*/ OPC_EmitInteger, MVT::i32, 1,
5870 : /*16558*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5871 : /*16561*/ OPC_EmitInteger, MVT::i32, 0,
5872 : /*16564*/ OPC_EmitInteger, MVT::i32, 0,
5873 : /*16567*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDGE_eg), 0,
5874 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
5875 : // Src: (selectcc:f32 f32:f32:$src0, (fpimm:f32)<<P:Predicate_FP_ZERO>>, f32:f32:$src1, f32:f32:$src2, (cond:Other)<<P:Predicate_COND_OGE>>) - Complexity = 7
5876 : // Dst: (CNDGE_eg:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2)
5877 : /*16592*/ 0, /*End of Scope*/
5878 : /*16593*/ 0, /*End of Scope*/
5879 : /*16594*/ /*Scope*/ 28|128,11/*1436*/, /*->18032*/
5880 : /*16596*/ OPC_CheckChild0Type, MVT::i32,
5881 : /*16598*/ OPC_Scope, 20|128,5/*660*/, /*->17261*/ // 3 children in Scope
5882 : /*16601*/ OPC_RecordChild1, // #1 = $src1
5883 : /*16602*/ OPC_CheckChild2Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5884 : /*16613*/ OPC_CheckChild3Integer, 0,
5885 : /*16615*/ OPC_MoveChild, 4,
5886 : /*16617*/ OPC_Scope, 106, /*->16725*/ // 6 children in Scope
5887 : /*16619*/ OPC_CheckCondCode, ISD::SETEQ,
5888 : /*16621*/ OPC_MoveParent,
5889 : /*16622*/ OPC_CheckType, MVT::i32,
5890 : /*16624*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5891 : /*16626*/ OPC_EmitInteger, MVT::i32, 0,
5892 : /*16629*/ OPC_EmitInteger, MVT::i32, 0,
5893 : /*16632*/ OPC_EmitInteger, MVT::i32, 1,
5894 : /*16635*/ OPC_EmitInteger, MVT::i32, 0,
5895 : /*16638*/ OPC_EmitInteger, MVT::i32, 0,
5896 : /*16641*/ OPC_EmitInteger, MVT::i32, 0,
5897 : /*16644*/ OPC_EmitInteger, MVT::i32, 0,
5898 : /*16647*/ OPC_EmitInteger, MVT::i32, 0,
5899 : /*16650*/ OPC_EmitInteger, MVT::i32, 0,
5900 : /*16653*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5901 : /*16665*/ OPC_EmitInteger, MVT::i32, 0,
5902 : /*16668*/ OPC_EmitInteger, MVT::i32, 0,
5903 : /*16671*/ OPC_EmitInteger, MVT::i32, 0,
5904 : /*16674*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5905 : /*16686*/ OPC_EmitInteger, MVT::i32, 1,
5906 : /*16689*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5907 : /*16692*/ OPC_EmitInteger, MVT::i32, 0,
5908 : /*16695*/ OPC_EmitInteger, MVT::i32, 0,
5909 : /*16698*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SETE_INT), 0,
5910 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5911 : // Src: (selectcc:i32 i32:i32:$src0, i32:i32:$src1, -1:i32, 0:i32, SETEQ:Other) - Complexity = 13
5912 : // Dst: (SETE_INT:i32 i32:i32:$src0, i32:i32:$src1)
5913 : /*16725*/ /*Scope*/ 106, /*->16832*/
5914 : /*16726*/ OPC_CheckCondCode, ISD::SETGT,
5915 : /*16728*/ OPC_MoveParent,
5916 : /*16729*/ OPC_CheckType, MVT::i32,
5917 : /*16731*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5918 : /*16733*/ OPC_EmitInteger, MVT::i32, 0,
5919 : /*16736*/ OPC_EmitInteger, MVT::i32, 0,
5920 : /*16739*/ OPC_EmitInteger, MVT::i32, 1,
5921 : /*16742*/ OPC_EmitInteger, MVT::i32, 0,
5922 : /*16745*/ OPC_EmitInteger, MVT::i32, 0,
5923 : /*16748*/ OPC_EmitInteger, MVT::i32, 0,
5924 : /*16751*/ OPC_EmitInteger, MVT::i32, 0,
5925 : /*16754*/ OPC_EmitInteger, MVT::i32, 0,
5926 : /*16757*/ OPC_EmitInteger, MVT::i32, 0,
5927 : /*16760*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5928 : /*16772*/ OPC_EmitInteger, MVT::i32, 0,
5929 : /*16775*/ OPC_EmitInteger, MVT::i32, 0,
5930 : /*16778*/ OPC_EmitInteger, MVT::i32, 0,
5931 : /*16781*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5932 : /*16793*/ OPC_EmitInteger, MVT::i32, 1,
5933 : /*16796*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5934 : /*16799*/ OPC_EmitInteger, MVT::i32, 0,
5935 : /*16802*/ OPC_EmitInteger, MVT::i32, 0,
5936 : /*16805*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SETGT_INT), 0,
5937 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5938 : // Src: (selectcc:i32 i32:i32:$src0, i32:i32:$src1, -1:i32, 0:i32, SETGT:Other) - Complexity = 13
5939 : // Dst: (SETGT_INT:i32 i32:i32:$src0, i32:i32:$src1)
5940 : /*16832*/ /*Scope*/ 106, /*->16939*/
5941 : /*16833*/ OPC_CheckCondCode, ISD::SETGE,
5942 : /*16835*/ OPC_MoveParent,
5943 : /*16836*/ OPC_CheckType, MVT::i32,
5944 : /*16838*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5945 : /*16840*/ OPC_EmitInteger, MVT::i32, 0,
5946 : /*16843*/ OPC_EmitInteger, MVT::i32, 0,
5947 : /*16846*/ OPC_EmitInteger, MVT::i32, 1,
5948 : /*16849*/ OPC_EmitInteger, MVT::i32, 0,
5949 : /*16852*/ OPC_EmitInteger, MVT::i32, 0,
5950 : /*16855*/ OPC_EmitInteger, MVT::i32, 0,
5951 : /*16858*/ OPC_EmitInteger, MVT::i32, 0,
5952 : /*16861*/ OPC_EmitInteger, MVT::i32, 0,
5953 : /*16864*/ OPC_EmitInteger, MVT::i32, 0,
5954 : /*16867*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5955 : /*16879*/ OPC_EmitInteger, MVT::i32, 0,
5956 : /*16882*/ OPC_EmitInteger, MVT::i32, 0,
5957 : /*16885*/ OPC_EmitInteger, MVT::i32, 0,
5958 : /*16888*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5959 : /*16900*/ OPC_EmitInteger, MVT::i32, 1,
5960 : /*16903*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5961 : /*16906*/ OPC_EmitInteger, MVT::i32, 0,
5962 : /*16909*/ OPC_EmitInteger, MVT::i32, 0,
5963 : /*16912*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SETGE_INT), 0,
5964 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5965 : // Src: (selectcc:i32 i32:i32:$src0, i32:i32:$src1, -1:i32, 0:i32, SETGE:Other) - Complexity = 13
5966 : // Dst: (SETGE_INT:i32 i32:i32:$src0, i32:i32:$src1)
5967 : /*16939*/ /*Scope*/ 106, /*->17046*/
5968 : /*16940*/ OPC_CheckCondCode, ISD::SETNE,
5969 : /*16942*/ OPC_MoveParent,
5970 : /*16943*/ OPC_CheckType, MVT::i32,
5971 : /*16945*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5972 : /*16947*/ OPC_EmitInteger, MVT::i32, 0,
5973 : /*16950*/ OPC_EmitInteger, MVT::i32, 0,
5974 : /*16953*/ OPC_EmitInteger, MVT::i32, 1,
5975 : /*16956*/ OPC_EmitInteger, MVT::i32, 0,
5976 : /*16959*/ OPC_EmitInteger, MVT::i32, 0,
5977 : /*16962*/ OPC_EmitInteger, MVT::i32, 0,
5978 : /*16965*/ OPC_EmitInteger, MVT::i32, 0,
5979 : /*16968*/ OPC_EmitInteger, MVT::i32, 0,
5980 : /*16971*/ OPC_EmitInteger, MVT::i32, 0,
5981 : /*16974*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5982 : /*16986*/ OPC_EmitInteger, MVT::i32, 0,
5983 : /*16989*/ OPC_EmitInteger, MVT::i32, 0,
5984 : /*16992*/ OPC_EmitInteger, MVT::i32, 0,
5985 : /*16995*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
5986 : /*17007*/ OPC_EmitInteger, MVT::i32, 1,
5987 : /*17010*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
5988 : /*17013*/ OPC_EmitInteger, MVT::i32, 0,
5989 : /*17016*/ OPC_EmitInteger, MVT::i32, 0,
5990 : /*17019*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SETNE_INT), 0,
5991 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
5992 : // Src: (selectcc:i32 i32:i32:$src0, i32:i32:$src1, -1:i32, 0:i32, SETNE:Other) - Complexity = 13
5993 : // Dst: (SETNE_INT:i32 i32:i32:$src0, i32:i32:$src1)
5994 : /*17046*/ /*Scope*/ 106, /*->17153*/
5995 : /*17047*/ OPC_CheckCondCode, ISD::SETUGT,
5996 : /*17049*/ OPC_MoveParent,
5997 : /*17050*/ OPC_CheckType, MVT::i32,
5998 : /*17052*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
5999 : /*17054*/ OPC_EmitInteger, MVT::i32, 0,
6000 : /*17057*/ OPC_EmitInteger, MVT::i32, 0,
6001 : /*17060*/ OPC_EmitInteger, MVT::i32, 1,
6002 : /*17063*/ OPC_EmitInteger, MVT::i32, 0,
6003 : /*17066*/ OPC_EmitInteger, MVT::i32, 0,
6004 : /*17069*/ OPC_EmitInteger, MVT::i32, 0,
6005 : /*17072*/ OPC_EmitInteger, MVT::i32, 0,
6006 : /*17075*/ OPC_EmitInteger, MVT::i32, 0,
6007 : /*17078*/ OPC_EmitInteger, MVT::i32, 0,
6008 : /*17081*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6009 : /*17093*/ OPC_EmitInteger, MVT::i32, 0,
6010 : /*17096*/ OPC_EmitInteger, MVT::i32, 0,
6011 : /*17099*/ OPC_EmitInteger, MVT::i32, 0,
6012 : /*17102*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6013 : /*17114*/ OPC_EmitInteger, MVT::i32, 1,
6014 : /*17117*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6015 : /*17120*/ OPC_EmitInteger, MVT::i32, 0,
6016 : /*17123*/ OPC_EmitInteger, MVT::i32, 0,
6017 : /*17126*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SETGT_UINT), 0,
6018 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
6019 : // Src: (selectcc:i32 i32:i32:$src0, i32:i32:$src1, -1:i32, 0:i32, SETUGT:Other) - Complexity = 13
6020 : // Dst: (SETGT_UINT:i32 i32:i32:$src0, i32:i32:$src1)
6021 : /*17153*/ /*Scope*/ 106, /*->17260*/
6022 : /*17154*/ OPC_CheckCondCode, ISD::SETUGE,
6023 : /*17156*/ OPC_MoveParent,
6024 : /*17157*/ OPC_CheckType, MVT::i32,
6025 : /*17159*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6026 : /*17161*/ OPC_EmitInteger, MVT::i32, 0,
6027 : /*17164*/ OPC_EmitInteger, MVT::i32, 0,
6028 : /*17167*/ OPC_EmitInteger, MVT::i32, 1,
6029 : /*17170*/ OPC_EmitInteger, MVT::i32, 0,
6030 : /*17173*/ OPC_EmitInteger, MVT::i32, 0,
6031 : /*17176*/ OPC_EmitInteger, MVT::i32, 0,
6032 : /*17179*/ OPC_EmitInteger, MVT::i32, 0,
6033 : /*17182*/ OPC_EmitInteger, MVT::i32, 0,
6034 : /*17185*/ OPC_EmitInteger, MVT::i32, 0,
6035 : /*17188*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6036 : /*17200*/ OPC_EmitInteger, MVT::i32, 0,
6037 : /*17203*/ OPC_EmitInteger, MVT::i32, 0,
6038 : /*17206*/ OPC_EmitInteger, MVT::i32, 0,
6039 : /*17209*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6040 : /*17221*/ OPC_EmitInteger, MVT::i32, 1,
6041 : /*17224*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6042 : /*17227*/ OPC_EmitInteger, MVT::i32, 0,
6043 : /*17230*/ OPC_EmitInteger, MVT::i32, 0,
6044 : /*17233*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SETGE_UINT), 0,
6045 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
6046 : // Src: (selectcc:i32 i32:i32:$src0, i32:i32:$src1, -1:i32, 0:i32, SETUGE:Other) - Complexity = 13
6047 : // Dst: (SETGE_UINT:i32 i32:i32:$src0, i32:i32:$src1)
6048 : /*17260*/ 0, /*End of Scope*/
6049 : /*17261*/ /*Scope*/ 5|128,5/*645*/, /*->17908*/
6050 : /*17263*/ OPC_CheckChild1Integer, 0,
6051 : /*17265*/ OPC_RecordChild2, // #1 = $src1
6052 : /*17266*/ OPC_RecordChild3, // #2 = $src2
6053 : /*17267*/ OPC_MoveChild, 4,
6054 : /*17269*/ OPC_Scope, 64|128,2/*320*/, /*->17592*/ // 4 children in Scope
6055 : /*17272*/ OPC_CheckOpcode, TARGET_VAL(ISD::CONDCODE),
6056 : /*17275*/ OPC_Scope, 104, /*->17381*/ // 3 children in Scope
6057 : /*17277*/ OPC_CheckPredicate, 109, // Predicate_COND_EQ
6058 : /*17279*/ OPC_MoveParent,
6059 : /*17280*/ OPC_CheckType, MVT::i32,
6060 : /*17282*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6061 : /*17284*/ OPC_EmitInteger, MVT::i32, 0,
6062 : /*17287*/ OPC_EmitInteger, MVT::i32, 0,
6063 : /*17290*/ OPC_EmitInteger, MVT::i32, 0,
6064 : /*17293*/ OPC_EmitInteger, MVT::i32, 0,
6065 : /*17296*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6066 : /*17308*/ OPC_EmitInteger, MVT::i32, 0,
6067 : /*17311*/ OPC_EmitInteger, MVT::i32, 0,
6068 : /*17314*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6069 : /*17326*/ OPC_EmitInteger, MVT::i32, 0,
6070 : /*17329*/ OPC_EmitInteger, MVT::i32, 0,
6071 : /*17332*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6072 : /*17344*/ OPC_EmitInteger, MVT::i32, 1,
6073 : /*17347*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6074 : /*17350*/ OPC_EmitInteger, MVT::i32, 0,
6075 : /*17353*/ OPC_EmitInteger, MVT::i32, 0,
6076 : /*17356*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDE_INT), 0,
6077 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
6078 : // Src: (selectcc:i32 i32:i32:$src0, 0:i32, i32:i32:$src1, i32:i32:$src2, (cond:Other)<<P:Predicate_COND_EQ>>) - Complexity = 8
6079 : // Dst: (CNDE_INT:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
6080 : /*17381*/ /*Scope*/ 104, /*->17486*/
6081 : /*17382*/ OPC_CheckPredicate, 110, // Predicate_COND_SGE
6082 : /*17384*/ OPC_MoveParent,
6083 : /*17385*/ OPC_CheckType, MVT::i32,
6084 : /*17387*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6085 : /*17389*/ OPC_EmitInteger, MVT::i32, 0,
6086 : /*17392*/ OPC_EmitInteger, MVT::i32, 0,
6087 : /*17395*/ OPC_EmitInteger, MVT::i32, 0,
6088 : /*17398*/ OPC_EmitInteger, MVT::i32, 0,
6089 : /*17401*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6090 : /*17413*/ OPC_EmitInteger, MVT::i32, 0,
6091 : /*17416*/ OPC_EmitInteger, MVT::i32, 0,
6092 : /*17419*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6093 : /*17431*/ OPC_EmitInteger, MVT::i32, 0,
6094 : /*17434*/ OPC_EmitInteger, MVT::i32, 0,
6095 : /*17437*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6096 : /*17449*/ OPC_EmitInteger, MVT::i32, 1,
6097 : /*17452*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6098 : /*17455*/ OPC_EmitInteger, MVT::i32, 0,
6099 : /*17458*/ OPC_EmitInteger, MVT::i32, 0,
6100 : /*17461*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDGE_INT), 0,
6101 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
6102 : // Src: (selectcc:i32 i32:i32:$src0, 0:i32, i32:i32:$src1, i32:i32:$src2, (cond:Other)<<P:Predicate_COND_SGE>>) - Complexity = 8
6103 : // Dst: (CNDGE_INT:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
6104 : /*17486*/ /*Scope*/ 104, /*->17591*/
6105 : /*17487*/ OPC_CheckPredicate, 111, // Predicate_COND_SGT
6106 : /*17489*/ OPC_MoveParent,
6107 : /*17490*/ OPC_CheckType, MVT::i32,
6108 : /*17492*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6109 : /*17494*/ OPC_EmitInteger, MVT::i32, 0,
6110 : /*17497*/ OPC_EmitInteger, MVT::i32, 0,
6111 : /*17500*/ OPC_EmitInteger, MVT::i32, 0,
6112 : /*17503*/ OPC_EmitInteger, MVT::i32, 0,
6113 : /*17506*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6114 : /*17518*/ OPC_EmitInteger, MVT::i32, 0,
6115 : /*17521*/ OPC_EmitInteger, MVT::i32, 0,
6116 : /*17524*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6117 : /*17536*/ OPC_EmitInteger, MVT::i32, 0,
6118 : /*17539*/ OPC_EmitInteger, MVT::i32, 0,
6119 : /*17542*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6120 : /*17554*/ OPC_EmitInteger, MVT::i32, 1,
6121 : /*17557*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6122 : /*17560*/ OPC_EmitInteger, MVT::i32, 0,
6123 : /*17563*/ OPC_EmitInteger, MVT::i32, 0,
6124 : /*17566*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDGT_INT), 0,
6125 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
6126 : // Src: (selectcc:i32 i32:i32:$src0, 0:i32, i32:i32:$src1, i32:i32:$src2, (cond:Other)<<P:Predicate_COND_SGT>>) - Complexity = 8
6127 : // Dst: (CNDGT_INT:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
6128 : /*17591*/ 0, /*End of Scope*/
6129 : /*17592*/ /*Scope*/ 104, /*->17697*/
6130 : /*17593*/ OPC_CheckCondCode, ISD::SETEQ,
6131 : /*17595*/ OPC_MoveParent,
6132 : /*17596*/ OPC_CheckType, MVT::f32,
6133 : /*17598*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6134 : /*17600*/ OPC_EmitInteger, MVT::i32, 0,
6135 : /*17603*/ OPC_EmitInteger, MVT::i32, 0,
6136 : /*17606*/ OPC_EmitInteger, MVT::i32, 0,
6137 : /*17609*/ OPC_EmitInteger, MVT::i32, 0,
6138 : /*17612*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6139 : /*17624*/ OPC_EmitInteger, MVT::i32, 0,
6140 : /*17627*/ OPC_EmitInteger, MVT::i32, 0,
6141 : /*17630*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6142 : /*17642*/ OPC_EmitInteger, MVT::i32, 0,
6143 : /*17645*/ OPC_EmitInteger, MVT::i32, 0,
6144 : /*17648*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6145 : /*17660*/ OPC_EmitInteger, MVT::i32, 1,
6146 : /*17663*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6147 : /*17666*/ OPC_EmitInteger, MVT::i32, 0,
6148 : /*17669*/ OPC_EmitInteger, MVT::i32, 0,
6149 : /*17672*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDE_INT), 0,
6150 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
6151 : // Src: (selectcc:f32 i32:i32:$src0, 0:i32, f32:f32:$src1, f32:f32:$src2, SETEQ:Other) - Complexity = 8
6152 : // Dst: (CNDE_INT:f32 ?:i32:$src0, ?:f32:$src1, ?:f32:$src2)
6153 : /*17697*/ /*Scope*/ 104, /*->17802*/
6154 : /*17698*/ OPC_CheckCondCode, ISD::SETGT,
6155 : /*17700*/ OPC_MoveParent,
6156 : /*17701*/ OPC_CheckType, MVT::f32,
6157 : /*17703*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6158 : /*17705*/ OPC_EmitInteger, MVT::i32, 0,
6159 : /*17708*/ OPC_EmitInteger, MVT::i32, 0,
6160 : /*17711*/ OPC_EmitInteger, MVT::i32, 0,
6161 : /*17714*/ OPC_EmitInteger, MVT::i32, 0,
6162 : /*17717*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6163 : /*17729*/ OPC_EmitInteger, MVT::i32, 0,
6164 : /*17732*/ OPC_EmitInteger, MVT::i32, 0,
6165 : /*17735*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6166 : /*17747*/ OPC_EmitInteger, MVT::i32, 0,
6167 : /*17750*/ OPC_EmitInteger, MVT::i32, 0,
6168 : /*17753*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6169 : /*17765*/ OPC_EmitInteger, MVT::i32, 1,
6170 : /*17768*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6171 : /*17771*/ OPC_EmitInteger, MVT::i32, 0,
6172 : /*17774*/ OPC_EmitInteger, MVT::i32, 0,
6173 : /*17777*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDGT_INT), 0,
6174 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
6175 : // Src: (selectcc:f32 i32:i32:$src0, 0:i32, f32:f32:$src1, f32:f32:$src2, SETGT:Other) - Complexity = 8
6176 : // Dst: (CNDGT_INT:f32 ?:i32:$src0, ?:f32:$src1, ?:f32:$src2)
6177 : /*17802*/ /*Scope*/ 104, /*->17907*/
6178 : /*17803*/ OPC_CheckCondCode, ISD::SETGE,
6179 : /*17805*/ OPC_MoveParent,
6180 : /*17806*/ OPC_CheckType, MVT::f32,
6181 : /*17808*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6182 : /*17810*/ OPC_EmitInteger, MVT::i32, 0,
6183 : /*17813*/ OPC_EmitInteger, MVT::i32, 0,
6184 : /*17816*/ OPC_EmitInteger, MVT::i32, 0,
6185 : /*17819*/ OPC_EmitInteger, MVT::i32, 0,
6186 : /*17822*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6187 : /*17834*/ OPC_EmitInteger, MVT::i32, 0,
6188 : /*17837*/ OPC_EmitInteger, MVT::i32, 0,
6189 : /*17840*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6190 : /*17852*/ OPC_EmitInteger, MVT::i32, 0,
6191 : /*17855*/ OPC_EmitInteger, MVT::i32, 0,
6192 : /*17858*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6193 : /*17870*/ OPC_EmitInteger, MVT::i32, 1,
6194 : /*17873*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6195 : /*17876*/ OPC_EmitInteger, MVT::i32, 0,
6196 : /*17879*/ OPC_EmitInteger, MVT::i32, 0,
6197 : /*17882*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDGE_INT), 0,
6198 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
6199 : // Src: (selectcc:f32 i32:i32:$src0, 0:i32, f32:f32:$src1, f32:f32:$src2, SETGE:Other) - Complexity = 8
6200 : // Dst: (CNDGE_INT:f32 ?:i32:$src0, ?:f32:$src1, ?:f32:$src2)
6201 : /*17907*/ 0, /*End of Scope*/
6202 : /*17908*/ /*Scope*/ 122, /*->18031*/
6203 : /*17909*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6204 : /*17920*/ OPC_RecordChild2, // #1 = $src1
6205 : /*17921*/ OPC_RecordChild3, // #2 = $src2
6206 : /*17922*/ OPC_MoveChild, 4,
6207 : /*17924*/ OPC_CheckOpcode, TARGET_VAL(ISD::CONDCODE),
6208 : /*17927*/ OPC_CheckPredicate, 111, // Predicate_COND_SGT
6209 : /*17929*/ OPC_MoveParent,
6210 : /*17930*/ OPC_CheckType, MVT::i32,
6211 : /*17932*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6212 : /*17934*/ OPC_EmitInteger, MVT::i32, 0,
6213 : /*17937*/ OPC_EmitInteger, MVT::i32, 0,
6214 : /*17940*/ OPC_EmitInteger, MVT::i32, 0,
6215 : /*17943*/ OPC_EmitInteger, MVT::i32, 0,
6216 : /*17946*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6217 : /*17958*/ OPC_EmitInteger, MVT::i32, 0,
6218 : /*17961*/ OPC_EmitInteger, MVT::i32, 0,
6219 : /*17964*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6220 : /*17976*/ OPC_EmitInteger, MVT::i32, 0,
6221 : /*17979*/ OPC_EmitInteger, MVT::i32, 0,
6222 : /*17982*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6223 : /*17994*/ OPC_EmitInteger, MVT::i32, 1,
6224 : /*17997*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6225 : /*18000*/ OPC_EmitInteger, MVT::i32, 0,
6226 : /*18003*/ OPC_EmitInteger, MVT::i32, 0,
6227 : /*18006*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CNDGE_INT), 0,
6228 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
6229 : // Src: (selectcc:i32 i32:i32:$src0, -1:i32, i32:i32:$src1, i32:i32:$src2, (cond:Other)<<P:Predicate_COND_SGT>>) - Complexity = 8
6230 : // Dst: (CNDGE_INT:i32 ?:i32:$src0, ?:i32:$src1, ?:i32:$src2)
6231 : /*18031*/ 0, /*End of Scope*/
6232 : /*18032*/ 0, /*End of Scope*/
6233 : /*18033*/ /*SwitchOpcode*/ 25|128,1/*153*/, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->18190
6234 : /*18037*/ OPC_RecordMemRef,
6235 : /*18038*/ OPC_RecordNode, // #0 = 'si_atomic_cmp_swap_glue' chained node
6236 : /*18039*/ OPC_Scope, 62, /*->18103*/ // 2 children in Scope
6237 : /*18041*/ OPC_CaptureGlueInput,
6238 : /*18042*/ OPC_RecordChild1, // #1 = $DS1Addr1Offset:ptr:offset
6239 : /*18043*/ OPC_RecordChild2, // #2 = $cmp
6240 : /*18044*/ OPC_RecordChild3, // #3 = $swap
6241 : /*18045*/ OPC_SwitchType /*2 cases */, 26, MVT::i32,// ->18074
6242 : /*18048*/ OPC_CheckPredicate, 112, // Predicate_si_atomic_cmp_swap_32_local
6243 : /*18050*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6244 : /*18052*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #4 #5
6245 : /*18055*/ OPC_EmitMergeInputChains1_0,
6246 : /*18056*/ OPC_EmitNodeXForm, 0, 5, // as_i16imm
6247 : /*18059*/ OPC_EmitInteger, MVT::i1, 0,
6248 : /*18062*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_CMPST_RTN_B32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
6249 : 1/*#VTs*/, MVT::i32, 5/*#Ops*/, 4, 2, 3, 6, 7,
6250 : // Src: (si_atomic_cmp_swap_glue:i32 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i32:i32:$cmp, i32:i32:$swap)<<P:Predicate_si_atomic_cmp_swap_32_local>> - Complexity = 13
6251 : // Dst: (DS_CMPST_RTN_B32:i32 ?:i32:$ptr, ?:i32:$cmp, ?:i32:$swap, (as_i16imm:i16 ?:i32:$offset), 0:i1)
6252 : /*18074*/ /*SwitchType*/ 26, MVT::i64,// ->18102
6253 : /*18076*/ OPC_CheckPredicate, 113, // Predicate_si_atomic_cmp_swap_64_local
6254 : /*18078*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6255 : /*18080*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectDS1Addr1Offset:$ #4 #5
6256 : /*18083*/ OPC_EmitMergeInputChains1_0,
6257 : /*18084*/ OPC_EmitNodeXForm, 0, 5, // as_i16imm
6258 : /*18087*/ OPC_EmitInteger, MVT::i1, 0,
6259 : /*18090*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DS_CMPST_RTN_B64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_MemRefs,
6260 : 1/*#VTs*/, MVT::i64, 5/*#Ops*/, 4, 2, 3, 6, 7,
6261 : // Src: (si_atomic_cmp_swap_glue:i64 (DS1Addr1Offset:iPTR i32:i32:$ptr, i32:i32:$offset), i64:i64:$cmp, i64:i64:$swap)<<P:Predicate_si_atomic_cmp_swap_64_local>> - Complexity = 13
6262 : // Dst: (DS_CMPST_RTN_B64:i64 ?:i32:$ptr, ?:i64:$cmp, ?:i64:$swap, (as_i16imm:i16 ?:i32:$offset), 0:i1)
6263 : /*18102*/ 0, // EndSwitchType
6264 : /*18103*/ /*Scope*/ 85, /*->18189*/
6265 : /*18104*/ OPC_RecordChild1, // #1 = $src0
6266 : /*18105*/ OPC_CheckChild1Type, MVT::i32,
6267 : /*18107*/ OPC_RecordChild2, // #2 = $src1
6268 : /*18108*/ OPC_RecordChild3, // #3 = $src2
6269 : /*18109*/ OPC_CheckPredicate, 114, // Predicate_atomic_cmp_swap_32_local
6270 : /*18111*/ OPC_CheckType, MVT::i32,
6271 : /*18113*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
6272 : /*18115*/ OPC_EmitMergeInputChains1_0,
6273 : /*18116*/ OPC_EmitInteger, MVT::i32, 0,
6274 : /*18119*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6275 : /*18131*/ OPC_EmitInteger, MVT::i32, 0,
6276 : /*18134*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6277 : /*18146*/ OPC_EmitInteger, MVT::i32, 0,
6278 : /*18149*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6279 : /*18161*/ OPC_EmitInteger, MVT::i32, 1,
6280 : /*18164*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6281 : /*18167*/ OPC_EmitInteger, MVT::i32, 0,
6282 : /*18170*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LDS_CMPST_RET), 0|OPFL_Chain|OPFL_MemRefs,
6283 : 1/*#VTs*/, MVT::i32, 12/*#Ops*/, 1, 4, 5, 2, 6, 7, 3, 8, 9, 10, 11, 12,
6284 : // Src: (atomic_cmp_swap:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)<<P:Predicate_atomic_cmp_swap_32_local>> - Complexity = 4
6285 : // Dst: (LDS_CMPST_RET:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
6286 : /*18189*/ 0, /*End of Scope*/
6287 : /*18190*/ /*SwitchOpcode*/ 56|128,2/*312*/, TARGET_VAL(ISD::AND),// ->18506
6288 : /*18194*/ OPC_Scope, 30|128,1/*158*/, /*->18355*/ // 2 children in Scope
6289 : /*18197*/ OPC_MoveChild, 0,
6290 : /*18199*/ OPC_CheckOpcode, TARGET_VAL(ISD::SRL),
6291 : /*18202*/ OPC_RecordChild0, // #0 = $src
6292 : /*18203*/ OPC_RecordChild1, // #1 = $rshift
6293 : /*18204*/ OPC_CheckChild1Type, MVT::i32,
6294 : /*18206*/ OPC_MoveParent,
6295 : /*18207*/ OPC_RecordChild1, // #2 = $mask
6296 : /*18208*/ OPC_MoveChild, 1,
6297 : /*18210*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
6298 : /*18213*/ OPC_CheckPredicate, 115, // Predicate_IMMZeroBasedBitfieldMask
6299 : /*18215*/ OPC_MoveParent,
6300 : /*18216*/ OPC_CheckType, MVT::i32,
6301 : /*18218*/ OPC_Scope, 23, /*->18243*/ // 2 children in Scope
6302 : /*18220*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6303 : /*18222*/ OPC_EmitNodeXForm, 5, 2, // IMMPopCount
6304 : /*18225*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
6305 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
6306 : /*18233*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFE_U32), 0,
6307 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 4,
6308 : // Src: (and:i32 (srl:i32 i32:i32:$src, i32:i32:$rshift), (imm:i32)<<P:Predicate_IMMZeroBasedBitfieldMask>>:$mask) - Complexity = 10
6309 : // Dst: (V_BFE_U32:i32 ?:i32:$src, ?:i32:$rshift, (S_MOV_B32:i32 (IMMPopCount:i32 ?:i32:$mask)))
6310 : /*18243*/ /*Scope*/ 110, /*->18354*/
6311 : /*18244*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
6312 : /*18246*/ OPC_EmitInteger, MVT::i32, 0,
6313 : /*18249*/ OPC_EmitInteger, MVT::i32, 0,
6314 : /*18252*/ OPC_EmitInteger, MVT::i32, 0,
6315 : /*18255*/ OPC_EmitInteger, MVT::i32, 0,
6316 : /*18258*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6317 : /*18270*/ OPC_EmitInteger, MVT::i32, 0,
6318 : /*18273*/ OPC_EmitInteger, MVT::i32, 0,
6319 : /*18276*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6320 : /*18288*/ OPC_EmitNodeXForm, 5, 2, // IMMPopCount
6321 : /*18291*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MOV_IMM_I32), 0,
6322 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 11, // Results = #12
6323 : /*18299*/ OPC_EmitInteger, MVT::i32, 0,
6324 : /*18302*/ OPC_EmitInteger, MVT::i32, 0,
6325 : /*18305*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6326 : /*18317*/ OPC_EmitInteger, MVT::i32, 1,
6327 : /*18320*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6328 : /*18323*/ OPC_EmitInteger, MVT::i32, 0,
6329 : /*18326*/ OPC_EmitInteger, MVT::i32, 0,
6330 : /*18329*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFE_UINT_eg), 0,
6331 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18, 19,
6332 : // Src: (and:i32 (srl:i32 i32:i32:$src, i32:i32:$rshift), (imm:i32)<<P:Predicate_IMMZeroBasedBitfieldMask>>:$mask) - Complexity = 10
6333 : // Dst: (BFE_UINT_eg:i32 ?:i32:$src, ?:i32:$rshift, (MOV_IMM_I32:i32 (IMMPopCount:i32 ?:i32:$mask)))
6334 : /*18354*/ 0, /*End of Scope*/
6335 : /*18355*/ /*Scope*/ 20|128,1/*148*/, /*->18505*/
6336 : /*18357*/ OPC_RecordChild0, // #0 = $src0
6337 : /*18358*/ OPC_RecordChild1, // #1 = $src1
6338 : /*18359*/ OPC_SwitchType /*3 cases */, 116, MVT::i32,// ->18478
6339 : /*18362*/ OPC_Scope, 101, /*->18465*/ // 2 children in Scope
6340 : /*18364*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6341 : /*18366*/ OPC_EmitInteger, MVT::i32, 0,
6342 : /*18369*/ OPC_EmitInteger, MVT::i32, 0,
6343 : /*18372*/ OPC_EmitInteger, MVT::i32, 1,
6344 : /*18375*/ OPC_EmitInteger, MVT::i32, 0,
6345 : /*18378*/ OPC_EmitInteger, MVT::i32, 0,
6346 : /*18381*/ OPC_EmitInteger, MVT::i32, 0,
6347 : /*18384*/ OPC_EmitInteger, MVT::i32, 0,
6348 : /*18387*/ OPC_EmitInteger, MVT::i32, 0,
6349 : /*18390*/ OPC_EmitInteger, MVT::i32, 0,
6350 : /*18393*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6351 : /*18405*/ OPC_EmitInteger, MVT::i32, 0,
6352 : /*18408*/ OPC_EmitInteger, MVT::i32, 0,
6353 : /*18411*/ OPC_EmitInteger, MVT::i32, 0,
6354 : /*18414*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6355 : /*18426*/ OPC_EmitInteger, MVT::i32, 1,
6356 : /*18429*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6357 : /*18432*/ OPC_EmitInteger, MVT::i32, 0,
6358 : /*18435*/ OPC_EmitInteger, MVT::i32, 0,
6359 : /*18438*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::AND_INT), 0,
6360 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
6361 : // Src: (and:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
6362 : // Dst: (AND_INT:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
6363 : /*18465*/ /*Scope*/ 11, /*->18477*/
6364 : /*18466*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
6365 : /*18468*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_AND_B32), 0,
6366 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6367 : // Src: (and:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
6368 : // Dst: (S_AND_B32:i32 i32:i32:$src0, i32:i32:$src1)
6369 : /*18477*/ 0, /*End of Scope*/
6370 : /*18478*/ /*SwitchType*/ 11, MVT::i64,// ->18491
6371 : /*18480*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
6372 : /*18482*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_AND_B64), 0,
6373 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 0, 1,
6374 : // Src: (and:i64 i64:i64:$src0, i64:i64:$src1) - Complexity = 3
6375 : // Dst: (S_AND_B64:i64 i64:i64:$src0, i64:i64:$src1)
6376 : /*18491*/ /*SwitchType*/ 11, MVT::i1,// ->18504
6377 : /*18493*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6378 : /*18495*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_AND_B64), 0,
6379 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
6380 : // Src: (and:i1 i1:i1:$src0, i1:i1:$src1) - Complexity = 3
6381 : // Dst: (S_AND_B64:i1 ?:i1:$src0, ?:i1:$src1)
6382 : /*18504*/ 0, // EndSwitchType
6383 : /*18505*/ 0, /*End of Scope*/
6384 : /*18506*/ /*SwitchOpcode*/ 93|128,10/*1373*/, TARGET_VAL(ISD::XOR),// ->19883
6385 : /*18510*/ OPC_Scope, 83|128,1/*211*/, /*->18724*/ // 5 children in Scope
6386 : /*18513*/ OPC_RecordChild0, // #0 = $z
6387 : /*18514*/ OPC_MoveChild, 1,
6388 : /*18516*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
6389 : /*18519*/ OPC_Scope, 23|128,1/*151*/, /*->18673*/ // 2 children in Scope
6390 : /*18522*/ OPC_RecordChild0, // #1 = $x
6391 : /*18523*/ OPC_MoveChild, 1,
6392 : /*18525*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
6393 : /*18528*/ OPC_Scope, 122, /*->18652*/ // 2 children in Scope
6394 : /*18530*/ OPC_RecordChild0, // #2 = $y
6395 : /*18531*/ OPC_CheckChild1Same, 0,
6396 : /*18533*/ OPC_MoveParent,
6397 : /*18534*/ OPC_MoveParent,
6398 : /*18535*/ OPC_CheckType, MVT::i32,
6399 : /*18537*/ OPC_Scope, 99, /*->18638*/ // 2 children in Scope
6400 : /*18539*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
6401 : /*18541*/ OPC_EmitInteger, MVT::i32, 0,
6402 : /*18544*/ OPC_EmitInteger, MVT::i32, 0,
6403 : /*18547*/ OPC_EmitInteger, MVT::i32, 0,
6404 : /*18550*/ OPC_EmitInteger, MVT::i32, 0,
6405 : /*18553*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6406 : /*18565*/ OPC_EmitInteger, MVT::i32, 0,
6407 : /*18568*/ OPC_EmitInteger, MVT::i32, 0,
6408 : /*18571*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6409 : /*18583*/ OPC_EmitInteger, MVT::i32, 0,
6410 : /*18586*/ OPC_EmitInteger, MVT::i32, 0,
6411 : /*18589*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6412 : /*18601*/ OPC_EmitInteger, MVT::i32, 1,
6413 : /*18604*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6414 : /*18607*/ OPC_EmitInteger, MVT::i32, 0,
6415 : /*18610*/ OPC_EmitInteger, MVT::i32, 0,
6416 : /*18613*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
6417 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 1, 5, 6, 7, 2, 8, 9, 10, 0, 11, 12, 13, 14, 15, 16, 17,
6418 : // Src: (xor:i32 i32:i32:$z, (and:i32 i32:i32:$x, (xor:i32 i32:i32:$y, i32:i32:$z))) - Complexity = 9
6419 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6420 : /*18638*/ /*Scope*/ 12, /*->18651*/
6421 : /*18639*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6422 : /*18641*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
6423 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 2, 0,
6424 : // Src: (xor:i32 i32:i32:$z, (and:i32 i32:i32:$x, (xor:i32 i32:i32:$y, i32:i32:$z))) - Complexity = 9
6425 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6426 : /*18651*/ 0, /*End of Scope*/
6427 : /*18652*/ /*Scope*/ 19, /*->18672*/
6428 : /*18653*/ OPC_CheckChild0Same, 0,
6429 : /*18655*/ OPC_RecordChild1, // #2 = $y
6430 : /*18656*/ OPC_MoveParent,
6431 : /*18657*/ OPC_MoveParent,
6432 : /*18658*/ OPC_CheckType, MVT::i32,
6433 : /*18660*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6434 : /*18662*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
6435 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 2, 0,
6436 : // Src: (xor:i32 i32:i32:$z, (and:i32 i32:i32:$x, (xor:i32 i32:i32:$z, i32:i32:$y))) - Complexity = 9
6437 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6438 : /*18672*/ 0, /*End of Scope*/
6439 : /*18673*/ /*Scope*/ 49, /*->18723*/
6440 : /*18674*/ OPC_MoveChild, 0,
6441 : /*18676*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
6442 : /*18679*/ OPC_Scope, 20, /*->18701*/ // 2 children in Scope
6443 : /*18681*/ OPC_RecordChild0, // #1 = $y
6444 : /*18682*/ OPC_CheckChild1Same, 0,
6445 : /*18684*/ OPC_MoveParent,
6446 : /*18685*/ OPC_RecordChild1, // #2 = $x
6447 : /*18686*/ OPC_MoveParent,
6448 : /*18687*/ OPC_CheckType, MVT::i32,
6449 : /*18689*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6450 : /*18691*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
6451 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 1, 0,
6452 : // Src: (xor:i32 i32:i32:$z, (and:i32 (xor:i32 i32:i32:$y, i32:i32:$z), i32:i32:$x)) - Complexity = 9
6453 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6454 : /*18701*/ /*Scope*/ 20, /*->18722*/
6455 : /*18702*/ OPC_CheckChild0Same, 0,
6456 : /*18704*/ OPC_RecordChild1, // #1 = $y
6457 : /*18705*/ OPC_MoveParent,
6458 : /*18706*/ OPC_RecordChild1, // #2 = $x
6459 : /*18707*/ OPC_MoveParent,
6460 : /*18708*/ OPC_CheckType, MVT::i32,
6461 : /*18710*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6462 : /*18712*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
6463 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 1, 0,
6464 : // Src: (xor:i32 i32:i32:$z, (and:i32 (xor:i32 i32:i32:$z, i32:i32:$y), i32:i32:$x)) - Complexity = 9
6465 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6466 : /*18722*/ 0, /*End of Scope*/
6467 : /*18723*/ 0, /*End of Scope*/
6468 : /*18724*/ /*Scope*/ 97, /*->18822*/
6469 : /*18725*/ OPC_MoveChild, 0,
6470 : /*18727*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
6471 : /*18730*/ OPC_Scope, 44, /*->18776*/ // 2 children in Scope
6472 : /*18732*/ OPC_RecordChild0, // #0 = $x
6473 : /*18733*/ OPC_MoveChild, 1,
6474 : /*18735*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
6475 : /*18738*/ OPC_RecordChild0, // #1 = $y
6476 : /*18739*/ OPC_RecordChild1, // #2 = $z
6477 : /*18740*/ OPC_MoveParent,
6478 : /*18741*/ OPC_MoveParent,
6479 : /*18742*/ OPC_CheckType, MVT::i32,
6480 : /*18744*/ OPC_Scope, 14, /*->18760*/ // 2 children in Scope
6481 : /*18746*/ OPC_CheckChild1Same, 2,
6482 : /*18748*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6483 : /*18750*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
6484 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
6485 : // Src: (xor:i32 (and:i32 i32:i32:$x, (xor:i32 i32:i32:$y, i32:i32:$z)), i32:i32:$z) - Complexity = 9
6486 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6487 : /*18760*/ /*Scope*/ 14, /*->18775*/
6488 : /*18761*/ OPC_CheckChild1Same, 1,
6489 : /*18763*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6490 : /*18765*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
6491 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 2, 1,
6492 : // Src: (xor:i32 (and:i32 i32:i32:$x, (xor:i32 i32:i32:$z, i32:i32:$y)), i32:i32:$z) - Complexity = 9
6493 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6494 : /*18775*/ 0, /*End of Scope*/
6495 : /*18776*/ /*Scope*/ 44, /*->18821*/
6496 : /*18777*/ OPC_MoveChild, 0,
6497 : /*18779*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
6498 : /*18782*/ OPC_RecordChild0, // #0 = $y
6499 : /*18783*/ OPC_RecordChild1, // #1 = $z
6500 : /*18784*/ OPC_MoveParent,
6501 : /*18785*/ OPC_RecordChild1, // #2 = $x
6502 : /*18786*/ OPC_MoveParent,
6503 : /*18787*/ OPC_CheckType, MVT::i32,
6504 : /*18789*/ OPC_Scope, 14, /*->18805*/ // 2 children in Scope
6505 : /*18791*/ OPC_CheckChild1Same, 1,
6506 : /*18793*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6507 : /*18795*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
6508 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 0, 1,
6509 : // Src: (xor:i32 (and:i32 (xor:i32 i32:i32:$y, i32:i32:$z), i32:i32:$x), i32:i32:$z) - Complexity = 9
6510 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6511 : /*18805*/ /*Scope*/ 14, /*->18820*/
6512 : /*18806*/ OPC_CheckChild1Same, 0,
6513 : /*18808*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6514 : /*18810*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
6515 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 1, 0,
6516 : // Src: (xor:i32 (and:i32 (xor:i32 i32:i32:$z, i32:i32:$y), i32:i32:$x), i32:i32:$z) - Complexity = 9
6517 : // Dst: (V_BFI_B32:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6518 : /*18820*/ 0, /*End of Scope*/
6519 : /*18821*/ 0, /*End of Scope*/
6520 : /*18822*/ /*Scope*/ 90|128,2/*346*/, /*->19170*/
6521 : /*18824*/ OPC_RecordChild0, // #0 = $z
6522 : /*18825*/ OPC_MoveChild, 1,
6523 : /*18827*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
6524 : /*18830*/ OPC_Scope, 112, /*->18944*/ // 2 children in Scope
6525 : /*18832*/ OPC_RecordChild0, // #1 = $x
6526 : /*18833*/ OPC_MoveChild, 1,
6527 : /*18835*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
6528 : /*18838*/ OPC_CheckChild0Same, 0,
6529 : /*18840*/ OPC_RecordChild1, // #2 = $y
6530 : /*18841*/ OPC_MoveParent,
6531 : /*18842*/ OPC_MoveParent,
6532 : /*18843*/ OPC_CheckType, MVT::i32,
6533 : /*18845*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
6534 : /*18847*/ OPC_EmitInteger, MVT::i32, 0,
6535 : /*18850*/ OPC_EmitInteger, MVT::i32, 0,
6536 : /*18853*/ OPC_EmitInteger, MVT::i32, 0,
6537 : /*18856*/ OPC_EmitInteger, MVT::i32, 0,
6538 : /*18859*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6539 : /*18871*/ OPC_EmitInteger, MVT::i32, 0,
6540 : /*18874*/ OPC_EmitInteger, MVT::i32, 0,
6541 : /*18877*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6542 : /*18889*/ OPC_EmitInteger, MVT::i32, 0,
6543 : /*18892*/ OPC_EmitInteger, MVT::i32, 0,
6544 : /*18895*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6545 : /*18907*/ OPC_EmitInteger, MVT::i32, 1,
6546 : /*18910*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6547 : /*18913*/ OPC_EmitInteger, MVT::i32, 0,
6548 : /*18916*/ OPC_EmitInteger, MVT::i32, 0,
6549 : /*18919*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
6550 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 1, 5, 6, 7, 2, 8, 9, 10, 0, 11, 12, 13, 14, 15, 16, 17,
6551 : // Src: (xor:i32 i32:i32:$z, (and:i32 i32:i32:$x, (xor:i32 i32:i32:$z, i32:i32:$y))) - Complexity = 9
6552 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6553 : /*18944*/ /*Scope*/ 95|128,1/*223*/, /*->19169*/
6554 : /*18946*/ OPC_MoveChild, 0,
6555 : /*18948*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
6556 : /*18951*/ OPC_Scope, 107, /*->19060*/ // 2 children in Scope
6557 : /*18953*/ OPC_RecordChild0, // #1 = $y
6558 : /*18954*/ OPC_CheckChild1Same, 0,
6559 : /*18956*/ OPC_MoveParent,
6560 : /*18957*/ OPC_RecordChild1, // #2 = $x
6561 : /*18958*/ OPC_MoveParent,
6562 : /*18959*/ OPC_CheckType, MVT::i32,
6563 : /*18961*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
6564 : /*18963*/ OPC_EmitInteger, MVT::i32, 0,
6565 : /*18966*/ OPC_EmitInteger, MVT::i32, 0,
6566 : /*18969*/ OPC_EmitInteger, MVT::i32, 0,
6567 : /*18972*/ OPC_EmitInteger, MVT::i32, 0,
6568 : /*18975*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6569 : /*18987*/ OPC_EmitInteger, MVT::i32, 0,
6570 : /*18990*/ OPC_EmitInteger, MVT::i32, 0,
6571 : /*18993*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6572 : /*19005*/ OPC_EmitInteger, MVT::i32, 0,
6573 : /*19008*/ OPC_EmitInteger, MVT::i32, 0,
6574 : /*19011*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6575 : /*19023*/ OPC_EmitInteger, MVT::i32, 1,
6576 : /*19026*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6577 : /*19029*/ OPC_EmitInteger, MVT::i32, 0,
6578 : /*19032*/ OPC_EmitInteger, MVT::i32, 0,
6579 : /*19035*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
6580 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 2, 5, 6, 7, 1, 8, 9, 10, 0, 11, 12, 13, 14, 15, 16, 17,
6581 : // Src: (xor:i32 i32:i32:$z, (and:i32 (xor:i32 i32:i32:$y, i32:i32:$z), i32:i32:$x)) - Complexity = 9
6582 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6583 : /*19060*/ /*Scope*/ 107, /*->19168*/
6584 : /*19061*/ OPC_CheckChild0Same, 0,
6585 : /*19063*/ OPC_RecordChild1, // #1 = $y
6586 : /*19064*/ OPC_MoveParent,
6587 : /*19065*/ OPC_RecordChild1, // #2 = $x
6588 : /*19066*/ OPC_MoveParent,
6589 : /*19067*/ OPC_CheckType, MVT::i32,
6590 : /*19069*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
6591 : /*19071*/ OPC_EmitInteger, MVT::i32, 0,
6592 : /*19074*/ OPC_EmitInteger, MVT::i32, 0,
6593 : /*19077*/ OPC_EmitInteger, MVT::i32, 0,
6594 : /*19080*/ OPC_EmitInteger, MVT::i32, 0,
6595 : /*19083*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6596 : /*19095*/ OPC_EmitInteger, MVT::i32, 0,
6597 : /*19098*/ OPC_EmitInteger, MVT::i32, 0,
6598 : /*19101*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6599 : /*19113*/ OPC_EmitInteger, MVT::i32, 0,
6600 : /*19116*/ OPC_EmitInteger, MVT::i32, 0,
6601 : /*19119*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6602 : /*19131*/ OPC_EmitInteger, MVT::i32, 1,
6603 : /*19134*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6604 : /*19137*/ OPC_EmitInteger, MVT::i32, 0,
6605 : /*19140*/ OPC_EmitInteger, MVT::i32, 0,
6606 : /*19143*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
6607 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 2, 5, 6, 7, 1, 8, 9, 10, 0, 11, 12, 13, 14, 15, 16, 17,
6608 : // Src: (xor:i32 i32:i32:$z, (and:i32 (xor:i32 i32:i32:$z, i32:i32:$y), i32:i32:$x)) - Complexity = 9
6609 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6610 : /*19168*/ 0, /*End of Scope*/
6611 : /*19169*/ 0, /*End of Scope*/
6612 : /*19170*/ /*Scope*/ 63|128,3/*447*/, /*->19619*/
6613 : /*19172*/ OPC_MoveChild, 0,
6614 : /*19174*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
6615 : /*19177*/ OPC_Scope, 90|128,1/*218*/, /*->19398*/ // 2 children in Scope
6616 : /*19180*/ OPC_RecordChild0, // #0 = $x
6617 : /*19181*/ OPC_MoveChild, 1,
6618 : /*19183*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
6619 : /*19186*/ OPC_RecordChild0, // #1 = $y
6620 : /*19187*/ OPC_RecordChild1, // #2 = $z
6621 : /*19188*/ OPC_MoveParent,
6622 : /*19189*/ OPC_MoveParent,
6623 : /*19190*/ OPC_CheckType, MVT::i32,
6624 : /*19192*/ OPC_Scope, 101, /*->19295*/ // 2 children in Scope
6625 : /*19194*/ OPC_CheckChild1Same, 2,
6626 : /*19196*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
6627 : /*19198*/ OPC_EmitInteger, MVT::i32, 0,
6628 : /*19201*/ OPC_EmitInteger, MVT::i32, 0,
6629 : /*19204*/ OPC_EmitInteger, MVT::i32, 0,
6630 : /*19207*/ OPC_EmitInteger, MVT::i32, 0,
6631 : /*19210*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6632 : /*19222*/ OPC_EmitInteger, MVT::i32, 0,
6633 : /*19225*/ OPC_EmitInteger, MVT::i32, 0,
6634 : /*19228*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6635 : /*19240*/ OPC_EmitInteger, MVT::i32, 0,
6636 : /*19243*/ OPC_EmitInteger, MVT::i32, 0,
6637 : /*19246*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6638 : /*19258*/ OPC_EmitInteger, MVT::i32, 1,
6639 : /*19261*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6640 : /*19264*/ OPC_EmitInteger, MVT::i32, 0,
6641 : /*19267*/ OPC_EmitInteger, MVT::i32, 0,
6642 : /*19270*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
6643 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
6644 : // Src: (xor:i32 (and:i32 i32:i32:$x, (xor:i32 i32:i32:$y, i32:i32:$z)), i32:i32:$z) - Complexity = 9
6645 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6646 : /*19295*/ /*Scope*/ 101, /*->19397*/
6647 : /*19296*/ OPC_CheckChild1Same, 1,
6648 : /*19298*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
6649 : /*19300*/ OPC_EmitInteger, MVT::i32, 0,
6650 : /*19303*/ OPC_EmitInteger, MVT::i32, 0,
6651 : /*19306*/ OPC_EmitInteger, MVT::i32, 0,
6652 : /*19309*/ OPC_EmitInteger, MVT::i32, 0,
6653 : /*19312*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6654 : /*19324*/ OPC_EmitInteger, MVT::i32, 0,
6655 : /*19327*/ OPC_EmitInteger, MVT::i32, 0,
6656 : /*19330*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6657 : /*19342*/ OPC_EmitInteger, MVT::i32, 0,
6658 : /*19345*/ OPC_EmitInteger, MVT::i32, 0,
6659 : /*19348*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6660 : /*19360*/ OPC_EmitInteger, MVT::i32, 1,
6661 : /*19363*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6662 : /*19366*/ OPC_EmitInteger, MVT::i32, 0,
6663 : /*19369*/ OPC_EmitInteger, MVT::i32, 0,
6664 : /*19372*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
6665 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 2, 8, 9, 10, 1, 11, 12, 13, 14, 15, 16, 17,
6666 : // Src: (xor:i32 (and:i32 i32:i32:$x, (xor:i32 i32:i32:$z, i32:i32:$y)), i32:i32:$z) - Complexity = 9
6667 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6668 : /*19397*/ 0, /*End of Scope*/
6669 : /*19398*/ /*Scope*/ 90|128,1/*218*/, /*->19618*/
6670 : /*19400*/ OPC_MoveChild, 0,
6671 : /*19402*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
6672 : /*19405*/ OPC_RecordChild0, // #0 = $y
6673 : /*19406*/ OPC_RecordChild1, // #1 = $z
6674 : /*19407*/ OPC_MoveParent,
6675 : /*19408*/ OPC_RecordChild1, // #2 = $x
6676 : /*19409*/ OPC_MoveParent,
6677 : /*19410*/ OPC_CheckType, MVT::i32,
6678 : /*19412*/ OPC_Scope, 101, /*->19515*/ // 2 children in Scope
6679 : /*19414*/ OPC_CheckChild1Same, 1,
6680 : /*19416*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
6681 : /*19418*/ OPC_EmitInteger, MVT::i32, 0,
6682 : /*19421*/ OPC_EmitInteger, MVT::i32, 0,
6683 : /*19424*/ OPC_EmitInteger, MVT::i32, 0,
6684 : /*19427*/ OPC_EmitInteger, MVT::i32, 0,
6685 : /*19430*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6686 : /*19442*/ OPC_EmitInteger, MVT::i32, 0,
6687 : /*19445*/ OPC_EmitInteger, MVT::i32, 0,
6688 : /*19448*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6689 : /*19460*/ OPC_EmitInteger, MVT::i32, 0,
6690 : /*19463*/ OPC_EmitInteger, MVT::i32, 0,
6691 : /*19466*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6692 : /*19478*/ OPC_EmitInteger, MVT::i32, 1,
6693 : /*19481*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6694 : /*19484*/ OPC_EmitInteger, MVT::i32, 0,
6695 : /*19487*/ OPC_EmitInteger, MVT::i32, 0,
6696 : /*19490*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
6697 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 2, 5, 6, 7, 0, 8, 9, 10, 1, 11, 12, 13, 14, 15, 16, 17,
6698 : // Src: (xor:i32 (and:i32 (xor:i32 i32:i32:$y, i32:i32:$z), i32:i32:$x), i32:i32:$z) - Complexity = 9
6699 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6700 : /*19515*/ /*Scope*/ 101, /*->19617*/
6701 : /*19516*/ OPC_CheckChild1Same, 0,
6702 : /*19518*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
6703 : /*19520*/ OPC_EmitInteger, MVT::i32, 0,
6704 : /*19523*/ OPC_EmitInteger, MVT::i32, 0,
6705 : /*19526*/ OPC_EmitInteger, MVT::i32, 0,
6706 : /*19529*/ OPC_EmitInteger, MVT::i32, 0,
6707 : /*19532*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6708 : /*19544*/ OPC_EmitInteger, MVT::i32, 0,
6709 : /*19547*/ OPC_EmitInteger, MVT::i32, 0,
6710 : /*19550*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6711 : /*19562*/ OPC_EmitInteger, MVT::i32, 0,
6712 : /*19565*/ OPC_EmitInteger, MVT::i32, 0,
6713 : /*19568*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6714 : /*19580*/ OPC_EmitInteger, MVT::i32, 1,
6715 : /*19583*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6716 : /*19586*/ OPC_EmitInteger, MVT::i32, 0,
6717 : /*19589*/ OPC_EmitInteger, MVT::i32, 0,
6718 : /*19592*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
6719 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 2, 5, 6, 7, 1, 8, 9, 10, 0, 11, 12, 13, 14, 15, 16, 17,
6720 : // Src: (xor:i32 (and:i32 (xor:i32 i32:i32:$z, i32:i32:$y), i32:i32:$x), i32:i32:$z) - Complexity = 9
6721 : // Dst: (BFI_INT_eg:i32 ?:i32:$x, ?:i32:$y, ?:i32:$z)
6722 : /*19617*/ 0, /*End of Scope*/
6723 : /*19618*/ 0, /*End of Scope*/
6724 : /*19619*/ /*Scope*/ 5|128,2/*261*/, /*->19882*/
6725 : /*19621*/ OPC_RecordChild0, // #0 = $src0
6726 : /*19622*/ OPC_Scope, 108, /*->19732*/ // 2 children in Scope
6727 : /*19624*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6728 : /*19635*/ OPC_SwitchType /*2 cases */, 81, MVT::i32,// ->19719
6729 : /*19638*/ OPC_Scope, 67, /*->19707*/ // 2 children in Scope
6730 : /*19640*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6731 : /*19642*/ OPC_EmitInteger, MVT::i32, 1,
6732 : /*19645*/ OPC_EmitInteger, MVT::i32, 0,
6733 : /*19648*/ OPC_EmitInteger, MVT::i32, 0,
6734 : /*19651*/ OPC_EmitInteger, MVT::i32, 0,
6735 : /*19654*/ OPC_EmitInteger, MVT::i32, 0,
6736 : /*19657*/ OPC_EmitInteger, MVT::i32, 0,
6737 : /*19660*/ OPC_EmitInteger, MVT::i32, 0,
6738 : /*19663*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6739 : /*19675*/ OPC_EmitInteger, MVT::i32, 1,
6740 : /*19678*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6741 : /*19681*/ OPC_EmitInteger, MVT::i32, 0,
6742 : /*19684*/ OPC_EmitInteger, MVT::i32, 0,
6743 : /*19687*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::NOT_INT), 0,
6744 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
6745 : // Src: (xor:i32 R600_Reg32:i32:$src0, -1:i32) - Complexity = 8
6746 : // Dst: (NOT_INT:i32 R600_Reg32:i32:$src0)
6747 : /*19707*/ /*Scope*/ 10, /*->19718*/
6748 : /*19708*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
6749 : /*19710*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_NOT_B32), 0,
6750 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0,
6751 : // Src: (xor:i32 i32:i32:$src0, -1:i32) - Complexity = 8
6752 : // Dst: (S_NOT_B32:i32 i32:i32:$src0)
6753 : /*19718*/ 0, /*End of Scope*/
6754 : /*19719*/ /*SwitchType*/ 10, MVT::i64,// ->19731
6755 : /*19721*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
6756 : /*19723*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_NOT_B64), 0,
6757 : 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 0,
6758 : // Src: (xor:i64 i64:i64:$src0, -1:i64) - Complexity = 8
6759 : // Dst: (S_NOT_B64:i64 i64:i64:$src0)
6760 : /*19731*/ 0, // EndSwitchType
6761 : /*19732*/ /*Scope*/ 19|128,1/*147*/, /*->19881*/
6762 : /*19734*/ OPC_RecordChild1, // #1 = $src1
6763 : /*19735*/ OPC_SwitchType /*3 cases */, 116, MVT::i32,// ->19854
6764 : /*19738*/ OPC_Scope, 101, /*->19841*/ // 2 children in Scope
6765 : /*19740*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6766 : /*19742*/ OPC_EmitInteger, MVT::i32, 0,
6767 : /*19745*/ OPC_EmitInteger, MVT::i32, 0,
6768 : /*19748*/ OPC_EmitInteger, MVT::i32, 1,
6769 : /*19751*/ OPC_EmitInteger, MVT::i32, 0,
6770 : /*19754*/ OPC_EmitInteger, MVT::i32, 0,
6771 : /*19757*/ OPC_EmitInteger, MVT::i32, 0,
6772 : /*19760*/ OPC_EmitInteger, MVT::i32, 0,
6773 : /*19763*/ OPC_EmitInteger, MVT::i32, 0,
6774 : /*19766*/ OPC_EmitInteger, MVT::i32, 0,
6775 : /*19769*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6776 : /*19781*/ OPC_EmitInteger, MVT::i32, 0,
6777 : /*19784*/ OPC_EmitInteger, MVT::i32, 0,
6778 : /*19787*/ OPC_EmitInteger, MVT::i32, 0,
6779 : /*19790*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
6780 : /*19802*/ OPC_EmitInteger, MVT::i32, 1,
6781 : /*19805*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
6782 : /*19808*/ OPC_EmitInteger, MVT::i32, 0,
6783 : /*19811*/ OPC_EmitInteger, MVT::i32, 0,
6784 : /*19814*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::XOR_INT), 0,
6785 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
6786 : // Src: (xor:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
6787 : // Dst: (XOR_INT:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
6788 : /*19841*/ /*Scope*/ 11, /*->19853*/
6789 : /*19842*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
6790 : /*19844*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_XOR_B32), 0,
6791 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6792 : // Src: (xor:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
6793 : // Dst: (S_XOR_B32:i32 i32:i32:$src0, i32:i32:$src1)
6794 : /*19853*/ 0, /*End of Scope*/
6795 : /*19854*/ /*SwitchType*/ 11, MVT::i64,// ->19867
6796 : /*19856*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
6797 : /*19858*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_XOR_B64), 0,
6798 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 0, 1,
6799 : // Src: (xor:i64 i64:i64:$src0, i64:i64:$src1) - Complexity = 3
6800 : // Dst: (S_XOR_B64:i64 i64:i64:$src0, i64:i64:$src1)
6801 : /*19867*/ /*SwitchType*/ 11, MVT::i1,// ->19880
6802 : /*19869*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6803 : /*19871*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_XOR_B64), 0,
6804 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
6805 : // Src: (xor:i1 i1:i1:$src0, i1:i1:$src1) - Complexity = 3
6806 : // Dst: (S_XOR_B64:i1 ?:i1:$src0, ?:i1:$src1)
6807 : /*19880*/ 0, // EndSwitchType
6808 : /*19881*/ 0, /*End of Scope*/
6809 : /*19882*/ 0, /*End of Scope*/
6810 : /*19883*/ /*SwitchOpcode*/ 33|128,15/*1953*/, TARGET_VAL(ISD::EXTRACT_VECTOR_ELT),// ->21840
6811 : /*19887*/ OPC_RecordChild0, // #0 = $vec
6812 : /*19888*/ OPC_Scope, 40|128,1/*168*/, /*->20059*/ // 8 children in Scope
6813 : /*19891*/ OPC_CheckChild0Type, MVT::v2i32,
6814 : /*19893*/ OPC_Scope, 33, /*->19928*/ // 5 children in Scope
6815 : /*19895*/ OPC_MoveChild, 1,
6816 : /*19897*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
6817 : /*19900*/ OPC_RecordChild0, // #1 = $idx
6818 : /*19901*/ OPC_RecordChild1, // #2 = $off
6819 : /*19902*/ OPC_MoveChild, 1,
6820 : /*19904*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
6821 : /*19907*/ OPC_MoveParent,
6822 : /*19908*/ OPC_CheckType, MVT::i32,
6823 : /*19910*/ OPC_MoveParent,
6824 : /*19911*/ OPC_CheckType, MVT::i32,
6825 : /*19913*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6826 : /*19915*/ OPC_EmitConvertToTarget, 2,
6827 : /*19917*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
6828 : 2/*#VTs*/, MVT::i32, MVT::i1, 3/*#Ops*/, 0, 1, 3,
6829 : // Src: (vector_extract:i32 v2i32:v2i32:$vec, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
6830 : // Dst: (SI_INDIRECT_SRC:i32:i1 ?:v2i32:$vec, ?:i32:$idx, (imm:i32):$off)
6831 : /*19928*/ /*Scope*/ 36, /*->19965*/
6832 : /*19929*/ OPC_CheckChild1Integer, 0,
6833 : /*19931*/ OPC_CheckType, MVT::i32,
6834 : /*19933*/ OPC_Scope, 14, /*->19949*/ // 2 children in Scope
6835 : /*19935*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6836 : /*19937*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
6837 : /*19940*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6838 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6839 : // Src: (vector_extract:i32 v2i32:v2i32:$src, 0:iPTR) - Complexity = 8
6840 : // Dst: (EXTRACT_SUBREG:i32 ?:v2i32:$src, sub0:i32)
6841 : /*19949*/ /*Scope*/ 14, /*->19964*/
6842 : /*19950*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6843 : /*19952*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
6844 : /*19955*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6845 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6846 : // Src: (vector_extract:i32 v2i32:v2i32:$src, 0:iPTR) - Complexity = 8
6847 : // Dst: (EXTRACT_SUBREG:i32 ?:v2i32:$src, sub0:i32)
6848 : /*19964*/ 0, /*End of Scope*/
6849 : /*19965*/ /*Scope*/ 36, /*->20002*/
6850 : /*19966*/ OPC_CheckChild1Integer, 1,
6851 : /*19968*/ OPC_CheckType, MVT::i32,
6852 : /*19970*/ OPC_Scope, 14, /*->19986*/ // 2 children in Scope
6853 : /*19972*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6854 : /*19974*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
6855 : /*19977*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6856 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6857 : // Src: (vector_extract:i32 v2i32:v2i32:$src, 1:iPTR) - Complexity = 8
6858 : // Dst: (EXTRACT_SUBREG:i32 ?:v2i32:$src, sub1:i32)
6859 : /*19986*/ /*Scope*/ 14, /*->20001*/
6860 : /*19987*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6861 : /*19989*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
6862 : /*19992*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6863 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6864 : // Src: (vector_extract:i32 v2i32:v2i32:$src, 1:iPTR) - Complexity = 8
6865 : // Dst: (EXTRACT_SUBREG:i32 ?:v2i32:$src, sub1:i32)
6866 : /*20001*/ 0, /*End of Scope*/
6867 : /*20002*/ /*Scope*/ 18, /*->20021*/
6868 : /*20003*/ OPC_CheckChild1Integer, 2,
6869 : /*20005*/ OPC_CheckType, MVT::i32,
6870 : /*20007*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6871 : /*20009*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
6872 : /*20012*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6873 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6874 : // Src: (vector_extract:i32 v2i32:v2i32:$src, 2:iPTR) - Complexity = 8
6875 : // Dst: (EXTRACT_SUBREG:i32 ?:v2i32:$src, sub2:i32)
6876 : /*20021*/ /*Scope*/ 36, /*->20058*/
6877 : /*20022*/ OPC_RecordChild1, // #1 = $index
6878 : /*20023*/ OPC_CheckChild1Type, MVT::i32,
6879 : /*20025*/ OPC_CheckType, MVT::i32,
6880 : /*20027*/ OPC_Scope, 11, /*->20040*/ // 2 children in Scope
6881 : /*20029*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6882 : /*20031*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_EXTRACT_ELT_V2), 0,
6883 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6884 : // Src: (extractelt:i32 v2i32:v2i32:$vec, i32:i32:$index) - Complexity = 3
6885 : // Dst: (R600_EXTRACT_ELT_V2:i32 ?:v2i32:$vec, ?:i32:$index)
6886 : /*20040*/ /*Scope*/ 16, /*->20057*/
6887 : /*20041*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6888 : /*20043*/ OPC_EmitInteger, MVT::i32, 0,
6889 : /*20046*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
6890 : 2/*#VTs*/, MVT::i32, MVT::i1, 3/*#Ops*/, 0, 1, 2,
6891 : // Src: (vector_extract:i32 v2i32:v2i32:$vec, i32:i32:$idx) - Complexity = 3
6892 : // Dst: (SI_INDIRECT_SRC:i32:i1 ?:v2i32:$vec, ?:i32:$idx, 0:i32)
6893 : /*20057*/ 0, /*End of Scope*/
6894 : /*20058*/ 0, /*End of Scope*/
6895 : /*20059*/ /*Scope*/ 95|128,1/*223*/, /*->20284*/
6896 : /*20061*/ OPC_CheckChild0Type, MVT::v4i32,
6897 : /*20063*/ OPC_Scope, 33, /*->20098*/ // 6 children in Scope
6898 : /*20065*/ OPC_MoveChild, 1,
6899 : /*20067*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
6900 : /*20070*/ OPC_RecordChild0, // #1 = $idx
6901 : /*20071*/ OPC_RecordChild1, // #2 = $off
6902 : /*20072*/ OPC_MoveChild, 1,
6903 : /*20074*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
6904 : /*20077*/ OPC_MoveParent,
6905 : /*20078*/ OPC_CheckType, MVT::i32,
6906 : /*20080*/ OPC_MoveParent,
6907 : /*20081*/ OPC_CheckType, MVT::i32,
6908 : /*20083*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6909 : /*20085*/ OPC_EmitConvertToTarget, 2,
6910 : /*20087*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
6911 : 2/*#VTs*/, MVT::i32, MVT::i1, 3/*#Ops*/, 0, 1, 3,
6912 : // Src: (vector_extract:i32 v4i32:v4i32:$vec, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
6913 : // Dst: (SI_INDIRECT_SRC:i32:i1 ?:v4i32:$vec, ?:i32:$idx, (imm:i32):$off)
6914 : /*20098*/ /*Scope*/ 36, /*->20135*/
6915 : /*20099*/ OPC_CheckChild1Integer, 0,
6916 : /*20101*/ OPC_CheckType, MVT::i32,
6917 : /*20103*/ OPC_Scope, 14, /*->20119*/ // 2 children in Scope
6918 : /*20105*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6919 : /*20107*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
6920 : /*20110*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6921 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6922 : // Src: (vector_extract:i32 v4i32:v4i32:$src, 0:iPTR) - Complexity = 8
6923 : // Dst: (EXTRACT_SUBREG:i32 ?:v4i32:$src, sub0:i32)
6924 : /*20119*/ /*Scope*/ 14, /*->20134*/
6925 : /*20120*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6926 : /*20122*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
6927 : /*20125*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6928 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6929 : // Src: (vector_extract:i32 v4i32:v4i32:$src, 0:iPTR) - Complexity = 8
6930 : // Dst: (EXTRACT_SUBREG:i32 ?:v4i32:$src, sub0:i32)
6931 : /*20134*/ 0, /*End of Scope*/
6932 : /*20135*/ /*Scope*/ 36, /*->20172*/
6933 : /*20136*/ OPC_CheckChild1Integer, 1,
6934 : /*20138*/ OPC_CheckType, MVT::i32,
6935 : /*20140*/ OPC_Scope, 14, /*->20156*/ // 2 children in Scope
6936 : /*20142*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6937 : /*20144*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
6938 : /*20147*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6939 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6940 : // Src: (vector_extract:i32 v4i32:v4i32:$src, 1:iPTR) - Complexity = 8
6941 : // Dst: (EXTRACT_SUBREG:i32 ?:v4i32:$src, sub1:i32)
6942 : /*20156*/ /*Scope*/ 14, /*->20171*/
6943 : /*20157*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6944 : /*20159*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
6945 : /*20162*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6946 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6947 : // Src: (vector_extract:i32 v4i32:v4i32:$src, 1:iPTR) - Complexity = 8
6948 : // Dst: (EXTRACT_SUBREG:i32 ?:v4i32:$src, sub1:i32)
6949 : /*20171*/ 0, /*End of Scope*/
6950 : /*20172*/ /*Scope*/ 36, /*->20209*/
6951 : /*20173*/ OPC_CheckChild1Integer, 2,
6952 : /*20175*/ OPC_CheckType, MVT::i32,
6953 : /*20177*/ OPC_Scope, 14, /*->20193*/ // 2 children in Scope
6954 : /*20179*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6955 : /*20181*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
6956 : /*20184*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6957 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6958 : // Src: (vector_extract:i32 v4i32:v4i32:$src, 2:iPTR) - Complexity = 8
6959 : // Dst: (EXTRACT_SUBREG:i32 ?:v4i32:$src, sub2:i32)
6960 : /*20193*/ /*Scope*/ 14, /*->20208*/
6961 : /*20194*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6962 : /*20196*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
6963 : /*20199*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6964 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6965 : // Src: (vector_extract:i32 v4i32:v4i32:$src, 2:iPTR) - Complexity = 8
6966 : // Dst: (EXTRACT_SUBREG:i32 ?:v4i32:$src, sub2:i32)
6967 : /*20208*/ 0, /*End of Scope*/
6968 : /*20209*/ /*Scope*/ 36, /*->20246*/
6969 : /*20210*/ OPC_CheckChild1Integer, 3,
6970 : /*20212*/ OPC_CheckType, MVT::i32,
6971 : /*20214*/ OPC_Scope, 14, /*->20230*/ // 2 children in Scope
6972 : /*20216*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6973 : /*20218*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
6974 : /*20221*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6975 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6976 : // Src: (vector_extract:i32 v4i32:v4i32:$src, 3:iPTR) - Complexity = 8
6977 : // Dst: (EXTRACT_SUBREG:i32 ?:v4i32:$src, sub3:i32)
6978 : /*20230*/ /*Scope*/ 14, /*->20245*/
6979 : /*20231*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6980 : /*20233*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
6981 : /*20236*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
6982 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6983 : // Src: (vector_extract:i32 v4i32:v4i32:$src, 3:iPTR) - Complexity = 8
6984 : // Dst: (EXTRACT_SUBREG:i32 ?:v4i32:$src, sub3:i32)
6985 : /*20245*/ 0, /*End of Scope*/
6986 : /*20246*/ /*Scope*/ 36, /*->20283*/
6987 : /*20247*/ OPC_RecordChild1, // #1 = $index
6988 : /*20248*/ OPC_CheckChild1Type, MVT::i32,
6989 : /*20250*/ OPC_CheckType, MVT::i32,
6990 : /*20252*/ OPC_Scope, 11, /*->20265*/ // 2 children in Scope
6991 : /*20254*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
6992 : /*20256*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_EXTRACT_ELT_V4), 0,
6993 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
6994 : // Src: (extractelt:i32 v4i32:v4i32:$vec, i32:i32:$index) - Complexity = 3
6995 : // Dst: (R600_EXTRACT_ELT_V4:i32 ?:v4i32:$vec, ?:i32:$index)
6996 : /*20265*/ /*Scope*/ 16, /*->20282*/
6997 : /*20266*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
6998 : /*20268*/ OPC_EmitInteger, MVT::i32, 0,
6999 : /*20271*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7000 : 2/*#VTs*/, MVT::i32, MVT::i1, 3/*#Ops*/, 0, 1, 2,
7001 : // Src: (vector_extract:i32 v4i32:v4i32:$vec, i32:i32:$idx) - Complexity = 3
7002 : // Dst: (SI_INDIRECT_SRC:i32:i1 ?:v4i32:$vec, ?:i32:$idx, 0:i32)
7003 : /*20282*/ 0, /*End of Scope*/
7004 : /*20283*/ 0, /*End of Scope*/
7005 : /*20284*/ /*Scope*/ 84|128,1/*212*/, /*->20498*/
7006 : /*20286*/ OPC_CheckChild0Type, MVT::v8i32,
7007 : /*20288*/ OPC_Scope, 33, /*->20323*/ // 10 children in Scope
7008 : /*20290*/ OPC_MoveChild, 1,
7009 : /*20292*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
7010 : /*20295*/ OPC_RecordChild0, // #1 = $idx
7011 : /*20296*/ OPC_RecordChild1, // #2 = $off
7012 : /*20297*/ OPC_MoveChild, 1,
7013 : /*20299*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
7014 : /*20302*/ OPC_MoveParent,
7015 : /*20303*/ OPC_CheckType, MVT::i32,
7016 : /*20305*/ OPC_MoveParent,
7017 : /*20306*/ OPC_CheckType, MVT::i32,
7018 : /*20308*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7019 : /*20310*/ OPC_EmitConvertToTarget, 2,
7020 : /*20312*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7021 : 2/*#VTs*/, MVT::i32, MVT::i1, 3/*#Ops*/, 0, 1, 3,
7022 : // Src: (vector_extract:i32 v8i32:v8i32:$vec, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
7023 : // Dst: (SI_INDIRECT_SRC:i32:i1 ?:v8i32:$vec, ?:i32:$idx, (imm:i32):$off)
7024 : /*20323*/ /*Scope*/ 18, /*->20342*/
7025 : /*20324*/ OPC_CheckChild1Integer, 0,
7026 : /*20326*/ OPC_CheckType, MVT::i32,
7027 : /*20328*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7028 : /*20330*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
7029 : /*20333*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7030 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7031 : // Src: (vector_extract:i32 v8i32:v8i32:$src, 0:iPTR) - Complexity = 8
7032 : // Dst: (EXTRACT_SUBREG:i32 ?:v8i32:$src, sub0:i32)
7033 : /*20342*/ /*Scope*/ 18, /*->20361*/
7034 : /*20343*/ OPC_CheckChild1Integer, 1,
7035 : /*20345*/ OPC_CheckType, MVT::i32,
7036 : /*20347*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7037 : /*20349*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
7038 : /*20352*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7039 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7040 : // Src: (vector_extract:i32 v8i32:v8i32:$src, 1:iPTR) - Complexity = 8
7041 : // Dst: (EXTRACT_SUBREG:i32 ?:v8i32:$src, sub1:i32)
7042 : /*20361*/ /*Scope*/ 18, /*->20380*/
7043 : /*20362*/ OPC_CheckChild1Integer, 2,
7044 : /*20364*/ OPC_CheckType, MVT::i32,
7045 : /*20366*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7046 : /*20368*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
7047 : /*20371*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7048 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7049 : // Src: (vector_extract:i32 v8i32:v8i32:$src, 2:iPTR) - Complexity = 8
7050 : // Dst: (EXTRACT_SUBREG:i32 ?:v8i32:$src, sub2:i32)
7051 : /*20380*/ /*Scope*/ 18, /*->20399*/
7052 : /*20381*/ OPC_CheckChild1Integer, 3,
7053 : /*20383*/ OPC_CheckType, MVT::i32,
7054 : /*20385*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7055 : /*20387*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
7056 : /*20390*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7057 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7058 : // Src: (vector_extract:i32 v8i32:v8i32:$src, 3:iPTR) - Complexity = 8
7059 : // Dst: (EXTRACT_SUBREG:i32 ?:v8i32:$src, sub3:i32)
7060 : /*20399*/ /*Scope*/ 18, /*->20418*/
7061 : /*20400*/ OPC_CheckChild1Integer, 4,
7062 : /*20402*/ OPC_CheckType, MVT::i32,
7063 : /*20404*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7064 : /*20406*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub4,
7065 : /*20409*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7066 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7067 : // Src: (vector_extract:i32 v8i32:v8i32:$src, 4:iPTR) - Complexity = 8
7068 : // Dst: (EXTRACT_SUBREG:i32 ?:v8i32:$src, sub4:i32)
7069 : /*20418*/ /*Scope*/ 18, /*->20437*/
7070 : /*20419*/ OPC_CheckChild1Integer, 5,
7071 : /*20421*/ OPC_CheckType, MVT::i32,
7072 : /*20423*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7073 : /*20425*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub5,
7074 : /*20428*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7075 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7076 : // Src: (vector_extract:i32 v8i32:v8i32:$src, 5:iPTR) - Complexity = 8
7077 : // Dst: (EXTRACT_SUBREG:i32 ?:v8i32:$src, sub5:i32)
7078 : /*20437*/ /*Scope*/ 18, /*->20456*/
7079 : /*20438*/ OPC_CheckChild1Integer, 6,
7080 : /*20440*/ OPC_CheckType, MVT::i32,
7081 : /*20442*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7082 : /*20444*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub6,
7083 : /*20447*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7084 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7085 : // Src: (vector_extract:i32 v8i32:v8i32:$src, 6:iPTR) - Complexity = 8
7086 : // Dst: (EXTRACT_SUBREG:i32 ?:v8i32:$src, sub6:i32)
7087 : /*20456*/ /*Scope*/ 18, /*->20475*/
7088 : /*20457*/ OPC_CheckChild1Integer, 7,
7089 : /*20459*/ OPC_CheckType, MVT::i32,
7090 : /*20461*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7091 : /*20463*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub7,
7092 : /*20466*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7093 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7094 : // Src: (vector_extract:i32 v8i32:v8i32:$src, 7:iPTR) - Complexity = 8
7095 : // Dst: (EXTRACT_SUBREG:i32 ?:v8i32:$src, sub7:i32)
7096 : /*20475*/ /*Scope*/ 21, /*->20497*/
7097 : /*20476*/ OPC_RecordChild1, // #1 = $idx
7098 : /*20477*/ OPC_CheckChild1Type, MVT::i32,
7099 : /*20479*/ OPC_CheckType, MVT::i32,
7100 : /*20481*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7101 : /*20483*/ OPC_EmitInteger, MVT::i32, 0,
7102 : /*20486*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7103 : 2/*#VTs*/, MVT::i32, MVT::i1, 3/*#Ops*/, 0, 1, 2,
7104 : // Src: (vector_extract:i32 v8i32:v8i32:$vec, i32:i32:$idx) - Complexity = 3
7105 : // Dst: (SI_INDIRECT_SRC:i32:i1 ?:v8i32:$vec, ?:i32:$idx, 0:i32)
7106 : /*20497*/ 0, /*End of Scope*/
7107 : /*20498*/ /*Scope*/ 108|128,2/*364*/, /*->20864*/
7108 : /*20500*/ OPC_CheckChild0Type, MVT::v16i32,
7109 : /*20502*/ OPC_Scope, 33, /*->20537*/ // 18 children in Scope
7110 : /*20504*/ OPC_MoveChild, 1,
7111 : /*20506*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
7112 : /*20509*/ OPC_RecordChild0, // #1 = $idx
7113 : /*20510*/ OPC_RecordChild1, // #2 = $off
7114 : /*20511*/ OPC_MoveChild, 1,
7115 : /*20513*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
7116 : /*20516*/ OPC_MoveParent,
7117 : /*20517*/ OPC_CheckType, MVT::i32,
7118 : /*20519*/ OPC_MoveParent,
7119 : /*20520*/ OPC_CheckType, MVT::i32,
7120 : /*20522*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7121 : /*20524*/ OPC_EmitConvertToTarget, 2,
7122 : /*20526*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7123 : 2/*#VTs*/, MVT::i32, MVT::i1, 3/*#Ops*/, 0, 1, 3,
7124 : // Src: (vector_extract:i32 v16i32:v16i32:$vec, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
7125 : // Dst: (SI_INDIRECT_SRC:i32:i1 ?:v16i32:$vec, ?:i32:$idx, (imm:i32):$off)
7126 : /*20537*/ /*Scope*/ 18, /*->20556*/
7127 : /*20538*/ OPC_CheckChild1Integer, 0,
7128 : /*20540*/ OPC_CheckType, MVT::i32,
7129 : /*20542*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7130 : /*20544*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
7131 : /*20547*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7132 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7133 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 0:iPTR) - Complexity = 8
7134 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub0:i32)
7135 : /*20556*/ /*Scope*/ 18, /*->20575*/
7136 : /*20557*/ OPC_CheckChild1Integer, 1,
7137 : /*20559*/ OPC_CheckType, MVT::i32,
7138 : /*20561*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7139 : /*20563*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
7140 : /*20566*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7141 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7142 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 1:iPTR) - Complexity = 8
7143 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub1:i32)
7144 : /*20575*/ /*Scope*/ 18, /*->20594*/
7145 : /*20576*/ OPC_CheckChild1Integer, 2,
7146 : /*20578*/ OPC_CheckType, MVT::i32,
7147 : /*20580*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7148 : /*20582*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
7149 : /*20585*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7150 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7151 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 2:iPTR) - Complexity = 8
7152 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub2:i32)
7153 : /*20594*/ /*Scope*/ 18, /*->20613*/
7154 : /*20595*/ OPC_CheckChild1Integer, 3,
7155 : /*20597*/ OPC_CheckType, MVT::i32,
7156 : /*20599*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7157 : /*20601*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
7158 : /*20604*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7159 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7160 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 3:iPTR) - Complexity = 8
7161 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub3:i32)
7162 : /*20613*/ /*Scope*/ 18, /*->20632*/
7163 : /*20614*/ OPC_CheckChild1Integer, 4,
7164 : /*20616*/ OPC_CheckType, MVT::i32,
7165 : /*20618*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7166 : /*20620*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub4,
7167 : /*20623*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7168 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7169 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 4:iPTR) - Complexity = 8
7170 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub4:i32)
7171 : /*20632*/ /*Scope*/ 18, /*->20651*/
7172 : /*20633*/ OPC_CheckChild1Integer, 5,
7173 : /*20635*/ OPC_CheckType, MVT::i32,
7174 : /*20637*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7175 : /*20639*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub5,
7176 : /*20642*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7177 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7178 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 5:iPTR) - Complexity = 8
7179 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub5:i32)
7180 : /*20651*/ /*Scope*/ 18, /*->20670*/
7181 : /*20652*/ OPC_CheckChild1Integer, 6,
7182 : /*20654*/ OPC_CheckType, MVT::i32,
7183 : /*20656*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7184 : /*20658*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub6,
7185 : /*20661*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7186 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7187 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 6:iPTR) - Complexity = 8
7188 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub6:i32)
7189 : /*20670*/ /*Scope*/ 18, /*->20689*/
7190 : /*20671*/ OPC_CheckChild1Integer, 7,
7191 : /*20673*/ OPC_CheckType, MVT::i32,
7192 : /*20675*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7193 : /*20677*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub7,
7194 : /*20680*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7195 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7196 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 7:iPTR) - Complexity = 8
7197 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub7:i32)
7198 : /*20689*/ /*Scope*/ 18, /*->20708*/
7199 : /*20690*/ OPC_CheckChild1Integer, 8,
7200 : /*20692*/ OPC_CheckType, MVT::i32,
7201 : /*20694*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7202 : /*20696*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub8,
7203 : /*20699*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7204 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7205 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 8:iPTR) - Complexity = 8
7206 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub8:i32)
7207 : /*20708*/ /*Scope*/ 18, /*->20727*/
7208 : /*20709*/ OPC_CheckChild1Integer, 9,
7209 : /*20711*/ OPC_CheckType, MVT::i32,
7210 : /*20713*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7211 : /*20715*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub9,
7212 : /*20718*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7213 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7214 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 9:iPTR) - Complexity = 8
7215 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub9:i32)
7216 : /*20727*/ /*Scope*/ 18, /*->20746*/
7217 : /*20728*/ OPC_CheckChild1Integer, 10,
7218 : /*20730*/ OPC_CheckType, MVT::i32,
7219 : /*20732*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7220 : /*20734*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub10,
7221 : /*20737*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7222 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7223 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 10:iPTR) - Complexity = 8
7224 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub10:i32)
7225 : /*20746*/ /*Scope*/ 18, /*->20765*/
7226 : /*20747*/ OPC_CheckChild1Integer, 11,
7227 : /*20749*/ OPC_CheckType, MVT::i32,
7228 : /*20751*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7229 : /*20753*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub11,
7230 : /*20756*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7231 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7232 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 11:iPTR) - Complexity = 8
7233 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub11:i32)
7234 : /*20765*/ /*Scope*/ 18, /*->20784*/
7235 : /*20766*/ OPC_CheckChild1Integer, 12,
7236 : /*20768*/ OPC_CheckType, MVT::i32,
7237 : /*20770*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7238 : /*20772*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub12,
7239 : /*20775*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7240 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7241 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 12:iPTR) - Complexity = 8
7242 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub12:i32)
7243 : /*20784*/ /*Scope*/ 18, /*->20803*/
7244 : /*20785*/ OPC_CheckChild1Integer, 13,
7245 : /*20787*/ OPC_CheckType, MVT::i32,
7246 : /*20789*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7247 : /*20791*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub13,
7248 : /*20794*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7249 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7250 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 13:iPTR) - Complexity = 8
7251 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub13:i32)
7252 : /*20803*/ /*Scope*/ 18, /*->20822*/
7253 : /*20804*/ OPC_CheckChild1Integer, 14,
7254 : /*20806*/ OPC_CheckType, MVT::i32,
7255 : /*20808*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7256 : /*20810*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub14,
7257 : /*20813*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7258 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7259 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 14:iPTR) - Complexity = 8
7260 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub14:i32)
7261 : /*20822*/ /*Scope*/ 18, /*->20841*/
7262 : /*20823*/ OPC_CheckChild1Integer, 15,
7263 : /*20825*/ OPC_CheckType, MVT::i32,
7264 : /*20827*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7265 : /*20829*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub15,
7266 : /*20832*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7267 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
7268 : // Src: (vector_extract:i32 v16i32:v16i32:$src, 15:iPTR) - Complexity = 8
7269 : // Dst: (EXTRACT_SUBREG:i32 ?:v16i32:$src, sub15:i32)
7270 : /*20841*/ /*Scope*/ 21, /*->20863*/
7271 : /*20842*/ OPC_RecordChild1, // #1 = $idx
7272 : /*20843*/ OPC_CheckChild1Type, MVT::i32,
7273 : /*20845*/ OPC_CheckType, MVT::i32,
7274 : /*20847*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7275 : /*20849*/ OPC_EmitInteger, MVT::i32, 0,
7276 : /*20852*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7277 : 2/*#VTs*/, MVT::i32, MVT::i1, 3/*#Ops*/, 0, 1, 2,
7278 : // Src: (vector_extract:i32 v16i32:v16i32:$vec, i32:i32:$idx) - Complexity = 3
7279 : // Dst: (SI_INDIRECT_SRC:i32:i1 ?:v16i32:$vec, ?:i32:$idx, 0:i32)
7280 : /*20863*/ 0, /*End of Scope*/
7281 : /*20864*/ /*Scope*/ 40|128,1/*168*/, /*->21034*/
7282 : /*20866*/ OPC_CheckChild0Type, MVT::v2f32,
7283 : /*20868*/ OPC_Scope, 33, /*->20903*/ // 5 children in Scope
7284 : /*20870*/ OPC_MoveChild, 1,
7285 : /*20872*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
7286 : /*20875*/ OPC_RecordChild0, // #1 = $idx
7287 : /*20876*/ OPC_RecordChild1, // #2 = $off
7288 : /*20877*/ OPC_MoveChild, 1,
7289 : /*20879*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
7290 : /*20882*/ OPC_MoveParent,
7291 : /*20883*/ OPC_CheckType, MVT::i32,
7292 : /*20885*/ OPC_MoveParent,
7293 : /*20886*/ OPC_CheckType, MVT::f32,
7294 : /*20888*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7295 : /*20890*/ OPC_EmitConvertToTarget, 2,
7296 : /*20892*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7297 : 2/*#VTs*/, MVT::f32, MVT::i1, 3/*#Ops*/, 0, 1, 3,
7298 : // Src: (vector_extract:f32 v2f32:v2f32:$vec, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
7299 : // Dst: (SI_INDIRECT_SRC:f32:i1 ?:v2f32:$vec, ?:i32:$idx, (imm:i32):$off)
7300 : /*20903*/ /*Scope*/ 36, /*->20940*/
7301 : /*20904*/ OPC_CheckChild1Integer, 0,
7302 : /*20906*/ OPC_CheckType, MVT::f32,
7303 : /*20908*/ OPC_Scope, 14, /*->20924*/ // 2 children in Scope
7304 : /*20910*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
7305 : /*20912*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
7306 : /*20915*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7307 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7308 : // Src: (vector_extract:f32 v2f32:v2f32:$src, 0:iPTR) - Complexity = 8
7309 : // Dst: (EXTRACT_SUBREG:f32 ?:v2f32:$src, sub0:i32)
7310 : /*20924*/ /*Scope*/ 14, /*->20939*/
7311 : /*20925*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7312 : /*20927*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
7313 : /*20930*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7314 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7315 : // Src: (vector_extract:f32 v2f32:v2f32:$src, 0:iPTR) - Complexity = 8
7316 : // Dst: (EXTRACT_SUBREG:f32 ?:v2f32:$src, sub0:i32)
7317 : /*20939*/ 0, /*End of Scope*/
7318 : /*20940*/ /*Scope*/ 36, /*->20977*/
7319 : /*20941*/ OPC_CheckChild1Integer, 1,
7320 : /*20943*/ OPC_CheckType, MVT::f32,
7321 : /*20945*/ OPC_Scope, 14, /*->20961*/ // 2 children in Scope
7322 : /*20947*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
7323 : /*20949*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
7324 : /*20952*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7325 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7326 : // Src: (vector_extract:f32 v2f32:v2f32:$src, 1:iPTR) - Complexity = 8
7327 : // Dst: (EXTRACT_SUBREG:f32 ?:v2f32:$src, sub1:i32)
7328 : /*20961*/ /*Scope*/ 14, /*->20976*/
7329 : /*20962*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7330 : /*20964*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
7331 : /*20967*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7332 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7333 : // Src: (vector_extract:f32 v2f32:v2f32:$src, 1:iPTR) - Complexity = 8
7334 : // Dst: (EXTRACT_SUBREG:f32 ?:v2f32:$src, sub1:i32)
7335 : /*20976*/ 0, /*End of Scope*/
7336 : /*20977*/ /*Scope*/ 18, /*->20996*/
7337 : /*20978*/ OPC_CheckChild1Integer, 2,
7338 : /*20980*/ OPC_CheckType, MVT::f32,
7339 : /*20982*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7340 : /*20984*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
7341 : /*20987*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7342 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7343 : // Src: (vector_extract:f32 v2f32:v2f32:$src, 2:iPTR) - Complexity = 8
7344 : // Dst: (EXTRACT_SUBREG:f32 ?:v2f32:$src, sub2:i32)
7345 : /*20996*/ /*Scope*/ 36, /*->21033*/
7346 : /*20997*/ OPC_RecordChild1, // #1 = $index
7347 : /*20998*/ OPC_CheckChild1Type, MVT::i32,
7348 : /*21000*/ OPC_CheckType, MVT::f32,
7349 : /*21002*/ OPC_Scope, 11, /*->21015*/ // 2 children in Scope
7350 : /*21004*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
7351 : /*21006*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_EXTRACT_ELT_V2), 0,
7352 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7353 : // Src: (extractelt:f32 v2f32:v2f32:$vec, i32:i32:$index) - Complexity = 3
7354 : // Dst: (R600_EXTRACT_ELT_V2:f32 ?:v2f32:$vec, ?:i32:$index)
7355 : /*21015*/ /*Scope*/ 16, /*->21032*/
7356 : /*21016*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7357 : /*21018*/ OPC_EmitInteger, MVT::i32, 0,
7358 : /*21021*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7359 : 2/*#VTs*/, MVT::f32, MVT::i1, 3/*#Ops*/, 0, 1, 2,
7360 : // Src: (vector_extract:f32 v2f32:v2f32:$vec, i32:i32:$idx) - Complexity = 3
7361 : // Dst: (SI_INDIRECT_SRC:f32:i1 ?:v2f32:$vec, ?:i32:$idx, 0:i32)
7362 : /*21032*/ 0, /*End of Scope*/
7363 : /*21033*/ 0, /*End of Scope*/
7364 : /*21034*/ /*Scope*/ 95|128,1/*223*/, /*->21259*/
7365 : /*21036*/ OPC_CheckChild0Type, MVT::v4f32,
7366 : /*21038*/ OPC_Scope, 33, /*->21073*/ // 6 children in Scope
7367 : /*21040*/ OPC_MoveChild, 1,
7368 : /*21042*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
7369 : /*21045*/ OPC_RecordChild0, // #1 = $idx
7370 : /*21046*/ OPC_RecordChild1, // #2 = $off
7371 : /*21047*/ OPC_MoveChild, 1,
7372 : /*21049*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
7373 : /*21052*/ OPC_MoveParent,
7374 : /*21053*/ OPC_CheckType, MVT::i32,
7375 : /*21055*/ OPC_MoveParent,
7376 : /*21056*/ OPC_CheckType, MVT::f32,
7377 : /*21058*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7378 : /*21060*/ OPC_EmitConvertToTarget, 2,
7379 : /*21062*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7380 : 2/*#VTs*/, MVT::f32, MVT::i1, 3/*#Ops*/, 0, 1, 3,
7381 : // Src: (vector_extract:f32 v4f32:v4f32:$vec, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
7382 : // Dst: (SI_INDIRECT_SRC:f32:i1 ?:v4f32:$vec, ?:i32:$idx, (imm:i32):$off)
7383 : /*21073*/ /*Scope*/ 36, /*->21110*/
7384 : /*21074*/ OPC_CheckChild1Integer, 0,
7385 : /*21076*/ OPC_CheckType, MVT::f32,
7386 : /*21078*/ OPC_Scope, 14, /*->21094*/ // 2 children in Scope
7387 : /*21080*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
7388 : /*21082*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
7389 : /*21085*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7390 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7391 : // Src: (vector_extract:f32 v4f32:v4f32:$src, 0:iPTR) - Complexity = 8
7392 : // Dst: (EXTRACT_SUBREG:f32 ?:v4f32:$src, sub0:i32)
7393 : /*21094*/ /*Scope*/ 14, /*->21109*/
7394 : /*21095*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7395 : /*21097*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
7396 : /*21100*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7397 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7398 : // Src: (vector_extract:f32 v4f32:v4f32:$src, 0:iPTR) - Complexity = 8
7399 : // Dst: (EXTRACT_SUBREG:f32 ?:v4f32:$src, sub0:i32)
7400 : /*21109*/ 0, /*End of Scope*/
7401 : /*21110*/ /*Scope*/ 36, /*->21147*/
7402 : /*21111*/ OPC_CheckChild1Integer, 1,
7403 : /*21113*/ OPC_CheckType, MVT::f32,
7404 : /*21115*/ OPC_Scope, 14, /*->21131*/ // 2 children in Scope
7405 : /*21117*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
7406 : /*21119*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
7407 : /*21122*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7408 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7409 : // Src: (vector_extract:f32 v4f32:v4f32:$src, 1:iPTR) - Complexity = 8
7410 : // Dst: (EXTRACT_SUBREG:f32 ?:v4f32:$src, sub1:i32)
7411 : /*21131*/ /*Scope*/ 14, /*->21146*/
7412 : /*21132*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7413 : /*21134*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
7414 : /*21137*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7415 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7416 : // Src: (vector_extract:f32 v4f32:v4f32:$src, 1:iPTR) - Complexity = 8
7417 : // Dst: (EXTRACT_SUBREG:f32 ?:v4f32:$src, sub1:i32)
7418 : /*21146*/ 0, /*End of Scope*/
7419 : /*21147*/ /*Scope*/ 36, /*->21184*/
7420 : /*21148*/ OPC_CheckChild1Integer, 2,
7421 : /*21150*/ OPC_CheckType, MVT::f32,
7422 : /*21152*/ OPC_Scope, 14, /*->21168*/ // 2 children in Scope
7423 : /*21154*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
7424 : /*21156*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
7425 : /*21159*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7426 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7427 : // Src: (vector_extract:f32 v4f32:v4f32:$src, 2:iPTR) - Complexity = 8
7428 : // Dst: (EXTRACT_SUBREG:f32 ?:v4f32:$src, sub2:i32)
7429 : /*21168*/ /*Scope*/ 14, /*->21183*/
7430 : /*21169*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7431 : /*21171*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
7432 : /*21174*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7433 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7434 : // Src: (vector_extract:f32 v4f32:v4f32:$src, 2:iPTR) - Complexity = 8
7435 : // Dst: (EXTRACT_SUBREG:f32 ?:v4f32:$src, sub2:i32)
7436 : /*21183*/ 0, /*End of Scope*/
7437 : /*21184*/ /*Scope*/ 36, /*->21221*/
7438 : /*21185*/ OPC_CheckChild1Integer, 3,
7439 : /*21187*/ OPC_CheckType, MVT::f32,
7440 : /*21189*/ OPC_Scope, 14, /*->21205*/ // 2 children in Scope
7441 : /*21191*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
7442 : /*21193*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
7443 : /*21196*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7444 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7445 : // Src: (vector_extract:f32 v4f32:v4f32:$src, 3:iPTR) - Complexity = 8
7446 : // Dst: (EXTRACT_SUBREG:f32 ?:v4f32:$src, sub3:i32)
7447 : /*21205*/ /*Scope*/ 14, /*->21220*/
7448 : /*21206*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7449 : /*21208*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
7450 : /*21211*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7451 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7452 : // Src: (vector_extract:f32 v4f32:v4f32:$src, 3:iPTR) - Complexity = 8
7453 : // Dst: (EXTRACT_SUBREG:f32 ?:v4f32:$src, sub3:i32)
7454 : /*21220*/ 0, /*End of Scope*/
7455 : /*21221*/ /*Scope*/ 36, /*->21258*/
7456 : /*21222*/ OPC_RecordChild1, // #1 = $index
7457 : /*21223*/ OPC_CheckChild1Type, MVT::i32,
7458 : /*21225*/ OPC_CheckType, MVT::f32,
7459 : /*21227*/ OPC_Scope, 11, /*->21240*/ // 2 children in Scope
7460 : /*21229*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
7461 : /*21231*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_EXTRACT_ELT_V4), 0,
7462 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7463 : // Src: (extractelt:f32 v4f32:v4f32:$vec, i32:i32:$index) - Complexity = 3
7464 : // Dst: (R600_EXTRACT_ELT_V4:f32 ?:v4f32:$vec, ?:i32:$index)
7465 : /*21240*/ /*Scope*/ 16, /*->21257*/
7466 : /*21241*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7467 : /*21243*/ OPC_EmitInteger, MVT::i32, 0,
7468 : /*21246*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7469 : 2/*#VTs*/, MVT::f32, MVT::i1, 3/*#Ops*/, 0, 1, 2,
7470 : // Src: (vector_extract:f32 v4f32:v4f32:$vec, i32:i32:$idx) - Complexity = 3
7471 : // Dst: (SI_INDIRECT_SRC:f32:i1 ?:v4f32:$vec, ?:i32:$idx, 0:i32)
7472 : /*21257*/ 0, /*End of Scope*/
7473 : /*21258*/ 0, /*End of Scope*/
7474 : /*21259*/ /*Scope*/ 84|128,1/*212*/, /*->21473*/
7475 : /*21261*/ OPC_CheckChild0Type, MVT::v8f32,
7476 : /*21263*/ OPC_Scope, 33, /*->21298*/ // 10 children in Scope
7477 : /*21265*/ OPC_MoveChild, 1,
7478 : /*21267*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
7479 : /*21270*/ OPC_RecordChild0, // #1 = $idx
7480 : /*21271*/ OPC_RecordChild1, // #2 = $off
7481 : /*21272*/ OPC_MoveChild, 1,
7482 : /*21274*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
7483 : /*21277*/ OPC_MoveParent,
7484 : /*21278*/ OPC_CheckType, MVT::i32,
7485 : /*21280*/ OPC_MoveParent,
7486 : /*21281*/ OPC_CheckType, MVT::f32,
7487 : /*21283*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7488 : /*21285*/ OPC_EmitConvertToTarget, 2,
7489 : /*21287*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7490 : 2/*#VTs*/, MVT::f32, MVT::i1, 3/*#Ops*/, 0, 1, 3,
7491 : // Src: (vector_extract:f32 v8f32:v8f32:$vec, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
7492 : // Dst: (SI_INDIRECT_SRC:f32:i1 ?:v8f32:$vec, ?:i32:$idx, (imm:i32):$off)
7493 : /*21298*/ /*Scope*/ 18, /*->21317*/
7494 : /*21299*/ OPC_CheckChild1Integer, 0,
7495 : /*21301*/ OPC_CheckType, MVT::f32,
7496 : /*21303*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7497 : /*21305*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
7498 : /*21308*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7499 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7500 : // Src: (vector_extract:f32 v8f32:v8f32:$src, 0:iPTR) - Complexity = 8
7501 : // Dst: (EXTRACT_SUBREG:f32 ?:v8f32:$src, sub0:i32)
7502 : /*21317*/ /*Scope*/ 18, /*->21336*/
7503 : /*21318*/ OPC_CheckChild1Integer, 1,
7504 : /*21320*/ OPC_CheckType, MVT::f32,
7505 : /*21322*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7506 : /*21324*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
7507 : /*21327*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7508 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7509 : // Src: (vector_extract:f32 v8f32:v8f32:$src, 1:iPTR) - Complexity = 8
7510 : // Dst: (EXTRACT_SUBREG:f32 ?:v8f32:$src, sub1:i32)
7511 : /*21336*/ /*Scope*/ 18, /*->21355*/
7512 : /*21337*/ OPC_CheckChild1Integer, 2,
7513 : /*21339*/ OPC_CheckType, MVT::f32,
7514 : /*21341*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7515 : /*21343*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
7516 : /*21346*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7517 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7518 : // Src: (vector_extract:f32 v8f32:v8f32:$src, 2:iPTR) - Complexity = 8
7519 : // Dst: (EXTRACT_SUBREG:f32 ?:v8f32:$src, sub2:i32)
7520 : /*21355*/ /*Scope*/ 18, /*->21374*/
7521 : /*21356*/ OPC_CheckChild1Integer, 3,
7522 : /*21358*/ OPC_CheckType, MVT::f32,
7523 : /*21360*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7524 : /*21362*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
7525 : /*21365*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7526 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7527 : // Src: (vector_extract:f32 v8f32:v8f32:$src, 3:iPTR) - Complexity = 8
7528 : // Dst: (EXTRACT_SUBREG:f32 ?:v8f32:$src, sub3:i32)
7529 : /*21374*/ /*Scope*/ 18, /*->21393*/
7530 : /*21375*/ OPC_CheckChild1Integer, 4,
7531 : /*21377*/ OPC_CheckType, MVT::f32,
7532 : /*21379*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7533 : /*21381*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub4,
7534 : /*21384*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7535 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7536 : // Src: (vector_extract:f32 v8f32:v8f32:$src, 4:iPTR) - Complexity = 8
7537 : // Dst: (EXTRACT_SUBREG:f32 ?:v8f32:$src, sub4:i32)
7538 : /*21393*/ /*Scope*/ 18, /*->21412*/
7539 : /*21394*/ OPC_CheckChild1Integer, 5,
7540 : /*21396*/ OPC_CheckType, MVT::f32,
7541 : /*21398*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7542 : /*21400*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub5,
7543 : /*21403*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7544 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7545 : // Src: (vector_extract:f32 v8f32:v8f32:$src, 5:iPTR) - Complexity = 8
7546 : // Dst: (EXTRACT_SUBREG:f32 ?:v8f32:$src, sub5:i32)
7547 : /*21412*/ /*Scope*/ 18, /*->21431*/
7548 : /*21413*/ OPC_CheckChild1Integer, 6,
7549 : /*21415*/ OPC_CheckType, MVT::f32,
7550 : /*21417*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7551 : /*21419*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub6,
7552 : /*21422*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7553 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7554 : // Src: (vector_extract:f32 v8f32:v8f32:$src, 6:iPTR) - Complexity = 8
7555 : // Dst: (EXTRACT_SUBREG:f32 ?:v8f32:$src, sub6:i32)
7556 : /*21431*/ /*Scope*/ 18, /*->21450*/
7557 : /*21432*/ OPC_CheckChild1Integer, 7,
7558 : /*21434*/ OPC_CheckType, MVT::f32,
7559 : /*21436*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7560 : /*21438*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub7,
7561 : /*21441*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7562 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7563 : // Src: (vector_extract:f32 v8f32:v8f32:$src, 7:iPTR) - Complexity = 8
7564 : // Dst: (EXTRACT_SUBREG:f32 ?:v8f32:$src, sub7:i32)
7565 : /*21450*/ /*Scope*/ 21, /*->21472*/
7566 : /*21451*/ OPC_RecordChild1, // #1 = $idx
7567 : /*21452*/ OPC_CheckChild1Type, MVT::i32,
7568 : /*21454*/ OPC_CheckType, MVT::f32,
7569 : /*21456*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7570 : /*21458*/ OPC_EmitInteger, MVT::i32, 0,
7571 : /*21461*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7572 : 2/*#VTs*/, MVT::f32, MVT::i1, 3/*#Ops*/, 0, 1, 2,
7573 : // Src: (vector_extract:f32 v8f32:v8f32:$vec, i32:i32:$idx) - Complexity = 3
7574 : // Dst: (SI_INDIRECT_SRC:f32:i1 ?:v8f32:$vec, ?:i32:$idx, 0:i32)
7575 : /*21472*/ 0, /*End of Scope*/
7576 : /*21473*/ /*Scope*/ 108|128,2/*364*/, /*->21839*/
7577 : /*21475*/ OPC_CheckChild0Type, MVT::v16f32,
7578 : /*21477*/ OPC_Scope, 33, /*->21512*/ // 18 children in Scope
7579 : /*21479*/ OPC_MoveChild, 1,
7580 : /*21481*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
7581 : /*21484*/ OPC_RecordChild0, // #1 = $idx
7582 : /*21485*/ OPC_RecordChild1, // #2 = $off
7583 : /*21486*/ OPC_MoveChild, 1,
7584 : /*21488*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
7585 : /*21491*/ OPC_MoveParent,
7586 : /*21492*/ OPC_CheckType, MVT::i32,
7587 : /*21494*/ OPC_MoveParent,
7588 : /*21495*/ OPC_CheckType, MVT::f32,
7589 : /*21497*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7590 : /*21499*/ OPC_EmitConvertToTarget, 2,
7591 : /*21501*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7592 : 2/*#VTs*/, MVT::f32, MVT::i1, 3/*#Ops*/, 0, 1, 3,
7593 : // Src: (vector_extract:f32 v16f32:v16f32:$vec, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
7594 : // Dst: (SI_INDIRECT_SRC:f32:i1 ?:v16f32:$vec, ?:i32:$idx, (imm:i32):$off)
7595 : /*21512*/ /*Scope*/ 18, /*->21531*/
7596 : /*21513*/ OPC_CheckChild1Integer, 0,
7597 : /*21515*/ OPC_CheckType, MVT::f32,
7598 : /*21517*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7599 : /*21519*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
7600 : /*21522*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7601 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7602 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 0:iPTR) - Complexity = 8
7603 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub0:i32)
7604 : /*21531*/ /*Scope*/ 18, /*->21550*/
7605 : /*21532*/ OPC_CheckChild1Integer, 1,
7606 : /*21534*/ OPC_CheckType, MVT::f32,
7607 : /*21536*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7608 : /*21538*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
7609 : /*21541*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7610 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7611 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 1:iPTR) - Complexity = 8
7612 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub1:i32)
7613 : /*21550*/ /*Scope*/ 18, /*->21569*/
7614 : /*21551*/ OPC_CheckChild1Integer, 2,
7615 : /*21553*/ OPC_CheckType, MVT::f32,
7616 : /*21555*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7617 : /*21557*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
7618 : /*21560*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7619 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7620 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 2:iPTR) - Complexity = 8
7621 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub2:i32)
7622 : /*21569*/ /*Scope*/ 18, /*->21588*/
7623 : /*21570*/ OPC_CheckChild1Integer, 3,
7624 : /*21572*/ OPC_CheckType, MVT::f32,
7625 : /*21574*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7626 : /*21576*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
7627 : /*21579*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7628 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7629 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 3:iPTR) - Complexity = 8
7630 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub3:i32)
7631 : /*21588*/ /*Scope*/ 18, /*->21607*/
7632 : /*21589*/ OPC_CheckChild1Integer, 4,
7633 : /*21591*/ OPC_CheckType, MVT::f32,
7634 : /*21593*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7635 : /*21595*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub4,
7636 : /*21598*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7637 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7638 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 4:iPTR) - Complexity = 8
7639 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub4:i32)
7640 : /*21607*/ /*Scope*/ 18, /*->21626*/
7641 : /*21608*/ OPC_CheckChild1Integer, 5,
7642 : /*21610*/ OPC_CheckType, MVT::f32,
7643 : /*21612*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7644 : /*21614*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub5,
7645 : /*21617*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7646 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7647 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 5:iPTR) - Complexity = 8
7648 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub5:i32)
7649 : /*21626*/ /*Scope*/ 18, /*->21645*/
7650 : /*21627*/ OPC_CheckChild1Integer, 6,
7651 : /*21629*/ OPC_CheckType, MVT::f32,
7652 : /*21631*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7653 : /*21633*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub6,
7654 : /*21636*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7655 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7656 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 6:iPTR) - Complexity = 8
7657 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub6:i32)
7658 : /*21645*/ /*Scope*/ 18, /*->21664*/
7659 : /*21646*/ OPC_CheckChild1Integer, 7,
7660 : /*21648*/ OPC_CheckType, MVT::f32,
7661 : /*21650*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7662 : /*21652*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub7,
7663 : /*21655*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7664 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7665 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 7:iPTR) - Complexity = 8
7666 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub7:i32)
7667 : /*21664*/ /*Scope*/ 18, /*->21683*/
7668 : /*21665*/ OPC_CheckChild1Integer, 8,
7669 : /*21667*/ OPC_CheckType, MVT::f32,
7670 : /*21669*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7671 : /*21671*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub8,
7672 : /*21674*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7673 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7674 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 8:iPTR) - Complexity = 8
7675 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub8:i32)
7676 : /*21683*/ /*Scope*/ 18, /*->21702*/
7677 : /*21684*/ OPC_CheckChild1Integer, 9,
7678 : /*21686*/ OPC_CheckType, MVT::f32,
7679 : /*21688*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7680 : /*21690*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub9,
7681 : /*21693*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7682 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7683 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 9:iPTR) - Complexity = 8
7684 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub9:i32)
7685 : /*21702*/ /*Scope*/ 18, /*->21721*/
7686 : /*21703*/ OPC_CheckChild1Integer, 10,
7687 : /*21705*/ OPC_CheckType, MVT::f32,
7688 : /*21707*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7689 : /*21709*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub10,
7690 : /*21712*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7691 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7692 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 10:iPTR) - Complexity = 8
7693 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub10:i32)
7694 : /*21721*/ /*Scope*/ 18, /*->21740*/
7695 : /*21722*/ OPC_CheckChild1Integer, 11,
7696 : /*21724*/ OPC_CheckType, MVT::f32,
7697 : /*21726*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7698 : /*21728*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub11,
7699 : /*21731*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7700 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7701 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 11:iPTR) - Complexity = 8
7702 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub11:i32)
7703 : /*21740*/ /*Scope*/ 18, /*->21759*/
7704 : /*21741*/ OPC_CheckChild1Integer, 12,
7705 : /*21743*/ OPC_CheckType, MVT::f32,
7706 : /*21745*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7707 : /*21747*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub12,
7708 : /*21750*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7709 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7710 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 12:iPTR) - Complexity = 8
7711 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub12:i32)
7712 : /*21759*/ /*Scope*/ 18, /*->21778*/
7713 : /*21760*/ OPC_CheckChild1Integer, 13,
7714 : /*21762*/ OPC_CheckType, MVT::f32,
7715 : /*21764*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7716 : /*21766*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub13,
7717 : /*21769*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7718 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7719 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 13:iPTR) - Complexity = 8
7720 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub13:i32)
7721 : /*21778*/ /*Scope*/ 18, /*->21797*/
7722 : /*21779*/ OPC_CheckChild1Integer, 14,
7723 : /*21781*/ OPC_CheckType, MVT::f32,
7724 : /*21783*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7725 : /*21785*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub14,
7726 : /*21788*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7727 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7728 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 14:iPTR) - Complexity = 8
7729 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub14:i32)
7730 : /*21797*/ /*Scope*/ 18, /*->21816*/
7731 : /*21798*/ OPC_CheckChild1Integer, 15,
7732 : /*21800*/ OPC_CheckType, MVT::f32,
7733 : /*21802*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7734 : /*21804*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub15,
7735 : /*21807*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
7736 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 1,
7737 : // Src: (vector_extract:f32 v16f32:v16f32:$src, 15:iPTR) - Complexity = 8
7738 : // Dst: (EXTRACT_SUBREG:f32 ?:v16f32:$src, sub15:i32)
7739 : /*21816*/ /*Scope*/ 21, /*->21838*/
7740 : /*21817*/ OPC_RecordChild1, // #1 = $idx
7741 : /*21818*/ OPC_CheckChild1Type, MVT::i32,
7742 : /*21820*/ OPC_CheckType, MVT::f32,
7743 : /*21822*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7744 : /*21824*/ OPC_EmitInteger, MVT::i32, 0,
7745 : /*21827*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_SRC), 0,
7746 : 2/*#VTs*/, MVT::f32, MVT::i1, 3/*#Ops*/, 0, 1, 2,
7747 : // Src: (vector_extract:f32 v16f32:v16f32:$vec, i32:i32:$idx) - Complexity = 3
7748 : // Dst: (SI_INDIRECT_SRC:f32:i1 ?:v16f32:$vec, ?:i32:$idx, 0:i32)
7749 : /*21838*/ 0, /*End of Scope*/
7750 : /*21839*/ 0, /*End of Scope*/
7751 : /*21840*/ /*SwitchOpcode*/ 50, TARGET_VAL(AMDGPUISD::CONST_ADDRESS),// ->21893
7752 : /*21843*/ OPC_RecordChild0, // #0 = $src
7753 : /*21844*/ OPC_CheckChild0Type, MVT::i32,
7754 : /*21846*/ OPC_Scope, 15, /*->21863*/ // 2 children in Scope
7755 : /*21848*/ OPC_CheckType, MVT::i32,
7756 : /*21850*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
7757 : /*21852*/ OPC_CheckComplexPat, /*CP*/9, /*#*/0, // SelectGlobalValueConstantOffset:$src #1
7758 : /*21855*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CONST_COPY), 0|OPFL_Variadic1,
7759 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1,
7760 : // Src: (CONST_ADDRESS:i32 ADDRGA_CONST_OFFSET:i32:$src) - Complexity = 9
7761 : // Dst: (CONST_COPY:i32 ADDRGA_CONST_OFFSET:i32:$src)
7762 : /*21863*/ /*Scope*/ 28, /*->21892*/
7763 : /*21864*/ OPC_RecordChild1, // #1 = $BUFFER_ID
7764 : /*21865*/ OPC_MoveChild, 1,
7765 : /*21867*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
7766 : /*21870*/ OPC_CheckType, MVT::i32,
7767 : /*21872*/ OPC_MoveParent,
7768 : /*21873*/ OPC_CheckType, MVT::v4i32,
7769 : /*21875*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
7770 : /*21877*/ OPC_CheckComplexPat, /*CP*/10, /*#*/0, // SelectGlobalValueVariableOffset:$ptr #2 #3
7771 : /*21880*/ OPC_EmitConvertToTarget, 1,
7772 : /*21882*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_VTX_CONSTBUF), 0|OPFL_Variadic2,
7773 : 1/*#VTs*/, MVT::v4i32, 3/*#Ops*/, 2, 3, 4,
7774 : // Src: (CONST_ADDRESS:v4i32 ADDRGA_VAR_OFFSET:i32:$ptr, (imm:i32):$BUFFER_ID) - Complexity = 15
7775 : // Dst: (TEX_VTX_CONSTBUF:v4i32 ADDRGA_VAR_OFFSET:i32:$ptr, (imm:i32):$BUFFER_ID)
7776 : /*21892*/ 0, /*End of Scope*/
7777 : /*21893*/ /*SwitchOpcode*/ 25|128,27|128,1/*19865*/, TARGET_VAL(ISD::INTRINSIC_WO_CHAIN),// ->41763
7778 : /*21898*/ OPC_Scope, 14, /*->21914*/ // 81 children in Scope
7779 : /*21900*/ OPC_CheckChild0Integer, 1|128,37/*4737*/,
7780 : /*21903*/ OPC_RecordChild1, // #0 = $src0
7781 : /*21904*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
7782 : /*21906*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_FLBIT_I32), 0,
7783 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0,
7784 : // Src: (intrinsic_wo_chain:i32 4737:iPTR, i32:i32:$src0) - Complexity = 8
7785 : // Dst: (S_FLBIT_I32:i32 i32:i32:$src0)
7786 : /*21914*/ /*Scope*/ 40, /*->21955*/
7787 : /*21915*/ OPC_CheckChild0Integer, 20|128,38/*4884*/,
7788 : /*21918*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7789 : /*21920*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,15/*4294967295*/,
7790 : /*21927*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,15/*4294967295*/,
7791 : /*21934*/ OPC_EmitInteger, MVT::i32, 0,
7792 : /*21937*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MBCNT_LO_U32_B32_e64), 0,
7793 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
7794 : /*21946*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MBCNT_HI_U32_B32_e64), 0,
7795 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 3,
7796 : // Src: (intrinsic_wo_chain:i32 4884:iPTR) - Complexity = 8
7797 : // Dst: (V_MBCNT_HI_U32_B32_e64:i32 4294967295:i32, (V_MBCNT_LO_U32_B32_e64:i32 4294967295:i32, 0:i32))
7798 : /*21955*/ /*Scope*/ 24, /*->21980*/
7799 : /*21956*/ OPC_CheckChild0Integer, 12|128,38/*4876*/,
7800 : /*21959*/ OPC_RecordChild1, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
7801 : /*21960*/ OPC_RecordChild2, // #1 = $VOP3Mods:src1:src1_modifiers
7802 : /*21961*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
7803 : /*21964*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
7804 : /*21967*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_PKRTZ_F16_F32_e64), 0,
7805 : 1/*#VTs*/, MVT::i32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
7806 : // Src: (intrinsic_wo_chain:i32 4876:iPTR, (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers)) - Complexity = -968
7807 : // Dst: (V_CVT_PKRTZ_F16_F32_e64:i32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
7808 : /*21980*/ /*Scope*/ 1|128,1/*129*/, /*->22111*/
7809 : /*21982*/ OPC_CheckChild0Integer, 11|128,37/*4747*/,
7810 : /*21985*/ OPC_RecordChild1, // #0 = $src0
7811 : /*21986*/ OPC_RecordChild2, // #1 = $src1
7812 : /*21987*/ OPC_Scope, 101, /*->22090*/ // 2 children in Scope
7813 : /*21989*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
7814 : /*21991*/ OPC_EmitInteger, MVT::i32, 0,
7815 : /*21994*/ OPC_EmitInteger, MVT::i32, 0,
7816 : /*21997*/ OPC_EmitInteger, MVT::i32, 1,
7817 : /*22000*/ OPC_EmitInteger, MVT::i32, 0,
7818 : /*22003*/ OPC_EmitInteger, MVT::i32, 0,
7819 : /*22006*/ OPC_EmitInteger, MVT::i32, 0,
7820 : /*22009*/ OPC_EmitInteger, MVT::i32, 0,
7821 : /*22012*/ OPC_EmitInteger, MVT::i32, 0,
7822 : /*22015*/ OPC_EmitInteger, MVT::i32, 0,
7823 : /*22018*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
7824 : /*22030*/ OPC_EmitInteger, MVT::i32, 0,
7825 : /*22033*/ OPC_EmitInteger, MVT::i32, 0,
7826 : /*22036*/ OPC_EmitInteger, MVT::i32, 0,
7827 : /*22039*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
7828 : /*22051*/ OPC_EmitInteger, MVT::i32, 1,
7829 : /*22054*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
7830 : /*22057*/ OPC_EmitInteger, MVT::i32, 0,
7831 : /*22060*/ OPC_EmitInteger, MVT::i32, 0,
7832 : /*22063*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL), 0,
7833 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
7834 : // Src: (intrinsic_wo_chain:f32 4747:iPTR, R600_Reg32:f32:$src0, R600_Reg32:f32:$src1) - Complexity = 8
7835 : // Dst: (MUL:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1)
7836 : /*22090*/ /*Scope*/ 19, /*->22110*/
7837 : /*22091*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
7838 : /*22094*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
7839 : /*22097*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MUL_LEGACY_F32_e64), 0,
7840 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
7841 : // Src: (intrinsic_wo_chain:f32 4747:iPTR, (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers)) - Complexity = -968
7842 : // Dst: (V_MUL_LEGACY_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
7843 : /*22110*/ 0, /*End of Scope*/
7844 : /*22111*/ /*Scope*/ 19|128,4/*531*/, /*->22644*/
7845 : /*22113*/ OPC_CheckChild0Integer, 127|128,36/*4735*/,
7846 : /*22116*/ OPC_RecordChild1, // #0 = $src0
7847 : /*22117*/ OPC_RecordChild2, // #1 = $src1
7848 : /*22118*/ OPC_Scope, 38|128,1/*166*/, /*->22287*/ // 4 children in Scope
7849 : /*22121*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
7850 : /*22123*/ OPC_EmitInteger, MVT::i32, 0,
7851 : /*22126*/ OPC_EmitInteger, MVT::i32, 0,
7852 : /*22129*/ OPC_EmitInteger, MVT::i32, 1,
7853 : /*22132*/ OPC_EmitInteger, MVT::i32, 0,
7854 : /*22135*/ OPC_EmitInteger, MVT::i32, 0,
7855 : /*22138*/ OPC_EmitInteger, MVT::i32, 0,
7856 : /*22141*/ OPC_EmitInteger, MVT::i32, 0,
7857 : /*22144*/ OPC_EmitInteger, MVT::i32, 0,
7858 : /*22147*/ OPC_EmitInteger, MVT::i32, 0,
7859 : /*22150*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
7860 : /*22162*/ OPC_EmitInteger, MVT::i32, 1,
7861 : /*22165*/ OPC_EmitInteger, MVT::i32, 0,
7862 : /*22168*/ OPC_EmitInteger, MVT::i32, 0,
7863 : /*22171*/ OPC_EmitInteger, MVT::i32, 0,
7864 : /*22174*/ OPC_EmitInteger, MVT::i32, 0,
7865 : /*22177*/ OPC_EmitInteger, MVT::i32, 0,
7866 : /*22180*/ OPC_EmitInteger, MVT::i32, 0,
7867 : /*22183*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
7868 : /*22195*/ OPC_EmitInteger, MVT::i32, 1,
7869 : /*22198*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
7870 : /*22201*/ OPC_EmitInteger, MVT::i32, 0,
7871 : /*22204*/ OPC_EmitInteger, MVT::i32, 0,
7872 : /*22207*/ OPC_EmitNode, TARGET_VAL(AMDGPU::RECIP_IEEE_r600), 0,
7873 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 12, 13, 14, 15, 1, 16, 17, 18, 19, 20, 21, 22, 23, // Results = #24
7874 : /*22227*/ OPC_EmitInteger, MVT::i32, 0,
7875 : /*22230*/ OPC_EmitInteger, MVT::i32, 0,
7876 : /*22233*/ OPC_EmitInteger, MVT::i32, 0,
7877 : /*22236*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
7878 : /*22248*/ OPC_EmitInteger, MVT::i32, 1,
7879 : /*22251*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
7880 : /*22254*/ OPC_EmitInteger, MVT::i32, 0,
7881 : /*22257*/ OPC_EmitInteger, MVT::i32, 0,
7882 : /*22260*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL_IEEE), 0,
7883 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31, 32,
7884 : // Src: (intrinsic_wo_chain:f32 4735:iPTR, f32:f32:$src0, f32:f32:$src1) - Complexity = 8
7885 : // Dst: (MUL_IEEE:f32 ?:f32:$src0, (RECIP_IEEE_r600:i32 ?:f32:$src1))
7886 : /*22287*/ /*Scope*/ 38|128,1/*166*/, /*->22455*/
7887 : /*22289*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
7888 : /*22291*/ OPC_EmitInteger, MVT::i32, 0,
7889 : /*22294*/ OPC_EmitInteger, MVT::i32, 0,
7890 : /*22297*/ OPC_EmitInteger, MVT::i32, 1,
7891 : /*22300*/ OPC_EmitInteger, MVT::i32, 0,
7892 : /*22303*/ OPC_EmitInteger, MVT::i32, 0,
7893 : /*22306*/ OPC_EmitInteger, MVT::i32, 0,
7894 : /*22309*/ OPC_EmitInteger, MVT::i32, 0,
7895 : /*22312*/ OPC_EmitInteger, MVT::i32, 0,
7896 : /*22315*/ OPC_EmitInteger, MVT::i32, 0,
7897 : /*22318*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
7898 : /*22330*/ OPC_EmitInteger, MVT::i32, 1,
7899 : /*22333*/ OPC_EmitInteger, MVT::i32, 0,
7900 : /*22336*/ OPC_EmitInteger, MVT::i32, 0,
7901 : /*22339*/ OPC_EmitInteger, MVT::i32, 0,
7902 : /*22342*/ OPC_EmitInteger, MVT::i32, 0,
7903 : /*22345*/ OPC_EmitInteger, MVT::i32, 0,
7904 : /*22348*/ OPC_EmitInteger, MVT::i32, 0,
7905 : /*22351*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
7906 : /*22363*/ OPC_EmitInteger, MVT::i32, 1,
7907 : /*22366*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
7908 : /*22369*/ OPC_EmitInteger, MVT::i32, 0,
7909 : /*22372*/ OPC_EmitInteger, MVT::i32, 0,
7910 : /*22375*/ OPC_EmitNode, TARGET_VAL(AMDGPU::RECIP_IEEE_eg), 0,
7911 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 12, 13, 14, 15, 1, 16, 17, 18, 19, 20, 21, 22, 23, // Results = #24
7912 : /*22395*/ OPC_EmitInteger, MVT::i32, 0,
7913 : /*22398*/ OPC_EmitInteger, MVT::i32, 0,
7914 : /*22401*/ OPC_EmitInteger, MVT::i32, 0,
7915 : /*22404*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
7916 : /*22416*/ OPC_EmitInteger, MVT::i32, 1,
7917 : /*22419*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
7918 : /*22422*/ OPC_EmitInteger, MVT::i32, 0,
7919 : /*22425*/ OPC_EmitInteger, MVT::i32, 0,
7920 : /*22428*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL_IEEE), 0,
7921 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31, 32,
7922 : // Src: (intrinsic_wo_chain:f32 4735:iPTR, f32:f32:$src0, f32:f32:$src1) - Complexity = 8
7923 : // Dst: (MUL_IEEE:f32 ?:f32:$src0, (RECIP_IEEE_eg:i32 ?:f32:$src1))
7924 : /*22455*/ /*Scope*/ 38|128,1/*166*/, /*->22623*/
7925 : /*22457*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
7926 : /*22459*/ OPC_EmitInteger, MVT::i32, 0,
7927 : /*22462*/ OPC_EmitInteger, MVT::i32, 0,
7928 : /*22465*/ OPC_EmitInteger, MVT::i32, 1,
7929 : /*22468*/ OPC_EmitInteger, MVT::i32, 0,
7930 : /*22471*/ OPC_EmitInteger, MVT::i32, 0,
7931 : /*22474*/ OPC_EmitInteger, MVT::i32, 0,
7932 : /*22477*/ OPC_EmitInteger, MVT::i32, 0,
7933 : /*22480*/ OPC_EmitInteger, MVT::i32, 0,
7934 : /*22483*/ OPC_EmitInteger, MVT::i32, 0,
7935 : /*22486*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
7936 : /*22498*/ OPC_EmitInteger, MVT::i32, 1,
7937 : /*22501*/ OPC_EmitInteger, MVT::i32, 0,
7938 : /*22504*/ OPC_EmitInteger, MVT::i32, 0,
7939 : /*22507*/ OPC_EmitInteger, MVT::i32, 0,
7940 : /*22510*/ OPC_EmitInteger, MVT::i32, 0,
7941 : /*22513*/ OPC_EmitInteger, MVT::i32, 0,
7942 : /*22516*/ OPC_EmitInteger, MVT::i32, 0,
7943 : /*22519*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
7944 : /*22531*/ OPC_EmitInteger, MVT::i32, 1,
7945 : /*22534*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
7946 : /*22537*/ OPC_EmitInteger, MVT::i32, 0,
7947 : /*22540*/ OPC_EmitInteger, MVT::i32, 0,
7948 : /*22543*/ OPC_EmitNode, TARGET_VAL(AMDGPU::RECIP_IEEE_cm), 0,
7949 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 12, 13, 14, 15, 1, 16, 17, 18, 19, 20, 21, 22, 23, // Results = #24
7950 : /*22563*/ OPC_EmitInteger, MVT::i32, 0,
7951 : /*22566*/ OPC_EmitInteger, MVT::i32, 0,
7952 : /*22569*/ OPC_EmitInteger, MVT::i32, 0,
7953 : /*22572*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
7954 : /*22584*/ OPC_EmitInteger, MVT::i32, 1,
7955 : /*22587*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
7956 : /*22590*/ OPC_EmitInteger, MVT::i32, 0,
7957 : /*22593*/ OPC_EmitInteger, MVT::i32, 0,
7958 : /*22596*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL_IEEE), 0,
7959 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31, 32,
7960 : // Src: (intrinsic_wo_chain:f32 4735:iPTR, f32:f32:$src0, f32:f32:$src1) - Complexity = 8
7961 : // Dst: (MUL_IEEE:f32 ?:f32:$src0, (RECIP_IEEE_cm:i32 ?:f32:$src1))
7962 : /*22623*/ /*Scope*/ 19, /*->22643*/
7963 : /*22624*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7964 : /*22626*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_RCP_LEGACY_F32_e32), 0,
7965 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1, // Results = #2
7966 : /*22634*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MUL_LEGACY_F32_e32), 0,
7967 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 2,
7968 : // Src: (intrinsic_wo_chain:f32 4735:iPTR, f32:f32:$src0, f32:f32:$src1) - Complexity = 8
7969 : // Dst: (V_MUL_LEGACY_F32_e32:f32 ?:f32:$src0, (V_RCP_LEGACY_F32_e32:i32 ?:f32:$src1))
7970 : /*22643*/ 0, /*End of Scope*/
7971 : /*22644*/ /*Scope*/ 46, /*->22691*/
7972 : /*22645*/ OPC_CheckChild0Integer, 119|128,36/*4727*/,
7973 : /*22648*/ OPC_RecordChild1, // #0 = $src0
7974 : /*22649*/ OPC_RecordChild2, // #1 = $src1
7975 : /*22650*/ OPC_RecordChild3, // #2 = $src2
7976 : /*22651*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
7977 : /*22653*/ OPC_EmitInteger, MVT::i32, 0,
7978 : /*22656*/ OPC_EmitInteger, MVT::i32, 0,
7979 : /*22659*/ OPC_EmitInteger, MVT::i32, 0,
7980 : /*22662*/ OPC_EmitInteger, MVT::i1, 0,
7981 : /*22665*/ OPC_EmitInteger, MVT::i32, 0,
7982 : /*22668*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CMP_GT_F32_e64), 0,
7983 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 4, 5, 0, 6, 7, // Results = #8
7984 : /*22681*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
7985 : 1/*#VTs*/, MVT::f32, 3/*#Ops*/, 2, 1, 8,
7986 : // Src: (intrinsic_wo_chain:f32 4727:iPTR, f32:f32:$src0, f32:f32:$src1, f32:f32:$src2) - Complexity = 8
7987 : // Dst: (V_CNDMASK_B32_e64:f32 ?:f32:$src2, ?:f32:$src1, (V_CMP_GT_F32_e64:i1 0:i32, 0:i32, 0:i32, ?:f32:$src0, 0:i1, 0:i32))
7988 : /*22691*/ /*Scope*/ 34|128,5/*674*/, /*->23367*/
7989 : /*22693*/ OPC_CheckChild0Integer, 22|128,38/*4886*/,
7990 : /*22696*/ OPC_RecordChild1, // #0 = $src_x
7991 : /*22697*/ OPC_RecordChild2, // #1 = $src_y
7992 : /*22698*/ OPC_RecordChild3, // #2 = $src_w
7993 : /*22699*/ OPC_Scope, 75|128,2/*331*/, /*->23033*/ // 2 children in Scope
7994 : /*22702*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
7995 : /*22704*/ OPC_EmitInteger, MVT::i32, 1,
7996 : /*22707*/ OPC_EmitInteger, MVT::i32, 0,
7997 : /*22710*/ OPC_EmitInteger, MVT::i32, 0,
7998 : /*22713*/ OPC_EmitInteger, MVT::i32, 0,
7999 : /*22716*/ OPC_EmitInteger, MVT::i32, 0,
8000 : /*22719*/ OPC_EmitInteger, MVT::i32, 0,
8001 : /*22722*/ OPC_EmitInteger, MVT::i32, 1,
8002 : /*22725*/ OPC_EmitInteger, MVT::i32, 0,
8003 : /*22728*/ OPC_EmitInteger, MVT::i32, 0,
8004 : /*22731*/ OPC_EmitInteger, MVT::i32, 0,
8005 : /*22734*/ OPC_EmitInteger, MVT::i32, 0,
8006 : /*22737*/ OPC_EmitInteger, MVT::i32, 0,
8007 : /*22740*/ OPC_EmitInteger, MVT::i32, 1,
8008 : /*22743*/ OPC_EmitInteger, MVT::i32, 0,
8009 : /*22746*/ OPC_EmitInteger, MVT::i32, 0,
8010 : /*22749*/ OPC_EmitInteger, MVT::i32, 0,
8011 : /*22752*/ OPC_EmitInteger, MVT::i32, 0,
8012 : /*22755*/ OPC_EmitInteger, MVT::i32, 0,
8013 : /*22758*/ OPC_EmitInteger, MVT::i32, 0,
8014 : /*22761*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8015 : /*22773*/ OPC_EmitRegister, MVT::f32, AMDGPU::ZERO,
8016 : /*22776*/ OPC_EmitInteger, MVT::i32, 0,
8017 : /*22779*/ OPC_EmitInteger, MVT::i32, 0,
8018 : /*22782*/ OPC_EmitInteger, MVT::i32, 0,
8019 : /*22785*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8020 : /*22797*/ OPC_EmitInteger, MVT::i32, 1,
8021 : /*22800*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
8022 : /*22803*/ OPC_EmitInteger, MVT::i32, 0,
8023 : /*22806*/ OPC_EmitInteger, MVT::i32, 0,
8024 : /*22809*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MAX), 0,
8025 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 13, 14, 15, 16, 17, 18, 1, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, // Results = #32
8026 : /*22836*/ OPC_EmitInteger, MVT::i32, 0,
8027 : /*22839*/ OPC_EmitInteger, MVT::i32, 0,
8028 : /*22842*/ OPC_EmitInteger, MVT::i32, 0,
8029 : /*22845*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8030 : /*22857*/ OPC_EmitInteger, MVT::i32, 1,
8031 : /*22860*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
8032 : /*22863*/ OPC_EmitInteger, MVT::i32, 0,
8033 : /*22866*/ OPC_EmitInteger, MVT::i32, 0,
8034 : /*22869*/ OPC_EmitNode, TARGET_VAL(AMDGPU::LOG_CLAMPED_r600), 0,
8035 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 9, 10, 11, 12, 32, 33, 34, 35, 36, 37, 38, 39, 40, // Results = #41
8036 : /*22889*/ OPC_EmitInteger, MVT::i32, 0,
8037 : /*22892*/ OPC_EmitInteger, MVT::i32, 0,
8038 : /*22895*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8039 : /*22907*/ OPC_EmitInteger, MVT::i32, 0,
8040 : /*22910*/ OPC_EmitInteger, MVT::i32, 0,
8041 : /*22913*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8042 : /*22925*/ OPC_EmitInteger, MVT::i32, 0,
8043 : /*22928*/ OPC_EmitInteger, MVT::i32, 0,
8044 : /*22931*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8045 : /*22943*/ OPC_EmitInteger, MVT::i32, 1,
8046 : /*22946*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
8047 : /*22949*/ OPC_EmitInteger, MVT::i32, 0,
8048 : /*22952*/ OPC_EmitInteger, MVT::i32, 0,
8049 : /*22955*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MUL_LIT_r600), 0,
8050 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 7, 8, 41, 42, 43, 44, 2, 45, 46, 47, 0, 48, 49, 50, 51, 52, 53, 54, // Results = #55
8051 : /*22980*/ OPC_EmitInteger, MVT::i32, 0,
8052 : /*22983*/ OPC_EmitInteger, MVT::i32, 0,
8053 : /*22986*/ OPC_EmitInteger, MVT::i32, 0,
8054 : /*22989*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8055 : /*23001*/ OPC_EmitInteger, MVT::i32, 1,
8056 : /*23004*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
8057 : /*23007*/ OPC_EmitInteger, MVT::i32, 0,
8058 : /*23010*/ OPC_EmitInteger, MVT::i32, 0,
8059 : /*23013*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EXP_IEEE_r600), 0,
8060 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 3, 4, 5, 6, 55, 56, 57, 58, 59, 60, 61, 62, 63,
8061 : // Src: (intrinsic_wo_chain:f32 4886:iPTR, f32:f32:$src_x, f32:f32:$src_y, f32:f32:$src_w) - Complexity = 8
8062 : // Dst: (EXP_IEEE_r600:f32 (MUL_LIT_r600:i32 (LOG_CLAMPED_r600:i32 (MAX:i32 ?:f32:$src_y, ZERO:f32)), ?:f32:$src_w, ?:f32:$src_x))
8063 : /*23033*/ /*Scope*/ 75|128,2/*331*/, /*->23366*/
8064 : /*23035*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
8065 : /*23037*/ OPC_EmitInteger, MVT::i32, 1,
8066 : /*23040*/ OPC_EmitInteger, MVT::i32, 0,
8067 : /*23043*/ OPC_EmitInteger, MVT::i32, 0,
8068 : /*23046*/ OPC_EmitInteger, MVT::i32, 0,
8069 : /*23049*/ OPC_EmitInteger, MVT::i32, 0,
8070 : /*23052*/ OPC_EmitInteger, MVT::i32, 0,
8071 : /*23055*/ OPC_EmitInteger, MVT::i32, 1,
8072 : /*23058*/ OPC_EmitInteger, MVT::i32, 0,
8073 : /*23061*/ OPC_EmitInteger, MVT::i32, 0,
8074 : /*23064*/ OPC_EmitInteger, MVT::i32, 0,
8075 : /*23067*/ OPC_EmitInteger, MVT::i32, 0,
8076 : /*23070*/ OPC_EmitInteger, MVT::i32, 0,
8077 : /*23073*/ OPC_EmitInteger, MVT::i32, 1,
8078 : /*23076*/ OPC_EmitInteger, MVT::i32, 0,
8079 : /*23079*/ OPC_EmitInteger, MVT::i32, 0,
8080 : /*23082*/ OPC_EmitInteger, MVT::i32, 0,
8081 : /*23085*/ OPC_EmitInteger, MVT::i32, 0,
8082 : /*23088*/ OPC_EmitInteger, MVT::i32, 0,
8083 : /*23091*/ OPC_EmitInteger, MVT::i32, 0,
8084 : /*23094*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8085 : /*23106*/ OPC_EmitRegister, MVT::f32, AMDGPU::ZERO,
8086 : /*23109*/ OPC_EmitInteger, MVT::i32, 0,
8087 : /*23112*/ OPC_EmitInteger, MVT::i32, 0,
8088 : /*23115*/ OPC_EmitInteger, MVT::i32, 0,
8089 : /*23118*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8090 : /*23130*/ OPC_EmitInteger, MVT::i32, 1,
8091 : /*23133*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
8092 : /*23136*/ OPC_EmitInteger, MVT::i32, 0,
8093 : /*23139*/ OPC_EmitInteger, MVT::i32, 0,
8094 : /*23142*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MAX), 0,
8095 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 13, 14, 15, 16, 17, 18, 1, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, // Results = #32
8096 : /*23169*/ OPC_EmitInteger, MVT::i32, 0,
8097 : /*23172*/ OPC_EmitInteger, MVT::i32, 0,
8098 : /*23175*/ OPC_EmitInteger, MVT::i32, 0,
8099 : /*23178*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8100 : /*23190*/ OPC_EmitInteger, MVT::i32, 1,
8101 : /*23193*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
8102 : /*23196*/ OPC_EmitInteger, MVT::i32, 0,
8103 : /*23199*/ OPC_EmitInteger, MVT::i32, 0,
8104 : /*23202*/ OPC_EmitNode, TARGET_VAL(AMDGPU::LOG_CLAMPED_eg), 0,
8105 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 9, 10, 11, 12, 32, 33, 34, 35, 36, 37, 38, 39, 40, // Results = #41
8106 : /*23222*/ OPC_EmitInteger, MVT::i32, 0,
8107 : /*23225*/ OPC_EmitInteger, MVT::i32, 0,
8108 : /*23228*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8109 : /*23240*/ OPC_EmitInteger, MVT::i32, 0,
8110 : /*23243*/ OPC_EmitInteger, MVT::i32, 0,
8111 : /*23246*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8112 : /*23258*/ OPC_EmitInteger, MVT::i32, 0,
8113 : /*23261*/ OPC_EmitInteger, MVT::i32, 0,
8114 : /*23264*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8115 : /*23276*/ OPC_EmitInteger, MVT::i32, 1,
8116 : /*23279*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
8117 : /*23282*/ OPC_EmitInteger, MVT::i32, 0,
8118 : /*23285*/ OPC_EmitInteger, MVT::i32, 0,
8119 : /*23288*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MUL_LIT_eg), 0,
8120 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 7, 8, 41, 42, 43, 44, 2, 45, 46, 47, 0, 48, 49, 50, 51, 52, 53, 54, // Results = #55
8121 : /*23313*/ OPC_EmitInteger, MVT::i32, 0,
8122 : /*23316*/ OPC_EmitInteger, MVT::i32, 0,
8123 : /*23319*/ OPC_EmitInteger, MVT::i32, 0,
8124 : /*23322*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
8125 : /*23334*/ OPC_EmitInteger, MVT::i32, 1,
8126 : /*23337*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
8127 : /*23340*/ OPC_EmitInteger, MVT::i32, 0,
8128 : /*23343*/ OPC_EmitInteger, MVT::i32, 0,
8129 : /*23346*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EXP_IEEE_eg), 0,
8130 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 3, 4, 5, 6, 55, 56, 57, 58, 59, 60, 61, 62, 63,
8131 : // Src: (intrinsic_wo_chain:f32 4886:iPTR, f32:f32:$src_x, f32:f32:$src_y, f32:f32:$src_w) - Complexity = 8
8132 : // Dst: (EXP_IEEE_eg:f32 (MUL_LIT_eg:i32 (LOG_CLAMPED_eg:i32 (MAX:i32 ?:f32:$src_y, ZERO:f32)), ?:f32:$src_w, ?:f32:$src_x))
8133 : /*23366*/ 0, /*End of Scope*/
8134 : /*23367*/ /*Scope*/ 18|128,3/*402*/, /*->23771*/
8135 : /*23369*/ OPC_CheckChild0Integer, 9|128,38/*4873*/,
8136 : /*23372*/ OPC_RecordChild1, // #0 = $addr
8137 : /*23373*/ OPC_Scope, 68|128,1/*196*/, /*->23572*/ // 2 children in Scope
8138 : /*23376*/ OPC_CheckChild1Type, MVT::v2i32,
8139 : /*23378*/ OPC_RecordChild2, // #1 = $rsrc
8140 : /*23379*/ OPC_MoveChild, 3,
8141 : /*23381*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
8142 : /*23384*/ OPC_Scope, 46, /*->23432*/ // 4 children in Scope
8143 : /*23386*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
8144 : /*23388*/ OPC_MoveParent,
8145 : /*23389*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8146 : /*23391*/ OPC_EmitInteger, MVT::i32, 15,
8147 : /*23394*/ OPC_EmitInteger, MVT::i1, 0,
8148 : /*23397*/ OPC_EmitInteger, MVT::i1, 0,
8149 : /*23400*/ OPC_EmitInteger, MVT::i1, 1,
8150 : /*23403*/ OPC_EmitInteger, MVT::i1, 0,
8151 : /*23406*/ OPC_EmitInteger, MVT::i1, 0,
8152 : /*23409*/ OPC_EmitInteger, MVT::i1, 0,
8153 : /*23412*/ OPC_EmitInteger, MVT::i1, 0,
8154 : /*23415*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_MIP_V4_V2), 0,
8155 : 1/*#VTs*/, MVT::v4i32, 10/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
8156 : // Src: (intrinsic_wo_chain:v4i32 4873:iPTR, v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 12
8157 : // Dst: (IMAGE_LOAD_MIP_V4_V2:v4i32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc)
8158 : /*23432*/ /*Scope*/ 46, /*->23479*/
8159 : /*23433*/ OPC_CheckPredicate, 117, // Predicate_TEX_MSAA
8160 : /*23435*/ OPC_MoveParent,
8161 : /*23436*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8162 : /*23438*/ OPC_EmitInteger, MVT::i32, 15,
8163 : /*23441*/ OPC_EmitInteger, MVT::i1, 0,
8164 : /*23444*/ OPC_EmitInteger, MVT::i1, 0,
8165 : /*23447*/ OPC_EmitInteger, MVT::i1, 0,
8166 : /*23450*/ OPC_EmitInteger, MVT::i1, 0,
8167 : /*23453*/ OPC_EmitInteger, MVT::i1, 0,
8168 : /*23456*/ OPC_EmitInteger, MVT::i1, 0,
8169 : /*23459*/ OPC_EmitInteger, MVT::i1, 0,
8170 : /*23462*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_V4_V2), 0,
8171 : 1/*#VTs*/, MVT::v4i32, 10/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
8172 : // Src: (intrinsic_wo_chain:v4i32 4873:iPTR, v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, (imm:i32)<<P:Predicate_TEX_MSAA>>) - Complexity = 12
8173 : // Dst: (IMAGE_LOAD_V4_V2:v4i32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc)
8174 : /*23479*/ /*Scope*/ 46, /*->23526*/
8175 : /*23480*/ OPC_CheckPredicate, 118, // Predicate_TEX_ARRAY_MSAA
8176 : /*23482*/ OPC_MoveParent,
8177 : /*23483*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8178 : /*23485*/ OPC_EmitInteger, MVT::i32, 15,
8179 : /*23488*/ OPC_EmitInteger, MVT::i1, 0,
8180 : /*23491*/ OPC_EmitInteger, MVT::i1, 0,
8181 : /*23494*/ OPC_EmitInteger, MVT::i1, 1,
8182 : /*23497*/ OPC_EmitInteger, MVT::i1, 0,
8183 : /*23500*/ OPC_EmitInteger, MVT::i1, 0,
8184 : /*23503*/ OPC_EmitInteger, MVT::i1, 0,
8185 : /*23506*/ OPC_EmitInteger, MVT::i1, 0,
8186 : /*23509*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_V4_V2), 0,
8187 : 1/*#VTs*/, MVT::v4i32, 10/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
8188 : // Src: (intrinsic_wo_chain:v4i32 4873:iPTR, v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, (imm:i32)<<P:Predicate_TEX_ARRAY_MSAA>>) - Complexity = 12
8189 : // Dst: (IMAGE_LOAD_V4_V2:v4i32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc)
8190 : /*23526*/ /*Scope*/ 44, /*->23571*/
8191 : /*23527*/ OPC_MoveParent,
8192 : /*23528*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8193 : /*23530*/ OPC_EmitInteger, MVT::i32, 15,
8194 : /*23533*/ OPC_EmitInteger, MVT::i1, 0,
8195 : /*23536*/ OPC_EmitInteger, MVT::i1, 0,
8196 : /*23539*/ OPC_EmitInteger, MVT::i1, 0,
8197 : /*23542*/ OPC_EmitInteger, MVT::i1, 0,
8198 : /*23545*/ OPC_EmitInteger, MVT::i1, 0,
8199 : /*23548*/ OPC_EmitInteger, MVT::i1, 0,
8200 : /*23551*/ OPC_EmitInteger, MVT::i1, 0,
8201 : /*23554*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_MIP_V4_V2), 0,
8202 : 1/*#VTs*/, MVT::v4i32, 10/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
8203 : // Src: (intrinsic_wo_chain:v4i32 4873:iPTR, v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, (imm:i32)) - Complexity = 11
8204 : // Dst: (IMAGE_LOAD_MIP_V4_V2:v4i32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc)
8205 : /*23571*/ 0, /*End of Scope*/
8206 : /*23572*/ /*Scope*/ 68|128,1/*196*/, /*->23770*/
8207 : /*23574*/ OPC_CheckChild1Type, MVT::v4i32,
8208 : /*23576*/ OPC_RecordChild2, // #1 = $rsrc
8209 : /*23577*/ OPC_MoveChild, 3,
8210 : /*23579*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
8211 : /*23582*/ OPC_Scope, 46, /*->23630*/ // 4 children in Scope
8212 : /*23584*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
8213 : /*23586*/ OPC_MoveParent,
8214 : /*23587*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8215 : /*23589*/ OPC_EmitInteger, MVT::i32, 15,
8216 : /*23592*/ OPC_EmitInteger, MVT::i1, 0,
8217 : /*23595*/ OPC_EmitInteger, MVT::i1, 0,
8218 : /*23598*/ OPC_EmitInteger, MVT::i1, 1,
8219 : /*23601*/ OPC_EmitInteger, MVT::i1, 0,
8220 : /*23604*/ OPC_EmitInteger, MVT::i1, 0,
8221 : /*23607*/ OPC_EmitInteger, MVT::i1, 0,
8222 : /*23610*/ OPC_EmitInteger, MVT::i1, 0,
8223 : /*23613*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_MIP_V4_V4), 0,
8224 : 1/*#VTs*/, MVT::v4i32, 10/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
8225 : // Src: (intrinsic_wo_chain:v4i32 4873:iPTR, v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 12
8226 : // Dst: (IMAGE_LOAD_MIP_V4_V4:v4i32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc)
8227 : /*23630*/ /*Scope*/ 46, /*->23677*/
8228 : /*23631*/ OPC_CheckPredicate, 117, // Predicate_TEX_MSAA
8229 : /*23633*/ OPC_MoveParent,
8230 : /*23634*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8231 : /*23636*/ OPC_EmitInteger, MVT::i32, 15,
8232 : /*23639*/ OPC_EmitInteger, MVT::i1, 0,
8233 : /*23642*/ OPC_EmitInteger, MVT::i1, 0,
8234 : /*23645*/ OPC_EmitInteger, MVT::i1, 0,
8235 : /*23648*/ OPC_EmitInteger, MVT::i1, 0,
8236 : /*23651*/ OPC_EmitInteger, MVT::i1, 0,
8237 : /*23654*/ OPC_EmitInteger, MVT::i1, 0,
8238 : /*23657*/ OPC_EmitInteger, MVT::i1, 0,
8239 : /*23660*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_V4_V4), 0,
8240 : 1/*#VTs*/, MVT::v4i32, 10/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
8241 : // Src: (intrinsic_wo_chain:v4i32 4873:iPTR, v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, (imm:i32)<<P:Predicate_TEX_MSAA>>) - Complexity = 12
8242 : // Dst: (IMAGE_LOAD_V4_V4:v4i32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc)
8243 : /*23677*/ /*Scope*/ 46, /*->23724*/
8244 : /*23678*/ OPC_CheckPredicate, 118, // Predicate_TEX_ARRAY_MSAA
8245 : /*23680*/ OPC_MoveParent,
8246 : /*23681*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8247 : /*23683*/ OPC_EmitInteger, MVT::i32, 15,
8248 : /*23686*/ OPC_EmitInteger, MVT::i1, 0,
8249 : /*23689*/ OPC_EmitInteger, MVT::i1, 0,
8250 : /*23692*/ OPC_EmitInteger, MVT::i1, 1,
8251 : /*23695*/ OPC_EmitInteger, MVT::i1, 0,
8252 : /*23698*/ OPC_EmitInteger, MVT::i1, 0,
8253 : /*23701*/ OPC_EmitInteger, MVT::i1, 0,
8254 : /*23704*/ OPC_EmitInteger, MVT::i1, 0,
8255 : /*23707*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_V4_V4), 0,
8256 : 1/*#VTs*/, MVT::v4i32, 10/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
8257 : // Src: (intrinsic_wo_chain:v4i32 4873:iPTR, v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, (imm:i32)<<P:Predicate_TEX_ARRAY_MSAA>>) - Complexity = 12
8258 : // Dst: (IMAGE_LOAD_V4_V4:v4i32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc)
8259 : /*23724*/ /*Scope*/ 44, /*->23769*/
8260 : /*23725*/ OPC_MoveParent,
8261 : /*23726*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8262 : /*23728*/ OPC_EmitInteger, MVT::i32, 15,
8263 : /*23731*/ OPC_EmitInteger, MVT::i1, 0,
8264 : /*23734*/ OPC_EmitInteger, MVT::i1, 0,
8265 : /*23737*/ OPC_EmitInteger, MVT::i1, 0,
8266 : /*23740*/ OPC_EmitInteger, MVT::i1, 0,
8267 : /*23743*/ OPC_EmitInteger, MVT::i1, 0,
8268 : /*23746*/ OPC_EmitInteger, MVT::i1, 0,
8269 : /*23749*/ OPC_EmitInteger, MVT::i1, 0,
8270 : /*23752*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_MIP_V4_V4), 0,
8271 : 1/*#VTs*/, MVT::v4i32, 10/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
8272 : // Src: (intrinsic_wo_chain:v4i32 4873:iPTR, v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, (imm:i32)) - Complexity = 11
8273 : // Dst: (IMAGE_LOAD_MIP_V4_V4:v4i32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc)
8274 : /*23769*/ 0, /*End of Scope*/
8275 : /*23770*/ 0, /*End of Scope*/
8276 : /*23771*/ /*Scope*/ 47|128,1/*175*/, /*->23948*/
8277 : /*23773*/ OPC_CheckChild0Integer, 13|128,38/*4877*/,
8278 : /*23776*/ OPC_RecordChild1, // #0 = $mipid
8279 : /*23777*/ OPC_RecordChild2, // #1 = $rsrc
8280 : /*23778*/ OPC_MoveChild, 3,
8281 : /*23780*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
8282 : /*23783*/ OPC_Scope, 54, /*->23839*/ // 3 children in Scope
8283 : /*23785*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
8284 : /*23787*/ OPC_MoveParent,
8285 : /*23788*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8286 : /*23790*/ OPC_EmitInteger, MVT::i32, 15,
8287 : /*23793*/ OPC_EmitInteger, MVT::i1, 0,
8288 : /*23796*/ OPC_EmitInteger, MVT::i1, 0,
8289 : /*23799*/ OPC_EmitInteger, MVT::i1, 1,
8290 : /*23802*/ OPC_EmitInteger, MVT::i1, 0,
8291 : /*23805*/ OPC_EmitInteger, MVT::i1, 0,
8292 : /*23808*/ OPC_EmitInteger, MVT::i1, 0,
8293 : /*23811*/ OPC_EmitInteger, MVT::i1, 0,
8294 : /*23814*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
8295 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0, // Results = #10
8296 : /*23822*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GET_RESINFO_V4_V1), 0,
8297 : 1/*#VTs*/, MVT::v4i32, 10/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 10, 1,
8298 : // Src: (intrinsic_wo_chain:v4i32 4877:iPTR, i32:i32:$mipid, v32i8:v32i8:$rsrc, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 12
8299 : // Dst: (IMAGE_GET_RESINFO_V4_V1:v4i32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, (V_MOV_B32_e32:i32 ?:i32:$mipid), ?:v32i8:$rsrc)
8300 : /*23839*/ /*Scope*/ 54, /*->23894*/
8301 : /*23840*/ OPC_CheckPredicate, 118, // Predicate_TEX_ARRAY_MSAA
8302 : /*23842*/ OPC_MoveParent,
8303 : /*23843*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8304 : /*23845*/ OPC_EmitInteger, MVT::i32, 15,
8305 : /*23848*/ OPC_EmitInteger, MVT::i1, 0,
8306 : /*23851*/ OPC_EmitInteger, MVT::i1, 0,
8307 : /*23854*/ OPC_EmitInteger, MVT::i1, 1,
8308 : /*23857*/ OPC_EmitInteger, MVT::i1, 0,
8309 : /*23860*/ OPC_EmitInteger, MVT::i1, 0,
8310 : /*23863*/ OPC_EmitInteger, MVT::i1, 0,
8311 : /*23866*/ OPC_EmitInteger, MVT::i1, 0,
8312 : /*23869*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
8313 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0, // Results = #10
8314 : /*23877*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GET_RESINFO_V4_V1), 0,
8315 : 1/*#VTs*/, MVT::v4i32, 10/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 10, 1,
8316 : // Src: (intrinsic_wo_chain:v4i32 4877:iPTR, i32:i32:$mipid, v32i8:v32i8:$rsrc, (imm:i32)<<P:Predicate_TEX_ARRAY_MSAA>>) - Complexity = 12
8317 : // Dst: (IMAGE_GET_RESINFO_V4_V1:v4i32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, (V_MOV_B32_e32:i32 ?:i32:$mipid), ?:v32i8:$rsrc)
8318 : /*23894*/ /*Scope*/ 52, /*->23947*/
8319 : /*23895*/ OPC_MoveParent,
8320 : /*23896*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8321 : /*23898*/ OPC_EmitInteger, MVT::i32, 15,
8322 : /*23901*/ OPC_EmitInteger, MVT::i1, 0,
8323 : /*23904*/ OPC_EmitInteger, MVT::i1, 0,
8324 : /*23907*/ OPC_EmitInteger, MVT::i1, 0,
8325 : /*23910*/ OPC_EmitInteger, MVT::i1, 0,
8326 : /*23913*/ OPC_EmitInteger, MVT::i1, 0,
8327 : /*23916*/ OPC_EmitInteger, MVT::i1, 0,
8328 : /*23919*/ OPC_EmitInteger, MVT::i1, 0,
8329 : /*23922*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
8330 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0, // Results = #10
8331 : /*23930*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GET_RESINFO_V4_V1), 0,
8332 : 1/*#VTs*/, MVT::v4i32, 10/*#Ops*/, 2, 3, 4, 5, 6, 7, 8, 9, 10, 1,
8333 : // Src: (intrinsic_wo_chain:v4i32 4877:iPTR, i32:i32:$mipid, v32i8:v32i8:$rsrc, (imm:i32)) - Complexity = 11
8334 : // Dst: (IMAGE_GET_RESINFO_V4_V1:v4i32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, (V_MOV_B32_e32:i32 ?:i32:$mipid), ?:v32i8:$rsrc)
8335 : /*23947*/ 0, /*End of Scope*/
8336 : /*23948*/ /*Scope*/ 28, /*->23977*/
8337 : /*23949*/ OPC_CheckChild0Integer, 45|128,37/*4781*/,
8338 : /*23952*/ OPC_RecordChild1, // #0 = $ptr
8339 : /*23953*/ OPC_RecordChild2, // #1 = $BUFFER_ID
8340 : /*23954*/ OPC_MoveChild, 2,
8341 : /*23956*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
8342 : /*23959*/ OPC_MoveParent,
8343 : /*23960*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
8344 : /*23962*/ OPC_CheckComplexPat, /*CP*/10, /*#*/0, // SelectGlobalValueVariableOffset:$ptr #2 #3
8345 : /*23965*/ OPC_EmitConvertToTarget, 1,
8346 : /*23967*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_VTX_TEXBUF), 0,
8347 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 2, 3, 4,
8348 : // Src: (intrinsic_wo_chain:v4f32 4781:iPTR, ADDRGA_VAR_OFFSET:i32:$ptr, (imm:i32):$BUFFER_ID) - Complexity = 20
8349 : // Dst: (TEX_VTX_TEXBUF:v4f32 ADDRGA_VAR_OFFSET:i32:$ptr, (imm:i32):$BUFFER_ID)
8350 : /*23977*/ /*Scope*/ 76, /*->24054*/
8351 : /*23978*/ OPC_CheckChild0Integer, 24|128,37/*4760*/,
8352 : /*23981*/ OPC_RecordChild1, // #0 = $src0
8353 : /*23982*/ OPC_RecordChild2, // #1 = $src1
8354 : /*23983*/ OPC_RecordChild3, // #2 = $src2
8355 : /*23984*/ OPC_RecordChild4, // #3 = $resourceId
8356 : /*23985*/ OPC_MoveChild, 4,
8357 : /*23987*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
8358 : /*23990*/ OPC_MoveParent,
8359 : /*23991*/ OPC_RecordChild5, // #4 = $samplerId
8360 : /*23992*/ OPC_MoveChild, 5,
8361 : /*23994*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
8362 : /*23997*/ OPC_MoveParent,
8363 : /*23998*/ OPC_RecordChild6, // #5 = $textureTarget
8364 : /*23999*/ OPC_MoveChild, 6,
8365 : /*24001*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
8366 : /*24004*/ OPC_Scope, 24, /*->24030*/ // 2 children in Scope
8367 : /*24006*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
8368 : /*24008*/ OPC_MoveParent,
8369 : /*24009*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
8370 : /*24011*/ OPC_EmitConvertToTarget, 3,
8371 : /*24013*/ OPC_EmitConvertToTarget, 4,
8372 : /*24015*/ OPC_EmitConvertToTarget, 5,
8373 : /*24017*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TXD_SHADOW), 0,
8374 : 1/*#VTs*/, MVT::v4f32, 6/*#Ops*/, 0, 1, 2, 6, 7, 8,
8375 : // Src: (intrinsic_wo_chain:v4f32 4760:iPTR, v4f32:v4f32:$src0, v4f32:v4f32:$src1, v4f32:v4f32:$src2, (imm:i32):$resourceId, (imm:i32):$samplerId, (imm:i32)<<P:Predicate_TEX_SHADOW>>:$textureTarget) - Complexity = 18
8376 : // Dst: (TXD_SHADOW:v4f32 v4f32:v4f32:$src0, v4f32:v4f32:$src1, v4f32:v4f32:$src2, (imm:i32):$resourceId, (imm:i32):$samplerId, (imm:i32):$textureTarget)
8377 : /*24030*/ /*Scope*/ 22, /*->24053*/
8378 : /*24031*/ OPC_MoveParent,
8379 : /*24032*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
8380 : /*24034*/ OPC_EmitConvertToTarget, 3,
8381 : /*24036*/ OPC_EmitConvertToTarget, 4,
8382 : /*24038*/ OPC_EmitConvertToTarget, 5,
8383 : /*24040*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TXD), 0,
8384 : 1/*#VTs*/, MVT::v4f32, 6/*#Ops*/, 0, 1, 2, 6, 7, 8,
8385 : // Src: (intrinsic_wo_chain:v4f32 4760:iPTR, v4f32:v4f32:$src0, v4f32:v4f32:$src1, v4f32:v4f32:$src2, (imm:i32):$resourceId, (imm:i32):$samplerId, (imm:i32):$textureTarget) - Complexity = 17
8386 : // Dst: (TXD:v4f32 v4f32:v4f32:$src0, v4f32:v4f32:$src1, v4f32:v4f32:$src2, (imm:i32):$resourceId, (imm:i32):$samplerId, (imm:i32):$textureTarget)
8387 : /*24053*/ 0, /*End of Scope*/
8388 : /*24054*/ /*Scope*/ 20, /*->24075*/
8389 : /*24055*/ OPC_CheckChild0Integer, 39|128,37/*4775*/,
8390 : /*24058*/ OPC_RecordChild1, // #0 = $src0
8391 : /*24059*/ OPC_MoveChild, 1,
8392 : /*24061*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
8393 : /*24064*/ OPC_MoveParent,
8394 : /*24065*/ OPC_EmitConvertToTarget, 0,
8395 : /*24067*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::INTERP_VEC_LOAD), 0,
8396 : 1/*#VTs*/, MVT::v4f32, 1/*#Ops*/, 1,
8397 : // Src: (intrinsic_wo_chain:v4f32 4775:iPTR, (imm:i32):$src0) - Complexity = 11
8398 : // Dst: (INTERP_VEC_LOAD:v4f32 (imm:i32):$src0)
8399 : /*24075*/ /*Scope*/ 71|128,2/*327*/, /*->24404*/
8400 : /*24077*/ OPC_CheckChild0Integer, 120|128,36/*4728*/,
8401 : /*24080*/ OPC_RecordChild1, // #0 = $src0
8402 : /*24081*/ OPC_Scope, 10, /*->24093*/ // 3 children in Scope
8403 : /*24083*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
8404 : /*24085*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CUBE_r600_pseudo), 0,
8405 : 1/*#VTs*/, MVT::v4f32, 1/*#Ops*/, 0,
8406 : // Src: (intrinsic_wo_chain:v4f32 4728:iPTR, v4f32:v4f32:$src0) - Complexity = 8
8407 : // Dst: (CUBE_r600_pseudo:v4f32 v4f32:v4f32:$src0)
8408 : /*24093*/ /*Scope*/ 10, /*->24104*/
8409 : /*24094*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
8410 : /*24096*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CUBE_eg_pseudo), 0,
8411 : 1/*#VTs*/, MVT::v4f32, 1/*#Ops*/, 0,
8412 : // Src: (intrinsic_wo_chain:v4f32 4728:iPTR, v4f32:v4f32:$src0) - Complexity = 8
8413 : // Dst: (CUBE_eg_pseudo:v4f32 v4f32:v4f32:$src0)
8414 : /*24104*/ /*Scope*/ 41|128,2/*297*/, /*->24403*/
8415 : /*24106*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8416 : /*24108*/ OPC_EmitInteger, MVT::i32, AMDGPU::VReg_128RegClassID,
8417 : /*24111*/ OPC_EmitInteger, MVT::i32, 0,
8418 : /*24114*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
8419 : /*24117*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8420 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 3, // Results = #4
8421 : /*24126*/ OPC_EmitInteger, MVT::i32, 0,
8422 : /*24129*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
8423 : /*24132*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8424 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 6, // Results = #7
8425 : /*24141*/ OPC_EmitInteger, MVT::i32, 0,
8426 : /*24144*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
8427 : /*24147*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8428 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 9, // Results = #10
8429 : /*24156*/ OPC_EmitInteger, MVT::i1, 0,
8430 : /*24159*/ OPC_EmitInteger, MVT::i32, 0,
8431 : /*24162*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CUBETC_F32), 0,
8432 : 1/*#VTs*/, MVT::i32, 8/*#Ops*/, 2, 4, 5, 7, 8, 10, 11, 12, // Results = #13
8433 : /*24177*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
8434 : /*24180*/ OPC_EmitInteger, MVT::i32, 0,
8435 : /*24183*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
8436 : /*24186*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8437 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 16, // Results = #17
8438 : /*24195*/ OPC_EmitInteger, MVT::i32, 0,
8439 : /*24198*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
8440 : /*24201*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8441 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 19, // Results = #20
8442 : /*24210*/ OPC_EmitInteger, MVT::i32, 0,
8443 : /*24213*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
8444 : /*24216*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8445 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 22, // Results = #23
8446 : /*24225*/ OPC_EmitInteger, MVT::i1, 0,
8447 : /*24228*/ OPC_EmitInteger, MVT::i32, 0,
8448 : /*24231*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CUBESC_F32), 0,
8449 : 1/*#VTs*/, MVT::i32, 8/*#Ops*/, 15, 17, 18, 20, 21, 23, 24, 25, // Results = #26
8450 : /*24246*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
8451 : /*24249*/ OPC_EmitInteger, MVT::i32, 0,
8452 : /*24252*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
8453 : /*24255*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8454 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 29, // Results = #30
8455 : /*24264*/ OPC_EmitInteger, MVT::i32, 0,
8456 : /*24267*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
8457 : /*24270*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8458 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 32, // Results = #33
8459 : /*24279*/ OPC_EmitInteger, MVT::i32, 0,
8460 : /*24282*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
8461 : /*24285*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8462 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 35, // Results = #36
8463 : /*24294*/ OPC_EmitInteger, MVT::i1, 0,
8464 : /*24297*/ OPC_EmitInteger, MVT::i32, 0,
8465 : /*24300*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CUBEMA_F32), 0,
8466 : 1/*#VTs*/, MVT::i32, 8/*#Ops*/, 28, 30, 31, 33, 34, 36, 37, 38, // Results = #39
8467 : /*24315*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
8468 : /*24318*/ OPC_EmitInteger, MVT::i32, 0,
8469 : /*24321*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
8470 : /*24324*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8471 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 42, // Results = #43
8472 : /*24333*/ OPC_EmitInteger, MVT::i32, 0,
8473 : /*24336*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
8474 : /*24339*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8475 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 45, // Results = #46
8476 : /*24348*/ OPC_EmitInteger, MVT::i32, 0,
8477 : /*24351*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
8478 : /*24354*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
8479 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 48, // Results = #49
8480 : /*24363*/ OPC_EmitInteger, MVT::i1, 0,
8481 : /*24366*/ OPC_EmitInteger, MVT::i32, 0,
8482 : /*24369*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CUBEID_F32), 0,
8483 : 1/*#VTs*/, MVT::i32, 8/*#Ops*/, 41, 43, 44, 46, 47, 49, 50, 51, // Results = #52
8484 : /*24384*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
8485 : /*24387*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
8486 : 1/*#VTs*/, MVT::v4f32, 9/*#Ops*/, 1, 13, 14, 26, 27, 39, 40, 52, 53,
8487 : // Src: (intrinsic_wo_chain:v4f32 4728:iPTR, v4f32:v4f32:$src) - Complexity = 8
8488 : // Dst: (REG_SEQUENCE:v4f32 VReg_128:i32, (V_CUBETC_F32:i32 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub0:i32), 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub1:i32), 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub2:i32), 0:i1, 0:i32), sub0:i32, (V_CUBESC_F32:i32 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub0:i32), 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub1:i32), 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub2:i32), 0:i1, 0:i32), sub1:i32, (V_CUBEMA_F32:i32 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub0:i32), 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub1:i32), 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub2:i32), 0:i1, 0:i32), sub2:i32, (V_CUBEID_F32:i32 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub0:i32), 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub1:i32), 0:i32, (EXTRACT_SUBREG:i32 ?:v4f32:$src, sub2:i32), 0:i1, 0:i32), sub3:i32)
8489 : /*24403*/ 0, /*End of Scope*/
8490 : /*24404*/ /*Scope*/ 95|128,2/*351*/, /*->24757*/
8491 : /*24406*/ OPC_CheckChild0Integer, 97|128,37/*4833*/,
8492 : /*24409*/ OPC_RecordChild1, // #0 = $addr
8493 : /*24410*/ OPC_Scope, 68, /*->24480*/ // 5 children in Scope
8494 : /*24412*/ OPC_CheckChild1Type, MVT::i32,
8495 : /*24414*/ OPC_RecordChild2, // #1 = $rsrc
8496 : /*24415*/ OPC_RecordChild3, // #2 = $sampler
8497 : /*24416*/ OPC_RecordChild4, // #3 = $dmask
8498 : /*24417*/ OPC_RecordChild5, // #4 = $unorm
8499 : /*24418*/ OPC_RecordChild6, // #5 = $r128
8500 : /*24419*/ OPC_RecordChild7, // #6 = $da
8501 : /*24420*/ OPC_MoveChild, 8,
8502 : /*24422*/ OPC_RecordNode, // #7 = $glc
8503 : /*24423*/ OPC_MoveParent,
8504 : /*24424*/ OPC_MoveChild, 9,
8505 : /*24426*/ OPC_RecordNode, // #8 = $slc
8506 : /*24427*/ OPC_MoveParent,
8507 : /*24428*/ OPC_MoveChild, 10,
8508 : /*24430*/ OPC_RecordNode, // #9 = $tfe
8509 : /*24431*/ OPC_MoveParent,
8510 : /*24432*/ OPC_MoveChild, 11,
8511 : /*24434*/ OPC_RecordNode, // #10 = $lwe
8512 : /*24435*/ OPC_MoveParent,
8513 : /*24436*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8514 : /*24438*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8515 : /*24441*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8516 : /*24444*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8517 : /*24447*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8518 : /*24450*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8519 : /*24453*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8520 : /*24456*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8521 : /*24459*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8522 : /*24462*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V1), 0,
8523 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8524 : // Src: (intrinsic_wo_chain:v4f32 4833:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8525 : // Dst: (IMAGE_SAMPLE_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8526 : /*24480*/ /*Scope*/ 68, /*->24549*/
8527 : /*24481*/ OPC_CheckChild1Type, MVT::v2i32,
8528 : /*24483*/ OPC_RecordChild2, // #1 = $rsrc
8529 : /*24484*/ OPC_RecordChild3, // #2 = $sampler
8530 : /*24485*/ OPC_RecordChild4, // #3 = $dmask
8531 : /*24486*/ OPC_RecordChild5, // #4 = $unorm
8532 : /*24487*/ OPC_RecordChild6, // #5 = $r128
8533 : /*24488*/ OPC_RecordChild7, // #6 = $da
8534 : /*24489*/ OPC_MoveChild, 8,
8535 : /*24491*/ OPC_RecordNode, // #7 = $glc
8536 : /*24492*/ OPC_MoveParent,
8537 : /*24493*/ OPC_MoveChild, 9,
8538 : /*24495*/ OPC_RecordNode, // #8 = $slc
8539 : /*24496*/ OPC_MoveParent,
8540 : /*24497*/ OPC_MoveChild, 10,
8541 : /*24499*/ OPC_RecordNode, // #9 = $tfe
8542 : /*24500*/ OPC_MoveParent,
8543 : /*24501*/ OPC_MoveChild, 11,
8544 : /*24503*/ OPC_RecordNode, // #10 = $lwe
8545 : /*24504*/ OPC_MoveParent,
8546 : /*24505*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8547 : /*24507*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8548 : /*24510*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8549 : /*24513*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8550 : /*24516*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8551 : /*24519*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8552 : /*24522*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8553 : /*24525*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8554 : /*24528*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8555 : /*24531*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V2), 0,
8556 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8557 : // Src: (intrinsic_wo_chain:v4f32 4833:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8558 : // Dst: (IMAGE_SAMPLE_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8559 : /*24549*/ /*Scope*/ 68, /*->24618*/
8560 : /*24550*/ OPC_CheckChild1Type, MVT::v4i32,
8561 : /*24552*/ OPC_RecordChild2, // #1 = $rsrc
8562 : /*24553*/ OPC_RecordChild3, // #2 = $sampler
8563 : /*24554*/ OPC_RecordChild4, // #3 = $dmask
8564 : /*24555*/ OPC_RecordChild5, // #4 = $unorm
8565 : /*24556*/ OPC_RecordChild6, // #5 = $r128
8566 : /*24557*/ OPC_RecordChild7, // #6 = $da
8567 : /*24558*/ OPC_MoveChild, 8,
8568 : /*24560*/ OPC_RecordNode, // #7 = $glc
8569 : /*24561*/ OPC_MoveParent,
8570 : /*24562*/ OPC_MoveChild, 9,
8571 : /*24564*/ OPC_RecordNode, // #8 = $slc
8572 : /*24565*/ OPC_MoveParent,
8573 : /*24566*/ OPC_MoveChild, 10,
8574 : /*24568*/ OPC_RecordNode, // #9 = $tfe
8575 : /*24569*/ OPC_MoveParent,
8576 : /*24570*/ OPC_MoveChild, 11,
8577 : /*24572*/ OPC_RecordNode, // #10 = $lwe
8578 : /*24573*/ OPC_MoveParent,
8579 : /*24574*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8580 : /*24576*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8581 : /*24579*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8582 : /*24582*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8583 : /*24585*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8584 : /*24588*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8585 : /*24591*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8586 : /*24594*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8587 : /*24597*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8588 : /*24600*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V4), 0,
8589 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8590 : // Src: (intrinsic_wo_chain:v4f32 4833:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8591 : // Dst: (IMAGE_SAMPLE_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8592 : /*24618*/ /*Scope*/ 68, /*->24687*/
8593 : /*24619*/ OPC_CheckChild1Type, MVT::v8i32,
8594 : /*24621*/ OPC_RecordChild2, // #1 = $rsrc
8595 : /*24622*/ OPC_RecordChild3, // #2 = $sampler
8596 : /*24623*/ OPC_RecordChild4, // #3 = $dmask
8597 : /*24624*/ OPC_RecordChild5, // #4 = $unorm
8598 : /*24625*/ OPC_RecordChild6, // #5 = $r128
8599 : /*24626*/ OPC_RecordChild7, // #6 = $da
8600 : /*24627*/ OPC_MoveChild, 8,
8601 : /*24629*/ OPC_RecordNode, // #7 = $glc
8602 : /*24630*/ OPC_MoveParent,
8603 : /*24631*/ OPC_MoveChild, 9,
8604 : /*24633*/ OPC_RecordNode, // #8 = $slc
8605 : /*24634*/ OPC_MoveParent,
8606 : /*24635*/ OPC_MoveChild, 10,
8607 : /*24637*/ OPC_RecordNode, // #9 = $tfe
8608 : /*24638*/ OPC_MoveParent,
8609 : /*24639*/ OPC_MoveChild, 11,
8610 : /*24641*/ OPC_RecordNode, // #10 = $lwe
8611 : /*24642*/ OPC_MoveParent,
8612 : /*24643*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8613 : /*24645*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8614 : /*24648*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8615 : /*24651*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8616 : /*24654*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8617 : /*24657*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8618 : /*24660*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8619 : /*24663*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8620 : /*24666*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8621 : /*24669*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V8), 0,
8622 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8623 : // Src: (intrinsic_wo_chain:v4f32 4833:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8624 : // Dst: (IMAGE_SAMPLE_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8625 : /*24687*/ /*Scope*/ 68, /*->24756*/
8626 : /*24688*/ OPC_CheckChild1Type, MVT::v16i32,
8627 : /*24690*/ OPC_RecordChild2, // #1 = $rsrc
8628 : /*24691*/ OPC_RecordChild3, // #2 = $sampler
8629 : /*24692*/ OPC_RecordChild4, // #3 = $dmask
8630 : /*24693*/ OPC_RecordChild5, // #4 = $unorm
8631 : /*24694*/ OPC_RecordChild6, // #5 = $r128
8632 : /*24695*/ OPC_RecordChild7, // #6 = $da
8633 : /*24696*/ OPC_MoveChild, 8,
8634 : /*24698*/ OPC_RecordNode, // #7 = $glc
8635 : /*24699*/ OPC_MoveParent,
8636 : /*24700*/ OPC_MoveChild, 9,
8637 : /*24702*/ OPC_RecordNode, // #8 = $slc
8638 : /*24703*/ OPC_MoveParent,
8639 : /*24704*/ OPC_MoveChild, 10,
8640 : /*24706*/ OPC_RecordNode, // #9 = $tfe
8641 : /*24707*/ OPC_MoveParent,
8642 : /*24708*/ OPC_MoveChild, 11,
8643 : /*24710*/ OPC_RecordNode, // #10 = $lwe
8644 : /*24711*/ OPC_MoveParent,
8645 : /*24712*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8646 : /*24714*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8647 : /*24717*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8648 : /*24720*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8649 : /*24723*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8650 : /*24726*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8651 : /*24729*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8652 : /*24732*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8653 : /*24735*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8654 : /*24738*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V16), 0,
8655 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8656 : // Src: (intrinsic_wo_chain:v4f32 4833:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8657 : // Dst: (IMAGE_SAMPLE_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8658 : /*24756*/ 0, /*End of Scope*/
8659 : /*24757*/ /*Scope*/ 95|128,2/*351*/, /*->25110*/
8660 : /*24759*/ OPC_CheckChild0Integer, 126|128,37/*4862*/,
8661 : /*24762*/ OPC_RecordChild1, // #0 = $addr
8662 : /*24763*/ OPC_Scope, 68, /*->24833*/ // 5 children in Scope
8663 : /*24765*/ OPC_CheckChild1Type, MVT::i32,
8664 : /*24767*/ OPC_RecordChild2, // #1 = $rsrc
8665 : /*24768*/ OPC_RecordChild3, // #2 = $sampler
8666 : /*24769*/ OPC_RecordChild4, // #3 = $dmask
8667 : /*24770*/ OPC_RecordChild5, // #4 = $unorm
8668 : /*24771*/ OPC_RecordChild6, // #5 = $r128
8669 : /*24772*/ OPC_RecordChild7, // #6 = $da
8670 : /*24773*/ OPC_MoveChild, 8,
8671 : /*24775*/ OPC_RecordNode, // #7 = $glc
8672 : /*24776*/ OPC_MoveParent,
8673 : /*24777*/ OPC_MoveChild, 9,
8674 : /*24779*/ OPC_RecordNode, // #8 = $slc
8675 : /*24780*/ OPC_MoveParent,
8676 : /*24781*/ OPC_MoveChild, 10,
8677 : /*24783*/ OPC_RecordNode, // #9 = $tfe
8678 : /*24784*/ OPC_MoveParent,
8679 : /*24785*/ OPC_MoveChild, 11,
8680 : /*24787*/ OPC_RecordNode, // #10 = $lwe
8681 : /*24788*/ OPC_MoveParent,
8682 : /*24789*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8683 : /*24791*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8684 : /*24794*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8685 : /*24797*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8686 : /*24800*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8687 : /*24803*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8688 : /*24806*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8689 : /*24809*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8690 : /*24812*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8691 : /*24815*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CL_V4_V1), 0,
8692 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8693 : // Src: (intrinsic_wo_chain:v4f32 4862:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8694 : // Dst: (IMAGE_SAMPLE_CL_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8695 : /*24833*/ /*Scope*/ 68, /*->24902*/
8696 : /*24834*/ OPC_CheckChild1Type, MVT::v2i32,
8697 : /*24836*/ OPC_RecordChild2, // #1 = $rsrc
8698 : /*24837*/ OPC_RecordChild3, // #2 = $sampler
8699 : /*24838*/ OPC_RecordChild4, // #3 = $dmask
8700 : /*24839*/ OPC_RecordChild5, // #4 = $unorm
8701 : /*24840*/ OPC_RecordChild6, // #5 = $r128
8702 : /*24841*/ OPC_RecordChild7, // #6 = $da
8703 : /*24842*/ OPC_MoveChild, 8,
8704 : /*24844*/ OPC_RecordNode, // #7 = $glc
8705 : /*24845*/ OPC_MoveParent,
8706 : /*24846*/ OPC_MoveChild, 9,
8707 : /*24848*/ OPC_RecordNode, // #8 = $slc
8708 : /*24849*/ OPC_MoveParent,
8709 : /*24850*/ OPC_MoveChild, 10,
8710 : /*24852*/ OPC_RecordNode, // #9 = $tfe
8711 : /*24853*/ OPC_MoveParent,
8712 : /*24854*/ OPC_MoveChild, 11,
8713 : /*24856*/ OPC_RecordNode, // #10 = $lwe
8714 : /*24857*/ OPC_MoveParent,
8715 : /*24858*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8716 : /*24860*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8717 : /*24863*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8718 : /*24866*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8719 : /*24869*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8720 : /*24872*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8721 : /*24875*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8722 : /*24878*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8723 : /*24881*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8724 : /*24884*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CL_V4_V2), 0,
8725 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8726 : // Src: (intrinsic_wo_chain:v4f32 4862:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8727 : // Dst: (IMAGE_SAMPLE_CL_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8728 : /*24902*/ /*Scope*/ 68, /*->24971*/
8729 : /*24903*/ OPC_CheckChild1Type, MVT::v4i32,
8730 : /*24905*/ OPC_RecordChild2, // #1 = $rsrc
8731 : /*24906*/ OPC_RecordChild3, // #2 = $sampler
8732 : /*24907*/ OPC_RecordChild4, // #3 = $dmask
8733 : /*24908*/ OPC_RecordChild5, // #4 = $unorm
8734 : /*24909*/ OPC_RecordChild6, // #5 = $r128
8735 : /*24910*/ OPC_RecordChild7, // #6 = $da
8736 : /*24911*/ OPC_MoveChild, 8,
8737 : /*24913*/ OPC_RecordNode, // #7 = $glc
8738 : /*24914*/ OPC_MoveParent,
8739 : /*24915*/ OPC_MoveChild, 9,
8740 : /*24917*/ OPC_RecordNode, // #8 = $slc
8741 : /*24918*/ OPC_MoveParent,
8742 : /*24919*/ OPC_MoveChild, 10,
8743 : /*24921*/ OPC_RecordNode, // #9 = $tfe
8744 : /*24922*/ OPC_MoveParent,
8745 : /*24923*/ OPC_MoveChild, 11,
8746 : /*24925*/ OPC_RecordNode, // #10 = $lwe
8747 : /*24926*/ OPC_MoveParent,
8748 : /*24927*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8749 : /*24929*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8750 : /*24932*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8751 : /*24935*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8752 : /*24938*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8753 : /*24941*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8754 : /*24944*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8755 : /*24947*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8756 : /*24950*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8757 : /*24953*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CL_V4_V4), 0,
8758 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8759 : // Src: (intrinsic_wo_chain:v4f32 4862:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8760 : // Dst: (IMAGE_SAMPLE_CL_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8761 : /*24971*/ /*Scope*/ 68, /*->25040*/
8762 : /*24972*/ OPC_CheckChild1Type, MVT::v8i32,
8763 : /*24974*/ OPC_RecordChild2, // #1 = $rsrc
8764 : /*24975*/ OPC_RecordChild3, // #2 = $sampler
8765 : /*24976*/ OPC_RecordChild4, // #3 = $dmask
8766 : /*24977*/ OPC_RecordChild5, // #4 = $unorm
8767 : /*24978*/ OPC_RecordChild6, // #5 = $r128
8768 : /*24979*/ OPC_RecordChild7, // #6 = $da
8769 : /*24980*/ OPC_MoveChild, 8,
8770 : /*24982*/ OPC_RecordNode, // #7 = $glc
8771 : /*24983*/ OPC_MoveParent,
8772 : /*24984*/ OPC_MoveChild, 9,
8773 : /*24986*/ OPC_RecordNode, // #8 = $slc
8774 : /*24987*/ OPC_MoveParent,
8775 : /*24988*/ OPC_MoveChild, 10,
8776 : /*24990*/ OPC_RecordNode, // #9 = $tfe
8777 : /*24991*/ OPC_MoveParent,
8778 : /*24992*/ OPC_MoveChild, 11,
8779 : /*24994*/ OPC_RecordNode, // #10 = $lwe
8780 : /*24995*/ OPC_MoveParent,
8781 : /*24996*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8782 : /*24998*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8783 : /*25001*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8784 : /*25004*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8785 : /*25007*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8786 : /*25010*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8787 : /*25013*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8788 : /*25016*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8789 : /*25019*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8790 : /*25022*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CL_V4_V8), 0,
8791 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8792 : // Src: (intrinsic_wo_chain:v4f32 4862:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8793 : // Dst: (IMAGE_SAMPLE_CL_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8794 : /*25040*/ /*Scope*/ 68, /*->25109*/
8795 : /*25041*/ OPC_CheckChild1Type, MVT::v16i32,
8796 : /*25043*/ OPC_RecordChild2, // #1 = $rsrc
8797 : /*25044*/ OPC_RecordChild3, // #2 = $sampler
8798 : /*25045*/ OPC_RecordChild4, // #3 = $dmask
8799 : /*25046*/ OPC_RecordChild5, // #4 = $unorm
8800 : /*25047*/ OPC_RecordChild6, // #5 = $r128
8801 : /*25048*/ OPC_RecordChild7, // #6 = $da
8802 : /*25049*/ OPC_MoveChild, 8,
8803 : /*25051*/ OPC_RecordNode, // #7 = $glc
8804 : /*25052*/ OPC_MoveParent,
8805 : /*25053*/ OPC_MoveChild, 9,
8806 : /*25055*/ OPC_RecordNode, // #8 = $slc
8807 : /*25056*/ OPC_MoveParent,
8808 : /*25057*/ OPC_MoveChild, 10,
8809 : /*25059*/ OPC_RecordNode, // #9 = $tfe
8810 : /*25060*/ OPC_MoveParent,
8811 : /*25061*/ OPC_MoveChild, 11,
8812 : /*25063*/ OPC_RecordNode, // #10 = $lwe
8813 : /*25064*/ OPC_MoveParent,
8814 : /*25065*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8815 : /*25067*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8816 : /*25070*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8817 : /*25073*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8818 : /*25076*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8819 : /*25079*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8820 : /*25082*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8821 : /*25085*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8822 : /*25088*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8823 : /*25091*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CL_V4_V16), 0,
8824 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8825 : // Src: (intrinsic_wo_chain:v4f32 4862:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8826 : // Dst: (IMAGE_SAMPLE_CL_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8827 : /*25109*/ 0, /*End of Scope*/
8828 : /*25110*/ /*Scope*/ 95|128,2/*351*/, /*->25463*/
8829 : /*25112*/ OPC_CheckChild0Integer, 0|128,38/*4864*/,
8830 : /*25115*/ OPC_RecordChild1, // #0 = $addr
8831 : /*25116*/ OPC_Scope, 68, /*->25186*/ // 5 children in Scope
8832 : /*25118*/ OPC_CheckChild1Type, MVT::i32,
8833 : /*25120*/ OPC_RecordChild2, // #1 = $rsrc
8834 : /*25121*/ OPC_RecordChild3, // #2 = $sampler
8835 : /*25122*/ OPC_RecordChild4, // #3 = $dmask
8836 : /*25123*/ OPC_RecordChild5, // #4 = $unorm
8837 : /*25124*/ OPC_RecordChild6, // #5 = $r128
8838 : /*25125*/ OPC_RecordChild7, // #6 = $da
8839 : /*25126*/ OPC_MoveChild, 8,
8840 : /*25128*/ OPC_RecordNode, // #7 = $glc
8841 : /*25129*/ OPC_MoveParent,
8842 : /*25130*/ OPC_MoveChild, 9,
8843 : /*25132*/ OPC_RecordNode, // #8 = $slc
8844 : /*25133*/ OPC_MoveParent,
8845 : /*25134*/ OPC_MoveChild, 10,
8846 : /*25136*/ OPC_RecordNode, // #9 = $tfe
8847 : /*25137*/ OPC_MoveParent,
8848 : /*25138*/ OPC_MoveChild, 11,
8849 : /*25140*/ OPC_RecordNode, // #10 = $lwe
8850 : /*25141*/ OPC_MoveParent,
8851 : /*25142*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8852 : /*25144*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8853 : /*25147*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8854 : /*25150*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8855 : /*25153*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8856 : /*25156*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8857 : /*25159*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8858 : /*25162*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8859 : /*25165*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8860 : /*25168*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V1), 0,
8861 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8862 : // Src: (intrinsic_wo_chain:v4f32 4864:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8863 : // Dst: (IMAGE_SAMPLE_D_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8864 : /*25186*/ /*Scope*/ 68, /*->25255*/
8865 : /*25187*/ OPC_CheckChild1Type, MVT::v2i32,
8866 : /*25189*/ OPC_RecordChild2, // #1 = $rsrc
8867 : /*25190*/ OPC_RecordChild3, // #2 = $sampler
8868 : /*25191*/ OPC_RecordChild4, // #3 = $dmask
8869 : /*25192*/ OPC_RecordChild5, // #4 = $unorm
8870 : /*25193*/ OPC_RecordChild6, // #5 = $r128
8871 : /*25194*/ OPC_RecordChild7, // #6 = $da
8872 : /*25195*/ OPC_MoveChild, 8,
8873 : /*25197*/ OPC_RecordNode, // #7 = $glc
8874 : /*25198*/ OPC_MoveParent,
8875 : /*25199*/ OPC_MoveChild, 9,
8876 : /*25201*/ OPC_RecordNode, // #8 = $slc
8877 : /*25202*/ OPC_MoveParent,
8878 : /*25203*/ OPC_MoveChild, 10,
8879 : /*25205*/ OPC_RecordNode, // #9 = $tfe
8880 : /*25206*/ OPC_MoveParent,
8881 : /*25207*/ OPC_MoveChild, 11,
8882 : /*25209*/ OPC_RecordNode, // #10 = $lwe
8883 : /*25210*/ OPC_MoveParent,
8884 : /*25211*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8885 : /*25213*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8886 : /*25216*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8887 : /*25219*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8888 : /*25222*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8889 : /*25225*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8890 : /*25228*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8891 : /*25231*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8892 : /*25234*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8893 : /*25237*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V2), 0,
8894 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8895 : // Src: (intrinsic_wo_chain:v4f32 4864:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8896 : // Dst: (IMAGE_SAMPLE_D_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8897 : /*25255*/ /*Scope*/ 68, /*->25324*/
8898 : /*25256*/ OPC_CheckChild1Type, MVT::v4i32,
8899 : /*25258*/ OPC_RecordChild2, // #1 = $rsrc
8900 : /*25259*/ OPC_RecordChild3, // #2 = $sampler
8901 : /*25260*/ OPC_RecordChild4, // #3 = $dmask
8902 : /*25261*/ OPC_RecordChild5, // #4 = $unorm
8903 : /*25262*/ OPC_RecordChild6, // #5 = $r128
8904 : /*25263*/ OPC_RecordChild7, // #6 = $da
8905 : /*25264*/ OPC_MoveChild, 8,
8906 : /*25266*/ OPC_RecordNode, // #7 = $glc
8907 : /*25267*/ OPC_MoveParent,
8908 : /*25268*/ OPC_MoveChild, 9,
8909 : /*25270*/ OPC_RecordNode, // #8 = $slc
8910 : /*25271*/ OPC_MoveParent,
8911 : /*25272*/ OPC_MoveChild, 10,
8912 : /*25274*/ OPC_RecordNode, // #9 = $tfe
8913 : /*25275*/ OPC_MoveParent,
8914 : /*25276*/ OPC_MoveChild, 11,
8915 : /*25278*/ OPC_RecordNode, // #10 = $lwe
8916 : /*25279*/ OPC_MoveParent,
8917 : /*25280*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8918 : /*25282*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8919 : /*25285*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8920 : /*25288*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8921 : /*25291*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8922 : /*25294*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8923 : /*25297*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8924 : /*25300*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8925 : /*25303*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8926 : /*25306*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V4), 0,
8927 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8928 : // Src: (intrinsic_wo_chain:v4f32 4864:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8929 : // Dst: (IMAGE_SAMPLE_D_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8930 : /*25324*/ /*Scope*/ 68, /*->25393*/
8931 : /*25325*/ OPC_CheckChild1Type, MVT::v8i32,
8932 : /*25327*/ OPC_RecordChild2, // #1 = $rsrc
8933 : /*25328*/ OPC_RecordChild3, // #2 = $sampler
8934 : /*25329*/ OPC_RecordChild4, // #3 = $dmask
8935 : /*25330*/ OPC_RecordChild5, // #4 = $unorm
8936 : /*25331*/ OPC_RecordChild6, // #5 = $r128
8937 : /*25332*/ OPC_RecordChild7, // #6 = $da
8938 : /*25333*/ OPC_MoveChild, 8,
8939 : /*25335*/ OPC_RecordNode, // #7 = $glc
8940 : /*25336*/ OPC_MoveParent,
8941 : /*25337*/ OPC_MoveChild, 9,
8942 : /*25339*/ OPC_RecordNode, // #8 = $slc
8943 : /*25340*/ OPC_MoveParent,
8944 : /*25341*/ OPC_MoveChild, 10,
8945 : /*25343*/ OPC_RecordNode, // #9 = $tfe
8946 : /*25344*/ OPC_MoveParent,
8947 : /*25345*/ OPC_MoveChild, 11,
8948 : /*25347*/ OPC_RecordNode, // #10 = $lwe
8949 : /*25348*/ OPC_MoveParent,
8950 : /*25349*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8951 : /*25351*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8952 : /*25354*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8953 : /*25357*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8954 : /*25360*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8955 : /*25363*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8956 : /*25366*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8957 : /*25369*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8958 : /*25372*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8959 : /*25375*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V8), 0,
8960 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8961 : // Src: (intrinsic_wo_chain:v4f32 4864:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8962 : // Dst: (IMAGE_SAMPLE_D_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8963 : /*25393*/ /*Scope*/ 68, /*->25462*/
8964 : /*25394*/ OPC_CheckChild1Type, MVT::v16i32,
8965 : /*25396*/ OPC_RecordChild2, // #1 = $rsrc
8966 : /*25397*/ OPC_RecordChild3, // #2 = $sampler
8967 : /*25398*/ OPC_RecordChild4, // #3 = $dmask
8968 : /*25399*/ OPC_RecordChild5, // #4 = $unorm
8969 : /*25400*/ OPC_RecordChild6, // #5 = $r128
8970 : /*25401*/ OPC_RecordChild7, // #6 = $da
8971 : /*25402*/ OPC_MoveChild, 8,
8972 : /*25404*/ OPC_RecordNode, // #7 = $glc
8973 : /*25405*/ OPC_MoveParent,
8974 : /*25406*/ OPC_MoveChild, 9,
8975 : /*25408*/ OPC_RecordNode, // #8 = $slc
8976 : /*25409*/ OPC_MoveParent,
8977 : /*25410*/ OPC_MoveChild, 10,
8978 : /*25412*/ OPC_RecordNode, // #9 = $tfe
8979 : /*25413*/ OPC_MoveParent,
8980 : /*25414*/ OPC_MoveChild, 11,
8981 : /*25416*/ OPC_RecordNode, // #10 = $lwe
8982 : /*25417*/ OPC_MoveParent,
8983 : /*25418*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
8984 : /*25420*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
8985 : /*25423*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
8986 : /*25426*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
8987 : /*25429*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
8988 : /*25432*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
8989 : /*25435*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
8990 : /*25438*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
8991 : /*25441*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
8992 : /*25444*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V16), 0,
8993 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
8994 : // Src: (intrinsic_wo_chain:v4f32 4864:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
8995 : // Dst: (IMAGE_SAMPLE_D_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
8996 : /*25462*/ 0, /*End of Scope*/
8997 : /*25463*/ /*Scope*/ 95|128,2/*351*/, /*->25816*/
8998 : /*25465*/ OPC_CheckChild0Integer, 1|128,38/*4865*/,
8999 : /*25468*/ OPC_RecordChild1, // #0 = $addr
9000 : /*25469*/ OPC_Scope, 68, /*->25539*/ // 5 children in Scope
9001 : /*25471*/ OPC_CheckChild1Type, MVT::i32,
9002 : /*25473*/ OPC_RecordChild2, // #1 = $rsrc
9003 : /*25474*/ OPC_RecordChild3, // #2 = $sampler
9004 : /*25475*/ OPC_RecordChild4, // #3 = $dmask
9005 : /*25476*/ OPC_RecordChild5, // #4 = $unorm
9006 : /*25477*/ OPC_RecordChild6, // #5 = $r128
9007 : /*25478*/ OPC_RecordChild7, // #6 = $da
9008 : /*25479*/ OPC_MoveChild, 8,
9009 : /*25481*/ OPC_RecordNode, // #7 = $glc
9010 : /*25482*/ OPC_MoveParent,
9011 : /*25483*/ OPC_MoveChild, 9,
9012 : /*25485*/ OPC_RecordNode, // #8 = $slc
9013 : /*25486*/ OPC_MoveParent,
9014 : /*25487*/ OPC_MoveChild, 10,
9015 : /*25489*/ OPC_RecordNode, // #9 = $tfe
9016 : /*25490*/ OPC_MoveParent,
9017 : /*25491*/ OPC_MoveChild, 11,
9018 : /*25493*/ OPC_RecordNode, // #10 = $lwe
9019 : /*25494*/ OPC_MoveParent,
9020 : /*25495*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9021 : /*25497*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9022 : /*25500*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9023 : /*25503*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9024 : /*25506*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9025 : /*25509*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9026 : /*25512*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9027 : /*25515*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9028 : /*25518*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9029 : /*25521*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_CL_V4_V1), 0,
9030 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9031 : // Src: (intrinsic_wo_chain:v4f32 4865:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9032 : // Dst: (IMAGE_SAMPLE_D_CL_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9033 : /*25539*/ /*Scope*/ 68, /*->25608*/
9034 : /*25540*/ OPC_CheckChild1Type, MVT::v2i32,
9035 : /*25542*/ OPC_RecordChild2, // #1 = $rsrc
9036 : /*25543*/ OPC_RecordChild3, // #2 = $sampler
9037 : /*25544*/ OPC_RecordChild4, // #3 = $dmask
9038 : /*25545*/ OPC_RecordChild5, // #4 = $unorm
9039 : /*25546*/ OPC_RecordChild6, // #5 = $r128
9040 : /*25547*/ OPC_RecordChild7, // #6 = $da
9041 : /*25548*/ OPC_MoveChild, 8,
9042 : /*25550*/ OPC_RecordNode, // #7 = $glc
9043 : /*25551*/ OPC_MoveParent,
9044 : /*25552*/ OPC_MoveChild, 9,
9045 : /*25554*/ OPC_RecordNode, // #8 = $slc
9046 : /*25555*/ OPC_MoveParent,
9047 : /*25556*/ OPC_MoveChild, 10,
9048 : /*25558*/ OPC_RecordNode, // #9 = $tfe
9049 : /*25559*/ OPC_MoveParent,
9050 : /*25560*/ OPC_MoveChild, 11,
9051 : /*25562*/ OPC_RecordNode, // #10 = $lwe
9052 : /*25563*/ OPC_MoveParent,
9053 : /*25564*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9054 : /*25566*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9055 : /*25569*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9056 : /*25572*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9057 : /*25575*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9058 : /*25578*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9059 : /*25581*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9060 : /*25584*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9061 : /*25587*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9062 : /*25590*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2), 0,
9063 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9064 : // Src: (intrinsic_wo_chain:v4f32 4865:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9065 : // Dst: (IMAGE_SAMPLE_D_CL_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9066 : /*25608*/ /*Scope*/ 68, /*->25677*/
9067 : /*25609*/ OPC_CheckChild1Type, MVT::v4i32,
9068 : /*25611*/ OPC_RecordChild2, // #1 = $rsrc
9069 : /*25612*/ OPC_RecordChild3, // #2 = $sampler
9070 : /*25613*/ OPC_RecordChild4, // #3 = $dmask
9071 : /*25614*/ OPC_RecordChild5, // #4 = $unorm
9072 : /*25615*/ OPC_RecordChild6, // #5 = $r128
9073 : /*25616*/ OPC_RecordChild7, // #6 = $da
9074 : /*25617*/ OPC_MoveChild, 8,
9075 : /*25619*/ OPC_RecordNode, // #7 = $glc
9076 : /*25620*/ OPC_MoveParent,
9077 : /*25621*/ OPC_MoveChild, 9,
9078 : /*25623*/ OPC_RecordNode, // #8 = $slc
9079 : /*25624*/ OPC_MoveParent,
9080 : /*25625*/ OPC_MoveChild, 10,
9081 : /*25627*/ OPC_RecordNode, // #9 = $tfe
9082 : /*25628*/ OPC_MoveParent,
9083 : /*25629*/ OPC_MoveChild, 11,
9084 : /*25631*/ OPC_RecordNode, // #10 = $lwe
9085 : /*25632*/ OPC_MoveParent,
9086 : /*25633*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9087 : /*25635*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9088 : /*25638*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9089 : /*25641*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9090 : /*25644*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9091 : /*25647*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9092 : /*25650*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9093 : /*25653*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9094 : /*25656*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9095 : /*25659*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4), 0,
9096 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9097 : // Src: (intrinsic_wo_chain:v4f32 4865:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9098 : // Dst: (IMAGE_SAMPLE_D_CL_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9099 : /*25677*/ /*Scope*/ 68, /*->25746*/
9100 : /*25678*/ OPC_CheckChild1Type, MVT::v8i32,
9101 : /*25680*/ OPC_RecordChild2, // #1 = $rsrc
9102 : /*25681*/ OPC_RecordChild3, // #2 = $sampler
9103 : /*25682*/ OPC_RecordChild4, // #3 = $dmask
9104 : /*25683*/ OPC_RecordChild5, // #4 = $unorm
9105 : /*25684*/ OPC_RecordChild6, // #5 = $r128
9106 : /*25685*/ OPC_RecordChild7, // #6 = $da
9107 : /*25686*/ OPC_MoveChild, 8,
9108 : /*25688*/ OPC_RecordNode, // #7 = $glc
9109 : /*25689*/ OPC_MoveParent,
9110 : /*25690*/ OPC_MoveChild, 9,
9111 : /*25692*/ OPC_RecordNode, // #8 = $slc
9112 : /*25693*/ OPC_MoveParent,
9113 : /*25694*/ OPC_MoveChild, 10,
9114 : /*25696*/ OPC_RecordNode, // #9 = $tfe
9115 : /*25697*/ OPC_MoveParent,
9116 : /*25698*/ OPC_MoveChild, 11,
9117 : /*25700*/ OPC_RecordNode, // #10 = $lwe
9118 : /*25701*/ OPC_MoveParent,
9119 : /*25702*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9120 : /*25704*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9121 : /*25707*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9122 : /*25710*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9123 : /*25713*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9124 : /*25716*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9125 : /*25719*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9126 : /*25722*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9127 : /*25725*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9128 : /*25728*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8), 0,
9129 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9130 : // Src: (intrinsic_wo_chain:v4f32 4865:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9131 : // Dst: (IMAGE_SAMPLE_D_CL_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9132 : /*25746*/ /*Scope*/ 68, /*->25815*/
9133 : /*25747*/ OPC_CheckChild1Type, MVT::v16i32,
9134 : /*25749*/ OPC_RecordChild2, // #1 = $rsrc
9135 : /*25750*/ OPC_RecordChild3, // #2 = $sampler
9136 : /*25751*/ OPC_RecordChild4, // #3 = $dmask
9137 : /*25752*/ OPC_RecordChild5, // #4 = $unorm
9138 : /*25753*/ OPC_RecordChild6, // #5 = $r128
9139 : /*25754*/ OPC_RecordChild7, // #6 = $da
9140 : /*25755*/ OPC_MoveChild, 8,
9141 : /*25757*/ OPC_RecordNode, // #7 = $glc
9142 : /*25758*/ OPC_MoveParent,
9143 : /*25759*/ OPC_MoveChild, 9,
9144 : /*25761*/ OPC_RecordNode, // #8 = $slc
9145 : /*25762*/ OPC_MoveParent,
9146 : /*25763*/ OPC_MoveChild, 10,
9147 : /*25765*/ OPC_RecordNode, // #9 = $tfe
9148 : /*25766*/ OPC_MoveParent,
9149 : /*25767*/ OPC_MoveChild, 11,
9150 : /*25769*/ OPC_RecordNode, // #10 = $lwe
9151 : /*25770*/ OPC_MoveParent,
9152 : /*25771*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9153 : /*25773*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9154 : /*25776*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9155 : /*25779*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9156 : /*25782*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9157 : /*25785*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9158 : /*25788*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9159 : /*25791*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9160 : /*25794*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9161 : /*25797*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_CL_V4_V16), 0,
9162 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9163 : // Src: (intrinsic_wo_chain:v4f32 4865:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9164 : // Dst: (IMAGE_SAMPLE_D_CL_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9165 : /*25815*/ 0, /*End of Scope*/
9166 : /*25816*/ /*Scope*/ 95|128,2/*351*/, /*->26169*/
9167 : /*25818*/ OPC_CheckChild0Integer, 4|128,38/*4868*/,
9168 : /*25821*/ OPC_RecordChild1, // #0 = $addr
9169 : /*25822*/ OPC_Scope, 68, /*->25892*/ // 5 children in Scope
9170 : /*25824*/ OPC_CheckChild1Type, MVT::i32,
9171 : /*25826*/ OPC_RecordChild2, // #1 = $rsrc
9172 : /*25827*/ OPC_RecordChild3, // #2 = $sampler
9173 : /*25828*/ OPC_RecordChild4, // #3 = $dmask
9174 : /*25829*/ OPC_RecordChild5, // #4 = $unorm
9175 : /*25830*/ OPC_RecordChild6, // #5 = $r128
9176 : /*25831*/ OPC_RecordChild7, // #6 = $da
9177 : /*25832*/ OPC_MoveChild, 8,
9178 : /*25834*/ OPC_RecordNode, // #7 = $glc
9179 : /*25835*/ OPC_MoveParent,
9180 : /*25836*/ OPC_MoveChild, 9,
9181 : /*25838*/ OPC_RecordNode, // #8 = $slc
9182 : /*25839*/ OPC_MoveParent,
9183 : /*25840*/ OPC_MoveChild, 10,
9184 : /*25842*/ OPC_RecordNode, // #9 = $tfe
9185 : /*25843*/ OPC_MoveParent,
9186 : /*25844*/ OPC_MoveChild, 11,
9187 : /*25846*/ OPC_RecordNode, // #10 = $lwe
9188 : /*25847*/ OPC_MoveParent,
9189 : /*25848*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9190 : /*25850*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9191 : /*25853*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9192 : /*25856*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9193 : /*25859*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9194 : /*25862*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9195 : /*25865*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9196 : /*25868*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9197 : /*25871*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9198 : /*25874*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V1), 0,
9199 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9200 : // Src: (intrinsic_wo_chain:v4f32 4868:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9201 : // Dst: (IMAGE_SAMPLE_L_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9202 : /*25892*/ /*Scope*/ 68, /*->25961*/
9203 : /*25893*/ OPC_CheckChild1Type, MVT::v2i32,
9204 : /*25895*/ OPC_RecordChild2, // #1 = $rsrc
9205 : /*25896*/ OPC_RecordChild3, // #2 = $sampler
9206 : /*25897*/ OPC_RecordChild4, // #3 = $dmask
9207 : /*25898*/ OPC_RecordChild5, // #4 = $unorm
9208 : /*25899*/ OPC_RecordChild6, // #5 = $r128
9209 : /*25900*/ OPC_RecordChild7, // #6 = $da
9210 : /*25901*/ OPC_MoveChild, 8,
9211 : /*25903*/ OPC_RecordNode, // #7 = $glc
9212 : /*25904*/ OPC_MoveParent,
9213 : /*25905*/ OPC_MoveChild, 9,
9214 : /*25907*/ OPC_RecordNode, // #8 = $slc
9215 : /*25908*/ OPC_MoveParent,
9216 : /*25909*/ OPC_MoveChild, 10,
9217 : /*25911*/ OPC_RecordNode, // #9 = $tfe
9218 : /*25912*/ OPC_MoveParent,
9219 : /*25913*/ OPC_MoveChild, 11,
9220 : /*25915*/ OPC_RecordNode, // #10 = $lwe
9221 : /*25916*/ OPC_MoveParent,
9222 : /*25917*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9223 : /*25919*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9224 : /*25922*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9225 : /*25925*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9226 : /*25928*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9227 : /*25931*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9228 : /*25934*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9229 : /*25937*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9230 : /*25940*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9231 : /*25943*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V2), 0,
9232 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9233 : // Src: (intrinsic_wo_chain:v4f32 4868:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9234 : // Dst: (IMAGE_SAMPLE_L_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9235 : /*25961*/ /*Scope*/ 68, /*->26030*/
9236 : /*25962*/ OPC_CheckChild1Type, MVT::v4i32,
9237 : /*25964*/ OPC_RecordChild2, // #1 = $rsrc
9238 : /*25965*/ OPC_RecordChild3, // #2 = $sampler
9239 : /*25966*/ OPC_RecordChild4, // #3 = $dmask
9240 : /*25967*/ OPC_RecordChild5, // #4 = $unorm
9241 : /*25968*/ OPC_RecordChild6, // #5 = $r128
9242 : /*25969*/ OPC_RecordChild7, // #6 = $da
9243 : /*25970*/ OPC_MoveChild, 8,
9244 : /*25972*/ OPC_RecordNode, // #7 = $glc
9245 : /*25973*/ OPC_MoveParent,
9246 : /*25974*/ OPC_MoveChild, 9,
9247 : /*25976*/ OPC_RecordNode, // #8 = $slc
9248 : /*25977*/ OPC_MoveParent,
9249 : /*25978*/ OPC_MoveChild, 10,
9250 : /*25980*/ OPC_RecordNode, // #9 = $tfe
9251 : /*25981*/ OPC_MoveParent,
9252 : /*25982*/ OPC_MoveChild, 11,
9253 : /*25984*/ OPC_RecordNode, // #10 = $lwe
9254 : /*25985*/ OPC_MoveParent,
9255 : /*25986*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9256 : /*25988*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9257 : /*25991*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9258 : /*25994*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9259 : /*25997*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9260 : /*26000*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9261 : /*26003*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9262 : /*26006*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9263 : /*26009*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9264 : /*26012*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V4), 0,
9265 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9266 : // Src: (intrinsic_wo_chain:v4f32 4868:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9267 : // Dst: (IMAGE_SAMPLE_L_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9268 : /*26030*/ /*Scope*/ 68, /*->26099*/
9269 : /*26031*/ OPC_CheckChild1Type, MVT::v8i32,
9270 : /*26033*/ OPC_RecordChild2, // #1 = $rsrc
9271 : /*26034*/ OPC_RecordChild3, // #2 = $sampler
9272 : /*26035*/ OPC_RecordChild4, // #3 = $dmask
9273 : /*26036*/ OPC_RecordChild5, // #4 = $unorm
9274 : /*26037*/ OPC_RecordChild6, // #5 = $r128
9275 : /*26038*/ OPC_RecordChild7, // #6 = $da
9276 : /*26039*/ OPC_MoveChild, 8,
9277 : /*26041*/ OPC_RecordNode, // #7 = $glc
9278 : /*26042*/ OPC_MoveParent,
9279 : /*26043*/ OPC_MoveChild, 9,
9280 : /*26045*/ OPC_RecordNode, // #8 = $slc
9281 : /*26046*/ OPC_MoveParent,
9282 : /*26047*/ OPC_MoveChild, 10,
9283 : /*26049*/ OPC_RecordNode, // #9 = $tfe
9284 : /*26050*/ OPC_MoveParent,
9285 : /*26051*/ OPC_MoveChild, 11,
9286 : /*26053*/ OPC_RecordNode, // #10 = $lwe
9287 : /*26054*/ OPC_MoveParent,
9288 : /*26055*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9289 : /*26057*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9290 : /*26060*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9291 : /*26063*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9292 : /*26066*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9293 : /*26069*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9294 : /*26072*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9295 : /*26075*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9296 : /*26078*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9297 : /*26081*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V8), 0,
9298 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9299 : // Src: (intrinsic_wo_chain:v4f32 4868:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9300 : // Dst: (IMAGE_SAMPLE_L_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9301 : /*26099*/ /*Scope*/ 68, /*->26168*/
9302 : /*26100*/ OPC_CheckChild1Type, MVT::v16i32,
9303 : /*26102*/ OPC_RecordChild2, // #1 = $rsrc
9304 : /*26103*/ OPC_RecordChild3, // #2 = $sampler
9305 : /*26104*/ OPC_RecordChild4, // #3 = $dmask
9306 : /*26105*/ OPC_RecordChild5, // #4 = $unorm
9307 : /*26106*/ OPC_RecordChild6, // #5 = $r128
9308 : /*26107*/ OPC_RecordChild7, // #6 = $da
9309 : /*26108*/ OPC_MoveChild, 8,
9310 : /*26110*/ OPC_RecordNode, // #7 = $glc
9311 : /*26111*/ OPC_MoveParent,
9312 : /*26112*/ OPC_MoveChild, 9,
9313 : /*26114*/ OPC_RecordNode, // #8 = $slc
9314 : /*26115*/ OPC_MoveParent,
9315 : /*26116*/ OPC_MoveChild, 10,
9316 : /*26118*/ OPC_RecordNode, // #9 = $tfe
9317 : /*26119*/ OPC_MoveParent,
9318 : /*26120*/ OPC_MoveChild, 11,
9319 : /*26122*/ OPC_RecordNode, // #10 = $lwe
9320 : /*26123*/ OPC_MoveParent,
9321 : /*26124*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9322 : /*26126*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9323 : /*26129*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9324 : /*26132*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9325 : /*26135*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9326 : /*26138*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9327 : /*26141*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9328 : /*26144*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9329 : /*26147*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9330 : /*26150*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V16), 0,
9331 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9332 : // Src: (intrinsic_wo_chain:v4f32 4868:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9333 : // Dst: (IMAGE_SAMPLE_L_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9334 : /*26168*/ 0, /*End of Scope*/
9335 : /*26169*/ /*Scope*/ 95|128,2/*351*/, /*->26522*/
9336 : /*26171*/ OPC_CheckChild0Integer, 98|128,37/*4834*/,
9337 : /*26174*/ OPC_RecordChild1, // #0 = $addr
9338 : /*26175*/ OPC_Scope, 68, /*->26245*/ // 5 children in Scope
9339 : /*26177*/ OPC_CheckChild1Type, MVT::i32,
9340 : /*26179*/ OPC_RecordChild2, // #1 = $rsrc
9341 : /*26180*/ OPC_RecordChild3, // #2 = $sampler
9342 : /*26181*/ OPC_RecordChild4, // #3 = $dmask
9343 : /*26182*/ OPC_RecordChild5, // #4 = $unorm
9344 : /*26183*/ OPC_RecordChild6, // #5 = $r128
9345 : /*26184*/ OPC_RecordChild7, // #6 = $da
9346 : /*26185*/ OPC_MoveChild, 8,
9347 : /*26187*/ OPC_RecordNode, // #7 = $glc
9348 : /*26188*/ OPC_MoveParent,
9349 : /*26189*/ OPC_MoveChild, 9,
9350 : /*26191*/ OPC_RecordNode, // #8 = $slc
9351 : /*26192*/ OPC_MoveParent,
9352 : /*26193*/ OPC_MoveChild, 10,
9353 : /*26195*/ OPC_RecordNode, // #9 = $tfe
9354 : /*26196*/ OPC_MoveParent,
9355 : /*26197*/ OPC_MoveChild, 11,
9356 : /*26199*/ OPC_RecordNode, // #10 = $lwe
9357 : /*26200*/ OPC_MoveParent,
9358 : /*26201*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9359 : /*26203*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9360 : /*26206*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9361 : /*26209*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9362 : /*26212*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9363 : /*26215*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9364 : /*26218*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9365 : /*26221*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9366 : /*26224*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9367 : /*26227*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V1), 0,
9368 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9369 : // Src: (intrinsic_wo_chain:v4f32 4834:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9370 : // Dst: (IMAGE_SAMPLE_B_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9371 : /*26245*/ /*Scope*/ 68, /*->26314*/
9372 : /*26246*/ OPC_CheckChild1Type, MVT::v2i32,
9373 : /*26248*/ OPC_RecordChild2, // #1 = $rsrc
9374 : /*26249*/ OPC_RecordChild3, // #2 = $sampler
9375 : /*26250*/ OPC_RecordChild4, // #3 = $dmask
9376 : /*26251*/ OPC_RecordChild5, // #4 = $unorm
9377 : /*26252*/ OPC_RecordChild6, // #5 = $r128
9378 : /*26253*/ OPC_RecordChild7, // #6 = $da
9379 : /*26254*/ OPC_MoveChild, 8,
9380 : /*26256*/ OPC_RecordNode, // #7 = $glc
9381 : /*26257*/ OPC_MoveParent,
9382 : /*26258*/ OPC_MoveChild, 9,
9383 : /*26260*/ OPC_RecordNode, // #8 = $slc
9384 : /*26261*/ OPC_MoveParent,
9385 : /*26262*/ OPC_MoveChild, 10,
9386 : /*26264*/ OPC_RecordNode, // #9 = $tfe
9387 : /*26265*/ OPC_MoveParent,
9388 : /*26266*/ OPC_MoveChild, 11,
9389 : /*26268*/ OPC_RecordNode, // #10 = $lwe
9390 : /*26269*/ OPC_MoveParent,
9391 : /*26270*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9392 : /*26272*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9393 : /*26275*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9394 : /*26278*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9395 : /*26281*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9396 : /*26284*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9397 : /*26287*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9398 : /*26290*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9399 : /*26293*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9400 : /*26296*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V2), 0,
9401 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9402 : // Src: (intrinsic_wo_chain:v4f32 4834:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9403 : // Dst: (IMAGE_SAMPLE_B_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9404 : /*26314*/ /*Scope*/ 68, /*->26383*/
9405 : /*26315*/ OPC_CheckChild1Type, MVT::v4i32,
9406 : /*26317*/ OPC_RecordChild2, // #1 = $rsrc
9407 : /*26318*/ OPC_RecordChild3, // #2 = $sampler
9408 : /*26319*/ OPC_RecordChild4, // #3 = $dmask
9409 : /*26320*/ OPC_RecordChild5, // #4 = $unorm
9410 : /*26321*/ OPC_RecordChild6, // #5 = $r128
9411 : /*26322*/ OPC_RecordChild7, // #6 = $da
9412 : /*26323*/ OPC_MoveChild, 8,
9413 : /*26325*/ OPC_RecordNode, // #7 = $glc
9414 : /*26326*/ OPC_MoveParent,
9415 : /*26327*/ OPC_MoveChild, 9,
9416 : /*26329*/ OPC_RecordNode, // #8 = $slc
9417 : /*26330*/ OPC_MoveParent,
9418 : /*26331*/ OPC_MoveChild, 10,
9419 : /*26333*/ OPC_RecordNode, // #9 = $tfe
9420 : /*26334*/ OPC_MoveParent,
9421 : /*26335*/ OPC_MoveChild, 11,
9422 : /*26337*/ OPC_RecordNode, // #10 = $lwe
9423 : /*26338*/ OPC_MoveParent,
9424 : /*26339*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9425 : /*26341*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9426 : /*26344*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9427 : /*26347*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9428 : /*26350*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9429 : /*26353*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9430 : /*26356*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9431 : /*26359*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9432 : /*26362*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9433 : /*26365*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V4), 0,
9434 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9435 : // Src: (intrinsic_wo_chain:v4f32 4834:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9436 : // Dst: (IMAGE_SAMPLE_B_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9437 : /*26383*/ /*Scope*/ 68, /*->26452*/
9438 : /*26384*/ OPC_CheckChild1Type, MVT::v8i32,
9439 : /*26386*/ OPC_RecordChild2, // #1 = $rsrc
9440 : /*26387*/ OPC_RecordChild3, // #2 = $sampler
9441 : /*26388*/ OPC_RecordChild4, // #3 = $dmask
9442 : /*26389*/ OPC_RecordChild5, // #4 = $unorm
9443 : /*26390*/ OPC_RecordChild6, // #5 = $r128
9444 : /*26391*/ OPC_RecordChild7, // #6 = $da
9445 : /*26392*/ OPC_MoveChild, 8,
9446 : /*26394*/ OPC_RecordNode, // #7 = $glc
9447 : /*26395*/ OPC_MoveParent,
9448 : /*26396*/ OPC_MoveChild, 9,
9449 : /*26398*/ OPC_RecordNode, // #8 = $slc
9450 : /*26399*/ OPC_MoveParent,
9451 : /*26400*/ OPC_MoveChild, 10,
9452 : /*26402*/ OPC_RecordNode, // #9 = $tfe
9453 : /*26403*/ OPC_MoveParent,
9454 : /*26404*/ OPC_MoveChild, 11,
9455 : /*26406*/ OPC_RecordNode, // #10 = $lwe
9456 : /*26407*/ OPC_MoveParent,
9457 : /*26408*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9458 : /*26410*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9459 : /*26413*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9460 : /*26416*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9461 : /*26419*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9462 : /*26422*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9463 : /*26425*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9464 : /*26428*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9465 : /*26431*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9466 : /*26434*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V8), 0,
9467 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9468 : // Src: (intrinsic_wo_chain:v4f32 4834:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9469 : // Dst: (IMAGE_SAMPLE_B_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9470 : /*26452*/ /*Scope*/ 68, /*->26521*/
9471 : /*26453*/ OPC_CheckChild1Type, MVT::v16i32,
9472 : /*26455*/ OPC_RecordChild2, // #1 = $rsrc
9473 : /*26456*/ OPC_RecordChild3, // #2 = $sampler
9474 : /*26457*/ OPC_RecordChild4, // #3 = $dmask
9475 : /*26458*/ OPC_RecordChild5, // #4 = $unorm
9476 : /*26459*/ OPC_RecordChild6, // #5 = $r128
9477 : /*26460*/ OPC_RecordChild7, // #6 = $da
9478 : /*26461*/ OPC_MoveChild, 8,
9479 : /*26463*/ OPC_RecordNode, // #7 = $glc
9480 : /*26464*/ OPC_MoveParent,
9481 : /*26465*/ OPC_MoveChild, 9,
9482 : /*26467*/ OPC_RecordNode, // #8 = $slc
9483 : /*26468*/ OPC_MoveParent,
9484 : /*26469*/ OPC_MoveChild, 10,
9485 : /*26471*/ OPC_RecordNode, // #9 = $tfe
9486 : /*26472*/ OPC_MoveParent,
9487 : /*26473*/ OPC_MoveChild, 11,
9488 : /*26475*/ OPC_RecordNode, // #10 = $lwe
9489 : /*26476*/ OPC_MoveParent,
9490 : /*26477*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9491 : /*26479*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9492 : /*26482*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9493 : /*26485*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9494 : /*26488*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9495 : /*26491*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9496 : /*26494*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9497 : /*26497*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9498 : /*26500*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9499 : /*26503*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V16), 0,
9500 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9501 : // Src: (intrinsic_wo_chain:v4f32 4834:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9502 : // Dst: (IMAGE_SAMPLE_B_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9503 : /*26521*/ 0, /*End of Scope*/
9504 : /*26522*/ /*Scope*/ 95|128,2/*351*/, /*->26875*/
9505 : /*26524*/ OPC_CheckChild0Integer, 99|128,37/*4835*/,
9506 : /*26527*/ OPC_RecordChild1, // #0 = $addr
9507 : /*26528*/ OPC_Scope, 68, /*->26598*/ // 5 children in Scope
9508 : /*26530*/ OPC_CheckChild1Type, MVT::i32,
9509 : /*26532*/ OPC_RecordChild2, // #1 = $rsrc
9510 : /*26533*/ OPC_RecordChild3, // #2 = $sampler
9511 : /*26534*/ OPC_RecordChild4, // #3 = $dmask
9512 : /*26535*/ OPC_RecordChild5, // #4 = $unorm
9513 : /*26536*/ OPC_RecordChild6, // #5 = $r128
9514 : /*26537*/ OPC_RecordChild7, // #6 = $da
9515 : /*26538*/ OPC_MoveChild, 8,
9516 : /*26540*/ OPC_RecordNode, // #7 = $glc
9517 : /*26541*/ OPC_MoveParent,
9518 : /*26542*/ OPC_MoveChild, 9,
9519 : /*26544*/ OPC_RecordNode, // #8 = $slc
9520 : /*26545*/ OPC_MoveParent,
9521 : /*26546*/ OPC_MoveChild, 10,
9522 : /*26548*/ OPC_RecordNode, // #9 = $tfe
9523 : /*26549*/ OPC_MoveParent,
9524 : /*26550*/ OPC_MoveChild, 11,
9525 : /*26552*/ OPC_RecordNode, // #10 = $lwe
9526 : /*26553*/ OPC_MoveParent,
9527 : /*26554*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9528 : /*26556*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9529 : /*26559*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9530 : /*26562*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9531 : /*26565*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9532 : /*26568*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9533 : /*26571*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9534 : /*26574*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9535 : /*26577*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9536 : /*26580*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_CL_V4_V1), 0,
9537 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9538 : // Src: (intrinsic_wo_chain:v4f32 4835:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9539 : // Dst: (IMAGE_SAMPLE_B_CL_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9540 : /*26598*/ /*Scope*/ 68, /*->26667*/
9541 : /*26599*/ OPC_CheckChild1Type, MVT::v2i32,
9542 : /*26601*/ OPC_RecordChild2, // #1 = $rsrc
9543 : /*26602*/ OPC_RecordChild3, // #2 = $sampler
9544 : /*26603*/ OPC_RecordChild4, // #3 = $dmask
9545 : /*26604*/ OPC_RecordChild5, // #4 = $unorm
9546 : /*26605*/ OPC_RecordChild6, // #5 = $r128
9547 : /*26606*/ OPC_RecordChild7, // #6 = $da
9548 : /*26607*/ OPC_MoveChild, 8,
9549 : /*26609*/ OPC_RecordNode, // #7 = $glc
9550 : /*26610*/ OPC_MoveParent,
9551 : /*26611*/ OPC_MoveChild, 9,
9552 : /*26613*/ OPC_RecordNode, // #8 = $slc
9553 : /*26614*/ OPC_MoveParent,
9554 : /*26615*/ OPC_MoveChild, 10,
9555 : /*26617*/ OPC_RecordNode, // #9 = $tfe
9556 : /*26618*/ OPC_MoveParent,
9557 : /*26619*/ OPC_MoveChild, 11,
9558 : /*26621*/ OPC_RecordNode, // #10 = $lwe
9559 : /*26622*/ OPC_MoveParent,
9560 : /*26623*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9561 : /*26625*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9562 : /*26628*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9563 : /*26631*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9564 : /*26634*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9565 : /*26637*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9566 : /*26640*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9567 : /*26643*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9568 : /*26646*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9569 : /*26649*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2), 0,
9570 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9571 : // Src: (intrinsic_wo_chain:v4f32 4835:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9572 : // Dst: (IMAGE_SAMPLE_B_CL_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9573 : /*26667*/ /*Scope*/ 68, /*->26736*/
9574 : /*26668*/ OPC_CheckChild1Type, MVT::v4i32,
9575 : /*26670*/ OPC_RecordChild2, // #1 = $rsrc
9576 : /*26671*/ OPC_RecordChild3, // #2 = $sampler
9577 : /*26672*/ OPC_RecordChild4, // #3 = $dmask
9578 : /*26673*/ OPC_RecordChild5, // #4 = $unorm
9579 : /*26674*/ OPC_RecordChild6, // #5 = $r128
9580 : /*26675*/ OPC_RecordChild7, // #6 = $da
9581 : /*26676*/ OPC_MoveChild, 8,
9582 : /*26678*/ OPC_RecordNode, // #7 = $glc
9583 : /*26679*/ OPC_MoveParent,
9584 : /*26680*/ OPC_MoveChild, 9,
9585 : /*26682*/ OPC_RecordNode, // #8 = $slc
9586 : /*26683*/ OPC_MoveParent,
9587 : /*26684*/ OPC_MoveChild, 10,
9588 : /*26686*/ OPC_RecordNode, // #9 = $tfe
9589 : /*26687*/ OPC_MoveParent,
9590 : /*26688*/ OPC_MoveChild, 11,
9591 : /*26690*/ OPC_RecordNode, // #10 = $lwe
9592 : /*26691*/ OPC_MoveParent,
9593 : /*26692*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9594 : /*26694*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9595 : /*26697*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9596 : /*26700*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9597 : /*26703*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9598 : /*26706*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9599 : /*26709*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9600 : /*26712*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9601 : /*26715*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9602 : /*26718*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4), 0,
9603 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9604 : // Src: (intrinsic_wo_chain:v4f32 4835:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9605 : // Dst: (IMAGE_SAMPLE_B_CL_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9606 : /*26736*/ /*Scope*/ 68, /*->26805*/
9607 : /*26737*/ OPC_CheckChild1Type, MVT::v8i32,
9608 : /*26739*/ OPC_RecordChild2, // #1 = $rsrc
9609 : /*26740*/ OPC_RecordChild3, // #2 = $sampler
9610 : /*26741*/ OPC_RecordChild4, // #3 = $dmask
9611 : /*26742*/ OPC_RecordChild5, // #4 = $unorm
9612 : /*26743*/ OPC_RecordChild6, // #5 = $r128
9613 : /*26744*/ OPC_RecordChild7, // #6 = $da
9614 : /*26745*/ OPC_MoveChild, 8,
9615 : /*26747*/ OPC_RecordNode, // #7 = $glc
9616 : /*26748*/ OPC_MoveParent,
9617 : /*26749*/ OPC_MoveChild, 9,
9618 : /*26751*/ OPC_RecordNode, // #8 = $slc
9619 : /*26752*/ OPC_MoveParent,
9620 : /*26753*/ OPC_MoveChild, 10,
9621 : /*26755*/ OPC_RecordNode, // #9 = $tfe
9622 : /*26756*/ OPC_MoveParent,
9623 : /*26757*/ OPC_MoveChild, 11,
9624 : /*26759*/ OPC_RecordNode, // #10 = $lwe
9625 : /*26760*/ OPC_MoveParent,
9626 : /*26761*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9627 : /*26763*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9628 : /*26766*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9629 : /*26769*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9630 : /*26772*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9631 : /*26775*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9632 : /*26778*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9633 : /*26781*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9634 : /*26784*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9635 : /*26787*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8), 0,
9636 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9637 : // Src: (intrinsic_wo_chain:v4f32 4835:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9638 : // Dst: (IMAGE_SAMPLE_B_CL_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9639 : /*26805*/ /*Scope*/ 68, /*->26874*/
9640 : /*26806*/ OPC_CheckChild1Type, MVT::v16i32,
9641 : /*26808*/ OPC_RecordChild2, // #1 = $rsrc
9642 : /*26809*/ OPC_RecordChild3, // #2 = $sampler
9643 : /*26810*/ OPC_RecordChild4, // #3 = $dmask
9644 : /*26811*/ OPC_RecordChild5, // #4 = $unorm
9645 : /*26812*/ OPC_RecordChild6, // #5 = $r128
9646 : /*26813*/ OPC_RecordChild7, // #6 = $da
9647 : /*26814*/ OPC_MoveChild, 8,
9648 : /*26816*/ OPC_RecordNode, // #7 = $glc
9649 : /*26817*/ OPC_MoveParent,
9650 : /*26818*/ OPC_MoveChild, 9,
9651 : /*26820*/ OPC_RecordNode, // #8 = $slc
9652 : /*26821*/ OPC_MoveParent,
9653 : /*26822*/ OPC_MoveChild, 10,
9654 : /*26824*/ OPC_RecordNode, // #9 = $tfe
9655 : /*26825*/ OPC_MoveParent,
9656 : /*26826*/ OPC_MoveChild, 11,
9657 : /*26828*/ OPC_RecordNode, // #10 = $lwe
9658 : /*26829*/ OPC_MoveParent,
9659 : /*26830*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9660 : /*26832*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9661 : /*26835*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9662 : /*26838*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9663 : /*26841*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9664 : /*26844*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9665 : /*26847*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9666 : /*26850*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9667 : /*26853*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9668 : /*26856*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_CL_V4_V16), 0,
9669 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9670 : // Src: (intrinsic_wo_chain:v4f32 4835:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9671 : // Dst: (IMAGE_SAMPLE_B_CL_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9672 : /*26874*/ 0, /*End of Scope*/
9673 : /*26875*/ /*Scope*/ 95|128,2/*351*/, /*->27228*/
9674 : /*26877*/ OPC_CheckChild0Integer, 6|128,38/*4870*/,
9675 : /*26880*/ OPC_RecordChild1, // #0 = $addr
9676 : /*26881*/ OPC_Scope, 68, /*->26951*/ // 5 children in Scope
9677 : /*26883*/ OPC_CheckChild1Type, MVT::i32,
9678 : /*26885*/ OPC_RecordChild2, // #1 = $rsrc
9679 : /*26886*/ OPC_RecordChild3, // #2 = $sampler
9680 : /*26887*/ OPC_RecordChild4, // #3 = $dmask
9681 : /*26888*/ OPC_RecordChild5, // #4 = $unorm
9682 : /*26889*/ OPC_RecordChild6, // #5 = $r128
9683 : /*26890*/ OPC_RecordChild7, // #6 = $da
9684 : /*26891*/ OPC_MoveChild, 8,
9685 : /*26893*/ OPC_RecordNode, // #7 = $glc
9686 : /*26894*/ OPC_MoveParent,
9687 : /*26895*/ OPC_MoveChild, 9,
9688 : /*26897*/ OPC_RecordNode, // #8 = $slc
9689 : /*26898*/ OPC_MoveParent,
9690 : /*26899*/ OPC_MoveChild, 10,
9691 : /*26901*/ OPC_RecordNode, // #9 = $tfe
9692 : /*26902*/ OPC_MoveParent,
9693 : /*26903*/ OPC_MoveChild, 11,
9694 : /*26905*/ OPC_RecordNode, // #10 = $lwe
9695 : /*26906*/ OPC_MoveParent,
9696 : /*26907*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9697 : /*26909*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9698 : /*26912*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9699 : /*26915*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9700 : /*26918*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9701 : /*26921*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9702 : /*26924*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9703 : /*26927*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9704 : /*26930*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9705 : /*26933*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_LZ_V4_V1), 0,
9706 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9707 : // Src: (intrinsic_wo_chain:v4f32 4870:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9708 : // Dst: (IMAGE_SAMPLE_LZ_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9709 : /*26951*/ /*Scope*/ 68, /*->27020*/
9710 : /*26952*/ OPC_CheckChild1Type, MVT::v2i32,
9711 : /*26954*/ OPC_RecordChild2, // #1 = $rsrc
9712 : /*26955*/ OPC_RecordChild3, // #2 = $sampler
9713 : /*26956*/ OPC_RecordChild4, // #3 = $dmask
9714 : /*26957*/ OPC_RecordChild5, // #4 = $unorm
9715 : /*26958*/ OPC_RecordChild6, // #5 = $r128
9716 : /*26959*/ OPC_RecordChild7, // #6 = $da
9717 : /*26960*/ OPC_MoveChild, 8,
9718 : /*26962*/ OPC_RecordNode, // #7 = $glc
9719 : /*26963*/ OPC_MoveParent,
9720 : /*26964*/ OPC_MoveChild, 9,
9721 : /*26966*/ OPC_RecordNode, // #8 = $slc
9722 : /*26967*/ OPC_MoveParent,
9723 : /*26968*/ OPC_MoveChild, 10,
9724 : /*26970*/ OPC_RecordNode, // #9 = $tfe
9725 : /*26971*/ OPC_MoveParent,
9726 : /*26972*/ OPC_MoveChild, 11,
9727 : /*26974*/ OPC_RecordNode, // #10 = $lwe
9728 : /*26975*/ OPC_MoveParent,
9729 : /*26976*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9730 : /*26978*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9731 : /*26981*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9732 : /*26984*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9733 : /*26987*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9734 : /*26990*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9735 : /*26993*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9736 : /*26996*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9737 : /*26999*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9738 : /*27002*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_LZ_V4_V2), 0,
9739 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9740 : // Src: (intrinsic_wo_chain:v4f32 4870:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9741 : // Dst: (IMAGE_SAMPLE_LZ_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9742 : /*27020*/ /*Scope*/ 68, /*->27089*/
9743 : /*27021*/ OPC_CheckChild1Type, MVT::v4i32,
9744 : /*27023*/ OPC_RecordChild2, // #1 = $rsrc
9745 : /*27024*/ OPC_RecordChild3, // #2 = $sampler
9746 : /*27025*/ OPC_RecordChild4, // #3 = $dmask
9747 : /*27026*/ OPC_RecordChild5, // #4 = $unorm
9748 : /*27027*/ OPC_RecordChild6, // #5 = $r128
9749 : /*27028*/ OPC_RecordChild7, // #6 = $da
9750 : /*27029*/ OPC_MoveChild, 8,
9751 : /*27031*/ OPC_RecordNode, // #7 = $glc
9752 : /*27032*/ OPC_MoveParent,
9753 : /*27033*/ OPC_MoveChild, 9,
9754 : /*27035*/ OPC_RecordNode, // #8 = $slc
9755 : /*27036*/ OPC_MoveParent,
9756 : /*27037*/ OPC_MoveChild, 10,
9757 : /*27039*/ OPC_RecordNode, // #9 = $tfe
9758 : /*27040*/ OPC_MoveParent,
9759 : /*27041*/ OPC_MoveChild, 11,
9760 : /*27043*/ OPC_RecordNode, // #10 = $lwe
9761 : /*27044*/ OPC_MoveParent,
9762 : /*27045*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9763 : /*27047*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9764 : /*27050*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9765 : /*27053*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9766 : /*27056*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9767 : /*27059*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9768 : /*27062*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9769 : /*27065*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9770 : /*27068*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9771 : /*27071*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_LZ_V4_V4), 0,
9772 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9773 : // Src: (intrinsic_wo_chain:v4f32 4870:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9774 : // Dst: (IMAGE_SAMPLE_LZ_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9775 : /*27089*/ /*Scope*/ 68, /*->27158*/
9776 : /*27090*/ OPC_CheckChild1Type, MVT::v8i32,
9777 : /*27092*/ OPC_RecordChild2, // #1 = $rsrc
9778 : /*27093*/ OPC_RecordChild3, // #2 = $sampler
9779 : /*27094*/ OPC_RecordChild4, // #3 = $dmask
9780 : /*27095*/ OPC_RecordChild5, // #4 = $unorm
9781 : /*27096*/ OPC_RecordChild6, // #5 = $r128
9782 : /*27097*/ OPC_RecordChild7, // #6 = $da
9783 : /*27098*/ OPC_MoveChild, 8,
9784 : /*27100*/ OPC_RecordNode, // #7 = $glc
9785 : /*27101*/ OPC_MoveParent,
9786 : /*27102*/ OPC_MoveChild, 9,
9787 : /*27104*/ OPC_RecordNode, // #8 = $slc
9788 : /*27105*/ OPC_MoveParent,
9789 : /*27106*/ OPC_MoveChild, 10,
9790 : /*27108*/ OPC_RecordNode, // #9 = $tfe
9791 : /*27109*/ OPC_MoveParent,
9792 : /*27110*/ OPC_MoveChild, 11,
9793 : /*27112*/ OPC_RecordNode, // #10 = $lwe
9794 : /*27113*/ OPC_MoveParent,
9795 : /*27114*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9796 : /*27116*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9797 : /*27119*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9798 : /*27122*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9799 : /*27125*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9800 : /*27128*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9801 : /*27131*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9802 : /*27134*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9803 : /*27137*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9804 : /*27140*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_LZ_V4_V8), 0,
9805 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9806 : // Src: (intrinsic_wo_chain:v4f32 4870:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9807 : // Dst: (IMAGE_SAMPLE_LZ_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9808 : /*27158*/ /*Scope*/ 68, /*->27227*/
9809 : /*27159*/ OPC_CheckChild1Type, MVT::v16i32,
9810 : /*27161*/ OPC_RecordChild2, // #1 = $rsrc
9811 : /*27162*/ OPC_RecordChild3, // #2 = $sampler
9812 : /*27163*/ OPC_RecordChild4, // #3 = $dmask
9813 : /*27164*/ OPC_RecordChild5, // #4 = $unorm
9814 : /*27165*/ OPC_RecordChild6, // #5 = $r128
9815 : /*27166*/ OPC_RecordChild7, // #6 = $da
9816 : /*27167*/ OPC_MoveChild, 8,
9817 : /*27169*/ OPC_RecordNode, // #7 = $glc
9818 : /*27170*/ OPC_MoveParent,
9819 : /*27171*/ OPC_MoveChild, 9,
9820 : /*27173*/ OPC_RecordNode, // #8 = $slc
9821 : /*27174*/ OPC_MoveParent,
9822 : /*27175*/ OPC_MoveChild, 10,
9823 : /*27177*/ OPC_RecordNode, // #9 = $tfe
9824 : /*27178*/ OPC_MoveParent,
9825 : /*27179*/ OPC_MoveChild, 11,
9826 : /*27181*/ OPC_RecordNode, // #10 = $lwe
9827 : /*27182*/ OPC_MoveParent,
9828 : /*27183*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9829 : /*27185*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9830 : /*27188*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9831 : /*27191*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9832 : /*27194*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9833 : /*27197*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9834 : /*27200*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9835 : /*27203*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9836 : /*27206*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9837 : /*27209*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_LZ_V4_V16), 0,
9838 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9839 : // Src: (intrinsic_wo_chain:v4f32 4870:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9840 : // Dst: (IMAGE_SAMPLE_LZ_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9841 : /*27227*/ 0, /*End of Scope*/
9842 : /*27228*/ /*Scope*/ 95|128,2/*351*/, /*->27581*/
9843 : /*27230*/ OPC_CheckChild0Integer, 122|128,37/*4858*/,
9844 : /*27233*/ OPC_RecordChild1, // #0 = $addr
9845 : /*27234*/ OPC_Scope, 68, /*->27304*/ // 5 children in Scope
9846 : /*27236*/ OPC_CheckChild1Type, MVT::i32,
9847 : /*27238*/ OPC_RecordChild2, // #1 = $rsrc
9848 : /*27239*/ OPC_RecordChild3, // #2 = $sampler
9849 : /*27240*/ OPC_RecordChild4, // #3 = $dmask
9850 : /*27241*/ OPC_RecordChild5, // #4 = $unorm
9851 : /*27242*/ OPC_RecordChild6, // #5 = $r128
9852 : /*27243*/ OPC_RecordChild7, // #6 = $da
9853 : /*27244*/ OPC_MoveChild, 8,
9854 : /*27246*/ OPC_RecordNode, // #7 = $glc
9855 : /*27247*/ OPC_MoveParent,
9856 : /*27248*/ OPC_MoveChild, 9,
9857 : /*27250*/ OPC_RecordNode, // #8 = $slc
9858 : /*27251*/ OPC_MoveParent,
9859 : /*27252*/ OPC_MoveChild, 10,
9860 : /*27254*/ OPC_RecordNode, // #9 = $tfe
9861 : /*27255*/ OPC_MoveParent,
9862 : /*27256*/ OPC_MoveChild, 11,
9863 : /*27258*/ OPC_RecordNode, // #10 = $lwe
9864 : /*27259*/ OPC_MoveParent,
9865 : /*27260*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9866 : /*27262*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9867 : /*27265*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9868 : /*27268*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9869 : /*27271*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9870 : /*27274*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9871 : /*27277*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9872 : /*27280*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9873 : /*27283*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9874 : /*27286*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_V4_V1), 0,
9875 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9876 : // Src: (intrinsic_wo_chain:v4f32 4858:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9877 : // Dst: (IMAGE_SAMPLE_CD_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9878 : /*27304*/ /*Scope*/ 68, /*->27373*/
9879 : /*27305*/ OPC_CheckChild1Type, MVT::v2i32,
9880 : /*27307*/ OPC_RecordChild2, // #1 = $rsrc
9881 : /*27308*/ OPC_RecordChild3, // #2 = $sampler
9882 : /*27309*/ OPC_RecordChild4, // #3 = $dmask
9883 : /*27310*/ OPC_RecordChild5, // #4 = $unorm
9884 : /*27311*/ OPC_RecordChild6, // #5 = $r128
9885 : /*27312*/ OPC_RecordChild7, // #6 = $da
9886 : /*27313*/ OPC_MoveChild, 8,
9887 : /*27315*/ OPC_RecordNode, // #7 = $glc
9888 : /*27316*/ OPC_MoveParent,
9889 : /*27317*/ OPC_MoveChild, 9,
9890 : /*27319*/ OPC_RecordNode, // #8 = $slc
9891 : /*27320*/ OPC_MoveParent,
9892 : /*27321*/ OPC_MoveChild, 10,
9893 : /*27323*/ OPC_RecordNode, // #9 = $tfe
9894 : /*27324*/ OPC_MoveParent,
9895 : /*27325*/ OPC_MoveChild, 11,
9896 : /*27327*/ OPC_RecordNode, // #10 = $lwe
9897 : /*27328*/ OPC_MoveParent,
9898 : /*27329*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9899 : /*27331*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9900 : /*27334*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9901 : /*27337*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9902 : /*27340*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9903 : /*27343*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9904 : /*27346*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9905 : /*27349*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9906 : /*27352*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9907 : /*27355*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_V4_V2), 0,
9908 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9909 : // Src: (intrinsic_wo_chain:v4f32 4858:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9910 : // Dst: (IMAGE_SAMPLE_CD_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9911 : /*27373*/ /*Scope*/ 68, /*->27442*/
9912 : /*27374*/ OPC_CheckChild1Type, MVT::v4i32,
9913 : /*27376*/ OPC_RecordChild2, // #1 = $rsrc
9914 : /*27377*/ OPC_RecordChild3, // #2 = $sampler
9915 : /*27378*/ OPC_RecordChild4, // #3 = $dmask
9916 : /*27379*/ OPC_RecordChild5, // #4 = $unorm
9917 : /*27380*/ OPC_RecordChild6, // #5 = $r128
9918 : /*27381*/ OPC_RecordChild7, // #6 = $da
9919 : /*27382*/ OPC_MoveChild, 8,
9920 : /*27384*/ OPC_RecordNode, // #7 = $glc
9921 : /*27385*/ OPC_MoveParent,
9922 : /*27386*/ OPC_MoveChild, 9,
9923 : /*27388*/ OPC_RecordNode, // #8 = $slc
9924 : /*27389*/ OPC_MoveParent,
9925 : /*27390*/ OPC_MoveChild, 10,
9926 : /*27392*/ OPC_RecordNode, // #9 = $tfe
9927 : /*27393*/ OPC_MoveParent,
9928 : /*27394*/ OPC_MoveChild, 11,
9929 : /*27396*/ OPC_RecordNode, // #10 = $lwe
9930 : /*27397*/ OPC_MoveParent,
9931 : /*27398*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9932 : /*27400*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9933 : /*27403*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9934 : /*27406*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9935 : /*27409*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9936 : /*27412*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9937 : /*27415*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9938 : /*27418*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9939 : /*27421*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9940 : /*27424*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_V4_V4), 0,
9941 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9942 : // Src: (intrinsic_wo_chain:v4f32 4858:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9943 : // Dst: (IMAGE_SAMPLE_CD_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9944 : /*27442*/ /*Scope*/ 68, /*->27511*/
9945 : /*27443*/ OPC_CheckChild1Type, MVT::v8i32,
9946 : /*27445*/ OPC_RecordChild2, // #1 = $rsrc
9947 : /*27446*/ OPC_RecordChild3, // #2 = $sampler
9948 : /*27447*/ OPC_RecordChild4, // #3 = $dmask
9949 : /*27448*/ OPC_RecordChild5, // #4 = $unorm
9950 : /*27449*/ OPC_RecordChild6, // #5 = $r128
9951 : /*27450*/ OPC_RecordChild7, // #6 = $da
9952 : /*27451*/ OPC_MoveChild, 8,
9953 : /*27453*/ OPC_RecordNode, // #7 = $glc
9954 : /*27454*/ OPC_MoveParent,
9955 : /*27455*/ OPC_MoveChild, 9,
9956 : /*27457*/ OPC_RecordNode, // #8 = $slc
9957 : /*27458*/ OPC_MoveParent,
9958 : /*27459*/ OPC_MoveChild, 10,
9959 : /*27461*/ OPC_RecordNode, // #9 = $tfe
9960 : /*27462*/ OPC_MoveParent,
9961 : /*27463*/ OPC_MoveChild, 11,
9962 : /*27465*/ OPC_RecordNode, // #10 = $lwe
9963 : /*27466*/ OPC_MoveParent,
9964 : /*27467*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9965 : /*27469*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9966 : /*27472*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
9967 : /*27475*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
9968 : /*27478*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
9969 : /*27481*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
9970 : /*27484*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
9971 : /*27487*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
9972 : /*27490*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
9973 : /*27493*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_V4_V8), 0,
9974 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
9975 : // Src: (intrinsic_wo_chain:v4f32 4858:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
9976 : // Dst: (IMAGE_SAMPLE_CD_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
9977 : /*27511*/ /*Scope*/ 68, /*->27580*/
9978 : /*27512*/ OPC_CheckChild1Type, MVT::v16i32,
9979 : /*27514*/ OPC_RecordChild2, // #1 = $rsrc
9980 : /*27515*/ OPC_RecordChild3, // #2 = $sampler
9981 : /*27516*/ OPC_RecordChild4, // #3 = $dmask
9982 : /*27517*/ OPC_RecordChild5, // #4 = $unorm
9983 : /*27518*/ OPC_RecordChild6, // #5 = $r128
9984 : /*27519*/ OPC_RecordChild7, // #6 = $da
9985 : /*27520*/ OPC_MoveChild, 8,
9986 : /*27522*/ OPC_RecordNode, // #7 = $glc
9987 : /*27523*/ OPC_MoveParent,
9988 : /*27524*/ OPC_MoveChild, 9,
9989 : /*27526*/ OPC_RecordNode, // #8 = $slc
9990 : /*27527*/ OPC_MoveParent,
9991 : /*27528*/ OPC_MoveChild, 10,
9992 : /*27530*/ OPC_RecordNode, // #9 = $tfe
9993 : /*27531*/ OPC_MoveParent,
9994 : /*27532*/ OPC_MoveChild, 11,
9995 : /*27534*/ OPC_RecordNode, // #10 = $lwe
9996 : /*27535*/ OPC_MoveParent,
9997 : /*27536*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
9998 : /*27538*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
9999 : /*27541*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10000 : /*27544*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10001 : /*27547*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10002 : /*27550*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10003 : /*27553*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10004 : /*27556*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10005 : /*27559*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10006 : /*27562*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_V4_V16), 0,
10007 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10008 : // Src: (intrinsic_wo_chain:v4f32 4858:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10009 : // Dst: (IMAGE_SAMPLE_CD_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10010 : /*27580*/ 0, /*End of Scope*/
10011 : /*27581*/ /*Scope*/ 95|128,2/*351*/, /*->27934*/
10012 : /*27583*/ OPC_CheckChild0Integer, 123|128,37/*4859*/,
10013 : /*27586*/ OPC_RecordChild1, // #0 = $addr
10014 : /*27587*/ OPC_Scope, 68, /*->27657*/ // 5 children in Scope
10015 : /*27589*/ OPC_CheckChild1Type, MVT::i32,
10016 : /*27591*/ OPC_RecordChild2, // #1 = $rsrc
10017 : /*27592*/ OPC_RecordChild3, // #2 = $sampler
10018 : /*27593*/ OPC_RecordChild4, // #3 = $dmask
10019 : /*27594*/ OPC_RecordChild5, // #4 = $unorm
10020 : /*27595*/ OPC_RecordChild6, // #5 = $r128
10021 : /*27596*/ OPC_RecordChild7, // #6 = $da
10022 : /*27597*/ OPC_MoveChild, 8,
10023 : /*27599*/ OPC_RecordNode, // #7 = $glc
10024 : /*27600*/ OPC_MoveParent,
10025 : /*27601*/ OPC_MoveChild, 9,
10026 : /*27603*/ OPC_RecordNode, // #8 = $slc
10027 : /*27604*/ OPC_MoveParent,
10028 : /*27605*/ OPC_MoveChild, 10,
10029 : /*27607*/ OPC_RecordNode, // #9 = $tfe
10030 : /*27608*/ OPC_MoveParent,
10031 : /*27609*/ OPC_MoveChild, 11,
10032 : /*27611*/ OPC_RecordNode, // #10 = $lwe
10033 : /*27612*/ OPC_MoveParent,
10034 : /*27613*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10035 : /*27615*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10036 : /*27618*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10037 : /*27621*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10038 : /*27624*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10039 : /*27627*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10040 : /*27630*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10041 : /*27633*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10042 : /*27636*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10043 : /*27639*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V1), 0,
10044 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10045 : // Src: (intrinsic_wo_chain:v4f32 4859:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10046 : // Dst: (IMAGE_SAMPLE_CD_CL_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10047 : /*27657*/ /*Scope*/ 68, /*->27726*/
10048 : /*27658*/ OPC_CheckChild1Type, MVT::v2i32,
10049 : /*27660*/ OPC_RecordChild2, // #1 = $rsrc
10050 : /*27661*/ OPC_RecordChild3, // #2 = $sampler
10051 : /*27662*/ OPC_RecordChild4, // #3 = $dmask
10052 : /*27663*/ OPC_RecordChild5, // #4 = $unorm
10053 : /*27664*/ OPC_RecordChild6, // #5 = $r128
10054 : /*27665*/ OPC_RecordChild7, // #6 = $da
10055 : /*27666*/ OPC_MoveChild, 8,
10056 : /*27668*/ OPC_RecordNode, // #7 = $glc
10057 : /*27669*/ OPC_MoveParent,
10058 : /*27670*/ OPC_MoveChild, 9,
10059 : /*27672*/ OPC_RecordNode, // #8 = $slc
10060 : /*27673*/ OPC_MoveParent,
10061 : /*27674*/ OPC_MoveChild, 10,
10062 : /*27676*/ OPC_RecordNode, // #9 = $tfe
10063 : /*27677*/ OPC_MoveParent,
10064 : /*27678*/ OPC_MoveChild, 11,
10065 : /*27680*/ OPC_RecordNode, // #10 = $lwe
10066 : /*27681*/ OPC_MoveParent,
10067 : /*27682*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10068 : /*27684*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10069 : /*27687*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10070 : /*27690*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10071 : /*27693*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10072 : /*27696*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10073 : /*27699*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10074 : /*27702*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10075 : /*27705*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10076 : /*27708*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2), 0,
10077 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10078 : // Src: (intrinsic_wo_chain:v4f32 4859:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10079 : // Dst: (IMAGE_SAMPLE_CD_CL_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10080 : /*27726*/ /*Scope*/ 68, /*->27795*/
10081 : /*27727*/ OPC_CheckChild1Type, MVT::v4i32,
10082 : /*27729*/ OPC_RecordChild2, // #1 = $rsrc
10083 : /*27730*/ OPC_RecordChild3, // #2 = $sampler
10084 : /*27731*/ OPC_RecordChild4, // #3 = $dmask
10085 : /*27732*/ OPC_RecordChild5, // #4 = $unorm
10086 : /*27733*/ OPC_RecordChild6, // #5 = $r128
10087 : /*27734*/ OPC_RecordChild7, // #6 = $da
10088 : /*27735*/ OPC_MoveChild, 8,
10089 : /*27737*/ OPC_RecordNode, // #7 = $glc
10090 : /*27738*/ OPC_MoveParent,
10091 : /*27739*/ OPC_MoveChild, 9,
10092 : /*27741*/ OPC_RecordNode, // #8 = $slc
10093 : /*27742*/ OPC_MoveParent,
10094 : /*27743*/ OPC_MoveChild, 10,
10095 : /*27745*/ OPC_RecordNode, // #9 = $tfe
10096 : /*27746*/ OPC_MoveParent,
10097 : /*27747*/ OPC_MoveChild, 11,
10098 : /*27749*/ OPC_RecordNode, // #10 = $lwe
10099 : /*27750*/ OPC_MoveParent,
10100 : /*27751*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10101 : /*27753*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10102 : /*27756*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10103 : /*27759*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10104 : /*27762*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10105 : /*27765*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10106 : /*27768*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10107 : /*27771*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10108 : /*27774*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10109 : /*27777*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4), 0,
10110 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10111 : // Src: (intrinsic_wo_chain:v4f32 4859:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10112 : // Dst: (IMAGE_SAMPLE_CD_CL_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10113 : /*27795*/ /*Scope*/ 68, /*->27864*/
10114 : /*27796*/ OPC_CheckChild1Type, MVT::v8i32,
10115 : /*27798*/ OPC_RecordChild2, // #1 = $rsrc
10116 : /*27799*/ OPC_RecordChild3, // #2 = $sampler
10117 : /*27800*/ OPC_RecordChild4, // #3 = $dmask
10118 : /*27801*/ OPC_RecordChild5, // #4 = $unorm
10119 : /*27802*/ OPC_RecordChild6, // #5 = $r128
10120 : /*27803*/ OPC_RecordChild7, // #6 = $da
10121 : /*27804*/ OPC_MoveChild, 8,
10122 : /*27806*/ OPC_RecordNode, // #7 = $glc
10123 : /*27807*/ OPC_MoveParent,
10124 : /*27808*/ OPC_MoveChild, 9,
10125 : /*27810*/ OPC_RecordNode, // #8 = $slc
10126 : /*27811*/ OPC_MoveParent,
10127 : /*27812*/ OPC_MoveChild, 10,
10128 : /*27814*/ OPC_RecordNode, // #9 = $tfe
10129 : /*27815*/ OPC_MoveParent,
10130 : /*27816*/ OPC_MoveChild, 11,
10131 : /*27818*/ OPC_RecordNode, // #10 = $lwe
10132 : /*27819*/ OPC_MoveParent,
10133 : /*27820*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10134 : /*27822*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10135 : /*27825*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10136 : /*27828*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10137 : /*27831*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10138 : /*27834*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10139 : /*27837*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10140 : /*27840*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10141 : /*27843*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10142 : /*27846*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8), 0,
10143 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10144 : // Src: (intrinsic_wo_chain:v4f32 4859:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10145 : // Dst: (IMAGE_SAMPLE_CD_CL_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10146 : /*27864*/ /*Scope*/ 68, /*->27933*/
10147 : /*27865*/ OPC_CheckChild1Type, MVT::v16i32,
10148 : /*27867*/ OPC_RecordChild2, // #1 = $rsrc
10149 : /*27868*/ OPC_RecordChild3, // #2 = $sampler
10150 : /*27869*/ OPC_RecordChild4, // #3 = $dmask
10151 : /*27870*/ OPC_RecordChild5, // #4 = $unorm
10152 : /*27871*/ OPC_RecordChild6, // #5 = $r128
10153 : /*27872*/ OPC_RecordChild7, // #6 = $da
10154 : /*27873*/ OPC_MoveChild, 8,
10155 : /*27875*/ OPC_RecordNode, // #7 = $glc
10156 : /*27876*/ OPC_MoveParent,
10157 : /*27877*/ OPC_MoveChild, 9,
10158 : /*27879*/ OPC_RecordNode, // #8 = $slc
10159 : /*27880*/ OPC_MoveParent,
10160 : /*27881*/ OPC_MoveChild, 10,
10161 : /*27883*/ OPC_RecordNode, // #9 = $tfe
10162 : /*27884*/ OPC_MoveParent,
10163 : /*27885*/ OPC_MoveChild, 11,
10164 : /*27887*/ OPC_RecordNode, // #10 = $lwe
10165 : /*27888*/ OPC_MoveParent,
10166 : /*27889*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10167 : /*27891*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10168 : /*27894*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10169 : /*27897*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10170 : /*27900*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10171 : /*27903*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10172 : /*27906*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10173 : /*27909*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10174 : /*27912*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10175 : /*27915*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V16), 0,
10176 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10177 : // Src: (intrinsic_wo_chain:v4f32 4859:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10178 : // Dst: (IMAGE_SAMPLE_CD_CL_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10179 : /*27933*/ 0, /*End of Scope*/
10180 : /*27934*/ /*Scope*/ 95|128,2/*351*/, /*->28287*/
10181 : /*27936*/ OPC_CheckChild0Integer, 102|128,37/*4838*/,
10182 : /*27939*/ OPC_RecordChild1, // #0 = $addr
10183 : /*27940*/ OPC_Scope, 68, /*->28010*/ // 5 children in Scope
10184 : /*27942*/ OPC_CheckChild1Type, MVT::i32,
10185 : /*27944*/ OPC_RecordChild2, // #1 = $rsrc
10186 : /*27945*/ OPC_RecordChild3, // #2 = $sampler
10187 : /*27946*/ OPC_RecordChild4, // #3 = $dmask
10188 : /*27947*/ OPC_RecordChild5, // #4 = $unorm
10189 : /*27948*/ OPC_RecordChild6, // #5 = $r128
10190 : /*27949*/ OPC_RecordChild7, // #6 = $da
10191 : /*27950*/ OPC_MoveChild, 8,
10192 : /*27952*/ OPC_RecordNode, // #7 = $glc
10193 : /*27953*/ OPC_MoveParent,
10194 : /*27954*/ OPC_MoveChild, 9,
10195 : /*27956*/ OPC_RecordNode, // #8 = $slc
10196 : /*27957*/ OPC_MoveParent,
10197 : /*27958*/ OPC_MoveChild, 10,
10198 : /*27960*/ OPC_RecordNode, // #9 = $tfe
10199 : /*27961*/ OPC_MoveParent,
10200 : /*27962*/ OPC_MoveChild, 11,
10201 : /*27964*/ OPC_RecordNode, // #10 = $lwe
10202 : /*27965*/ OPC_MoveParent,
10203 : /*27966*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10204 : /*27968*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10205 : /*27971*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10206 : /*27974*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10207 : /*27977*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10208 : /*27980*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10209 : /*27983*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10210 : /*27986*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10211 : /*27989*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10212 : /*27992*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V1), 0,
10213 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10214 : // Src: (intrinsic_wo_chain:v4f32 4838:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10215 : // Dst: (IMAGE_SAMPLE_C_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10216 : /*28010*/ /*Scope*/ 68, /*->28079*/
10217 : /*28011*/ OPC_CheckChild1Type, MVT::v2i32,
10218 : /*28013*/ OPC_RecordChild2, // #1 = $rsrc
10219 : /*28014*/ OPC_RecordChild3, // #2 = $sampler
10220 : /*28015*/ OPC_RecordChild4, // #3 = $dmask
10221 : /*28016*/ OPC_RecordChild5, // #4 = $unorm
10222 : /*28017*/ OPC_RecordChild6, // #5 = $r128
10223 : /*28018*/ OPC_RecordChild7, // #6 = $da
10224 : /*28019*/ OPC_MoveChild, 8,
10225 : /*28021*/ OPC_RecordNode, // #7 = $glc
10226 : /*28022*/ OPC_MoveParent,
10227 : /*28023*/ OPC_MoveChild, 9,
10228 : /*28025*/ OPC_RecordNode, // #8 = $slc
10229 : /*28026*/ OPC_MoveParent,
10230 : /*28027*/ OPC_MoveChild, 10,
10231 : /*28029*/ OPC_RecordNode, // #9 = $tfe
10232 : /*28030*/ OPC_MoveParent,
10233 : /*28031*/ OPC_MoveChild, 11,
10234 : /*28033*/ OPC_RecordNode, // #10 = $lwe
10235 : /*28034*/ OPC_MoveParent,
10236 : /*28035*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10237 : /*28037*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10238 : /*28040*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10239 : /*28043*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10240 : /*28046*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10241 : /*28049*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10242 : /*28052*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10243 : /*28055*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10244 : /*28058*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10245 : /*28061*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V2), 0,
10246 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10247 : // Src: (intrinsic_wo_chain:v4f32 4838:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10248 : // Dst: (IMAGE_SAMPLE_C_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10249 : /*28079*/ /*Scope*/ 68, /*->28148*/
10250 : /*28080*/ OPC_CheckChild1Type, MVT::v4i32,
10251 : /*28082*/ OPC_RecordChild2, // #1 = $rsrc
10252 : /*28083*/ OPC_RecordChild3, // #2 = $sampler
10253 : /*28084*/ OPC_RecordChild4, // #3 = $dmask
10254 : /*28085*/ OPC_RecordChild5, // #4 = $unorm
10255 : /*28086*/ OPC_RecordChild6, // #5 = $r128
10256 : /*28087*/ OPC_RecordChild7, // #6 = $da
10257 : /*28088*/ OPC_MoveChild, 8,
10258 : /*28090*/ OPC_RecordNode, // #7 = $glc
10259 : /*28091*/ OPC_MoveParent,
10260 : /*28092*/ OPC_MoveChild, 9,
10261 : /*28094*/ OPC_RecordNode, // #8 = $slc
10262 : /*28095*/ OPC_MoveParent,
10263 : /*28096*/ OPC_MoveChild, 10,
10264 : /*28098*/ OPC_RecordNode, // #9 = $tfe
10265 : /*28099*/ OPC_MoveParent,
10266 : /*28100*/ OPC_MoveChild, 11,
10267 : /*28102*/ OPC_RecordNode, // #10 = $lwe
10268 : /*28103*/ OPC_MoveParent,
10269 : /*28104*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10270 : /*28106*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10271 : /*28109*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10272 : /*28112*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10273 : /*28115*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10274 : /*28118*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10275 : /*28121*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10276 : /*28124*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10277 : /*28127*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10278 : /*28130*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V4), 0,
10279 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10280 : // Src: (intrinsic_wo_chain:v4f32 4838:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10281 : // Dst: (IMAGE_SAMPLE_C_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10282 : /*28148*/ /*Scope*/ 68, /*->28217*/
10283 : /*28149*/ OPC_CheckChild1Type, MVT::v8i32,
10284 : /*28151*/ OPC_RecordChild2, // #1 = $rsrc
10285 : /*28152*/ OPC_RecordChild3, // #2 = $sampler
10286 : /*28153*/ OPC_RecordChild4, // #3 = $dmask
10287 : /*28154*/ OPC_RecordChild5, // #4 = $unorm
10288 : /*28155*/ OPC_RecordChild6, // #5 = $r128
10289 : /*28156*/ OPC_RecordChild7, // #6 = $da
10290 : /*28157*/ OPC_MoveChild, 8,
10291 : /*28159*/ OPC_RecordNode, // #7 = $glc
10292 : /*28160*/ OPC_MoveParent,
10293 : /*28161*/ OPC_MoveChild, 9,
10294 : /*28163*/ OPC_RecordNode, // #8 = $slc
10295 : /*28164*/ OPC_MoveParent,
10296 : /*28165*/ OPC_MoveChild, 10,
10297 : /*28167*/ OPC_RecordNode, // #9 = $tfe
10298 : /*28168*/ OPC_MoveParent,
10299 : /*28169*/ OPC_MoveChild, 11,
10300 : /*28171*/ OPC_RecordNode, // #10 = $lwe
10301 : /*28172*/ OPC_MoveParent,
10302 : /*28173*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10303 : /*28175*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10304 : /*28178*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10305 : /*28181*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10306 : /*28184*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10307 : /*28187*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10308 : /*28190*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10309 : /*28193*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10310 : /*28196*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10311 : /*28199*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V8), 0,
10312 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10313 : // Src: (intrinsic_wo_chain:v4f32 4838:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10314 : // Dst: (IMAGE_SAMPLE_C_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10315 : /*28217*/ /*Scope*/ 68, /*->28286*/
10316 : /*28218*/ OPC_CheckChild1Type, MVT::v16i32,
10317 : /*28220*/ OPC_RecordChild2, // #1 = $rsrc
10318 : /*28221*/ OPC_RecordChild3, // #2 = $sampler
10319 : /*28222*/ OPC_RecordChild4, // #3 = $dmask
10320 : /*28223*/ OPC_RecordChild5, // #4 = $unorm
10321 : /*28224*/ OPC_RecordChild6, // #5 = $r128
10322 : /*28225*/ OPC_RecordChild7, // #6 = $da
10323 : /*28226*/ OPC_MoveChild, 8,
10324 : /*28228*/ OPC_RecordNode, // #7 = $glc
10325 : /*28229*/ OPC_MoveParent,
10326 : /*28230*/ OPC_MoveChild, 9,
10327 : /*28232*/ OPC_RecordNode, // #8 = $slc
10328 : /*28233*/ OPC_MoveParent,
10329 : /*28234*/ OPC_MoveChild, 10,
10330 : /*28236*/ OPC_RecordNode, // #9 = $tfe
10331 : /*28237*/ OPC_MoveParent,
10332 : /*28238*/ OPC_MoveChild, 11,
10333 : /*28240*/ OPC_RecordNode, // #10 = $lwe
10334 : /*28241*/ OPC_MoveParent,
10335 : /*28242*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10336 : /*28244*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10337 : /*28247*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10338 : /*28250*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10339 : /*28253*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10340 : /*28256*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10341 : /*28259*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10342 : /*28262*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10343 : /*28265*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10344 : /*28268*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V16), 0,
10345 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10346 : // Src: (intrinsic_wo_chain:v4f32 4838:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10347 : // Dst: (IMAGE_SAMPLE_C_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10348 : /*28286*/ 0, /*End of Scope*/
10349 : /*28287*/ /*Scope*/ 95|128,2/*351*/, /*->28640*/
10350 : /*28289*/ OPC_CheckChild0Integer, 111|128,37/*4847*/,
10351 : /*28292*/ OPC_RecordChild1, // #0 = $addr
10352 : /*28293*/ OPC_Scope, 68, /*->28363*/ // 5 children in Scope
10353 : /*28295*/ OPC_CheckChild1Type, MVT::i32,
10354 : /*28297*/ OPC_RecordChild2, // #1 = $rsrc
10355 : /*28298*/ OPC_RecordChild3, // #2 = $sampler
10356 : /*28299*/ OPC_RecordChild4, // #3 = $dmask
10357 : /*28300*/ OPC_RecordChild5, // #4 = $unorm
10358 : /*28301*/ OPC_RecordChild6, // #5 = $r128
10359 : /*28302*/ OPC_RecordChild7, // #6 = $da
10360 : /*28303*/ OPC_MoveChild, 8,
10361 : /*28305*/ OPC_RecordNode, // #7 = $glc
10362 : /*28306*/ OPC_MoveParent,
10363 : /*28307*/ OPC_MoveChild, 9,
10364 : /*28309*/ OPC_RecordNode, // #8 = $slc
10365 : /*28310*/ OPC_MoveParent,
10366 : /*28311*/ OPC_MoveChild, 10,
10367 : /*28313*/ OPC_RecordNode, // #9 = $tfe
10368 : /*28314*/ OPC_MoveParent,
10369 : /*28315*/ OPC_MoveChild, 11,
10370 : /*28317*/ OPC_RecordNode, // #10 = $lwe
10371 : /*28318*/ OPC_MoveParent,
10372 : /*28319*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10373 : /*28321*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10374 : /*28324*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10375 : /*28327*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10376 : /*28330*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10377 : /*28333*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10378 : /*28336*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10379 : /*28339*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10380 : /*28342*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10381 : /*28345*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CL_V4_V1), 0,
10382 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10383 : // Src: (intrinsic_wo_chain:v4f32 4847:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10384 : // Dst: (IMAGE_SAMPLE_C_CL_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10385 : /*28363*/ /*Scope*/ 68, /*->28432*/
10386 : /*28364*/ OPC_CheckChild1Type, MVT::v2i32,
10387 : /*28366*/ OPC_RecordChild2, // #1 = $rsrc
10388 : /*28367*/ OPC_RecordChild3, // #2 = $sampler
10389 : /*28368*/ OPC_RecordChild4, // #3 = $dmask
10390 : /*28369*/ OPC_RecordChild5, // #4 = $unorm
10391 : /*28370*/ OPC_RecordChild6, // #5 = $r128
10392 : /*28371*/ OPC_RecordChild7, // #6 = $da
10393 : /*28372*/ OPC_MoveChild, 8,
10394 : /*28374*/ OPC_RecordNode, // #7 = $glc
10395 : /*28375*/ OPC_MoveParent,
10396 : /*28376*/ OPC_MoveChild, 9,
10397 : /*28378*/ OPC_RecordNode, // #8 = $slc
10398 : /*28379*/ OPC_MoveParent,
10399 : /*28380*/ OPC_MoveChild, 10,
10400 : /*28382*/ OPC_RecordNode, // #9 = $tfe
10401 : /*28383*/ OPC_MoveParent,
10402 : /*28384*/ OPC_MoveChild, 11,
10403 : /*28386*/ OPC_RecordNode, // #10 = $lwe
10404 : /*28387*/ OPC_MoveParent,
10405 : /*28388*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10406 : /*28390*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10407 : /*28393*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10408 : /*28396*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10409 : /*28399*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10410 : /*28402*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10411 : /*28405*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10412 : /*28408*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10413 : /*28411*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10414 : /*28414*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2), 0,
10415 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10416 : // Src: (intrinsic_wo_chain:v4f32 4847:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10417 : // Dst: (IMAGE_SAMPLE_C_CL_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10418 : /*28432*/ /*Scope*/ 68, /*->28501*/
10419 : /*28433*/ OPC_CheckChild1Type, MVT::v4i32,
10420 : /*28435*/ OPC_RecordChild2, // #1 = $rsrc
10421 : /*28436*/ OPC_RecordChild3, // #2 = $sampler
10422 : /*28437*/ OPC_RecordChild4, // #3 = $dmask
10423 : /*28438*/ OPC_RecordChild5, // #4 = $unorm
10424 : /*28439*/ OPC_RecordChild6, // #5 = $r128
10425 : /*28440*/ OPC_RecordChild7, // #6 = $da
10426 : /*28441*/ OPC_MoveChild, 8,
10427 : /*28443*/ OPC_RecordNode, // #7 = $glc
10428 : /*28444*/ OPC_MoveParent,
10429 : /*28445*/ OPC_MoveChild, 9,
10430 : /*28447*/ OPC_RecordNode, // #8 = $slc
10431 : /*28448*/ OPC_MoveParent,
10432 : /*28449*/ OPC_MoveChild, 10,
10433 : /*28451*/ OPC_RecordNode, // #9 = $tfe
10434 : /*28452*/ OPC_MoveParent,
10435 : /*28453*/ OPC_MoveChild, 11,
10436 : /*28455*/ OPC_RecordNode, // #10 = $lwe
10437 : /*28456*/ OPC_MoveParent,
10438 : /*28457*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10439 : /*28459*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10440 : /*28462*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10441 : /*28465*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10442 : /*28468*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10443 : /*28471*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10444 : /*28474*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10445 : /*28477*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10446 : /*28480*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10447 : /*28483*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4), 0,
10448 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10449 : // Src: (intrinsic_wo_chain:v4f32 4847:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10450 : // Dst: (IMAGE_SAMPLE_C_CL_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10451 : /*28501*/ /*Scope*/ 68, /*->28570*/
10452 : /*28502*/ OPC_CheckChild1Type, MVT::v8i32,
10453 : /*28504*/ OPC_RecordChild2, // #1 = $rsrc
10454 : /*28505*/ OPC_RecordChild3, // #2 = $sampler
10455 : /*28506*/ OPC_RecordChild4, // #3 = $dmask
10456 : /*28507*/ OPC_RecordChild5, // #4 = $unorm
10457 : /*28508*/ OPC_RecordChild6, // #5 = $r128
10458 : /*28509*/ OPC_RecordChild7, // #6 = $da
10459 : /*28510*/ OPC_MoveChild, 8,
10460 : /*28512*/ OPC_RecordNode, // #7 = $glc
10461 : /*28513*/ OPC_MoveParent,
10462 : /*28514*/ OPC_MoveChild, 9,
10463 : /*28516*/ OPC_RecordNode, // #8 = $slc
10464 : /*28517*/ OPC_MoveParent,
10465 : /*28518*/ OPC_MoveChild, 10,
10466 : /*28520*/ OPC_RecordNode, // #9 = $tfe
10467 : /*28521*/ OPC_MoveParent,
10468 : /*28522*/ OPC_MoveChild, 11,
10469 : /*28524*/ OPC_RecordNode, // #10 = $lwe
10470 : /*28525*/ OPC_MoveParent,
10471 : /*28526*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10472 : /*28528*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10473 : /*28531*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10474 : /*28534*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10475 : /*28537*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10476 : /*28540*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10477 : /*28543*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10478 : /*28546*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10479 : /*28549*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10480 : /*28552*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8), 0,
10481 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10482 : // Src: (intrinsic_wo_chain:v4f32 4847:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10483 : // Dst: (IMAGE_SAMPLE_C_CL_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10484 : /*28570*/ /*Scope*/ 68, /*->28639*/
10485 : /*28571*/ OPC_CheckChild1Type, MVT::v16i32,
10486 : /*28573*/ OPC_RecordChild2, // #1 = $rsrc
10487 : /*28574*/ OPC_RecordChild3, // #2 = $sampler
10488 : /*28575*/ OPC_RecordChild4, // #3 = $dmask
10489 : /*28576*/ OPC_RecordChild5, // #4 = $unorm
10490 : /*28577*/ OPC_RecordChild6, // #5 = $r128
10491 : /*28578*/ OPC_RecordChild7, // #6 = $da
10492 : /*28579*/ OPC_MoveChild, 8,
10493 : /*28581*/ OPC_RecordNode, // #7 = $glc
10494 : /*28582*/ OPC_MoveParent,
10495 : /*28583*/ OPC_MoveChild, 9,
10496 : /*28585*/ OPC_RecordNode, // #8 = $slc
10497 : /*28586*/ OPC_MoveParent,
10498 : /*28587*/ OPC_MoveChild, 10,
10499 : /*28589*/ OPC_RecordNode, // #9 = $tfe
10500 : /*28590*/ OPC_MoveParent,
10501 : /*28591*/ OPC_MoveChild, 11,
10502 : /*28593*/ OPC_RecordNode, // #10 = $lwe
10503 : /*28594*/ OPC_MoveParent,
10504 : /*28595*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10505 : /*28597*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10506 : /*28600*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10507 : /*28603*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10508 : /*28606*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10509 : /*28609*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10510 : /*28612*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10511 : /*28615*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10512 : /*28618*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10513 : /*28621*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CL_V4_V16), 0,
10514 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10515 : // Src: (intrinsic_wo_chain:v4f32 4847:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10516 : // Dst: (IMAGE_SAMPLE_C_CL_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10517 : /*28639*/ 0, /*End of Scope*/
10518 : /*28640*/ /*Scope*/ 95|128,2/*351*/, /*->28993*/
10519 : /*28642*/ OPC_CheckChild0Integer, 113|128,37/*4849*/,
10520 : /*28645*/ OPC_RecordChild1, // #0 = $addr
10521 : /*28646*/ OPC_Scope, 68, /*->28716*/ // 5 children in Scope
10522 : /*28648*/ OPC_CheckChild1Type, MVT::i32,
10523 : /*28650*/ OPC_RecordChild2, // #1 = $rsrc
10524 : /*28651*/ OPC_RecordChild3, // #2 = $sampler
10525 : /*28652*/ OPC_RecordChild4, // #3 = $dmask
10526 : /*28653*/ OPC_RecordChild5, // #4 = $unorm
10527 : /*28654*/ OPC_RecordChild6, // #5 = $r128
10528 : /*28655*/ OPC_RecordChild7, // #6 = $da
10529 : /*28656*/ OPC_MoveChild, 8,
10530 : /*28658*/ OPC_RecordNode, // #7 = $glc
10531 : /*28659*/ OPC_MoveParent,
10532 : /*28660*/ OPC_MoveChild, 9,
10533 : /*28662*/ OPC_RecordNode, // #8 = $slc
10534 : /*28663*/ OPC_MoveParent,
10535 : /*28664*/ OPC_MoveChild, 10,
10536 : /*28666*/ OPC_RecordNode, // #9 = $tfe
10537 : /*28667*/ OPC_MoveParent,
10538 : /*28668*/ OPC_MoveChild, 11,
10539 : /*28670*/ OPC_RecordNode, // #10 = $lwe
10540 : /*28671*/ OPC_MoveParent,
10541 : /*28672*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10542 : /*28674*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10543 : /*28677*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10544 : /*28680*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10545 : /*28683*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10546 : /*28686*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10547 : /*28689*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10548 : /*28692*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10549 : /*28695*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10550 : /*28698*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V1), 0,
10551 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10552 : // Src: (intrinsic_wo_chain:v4f32 4849:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10553 : // Dst: (IMAGE_SAMPLE_C_D_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10554 : /*28716*/ /*Scope*/ 68, /*->28785*/
10555 : /*28717*/ OPC_CheckChild1Type, MVT::v2i32,
10556 : /*28719*/ OPC_RecordChild2, // #1 = $rsrc
10557 : /*28720*/ OPC_RecordChild3, // #2 = $sampler
10558 : /*28721*/ OPC_RecordChild4, // #3 = $dmask
10559 : /*28722*/ OPC_RecordChild5, // #4 = $unorm
10560 : /*28723*/ OPC_RecordChild6, // #5 = $r128
10561 : /*28724*/ OPC_RecordChild7, // #6 = $da
10562 : /*28725*/ OPC_MoveChild, 8,
10563 : /*28727*/ OPC_RecordNode, // #7 = $glc
10564 : /*28728*/ OPC_MoveParent,
10565 : /*28729*/ OPC_MoveChild, 9,
10566 : /*28731*/ OPC_RecordNode, // #8 = $slc
10567 : /*28732*/ OPC_MoveParent,
10568 : /*28733*/ OPC_MoveChild, 10,
10569 : /*28735*/ OPC_RecordNode, // #9 = $tfe
10570 : /*28736*/ OPC_MoveParent,
10571 : /*28737*/ OPC_MoveChild, 11,
10572 : /*28739*/ OPC_RecordNode, // #10 = $lwe
10573 : /*28740*/ OPC_MoveParent,
10574 : /*28741*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10575 : /*28743*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10576 : /*28746*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10577 : /*28749*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10578 : /*28752*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10579 : /*28755*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10580 : /*28758*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10581 : /*28761*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10582 : /*28764*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10583 : /*28767*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V2), 0,
10584 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10585 : // Src: (intrinsic_wo_chain:v4f32 4849:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10586 : // Dst: (IMAGE_SAMPLE_C_D_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10587 : /*28785*/ /*Scope*/ 68, /*->28854*/
10588 : /*28786*/ OPC_CheckChild1Type, MVT::v4i32,
10589 : /*28788*/ OPC_RecordChild2, // #1 = $rsrc
10590 : /*28789*/ OPC_RecordChild3, // #2 = $sampler
10591 : /*28790*/ OPC_RecordChild4, // #3 = $dmask
10592 : /*28791*/ OPC_RecordChild5, // #4 = $unorm
10593 : /*28792*/ OPC_RecordChild6, // #5 = $r128
10594 : /*28793*/ OPC_RecordChild7, // #6 = $da
10595 : /*28794*/ OPC_MoveChild, 8,
10596 : /*28796*/ OPC_RecordNode, // #7 = $glc
10597 : /*28797*/ OPC_MoveParent,
10598 : /*28798*/ OPC_MoveChild, 9,
10599 : /*28800*/ OPC_RecordNode, // #8 = $slc
10600 : /*28801*/ OPC_MoveParent,
10601 : /*28802*/ OPC_MoveChild, 10,
10602 : /*28804*/ OPC_RecordNode, // #9 = $tfe
10603 : /*28805*/ OPC_MoveParent,
10604 : /*28806*/ OPC_MoveChild, 11,
10605 : /*28808*/ OPC_RecordNode, // #10 = $lwe
10606 : /*28809*/ OPC_MoveParent,
10607 : /*28810*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10608 : /*28812*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10609 : /*28815*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10610 : /*28818*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10611 : /*28821*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10612 : /*28824*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10613 : /*28827*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10614 : /*28830*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10615 : /*28833*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10616 : /*28836*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V4), 0,
10617 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10618 : // Src: (intrinsic_wo_chain:v4f32 4849:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10619 : // Dst: (IMAGE_SAMPLE_C_D_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10620 : /*28854*/ /*Scope*/ 68, /*->28923*/
10621 : /*28855*/ OPC_CheckChild1Type, MVT::v8i32,
10622 : /*28857*/ OPC_RecordChild2, // #1 = $rsrc
10623 : /*28858*/ OPC_RecordChild3, // #2 = $sampler
10624 : /*28859*/ OPC_RecordChild4, // #3 = $dmask
10625 : /*28860*/ OPC_RecordChild5, // #4 = $unorm
10626 : /*28861*/ OPC_RecordChild6, // #5 = $r128
10627 : /*28862*/ OPC_RecordChild7, // #6 = $da
10628 : /*28863*/ OPC_MoveChild, 8,
10629 : /*28865*/ OPC_RecordNode, // #7 = $glc
10630 : /*28866*/ OPC_MoveParent,
10631 : /*28867*/ OPC_MoveChild, 9,
10632 : /*28869*/ OPC_RecordNode, // #8 = $slc
10633 : /*28870*/ OPC_MoveParent,
10634 : /*28871*/ OPC_MoveChild, 10,
10635 : /*28873*/ OPC_RecordNode, // #9 = $tfe
10636 : /*28874*/ OPC_MoveParent,
10637 : /*28875*/ OPC_MoveChild, 11,
10638 : /*28877*/ OPC_RecordNode, // #10 = $lwe
10639 : /*28878*/ OPC_MoveParent,
10640 : /*28879*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10641 : /*28881*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10642 : /*28884*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10643 : /*28887*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10644 : /*28890*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10645 : /*28893*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10646 : /*28896*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10647 : /*28899*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10648 : /*28902*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10649 : /*28905*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V8), 0,
10650 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10651 : // Src: (intrinsic_wo_chain:v4f32 4849:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10652 : // Dst: (IMAGE_SAMPLE_C_D_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10653 : /*28923*/ /*Scope*/ 68, /*->28992*/
10654 : /*28924*/ OPC_CheckChild1Type, MVT::v16i32,
10655 : /*28926*/ OPC_RecordChild2, // #1 = $rsrc
10656 : /*28927*/ OPC_RecordChild3, // #2 = $sampler
10657 : /*28928*/ OPC_RecordChild4, // #3 = $dmask
10658 : /*28929*/ OPC_RecordChild5, // #4 = $unorm
10659 : /*28930*/ OPC_RecordChild6, // #5 = $r128
10660 : /*28931*/ OPC_RecordChild7, // #6 = $da
10661 : /*28932*/ OPC_MoveChild, 8,
10662 : /*28934*/ OPC_RecordNode, // #7 = $glc
10663 : /*28935*/ OPC_MoveParent,
10664 : /*28936*/ OPC_MoveChild, 9,
10665 : /*28938*/ OPC_RecordNode, // #8 = $slc
10666 : /*28939*/ OPC_MoveParent,
10667 : /*28940*/ OPC_MoveChild, 10,
10668 : /*28942*/ OPC_RecordNode, // #9 = $tfe
10669 : /*28943*/ OPC_MoveParent,
10670 : /*28944*/ OPC_MoveChild, 11,
10671 : /*28946*/ OPC_RecordNode, // #10 = $lwe
10672 : /*28947*/ OPC_MoveParent,
10673 : /*28948*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10674 : /*28950*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10675 : /*28953*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10676 : /*28956*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10677 : /*28959*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10678 : /*28962*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10679 : /*28965*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10680 : /*28968*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10681 : /*28971*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10682 : /*28974*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V16), 0,
10683 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10684 : // Src: (intrinsic_wo_chain:v4f32 4849:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10685 : // Dst: (IMAGE_SAMPLE_C_D_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10686 : /*28992*/ 0, /*End of Scope*/
10687 : /*28993*/ /*Scope*/ 95|128,2/*351*/, /*->29346*/
10688 : /*28995*/ OPC_CheckChild0Integer, 114|128,37/*4850*/,
10689 : /*28998*/ OPC_RecordChild1, // #0 = $addr
10690 : /*28999*/ OPC_Scope, 68, /*->29069*/ // 5 children in Scope
10691 : /*29001*/ OPC_CheckChild1Type, MVT::i32,
10692 : /*29003*/ OPC_RecordChild2, // #1 = $rsrc
10693 : /*29004*/ OPC_RecordChild3, // #2 = $sampler
10694 : /*29005*/ OPC_RecordChild4, // #3 = $dmask
10695 : /*29006*/ OPC_RecordChild5, // #4 = $unorm
10696 : /*29007*/ OPC_RecordChild6, // #5 = $r128
10697 : /*29008*/ OPC_RecordChild7, // #6 = $da
10698 : /*29009*/ OPC_MoveChild, 8,
10699 : /*29011*/ OPC_RecordNode, // #7 = $glc
10700 : /*29012*/ OPC_MoveParent,
10701 : /*29013*/ OPC_MoveChild, 9,
10702 : /*29015*/ OPC_RecordNode, // #8 = $slc
10703 : /*29016*/ OPC_MoveParent,
10704 : /*29017*/ OPC_MoveChild, 10,
10705 : /*29019*/ OPC_RecordNode, // #9 = $tfe
10706 : /*29020*/ OPC_MoveParent,
10707 : /*29021*/ OPC_MoveChild, 11,
10708 : /*29023*/ OPC_RecordNode, // #10 = $lwe
10709 : /*29024*/ OPC_MoveParent,
10710 : /*29025*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10711 : /*29027*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10712 : /*29030*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10713 : /*29033*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10714 : /*29036*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10715 : /*29039*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10716 : /*29042*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10717 : /*29045*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10718 : /*29048*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10719 : /*29051*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V1), 0,
10720 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10721 : // Src: (intrinsic_wo_chain:v4f32 4850:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10722 : // Dst: (IMAGE_SAMPLE_C_D_CL_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10723 : /*29069*/ /*Scope*/ 68, /*->29138*/
10724 : /*29070*/ OPC_CheckChild1Type, MVT::v2i32,
10725 : /*29072*/ OPC_RecordChild2, // #1 = $rsrc
10726 : /*29073*/ OPC_RecordChild3, // #2 = $sampler
10727 : /*29074*/ OPC_RecordChild4, // #3 = $dmask
10728 : /*29075*/ OPC_RecordChild5, // #4 = $unorm
10729 : /*29076*/ OPC_RecordChild6, // #5 = $r128
10730 : /*29077*/ OPC_RecordChild7, // #6 = $da
10731 : /*29078*/ OPC_MoveChild, 8,
10732 : /*29080*/ OPC_RecordNode, // #7 = $glc
10733 : /*29081*/ OPC_MoveParent,
10734 : /*29082*/ OPC_MoveChild, 9,
10735 : /*29084*/ OPC_RecordNode, // #8 = $slc
10736 : /*29085*/ OPC_MoveParent,
10737 : /*29086*/ OPC_MoveChild, 10,
10738 : /*29088*/ OPC_RecordNode, // #9 = $tfe
10739 : /*29089*/ OPC_MoveParent,
10740 : /*29090*/ OPC_MoveChild, 11,
10741 : /*29092*/ OPC_RecordNode, // #10 = $lwe
10742 : /*29093*/ OPC_MoveParent,
10743 : /*29094*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10744 : /*29096*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10745 : /*29099*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10746 : /*29102*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10747 : /*29105*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10748 : /*29108*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10749 : /*29111*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10750 : /*29114*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10751 : /*29117*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10752 : /*29120*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V2), 0,
10753 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10754 : // Src: (intrinsic_wo_chain:v4f32 4850:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10755 : // Dst: (IMAGE_SAMPLE_C_D_CL_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10756 : /*29138*/ /*Scope*/ 68, /*->29207*/
10757 : /*29139*/ OPC_CheckChild1Type, MVT::v4i32,
10758 : /*29141*/ OPC_RecordChild2, // #1 = $rsrc
10759 : /*29142*/ OPC_RecordChild3, // #2 = $sampler
10760 : /*29143*/ OPC_RecordChild4, // #3 = $dmask
10761 : /*29144*/ OPC_RecordChild5, // #4 = $unorm
10762 : /*29145*/ OPC_RecordChild6, // #5 = $r128
10763 : /*29146*/ OPC_RecordChild7, // #6 = $da
10764 : /*29147*/ OPC_MoveChild, 8,
10765 : /*29149*/ OPC_RecordNode, // #7 = $glc
10766 : /*29150*/ OPC_MoveParent,
10767 : /*29151*/ OPC_MoveChild, 9,
10768 : /*29153*/ OPC_RecordNode, // #8 = $slc
10769 : /*29154*/ OPC_MoveParent,
10770 : /*29155*/ OPC_MoveChild, 10,
10771 : /*29157*/ OPC_RecordNode, // #9 = $tfe
10772 : /*29158*/ OPC_MoveParent,
10773 : /*29159*/ OPC_MoveChild, 11,
10774 : /*29161*/ OPC_RecordNode, // #10 = $lwe
10775 : /*29162*/ OPC_MoveParent,
10776 : /*29163*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10777 : /*29165*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10778 : /*29168*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10779 : /*29171*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10780 : /*29174*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10781 : /*29177*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10782 : /*29180*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10783 : /*29183*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10784 : /*29186*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10785 : /*29189*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4), 0,
10786 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10787 : // Src: (intrinsic_wo_chain:v4f32 4850:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10788 : // Dst: (IMAGE_SAMPLE_C_D_CL_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10789 : /*29207*/ /*Scope*/ 68, /*->29276*/
10790 : /*29208*/ OPC_CheckChild1Type, MVT::v8i32,
10791 : /*29210*/ OPC_RecordChild2, // #1 = $rsrc
10792 : /*29211*/ OPC_RecordChild3, // #2 = $sampler
10793 : /*29212*/ OPC_RecordChild4, // #3 = $dmask
10794 : /*29213*/ OPC_RecordChild5, // #4 = $unorm
10795 : /*29214*/ OPC_RecordChild6, // #5 = $r128
10796 : /*29215*/ OPC_RecordChild7, // #6 = $da
10797 : /*29216*/ OPC_MoveChild, 8,
10798 : /*29218*/ OPC_RecordNode, // #7 = $glc
10799 : /*29219*/ OPC_MoveParent,
10800 : /*29220*/ OPC_MoveChild, 9,
10801 : /*29222*/ OPC_RecordNode, // #8 = $slc
10802 : /*29223*/ OPC_MoveParent,
10803 : /*29224*/ OPC_MoveChild, 10,
10804 : /*29226*/ OPC_RecordNode, // #9 = $tfe
10805 : /*29227*/ OPC_MoveParent,
10806 : /*29228*/ OPC_MoveChild, 11,
10807 : /*29230*/ OPC_RecordNode, // #10 = $lwe
10808 : /*29231*/ OPC_MoveParent,
10809 : /*29232*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10810 : /*29234*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10811 : /*29237*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10812 : /*29240*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10813 : /*29243*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10814 : /*29246*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10815 : /*29249*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10816 : /*29252*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10817 : /*29255*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10818 : /*29258*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8), 0,
10819 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10820 : // Src: (intrinsic_wo_chain:v4f32 4850:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10821 : // Dst: (IMAGE_SAMPLE_C_D_CL_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10822 : /*29276*/ /*Scope*/ 68, /*->29345*/
10823 : /*29277*/ OPC_CheckChild1Type, MVT::v16i32,
10824 : /*29279*/ OPC_RecordChild2, // #1 = $rsrc
10825 : /*29280*/ OPC_RecordChild3, // #2 = $sampler
10826 : /*29281*/ OPC_RecordChild4, // #3 = $dmask
10827 : /*29282*/ OPC_RecordChild5, // #4 = $unorm
10828 : /*29283*/ OPC_RecordChild6, // #5 = $r128
10829 : /*29284*/ OPC_RecordChild7, // #6 = $da
10830 : /*29285*/ OPC_MoveChild, 8,
10831 : /*29287*/ OPC_RecordNode, // #7 = $glc
10832 : /*29288*/ OPC_MoveParent,
10833 : /*29289*/ OPC_MoveChild, 9,
10834 : /*29291*/ OPC_RecordNode, // #8 = $slc
10835 : /*29292*/ OPC_MoveParent,
10836 : /*29293*/ OPC_MoveChild, 10,
10837 : /*29295*/ OPC_RecordNode, // #9 = $tfe
10838 : /*29296*/ OPC_MoveParent,
10839 : /*29297*/ OPC_MoveChild, 11,
10840 : /*29299*/ OPC_RecordNode, // #10 = $lwe
10841 : /*29300*/ OPC_MoveParent,
10842 : /*29301*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10843 : /*29303*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10844 : /*29306*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10845 : /*29309*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10846 : /*29312*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10847 : /*29315*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10848 : /*29318*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10849 : /*29321*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10850 : /*29324*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10851 : /*29327*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V16), 0,
10852 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10853 : // Src: (intrinsic_wo_chain:v4f32 4850:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10854 : // Dst: (IMAGE_SAMPLE_C_D_CL_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10855 : /*29345*/ 0, /*End of Scope*/
10856 : /*29346*/ /*Scope*/ 95|128,2/*351*/, /*->29699*/
10857 : /*29348*/ OPC_CheckChild0Integer, 117|128,37/*4853*/,
10858 : /*29351*/ OPC_RecordChild1, // #0 = $addr
10859 : /*29352*/ OPC_Scope, 68, /*->29422*/ // 5 children in Scope
10860 : /*29354*/ OPC_CheckChild1Type, MVT::i32,
10861 : /*29356*/ OPC_RecordChild2, // #1 = $rsrc
10862 : /*29357*/ OPC_RecordChild3, // #2 = $sampler
10863 : /*29358*/ OPC_RecordChild4, // #3 = $dmask
10864 : /*29359*/ OPC_RecordChild5, // #4 = $unorm
10865 : /*29360*/ OPC_RecordChild6, // #5 = $r128
10866 : /*29361*/ OPC_RecordChild7, // #6 = $da
10867 : /*29362*/ OPC_MoveChild, 8,
10868 : /*29364*/ OPC_RecordNode, // #7 = $glc
10869 : /*29365*/ OPC_MoveParent,
10870 : /*29366*/ OPC_MoveChild, 9,
10871 : /*29368*/ OPC_RecordNode, // #8 = $slc
10872 : /*29369*/ OPC_MoveParent,
10873 : /*29370*/ OPC_MoveChild, 10,
10874 : /*29372*/ OPC_RecordNode, // #9 = $tfe
10875 : /*29373*/ OPC_MoveParent,
10876 : /*29374*/ OPC_MoveChild, 11,
10877 : /*29376*/ OPC_RecordNode, // #10 = $lwe
10878 : /*29377*/ OPC_MoveParent,
10879 : /*29378*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10880 : /*29380*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10881 : /*29383*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10882 : /*29386*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10883 : /*29389*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10884 : /*29392*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10885 : /*29395*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10886 : /*29398*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10887 : /*29401*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10888 : /*29404*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V1), 0,
10889 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10890 : // Src: (intrinsic_wo_chain:v4f32 4853:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10891 : // Dst: (IMAGE_SAMPLE_C_L_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10892 : /*29422*/ /*Scope*/ 68, /*->29491*/
10893 : /*29423*/ OPC_CheckChild1Type, MVT::v2i32,
10894 : /*29425*/ OPC_RecordChild2, // #1 = $rsrc
10895 : /*29426*/ OPC_RecordChild3, // #2 = $sampler
10896 : /*29427*/ OPC_RecordChild4, // #3 = $dmask
10897 : /*29428*/ OPC_RecordChild5, // #4 = $unorm
10898 : /*29429*/ OPC_RecordChild6, // #5 = $r128
10899 : /*29430*/ OPC_RecordChild7, // #6 = $da
10900 : /*29431*/ OPC_MoveChild, 8,
10901 : /*29433*/ OPC_RecordNode, // #7 = $glc
10902 : /*29434*/ OPC_MoveParent,
10903 : /*29435*/ OPC_MoveChild, 9,
10904 : /*29437*/ OPC_RecordNode, // #8 = $slc
10905 : /*29438*/ OPC_MoveParent,
10906 : /*29439*/ OPC_MoveChild, 10,
10907 : /*29441*/ OPC_RecordNode, // #9 = $tfe
10908 : /*29442*/ OPC_MoveParent,
10909 : /*29443*/ OPC_MoveChild, 11,
10910 : /*29445*/ OPC_RecordNode, // #10 = $lwe
10911 : /*29446*/ OPC_MoveParent,
10912 : /*29447*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10913 : /*29449*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10914 : /*29452*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10915 : /*29455*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10916 : /*29458*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10917 : /*29461*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10918 : /*29464*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10919 : /*29467*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10920 : /*29470*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10921 : /*29473*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V2), 0,
10922 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10923 : // Src: (intrinsic_wo_chain:v4f32 4853:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10924 : // Dst: (IMAGE_SAMPLE_C_L_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10925 : /*29491*/ /*Scope*/ 68, /*->29560*/
10926 : /*29492*/ OPC_CheckChild1Type, MVT::v4i32,
10927 : /*29494*/ OPC_RecordChild2, // #1 = $rsrc
10928 : /*29495*/ OPC_RecordChild3, // #2 = $sampler
10929 : /*29496*/ OPC_RecordChild4, // #3 = $dmask
10930 : /*29497*/ OPC_RecordChild5, // #4 = $unorm
10931 : /*29498*/ OPC_RecordChild6, // #5 = $r128
10932 : /*29499*/ OPC_RecordChild7, // #6 = $da
10933 : /*29500*/ OPC_MoveChild, 8,
10934 : /*29502*/ OPC_RecordNode, // #7 = $glc
10935 : /*29503*/ OPC_MoveParent,
10936 : /*29504*/ OPC_MoveChild, 9,
10937 : /*29506*/ OPC_RecordNode, // #8 = $slc
10938 : /*29507*/ OPC_MoveParent,
10939 : /*29508*/ OPC_MoveChild, 10,
10940 : /*29510*/ OPC_RecordNode, // #9 = $tfe
10941 : /*29511*/ OPC_MoveParent,
10942 : /*29512*/ OPC_MoveChild, 11,
10943 : /*29514*/ OPC_RecordNode, // #10 = $lwe
10944 : /*29515*/ OPC_MoveParent,
10945 : /*29516*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10946 : /*29518*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10947 : /*29521*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10948 : /*29524*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10949 : /*29527*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10950 : /*29530*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10951 : /*29533*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10952 : /*29536*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10953 : /*29539*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10954 : /*29542*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V4), 0,
10955 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10956 : // Src: (intrinsic_wo_chain:v4f32 4853:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10957 : // Dst: (IMAGE_SAMPLE_C_L_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10958 : /*29560*/ /*Scope*/ 68, /*->29629*/
10959 : /*29561*/ OPC_CheckChild1Type, MVT::v8i32,
10960 : /*29563*/ OPC_RecordChild2, // #1 = $rsrc
10961 : /*29564*/ OPC_RecordChild3, // #2 = $sampler
10962 : /*29565*/ OPC_RecordChild4, // #3 = $dmask
10963 : /*29566*/ OPC_RecordChild5, // #4 = $unorm
10964 : /*29567*/ OPC_RecordChild6, // #5 = $r128
10965 : /*29568*/ OPC_RecordChild7, // #6 = $da
10966 : /*29569*/ OPC_MoveChild, 8,
10967 : /*29571*/ OPC_RecordNode, // #7 = $glc
10968 : /*29572*/ OPC_MoveParent,
10969 : /*29573*/ OPC_MoveChild, 9,
10970 : /*29575*/ OPC_RecordNode, // #8 = $slc
10971 : /*29576*/ OPC_MoveParent,
10972 : /*29577*/ OPC_MoveChild, 10,
10973 : /*29579*/ OPC_RecordNode, // #9 = $tfe
10974 : /*29580*/ OPC_MoveParent,
10975 : /*29581*/ OPC_MoveChild, 11,
10976 : /*29583*/ OPC_RecordNode, // #10 = $lwe
10977 : /*29584*/ OPC_MoveParent,
10978 : /*29585*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
10979 : /*29587*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
10980 : /*29590*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
10981 : /*29593*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
10982 : /*29596*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
10983 : /*29599*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
10984 : /*29602*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
10985 : /*29605*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
10986 : /*29608*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
10987 : /*29611*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V8), 0,
10988 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
10989 : // Src: (intrinsic_wo_chain:v4f32 4853:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
10990 : // Dst: (IMAGE_SAMPLE_C_L_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
10991 : /*29629*/ /*Scope*/ 68, /*->29698*/
10992 : /*29630*/ OPC_CheckChild1Type, MVT::v16i32,
10993 : /*29632*/ OPC_RecordChild2, // #1 = $rsrc
10994 : /*29633*/ OPC_RecordChild3, // #2 = $sampler
10995 : /*29634*/ OPC_RecordChild4, // #3 = $dmask
10996 : /*29635*/ OPC_RecordChild5, // #4 = $unorm
10997 : /*29636*/ OPC_RecordChild6, // #5 = $r128
10998 : /*29637*/ OPC_RecordChild7, // #6 = $da
10999 : /*29638*/ OPC_MoveChild, 8,
11000 : /*29640*/ OPC_RecordNode, // #7 = $glc
11001 : /*29641*/ OPC_MoveParent,
11002 : /*29642*/ OPC_MoveChild, 9,
11003 : /*29644*/ OPC_RecordNode, // #8 = $slc
11004 : /*29645*/ OPC_MoveParent,
11005 : /*29646*/ OPC_MoveChild, 10,
11006 : /*29648*/ OPC_RecordNode, // #9 = $tfe
11007 : /*29649*/ OPC_MoveParent,
11008 : /*29650*/ OPC_MoveChild, 11,
11009 : /*29652*/ OPC_RecordNode, // #10 = $lwe
11010 : /*29653*/ OPC_MoveParent,
11011 : /*29654*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11012 : /*29656*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11013 : /*29659*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11014 : /*29662*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11015 : /*29665*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11016 : /*29668*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11017 : /*29671*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11018 : /*29674*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11019 : /*29677*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11020 : /*29680*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V16), 0,
11021 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11022 : // Src: (intrinsic_wo_chain:v4f32 4853:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11023 : // Dst: (IMAGE_SAMPLE_C_L_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11024 : /*29698*/ 0, /*End of Scope*/
11025 : /*29699*/ /*Scope*/ 95|128,2/*351*/, /*->30052*/
11026 : /*29701*/ OPC_CheckChild0Integer, 103|128,37/*4839*/,
11027 : /*29704*/ OPC_RecordChild1, // #0 = $addr
11028 : /*29705*/ OPC_Scope, 68, /*->29775*/ // 5 children in Scope
11029 : /*29707*/ OPC_CheckChild1Type, MVT::i32,
11030 : /*29709*/ OPC_RecordChild2, // #1 = $rsrc
11031 : /*29710*/ OPC_RecordChild3, // #2 = $sampler
11032 : /*29711*/ OPC_RecordChild4, // #3 = $dmask
11033 : /*29712*/ OPC_RecordChild5, // #4 = $unorm
11034 : /*29713*/ OPC_RecordChild6, // #5 = $r128
11035 : /*29714*/ OPC_RecordChild7, // #6 = $da
11036 : /*29715*/ OPC_MoveChild, 8,
11037 : /*29717*/ OPC_RecordNode, // #7 = $glc
11038 : /*29718*/ OPC_MoveParent,
11039 : /*29719*/ OPC_MoveChild, 9,
11040 : /*29721*/ OPC_RecordNode, // #8 = $slc
11041 : /*29722*/ OPC_MoveParent,
11042 : /*29723*/ OPC_MoveChild, 10,
11043 : /*29725*/ OPC_RecordNode, // #9 = $tfe
11044 : /*29726*/ OPC_MoveParent,
11045 : /*29727*/ OPC_MoveChild, 11,
11046 : /*29729*/ OPC_RecordNode, // #10 = $lwe
11047 : /*29730*/ OPC_MoveParent,
11048 : /*29731*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11049 : /*29733*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11050 : /*29736*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11051 : /*29739*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11052 : /*29742*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11053 : /*29745*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11054 : /*29748*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11055 : /*29751*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11056 : /*29754*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11057 : /*29757*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V1), 0,
11058 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11059 : // Src: (intrinsic_wo_chain:v4f32 4839:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11060 : // Dst: (IMAGE_SAMPLE_C_B_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11061 : /*29775*/ /*Scope*/ 68, /*->29844*/
11062 : /*29776*/ OPC_CheckChild1Type, MVT::v2i32,
11063 : /*29778*/ OPC_RecordChild2, // #1 = $rsrc
11064 : /*29779*/ OPC_RecordChild3, // #2 = $sampler
11065 : /*29780*/ OPC_RecordChild4, // #3 = $dmask
11066 : /*29781*/ OPC_RecordChild5, // #4 = $unorm
11067 : /*29782*/ OPC_RecordChild6, // #5 = $r128
11068 : /*29783*/ OPC_RecordChild7, // #6 = $da
11069 : /*29784*/ OPC_MoveChild, 8,
11070 : /*29786*/ OPC_RecordNode, // #7 = $glc
11071 : /*29787*/ OPC_MoveParent,
11072 : /*29788*/ OPC_MoveChild, 9,
11073 : /*29790*/ OPC_RecordNode, // #8 = $slc
11074 : /*29791*/ OPC_MoveParent,
11075 : /*29792*/ OPC_MoveChild, 10,
11076 : /*29794*/ OPC_RecordNode, // #9 = $tfe
11077 : /*29795*/ OPC_MoveParent,
11078 : /*29796*/ OPC_MoveChild, 11,
11079 : /*29798*/ OPC_RecordNode, // #10 = $lwe
11080 : /*29799*/ OPC_MoveParent,
11081 : /*29800*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11082 : /*29802*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11083 : /*29805*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11084 : /*29808*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11085 : /*29811*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11086 : /*29814*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11087 : /*29817*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11088 : /*29820*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11089 : /*29823*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11090 : /*29826*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V2), 0,
11091 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11092 : // Src: (intrinsic_wo_chain:v4f32 4839:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11093 : // Dst: (IMAGE_SAMPLE_C_B_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11094 : /*29844*/ /*Scope*/ 68, /*->29913*/
11095 : /*29845*/ OPC_CheckChild1Type, MVT::v4i32,
11096 : /*29847*/ OPC_RecordChild2, // #1 = $rsrc
11097 : /*29848*/ OPC_RecordChild3, // #2 = $sampler
11098 : /*29849*/ OPC_RecordChild4, // #3 = $dmask
11099 : /*29850*/ OPC_RecordChild5, // #4 = $unorm
11100 : /*29851*/ OPC_RecordChild6, // #5 = $r128
11101 : /*29852*/ OPC_RecordChild7, // #6 = $da
11102 : /*29853*/ OPC_MoveChild, 8,
11103 : /*29855*/ OPC_RecordNode, // #7 = $glc
11104 : /*29856*/ OPC_MoveParent,
11105 : /*29857*/ OPC_MoveChild, 9,
11106 : /*29859*/ OPC_RecordNode, // #8 = $slc
11107 : /*29860*/ OPC_MoveParent,
11108 : /*29861*/ OPC_MoveChild, 10,
11109 : /*29863*/ OPC_RecordNode, // #9 = $tfe
11110 : /*29864*/ OPC_MoveParent,
11111 : /*29865*/ OPC_MoveChild, 11,
11112 : /*29867*/ OPC_RecordNode, // #10 = $lwe
11113 : /*29868*/ OPC_MoveParent,
11114 : /*29869*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11115 : /*29871*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11116 : /*29874*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11117 : /*29877*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11118 : /*29880*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11119 : /*29883*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11120 : /*29886*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11121 : /*29889*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11122 : /*29892*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11123 : /*29895*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V4), 0,
11124 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11125 : // Src: (intrinsic_wo_chain:v4f32 4839:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11126 : // Dst: (IMAGE_SAMPLE_C_B_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11127 : /*29913*/ /*Scope*/ 68, /*->29982*/
11128 : /*29914*/ OPC_CheckChild1Type, MVT::v8i32,
11129 : /*29916*/ OPC_RecordChild2, // #1 = $rsrc
11130 : /*29917*/ OPC_RecordChild3, // #2 = $sampler
11131 : /*29918*/ OPC_RecordChild4, // #3 = $dmask
11132 : /*29919*/ OPC_RecordChild5, // #4 = $unorm
11133 : /*29920*/ OPC_RecordChild6, // #5 = $r128
11134 : /*29921*/ OPC_RecordChild7, // #6 = $da
11135 : /*29922*/ OPC_MoveChild, 8,
11136 : /*29924*/ OPC_RecordNode, // #7 = $glc
11137 : /*29925*/ OPC_MoveParent,
11138 : /*29926*/ OPC_MoveChild, 9,
11139 : /*29928*/ OPC_RecordNode, // #8 = $slc
11140 : /*29929*/ OPC_MoveParent,
11141 : /*29930*/ OPC_MoveChild, 10,
11142 : /*29932*/ OPC_RecordNode, // #9 = $tfe
11143 : /*29933*/ OPC_MoveParent,
11144 : /*29934*/ OPC_MoveChild, 11,
11145 : /*29936*/ OPC_RecordNode, // #10 = $lwe
11146 : /*29937*/ OPC_MoveParent,
11147 : /*29938*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11148 : /*29940*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11149 : /*29943*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11150 : /*29946*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11151 : /*29949*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11152 : /*29952*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11153 : /*29955*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11154 : /*29958*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11155 : /*29961*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11156 : /*29964*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V8), 0,
11157 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11158 : // Src: (intrinsic_wo_chain:v4f32 4839:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11159 : // Dst: (IMAGE_SAMPLE_C_B_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11160 : /*29982*/ /*Scope*/ 68, /*->30051*/
11161 : /*29983*/ OPC_CheckChild1Type, MVT::v16i32,
11162 : /*29985*/ OPC_RecordChild2, // #1 = $rsrc
11163 : /*29986*/ OPC_RecordChild3, // #2 = $sampler
11164 : /*29987*/ OPC_RecordChild4, // #3 = $dmask
11165 : /*29988*/ OPC_RecordChild5, // #4 = $unorm
11166 : /*29989*/ OPC_RecordChild6, // #5 = $r128
11167 : /*29990*/ OPC_RecordChild7, // #6 = $da
11168 : /*29991*/ OPC_MoveChild, 8,
11169 : /*29993*/ OPC_RecordNode, // #7 = $glc
11170 : /*29994*/ OPC_MoveParent,
11171 : /*29995*/ OPC_MoveChild, 9,
11172 : /*29997*/ OPC_RecordNode, // #8 = $slc
11173 : /*29998*/ OPC_MoveParent,
11174 : /*29999*/ OPC_MoveChild, 10,
11175 : /*30001*/ OPC_RecordNode, // #9 = $tfe
11176 : /*30002*/ OPC_MoveParent,
11177 : /*30003*/ OPC_MoveChild, 11,
11178 : /*30005*/ OPC_RecordNode, // #10 = $lwe
11179 : /*30006*/ OPC_MoveParent,
11180 : /*30007*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11181 : /*30009*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11182 : /*30012*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11183 : /*30015*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11184 : /*30018*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11185 : /*30021*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11186 : /*30024*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11187 : /*30027*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11188 : /*30030*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11189 : /*30033*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V16), 0,
11190 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11191 : // Src: (intrinsic_wo_chain:v4f32 4839:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11192 : // Dst: (IMAGE_SAMPLE_C_B_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11193 : /*30051*/ 0, /*End of Scope*/
11194 : /*30052*/ /*Scope*/ 95|128,2/*351*/, /*->30405*/
11195 : /*30054*/ OPC_CheckChild0Integer, 104|128,37/*4840*/,
11196 : /*30057*/ OPC_RecordChild1, // #0 = $addr
11197 : /*30058*/ OPC_Scope, 68, /*->30128*/ // 5 children in Scope
11198 : /*30060*/ OPC_CheckChild1Type, MVT::i32,
11199 : /*30062*/ OPC_RecordChild2, // #1 = $rsrc
11200 : /*30063*/ OPC_RecordChild3, // #2 = $sampler
11201 : /*30064*/ OPC_RecordChild4, // #3 = $dmask
11202 : /*30065*/ OPC_RecordChild5, // #4 = $unorm
11203 : /*30066*/ OPC_RecordChild6, // #5 = $r128
11204 : /*30067*/ OPC_RecordChild7, // #6 = $da
11205 : /*30068*/ OPC_MoveChild, 8,
11206 : /*30070*/ OPC_RecordNode, // #7 = $glc
11207 : /*30071*/ OPC_MoveParent,
11208 : /*30072*/ OPC_MoveChild, 9,
11209 : /*30074*/ OPC_RecordNode, // #8 = $slc
11210 : /*30075*/ OPC_MoveParent,
11211 : /*30076*/ OPC_MoveChild, 10,
11212 : /*30078*/ OPC_RecordNode, // #9 = $tfe
11213 : /*30079*/ OPC_MoveParent,
11214 : /*30080*/ OPC_MoveChild, 11,
11215 : /*30082*/ OPC_RecordNode, // #10 = $lwe
11216 : /*30083*/ OPC_MoveParent,
11217 : /*30084*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11218 : /*30086*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11219 : /*30089*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11220 : /*30092*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11221 : /*30095*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11222 : /*30098*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11223 : /*30101*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11224 : /*30104*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11225 : /*30107*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11226 : /*30110*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V1), 0,
11227 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11228 : // Src: (intrinsic_wo_chain:v4f32 4840:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11229 : // Dst: (IMAGE_SAMPLE_C_B_CL_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11230 : /*30128*/ /*Scope*/ 68, /*->30197*/
11231 : /*30129*/ OPC_CheckChild1Type, MVT::v2i32,
11232 : /*30131*/ OPC_RecordChild2, // #1 = $rsrc
11233 : /*30132*/ OPC_RecordChild3, // #2 = $sampler
11234 : /*30133*/ OPC_RecordChild4, // #3 = $dmask
11235 : /*30134*/ OPC_RecordChild5, // #4 = $unorm
11236 : /*30135*/ OPC_RecordChild6, // #5 = $r128
11237 : /*30136*/ OPC_RecordChild7, // #6 = $da
11238 : /*30137*/ OPC_MoveChild, 8,
11239 : /*30139*/ OPC_RecordNode, // #7 = $glc
11240 : /*30140*/ OPC_MoveParent,
11241 : /*30141*/ OPC_MoveChild, 9,
11242 : /*30143*/ OPC_RecordNode, // #8 = $slc
11243 : /*30144*/ OPC_MoveParent,
11244 : /*30145*/ OPC_MoveChild, 10,
11245 : /*30147*/ OPC_RecordNode, // #9 = $tfe
11246 : /*30148*/ OPC_MoveParent,
11247 : /*30149*/ OPC_MoveChild, 11,
11248 : /*30151*/ OPC_RecordNode, // #10 = $lwe
11249 : /*30152*/ OPC_MoveParent,
11250 : /*30153*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11251 : /*30155*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11252 : /*30158*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11253 : /*30161*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11254 : /*30164*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11255 : /*30167*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11256 : /*30170*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11257 : /*30173*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11258 : /*30176*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11259 : /*30179*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V2), 0,
11260 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11261 : // Src: (intrinsic_wo_chain:v4f32 4840:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11262 : // Dst: (IMAGE_SAMPLE_C_B_CL_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11263 : /*30197*/ /*Scope*/ 68, /*->30266*/
11264 : /*30198*/ OPC_CheckChild1Type, MVT::v4i32,
11265 : /*30200*/ OPC_RecordChild2, // #1 = $rsrc
11266 : /*30201*/ OPC_RecordChild3, // #2 = $sampler
11267 : /*30202*/ OPC_RecordChild4, // #3 = $dmask
11268 : /*30203*/ OPC_RecordChild5, // #4 = $unorm
11269 : /*30204*/ OPC_RecordChild6, // #5 = $r128
11270 : /*30205*/ OPC_RecordChild7, // #6 = $da
11271 : /*30206*/ OPC_MoveChild, 8,
11272 : /*30208*/ OPC_RecordNode, // #7 = $glc
11273 : /*30209*/ OPC_MoveParent,
11274 : /*30210*/ OPC_MoveChild, 9,
11275 : /*30212*/ OPC_RecordNode, // #8 = $slc
11276 : /*30213*/ OPC_MoveParent,
11277 : /*30214*/ OPC_MoveChild, 10,
11278 : /*30216*/ OPC_RecordNode, // #9 = $tfe
11279 : /*30217*/ OPC_MoveParent,
11280 : /*30218*/ OPC_MoveChild, 11,
11281 : /*30220*/ OPC_RecordNode, // #10 = $lwe
11282 : /*30221*/ OPC_MoveParent,
11283 : /*30222*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11284 : /*30224*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11285 : /*30227*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11286 : /*30230*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11287 : /*30233*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11288 : /*30236*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11289 : /*30239*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11290 : /*30242*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11291 : /*30245*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11292 : /*30248*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4), 0,
11293 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11294 : // Src: (intrinsic_wo_chain:v4f32 4840:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11295 : // Dst: (IMAGE_SAMPLE_C_B_CL_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11296 : /*30266*/ /*Scope*/ 68, /*->30335*/
11297 : /*30267*/ OPC_CheckChild1Type, MVT::v8i32,
11298 : /*30269*/ OPC_RecordChild2, // #1 = $rsrc
11299 : /*30270*/ OPC_RecordChild3, // #2 = $sampler
11300 : /*30271*/ OPC_RecordChild4, // #3 = $dmask
11301 : /*30272*/ OPC_RecordChild5, // #4 = $unorm
11302 : /*30273*/ OPC_RecordChild6, // #5 = $r128
11303 : /*30274*/ OPC_RecordChild7, // #6 = $da
11304 : /*30275*/ OPC_MoveChild, 8,
11305 : /*30277*/ OPC_RecordNode, // #7 = $glc
11306 : /*30278*/ OPC_MoveParent,
11307 : /*30279*/ OPC_MoveChild, 9,
11308 : /*30281*/ OPC_RecordNode, // #8 = $slc
11309 : /*30282*/ OPC_MoveParent,
11310 : /*30283*/ OPC_MoveChild, 10,
11311 : /*30285*/ OPC_RecordNode, // #9 = $tfe
11312 : /*30286*/ OPC_MoveParent,
11313 : /*30287*/ OPC_MoveChild, 11,
11314 : /*30289*/ OPC_RecordNode, // #10 = $lwe
11315 : /*30290*/ OPC_MoveParent,
11316 : /*30291*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11317 : /*30293*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11318 : /*30296*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11319 : /*30299*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11320 : /*30302*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11321 : /*30305*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11322 : /*30308*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11323 : /*30311*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11324 : /*30314*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11325 : /*30317*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8), 0,
11326 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11327 : // Src: (intrinsic_wo_chain:v4f32 4840:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11328 : // Dst: (IMAGE_SAMPLE_C_B_CL_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11329 : /*30335*/ /*Scope*/ 68, /*->30404*/
11330 : /*30336*/ OPC_CheckChild1Type, MVT::v16i32,
11331 : /*30338*/ OPC_RecordChild2, // #1 = $rsrc
11332 : /*30339*/ OPC_RecordChild3, // #2 = $sampler
11333 : /*30340*/ OPC_RecordChild4, // #3 = $dmask
11334 : /*30341*/ OPC_RecordChild5, // #4 = $unorm
11335 : /*30342*/ OPC_RecordChild6, // #5 = $r128
11336 : /*30343*/ OPC_RecordChild7, // #6 = $da
11337 : /*30344*/ OPC_MoveChild, 8,
11338 : /*30346*/ OPC_RecordNode, // #7 = $glc
11339 : /*30347*/ OPC_MoveParent,
11340 : /*30348*/ OPC_MoveChild, 9,
11341 : /*30350*/ OPC_RecordNode, // #8 = $slc
11342 : /*30351*/ OPC_MoveParent,
11343 : /*30352*/ OPC_MoveChild, 10,
11344 : /*30354*/ OPC_RecordNode, // #9 = $tfe
11345 : /*30355*/ OPC_MoveParent,
11346 : /*30356*/ OPC_MoveChild, 11,
11347 : /*30358*/ OPC_RecordNode, // #10 = $lwe
11348 : /*30359*/ OPC_MoveParent,
11349 : /*30360*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11350 : /*30362*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11351 : /*30365*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11352 : /*30368*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11353 : /*30371*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11354 : /*30374*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11355 : /*30377*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11356 : /*30380*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11357 : /*30383*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11358 : /*30386*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V16), 0,
11359 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11360 : // Src: (intrinsic_wo_chain:v4f32 4840:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11361 : // Dst: (IMAGE_SAMPLE_C_B_CL_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11362 : /*30404*/ 0, /*End of Scope*/
11363 : /*30405*/ /*Scope*/ 95|128,2/*351*/, /*->30758*/
11364 : /*30407*/ OPC_CheckChild0Integer, 119|128,37/*4855*/,
11365 : /*30410*/ OPC_RecordChild1, // #0 = $addr
11366 : /*30411*/ OPC_Scope, 68, /*->30481*/ // 5 children in Scope
11367 : /*30413*/ OPC_CheckChild1Type, MVT::i32,
11368 : /*30415*/ OPC_RecordChild2, // #1 = $rsrc
11369 : /*30416*/ OPC_RecordChild3, // #2 = $sampler
11370 : /*30417*/ OPC_RecordChild4, // #3 = $dmask
11371 : /*30418*/ OPC_RecordChild5, // #4 = $unorm
11372 : /*30419*/ OPC_RecordChild6, // #5 = $r128
11373 : /*30420*/ OPC_RecordChild7, // #6 = $da
11374 : /*30421*/ OPC_MoveChild, 8,
11375 : /*30423*/ OPC_RecordNode, // #7 = $glc
11376 : /*30424*/ OPC_MoveParent,
11377 : /*30425*/ OPC_MoveChild, 9,
11378 : /*30427*/ OPC_RecordNode, // #8 = $slc
11379 : /*30428*/ OPC_MoveParent,
11380 : /*30429*/ OPC_MoveChild, 10,
11381 : /*30431*/ OPC_RecordNode, // #9 = $tfe
11382 : /*30432*/ OPC_MoveParent,
11383 : /*30433*/ OPC_MoveChild, 11,
11384 : /*30435*/ OPC_RecordNode, // #10 = $lwe
11385 : /*30436*/ OPC_MoveParent,
11386 : /*30437*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11387 : /*30439*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11388 : /*30442*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11389 : /*30445*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11390 : /*30448*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11391 : /*30451*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11392 : /*30454*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11393 : /*30457*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11394 : /*30460*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11395 : /*30463*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V1), 0,
11396 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11397 : // Src: (intrinsic_wo_chain:v4f32 4855:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11398 : // Dst: (IMAGE_SAMPLE_C_LZ_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11399 : /*30481*/ /*Scope*/ 68, /*->30550*/
11400 : /*30482*/ OPC_CheckChild1Type, MVT::v2i32,
11401 : /*30484*/ OPC_RecordChild2, // #1 = $rsrc
11402 : /*30485*/ OPC_RecordChild3, // #2 = $sampler
11403 : /*30486*/ OPC_RecordChild4, // #3 = $dmask
11404 : /*30487*/ OPC_RecordChild5, // #4 = $unorm
11405 : /*30488*/ OPC_RecordChild6, // #5 = $r128
11406 : /*30489*/ OPC_RecordChild7, // #6 = $da
11407 : /*30490*/ OPC_MoveChild, 8,
11408 : /*30492*/ OPC_RecordNode, // #7 = $glc
11409 : /*30493*/ OPC_MoveParent,
11410 : /*30494*/ OPC_MoveChild, 9,
11411 : /*30496*/ OPC_RecordNode, // #8 = $slc
11412 : /*30497*/ OPC_MoveParent,
11413 : /*30498*/ OPC_MoveChild, 10,
11414 : /*30500*/ OPC_RecordNode, // #9 = $tfe
11415 : /*30501*/ OPC_MoveParent,
11416 : /*30502*/ OPC_MoveChild, 11,
11417 : /*30504*/ OPC_RecordNode, // #10 = $lwe
11418 : /*30505*/ OPC_MoveParent,
11419 : /*30506*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11420 : /*30508*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11421 : /*30511*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11422 : /*30514*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11423 : /*30517*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11424 : /*30520*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11425 : /*30523*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11426 : /*30526*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11427 : /*30529*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11428 : /*30532*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2), 0,
11429 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11430 : // Src: (intrinsic_wo_chain:v4f32 4855:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11431 : // Dst: (IMAGE_SAMPLE_C_LZ_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11432 : /*30550*/ /*Scope*/ 68, /*->30619*/
11433 : /*30551*/ OPC_CheckChild1Type, MVT::v4i32,
11434 : /*30553*/ OPC_RecordChild2, // #1 = $rsrc
11435 : /*30554*/ OPC_RecordChild3, // #2 = $sampler
11436 : /*30555*/ OPC_RecordChild4, // #3 = $dmask
11437 : /*30556*/ OPC_RecordChild5, // #4 = $unorm
11438 : /*30557*/ OPC_RecordChild6, // #5 = $r128
11439 : /*30558*/ OPC_RecordChild7, // #6 = $da
11440 : /*30559*/ OPC_MoveChild, 8,
11441 : /*30561*/ OPC_RecordNode, // #7 = $glc
11442 : /*30562*/ OPC_MoveParent,
11443 : /*30563*/ OPC_MoveChild, 9,
11444 : /*30565*/ OPC_RecordNode, // #8 = $slc
11445 : /*30566*/ OPC_MoveParent,
11446 : /*30567*/ OPC_MoveChild, 10,
11447 : /*30569*/ OPC_RecordNode, // #9 = $tfe
11448 : /*30570*/ OPC_MoveParent,
11449 : /*30571*/ OPC_MoveChild, 11,
11450 : /*30573*/ OPC_RecordNode, // #10 = $lwe
11451 : /*30574*/ OPC_MoveParent,
11452 : /*30575*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11453 : /*30577*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11454 : /*30580*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11455 : /*30583*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11456 : /*30586*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11457 : /*30589*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11458 : /*30592*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11459 : /*30595*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11460 : /*30598*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11461 : /*30601*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4), 0,
11462 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11463 : // Src: (intrinsic_wo_chain:v4f32 4855:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11464 : // Dst: (IMAGE_SAMPLE_C_LZ_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11465 : /*30619*/ /*Scope*/ 68, /*->30688*/
11466 : /*30620*/ OPC_CheckChild1Type, MVT::v8i32,
11467 : /*30622*/ OPC_RecordChild2, // #1 = $rsrc
11468 : /*30623*/ OPC_RecordChild3, // #2 = $sampler
11469 : /*30624*/ OPC_RecordChild4, // #3 = $dmask
11470 : /*30625*/ OPC_RecordChild5, // #4 = $unorm
11471 : /*30626*/ OPC_RecordChild6, // #5 = $r128
11472 : /*30627*/ OPC_RecordChild7, // #6 = $da
11473 : /*30628*/ OPC_MoveChild, 8,
11474 : /*30630*/ OPC_RecordNode, // #7 = $glc
11475 : /*30631*/ OPC_MoveParent,
11476 : /*30632*/ OPC_MoveChild, 9,
11477 : /*30634*/ OPC_RecordNode, // #8 = $slc
11478 : /*30635*/ OPC_MoveParent,
11479 : /*30636*/ OPC_MoveChild, 10,
11480 : /*30638*/ OPC_RecordNode, // #9 = $tfe
11481 : /*30639*/ OPC_MoveParent,
11482 : /*30640*/ OPC_MoveChild, 11,
11483 : /*30642*/ OPC_RecordNode, // #10 = $lwe
11484 : /*30643*/ OPC_MoveParent,
11485 : /*30644*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11486 : /*30646*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11487 : /*30649*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11488 : /*30652*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11489 : /*30655*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11490 : /*30658*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11491 : /*30661*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11492 : /*30664*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11493 : /*30667*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11494 : /*30670*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V8), 0,
11495 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11496 : // Src: (intrinsic_wo_chain:v4f32 4855:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11497 : // Dst: (IMAGE_SAMPLE_C_LZ_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11498 : /*30688*/ /*Scope*/ 68, /*->30757*/
11499 : /*30689*/ OPC_CheckChild1Type, MVT::v16i32,
11500 : /*30691*/ OPC_RecordChild2, // #1 = $rsrc
11501 : /*30692*/ OPC_RecordChild3, // #2 = $sampler
11502 : /*30693*/ OPC_RecordChild4, // #3 = $dmask
11503 : /*30694*/ OPC_RecordChild5, // #4 = $unorm
11504 : /*30695*/ OPC_RecordChild6, // #5 = $r128
11505 : /*30696*/ OPC_RecordChild7, // #6 = $da
11506 : /*30697*/ OPC_MoveChild, 8,
11507 : /*30699*/ OPC_RecordNode, // #7 = $glc
11508 : /*30700*/ OPC_MoveParent,
11509 : /*30701*/ OPC_MoveChild, 9,
11510 : /*30703*/ OPC_RecordNode, // #8 = $slc
11511 : /*30704*/ OPC_MoveParent,
11512 : /*30705*/ OPC_MoveChild, 10,
11513 : /*30707*/ OPC_RecordNode, // #9 = $tfe
11514 : /*30708*/ OPC_MoveParent,
11515 : /*30709*/ OPC_MoveChild, 11,
11516 : /*30711*/ OPC_RecordNode, // #10 = $lwe
11517 : /*30712*/ OPC_MoveParent,
11518 : /*30713*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11519 : /*30715*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11520 : /*30718*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11521 : /*30721*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11522 : /*30724*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11523 : /*30727*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11524 : /*30730*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11525 : /*30733*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11526 : /*30736*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11527 : /*30739*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V16), 0,
11528 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11529 : // Src: (intrinsic_wo_chain:v4f32 4855:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11530 : // Dst: (IMAGE_SAMPLE_C_LZ_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11531 : /*30757*/ 0, /*End of Scope*/
11532 : /*30758*/ /*Scope*/ 95|128,2/*351*/, /*->31111*/
11533 : /*30760*/ OPC_CheckChild0Integer, 107|128,37/*4843*/,
11534 : /*30763*/ OPC_RecordChild1, // #0 = $addr
11535 : /*30764*/ OPC_Scope, 68, /*->30834*/ // 5 children in Scope
11536 : /*30766*/ OPC_CheckChild1Type, MVT::i32,
11537 : /*30768*/ OPC_RecordChild2, // #1 = $rsrc
11538 : /*30769*/ OPC_RecordChild3, // #2 = $sampler
11539 : /*30770*/ OPC_RecordChild4, // #3 = $dmask
11540 : /*30771*/ OPC_RecordChild5, // #4 = $unorm
11541 : /*30772*/ OPC_RecordChild6, // #5 = $r128
11542 : /*30773*/ OPC_RecordChild7, // #6 = $da
11543 : /*30774*/ OPC_MoveChild, 8,
11544 : /*30776*/ OPC_RecordNode, // #7 = $glc
11545 : /*30777*/ OPC_MoveParent,
11546 : /*30778*/ OPC_MoveChild, 9,
11547 : /*30780*/ OPC_RecordNode, // #8 = $slc
11548 : /*30781*/ OPC_MoveParent,
11549 : /*30782*/ OPC_MoveChild, 10,
11550 : /*30784*/ OPC_RecordNode, // #9 = $tfe
11551 : /*30785*/ OPC_MoveParent,
11552 : /*30786*/ OPC_MoveChild, 11,
11553 : /*30788*/ OPC_RecordNode, // #10 = $lwe
11554 : /*30789*/ OPC_MoveParent,
11555 : /*30790*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11556 : /*30792*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11557 : /*30795*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11558 : /*30798*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11559 : /*30801*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11560 : /*30804*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11561 : /*30807*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11562 : /*30810*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11563 : /*30813*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11564 : /*30816*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_V4_V1), 0,
11565 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11566 : // Src: (intrinsic_wo_chain:v4f32 4843:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11567 : // Dst: (IMAGE_SAMPLE_C_CD_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11568 : /*30834*/ /*Scope*/ 68, /*->30903*/
11569 : /*30835*/ OPC_CheckChild1Type, MVT::v2i32,
11570 : /*30837*/ OPC_RecordChild2, // #1 = $rsrc
11571 : /*30838*/ OPC_RecordChild3, // #2 = $sampler
11572 : /*30839*/ OPC_RecordChild4, // #3 = $dmask
11573 : /*30840*/ OPC_RecordChild5, // #4 = $unorm
11574 : /*30841*/ OPC_RecordChild6, // #5 = $r128
11575 : /*30842*/ OPC_RecordChild7, // #6 = $da
11576 : /*30843*/ OPC_MoveChild, 8,
11577 : /*30845*/ OPC_RecordNode, // #7 = $glc
11578 : /*30846*/ OPC_MoveParent,
11579 : /*30847*/ OPC_MoveChild, 9,
11580 : /*30849*/ OPC_RecordNode, // #8 = $slc
11581 : /*30850*/ OPC_MoveParent,
11582 : /*30851*/ OPC_MoveChild, 10,
11583 : /*30853*/ OPC_RecordNode, // #9 = $tfe
11584 : /*30854*/ OPC_MoveParent,
11585 : /*30855*/ OPC_MoveChild, 11,
11586 : /*30857*/ OPC_RecordNode, // #10 = $lwe
11587 : /*30858*/ OPC_MoveParent,
11588 : /*30859*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11589 : /*30861*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11590 : /*30864*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11591 : /*30867*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11592 : /*30870*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11593 : /*30873*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11594 : /*30876*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11595 : /*30879*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11596 : /*30882*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11597 : /*30885*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_V4_V2), 0,
11598 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11599 : // Src: (intrinsic_wo_chain:v4f32 4843:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11600 : // Dst: (IMAGE_SAMPLE_C_CD_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11601 : /*30903*/ /*Scope*/ 68, /*->30972*/
11602 : /*30904*/ OPC_CheckChild1Type, MVT::v4i32,
11603 : /*30906*/ OPC_RecordChild2, // #1 = $rsrc
11604 : /*30907*/ OPC_RecordChild3, // #2 = $sampler
11605 : /*30908*/ OPC_RecordChild4, // #3 = $dmask
11606 : /*30909*/ OPC_RecordChild5, // #4 = $unorm
11607 : /*30910*/ OPC_RecordChild6, // #5 = $r128
11608 : /*30911*/ OPC_RecordChild7, // #6 = $da
11609 : /*30912*/ OPC_MoveChild, 8,
11610 : /*30914*/ OPC_RecordNode, // #7 = $glc
11611 : /*30915*/ OPC_MoveParent,
11612 : /*30916*/ OPC_MoveChild, 9,
11613 : /*30918*/ OPC_RecordNode, // #8 = $slc
11614 : /*30919*/ OPC_MoveParent,
11615 : /*30920*/ OPC_MoveChild, 10,
11616 : /*30922*/ OPC_RecordNode, // #9 = $tfe
11617 : /*30923*/ OPC_MoveParent,
11618 : /*30924*/ OPC_MoveChild, 11,
11619 : /*30926*/ OPC_RecordNode, // #10 = $lwe
11620 : /*30927*/ OPC_MoveParent,
11621 : /*30928*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11622 : /*30930*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11623 : /*30933*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11624 : /*30936*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11625 : /*30939*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11626 : /*30942*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11627 : /*30945*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11628 : /*30948*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11629 : /*30951*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11630 : /*30954*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4), 0,
11631 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11632 : // Src: (intrinsic_wo_chain:v4f32 4843:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11633 : // Dst: (IMAGE_SAMPLE_C_CD_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11634 : /*30972*/ /*Scope*/ 68, /*->31041*/
11635 : /*30973*/ OPC_CheckChild1Type, MVT::v8i32,
11636 : /*30975*/ OPC_RecordChild2, // #1 = $rsrc
11637 : /*30976*/ OPC_RecordChild3, // #2 = $sampler
11638 : /*30977*/ OPC_RecordChild4, // #3 = $dmask
11639 : /*30978*/ OPC_RecordChild5, // #4 = $unorm
11640 : /*30979*/ OPC_RecordChild6, // #5 = $r128
11641 : /*30980*/ OPC_RecordChild7, // #6 = $da
11642 : /*30981*/ OPC_MoveChild, 8,
11643 : /*30983*/ OPC_RecordNode, // #7 = $glc
11644 : /*30984*/ OPC_MoveParent,
11645 : /*30985*/ OPC_MoveChild, 9,
11646 : /*30987*/ OPC_RecordNode, // #8 = $slc
11647 : /*30988*/ OPC_MoveParent,
11648 : /*30989*/ OPC_MoveChild, 10,
11649 : /*30991*/ OPC_RecordNode, // #9 = $tfe
11650 : /*30992*/ OPC_MoveParent,
11651 : /*30993*/ OPC_MoveChild, 11,
11652 : /*30995*/ OPC_RecordNode, // #10 = $lwe
11653 : /*30996*/ OPC_MoveParent,
11654 : /*30997*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11655 : /*30999*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11656 : /*31002*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11657 : /*31005*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11658 : /*31008*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11659 : /*31011*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11660 : /*31014*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11661 : /*31017*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11662 : /*31020*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11663 : /*31023*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8), 0,
11664 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11665 : // Src: (intrinsic_wo_chain:v4f32 4843:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11666 : // Dst: (IMAGE_SAMPLE_C_CD_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11667 : /*31041*/ /*Scope*/ 68, /*->31110*/
11668 : /*31042*/ OPC_CheckChild1Type, MVT::v16i32,
11669 : /*31044*/ OPC_RecordChild2, // #1 = $rsrc
11670 : /*31045*/ OPC_RecordChild3, // #2 = $sampler
11671 : /*31046*/ OPC_RecordChild4, // #3 = $dmask
11672 : /*31047*/ OPC_RecordChild5, // #4 = $unorm
11673 : /*31048*/ OPC_RecordChild6, // #5 = $r128
11674 : /*31049*/ OPC_RecordChild7, // #6 = $da
11675 : /*31050*/ OPC_MoveChild, 8,
11676 : /*31052*/ OPC_RecordNode, // #7 = $glc
11677 : /*31053*/ OPC_MoveParent,
11678 : /*31054*/ OPC_MoveChild, 9,
11679 : /*31056*/ OPC_RecordNode, // #8 = $slc
11680 : /*31057*/ OPC_MoveParent,
11681 : /*31058*/ OPC_MoveChild, 10,
11682 : /*31060*/ OPC_RecordNode, // #9 = $tfe
11683 : /*31061*/ OPC_MoveParent,
11684 : /*31062*/ OPC_MoveChild, 11,
11685 : /*31064*/ OPC_RecordNode, // #10 = $lwe
11686 : /*31065*/ OPC_MoveParent,
11687 : /*31066*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11688 : /*31068*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11689 : /*31071*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11690 : /*31074*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11691 : /*31077*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11692 : /*31080*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11693 : /*31083*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11694 : /*31086*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11695 : /*31089*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11696 : /*31092*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_V4_V16), 0,
11697 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11698 : // Src: (intrinsic_wo_chain:v4f32 4843:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11699 : // Dst: (IMAGE_SAMPLE_C_CD_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11700 : /*31110*/ 0, /*End of Scope*/
11701 : /*31111*/ /*Scope*/ 95|128,2/*351*/, /*->31464*/
11702 : /*31113*/ OPC_CheckChild0Integer, 108|128,37/*4844*/,
11703 : /*31116*/ OPC_RecordChild1, // #0 = $addr
11704 : /*31117*/ OPC_Scope, 68, /*->31187*/ // 5 children in Scope
11705 : /*31119*/ OPC_CheckChild1Type, MVT::i32,
11706 : /*31121*/ OPC_RecordChild2, // #1 = $rsrc
11707 : /*31122*/ OPC_RecordChild3, // #2 = $sampler
11708 : /*31123*/ OPC_RecordChild4, // #3 = $dmask
11709 : /*31124*/ OPC_RecordChild5, // #4 = $unorm
11710 : /*31125*/ OPC_RecordChild6, // #5 = $r128
11711 : /*31126*/ OPC_RecordChild7, // #6 = $da
11712 : /*31127*/ OPC_MoveChild, 8,
11713 : /*31129*/ OPC_RecordNode, // #7 = $glc
11714 : /*31130*/ OPC_MoveParent,
11715 : /*31131*/ OPC_MoveChild, 9,
11716 : /*31133*/ OPC_RecordNode, // #8 = $slc
11717 : /*31134*/ OPC_MoveParent,
11718 : /*31135*/ OPC_MoveChild, 10,
11719 : /*31137*/ OPC_RecordNode, // #9 = $tfe
11720 : /*31138*/ OPC_MoveParent,
11721 : /*31139*/ OPC_MoveChild, 11,
11722 : /*31141*/ OPC_RecordNode, // #10 = $lwe
11723 : /*31142*/ OPC_MoveParent,
11724 : /*31143*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11725 : /*31145*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11726 : /*31148*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11727 : /*31151*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11728 : /*31154*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11729 : /*31157*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11730 : /*31160*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11731 : /*31163*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11732 : /*31166*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11733 : /*31169*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V1), 0,
11734 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11735 : // Src: (intrinsic_wo_chain:v4f32 4844:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11736 : // Dst: (IMAGE_SAMPLE_C_CD_CL_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11737 : /*31187*/ /*Scope*/ 68, /*->31256*/
11738 : /*31188*/ OPC_CheckChild1Type, MVT::v2i32,
11739 : /*31190*/ OPC_RecordChild2, // #1 = $rsrc
11740 : /*31191*/ OPC_RecordChild3, // #2 = $sampler
11741 : /*31192*/ OPC_RecordChild4, // #3 = $dmask
11742 : /*31193*/ OPC_RecordChild5, // #4 = $unorm
11743 : /*31194*/ OPC_RecordChild6, // #5 = $r128
11744 : /*31195*/ OPC_RecordChild7, // #6 = $da
11745 : /*31196*/ OPC_MoveChild, 8,
11746 : /*31198*/ OPC_RecordNode, // #7 = $glc
11747 : /*31199*/ OPC_MoveParent,
11748 : /*31200*/ OPC_MoveChild, 9,
11749 : /*31202*/ OPC_RecordNode, // #8 = $slc
11750 : /*31203*/ OPC_MoveParent,
11751 : /*31204*/ OPC_MoveChild, 10,
11752 : /*31206*/ OPC_RecordNode, // #9 = $tfe
11753 : /*31207*/ OPC_MoveParent,
11754 : /*31208*/ OPC_MoveChild, 11,
11755 : /*31210*/ OPC_RecordNode, // #10 = $lwe
11756 : /*31211*/ OPC_MoveParent,
11757 : /*31212*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11758 : /*31214*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11759 : /*31217*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11760 : /*31220*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11761 : /*31223*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11762 : /*31226*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11763 : /*31229*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11764 : /*31232*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11765 : /*31235*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11766 : /*31238*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V2), 0,
11767 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11768 : // Src: (intrinsic_wo_chain:v4f32 4844:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11769 : // Dst: (IMAGE_SAMPLE_C_CD_CL_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11770 : /*31256*/ /*Scope*/ 68, /*->31325*/
11771 : /*31257*/ OPC_CheckChild1Type, MVT::v4i32,
11772 : /*31259*/ OPC_RecordChild2, // #1 = $rsrc
11773 : /*31260*/ OPC_RecordChild3, // #2 = $sampler
11774 : /*31261*/ OPC_RecordChild4, // #3 = $dmask
11775 : /*31262*/ OPC_RecordChild5, // #4 = $unorm
11776 : /*31263*/ OPC_RecordChild6, // #5 = $r128
11777 : /*31264*/ OPC_RecordChild7, // #6 = $da
11778 : /*31265*/ OPC_MoveChild, 8,
11779 : /*31267*/ OPC_RecordNode, // #7 = $glc
11780 : /*31268*/ OPC_MoveParent,
11781 : /*31269*/ OPC_MoveChild, 9,
11782 : /*31271*/ OPC_RecordNode, // #8 = $slc
11783 : /*31272*/ OPC_MoveParent,
11784 : /*31273*/ OPC_MoveChild, 10,
11785 : /*31275*/ OPC_RecordNode, // #9 = $tfe
11786 : /*31276*/ OPC_MoveParent,
11787 : /*31277*/ OPC_MoveChild, 11,
11788 : /*31279*/ OPC_RecordNode, // #10 = $lwe
11789 : /*31280*/ OPC_MoveParent,
11790 : /*31281*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11791 : /*31283*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11792 : /*31286*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11793 : /*31289*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11794 : /*31292*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11795 : /*31295*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11796 : /*31298*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11797 : /*31301*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11798 : /*31304*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11799 : /*31307*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4), 0,
11800 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11801 : // Src: (intrinsic_wo_chain:v4f32 4844:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11802 : // Dst: (IMAGE_SAMPLE_C_CD_CL_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11803 : /*31325*/ /*Scope*/ 68, /*->31394*/
11804 : /*31326*/ OPC_CheckChild1Type, MVT::v8i32,
11805 : /*31328*/ OPC_RecordChild2, // #1 = $rsrc
11806 : /*31329*/ OPC_RecordChild3, // #2 = $sampler
11807 : /*31330*/ OPC_RecordChild4, // #3 = $dmask
11808 : /*31331*/ OPC_RecordChild5, // #4 = $unorm
11809 : /*31332*/ OPC_RecordChild6, // #5 = $r128
11810 : /*31333*/ OPC_RecordChild7, // #6 = $da
11811 : /*31334*/ OPC_MoveChild, 8,
11812 : /*31336*/ OPC_RecordNode, // #7 = $glc
11813 : /*31337*/ OPC_MoveParent,
11814 : /*31338*/ OPC_MoveChild, 9,
11815 : /*31340*/ OPC_RecordNode, // #8 = $slc
11816 : /*31341*/ OPC_MoveParent,
11817 : /*31342*/ OPC_MoveChild, 10,
11818 : /*31344*/ OPC_RecordNode, // #9 = $tfe
11819 : /*31345*/ OPC_MoveParent,
11820 : /*31346*/ OPC_MoveChild, 11,
11821 : /*31348*/ OPC_RecordNode, // #10 = $lwe
11822 : /*31349*/ OPC_MoveParent,
11823 : /*31350*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11824 : /*31352*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11825 : /*31355*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11826 : /*31358*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11827 : /*31361*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11828 : /*31364*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11829 : /*31367*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11830 : /*31370*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11831 : /*31373*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11832 : /*31376*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8), 0,
11833 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11834 : // Src: (intrinsic_wo_chain:v4f32 4844:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11835 : // Dst: (IMAGE_SAMPLE_C_CD_CL_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11836 : /*31394*/ /*Scope*/ 68, /*->31463*/
11837 : /*31395*/ OPC_CheckChild1Type, MVT::v16i32,
11838 : /*31397*/ OPC_RecordChild2, // #1 = $rsrc
11839 : /*31398*/ OPC_RecordChild3, // #2 = $sampler
11840 : /*31399*/ OPC_RecordChild4, // #3 = $dmask
11841 : /*31400*/ OPC_RecordChild5, // #4 = $unorm
11842 : /*31401*/ OPC_RecordChild6, // #5 = $r128
11843 : /*31402*/ OPC_RecordChild7, // #6 = $da
11844 : /*31403*/ OPC_MoveChild, 8,
11845 : /*31405*/ OPC_RecordNode, // #7 = $glc
11846 : /*31406*/ OPC_MoveParent,
11847 : /*31407*/ OPC_MoveChild, 9,
11848 : /*31409*/ OPC_RecordNode, // #8 = $slc
11849 : /*31410*/ OPC_MoveParent,
11850 : /*31411*/ OPC_MoveChild, 10,
11851 : /*31413*/ OPC_RecordNode, // #9 = $tfe
11852 : /*31414*/ OPC_MoveParent,
11853 : /*31415*/ OPC_MoveChild, 11,
11854 : /*31417*/ OPC_RecordNode, // #10 = $lwe
11855 : /*31418*/ OPC_MoveParent,
11856 : /*31419*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11857 : /*31421*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11858 : /*31424*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11859 : /*31427*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11860 : /*31430*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11861 : /*31433*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11862 : /*31436*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11863 : /*31439*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11864 : /*31442*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11865 : /*31445*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V16), 0,
11866 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11867 : // Src: (intrinsic_wo_chain:v4f32 4844:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11868 : // Dst: (IMAGE_SAMPLE_C_CD_CL_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11869 : /*31463*/ 0, /*End of Scope*/
11870 : /*31464*/ /*Scope*/ 95|128,2/*351*/, /*->31817*/
11871 : /*31466*/ OPC_CheckChild0Integer, 8|128,38/*4872*/,
11872 : /*31469*/ OPC_RecordChild1, // #0 = $addr
11873 : /*31470*/ OPC_Scope, 68, /*->31540*/ // 5 children in Scope
11874 : /*31472*/ OPC_CheckChild1Type, MVT::i32,
11875 : /*31474*/ OPC_RecordChild2, // #1 = $rsrc
11876 : /*31475*/ OPC_RecordChild3, // #2 = $sampler
11877 : /*31476*/ OPC_RecordChild4, // #3 = $dmask
11878 : /*31477*/ OPC_RecordChild5, // #4 = $unorm
11879 : /*31478*/ OPC_RecordChild6, // #5 = $r128
11880 : /*31479*/ OPC_RecordChild7, // #6 = $da
11881 : /*31480*/ OPC_MoveChild, 8,
11882 : /*31482*/ OPC_RecordNode, // #7 = $glc
11883 : /*31483*/ OPC_MoveParent,
11884 : /*31484*/ OPC_MoveChild, 9,
11885 : /*31486*/ OPC_RecordNode, // #8 = $slc
11886 : /*31487*/ OPC_MoveParent,
11887 : /*31488*/ OPC_MoveChild, 10,
11888 : /*31490*/ OPC_RecordNode, // #9 = $tfe
11889 : /*31491*/ OPC_MoveParent,
11890 : /*31492*/ OPC_MoveChild, 11,
11891 : /*31494*/ OPC_RecordNode, // #10 = $lwe
11892 : /*31495*/ OPC_MoveParent,
11893 : /*31496*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11894 : /*31498*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11895 : /*31501*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11896 : /*31504*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11897 : /*31507*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11898 : /*31510*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11899 : /*31513*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11900 : /*31516*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11901 : /*31519*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11902 : /*31522*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_O_V4_V1), 0,
11903 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11904 : // Src: (intrinsic_wo_chain:v4f32 4872:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11905 : // Dst: (IMAGE_SAMPLE_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11906 : /*31540*/ /*Scope*/ 68, /*->31609*/
11907 : /*31541*/ OPC_CheckChild1Type, MVT::v2i32,
11908 : /*31543*/ OPC_RecordChild2, // #1 = $rsrc
11909 : /*31544*/ OPC_RecordChild3, // #2 = $sampler
11910 : /*31545*/ OPC_RecordChild4, // #3 = $dmask
11911 : /*31546*/ OPC_RecordChild5, // #4 = $unorm
11912 : /*31547*/ OPC_RecordChild6, // #5 = $r128
11913 : /*31548*/ OPC_RecordChild7, // #6 = $da
11914 : /*31549*/ OPC_MoveChild, 8,
11915 : /*31551*/ OPC_RecordNode, // #7 = $glc
11916 : /*31552*/ OPC_MoveParent,
11917 : /*31553*/ OPC_MoveChild, 9,
11918 : /*31555*/ OPC_RecordNode, // #8 = $slc
11919 : /*31556*/ OPC_MoveParent,
11920 : /*31557*/ OPC_MoveChild, 10,
11921 : /*31559*/ OPC_RecordNode, // #9 = $tfe
11922 : /*31560*/ OPC_MoveParent,
11923 : /*31561*/ OPC_MoveChild, 11,
11924 : /*31563*/ OPC_RecordNode, // #10 = $lwe
11925 : /*31564*/ OPC_MoveParent,
11926 : /*31565*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11927 : /*31567*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11928 : /*31570*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11929 : /*31573*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11930 : /*31576*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11931 : /*31579*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11932 : /*31582*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11933 : /*31585*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11934 : /*31588*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11935 : /*31591*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_O_V4_V2), 0,
11936 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11937 : // Src: (intrinsic_wo_chain:v4f32 4872:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11938 : // Dst: (IMAGE_SAMPLE_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11939 : /*31609*/ /*Scope*/ 68, /*->31678*/
11940 : /*31610*/ OPC_CheckChild1Type, MVT::v4i32,
11941 : /*31612*/ OPC_RecordChild2, // #1 = $rsrc
11942 : /*31613*/ OPC_RecordChild3, // #2 = $sampler
11943 : /*31614*/ OPC_RecordChild4, // #3 = $dmask
11944 : /*31615*/ OPC_RecordChild5, // #4 = $unorm
11945 : /*31616*/ OPC_RecordChild6, // #5 = $r128
11946 : /*31617*/ OPC_RecordChild7, // #6 = $da
11947 : /*31618*/ OPC_MoveChild, 8,
11948 : /*31620*/ OPC_RecordNode, // #7 = $glc
11949 : /*31621*/ OPC_MoveParent,
11950 : /*31622*/ OPC_MoveChild, 9,
11951 : /*31624*/ OPC_RecordNode, // #8 = $slc
11952 : /*31625*/ OPC_MoveParent,
11953 : /*31626*/ OPC_MoveChild, 10,
11954 : /*31628*/ OPC_RecordNode, // #9 = $tfe
11955 : /*31629*/ OPC_MoveParent,
11956 : /*31630*/ OPC_MoveChild, 11,
11957 : /*31632*/ OPC_RecordNode, // #10 = $lwe
11958 : /*31633*/ OPC_MoveParent,
11959 : /*31634*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11960 : /*31636*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11961 : /*31639*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11962 : /*31642*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11963 : /*31645*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11964 : /*31648*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11965 : /*31651*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11966 : /*31654*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
11967 : /*31657*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
11968 : /*31660*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_O_V4_V4), 0,
11969 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
11970 : // Src: (intrinsic_wo_chain:v4f32 4872:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
11971 : // Dst: (IMAGE_SAMPLE_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
11972 : /*31678*/ /*Scope*/ 68, /*->31747*/
11973 : /*31679*/ OPC_CheckChild1Type, MVT::v8i32,
11974 : /*31681*/ OPC_RecordChild2, // #1 = $rsrc
11975 : /*31682*/ OPC_RecordChild3, // #2 = $sampler
11976 : /*31683*/ OPC_RecordChild4, // #3 = $dmask
11977 : /*31684*/ OPC_RecordChild5, // #4 = $unorm
11978 : /*31685*/ OPC_RecordChild6, // #5 = $r128
11979 : /*31686*/ OPC_RecordChild7, // #6 = $da
11980 : /*31687*/ OPC_MoveChild, 8,
11981 : /*31689*/ OPC_RecordNode, // #7 = $glc
11982 : /*31690*/ OPC_MoveParent,
11983 : /*31691*/ OPC_MoveChild, 9,
11984 : /*31693*/ OPC_RecordNode, // #8 = $slc
11985 : /*31694*/ OPC_MoveParent,
11986 : /*31695*/ OPC_MoveChild, 10,
11987 : /*31697*/ OPC_RecordNode, // #9 = $tfe
11988 : /*31698*/ OPC_MoveParent,
11989 : /*31699*/ OPC_MoveChild, 11,
11990 : /*31701*/ OPC_RecordNode, // #10 = $lwe
11991 : /*31702*/ OPC_MoveParent,
11992 : /*31703*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
11993 : /*31705*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
11994 : /*31708*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
11995 : /*31711*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
11996 : /*31714*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
11997 : /*31717*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
11998 : /*31720*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
11999 : /*31723*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12000 : /*31726*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12001 : /*31729*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_O_V4_V8), 0,
12002 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12003 : // Src: (intrinsic_wo_chain:v4f32 4872:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12004 : // Dst: (IMAGE_SAMPLE_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12005 : /*31747*/ /*Scope*/ 68, /*->31816*/
12006 : /*31748*/ OPC_CheckChild1Type, MVT::v16i32,
12007 : /*31750*/ OPC_RecordChild2, // #1 = $rsrc
12008 : /*31751*/ OPC_RecordChild3, // #2 = $sampler
12009 : /*31752*/ OPC_RecordChild4, // #3 = $dmask
12010 : /*31753*/ OPC_RecordChild5, // #4 = $unorm
12011 : /*31754*/ OPC_RecordChild6, // #5 = $r128
12012 : /*31755*/ OPC_RecordChild7, // #6 = $da
12013 : /*31756*/ OPC_MoveChild, 8,
12014 : /*31758*/ OPC_RecordNode, // #7 = $glc
12015 : /*31759*/ OPC_MoveParent,
12016 : /*31760*/ OPC_MoveChild, 9,
12017 : /*31762*/ OPC_RecordNode, // #8 = $slc
12018 : /*31763*/ OPC_MoveParent,
12019 : /*31764*/ OPC_MoveChild, 10,
12020 : /*31766*/ OPC_RecordNode, // #9 = $tfe
12021 : /*31767*/ OPC_MoveParent,
12022 : /*31768*/ OPC_MoveChild, 11,
12023 : /*31770*/ OPC_RecordNode, // #10 = $lwe
12024 : /*31771*/ OPC_MoveParent,
12025 : /*31772*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12026 : /*31774*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12027 : /*31777*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12028 : /*31780*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12029 : /*31783*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12030 : /*31786*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12031 : /*31789*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12032 : /*31792*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12033 : /*31795*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12034 : /*31798*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_O_V4_V16), 0,
12035 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12036 : // Src: (intrinsic_wo_chain:v4f32 4872:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12037 : // Dst: (IMAGE_SAMPLE_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12038 : /*31816*/ 0, /*End of Scope*/
12039 : /*31817*/ /*Scope*/ 95|128,2/*351*/, /*->32170*/
12040 : /*31819*/ OPC_CheckChild0Integer, 127|128,37/*4863*/,
12041 : /*31822*/ OPC_RecordChild1, // #0 = $addr
12042 : /*31823*/ OPC_Scope, 68, /*->31893*/ // 5 children in Scope
12043 : /*31825*/ OPC_CheckChild1Type, MVT::i32,
12044 : /*31827*/ OPC_RecordChild2, // #1 = $rsrc
12045 : /*31828*/ OPC_RecordChild3, // #2 = $sampler
12046 : /*31829*/ OPC_RecordChild4, // #3 = $dmask
12047 : /*31830*/ OPC_RecordChild5, // #4 = $unorm
12048 : /*31831*/ OPC_RecordChild6, // #5 = $r128
12049 : /*31832*/ OPC_RecordChild7, // #6 = $da
12050 : /*31833*/ OPC_MoveChild, 8,
12051 : /*31835*/ OPC_RecordNode, // #7 = $glc
12052 : /*31836*/ OPC_MoveParent,
12053 : /*31837*/ OPC_MoveChild, 9,
12054 : /*31839*/ OPC_RecordNode, // #8 = $slc
12055 : /*31840*/ OPC_MoveParent,
12056 : /*31841*/ OPC_MoveChild, 10,
12057 : /*31843*/ OPC_RecordNode, // #9 = $tfe
12058 : /*31844*/ OPC_MoveParent,
12059 : /*31845*/ OPC_MoveChild, 11,
12060 : /*31847*/ OPC_RecordNode, // #10 = $lwe
12061 : /*31848*/ OPC_MoveParent,
12062 : /*31849*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12063 : /*31851*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12064 : /*31854*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12065 : /*31857*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12066 : /*31860*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12067 : /*31863*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12068 : /*31866*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12069 : /*31869*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12070 : /*31872*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12071 : /*31875*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CL_O_V4_V1), 0,
12072 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12073 : // Src: (intrinsic_wo_chain:v4f32 4863:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12074 : // Dst: (IMAGE_SAMPLE_CL_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12075 : /*31893*/ /*Scope*/ 68, /*->31962*/
12076 : /*31894*/ OPC_CheckChild1Type, MVT::v2i32,
12077 : /*31896*/ OPC_RecordChild2, // #1 = $rsrc
12078 : /*31897*/ OPC_RecordChild3, // #2 = $sampler
12079 : /*31898*/ OPC_RecordChild4, // #3 = $dmask
12080 : /*31899*/ OPC_RecordChild5, // #4 = $unorm
12081 : /*31900*/ OPC_RecordChild6, // #5 = $r128
12082 : /*31901*/ OPC_RecordChild7, // #6 = $da
12083 : /*31902*/ OPC_MoveChild, 8,
12084 : /*31904*/ OPC_RecordNode, // #7 = $glc
12085 : /*31905*/ OPC_MoveParent,
12086 : /*31906*/ OPC_MoveChild, 9,
12087 : /*31908*/ OPC_RecordNode, // #8 = $slc
12088 : /*31909*/ OPC_MoveParent,
12089 : /*31910*/ OPC_MoveChild, 10,
12090 : /*31912*/ OPC_RecordNode, // #9 = $tfe
12091 : /*31913*/ OPC_MoveParent,
12092 : /*31914*/ OPC_MoveChild, 11,
12093 : /*31916*/ OPC_RecordNode, // #10 = $lwe
12094 : /*31917*/ OPC_MoveParent,
12095 : /*31918*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12096 : /*31920*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12097 : /*31923*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12098 : /*31926*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12099 : /*31929*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12100 : /*31932*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12101 : /*31935*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12102 : /*31938*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12103 : /*31941*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12104 : /*31944*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2), 0,
12105 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12106 : // Src: (intrinsic_wo_chain:v4f32 4863:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12107 : // Dst: (IMAGE_SAMPLE_CL_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12108 : /*31962*/ /*Scope*/ 68, /*->32031*/
12109 : /*31963*/ OPC_CheckChild1Type, MVT::v4i32,
12110 : /*31965*/ OPC_RecordChild2, // #1 = $rsrc
12111 : /*31966*/ OPC_RecordChild3, // #2 = $sampler
12112 : /*31967*/ OPC_RecordChild4, // #3 = $dmask
12113 : /*31968*/ OPC_RecordChild5, // #4 = $unorm
12114 : /*31969*/ OPC_RecordChild6, // #5 = $r128
12115 : /*31970*/ OPC_RecordChild7, // #6 = $da
12116 : /*31971*/ OPC_MoveChild, 8,
12117 : /*31973*/ OPC_RecordNode, // #7 = $glc
12118 : /*31974*/ OPC_MoveParent,
12119 : /*31975*/ OPC_MoveChild, 9,
12120 : /*31977*/ OPC_RecordNode, // #8 = $slc
12121 : /*31978*/ OPC_MoveParent,
12122 : /*31979*/ OPC_MoveChild, 10,
12123 : /*31981*/ OPC_RecordNode, // #9 = $tfe
12124 : /*31982*/ OPC_MoveParent,
12125 : /*31983*/ OPC_MoveChild, 11,
12126 : /*31985*/ OPC_RecordNode, // #10 = $lwe
12127 : /*31986*/ OPC_MoveParent,
12128 : /*31987*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12129 : /*31989*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12130 : /*31992*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12131 : /*31995*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12132 : /*31998*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12133 : /*32001*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12134 : /*32004*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12135 : /*32007*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12136 : /*32010*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12137 : /*32013*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4), 0,
12138 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12139 : // Src: (intrinsic_wo_chain:v4f32 4863:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12140 : // Dst: (IMAGE_SAMPLE_CL_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12141 : /*32031*/ /*Scope*/ 68, /*->32100*/
12142 : /*32032*/ OPC_CheckChild1Type, MVT::v8i32,
12143 : /*32034*/ OPC_RecordChild2, // #1 = $rsrc
12144 : /*32035*/ OPC_RecordChild3, // #2 = $sampler
12145 : /*32036*/ OPC_RecordChild4, // #3 = $dmask
12146 : /*32037*/ OPC_RecordChild5, // #4 = $unorm
12147 : /*32038*/ OPC_RecordChild6, // #5 = $r128
12148 : /*32039*/ OPC_RecordChild7, // #6 = $da
12149 : /*32040*/ OPC_MoveChild, 8,
12150 : /*32042*/ OPC_RecordNode, // #7 = $glc
12151 : /*32043*/ OPC_MoveParent,
12152 : /*32044*/ OPC_MoveChild, 9,
12153 : /*32046*/ OPC_RecordNode, // #8 = $slc
12154 : /*32047*/ OPC_MoveParent,
12155 : /*32048*/ OPC_MoveChild, 10,
12156 : /*32050*/ OPC_RecordNode, // #9 = $tfe
12157 : /*32051*/ OPC_MoveParent,
12158 : /*32052*/ OPC_MoveChild, 11,
12159 : /*32054*/ OPC_RecordNode, // #10 = $lwe
12160 : /*32055*/ OPC_MoveParent,
12161 : /*32056*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12162 : /*32058*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12163 : /*32061*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12164 : /*32064*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12165 : /*32067*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12166 : /*32070*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12167 : /*32073*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12168 : /*32076*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12169 : /*32079*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12170 : /*32082*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8), 0,
12171 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12172 : // Src: (intrinsic_wo_chain:v4f32 4863:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12173 : // Dst: (IMAGE_SAMPLE_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12174 : /*32100*/ /*Scope*/ 68, /*->32169*/
12175 : /*32101*/ OPC_CheckChild1Type, MVT::v16i32,
12176 : /*32103*/ OPC_RecordChild2, // #1 = $rsrc
12177 : /*32104*/ OPC_RecordChild3, // #2 = $sampler
12178 : /*32105*/ OPC_RecordChild4, // #3 = $dmask
12179 : /*32106*/ OPC_RecordChild5, // #4 = $unorm
12180 : /*32107*/ OPC_RecordChild6, // #5 = $r128
12181 : /*32108*/ OPC_RecordChild7, // #6 = $da
12182 : /*32109*/ OPC_MoveChild, 8,
12183 : /*32111*/ OPC_RecordNode, // #7 = $glc
12184 : /*32112*/ OPC_MoveParent,
12185 : /*32113*/ OPC_MoveChild, 9,
12186 : /*32115*/ OPC_RecordNode, // #8 = $slc
12187 : /*32116*/ OPC_MoveParent,
12188 : /*32117*/ OPC_MoveChild, 10,
12189 : /*32119*/ OPC_RecordNode, // #9 = $tfe
12190 : /*32120*/ OPC_MoveParent,
12191 : /*32121*/ OPC_MoveChild, 11,
12192 : /*32123*/ OPC_RecordNode, // #10 = $lwe
12193 : /*32124*/ OPC_MoveParent,
12194 : /*32125*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12195 : /*32127*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12196 : /*32130*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12197 : /*32133*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12198 : /*32136*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12199 : /*32139*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12200 : /*32142*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12201 : /*32145*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12202 : /*32148*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12203 : /*32151*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CL_O_V4_V16), 0,
12204 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12205 : // Src: (intrinsic_wo_chain:v4f32 4863:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12206 : // Dst: (IMAGE_SAMPLE_CL_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12207 : /*32169*/ 0, /*End of Scope*/
12208 : /*32170*/ /*Scope*/ 95|128,2/*351*/, /*->32523*/
12209 : /*32172*/ OPC_CheckChild0Integer, 3|128,38/*4867*/,
12210 : /*32175*/ OPC_RecordChild1, // #0 = $addr
12211 : /*32176*/ OPC_Scope, 68, /*->32246*/ // 5 children in Scope
12212 : /*32178*/ OPC_CheckChild1Type, MVT::i32,
12213 : /*32180*/ OPC_RecordChild2, // #1 = $rsrc
12214 : /*32181*/ OPC_RecordChild3, // #2 = $sampler
12215 : /*32182*/ OPC_RecordChild4, // #3 = $dmask
12216 : /*32183*/ OPC_RecordChild5, // #4 = $unorm
12217 : /*32184*/ OPC_RecordChild6, // #5 = $r128
12218 : /*32185*/ OPC_RecordChild7, // #6 = $da
12219 : /*32186*/ OPC_MoveChild, 8,
12220 : /*32188*/ OPC_RecordNode, // #7 = $glc
12221 : /*32189*/ OPC_MoveParent,
12222 : /*32190*/ OPC_MoveChild, 9,
12223 : /*32192*/ OPC_RecordNode, // #8 = $slc
12224 : /*32193*/ OPC_MoveParent,
12225 : /*32194*/ OPC_MoveChild, 10,
12226 : /*32196*/ OPC_RecordNode, // #9 = $tfe
12227 : /*32197*/ OPC_MoveParent,
12228 : /*32198*/ OPC_MoveChild, 11,
12229 : /*32200*/ OPC_RecordNode, // #10 = $lwe
12230 : /*32201*/ OPC_MoveParent,
12231 : /*32202*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12232 : /*32204*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12233 : /*32207*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12234 : /*32210*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12235 : /*32213*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12236 : /*32216*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12237 : /*32219*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12238 : /*32222*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12239 : /*32225*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12240 : /*32228*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_O_V4_V1), 0,
12241 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12242 : // Src: (intrinsic_wo_chain:v4f32 4867:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12243 : // Dst: (IMAGE_SAMPLE_D_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12244 : /*32246*/ /*Scope*/ 68, /*->32315*/
12245 : /*32247*/ OPC_CheckChild1Type, MVT::v2i32,
12246 : /*32249*/ OPC_RecordChild2, // #1 = $rsrc
12247 : /*32250*/ OPC_RecordChild3, // #2 = $sampler
12248 : /*32251*/ OPC_RecordChild4, // #3 = $dmask
12249 : /*32252*/ OPC_RecordChild5, // #4 = $unorm
12250 : /*32253*/ OPC_RecordChild6, // #5 = $r128
12251 : /*32254*/ OPC_RecordChild7, // #6 = $da
12252 : /*32255*/ OPC_MoveChild, 8,
12253 : /*32257*/ OPC_RecordNode, // #7 = $glc
12254 : /*32258*/ OPC_MoveParent,
12255 : /*32259*/ OPC_MoveChild, 9,
12256 : /*32261*/ OPC_RecordNode, // #8 = $slc
12257 : /*32262*/ OPC_MoveParent,
12258 : /*32263*/ OPC_MoveChild, 10,
12259 : /*32265*/ OPC_RecordNode, // #9 = $tfe
12260 : /*32266*/ OPC_MoveParent,
12261 : /*32267*/ OPC_MoveChild, 11,
12262 : /*32269*/ OPC_RecordNode, // #10 = $lwe
12263 : /*32270*/ OPC_MoveParent,
12264 : /*32271*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12265 : /*32273*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12266 : /*32276*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12267 : /*32279*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12268 : /*32282*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12269 : /*32285*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12270 : /*32288*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12271 : /*32291*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12272 : /*32294*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12273 : /*32297*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_O_V4_V2), 0,
12274 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12275 : // Src: (intrinsic_wo_chain:v4f32 4867:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12276 : // Dst: (IMAGE_SAMPLE_D_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12277 : /*32315*/ /*Scope*/ 68, /*->32384*/
12278 : /*32316*/ OPC_CheckChild1Type, MVT::v4i32,
12279 : /*32318*/ OPC_RecordChild2, // #1 = $rsrc
12280 : /*32319*/ OPC_RecordChild3, // #2 = $sampler
12281 : /*32320*/ OPC_RecordChild4, // #3 = $dmask
12282 : /*32321*/ OPC_RecordChild5, // #4 = $unorm
12283 : /*32322*/ OPC_RecordChild6, // #5 = $r128
12284 : /*32323*/ OPC_RecordChild7, // #6 = $da
12285 : /*32324*/ OPC_MoveChild, 8,
12286 : /*32326*/ OPC_RecordNode, // #7 = $glc
12287 : /*32327*/ OPC_MoveParent,
12288 : /*32328*/ OPC_MoveChild, 9,
12289 : /*32330*/ OPC_RecordNode, // #8 = $slc
12290 : /*32331*/ OPC_MoveParent,
12291 : /*32332*/ OPC_MoveChild, 10,
12292 : /*32334*/ OPC_RecordNode, // #9 = $tfe
12293 : /*32335*/ OPC_MoveParent,
12294 : /*32336*/ OPC_MoveChild, 11,
12295 : /*32338*/ OPC_RecordNode, // #10 = $lwe
12296 : /*32339*/ OPC_MoveParent,
12297 : /*32340*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12298 : /*32342*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12299 : /*32345*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12300 : /*32348*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12301 : /*32351*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12302 : /*32354*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12303 : /*32357*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12304 : /*32360*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12305 : /*32363*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12306 : /*32366*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_O_V4_V4), 0,
12307 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12308 : // Src: (intrinsic_wo_chain:v4f32 4867:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12309 : // Dst: (IMAGE_SAMPLE_D_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12310 : /*32384*/ /*Scope*/ 68, /*->32453*/
12311 : /*32385*/ OPC_CheckChild1Type, MVT::v8i32,
12312 : /*32387*/ OPC_RecordChild2, // #1 = $rsrc
12313 : /*32388*/ OPC_RecordChild3, // #2 = $sampler
12314 : /*32389*/ OPC_RecordChild4, // #3 = $dmask
12315 : /*32390*/ OPC_RecordChild5, // #4 = $unorm
12316 : /*32391*/ OPC_RecordChild6, // #5 = $r128
12317 : /*32392*/ OPC_RecordChild7, // #6 = $da
12318 : /*32393*/ OPC_MoveChild, 8,
12319 : /*32395*/ OPC_RecordNode, // #7 = $glc
12320 : /*32396*/ OPC_MoveParent,
12321 : /*32397*/ OPC_MoveChild, 9,
12322 : /*32399*/ OPC_RecordNode, // #8 = $slc
12323 : /*32400*/ OPC_MoveParent,
12324 : /*32401*/ OPC_MoveChild, 10,
12325 : /*32403*/ OPC_RecordNode, // #9 = $tfe
12326 : /*32404*/ OPC_MoveParent,
12327 : /*32405*/ OPC_MoveChild, 11,
12328 : /*32407*/ OPC_RecordNode, // #10 = $lwe
12329 : /*32408*/ OPC_MoveParent,
12330 : /*32409*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12331 : /*32411*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12332 : /*32414*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12333 : /*32417*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12334 : /*32420*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12335 : /*32423*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12336 : /*32426*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12337 : /*32429*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12338 : /*32432*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12339 : /*32435*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_O_V4_V8), 0,
12340 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12341 : // Src: (intrinsic_wo_chain:v4f32 4867:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12342 : // Dst: (IMAGE_SAMPLE_D_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12343 : /*32453*/ /*Scope*/ 68, /*->32522*/
12344 : /*32454*/ OPC_CheckChild1Type, MVT::v16i32,
12345 : /*32456*/ OPC_RecordChild2, // #1 = $rsrc
12346 : /*32457*/ OPC_RecordChild3, // #2 = $sampler
12347 : /*32458*/ OPC_RecordChild4, // #3 = $dmask
12348 : /*32459*/ OPC_RecordChild5, // #4 = $unorm
12349 : /*32460*/ OPC_RecordChild6, // #5 = $r128
12350 : /*32461*/ OPC_RecordChild7, // #6 = $da
12351 : /*32462*/ OPC_MoveChild, 8,
12352 : /*32464*/ OPC_RecordNode, // #7 = $glc
12353 : /*32465*/ OPC_MoveParent,
12354 : /*32466*/ OPC_MoveChild, 9,
12355 : /*32468*/ OPC_RecordNode, // #8 = $slc
12356 : /*32469*/ OPC_MoveParent,
12357 : /*32470*/ OPC_MoveChild, 10,
12358 : /*32472*/ OPC_RecordNode, // #9 = $tfe
12359 : /*32473*/ OPC_MoveParent,
12360 : /*32474*/ OPC_MoveChild, 11,
12361 : /*32476*/ OPC_RecordNode, // #10 = $lwe
12362 : /*32477*/ OPC_MoveParent,
12363 : /*32478*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12364 : /*32480*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12365 : /*32483*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12366 : /*32486*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12367 : /*32489*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12368 : /*32492*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12369 : /*32495*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12370 : /*32498*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12371 : /*32501*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12372 : /*32504*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_O_V4_V16), 0,
12373 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12374 : // Src: (intrinsic_wo_chain:v4f32 4867:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12375 : // Dst: (IMAGE_SAMPLE_D_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12376 : /*32522*/ 0, /*End of Scope*/
12377 : /*32523*/ /*Scope*/ 95|128,2/*351*/, /*->32876*/
12378 : /*32525*/ OPC_CheckChild0Integer, 2|128,38/*4866*/,
12379 : /*32528*/ OPC_RecordChild1, // #0 = $addr
12380 : /*32529*/ OPC_Scope, 68, /*->32599*/ // 5 children in Scope
12381 : /*32531*/ OPC_CheckChild1Type, MVT::i32,
12382 : /*32533*/ OPC_RecordChild2, // #1 = $rsrc
12383 : /*32534*/ OPC_RecordChild3, // #2 = $sampler
12384 : /*32535*/ OPC_RecordChild4, // #3 = $dmask
12385 : /*32536*/ OPC_RecordChild5, // #4 = $unorm
12386 : /*32537*/ OPC_RecordChild6, // #5 = $r128
12387 : /*32538*/ OPC_RecordChild7, // #6 = $da
12388 : /*32539*/ OPC_MoveChild, 8,
12389 : /*32541*/ OPC_RecordNode, // #7 = $glc
12390 : /*32542*/ OPC_MoveParent,
12391 : /*32543*/ OPC_MoveChild, 9,
12392 : /*32545*/ OPC_RecordNode, // #8 = $slc
12393 : /*32546*/ OPC_MoveParent,
12394 : /*32547*/ OPC_MoveChild, 10,
12395 : /*32549*/ OPC_RecordNode, // #9 = $tfe
12396 : /*32550*/ OPC_MoveParent,
12397 : /*32551*/ OPC_MoveChild, 11,
12398 : /*32553*/ OPC_RecordNode, // #10 = $lwe
12399 : /*32554*/ OPC_MoveParent,
12400 : /*32555*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12401 : /*32557*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12402 : /*32560*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12403 : /*32563*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12404 : /*32566*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12405 : /*32569*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12406 : /*32572*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12407 : /*32575*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12408 : /*32578*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12409 : /*32581*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V1), 0,
12410 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12411 : // Src: (intrinsic_wo_chain:v4f32 4866:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12412 : // Dst: (IMAGE_SAMPLE_D_CL_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12413 : /*32599*/ /*Scope*/ 68, /*->32668*/
12414 : /*32600*/ OPC_CheckChild1Type, MVT::v2i32,
12415 : /*32602*/ OPC_RecordChild2, // #1 = $rsrc
12416 : /*32603*/ OPC_RecordChild3, // #2 = $sampler
12417 : /*32604*/ OPC_RecordChild4, // #3 = $dmask
12418 : /*32605*/ OPC_RecordChild5, // #4 = $unorm
12419 : /*32606*/ OPC_RecordChild6, // #5 = $r128
12420 : /*32607*/ OPC_RecordChild7, // #6 = $da
12421 : /*32608*/ OPC_MoveChild, 8,
12422 : /*32610*/ OPC_RecordNode, // #7 = $glc
12423 : /*32611*/ OPC_MoveParent,
12424 : /*32612*/ OPC_MoveChild, 9,
12425 : /*32614*/ OPC_RecordNode, // #8 = $slc
12426 : /*32615*/ OPC_MoveParent,
12427 : /*32616*/ OPC_MoveChild, 10,
12428 : /*32618*/ OPC_RecordNode, // #9 = $tfe
12429 : /*32619*/ OPC_MoveParent,
12430 : /*32620*/ OPC_MoveChild, 11,
12431 : /*32622*/ OPC_RecordNode, // #10 = $lwe
12432 : /*32623*/ OPC_MoveParent,
12433 : /*32624*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12434 : /*32626*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12435 : /*32629*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12436 : /*32632*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12437 : /*32635*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12438 : /*32638*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12439 : /*32641*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12440 : /*32644*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12441 : /*32647*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12442 : /*32650*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V2), 0,
12443 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12444 : // Src: (intrinsic_wo_chain:v4f32 4866:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12445 : // Dst: (IMAGE_SAMPLE_D_CL_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12446 : /*32668*/ /*Scope*/ 68, /*->32737*/
12447 : /*32669*/ OPC_CheckChild1Type, MVT::v4i32,
12448 : /*32671*/ OPC_RecordChild2, // #1 = $rsrc
12449 : /*32672*/ OPC_RecordChild3, // #2 = $sampler
12450 : /*32673*/ OPC_RecordChild4, // #3 = $dmask
12451 : /*32674*/ OPC_RecordChild5, // #4 = $unorm
12452 : /*32675*/ OPC_RecordChild6, // #5 = $r128
12453 : /*32676*/ OPC_RecordChild7, // #6 = $da
12454 : /*32677*/ OPC_MoveChild, 8,
12455 : /*32679*/ OPC_RecordNode, // #7 = $glc
12456 : /*32680*/ OPC_MoveParent,
12457 : /*32681*/ OPC_MoveChild, 9,
12458 : /*32683*/ OPC_RecordNode, // #8 = $slc
12459 : /*32684*/ OPC_MoveParent,
12460 : /*32685*/ OPC_MoveChild, 10,
12461 : /*32687*/ OPC_RecordNode, // #9 = $tfe
12462 : /*32688*/ OPC_MoveParent,
12463 : /*32689*/ OPC_MoveChild, 11,
12464 : /*32691*/ OPC_RecordNode, // #10 = $lwe
12465 : /*32692*/ OPC_MoveParent,
12466 : /*32693*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12467 : /*32695*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12468 : /*32698*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12469 : /*32701*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12470 : /*32704*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12471 : /*32707*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12472 : /*32710*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12473 : /*32713*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12474 : /*32716*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12475 : /*32719*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4), 0,
12476 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12477 : // Src: (intrinsic_wo_chain:v4f32 4866:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12478 : // Dst: (IMAGE_SAMPLE_D_CL_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12479 : /*32737*/ /*Scope*/ 68, /*->32806*/
12480 : /*32738*/ OPC_CheckChild1Type, MVT::v8i32,
12481 : /*32740*/ OPC_RecordChild2, // #1 = $rsrc
12482 : /*32741*/ OPC_RecordChild3, // #2 = $sampler
12483 : /*32742*/ OPC_RecordChild4, // #3 = $dmask
12484 : /*32743*/ OPC_RecordChild5, // #4 = $unorm
12485 : /*32744*/ OPC_RecordChild6, // #5 = $r128
12486 : /*32745*/ OPC_RecordChild7, // #6 = $da
12487 : /*32746*/ OPC_MoveChild, 8,
12488 : /*32748*/ OPC_RecordNode, // #7 = $glc
12489 : /*32749*/ OPC_MoveParent,
12490 : /*32750*/ OPC_MoveChild, 9,
12491 : /*32752*/ OPC_RecordNode, // #8 = $slc
12492 : /*32753*/ OPC_MoveParent,
12493 : /*32754*/ OPC_MoveChild, 10,
12494 : /*32756*/ OPC_RecordNode, // #9 = $tfe
12495 : /*32757*/ OPC_MoveParent,
12496 : /*32758*/ OPC_MoveChild, 11,
12497 : /*32760*/ OPC_RecordNode, // #10 = $lwe
12498 : /*32761*/ OPC_MoveParent,
12499 : /*32762*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12500 : /*32764*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12501 : /*32767*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12502 : /*32770*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12503 : /*32773*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12504 : /*32776*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12505 : /*32779*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12506 : /*32782*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12507 : /*32785*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12508 : /*32788*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8), 0,
12509 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12510 : // Src: (intrinsic_wo_chain:v4f32 4866:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12511 : // Dst: (IMAGE_SAMPLE_D_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12512 : /*32806*/ /*Scope*/ 68, /*->32875*/
12513 : /*32807*/ OPC_CheckChild1Type, MVT::v16i32,
12514 : /*32809*/ OPC_RecordChild2, // #1 = $rsrc
12515 : /*32810*/ OPC_RecordChild3, // #2 = $sampler
12516 : /*32811*/ OPC_RecordChild4, // #3 = $dmask
12517 : /*32812*/ OPC_RecordChild5, // #4 = $unorm
12518 : /*32813*/ OPC_RecordChild6, // #5 = $r128
12519 : /*32814*/ OPC_RecordChild7, // #6 = $da
12520 : /*32815*/ OPC_MoveChild, 8,
12521 : /*32817*/ OPC_RecordNode, // #7 = $glc
12522 : /*32818*/ OPC_MoveParent,
12523 : /*32819*/ OPC_MoveChild, 9,
12524 : /*32821*/ OPC_RecordNode, // #8 = $slc
12525 : /*32822*/ OPC_MoveParent,
12526 : /*32823*/ OPC_MoveChild, 10,
12527 : /*32825*/ OPC_RecordNode, // #9 = $tfe
12528 : /*32826*/ OPC_MoveParent,
12529 : /*32827*/ OPC_MoveChild, 11,
12530 : /*32829*/ OPC_RecordNode, // #10 = $lwe
12531 : /*32830*/ OPC_MoveParent,
12532 : /*32831*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12533 : /*32833*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12534 : /*32836*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12535 : /*32839*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12536 : /*32842*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12537 : /*32845*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12538 : /*32848*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12539 : /*32851*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12540 : /*32854*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12541 : /*32857*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V16), 0,
12542 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12543 : // Src: (intrinsic_wo_chain:v4f32 4866:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12544 : // Dst: (IMAGE_SAMPLE_D_CL_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12545 : /*32875*/ 0, /*End of Scope*/
12546 : /*32876*/ /*Scope*/ 95|128,2/*351*/, /*->33229*/
12547 : /*32878*/ OPC_CheckChild0Integer, 5|128,38/*4869*/,
12548 : /*32881*/ OPC_RecordChild1, // #0 = $addr
12549 : /*32882*/ OPC_Scope, 68, /*->32952*/ // 5 children in Scope
12550 : /*32884*/ OPC_CheckChild1Type, MVT::i32,
12551 : /*32886*/ OPC_RecordChild2, // #1 = $rsrc
12552 : /*32887*/ OPC_RecordChild3, // #2 = $sampler
12553 : /*32888*/ OPC_RecordChild4, // #3 = $dmask
12554 : /*32889*/ OPC_RecordChild5, // #4 = $unorm
12555 : /*32890*/ OPC_RecordChild6, // #5 = $r128
12556 : /*32891*/ OPC_RecordChild7, // #6 = $da
12557 : /*32892*/ OPC_MoveChild, 8,
12558 : /*32894*/ OPC_RecordNode, // #7 = $glc
12559 : /*32895*/ OPC_MoveParent,
12560 : /*32896*/ OPC_MoveChild, 9,
12561 : /*32898*/ OPC_RecordNode, // #8 = $slc
12562 : /*32899*/ OPC_MoveParent,
12563 : /*32900*/ OPC_MoveChild, 10,
12564 : /*32902*/ OPC_RecordNode, // #9 = $tfe
12565 : /*32903*/ OPC_MoveParent,
12566 : /*32904*/ OPC_MoveChild, 11,
12567 : /*32906*/ OPC_RecordNode, // #10 = $lwe
12568 : /*32907*/ OPC_MoveParent,
12569 : /*32908*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12570 : /*32910*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12571 : /*32913*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12572 : /*32916*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12573 : /*32919*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12574 : /*32922*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12575 : /*32925*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12576 : /*32928*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12577 : /*32931*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12578 : /*32934*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_O_V4_V1), 0,
12579 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12580 : // Src: (intrinsic_wo_chain:v4f32 4869:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12581 : // Dst: (IMAGE_SAMPLE_L_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12582 : /*32952*/ /*Scope*/ 68, /*->33021*/
12583 : /*32953*/ OPC_CheckChild1Type, MVT::v2i32,
12584 : /*32955*/ OPC_RecordChild2, // #1 = $rsrc
12585 : /*32956*/ OPC_RecordChild3, // #2 = $sampler
12586 : /*32957*/ OPC_RecordChild4, // #3 = $dmask
12587 : /*32958*/ OPC_RecordChild5, // #4 = $unorm
12588 : /*32959*/ OPC_RecordChild6, // #5 = $r128
12589 : /*32960*/ OPC_RecordChild7, // #6 = $da
12590 : /*32961*/ OPC_MoveChild, 8,
12591 : /*32963*/ OPC_RecordNode, // #7 = $glc
12592 : /*32964*/ OPC_MoveParent,
12593 : /*32965*/ OPC_MoveChild, 9,
12594 : /*32967*/ OPC_RecordNode, // #8 = $slc
12595 : /*32968*/ OPC_MoveParent,
12596 : /*32969*/ OPC_MoveChild, 10,
12597 : /*32971*/ OPC_RecordNode, // #9 = $tfe
12598 : /*32972*/ OPC_MoveParent,
12599 : /*32973*/ OPC_MoveChild, 11,
12600 : /*32975*/ OPC_RecordNode, // #10 = $lwe
12601 : /*32976*/ OPC_MoveParent,
12602 : /*32977*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12603 : /*32979*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12604 : /*32982*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12605 : /*32985*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12606 : /*32988*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12607 : /*32991*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12608 : /*32994*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12609 : /*32997*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12610 : /*33000*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12611 : /*33003*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_O_V4_V2), 0,
12612 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12613 : // Src: (intrinsic_wo_chain:v4f32 4869:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12614 : // Dst: (IMAGE_SAMPLE_L_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12615 : /*33021*/ /*Scope*/ 68, /*->33090*/
12616 : /*33022*/ OPC_CheckChild1Type, MVT::v4i32,
12617 : /*33024*/ OPC_RecordChild2, // #1 = $rsrc
12618 : /*33025*/ OPC_RecordChild3, // #2 = $sampler
12619 : /*33026*/ OPC_RecordChild4, // #3 = $dmask
12620 : /*33027*/ OPC_RecordChild5, // #4 = $unorm
12621 : /*33028*/ OPC_RecordChild6, // #5 = $r128
12622 : /*33029*/ OPC_RecordChild7, // #6 = $da
12623 : /*33030*/ OPC_MoveChild, 8,
12624 : /*33032*/ OPC_RecordNode, // #7 = $glc
12625 : /*33033*/ OPC_MoveParent,
12626 : /*33034*/ OPC_MoveChild, 9,
12627 : /*33036*/ OPC_RecordNode, // #8 = $slc
12628 : /*33037*/ OPC_MoveParent,
12629 : /*33038*/ OPC_MoveChild, 10,
12630 : /*33040*/ OPC_RecordNode, // #9 = $tfe
12631 : /*33041*/ OPC_MoveParent,
12632 : /*33042*/ OPC_MoveChild, 11,
12633 : /*33044*/ OPC_RecordNode, // #10 = $lwe
12634 : /*33045*/ OPC_MoveParent,
12635 : /*33046*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12636 : /*33048*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12637 : /*33051*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12638 : /*33054*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12639 : /*33057*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12640 : /*33060*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12641 : /*33063*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12642 : /*33066*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12643 : /*33069*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12644 : /*33072*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_O_V4_V4), 0,
12645 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12646 : // Src: (intrinsic_wo_chain:v4f32 4869:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12647 : // Dst: (IMAGE_SAMPLE_L_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12648 : /*33090*/ /*Scope*/ 68, /*->33159*/
12649 : /*33091*/ OPC_CheckChild1Type, MVT::v8i32,
12650 : /*33093*/ OPC_RecordChild2, // #1 = $rsrc
12651 : /*33094*/ OPC_RecordChild3, // #2 = $sampler
12652 : /*33095*/ OPC_RecordChild4, // #3 = $dmask
12653 : /*33096*/ OPC_RecordChild5, // #4 = $unorm
12654 : /*33097*/ OPC_RecordChild6, // #5 = $r128
12655 : /*33098*/ OPC_RecordChild7, // #6 = $da
12656 : /*33099*/ OPC_MoveChild, 8,
12657 : /*33101*/ OPC_RecordNode, // #7 = $glc
12658 : /*33102*/ OPC_MoveParent,
12659 : /*33103*/ OPC_MoveChild, 9,
12660 : /*33105*/ OPC_RecordNode, // #8 = $slc
12661 : /*33106*/ OPC_MoveParent,
12662 : /*33107*/ OPC_MoveChild, 10,
12663 : /*33109*/ OPC_RecordNode, // #9 = $tfe
12664 : /*33110*/ OPC_MoveParent,
12665 : /*33111*/ OPC_MoveChild, 11,
12666 : /*33113*/ OPC_RecordNode, // #10 = $lwe
12667 : /*33114*/ OPC_MoveParent,
12668 : /*33115*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12669 : /*33117*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12670 : /*33120*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12671 : /*33123*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12672 : /*33126*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12673 : /*33129*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12674 : /*33132*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12675 : /*33135*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12676 : /*33138*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12677 : /*33141*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_O_V4_V8), 0,
12678 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12679 : // Src: (intrinsic_wo_chain:v4f32 4869:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12680 : // Dst: (IMAGE_SAMPLE_L_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12681 : /*33159*/ /*Scope*/ 68, /*->33228*/
12682 : /*33160*/ OPC_CheckChild1Type, MVT::v16i32,
12683 : /*33162*/ OPC_RecordChild2, // #1 = $rsrc
12684 : /*33163*/ OPC_RecordChild3, // #2 = $sampler
12685 : /*33164*/ OPC_RecordChild4, // #3 = $dmask
12686 : /*33165*/ OPC_RecordChild5, // #4 = $unorm
12687 : /*33166*/ OPC_RecordChild6, // #5 = $r128
12688 : /*33167*/ OPC_RecordChild7, // #6 = $da
12689 : /*33168*/ OPC_MoveChild, 8,
12690 : /*33170*/ OPC_RecordNode, // #7 = $glc
12691 : /*33171*/ OPC_MoveParent,
12692 : /*33172*/ OPC_MoveChild, 9,
12693 : /*33174*/ OPC_RecordNode, // #8 = $slc
12694 : /*33175*/ OPC_MoveParent,
12695 : /*33176*/ OPC_MoveChild, 10,
12696 : /*33178*/ OPC_RecordNode, // #9 = $tfe
12697 : /*33179*/ OPC_MoveParent,
12698 : /*33180*/ OPC_MoveChild, 11,
12699 : /*33182*/ OPC_RecordNode, // #10 = $lwe
12700 : /*33183*/ OPC_MoveParent,
12701 : /*33184*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12702 : /*33186*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12703 : /*33189*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12704 : /*33192*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12705 : /*33195*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12706 : /*33198*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12707 : /*33201*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12708 : /*33204*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12709 : /*33207*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12710 : /*33210*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_O_V4_V16), 0,
12711 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12712 : // Src: (intrinsic_wo_chain:v4f32 4869:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12713 : // Dst: (IMAGE_SAMPLE_L_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12714 : /*33228*/ 0, /*End of Scope*/
12715 : /*33229*/ /*Scope*/ 95|128,2/*351*/, /*->33582*/
12716 : /*33231*/ OPC_CheckChild0Integer, 101|128,37/*4837*/,
12717 : /*33234*/ OPC_RecordChild1, // #0 = $addr
12718 : /*33235*/ OPC_Scope, 68, /*->33305*/ // 5 children in Scope
12719 : /*33237*/ OPC_CheckChild1Type, MVT::i32,
12720 : /*33239*/ OPC_RecordChild2, // #1 = $rsrc
12721 : /*33240*/ OPC_RecordChild3, // #2 = $sampler
12722 : /*33241*/ OPC_RecordChild4, // #3 = $dmask
12723 : /*33242*/ OPC_RecordChild5, // #4 = $unorm
12724 : /*33243*/ OPC_RecordChild6, // #5 = $r128
12725 : /*33244*/ OPC_RecordChild7, // #6 = $da
12726 : /*33245*/ OPC_MoveChild, 8,
12727 : /*33247*/ OPC_RecordNode, // #7 = $glc
12728 : /*33248*/ OPC_MoveParent,
12729 : /*33249*/ OPC_MoveChild, 9,
12730 : /*33251*/ OPC_RecordNode, // #8 = $slc
12731 : /*33252*/ OPC_MoveParent,
12732 : /*33253*/ OPC_MoveChild, 10,
12733 : /*33255*/ OPC_RecordNode, // #9 = $tfe
12734 : /*33256*/ OPC_MoveParent,
12735 : /*33257*/ OPC_MoveChild, 11,
12736 : /*33259*/ OPC_RecordNode, // #10 = $lwe
12737 : /*33260*/ OPC_MoveParent,
12738 : /*33261*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12739 : /*33263*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12740 : /*33266*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12741 : /*33269*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12742 : /*33272*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12743 : /*33275*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12744 : /*33278*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12745 : /*33281*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12746 : /*33284*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12747 : /*33287*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_O_V4_V1), 0,
12748 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12749 : // Src: (intrinsic_wo_chain:v4f32 4837:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12750 : // Dst: (IMAGE_SAMPLE_B_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12751 : /*33305*/ /*Scope*/ 68, /*->33374*/
12752 : /*33306*/ OPC_CheckChild1Type, MVT::v2i32,
12753 : /*33308*/ OPC_RecordChild2, // #1 = $rsrc
12754 : /*33309*/ OPC_RecordChild3, // #2 = $sampler
12755 : /*33310*/ OPC_RecordChild4, // #3 = $dmask
12756 : /*33311*/ OPC_RecordChild5, // #4 = $unorm
12757 : /*33312*/ OPC_RecordChild6, // #5 = $r128
12758 : /*33313*/ OPC_RecordChild7, // #6 = $da
12759 : /*33314*/ OPC_MoveChild, 8,
12760 : /*33316*/ OPC_RecordNode, // #7 = $glc
12761 : /*33317*/ OPC_MoveParent,
12762 : /*33318*/ OPC_MoveChild, 9,
12763 : /*33320*/ OPC_RecordNode, // #8 = $slc
12764 : /*33321*/ OPC_MoveParent,
12765 : /*33322*/ OPC_MoveChild, 10,
12766 : /*33324*/ OPC_RecordNode, // #9 = $tfe
12767 : /*33325*/ OPC_MoveParent,
12768 : /*33326*/ OPC_MoveChild, 11,
12769 : /*33328*/ OPC_RecordNode, // #10 = $lwe
12770 : /*33329*/ OPC_MoveParent,
12771 : /*33330*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12772 : /*33332*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12773 : /*33335*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12774 : /*33338*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12775 : /*33341*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12776 : /*33344*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12777 : /*33347*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12778 : /*33350*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12779 : /*33353*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12780 : /*33356*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_O_V4_V2), 0,
12781 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12782 : // Src: (intrinsic_wo_chain:v4f32 4837:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12783 : // Dst: (IMAGE_SAMPLE_B_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12784 : /*33374*/ /*Scope*/ 68, /*->33443*/
12785 : /*33375*/ OPC_CheckChild1Type, MVT::v4i32,
12786 : /*33377*/ OPC_RecordChild2, // #1 = $rsrc
12787 : /*33378*/ OPC_RecordChild3, // #2 = $sampler
12788 : /*33379*/ OPC_RecordChild4, // #3 = $dmask
12789 : /*33380*/ OPC_RecordChild5, // #4 = $unorm
12790 : /*33381*/ OPC_RecordChild6, // #5 = $r128
12791 : /*33382*/ OPC_RecordChild7, // #6 = $da
12792 : /*33383*/ OPC_MoveChild, 8,
12793 : /*33385*/ OPC_RecordNode, // #7 = $glc
12794 : /*33386*/ OPC_MoveParent,
12795 : /*33387*/ OPC_MoveChild, 9,
12796 : /*33389*/ OPC_RecordNode, // #8 = $slc
12797 : /*33390*/ OPC_MoveParent,
12798 : /*33391*/ OPC_MoveChild, 10,
12799 : /*33393*/ OPC_RecordNode, // #9 = $tfe
12800 : /*33394*/ OPC_MoveParent,
12801 : /*33395*/ OPC_MoveChild, 11,
12802 : /*33397*/ OPC_RecordNode, // #10 = $lwe
12803 : /*33398*/ OPC_MoveParent,
12804 : /*33399*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12805 : /*33401*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12806 : /*33404*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12807 : /*33407*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12808 : /*33410*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12809 : /*33413*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12810 : /*33416*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12811 : /*33419*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12812 : /*33422*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12813 : /*33425*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_O_V4_V4), 0,
12814 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12815 : // Src: (intrinsic_wo_chain:v4f32 4837:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12816 : // Dst: (IMAGE_SAMPLE_B_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12817 : /*33443*/ /*Scope*/ 68, /*->33512*/
12818 : /*33444*/ OPC_CheckChild1Type, MVT::v8i32,
12819 : /*33446*/ OPC_RecordChild2, // #1 = $rsrc
12820 : /*33447*/ OPC_RecordChild3, // #2 = $sampler
12821 : /*33448*/ OPC_RecordChild4, // #3 = $dmask
12822 : /*33449*/ OPC_RecordChild5, // #4 = $unorm
12823 : /*33450*/ OPC_RecordChild6, // #5 = $r128
12824 : /*33451*/ OPC_RecordChild7, // #6 = $da
12825 : /*33452*/ OPC_MoveChild, 8,
12826 : /*33454*/ OPC_RecordNode, // #7 = $glc
12827 : /*33455*/ OPC_MoveParent,
12828 : /*33456*/ OPC_MoveChild, 9,
12829 : /*33458*/ OPC_RecordNode, // #8 = $slc
12830 : /*33459*/ OPC_MoveParent,
12831 : /*33460*/ OPC_MoveChild, 10,
12832 : /*33462*/ OPC_RecordNode, // #9 = $tfe
12833 : /*33463*/ OPC_MoveParent,
12834 : /*33464*/ OPC_MoveChild, 11,
12835 : /*33466*/ OPC_RecordNode, // #10 = $lwe
12836 : /*33467*/ OPC_MoveParent,
12837 : /*33468*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12838 : /*33470*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12839 : /*33473*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12840 : /*33476*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12841 : /*33479*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12842 : /*33482*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12843 : /*33485*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12844 : /*33488*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12845 : /*33491*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12846 : /*33494*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_O_V4_V8), 0,
12847 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12848 : // Src: (intrinsic_wo_chain:v4f32 4837:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12849 : // Dst: (IMAGE_SAMPLE_B_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12850 : /*33512*/ /*Scope*/ 68, /*->33581*/
12851 : /*33513*/ OPC_CheckChild1Type, MVT::v16i32,
12852 : /*33515*/ OPC_RecordChild2, // #1 = $rsrc
12853 : /*33516*/ OPC_RecordChild3, // #2 = $sampler
12854 : /*33517*/ OPC_RecordChild4, // #3 = $dmask
12855 : /*33518*/ OPC_RecordChild5, // #4 = $unorm
12856 : /*33519*/ OPC_RecordChild6, // #5 = $r128
12857 : /*33520*/ OPC_RecordChild7, // #6 = $da
12858 : /*33521*/ OPC_MoveChild, 8,
12859 : /*33523*/ OPC_RecordNode, // #7 = $glc
12860 : /*33524*/ OPC_MoveParent,
12861 : /*33525*/ OPC_MoveChild, 9,
12862 : /*33527*/ OPC_RecordNode, // #8 = $slc
12863 : /*33528*/ OPC_MoveParent,
12864 : /*33529*/ OPC_MoveChild, 10,
12865 : /*33531*/ OPC_RecordNode, // #9 = $tfe
12866 : /*33532*/ OPC_MoveParent,
12867 : /*33533*/ OPC_MoveChild, 11,
12868 : /*33535*/ OPC_RecordNode, // #10 = $lwe
12869 : /*33536*/ OPC_MoveParent,
12870 : /*33537*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12871 : /*33539*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12872 : /*33542*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12873 : /*33545*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12874 : /*33548*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12875 : /*33551*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12876 : /*33554*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12877 : /*33557*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12878 : /*33560*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12879 : /*33563*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_O_V4_V16), 0,
12880 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12881 : // Src: (intrinsic_wo_chain:v4f32 4837:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12882 : // Dst: (IMAGE_SAMPLE_B_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12883 : /*33581*/ 0, /*End of Scope*/
12884 : /*33582*/ /*Scope*/ 95|128,2/*351*/, /*->33935*/
12885 : /*33584*/ OPC_CheckChild0Integer, 100|128,37/*4836*/,
12886 : /*33587*/ OPC_RecordChild1, // #0 = $addr
12887 : /*33588*/ OPC_Scope, 68, /*->33658*/ // 5 children in Scope
12888 : /*33590*/ OPC_CheckChild1Type, MVT::i32,
12889 : /*33592*/ OPC_RecordChild2, // #1 = $rsrc
12890 : /*33593*/ OPC_RecordChild3, // #2 = $sampler
12891 : /*33594*/ OPC_RecordChild4, // #3 = $dmask
12892 : /*33595*/ OPC_RecordChild5, // #4 = $unorm
12893 : /*33596*/ OPC_RecordChild6, // #5 = $r128
12894 : /*33597*/ OPC_RecordChild7, // #6 = $da
12895 : /*33598*/ OPC_MoveChild, 8,
12896 : /*33600*/ OPC_RecordNode, // #7 = $glc
12897 : /*33601*/ OPC_MoveParent,
12898 : /*33602*/ OPC_MoveChild, 9,
12899 : /*33604*/ OPC_RecordNode, // #8 = $slc
12900 : /*33605*/ OPC_MoveParent,
12901 : /*33606*/ OPC_MoveChild, 10,
12902 : /*33608*/ OPC_RecordNode, // #9 = $tfe
12903 : /*33609*/ OPC_MoveParent,
12904 : /*33610*/ OPC_MoveChild, 11,
12905 : /*33612*/ OPC_RecordNode, // #10 = $lwe
12906 : /*33613*/ OPC_MoveParent,
12907 : /*33614*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12908 : /*33616*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12909 : /*33619*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12910 : /*33622*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12911 : /*33625*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12912 : /*33628*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12913 : /*33631*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12914 : /*33634*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12915 : /*33637*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12916 : /*33640*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V1), 0,
12917 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12918 : // Src: (intrinsic_wo_chain:v4f32 4836:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12919 : // Dst: (IMAGE_SAMPLE_B_CL_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12920 : /*33658*/ /*Scope*/ 68, /*->33727*/
12921 : /*33659*/ OPC_CheckChild1Type, MVT::v2i32,
12922 : /*33661*/ OPC_RecordChild2, // #1 = $rsrc
12923 : /*33662*/ OPC_RecordChild3, // #2 = $sampler
12924 : /*33663*/ OPC_RecordChild4, // #3 = $dmask
12925 : /*33664*/ OPC_RecordChild5, // #4 = $unorm
12926 : /*33665*/ OPC_RecordChild6, // #5 = $r128
12927 : /*33666*/ OPC_RecordChild7, // #6 = $da
12928 : /*33667*/ OPC_MoveChild, 8,
12929 : /*33669*/ OPC_RecordNode, // #7 = $glc
12930 : /*33670*/ OPC_MoveParent,
12931 : /*33671*/ OPC_MoveChild, 9,
12932 : /*33673*/ OPC_RecordNode, // #8 = $slc
12933 : /*33674*/ OPC_MoveParent,
12934 : /*33675*/ OPC_MoveChild, 10,
12935 : /*33677*/ OPC_RecordNode, // #9 = $tfe
12936 : /*33678*/ OPC_MoveParent,
12937 : /*33679*/ OPC_MoveChild, 11,
12938 : /*33681*/ OPC_RecordNode, // #10 = $lwe
12939 : /*33682*/ OPC_MoveParent,
12940 : /*33683*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12941 : /*33685*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12942 : /*33688*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12943 : /*33691*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12944 : /*33694*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12945 : /*33697*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12946 : /*33700*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12947 : /*33703*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12948 : /*33706*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12949 : /*33709*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V2), 0,
12950 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12951 : // Src: (intrinsic_wo_chain:v4f32 4836:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12952 : // Dst: (IMAGE_SAMPLE_B_CL_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12953 : /*33727*/ /*Scope*/ 68, /*->33796*/
12954 : /*33728*/ OPC_CheckChild1Type, MVT::v4i32,
12955 : /*33730*/ OPC_RecordChild2, // #1 = $rsrc
12956 : /*33731*/ OPC_RecordChild3, // #2 = $sampler
12957 : /*33732*/ OPC_RecordChild4, // #3 = $dmask
12958 : /*33733*/ OPC_RecordChild5, // #4 = $unorm
12959 : /*33734*/ OPC_RecordChild6, // #5 = $r128
12960 : /*33735*/ OPC_RecordChild7, // #6 = $da
12961 : /*33736*/ OPC_MoveChild, 8,
12962 : /*33738*/ OPC_RecordNode, // #7 = $glc
12963 : /*33739*/ OPC_MoveParent,
12964 : /*33740*/ OPC_MoveChild, 9,
12965 : /*33742*/ OPC_RecordNode, // #8 = $slc
12966 : /*33743*/ OPC_MoveParent,
12967 : /*33744*/ OPC_MoveChild, 10,
12968 : /*33746*/ OPC_RecordNode, // #9 = $tfe
12969 : /*33747*/ OPC_MoveParent,
12970 : /*33748*/ OPC_MoveChild, 11,
12971 : /*33750*/ OPC_RecordNode, // #10 = $lwe
12972 : /*33751*/ OPC_MoveParent,
12973 : /*33752*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
12974 : /*33754*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
12975 : /*33757*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
12976 : /*33760*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
12977 : /*33763*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
12978 : /*33766*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
12979 : /*33769*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
12980 : /*33772*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
12981 : /*33775*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
12982 : /*33778*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4), 0,
12983 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
12984 : // Src: (intrinsic_wo_chain:v4f32 4836:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
12985 : // Dst: (IMAGE_SAMPLE_B_CL_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
12986 : /*33796*/ /*Scope*/ 68, /*->33865*/
12987 : /*33797*/ OPC_CheckChild1Type, MVT::v8i32,
12988 : /*33799*/ OPC_RecordChild2, // #1 = $rsrc
12989 : /*33800*/ OPC_RecordChild3, // #2 = $sampler
12990 : /*33801*/ OPC_RecordChild4, // #3 = $dmask
12991 : /*33802*/ OPC_RecordChild5, // #4 = $unorm
12992 : /*33803*/ OPC_RecordChild6, // #5 = $r128
12993 : /*33804*/ OPC_RecordChild7, // #6 = $da
12994 : /*33805*/ OPC_MoveChild, 8,
12995 : /*33807*/ OPC_RecordNode, // #7 = $glc
12996 : /*33808*/ OPC_MoveParent,
12997 : /*33809*/ OPC_MoveChild, 9,
12998 : /*33811*/ OPC_RecordNode, // #8 = $slc
12999 : /*33812*/ OPC_MoveParent,
13000 : /*33813*/ OPC_MoveChild, 10,
13001 : /*33815*/ OPC_RecordNode, // #9 = $tfe
13002 : /*33816*/ OPC_MoveParent,
13003 : /*33817*/ OPC_MoveChild, 11,
13004 : /*33819*/ OPC_RecordNode, // #10 = $lwe
13005 : /*33820*/ OPC_MoveParent,
13006 : /*33821*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13007 : /*33823*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13008 : /*33826*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13009 : /*33829*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13010 : /*33832*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13011 : /*33835*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13012 : /*33838*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13013 : /*33841*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13014 : /*33844*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13015 : /*33847*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8), 0,
13016 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13017 : // Src: (intrinsic_wo_chain:v4f32 4836:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13018 : // Dst: (IMAGE_SAMPLE_B_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13019 : /*33865*/ /*Scope*/ 68, /*->33934*/
13020 : /*33866*/ OPC_CheckChild1Type, MVT::v16i32,
13021 : /*33868*/ OPC_RecordChild2, // #1 = $rsrc
13022 : /*33869*/ OPC_RecordChild3, // #2 = $sampler
13023 : /*33870*/ OPC_RecordChild4, // #3 = $dmask
13024 : /*33871*/ OPC_RecordChild5, // #4 = $unorm
13025 : /*33872*/ OPC_RecordChild6, // #5 = $r128
13026 : /*33873*/ OPC_RecordChild7, // #6 = $da
13027 : /*33874*/ OPC_MoveChild, 8,
13028 : /*33876*/ OPC_RecordNode, // #7 = $glc
13029 : /*33877*/ OPC_MoveParent,
13030 : /*33878*/ OPC_MoveChild, 9,
13031 : /*33880*/ OPC_RecordNode, // #8 = $slc
13032 : /*33881*/ OPC_MoveParent,
13033 : /*33882*/ OPC_MoveChild, 10,
13034 : /*33884*/ OPC_RecordNode, // #9 = $tfe
13035 : /*33885*/ OPC_MoveParent,
13036 : /*33886*/ OPC_MoveChild, 11,
13037 : /*33888*/ OPC_RecordNode, // #10 = $lwe
13038 : /*33889*/ OPC_MoveParent,
13039 : /*33890*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13040 : /*33892*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13041 : /*33895*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13042 : /*33898*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13043 : /*33901*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13044 : /*33904*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13045 : /*33907*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13046 : /*33910*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13047 : /*33913*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13048 : /*33916*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V16), 0,
13049 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13050 : // Src: (intrinsic_wo_chain:v4f32 4836:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13051 : // Dst: (IMAGE_SAMPLE_B_CL_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13052 : /*33934*/ 0, /*End of Scope*/
13053 : /*33935*/ /*Scope*/ 95|128,2/*351*/, /*->34288*/
13054 : /*33937*/ OPC_CheckChild0Integer, 7|128,38/*4871*/,
13055 : /*33940*/ OPC_RecordChild1, // #0 = $addr
13056 : /*33941*/ OPC_Scope, 68, /*->34011*/ // 5 children in Scope
13057 : /*33943*/ OPC_CheckChild1Type, MVT::i32,
13058 : /*33945*/ OPC_RecordChild2, // #1 = $rsrc
13059 : /*33946*/ OPC_RecordChild3, // #2 = $sampler
13060 : /*33947*/ OPC_RecordChild4, // #3 = $dmask
13061 : /*33948*/ OPC_RecordChild5, // #4 = $unorm
13062 : /*33949*/ OPC_RecordChild6, // #5 = $r128
13063 : /*33950*/ OPC_RecordChild7, // #6 = $da
13064 : /*33951*/ OPC_MoveChild, 8,
13065 : /*33953*/ OPC_RecordNode, // #7 = $glc
13066 : /*33954*/ OPC_MoveParent,
13067 : /*33955*/ OPC_MoveChild, 9,
13068 : /*33957*/ OPC_RecordNode, // #8 = $slc
13069 : /*33958*/ OPC_MoveParent,
13070 : /*33959*/ OPC_MoveChild, 10,
13071 : /*33961*/ OPC_RecordNode, // #9 = $tfe
13072 : /*33962*/ OPC_MoveParent,
13073 : /*33963*/ OPC_MoveChild, 11,
13074 : /*33965*/ OPC_RecordNode, // #10 = $lwe
13075 : /*33966*/ OPC_MoveParent,
13076 : /*33967*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13077 : /*33969*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13078 : /*33972*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13079 : /*33975*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13080 : /*33978*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13081 : /*33981*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13082 : /*33984*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13083 : /*33987*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13084 : /*33990*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13085 : /*33993*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V1), 0,
13086 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13087 : // Src: (intrinsic_wo_chain:v4f32 4871:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13088 : // Dst: (IMAGE_SAMPLE_LZ_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13089 : /*34011*/ /*Scope*/ 68, /*->34080*/
13090 : /*34012*/ OPC_CheckChild1Type, MVT::v2i32,
13091 : /*34014*/ OPC_RecordChild2, // #1 = $rsrc
13092 : /*34015*/ OPC_RecordChild3, // #2 = $sampler
13093 : /*34016*/ OPC_RecordChild4, // #3 = $dmask
13094 : /*34017*/ OPC_RecordChild5, // #4 = $unorm
13095 : /*34018*/ OPC_RecordChild6, // #5 = $r128
13096 : /*34019*/ OPC_RecordChild7, // #6 = $da
13097 : /*34020*/ OPC_MoveChild, 8,
13098 : /*34022*/ OPC_RecordNode, // #7 = $glc
13099 : /*34023*/ OPC_MoveParent,
13100 : /*34024*/ OPC_MoveChild, 9,
13101 : /*34026*/ OPC_RecordNode, // #8 = $slc
13102 : /*34027*/ OPC_MoveParent,
13103 : /*34028*/ OPC_MoveChild, 10,
13104 : /*34030*/ OPC_RecordNode, // #9 = $tfe
13105 : /*34031*/ OPC_MoveParent,
13106 : /*34032*/ OPC_MoveChild, 11,
13107 : /*34034*/ OPC_RecordNode, // #10 = $lwe
13108 : /*34035*/ OPC_MoveParent,
13109 : /*34036*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13110 : /*34038*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13111 : /*34041*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13112 : /*34044*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13113 : /*34047*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13114 : /*34050*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13115 : /*34053*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13116 : /*34056*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13117 : /*34059*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13118 : /*34062*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2), 0,
13119 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13120 : // Src: (intrinsic_wo_chain:v4f32 4871:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13121 : // Dst: (IMAGE_SAMPLE_LZ_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13122 : /*34080*/ /*Scope*/ 68, /*->34149*/
13123 : /*34081*/ OPC_CheckChild1Type, MVT::v4i32,
13124 : /*34083*/ OPC_RecordChild2, // #1 = $rsrc
13125 : /*34084*/ OPC_RecordChild3, // #2 = $sampler
13126 : /*34085*/ OPC_RecordChild4, // #3 = $dmask
13127 : /*34086*/ OPC_RecordChild5, // #4 = $unorm
13128 : /*34087*/ OPC_RecordChild6, // #5 = $r128
13129 : /*34088*/ OPC_RecordChild7, // #6 = $da
13130 : /*34089*/ OPC_MoveChild, 8,
13131 : /*34091*/ OPC_RecordNode, // #7 = $glc
13132 : /*34092*/ OPC_MoveParent,
13133 : /*34093*/ OPC_MoveChild, 9,
13134 : /*34095*/ OPC_RecordNode, // #8 = $slc
13135 : /*34096*/ OPC_MoveParent,
13136 : /*34097*/ OPC_MoveChild, 10,
13137 : /*34099*/ OPC_RecordNode, // #9 = $tfe
13138 : /*34100*/ OPC_MoveParent,
13139 : /*34101*/ OPC_MoveChild, 11,
13140 : /*34103*/ OPC_RecordNode, // #10 = $lwe
13141 : /*34104*/ OPC_MoveParent,
13142 : /*34105*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13143 : /*34107*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13144 : /*34110*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13145 : /*34113*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13146 : /*34116*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13147 : /*34119*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13148 : /*34122*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13149 : /*34125*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13150 : /*34128*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13151 : /*34131*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4), 0,
13152 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13153 : // Src: (intrinsic_wo_chain:v4f32 4871:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13154 : // Dst: (IMAGE_SAMPLE_LZ_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13155 : /*34149*/ /*Scope*/ 68, /*->34218*/
13156 : /*34150*/ OPC_CheckChild1Type, MVT::v8i32,
13157 : /*34152*/ OPC_RecordChild2, // #1 = $rsrc
13158 : /*34153*/ OPC_RecordChild3, // #2 = $sampler
13159 : /*34154*/ OPC_RecordChild4, // #3 = $dmask
13160 : /*34155*/ OPC_RecordChild5, // #4 = $unorm
13161 : /*34156*/ OPC_RecordChild6, // #5 = $r128
13162 : /*34157*/ OPC_RecordChild7, // #6 = $da
13163 : /*34158*/ OPC_MoveChild, 8,
13164 : /*34160*/ OPC_RecordNode, // #7 = $glc
13165 : /*34161*/ OPC_MoveParent,
13166 : /*34162*/ OPC_MoveChild, 9,
13167 : /*34164*/ OPC_RecordNode, // #8 = $slc
13168 : /*34165*/ OPC_MoveParent,
13169 : /*34166*/ OPC_MoveChild, 10,
13170 : /*34168*/ OPC_RecordNode, // #9 = $tfe
13171 : /*34169*/ OPC_MoveParent,
13172 : /*34170*/ OPC_MoveChild, 11,
13173 : /*34172*/ OPC_RecordNode, // #10 = $lwe
13174 : /*34173*/ OPC_MoveParent,
13175 : /*34174*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13176 : /*34176*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13177 : /*34179*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13178 : /*34182*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13179 : /*34185*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13180 : /*34188*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13181 : /*34191*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13182 : /*34194*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13183 : /*34197*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13184 : /*34200*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V8), 0,
13185 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13186 : // Src: (intrinsic_wo_chain:v4f32 4871:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13187 : // Dst: (IMAGE_SAMPLE_LZ_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13188 : /*34218*/ /*Scope*/ 68, /*->34287*/
13189 : /*34219*/ OPC_CheckChild1Type, MVT::v16i32,
13190 : /*34221*/ OPC_RecordChild2, // #1 = $rsrc
13191 : /*34222*/ OPC_RecordChild3, // #2 = $sampler
13192 : /*34223*/ OPC_RecordChild4, // #3 = $dmask
13193 : /*34224*/ OPC_RecordChild5, // #4 = $unorm
13194 : /*34225*/ OPC_RecordChild6, // #5 = $r128
13195 : /*34226*/ OPC_RecordChild7, // #6 = $da
13196 : /*34227*/ OPC_MoveChild, 8,
13197 : /*34229*/ OPC_RecordNode, // #7 = $glc
13198 : /*34230*/ OPC_MoveParent,
13199 : /*34231*/ OPC_MoveChild, 9,
13200 : /*34233*/ OPC_RecordNode, // #8 = $slc
13201 : /*34234*/ OPC_MoveParent,
13202 : /*34235*/ OPC_MoveChild, 10,
13203 : /*34237*/ OPC_RecordNode, // #9 = $tfe
13204 : /*34238*/ OPC_MoveParent,
13205 : /*34239*/ OPC_MoveChild, 11,
13206 : /*34241*/ OPC_RecordNode, // #10 = $lwe
13207 : /*34242*/ OPC_MoveParent,
13208 : /*34243*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13209 : /*34245*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13210 : /*34248*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13211 : /*34251*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13212 : /*34254*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13213 : /*34257*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13214 : /*34260*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13215 : /*34263*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13216 : /*34266*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13217 : /*34269*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V16), 0,
13218 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13219 : // Src: (intrinsic_wo_chain:v4f32 4871:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13220 : // Dst: (IMAGE_SAMPLE_LZ_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13221 : /*34287*/ 0, /*End of Scope*/
13222 : /*34288*/ /*Scope*/ 95|128,2/*351*/, /*->34641*/
13223 : /*34290*/ OPC_CheckChild0Integer, 125|128,37/*4861*/,
13224 : /*34293*/ OPC_RecordChild1, // #0 = $addr
13225 : /*34294*/ OPC_Scope, 68, /*->34364*/ // 5 children in Scope
13226 : /*34296*/ OPC_CheckChild1Type, MVT::i32,
13227 : /*34298*/ OPC_RecordChild2, // #1 = $rsrc
13228 : /*34299*/ OPC_RecordChild3, // #2 = $sampler
13229 : /*34300*/ OPC_RecordChild4, // #3 = $dmask
13230 : /*34301*/ OPC_RecordChild5, // #4 = $unorm
13231 : /*34302*/ OPC_RecordChild6, // #5 = $r128
13232 : /*34303*/ OPC_RecordChild7, // #6 = $da
13233 : /*34304*/ OPC_MoveChild, 8,
13234 : /*34306*/ OPC_RecordNode, // #7 = $glc
13235 : /*34307*/ OPC_MoveParent,
13236 : /*34308*/ OPC_MoveChild, 9,
13237 : /*34310*/ OPC_RecordNode, // #8 = $slc
13238 : /*34311*/ OPC_MoveParent,
13239 : /*34312*/ OPC_MoveChild, 10,
13240 : /*34314*/ OPC_RecordNode, // #9 = $tfe
13241 : /*34315*/ OPC_MoveParent,
13242 : /*34316*/ OPC_MoveChild, 11,
13243 : /*34318*/ OPC_RecordNode, // #10 = $lwe
13244 : /*34319*/ OPC_MoveParent,
13245 : /*34320*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13246 : /*34322*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13247 : /*34325*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13248 : /*34328*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13249 : /*34331*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13250 : /*34334*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13251 : /*34337*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13252 : /*34340*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13253 : /*34343*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13254 : /*34346*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_O_V4_V1), 0,
13255 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13256 : // Src: (intrinsic_wo_chain:v4f32 4861:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13257 : // Dst: (IMAGE_SAMPLE_CD_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13258 : /*34364*/ /*Scope*/ 68, /*->34433*/
13259 : /*34365*/ OPC_CheckChild1Type, MVT::v2i32,
13260 : /*34367*/ OPC_RecordChild2, // #1 = $rsrc
13261 : /*34368*/ OPC_RecordChild3, // #2 = $sampler
13262 : /*34369*/ OPC_RecordChild4, // #3 = $dmask
13263 : /*34370*/ OPC_RecordChild5, // #4 = $unorm
13264 : /*34371*/ OPC_RecordChild6, // #5 = $r128
13265 : /*34372*/ OPC_RecordChild7, // #6 = $da
13266 : /*34373*/ OPC_MoveChild, 8,
13267 : /*34375*/ OPC_RecordNode, // #7 = $glc
13268 : /*34376*/ OPC_MoveParent,
13269 : /*34377*/ OPC_MoveChild, 9,
13270 : /*34379*/ OPC_RecordNode, // #8 = $slc
13271 : /*34380*/ OPC_MoveParent,
13272 : /*34381*/ OPC_MoveChild, 10,
13273 : /*34383*/ OPC_RecordNode, // #9 = $tfe
13274 : /*34384*/ OPC_MoveParent,
13275 : /*34385*/ OPC_MoveChild, 11,
13276 : /*34387*/ OPC_RecordNode, // #10 = $lwe
13277 : /*34388*/ OPC_MoveParent,
13278 : /*34389*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13279 : /*34391*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13280 : /*34394*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13281 : /*34397*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13282 : /*34400*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13283 : /*34403*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13284 : /*34406*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13285 : /*34409*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13286 : /*34412*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13287 : /*34415*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_O_V4_V2), 0,
13288 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13289 : // Src: (intrinsic_wo_chain:v4f32 4861:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13290 : // Dst: (IMAGE_SAMPLE_CD_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13291 : /*34433*/ /*Scope*/ 68, /*->34502*/
13292 : /*34434*/ OPC_CheckChild1Type, MVT::v4i32,
13293 : /*34436*/ OPC_RecordChild2, // #1 = $rsrc
13294 : /*34437*/ OPC_RecordChild3, // #2 = $sampler
13295 : /*34438*/ OPC_RecordChild4, // #3 = $dmask
13296 : /*34439*/ OPC_RecordChild5, // #4 = $unorm
13297 : /*34440*/ OPC_RecordChild6, // #5 = $r128
13298 : /*34441*/ OPC_RecordChild7, // #6 = $da
13299 : /*34442*/ OPC_MoveChild, 8,
13300 : /*34444*/ OPC_RecordNode, // #7 = $glc
13301 : /*34445*/ OPC_MoveParent,
13302 : /*34446*/ OPC_MoveChild, 9,
13303 : /*34448*/ OPC_RecordNode, // #8 = $slc
13304 : /*34449*/ OPC_MoveParent,
13305 : /*34450*/ OPC_MoveChild, 10,
13306 : /*34452*/ OPC_RecordNode, // #9 = $tfe
13307 : /*34453*/ OPC_MoveParent,
13308 : /*34454*/ OPC_MoveChild, 11,
13309 : /*34456*/ OPC_RecordNode, // #10 = $lwe
13310 : /*34457*/ OPC_MoveParent,
13311 : /*34458*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13312 : /*34460*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13313 : /*34463*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13314 : /*34466*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13315 : /*34469*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13316 : /*34472*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13317 : /*34475*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13318 : /*34478*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13319 : /*34481*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13320 : /*34484*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4), 0,
13321 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13322 : // Src: (intrinsic_wo_chain:v4f32 4861:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13323 : // Dst: (IMAGE_SAMPLE_CD_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13324 : /*34502*/ /*Scope*/ 68, /*->34571*/
13325 : /*34503*/ OPC_CheckChild1Type, MVT::v8i32,
13326 : /*34505*/ OPC_RecordChild2, // #1 = $rsrc
13327 : /*34506*/ OPC_RecordChild3, // #2 = $sampler
13328 : /*34507*/ OPC_RecordChild4, // #3 = $dmask
13329 : /*34508*/ OPC_RecordChild5, // #4 = $unorm
13330 : /*34509*/ OPC_RecordChild6, // #5 = $r128
13331 : /*34510*/ OPC_RecordChild7, // #6 = $da
13332 : /*34511*/ OPC_MoveChild, 8,
13333 : /*34513*/ OPC_RecordNode, // #7 = $glc
13334 : /*34514*/ OPC_MoveParent,
13335 : /*34515*/ OPC_MoveChild, 9,
13336 : /*34517*/ OPC_RecordNode, // #8 = $slc
13337 : /*34518*/ OPC_MoveParent,
13338 : /*34519*/ OPC_MoveChild, 10,
13339 : /*34521*/ OPC_RecordNode, // #9 = $tfe
13340 : /*34522*/ OPC_MoveParent,
13341 : /*34523*/ OPC_MoveChild, 11,
13342 : /*34525*/ OPC_RecordNode, // #10 = $lwe
13343 : /*34526*/ OPC_MoveParent,
13344 : /*34527*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13345 : /*34529*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13346 : /*34532*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13347 : /*34535*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13348 : /*34538*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13349 : /*34541*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13350 : /*34544*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13351 : /*34547*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13352 : /*34550*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13353 : /*34553*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8), 0,
13354 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13355 : // Src: (intrinsic_wo_chain:v4f32 4861:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13356 : // Dst: (IMAGE_SAMPLE_CD_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13357 : /*34571*/ /*Scope*/ 68, /*->34640*/
13358 : /*34572*/ OPC_CheckChild1Type, MVT::v16i32,
13359 : /*34574*/ OPC_RecordChild2, // #1 = $rsrc
13360 : /*34575*/ OPC_RecordChild3, // #2 = $sampler
13361 : /*34576*/ OPC_RecordChild4, // #3 = $dmask
13362 : /*34577*/ OPC_RecordChild5, // #4 = $unorm
13363 : /*34578*/ OPC_RecordChild6, // #5 = $r128
13364 : /*34579*/ OPC_RecordChild7, // #6 = $da
13365 : /*34580*/ OPC_MoveChild, 8,
13366 : /*34582*/ OPC_RecordNode, // #7 = $glc
13367 : /*34583*/ OPC_MoveParent,
13368 : /*34584*/ OPC_MoveChild, 9,
13369 : /*34586*/ OPC_RecordNode, // #8 = $slc
13370 : /*34587*/ OPC_MoveParent,
13371 : /*34588*/ OPC_MoveChild, 10,
13372 : /*34590*/ OPC_RecordNode, // #9 = $tfe
13373 : /*34591*/ OPC_MoveParent,
13374 : /*34592*/ OPC_MoveChild, 11,
13375 : /*34594*/ OPC_RecordNode, // #10 = $lwe
13376 : /*34595*/ OPC_MoveParent,
13377 : /*34596*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13378 : /*34598*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13379 : /*34601*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13380 : /*34604*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13381 : /*34607*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13382 : /*34610*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13383 : /*34613*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13384 : /*34616*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13385 : /*34619*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13386 : /*34622*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_O_V4_V16), 0,
13387 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13388 : // Src: (intrinsic_wo_chain:v4f32 4861:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13389 : // Dst: (IMAGE_SAMPLE_CD_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13390 : /*34640*/ 0, /*End of Scope*/
13391 : /*34641*/ /*Scope*/ 95|128,2/*351*/, /*->34994*/
13392 : /*34643*/ OPC_CheckChild0Integer, 124|128,37/*4860*/,
13393 : /*34646*/ OPC_RecordChild1, // #0 = $addr
13394 : /*34647*/ OPC_Scope, 68, /*->34717*/ // 5 children in Scope
13395 : /*34649*/ OPC_CheckChild1Type, MVT::i32,
13396 : /*34651*/ OPC_RecordChild2, // #1 = $rsrc
13397 : /*34652*/ OPC_RecordChild3, // #2 = $sampler
13398 : /*34653*/ OPC_RecordChild4, // #3 = $dmask
13399 : /*34654*/ OPC_RecordChild5, // #4 = $unorm
13400 : /*34655*/ OPC_RecordChild6, // #5 = $r128
13401 : /*34656*/ OPC_RecordChild7, // #6 = $da
13402 : /*34657*/ OPC_MoveChild, 8,
13403 : /*34659*/ OPC_RecordNode, // #7 = $glc
13404 : /*34660*/ OPC_MoveParent,
13405 : /*34661*/ OPC_MoveChild, 9,
13406 : /*34663*/ OPC_RecordNode, // #8 = $slc
13407 : /*34664*/ OPC_MoveParent,
13408 : /*34665*/ OPC_MoveChild, 10,
13409 : /*34667*/ OPC_RecordNode, // #9 = $tfe
13410 : /*34668*/ OPC_MoveParent,
13411 : /*34669*/ OPC_MoveChild, 11,
13412 : /*34671*/ OPC_RecordNode, // #10 = $lwe
13413 : /*34672*/ OPC_MoveParent,
13414 : /*34673*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13415 : /*34675*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13416 : /*34678*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13417 : /*34681*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13418 : /*34684*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13419 : /*34687*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13420 : /*34690*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13421 : /*34693*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13422 : /*34696*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13423 : /*34699*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V1), 0,
13424 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13425 : // Src: (intrinsic_wo_chain:v4f32 4860:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13426 : // Dst: (IMAGE_SAMPLE_CD_CL_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13427 : /*34717*/ /*Scope*/ 68, /*->34786*/
13428 : /*34718*/ OPC_CheckChild1Type, MVT::v2i32,
13429 : /*34720*/ OPC_RecordChild2, // #1 = $rsrc
13430 : /*34721*/ OPC_RecordChild3, // #2 = $sampler
13431 : /*34722*/ OPC_RecordChild4, // #3 = $dmask
13432 : /*34723*/ OPC_RecordChild5, // #4 = $unorm
13433 : /*34724*/ OPC_RecordChild6, // #5 = $r128
13434 : /*34725*/ OPC_RecordChild7, // #6 = $da
13435 : /*34726*/ OPC_MoveChild, 8,
13436 : /*34728*/ OPC_RecordNode, // #7 = $glc
13437 : /*34729*/ OPC_MoveParent,
13438 : /*34730*/ OPC_MoveChild, 9,
13439 : /*34732*/ OPC_RecordNode, // #8 = $slc
13440 : /*34733*/ OPC_MoveParent,
13441 : /*34734*/ OPC_MoveChild, 10,
13442 : /*34736*/ OPC_RecordNode, // #9 = $tfe
13443 : /*34737*/ OPC_MoveParent,
13444 : /*34738*/ OPC_MoveChild, 11,
13445 : /*34740*/ OPC_RecordNode, // #10 = $lwe
13446 : /*34741*/ OPC_MoveParent,
13447 : /*34742*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13448 : /*34744*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13449 : /*34747*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13450 : /*34750*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13451 : /*34753*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13452 : /*34756*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13453 : /*34759*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13454 : /*34762*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13455 : /*34765*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13456 : /*34768*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V2), 0,
13457 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13458 : // Src: (intrinsic_wo_chain:v4f32 4860:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13459 : // Dst: (IMAGE_SAMPLE_CD_CL_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13460 : /*34786*/ /*Scope*/ 68, /*->34855*/
13461 : /*34787*/ OPC_CheckChild1Type, MVT::v4i32,
13462 : /*34789*/ OPC_RecordChild2, // #1 = $rsrc
13463 : /*34790*/ OPC_RecordChild3, // #2 = $sampler
13464 : /*34791*/ OPC_RecordChild4, // #3 = $dmask
13465 : /*34792*/ OPC_RecordChild5, // #4 = $unorm
13466 : /*34793*/ OPC_RecordChild6, // #5 = $r128
13467 : /*34794*/ OPC_RecordChild7, // #6 = $da
13468 : /*34795*/ OPC_MoveChild, 8,
13469 : /*34797*/ OPC_RecordNode, // #7 = $glc
13470 : /*34798*/ OPC_MoveParent,
13471 : /*34799*/ OPC_MoveChild, 9,
13472 : /*34801*/ OPC_RecordNode, // #8 = $slc
13473 : /*34802*/ OPC_MoveParent,
13474 : /*34803*/ OPC_MoveChild, 10,
13475 : /*34805*/ OPC_RecordNode, // #9 = $tfe
13476 : /*34806*/ OPC_MoveParent,
13477 : /*34807*/ OPC_MoveChild, 11,
13478 : /*34809*/ OPC_RecordNode, // #10 = $lwe
13479 : /*34810*/ OPC_MoveParent,
13480 : /*34811*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13481 : /*34813*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13482 : /*34816*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13483 : /*34819*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13484 : /*34822*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13485 : /*34825*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13486 : /*34828*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13487 : /*34831*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13488 : /*34834*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13489 : /*34837*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4), 0,
13490 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13491 : // Src: (intrinsic_wo_chain:v4f32 4860:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13492 : // Dst: (IMAGE_SAMPLE_CD_CL_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13493 : /*34855*/ /*Scope*/ 68, /*->34924*/
13494 : /*34856*/ OPC_CheckChild1Type, MVT::v8i32,
13495 : /*34858*/ OPC_RecordChild2, // #1 = $rsrc
13496 : /*34859*/ OPC_RecordChild3, // #2 = $sampler
13497 : /*34860*/ OPC_RecordChild4, // #3 = $dmask
13498 : /*34861*/ OPC_RecordChild5, // #4 = $unorm
13499 : /*34862*/ OPC_RecordChild6, // #5 = $r128
13500 : /*34863*/ OPC_RecordChild7, // #6 = $da
13501 : /*34864*/ OPC_MoveChild, 8,
13502 : /*34866*/ OPC_RecordNode, // #7 = $glc
13503 : /*34867*/ OPC_MoveParent,
13504 : /*34868*/ OPC_MoveChild, 9,
13505 : /*34870*/ OPC_RecordNode, // #8 = $slc
13506 : /*34871*/ OPC_MoveParent,
13507 : /*34872*/ OPC_MoveChild, 10,
13508 : /*34874*/ OPC_RecordNode, // #9 = $tfe
13509 : /*34875*/ OPC_MoveParent,
13510 : /*34876*/ OPC_MoveChild, 11,
13511 : /*34878*/ OPC_RecordNode, // #10 = $lwe
13512 : /*34879*/ OPC_MoveParent,
13513 : /*34880*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13514 : /*34882*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13515 : /*34885*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13516 : /*34888*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13517 : /*34891*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13518 : /*34894*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13519 : /*34897*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13520 : /*34900*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13521 : /*34903*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13522 : /*34906*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8), 0,
13523 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13524 : // Src: (intrinsic_wo_chain:v4f32 4860:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13525 : // Dst: (IMAGE_SAMPLE_CD_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13526 : /*34924*/ /*Scope*/ 68, /*->34993*/
13527 : /*34925*/ OPC_CheckChild1Type, MVT::v16i32,
13528 : /*34927*/ OPC_RecordChild2, // #1 = $rsrc
13529 : /*34928*/ OPC_RecordChild3, // #2 = $sampler
13530 : /*34929*/ OPC_RecordChild4, // #3 = $dmask
13531 : /*34930*/ OPC_RecordChild5, // #4 = $unorm
13532 : /*34931*/ OPC_RecordChild6, // #5 = $r128
13533 : /*34932*/ OPC_RecordChild7, // #6 = $da
13534 : /*34933*/ OPC_MoveChild, 8,
13535 : /*34935*/ OPC_RecordNode, // #7 = $glc
13536 : /*34936*/ OPC_MoveParent,
13537 : /*34937*/ OPC_MoveChild, 9,
13538 : /*34939*/ OPC_RecordNode, // #8 = $slc
13539 : /*34940*/ OPC_MoveParent,
13540 : /*34941*/ OPC_MoveChild, 10,
13541 : /*34943*/ OPC_RecordNode, // #9 = $tfe
13542 : /*34944*/ OPC_MoveParent,
13543 : /*34945*/ OPC_MoveChild, 11,
13544 : /*34947*/ OPC_RecordNode, // #10 = $lwe
13545 : /*34948*/ OPC_MoveParent,
13546 : /*34949*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13547 : /*34951*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13548 : /*34954*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13549 : /*34957*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13550 : /*34960*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13551 : /*34963*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13552 : /*34966*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13553 : /*34969*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13554 : /*34972*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13555 : /*34975*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V16), 0,
13556 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13557 : // Src: (intrinsic_wo_chain:v4f32 4860:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13558 : // Dst: (IMAGE_SAMPLE_CD_CL_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13559 : /*34993*/ 0, /*End of Scope*/
13560 : /*34994*/ /*Scope*/ 95|128,2/*351*/, /*->35347*/
13561 : /*34996*/ OPC_CheckChild0Integer, 121|128,37/*4857*/,
13562 : /*34999*/ OPC_RecordChild1, // #0 = $addr
13563 : /*35000*/ OPC_Scope, 68, /*->35070*/ // 5 children in Scope
13564 : /*35002*/ OPC_CheckChild1Type, MVT::i32,
13565 : /*35004*/ OPC_RecordChild2, // #1 = $rsrc
13566 : /*35005*/ OPC_RecordChild3, // #2 = $sampler
13567 : /*35006*/ OPC_RecordChild4, // #3 = $dmask
13568 : /*35007*/ OPC_RecordChild5, // #4 = $unorm
13569 : /*35008*/ OPC_RecordChild6, // #5 = $r128
13570 : /*35009*/ OPC_RecordChild7, // #6 = $da
13571 : /*35010*/ OPC_MoveChild, 8,
13572 : /*35012*/ OPC_RecordNode, // #7 = $glc
13573 : /*35013*/ OPC_MoveParent,
13574 : /*35014*/ OPC_MoveChild, 9,
13575 : /*35016*/ OPC_RecordNode, // #8 = $slc
13576 : /*35017*/ OPC_MoveParent,
13577 : /*35018*/ OPC_MoveChild, 10,
13578 : /*35020*/ OPC_RecordNode, // #9 = $tfe
13579 : /*35021*/ OPC_MoveParent,
13580 : /*35022*/ OPC_MoveChild, 11,
13581 : /*35024*/ OPC_RecordNode, // #10 = $lwe
13582 : /*35025*/ OPC_MoveParent,
13583 : /*35026*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13584 : /*35028*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13585 : /*35031*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13586 : /*35034*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13587 : /*35037*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13588 : /*35040*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13589 : /*35043*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13590 : /*35046*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13591 : /*35049*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13592 : /*35052*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_O_V4_V1), 0,
13593 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13594 : // Src: (intrinsic_wo_chain:v4f32 4857:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13595 : // Dst: (IMAGE_SAMPLE_C_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13596 : /*35070*/ /*Scope*/ 68, /*->35139*/
13597 : /*35071*/ OPC_CheckChild1Type, MVT::v2i32,
13598 : /*35073*/ OPC_RecordChild2, // #1 = $rsrc
13599 : /*35074*/ OPC_RecordChild3, // #2 = $sampler
13600 : /*35075*/ OPC_RecordChild4, // #3 = $dmask
13601 : /*35076*/ OPC_RecordChild5, // #4 = $unorm
13602 : /*35077*/ OPC_RecordChild6, // #5 = $r128
13603 : /*35078*/ OPC_RecordChild7, // #6 = $da
13604 : /*35079*/ OPC_MoveChild, 8,
13605 : /*35081*/ OPC_RecordNode, // #7 = $glc
13606 : /*35082*/ OPC_MoveParent,
13607 : /*35083*/ OPC_MoveChild, 9,
13608 : /*35085*/ OPC_RecordNode, // #8 = $slc
13609 : /*35086*/ OPC_MoveParent,
13610 : /*35087*/ OPC_MoveChild, 10,
13611 : /*35089*/ OPC_RecordNode, // #9 = $tfe
13612 : /*35090*/ OPC_MoveParent,
13613 : /*35091*/ OPC_MoveChild, 11,
13614 : /*35093*/ OPC_RecordNode, // #10 = $lwe
13615 : /*35094*/ OPC_MoveParent,
13616 : /*35095*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13617 : /*35097*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13618 : /*35100*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13619 : /*35103*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13620 : /*35106*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13621 : /*35109*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13622 : /*35112*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13623 : /*35115*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13624 : /*35118*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13625 : /*35121*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_O_V4_V2), 0,
13626 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13627 : // Src: (intrinsic_wo_chain:v4f32 4857:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13628 : // Dst: (IMAGE_SAMPLE_C_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13629 : /*35139*/ /*Scope*/ 68, /*->35208*/
13630 : /*35140*/ OPC_CheckChild1Type, MVT::v4i32,
13631 : /*35142*/ OPC_RecordChild2, // #1 = $rsrc
13632 : /*35143*/ OPC_RecordChild3, // #2 = $sampler
13633 : /*35144*/ OPC_RecordChild4, // #3 = $dmask
13634 : /*35145*/ OPC_RecordChild5, // #4 = $unorm
13635 : /*35146*/ OPC_RecordChild6, // #5 = $r128
13636 : /*35147*/ OPC_RecordChild7, // #6 = $da
13637 : /*35148*/ OPC_MoveChild, 8,
13638 : /*35150*/ OPC_RecordNode, // #7 = $glc
13639 : /*35151*/ OPC_MoveParent,
13640 : /*35152*/ OPC_MoveChild, 9,
13641 : /*35154*/ OPC_RecordNode, // #8 = $slc
13642 : /*35155*/ OPC_MoveParent,
13643 : /*35156*/ OPC_MoveChild, 10,
13644 : /*35158*/ OPC_RecordNode, // #9 = $tfe
13645 : /*35159*/ OPC_MoveParent,
13646 : /*35160*/ OPC_MoveChild, 11,
13647 : /*35162*/ OPC_RecordNode, // #10 = $lwe
13648 : /*35163*/ OPC_MoveParent,
13649 : /*35164*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13650 : /*35166*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13651 : /*35169*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13652 : /*35172*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13653 : /*35175*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13654 : /*35178*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13655 : /*35181*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13656 : /*35184*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13657 : /*35187*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13658 : /*35190*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_O_V4_V4), 0,
13659 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13660 : // Src: (intrinsic_wo_chain:v4f32 4857:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13661 : // Dst: (IMAGE_SAMPLE_C_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13662 : /*35208*/ /*Scope*/ 68, /*->35277*/
13663 : /*35209*/ OPC_CheckChild1Type, MVT::v8i32,
13664 : /*35211*/ OPC_RecordChild2, // #1 = $rsrc
13665 : /*35212*/ OPC_RecordChild3, // #2 = $sampler
13666 : /*35213*/ OPC_RecordChild4, // #3 = $dmask
13667 : /*35214*/ OPC_RecordChild5, // #4 = $unorm
13668 : /*35215*/ OPC_RecordChild6, // #5 = $r128
13669 : /*35216*/ OPC_RecordChild7, // #6 = $da
13670 : /*35217*/ OPC_MoveChild, 8,
13671 : /*35219*/ OPC_RecordNode, // #7 = $glc
13672 : /*35220*/ OPC_MoveParent,
13673 : /*35221*/ OPC_MoveChild, 9,
13674 : /*35223*/ OPC_RecordNode, // #8 = $slc
13675 : /*35224*/ OPC_MoveParent,
13676 : /*35225*/ OPC_MoveChild, 10,
13677 : /*35227*/ OPC_RecordNode, // #9 = $tfe
13678 : /*35228*/ OPC_MoveParent,
13679 : /*35229*/ OPC_MoveChild, 11,
13680 : /*35231*/ OPC_RecordNode, // #10 = $lwe
13681 : /*35232*/ OPC_MoveParent,
13682 : /*35233*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13683 : /*35235*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13684 : /*35238*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13685 : /*35241*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13686 : /*35244*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13687 : /*35247*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13688 : /*35250*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13689 : /*35253*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13690 : /*35256*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13691 : /*35259*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_O_V4_V8), 0,
13692 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13693 : // Src: (intrinsic_wo_chain:v4f32 4857:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13694 : // Dst: (IMAGE_SAMPLE_C_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13695 : /*35277*/ /*Scope*/ 68, /*->35346*/
13696 : /*35278*/ OPC_CheckChild1Type, MVT::v16i32,
13697 : /*35280*/ OPC_RecordChild2, // #1 = $rsrc
13698 : /*35281*/ OPC_RecordChild3, // #2 = $sampler
13699 : /*35282*/ OPC_RecordChild4, // #3 = $dmask
13700 : /*35283*/ OPC_RecordChild5, // #4 = $unorm
13701 : /*35284*/ OPC_RecordChild6, // #5 = $r128
13702 : /*35285*/ OPC_RecordChild7, // #6 = $da
13703 : /*35286*/ OPC_MoveChild, 8,
13704 : /*35288*/ OPC_RecordNode, // #7 = $glc
13705 : /*35289*/ OPC_MoveParent,
13706 : /*35290*/ OPC_MoveChild, 9,
13707 : /*35292*/ OPC_RecordNode, // #8 = $slc
13708 : /*35293*/ OPC_MoveParent,
13709 : /*35294*/ OPC_MoveChild, 10,
13710 : /*35296*/ OPC_RecordNode, // #9 = $tfe
13711 : /*35297*/ OPC_MoveParent,
13712 : /*35298*/ OPC_MoveChild, 11,
13713 : /*35300*/ OPC_RecordNode, // #10 = $lwe
13714 : /*35301*/ OPC_MoveParent,
13715 : /*35302*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13716 : /*35304*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13717 : /*35307*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13718 : /*35310*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13719 : /*35313*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13720 : /*35316*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13721 : /*35319*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13722 : /*35322*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13723 : /*35325*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13724 : /*35328*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_O_V4_V16), 0,
13725 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13726 : // Src: (intrinsic_wo_chain:v4f32 4857:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13727 : // Dst: (IMAGE_SAMPLE_C_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13728 : /*35346*/ 0, /*End of Scope*/
13729 : /*35347*/ /*Scope*/ 95|128,2/*351*/, /*->35700*/
13730 : /*35349*/ OPC_CheckChild0Integer, 112|128,37/*4848*/,
13731 : /*35352*/ OPC_RecordChild1, // #0 = $addr
13732 : /*35353*/ OPC_Scope, 68, /*->35423*/ // 5 children in Scope
13733 : /*35355*/ OPC_CheckChild1Type, MVT::i32,
13734 : /*35357*/ OPC_RecordChild2, // #1 = $rsrc
13735 : /*35358*/ OPC_RecordChild3, // #2 = $sampler
13736 : /*35359*/ OPC_RecordChild4, // #3 = $dmask
13737 : /*35360*/ OPC_RecordChild5, // #4 = $unorm
13738 : /*35361*/ OPC_RecordChild6, // #5 = $r128
13739 : /*35362*/ OPC_RecordChild7, // #6 = $da
13740 : /*35363*/ OPC_MoveChild, 8,
13741 : /*35365*/ OPC_RecordNode, // #7 = $glc
13742 : /*35366*/ OPC_MoveParent,
13743 : /*35367*/ OPC_MoveChild, 9,
13744 : /*35369*/ OPC_RecordNode, // #8 = $slc
13745 : /*35370*/ OPC_MoveParent,
13746 : /*35371*/ OPC_MoveChild, 10,
13747 : /*35373*/ OPC_RecordNode, // #9 = $tfe
13748 : /*35374*/ OPC_MoveParent,
13749 : /*35375*/ OPC_MoveChild, 11,
13750 : /*35377*/ OPC_RecordNode, // #10 = $lwe
13751 : /*35378*/ OPC_MoveParent,
13752 : /*35379*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13753 : /*35381*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13754 : /*35384*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13755 : /*35387*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13756 : /*35390*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13757 : /*35393*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13758 : /*35396*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13759 : /*35399*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13760 : /*35402*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13761 : /*35405*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V1), 0,
13762 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13763 : // Src: (intrinsic_wo_chain:v4f32 4848:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13764 : // Dst: (IMAGE_SAMPLE_C_CL_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13765 : /*35423*/ /*Scope*/ 68, /*->35492*/
13766 : /*35424*/ OPC_CheckChild1Type, MVT::v2i32,
13767 : /*35426*/ OPC_RecordChild2, // #1 = $rsrc
13768 : /*35427*/ OPC_RecordChild3, // #2 = $sampler
13769 : /*35428*/ OPC_RecordChild4, // #3 = $dmask
13770 : /*35429*/ OPC_RecordChild5, // #4 = $unorm
13771 : /*35430*/ OPC_RecordChild6, // #5 = $r128
13772 : /*35431*/ OPC_RecordChild7, // #6 = $da
13773 : /*35432*/ OPC_MoveChild, 8,
13774 : /*35434*/ OPC_RecordNode, // #7 = $glc
13775 : /*35435*/ OPC_MoveParent,
13776 : /*35436*/ OPC_MoveChild, 9,
13777 : /*35438*/ OPC_RecordNode, // #8 = $slc
13778 : /*35439*/ OPC_MoveParent,
13779 : /*35440*/ OPC_MoveChild, 10,
13780 : /*35442*/ OPC_RecordNode, // #9 = $tfe
13781 : /*35443*/ OPC_MoveParent,
13782 : /*35444*/ OPC_MoveChild, 11,
13783 : /*35446*/ OPC_RecordNode, // #10 = $lwe
13784 : /*35447*/ OPC_MoveParent,
13785 : /*35448*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13786 : /*35450*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13787 : /*35453*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13788 : /*35456*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13789 : /*35459*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13790 : /*35462*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13791 : /*35465*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13792 : /*35468*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13793 : /*35471*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13794 : /*35474*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V2), 0,
13795 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13796 : // Src: (intrinsic_wo_chain:v4f32 4848:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13797 : // Dst: (IMAGE_SAMPLE_C_CL_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13798 : /*35492*/ /*Scope*/ 68, /*->35561*/
13799 : /*35493*/ OPC_CheckChild1Type, MVT::v4i32,
13800 : /*35495*/ OPC_RecordChild2, // #1 = $rsrc
13801 : /*35496*/ OPC_RecordChild3, // #2 = $sampler
13802 : /*35497*/ OPC_RecordChild4, // #3 = $dmask
13803 : /*35498*/ OPC_RecordChild5, // #4 = $unorm
13804 : /*35499*/ OPC_RecordChild6, // #5 = $r128
13805 : /*35500*/ OPC_RecordChild7, // #6 = $da
13806 : /*35501*/ OPC_MoveChild, 8,
13807 : /*35503*/ OPC_RecordNode, // #7 = $glc
13808 : /*35504*/ OPC_MoveParent,
13809 : /*35505*/ OPC_MoveChild, 9,
13810 : /*35507*/ OPC_RecordNode, // #8 = $slc
13811 : /*35508*/ OPC_MoveParent,
13812 : /*35509*/ OPC_MoveChild, 10,
13813 : /*35511*/ OPC_RecordNode, // #9 = $tfe
13814 : /*35512*/ OPC_MoveParent,
13815 : /*35513*/ OPC_MoveChild, 11,
13816 : /*35515*/ OPC_RecordNode, // #10 = $lwe
13817 : /*35516*/ OPC_MoveParent,
13818 : /*35517*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13819 : /*35519*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13820 : /*35522*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13821 : /*35525*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13822 : /*35528*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13823 : /*35531*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13824 : /*35534*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13825 : /*35537*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13826 : /*35540*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13827 : /*35543*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4), 0,
13828 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13829 : // Src: (intrinsic_wo_chain:v4f32 4848:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13830 : // Dst: (IMAGE_SAMPLE_C_CL_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13831 : /*35561*/ /*Scope*/ 68, /*->35630*/
13832 : /*35562*/ OPC_CheckChild1Type, MVT::v8i32,
13833 : /*35564*/ OPC_RecordChild2, // #1 = $rsrc
13834 : /*35565*/ OPC_RecordChild3, // #2 = $sampler
13835 : /*35566*/ OPC_RecordChild4, // #3 = $dmask
13836 : /*35567*/ OPC_RecordChild5, // #4 = $unorm
13837 : /*35568*/ OPC_RecordChild6, // #5 = $r128
13838 : /*35569*/ OPC_RecordChild7, // #6 = $da
13839 : /*35570*/ OPC_MoveChild, 8,
13840 : /*35572*/ OPC_RecordNode, // #7 = $glc
13841 : /*35573*/ OPC_MoveParent,
13842 : /*35574*/ OPC_MoveChild, 9,
13843 : /*35576*/ OPC_RecordNode, // #8 = $slc
13844 : /*35577*/ OPC_MoveParent,
13845 : /*35578*/ OPC_MoveChild, 10,
13846 : /*35580*/ OPC_RecordNode, // #9 = $tfe
13847 : /*35581*/ OPC_MoveParent,
13848 : /*35582*/ OPC_MoveChild, 11,
13849 : /*35584*/ OPC_RecordNode, // #10 = $lwe
13850 : /*35585*/ OPC_MoveParent,
13851 : /*35586*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13852 : /*35588*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13853 : /*35591*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13854 : /*35594*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13855 : /*35597*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13856 : /*35600*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13857 : /*35603*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13858 : /*35606*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13859 : /*35609*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13860 : /*35612*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8), 0,
13861 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13862 : // Src: (intrinsic_wo_chain:v4f32 4848:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13863 : // Dst: (IMAGE_SAMPLE_C_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13864 : /*35630*/ /*Scope*/ 68, /*->35699*/
13865 : /*35631*/ OPC_CheckChild1Type, MVT::v16i32,
13866 : /*35633*/ OPC_RecordChild2, // #1 = $rsrc
13867 : /*35634*/ OPC_RecordChild3, // #2 = $sampler
13868 : /*35635*/ OPC_RecordChild4, // #3 = $dmask
13869 : /*35636*/ OPC_RecordChild5, // #4 = $unorm
13870 : /*35637*/ OPC_RecordChild6, // #5 = $r128
13871 : /*35638*/ OPC_RecordChild7, // #6 = $da
13872 : /*35639*/ OPC_MoveChild, 8,
13873 : /*35641*/ OPC_RecordNode, // #7 = $glc
13874 : /*35642*/ OPC_MoveParent,
13875 : /*35643*/ OPC_MoveChild, 9,
13876 : /*35645*/ OPC_RecordNode, // #8 = $slc
13877 : /*35646*/ OPC_MoveParent,
13878 : /*35647*/ OPC_MoveChild, 10,
13879 : /*35649*/ OPC_RecordNode, // #9 = $tfe
13880 : /*35650*/ OPC_MoveParent,
13881 : /*35651*/ OPC_MoveChild, 11,
13882 : /*35653*/ OPC_RecordNode, // #10 = $lwe
13883 : /*35654*/ OPC_MoveParent,
13884 : /*35655*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13885 : /*35657*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13886 : /*35660*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13887 : /*35663*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13888 : /*35666*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13889 : /*35669*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13890 : /*35672*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13891 : /*35675*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13892 : /*35678*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13893 : /*35681*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V16), 0,
13894 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13895 : // Src: (intrinsic_wo_chain:v4f32 4848:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13896 : // Dst: (IMAGE_SAMPLE_C_CL_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13897 : /*35699*/ 0, /*End of Scope*/
13898 : /*35700*/ /*Scope*/ 95|128,2/*351*/, /*->36053*/
13899 : /*35702*/ OPC_CheckChild0Integer, 116|128,37/*4852*/,
13900 : /*35705*/ OPC_RecordChild1, // #0 = $addr
13901 : /*35706*/ OPC_Scope, 68, /*->35776*/ // 5 children in Scope
13902 : /*35708*/ OPC_CheckChild1Type, MVT::i32,
13903 : /*35710*/ OPC_RecordChild2, // #1 = $rsrc
13904 : /*35711*/ OPC_RecordChild3, // #2 = $sampler
13905 : /*35712*/ OPC_RecordChild4, // #3 = $dmask
13906 : /*35713*/ OPC_RecordChild5, // #4 = $unorm
13907 : /*35714*/ OPC_RecordChild6, // #5 = $r128
13908 : /*35715*/ OPC_RecordChild7, // #6 = $da
13909 : /*35716*/ OPC_MoveChild, 8,
13910 : /*35718*/ OPC_RecordNode, // #7 = $glc
13911 : /*35719*/ OPC_MoveParent,
13912 : /*35720*/ OPC_MoveChild, 9,
13913 : /*35722*/ OPC_RecordNode, // #8 = $slc
13914 : /*35723*/ OPC_MoveParent,
13915 : /*35724*/ OPC_MoveChild, 10,
13916 : /*35726*/ OPC_RecordNode, // #9 = $tfe
13917 : /*35727*/ OPC_MoveParent,
13918 : /*35728*/ OPC_MoveChild, 11,
13919 : /*35730*/ OPC_RecordNode, // #10 = $lwe
13920 : /*35731*/ OPC_MoveParent,
13921 : /*35732*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13922 : /*35734*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13923 : /*35737*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13924 : /*35740*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13925 : /*35743*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13926 : /*35746*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13927 : /*35749*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13928 : /*35752*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13929 : /*35755*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13930 : /*35758*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V1), 0,
13931 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13932 : // Src: (intrinsic_wo_chain:v4f32 4852:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13933 : // Dst: (IMAGE_SAMPLE_C_D_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13934 : /*35776*/ /*Scope*/ 68, /*->35845*/
13935 : /*35777*/ OPC_CheckChild1Type, MVT::v2i32,
13936 : /*35779*/ OPC_RecordChild2, // #1 = $rsrc
13937 : /*35780*/ OPC_RecordChild3, // #2 = $sampler
13938 : /*35781*/ OPC_RecordChild4, // #3 = $dmask
13939 : /*35782*/ OPC_RecordChild5, // #4 = $unorm
13940 : /*35783*/ OPC_RecordChild6, // #5 = $r128
13941 : /*35784*/ OPC_RecordChild7, // #6 = $da
13942 : /*35785*/ OPC_MoveChild, 8,
13943 : /*35787*/ OPC_RecordNode, // #7 = $glc
13944 : /*35788*/ OPC_MoveParent,
13945 : /*35789*/ OPC_MoveChild, 9,
13946 : /*35791*/ OPC_RecordNode, // #8 = $slc
13947 : /*35792*/ OPC_MoveParent,
13948 : /*35793*/ OPC_MoveChild, 10,
13949 : /*35795*/ OPC_RecordNode, // #9 = $tfe
13950 : /*35796*/ OPC_MoveParent,
13951 : /*35797*/ OPC_MoveChild, 11,
13952 : /*35799*/ OPC_RecordNode, // #10 = $lwe
13953 : /*35800*/ OPC_MoveParent,
13954 : /*35801*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13955 : /*35803*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13956 : /*35806*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13957 : /*35809*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13958 : /*35812*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13959 : /*35815*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13960 : /*35818*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13961 : /*35821*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13962 : /*35824*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13963 : /*35827*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V2), 0,
13964 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13965 : // Src: (intrinsic_wo_chain:v4f32 4852:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13966 : // Dst: (IMAGE_SAMPLE_C_D_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
13967 : /*35845*/ /*Scope*/ 68, /*->35914*/
13968 : /*35846*/ OPC_CheckChild1Type, MVT::v4i32,
13969 : /*35848*/ OPC_RecordChild2, // #1 = $rsrc
13970 : /*35849*/ OPC_RecordChild3, // #2 = $sampler
13971 : /*35850*/ OPC_RecordChild4, // #3 = $dmask
13972 : /*35851*/ OPC_RecordChild5, // #4 = $unorm
13973 : /*35852*/ OPC_RecordChild6, // #5 = $r128
13974 : /*35853*/ OPC_RecordChild7, // #6 = $da
13975 : /*35854*/ OPC_MoveChild, 8,
13976 : /*35856*/ OPC_RecordNode, // #7 = $glc
13977 : /*35857*/ OPC_MoveParent,
13978 : /*35858*/ OPC_MoveChild, 9,
13979 : /*35860*/ OPC_RecordNode, // #8 = $slc
13980 : /*35861*/ OPC_MoveParent,
13981 : /*35862*/ OPC_MoveChild, 10,
13982 : /*35864*/ OPC_RecordNode, // #9 = $tfe
13983 : /*35865*/ OPC_MoveParent,
13984 : /*35866*/ OPC_MoveChild, 11,
13985 : /*35868*/ OPC_RecordNode, // #10 = $lwe
13986 : /*35869*/ OPC_MoveParent,
13987 : /*35870*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
13988 : /*35872*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
13989 : /*35875*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
13990 : /*35878*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
13991 : /*35881*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
13992 : /*35884*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
13993 : /*35887*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
13994 : /*35890*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
13995 : /*35893*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
13996 : /*35896*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4), 0,
13997 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
13998 : // Src: (intrinsic_wo_chain:v4f32 4852:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
13999 : // Dst: (IMAGE_SAMPLE_C_D_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14000 : /*35914*/ /*Scope*/ 68, /*->35983*/
14001 : /*35915*/ OPC_CheckChild1Type, MVT::v8i32,
14002 : /*35917*/ OPC_RecordChild2, // #1 = $rsrc
14003 : /*35918*/ OPC_RecordChild3, // #2 = $sampler
14004 : /*35919*/ OPC_RecordChild4, // #3 = $dmask
14005 : /*35920*/ OPC_RecordChild5, // #4 = $unorm
14006 : /*35921*/ OPC_RecordChild6, // #5 = $r128
14007 : /*35922*/ OPC_RecordChild7, // #6 = $da
14008 : /*35923*/ OPC_MoveChild, 8,
14009 : /*35925*/ OPC_RecordNode, // #7 = $glc
14010 : /*35926*/ OPC_MoveParent,
14011 : /*35927*/ OPC_MoveChild, 9,
14012 : /*35929*/ OPC_RecordNode, // #8 = $slc
14013 : /*35930*/ OPC_MoveParent,
14014 : /*35931*/ OPC_MoveChild, 10,
14015 : /*35933*/ OPC_RecordNode, // #9 = $tfe
14016 : /*35934*/ OPC_MoveParent,
14017 : /*35935*/ OPC_MoveChild, 11,
14018 : /*35937*/ OPC_RecordNode, // #10 = $lwe
14019 : /*35938*/ OPC_MoveParent,
14020 : /*35939*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14021 : /*35941*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14022 : /*35944*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14023 : /*35947*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14024 : /*35950*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14025 : /*35953*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14026 : /*35956*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14027 : /*35959*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14028 : /*35962*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14029 : /*35965*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8), 0,
14030 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14031 : // Src: (intrinsic_wo_chain:v4f32 4852:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14032 : // Dst: (IMAGE_SAMPLE_C_D_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14033 : /*35983*/ /*Scope*/ 68, /*->36052*/
14034 : /*35984*/ OPC_CheckChild1Type, MVT::v16i32,
14035 : /*35986*/ OPC_RecordChild2, // #1 = $rsrc
14036 : /*35987*/ OPC_RecordChild3, // #2 = $sampler
14037 : /*35988*/ OPC_RecordChild4, // #3 = $dmask
14038 : /*35989*/ OPC_RecordChild5, // #4 = $unorm
14039 : /*35990*/ OPC_RecordChild6, // #5 = $r128
14040 : /*35991*/ OPC_RecordChild7, // #6 = $da
14041 : /*35992*/ OPC_MoveChild, 8,
14042 : /*35994*/ OPC_RecordNode, // #7 = $glc
14043 : /*35995*/ OPC_MoveParent,
14044 : /*35996*/ OPC_MoveChild, 9,
14045 : /*35998*/ OPC_RecordNode, // #8 = $slc
14046 : /*35999*/ OPC_MoveParent,
14047 : /*36000*/ OPC_MoveChild, 10,
14048 : /*36002*/ OPC_RecordNode, // #9 = $tfe
14049 : /*36003*/ OPC_MoveParent,
14050 : /*36004*/ OPC_MoveChild, 11,
14051 : /*36006*/ OPC_RecordNode, // #10 = $lwe
14052 : /*36007*/ OPC_MoveParent,
14053 : /*36008*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14054 : /*36010*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14055 : /*36013*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14056 : /*36016*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14057 : /*36019*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14058 : /*36022*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14059 : /*36025*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14060 : /*36028*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14061 : /*36031*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14062 : /*36034*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V16), 0,
14063 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14064 : // Src: (intrinsic_wo_chain:v4f32 4852:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14065 : // Dst: (IMAGE_SAMPLE_C_D_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14066 : /*36052*/ 0, /*End of Scope*/
14067 : /*36053*/ /*Scope*/ 95|128,2/*351*/, /*->36406*/
14068 : /*36055*/ OPC_CheckChild0Integer, 115|128,37/*4851*/,
14069 : /*36058*/ OPC_RecordChild1, // #0 = $addr
14070 : /*36059*/ OPC_Scope, 68, /*->36129*/ // 5 children in Scope
14071 : /*36061*/ OPC_CheckChild1Type, MVT::i32,
14072 : /*36063*/ OPC_RecordChild2, // #1 = $rsrc
14073 : /*36064*/ OPC_RecordChild3, // #2 = $sampler
14074 : /*36065*/ OPC_RecordChild4, // #3 = $dmask
14075 : /*36066*/ OPC_RecordChild5, // #4 = $unorm
14076 : /*36067*/ OPC_RecordChild6, // #5 = $r128
14077 : /*36068*/ OPC_RecordChild7, // #6 = $da
14078 : /*36069*/ OPC_MoveChild, 8,
14079 : /*36071*/ OPC_RecordNode, // #7 = $glc
14080 : /*36072*/ OPC_MoveParent,
14081 : /*36073*/ OPC_MoveChild, 9,
14082 : /*36075*/ OPC_RecordNode, // #8 = $slc
14083 : /*36076*/ OPC_MoveParent,
14084 : /*36077*/ OPC_MoveChild, 10,
14085 : /*36079*/ OPC_RecordNode, // #9 = $tfe
14086 : /*36080*/ OPC_MoveParent,
14087 : /*36081*/ OPC_MoveChild, 11,
14088 : /*36083*/ OPC_RecordNode, // #10 = $lwe
14089 : /*36084*/ OPC_MoveParent,
14090 : /*36085*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14091 : /*36087*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14092 : /*36090*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14093 : /*36093*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14094 : /*36096*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14095 : /*36099*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14096 : /*36102*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14097 : /*36105*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14098 : /*36108*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14099 : /*36111*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V1), 0,
14100 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14101 : // Src: (intrinsic_wo_chain:v4f32 4851:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14102 : // Dst: (IMAGE_SAMPLE_C_D_CL_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14103 : /*36129*/ /*Scope*/ 68, /*->36198*/
14104 : /*36130*/ OPC_CheckChild1Type, MVT::v2i32,
14105 : /*36132*/ OPC_RecordChild2, // #1 = $rsrc
14106 : /*36133*/ OPC_RecordChild3, // #2 = $sampler
14107 : /*36134*/ OPC_RecordChild4, // #3 = $dmask
14108 : /*36135*/ OPC_RecordChild5, // #4 = $unorm
14109 : /*36136*/ OPC_RecordChild6, // #5 = $r128
14110 : /*36137*/ OPC_RecordChild7, // #6 = $da
14111 : /*36138*/ OPC_MoveChild, 8,
14112 : /*36140*/ OPC_RecordNode, // #7 = $glc
14113 : /*36141*/ OPC_MoveParent,
14114 : /*36142*/ OPC_MoveChild, 9,
14115 : /*36144*/ OPC_RecordNode, // #8 = $slc
14116 : /*36145*/ OPC_MoveParent,
14117 : /*36146*/ OPC_MoveChild, 10,
14118 : /*36148*/ OPC_RecordNode, // #9 = $tfe
14119 : /*36149*/ OPC_MoveParent,
14120 : /*36150*/ OPC_MoveChild, 11,
14121 : /*36152*/ OPC_RecordNode, // #10 = $lwe
14122 : /*36153*/ OPC_MoveParent,
14123 : /*36154*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14124 : /*36156*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14125 : /*36159*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14126 : /*36162*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14127 : /*36165*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14128 : /*36168*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14129 : /*36171*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14130 : /*36174*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14131 : /*36177*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14132 : /*36180*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V2), 0,
14133 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14134 : // Src: (intrinsic_wo_chain:v4f32 4851:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14135 : // Dst: (IMAGE_SAMPLE_C_D_CL_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14136 : /*36198*/ /*Scope*/ 68, /*->36267*/
14137 : /*36199*/ OPC_CheckChild1Type, MVT::v4i32,
14138 : /*36201*/ OPC_RecordChild2, // #1 = $rsrc
14139 : /*36202*/ OPC_RecordChild3, // #2 = $sampler
14140 : /*36203*/ OPC_RecordChild4, // #3 = $dmask
14141 : /*36204*/ OPC_RecordChild5, // #4 = $unorm
14142 : /*36205*/ OPC_RecordChild6, // #5 = $r128
14143 : /*36206*/ OPC_RecordChild7, // #6 = $da
14144 : /*36207*/ OPC_MoveChild, 8,
14145 : /*36209*/ OPC_RecordNode, // #7 = $glc
14146 : /*36210*/ OPC_MoveParent,
14147 : /*36211*/ OPC_MoveChild, 9,
14148 : /*36213*/ OPC_RecordNode, // #8 = $slc
14149 : /*36214*/ OPC_MoveParent,
14150 : /*36215*/ OPC_MoveChild, 10,
14151 : /*36217*/ OPC_RecordNode, // #9 = $tfe
14152 : /*36218*/ OPC_MoveParent,
14153 : /*36219*/ OPC_MoveChild, 11,
14154 : /*36221*/ OPC_RecordNode, // #10 = $lwe
14155 : /*36222*/ OPC_MoveParent,
14156 : /*36223*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14157 : /*36225*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14158 : /*36228*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14159 : /*36231*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14160 : /*36234*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14161 : /*36237*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14162 : /*36240*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14163 : /*36243*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14164 : /*36246*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14165 : /*36249*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4), 0,
14166 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14167 : // Src: (intrinsic_wo_chain:v4f32 4851:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14168 : // Dst: (IMAGE_SAMPLE_C_D_CL_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14169 : /*36267*/ /*Scope*/ 68, /*->36336*/
14170 : /*36268*/ OPC_CheckChild1Type, MVT::v8i32,
14171 : /*36270*/ OPC_RecordChild2, // #1 = $rsrc
14172 : /*36271*/ OPC_RecordChild3, // #2 = $sampler
14173 : /*36272*/ OPC_RecordChild4, // #3 = $dmask
14174 : /*36273*/ OPC_RecordChild5, // #4 = $unorm
14175 : /*36274*/ OPC_RecordChild6, // #5 = $r128
14176 : /*36275*/ OPC_RecordChild7, // #6 = $da
14177 : /*36276*/ OPC_MoveChild, 8,
14178 : /*36278*/ OPC_RecordNode, // #7 = $glc
14179 : /*36279*/ OPC_MoveParent,
14180 : /*36280*/ OPC_MoveChild, 9,
14181 : /*36282*/ OPC_RecordNode, // #8 = $slc
14182 : /*36283*/ OPC_MoveParent,
14183 : /*36284*/ OPC_MoveChild, 10,
14184 : /*36286*/ OPC_RecordNode, // #9 = $tfe
14185 : /*36287*/ OPC_MoveParent,
14186 : /*36288*/ OPC_MoveChild, 11,
14187 : /*36290*/ OPC_RecordNode, // #10 = $lwe
14188 : /*36291*/ OPC_MoveParent,
14189 : /*36292*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14190 : /*36294*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14191 : /*36297*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14192 : /*36300*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14193 : /*36303*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14194 : /*36306*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14195 : /*36309*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14196 : /*36312*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14197 : /*36315*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14198 : /*36318*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8), 0,
14199 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14200 : // Src: (intrinsic_wo_chain:v4f32 4851:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14201 : // Dst: (IMAGE_SAMPLE_C_D_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14202 : /*36336*/ /*Scope*/ 68, /*->36405*/
14203 : /*36337*/ OPC_CheckChild1Type, MVT::v16i32,
14204 : /*36339*/ OPC_RecordChild2, // #1 = $rsrc
14205 : /*36340*/ OPC_RecordChild3, // #2 = $sampler
14206 : /*36341*/ OPC_RecordChild4, // #3 = $dmask
14207 : /*36342*/ OPC_RecordChild5, // #4 = $unorm
14208 : /*36343*/ OPC_RecordChild6, // #5 = $r128
14209 : /*36344*/ OPC_RecordChild7, // #6 = $da
14210 : /*36345*/ OPC_MoveChild, 8,
14211 : /*36347*/ OPC_RecordNode, // #7 = $glc
14212 : /*36348*/ OPC_MoveParent,
14213 : /*36349*/ OPC_MoveChild, 9,
14214 : /*36351*/ OPC_RecordNode, // #8 = $slc
14215 : /*36352*/ OPC_MoveParent,
14216 : /*36353*/ OPC_MoveChild, 10,
14217 : /*36355*/ OPC_RecordNode, // #9 = $tfe
14218 : /*36356*/ OPC_MoveParent,
14219 : /*36357*/ OPC_MoveChild, 11,
14220 : /*36359*/ OPC_RecordNode, // #10 = $lwe
14221 : /*36360*/ OPC_MoveParent,
14222 : /*36361*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14223 : /*36363*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14224 : /*36366*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14225 : /*36369*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14226 : /*36372*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14227 : /*36375*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14228 : /*36378*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14229 : /*36381*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14230 : /*36384*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14231 : /*36387*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V16), 0,
14232 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14233 : // Src: (intrinsic_wo_chain:v4f32 4851:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14234 : // Dst: (IMAGE_SAMPLE_C_D_CL_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14235 : /*36405*/ 0, /*End of Scope*/
14236 : /*36406*/ /*Scope*/ 95|128,2/*351*/, /*->36759*/
14237 : /*36408*/ OPC_CheckChild0Integer, 118|128,37/*4854*/,
14238 : /*36411*/ OPC_RecordChild1, // #0 = $addr
14239 : /*36412*/ OPC_Scope, 68, /*->36482*/ // 5 children in Scope
14240 : /*36414*/ OPC_CheckChild1Type, MVT::i32,
14241 : /*36416*/ OPC_RecordChild2, // #1 = $rsrc
14242 : /*36417*/ OPC_RecordChild3, // #2 = $sampler
14243 : /*36418*/ OPC_RecordChild4, // #3 = $dmask
14244 : /*36419*/ OPC_RecordChild5, // #4 = $unorm
14245 : /*36420*/ OPC_RecordChild6, // #5 = $r128
14246 : /*36421*/ OPC_RecordChild7, // #6 = $da
14247 : /*36422*/ OPC_MoveChild, 8,
14248 : /*36424*/ OPC_RecordNode, // #7 = $glc
14249 : /*36425*/ OPC_MoveParent,
14250 : /*36426*/ OPC_MoveChild, 9,
14251 : /*36428*/ OPC_RecordNode, // #8 = $slc
14252 : /*36429*/ OPC_MoveParent,
14253 : /*36430*/ OPC_MoveChild, 10,
14254 : /*36432*/ OPC_RecordNode, // #9 = $tfe
14255 : /*36433*/ OPC_MoveParent,
14256 : /*36434*/ OPC_MoveChild, 11,
14257 : /*36436*/ OPC_RecordNode, // #10 = $lwe
14258 : /*36437*/ OPC_MoveParent,
14259 : /*36438*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14260 : /*36440*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14261 : /*36443*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14262 : /*36446*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14263 : /*36449*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14264 : /*36452*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14265 : /*36455*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14266 : /*36458*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14267 : /*36461*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14268 : /*36464*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V1), 0,
14269 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14270 : // Src: (intrinsic_wo_chain:v4f32 4854:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14271 : // Dst: (IMAGE_SAMPLE_C_L_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14272 : /*36482*/ /*Scope*/ 68, /*->36551*/
14273 : /*36483*/ OPC_CheckChild1Type, MVT::v2i32,
14274 : /*36485*/ OPC_RecordChild2, // #1 = $rsrc
14275 : /*36486*/ OPC_RecordChild3, // #2 = $sampler
14276 : /*36487*/ OPC_RecordChild4, // #3 = $dmask
14277 : /*36488*/ OPC_RecordChild5, // #4 = $unorm
14278 : /*36489*/ OPC_RecordChild6, // #5 = $r128
14279 : /*36490*/ OPC_RecordChild7, // #6 = $da
14280 : /*36491*/ OPC_MoveChild, 8,
14281 : /*36493*/ OPC_RecordNode, // #7 = $glc
14282 : /*36494*/ OPC_MoveParent,
14283 : /*36495*/ OPC_MoveChild, 9,
14284 : /*36497*/ OPC_RecordNode, // #8 = $slc
14285 : /*36498*/ OPC_MoveParent,
14286 : /*36499*/ OPC_MoveChild, 10,
14287 : /*36501*/ OPC_RecordNode, // #9 = $tfe
14288 : /*36502*/ OPC_MoveParent,
14289 : /*36503*/ OPC_MoveChild, 11,
14290 : /*36505*/ OPC_RecordNode, // #10 = $lwe
14291 : /*36506*/ OPC_MoveParent,
14292 : /*36507*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14293 : /*36509*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14294 : /*36512*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14295 : /*36515*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14296 : /*36518*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14297 : /*36521*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14298 : /*36524*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14299 : /*36527*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14300 : /*36530*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14301 : /*36533*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V2), 0,
14302 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14303 : // Src: (intrinsic_wo_chain:v4f32 4854:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14304 : // Dst: (IMAGE_SAMPLE_C_L_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14305 : /*36551*/ /*Scope*/ 68, /*->36620*/
14306 : /*36552*/ OPC_CheckChild1Type, MVT::v4i32,
14307 : /*36554*/ OPC_RecordChild2, // #1 = $rsrc
14308 : /*36555*/ OPC_RecordChild3, // #2 = $sampler
14309 : /*36556*/ OPC_RecordChild4, // #3 = $dmask
14310 : /*36557*/ OPC_RecordChild5, // #4 = $unorm
14311 : /*36558*/ OPC_RecordChild6, // #5 = $r128
14312 : /*36559*/ OPC_RecordChild7, // #6 = $da
14313 : /*36560*/ OPC_MoveChild, 8,
14314 : /*36562*/ OPC_RecordNode, // #7 = $glc
14315 : /*36563*/ OPC_MoveParent,
14316 : /*36564*/ OPC_MoveChild, 9,
14317 : /*36566*/ OPC_RecordNode, // #8 = $slc
14318 : /*36567*/ OPC_MoveParent,
14319 : /*36568*/ OPC_MoveChild, 10,
14320 : /*36570*/ OPC_RecordNode, // #9 = $tfe
14321 : /*36571*/ OPC_MoveParent,
14322 : /*36572*/ OPC_MoveChild, 11,
14323 : /*36574*/ OPC_RecordNode, // #10 = $lwe
14324 : /*36575*/ OPC_MoveParent,
14325 : /*36576*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14326 : /*36578*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14327 : /*36581*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14328 : /*36584*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14329 : /*36587*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14330 : /*36590*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14331 : /*36593*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14332 : /*36596*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14333 : /*36599*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14334 : /*36602*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4), 0,
14335 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14336 : // Src: (intrinsic_wo_chain:v4f32 4854:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14337 : // Dst: (IMAGE_SAMPLE_C_L_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14338 : /*36620*/ /*Scope*/ 68, /*->36689*/
14339 : /*36621*/ OPC_CheckChild1Type, MVT::v8i32,
14340 : /*36623*/ OPC_RecordChild2, // #1 = $rsrc
14341 : /*36624*/ OPC_RecordChild3, // #2 = $sampler
14342 : /*36625*/ OPC_RecordChild4, // #3 = $dmask
14343 : /*36626*/ OPC_RecordChild5, // #4 = $unorm
14344 : /*36627*/ OPC_RecordChild6, // #5 = $r128
14345 : /*36628*/ OPC_RecordChild7, // #6 = $da
14346 : /*36629*/ OPC_MoveChild, 8,
14347 : /*36631*/ OPC_RecordNode, // #7 = $glc
14348 : /*36632*/ OPC_MoveParent,
14349 : /*36633*/ OPC_MoveChild, 9,
14350 : /*36635*/ OPC_RecordNode, // #8 = $slc
14351 : /*36636*/ OPC_MoveParent,
14352 : /*36637*/ OPC_MoveChild, 10,
14353 : /*36639*/ OPC_RecordNode, // #9 = $tfe
14354 : /*36640*/ OPC_MoveParent,
14355 : /*36641*/ OPC_MoveChild, 11,
14356 : /*36643*/ OPC_RecordNode, // #10 = $lwe
14357 : /*36644*/ OPC_MoveParent,
14358 : /*36645*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14359 : /*36647*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14360 : /*36650*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14361 : /*36653*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14362 : /*36656*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14363 : /*36659*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14364 : /*36662*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14365 : /*36665*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14366 : /*36668*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14367 : /*36671*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8), 0,
14368 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14369 : // Src: (intrinsic_wo_chain:v4f32 4854:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14370 : // Dst: (IMAGE_SAMPLE_C_L_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14371 : /*36689*/ /*Scope*/ 68, /*->36758*/
14372 : /*36690*/ OPC_CheckChild1Type, MVT::v16i32,
14373 : /*36692*/ OPC_RecordChild2, // #1 = $rsrc
14374 : /*36693*/ OPC_RecordChild3, // #2 = $sampler
14375 : /*36694*/ OPC_RecordChild4, // #3 = $dmask
14376 : /*36695*/ OPC_RecordChild5, // #4 = $unorm
14377 : /*36696*/ OPC_RecordChild6, // #5 = $r128
14378 : /*36697*/ OPC_RecordChild7, // #6 = $da
14379 : /*36698*/ OPC_MoveChild, 8,
14380 : /*36700*/ OPC_RecordNode, // #7 = $glc
14381 : /*36701*/ OPC_MoveParent,
14382 : /*36702*/ OPC_MoveChild, 9,
14383 : /*36704*/ OPC_RecordNode, // #8 = $slc
14384 : /*36705*/ OPC_MoveParent,
14385 : /*36706*/ OPC_MoveChild, 10,
14386 : /*36708*/ OPC_RecordNode, // #9 = $tfe
14387 : /*36709*/ OPC_MoveParent,
14388 : /*36710*/ OPC_MoveChild, 11,
14389 : /*36712*/ OPC_RecordNode, // #10 = $lwe
14390 : /*36713*/ OPC_MoveParent,
14391 : /*36714*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14392 : /*36716*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14393 : /*36719*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14394 : /*36722*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14395 : /*36725*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14396 : /*36728*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14397 : /*36731*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14398 : /*36734*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14399 : /*36737*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14400 : /*36740*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V16), 0,
14401 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14402 : // Src: (intrinsic_wo_chain:v4f32 4854:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14403 : // Dst: (IMAGE_SAMPLE_C_L_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14404 : /*36758*/ 0, /*End of Scope*/
14405 : /*36759*/ /*Scope*/ 95|128,2/*351*/, /*->37112*/
14406 : /*36761*/ OPC_CheckChild0Integer, 106|128,37/*4842*/,
14407 : /*36764*/ OPC_RecordChild1, // #0 = $addr
14408 : /*36765*/ OPC_Scope, 68, /*->36835*/ // 5 children in Scope
14409 : /*36767*/ OPC_CheckChild1Type, MVT::i32,
14410 : /*36769*/ OPC_RecordChild2, // #1 = $rsrc
14411 : /*36770*/ OPC_RecordChild3, // #2 = $sampler
14412 : /*36771*/ OPC_RecordChild4, // #3 = $dmask
14413 : /*36772*/ OPC_RecordChild5, // #4 = $unorm
14414 : /*36773*/ OPC_RecordChild6, // #5 = $r128
14415 : /*36774*/ OPC_RecordChild7, // #6 = $da
14416 : /*36775*/ OPC_MoveChild, 8,
14417 : /*36777*/ OPC_RecordNode, // #7 = $glc
14418 : /*36778*/ OPC_MoveParent,
14419 : /*36779*/ OPC_MoveChild, 9,
14420 : /*36781*/ OPC_RecordNode, // #8 = $slc
14421 : /*36782*/ OPC_MoveParent,
14422 : /*36783*/ OPC_MoveChild, 10,
14423 : /*36785*/ OPC_RecordNode, // #9 = $tfe
14424 : /*36786*/ OPC_MoveParent,
14425 : /*36787*/ OPC_MoveChild, 11,
14426 : /*36789*/ OPC_RecordNode, // #10 = $lwe
14427 : /*36790*/ OPC_MoveParent,
14428 : /*36791*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14429 : /*36793*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14430 : /*36796*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14431 : /*36799*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14432 : /*36802*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14433 : /*36805*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14434 : /*36808*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14435 : /*36811*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14436 : /*36814*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14437 : /*36817*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V1), 0,
14438 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14439 : // Src: (intrinsic_wo_chain:v4f32 4842:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14440 : // Dst: (IMAGE_SAMPLE_C_B_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14441 : /*36835*/ /*Scope*/ 68, /*->36904*/
14442 : /*36836*/ OPC_CheckChild1Type, MVT::v2i32,
14443 : /*36838*/ OPC_RecordChild2, // #1 = $rsrc
14444 : /*36839*/ OPC_RecordChild3, // #2 = $sampler
14445 : /*36840*/ OPC_RecordChild4, // #3 = $dmask
14446 : /*36841*/ OPC_RecordChild5, // #4 = $unorm
14447 : /*36842*/ OPC_RecordChild6, // #5 = $r128
14448 : /*36843*/ OPC_RecordChild7, // #6 = $da
14449 : /*36844*/ OPC_MoveChild, 8,
14450 : /*36846*/ OPC_RecordNode, // #7 = $glc
14451 : /*36847*/ OPC_MoveParent,
14452 : /*36848*/ OPC_MoveChild, 9,
14453 : /*36850*/ OPC_RecordNode, // #8 = $slc
14454 : /*36851*/ OPC_MoveParent,
14455 : /*36852*/ OPC_MoveChild, 10,
14456 : /*36854*/ OPC_RecordNode, // #9 = $tfe
14457 : /*36855*/ OPC_MoveParent,
14458 : /*36856*/ OPC_MoveChild, 11,
14459 : /*36858*/ OPC_RecordNode, // #10 = $lwe
14460 : /*36859*/ OPC_MoveParent,
14461 : /*36860*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14462 : /*36862*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14463 : /*36865*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14464 : /*36868*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14465 : /*36871*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14466 : /*36874*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14467 : /*36877*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14468 : /*36880*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14469 : /*36883*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14470 : /*36886*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V2), 0,
14471 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14472 : // Src: (intrinsic_wo_chain:v4f32 4842:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14473 : // Dst: (IMAGE_SAMPLE_C_B_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14474 : /*36904*/ /*Scope*/ 68, /*->36973*/
14475 : /*36905*/ OPC_CheckChild1Type, MVT::v4i32,
14476 : /*36907*/ OPC_RecordChild2, // #1 = $rsrc
14477 : /*36908*/ OPC_RecordChild3, // #2 = $sampler
14478 : /*36909*/ OPC_RecordChild4, // #3 = $dmask
14479 : /*36910*/ OPC_RecordChild5, // #4 = $unorm
14480 : /*36911*/ OPC_RecordChild6, // #5 = $r128
14481 : /*36912*/ OPC_RecordChild7, // #6 = $da
14482 : /*36913*/ OPC_MoveChild, 8,
14483 : /*36915*/ OPC_RecordNode, // #7 = $glc
14484 : /*36916*/ OPC_MoveParent,
14485 : /*36917*/ OPC_MoveChild, 9,
14486 : /*36919*/ OPC_RecordNode, // #8 = $slc
14487 : /*36920*/ OPC_MoveParent,
14488 : /*36921*/ OPC_MoveChild, 10,
14489 : /*36923*/ OPC_RecordNode, // #9 = $tfe
14490 : /*36924*/ OPC_MoveParent,
14491 : /*36925*/ OPC_MoveChild, 11,
14492 : /*36927*/ OPC_RecordNode, // #10 = $lwe
14493 : /*36928*/ OPC_MoveParent,
14494 : /*36929*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14495 : /*36931*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14496 : /*36934*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14497 : /*36937*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14498 : /*36940*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14499 : /*36943*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14500 : /*36946*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14501 : /*36949*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14502 : /*36952*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14503 : /*36955*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4), 0,
14504 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14505 : // Src: (intrinsic_wo_chain:v4f32 4842:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14506 : // Dst: (IMAGE_SAMPLE_C_B_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14507 : /*36973*/ /*Scope*/ 68, /*->37042*/
14508 : /*36974*/ OPC_CheckChild1Type, MVT::v8i32,
14509 : /*36976*/ OPC_RecordChild2, // #1 = $rsrc
14510 : /*36977*/ OPC_RecordChild3, // #2 = $sampler
14511 : /*36978*/ OPC_RecordChild4, // #3 = $dmask
14512 : /*36979*/ OPC_RecordChild5, // #4 = $unorm
14513 : /*36980*/ OPC_RecordChild6, // #5 = $r128
14514 : /*36981*/ OPC_RecordChild7, // #6 = $da
14515 : /*36982*/ OPC_MoveChild, 8,
14516 : /*36984*/ OPC_RecordNode, // #7 = $glc
14517 : /*36985*/ OPC_MoveParent,
14518 : /*36986*/ OPC_MoveChild, 9,
14519 : /*36988*/ OPC_RecordNode, // #8 = $slc
14520 : /*36989*/ OPC_MoveParent,
14521 : /*36990*/ OPC_MoveChild, 10,
14522 : /*36992*/ OPC_RecordNode, // #9 = $tfe
14523 : /*36993*/ OPC_MoveParent,
14524 : /*36994*/ OPC_MoveChild, 11,
14525 : /*36996*/ OPC_RecordNode, // #10 = $lwe
14526 : /*36997*/ OPC_MoveParent,
14527 : /*36998*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14528 : /*37000*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14529 : /*37003*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14530 : /*37006*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14531 : /*37009*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14532 : /*37012*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14533 : /*37015*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14534 : /*37018*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14535 : /*37021*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14536 : /*37024*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8), 0,
14537 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14538 : // Src: (intrinsic_wo_chain:v4f32 4842:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14539 : // Dst: (IMAGE_SAMPLE_C_B_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14540 : /*37042*/ /*Scope*/ 68, /*->37111*/
14541 : /*37043*/ OPC_CheckChild1Type, MVT::v16i32,
14542 : /*37045*/ OPC_RecordChild2, // #1 = $rsrc
14543 : /*37046*/ OPC_RecordChild3, // #2 = $sampler
14544 : /*37047*/ OPC_RecordChild4, // #3 = $dmask
14545 : /*37048*/ OPC_RecordChild5, // #4 = $unorm
14546 : /*37049*/ OPC_RecordChild6, // #5 = $r128
14547 : /*37050*/ OPC_RecordChild7, // #6 = $da
14548 : /*37051*/ OPC_MoveChild, 8,
14549 : /*37053*/ OPC_RecordNode, // #7 = $glc
14550 : /*37054*/ OPC_MoveParent,
14551 : /*37055*/ OPC_MoveChild, 9,
14552 : /*37057*/ OPC_RecordNode, // #8 = $slc
14553 : /*37058*/ OPC_MoveParent,
14554 : /*37059*/ OPC_MoveChild, 10,
14555 : /*37061*/ OPC_RecordNode, // #9 = $tfe
14556 : /*37062*/ OPC_MoveParent,
14557 : /*37063*/ OPC_MoveChild, 11,
14558 : /*37065*/ OPC_RecordNode, // #10 = $lwe
14559 : /*37066*/ OPC_MoveParent,
14560 : /*37067*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14561 : /*37069*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14562 : /*37072*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14563 : /*37075*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14564 : /*37078*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14565 : /*37081*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14566 : /*37084*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14567 : /*37087*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14568 : /*37090*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14569 : /*37093*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V16), 0,
14570 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14571 : // Src: (intrinsic_wo_chain:v4f32 4842:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14572 : // Dst: (IMAGE_SAMPLE_C_B_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14573 : /*37111*/ 0, /*End of Scope*/
14574 : /*37112*/ /*Scope*/ 95|128,2/*351*/, /*->37465*/
14575 : /*37114*/ OPC_CheckChild0Integer, 105|128,37/*4841*/,
14576 : /*37117*/ OPC_RecordChild1, // #0 = $addr
14577 : /*37118*/ OPC_Scope, 68, /*->37188*/ // 5 children in Scope
14578 : /*37120*/ OPC_CheckChild1Type, MVT::i32,
14579 : /*37122*/ OPC_RecordChild2, // #1 = $rsrc
14580 : /*37123*/ OPC_RecordChild3, // #2 = $sampler
14581 : /*37124*/ OPC_RecordChild4, // #3 = $dmask
14582 : /*37125*/ OPC_RecordChild5, // #4 = $unorm
14583 : /*37126*/ OPC_RecordChild6, // #5 = $r128
14584 : /*37127*/ OPC_RecordChild7, // #6 = $da
14585 : /*37128*/ OPC_MoveChild, 8,
14586 : /*37130*/ OPC_RecordNode, // #7 = $glc
14587 : /*37131*/ OPC_MoveParent,
14588 : /*37132*/ OPC_MoveChild, 9,
14589 : /*37134*/ OPC_RecordNode, // #8 = $slc
14590 : /*37135*/ OPC_MoveParent,
14591 : /*37136*/ OPC_MoveChild, 10,
14592 : /*37138*/ OPC_RecordNode, // #9 = $tfe
14593 : /*37139*/ OPC_MoveParent,
14594 : /*37140*/ OPC_MoveChild, 11,
14595 : /*37142*/ OPC_RecordNode, // #10 = $lwe
14596 : /*37143*/ OPC_MoveParent,
14597 : /*37144*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14598 : /*37146*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14599 : /*37149*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14600 : /*37152*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14601 : /*37155*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14602 : /*37158*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14603 : /*37161*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14604 : /*37164*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14605 : /*37167*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14606 : /*37170*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V1), 0,
14607 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14608 : // Src: (intrinsic_wo_chain:v4f32 4841:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14609 : // Dst: (IMAGE_SAMPLE_C_B_CL_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14610 : /*37188*/ /*Scope*/ 68, /*->37257*/
14611 : /*37189*/ OPC_CheckChild1Type, MVT::v2i32,
14612 : /*37191*/ OPC_RecordChild2, // #1 = $rsrc
14613 : /*37192*/ OPC_RecordChild3, // #2 = $sampler
14614 : /*37193*/ OPC_RecordChild4, // #3 = $dmask
14615 : /*37194*/ OPC_RecordChild5, // #4 = $unorm
14616 : /*37195*/ OPC_RecordChild6, // #5 = $r128
14617 : /*37196*/ OPC_RecordChild7, // #6 = $da
14618 : /*37197*/ OPC_MoveChild, 8,
14619 : /*37199*/ OPC_RecordNode, // #7 = $glc
14620 : /*37200*/ OPC_MoveParent,
14621 : /*37201*/ OPC_MoveChild, 9,
14622 : /*37203*/ OPC_RecordNode, // #8 = $slc
14623 : /*37204*/ OPC_MoveParent,
14624 : /*37205*/ OPC_MoveChild, 10,
14625 : /*37207*/ OPC_RecordNode, // #9 = $tfe
14626 : /*37208*/ OPC_MoveParent,
14627 : /*37209*/ OPC_MoveChild, 11,
14628 : /*37211*/ OPC_RecordNode, // #10 = $lwe
14629 : /*37212*/ OPC_MoveParent,
14630 : /*37213*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14631 : /*37215*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14632 : /*37218*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14633 : /*37221*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14634 : /*37224*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14635 : /*37227*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14636 : /*37230*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14637 : /*37233*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14638 : /*37236*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14639 : /*37239*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V2), 0,
14640 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14641 : // Src: (intrinsic_wo_chain:v4f32 4841:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14642 : // Dst: (IMAGE_SAMPLE_C_B_CL_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14643 : /*37257*/ /*Scope*/ 68, /*->37326*/
14644 : /*37258*/ OPC_CheckChild1Type, MVT::v4i32,
14645 : /*37260*/ OPC_RecordChild2, // #1 = $rsrc
14646 : /*37261*/ OPC_RecordChild3, // #2 = $sampler
14647 : /*37262*/ OPC_RecordChild4, // #3 = $dmask
14648 : /*37263*/ OPC_RecordChild5, // #4 = $unorm
14649 : /*37264*/ OPC_RecordChild6, // #5 = $r128
14650 : /*37265*/ OPC_RecordChild7, // #6 = $da
14651 : /*37266*/ OPC_MoveChild, 8,
14652 : /*37268*/ OPC_RecordNode, // #7 = $glc
14653 : /*37269*/ OPC_MoveParent,
14654 : /*37270*/ OPC_MoveChild, 9,
14655 : /*37272*/ OPC_RecordNode, // #8 = $slc
14656 : /*37273*/ OPC_MoveParent,
14657 : /*37274*/ OPC_MoveChild, 10,
14658 : /*37276*/ OPC_RecordNode, // #9 = $tfe
14659 : /*37277*/ OPC_MoveParent,
14660 : /*37278*/ OPC_MoveChild, 11,
14661 : /*37280*/ OPC_RecordNode, // #10 = $lwe
14662 : /*37281*/ OPC_MoveParent,
14663 : /*37282*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14664 : /*37284*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14665 : /*37287*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14666 : /*37290*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14667 : /*37293*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14668 : /*37296*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14669 : /*37299*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14670 : /*37302*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14671 : /*37305*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14672 : /*37308*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4), 0,
14673 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14674 : // Src: (intrinsic_wo_chain:v4f32 4841:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14675 : // Dst: (IMAGE_SAMPLE_C_B_CL_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14676 : /*37326*/ /*Scope*/ 68, /*->37395*/
14677 : /*37327*/ OPC_CheckChild1Type, MVT::v8i32,
14678 : /*37329*/ OPC_RecordChild2, // #1 = $rsrc
14679 : /*37330*/ OPC_RecordChild3, // #2 = $sampler
14680 : /*37331*/ OPC_RecordChild4, // #3 = $dmask
14681 : /*37332*/ OPC_RecordChild5, // #4 = $unorm
14682 : /*37333*/ OPC_RecordChild6, // #5 = $r128
14683 : /*37334*/ OPC_RecordChild7, // #6 = $da
14684 : /*37335*/ OPC_MoveChild, 8,
14685 : /*37337*/ OPC_RecordNode, // #7 = $glc
14686 : /*37338*/ OPC_MoveParent,
14687 : /*37339*/ OPC_MoveChild, 9,
14688 : /*37341*/ OPC_RecordNode, // #8 = $slc
14689 : /*37342*/ OPC_MoveParent,
14690 : /*37343*/ OPC_MoveChild, 10,
14691 : /*37345*/ OPC_RecordNode, // #9 = $tfe
14692 : /*37346*/ OPC_MoveParent,
14693 : /*37347*/ OPC_MoveChild, 11,
14694 : /*37349*/ OPC_RecordNode, // #10 = $lwe
14695 : /*37350*/ OPC_MoveParent,
14696 : /*37351*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14697 : /*37353*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14698 : /*37356*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14699 : /*37359*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14700 : /*37362*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14701 : /*37365*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14702 : /*37368*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14703 : /*37371*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14704 : /*37374*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14705 : /*37377*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8), 0,
14706 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14707 : // Src: (intrinsic_wo_chain:v4f32 4841:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14708 : // Dst: (IMAGE_SAMPLE_C_B_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14709 : /*37395*/ /*Scope*/ 68, /*->37464*/
14710 : /*37396*/ OPC_CheckChild1Type, MVT::v16i32,
14711 : /*37398*/ OPC_RecordChild2, // #1 = $rsrc
14712 : /*37399*/ OPC_RecordChild3, // #2 = $sampler
14713 : /*37400*/ OPC_RecordChild4, // #3 = $dmask
14714 : /*37401*/ OPC_RecordChild5, // #4 = $unorm
14715 : /*37402*/ OPC_RecordChild6, // #5 = $r128
14716 : /*37403*/ OPC_RecordChild7, // #6 = $da
14717 : /*37404*/ OPC_MoveChild, 8,
14718 : /*37406*/ OPC_RecordNode, // #7 = $glc
14719 : /*37407*/ OPC_MoveParent,
14720 : /*37408*/ OPC_MoveChild, 9,
14721 : /*37410*/ OPC_RecordNode, // #8 = $slc
14722 : /*37411*/ OPC_MoveParent,
14723 : /*37412*/ OPC_MoveChild, 10,
14724 : /*37414*/ OPC_RecordNode, // #9 = $tfe
14725 : /*37415*/ OPC_MoveParent,
14726 : /*37416*/ OPC_MoveChild, 11,
14727 : /*37418*/ OPC_RecordNode, // #10 = $lwe
14728 : /*37419*/ OPC_MoveParent,
14729 : /*37420*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14730 : /*37422*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14731 : /*37425*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14732 : /*37428*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14733 : /*37431*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14734 : /*37434*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14735 : /*37437*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14736 : /*37440*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14737 : /*37443*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14738 : /*37446*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V16), 0,
14739 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14740 : // Src: (intrinsic_wo_chain:v4f32 4841:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14741 : // Dst: (IMAGE_SAMPLE_C_B_CL_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14742 : /*37464*/ 0, /*End of Scope*/
14743 : /*37465*/ /*Scope*/ 95|128,2/*351*/, /*->37818*/
14744 : /*37467*/ OPC_CheckChild0Integer, 120|128,37/*4856*/,
14745 : /*37470*/ OPC_RecordChild1, // #0 = $addr
14746 : /*37471*/ OPC_Scope, 68, /*->37541*/ // 5 children in Scope
14747 : /*37473*/ OPC_CheckChild1Type, MVT::i32,
14748 : /*37475*/ OPC_RecordChild2, // #1 = $rsrc
14749 : /*37476*/ OPC_RecordChild3, // #2 = $sampler
14750 : /*37477*/ OPC_RecordChild4, // #3 = $dmask
14751 : /*37478*/ OPC_RecordChild5, // #4 = $unorm
14752 : /*37479*/ OPC_RecordChild6, // #5 = $r128
14753 : /*37480*/ OPC_RecordChild7, // #6 = $da
14754 : /*37481*/ OPC_MoveChild, 8,
14755 : /*37483*/ OPC_RecordNode, // #7 = $glc
14756 : /*37484*/ OPC_MoveParent,
14757 : /*37485*/ OPC_MoveChild, 9,
14758 : /*37487*/ OPC_RecordNode, // #8 = $slc
14759 : /*37488*/ OPC_MoveParent,
14760 : /*37489*/ OPC_MoveChild, 10,
14761 : /*37491*/ OPC_RecordNode, // #9 = $tfe
14762 : /*37492*/ OPC_MoveParent,
14763 : /*37493*/ OPC_MoveChild, 11,
14764 : /*37495*/ OPC_RecordNode, // #10 = $lwe
14765 : /*37496*/ OPC_MoveParent,
14766 : /*37497*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14767 : /*37499*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14768 : /*37502*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14769 : /*37505*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14770 : /*37508*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14771 : /*37511*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14772 : /*37514*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14773 : /*37517*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14774 : /*37520*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14775 : /*37523*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V1), 0,
14776 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14777 : // Src: (intrinsic_wo_chain:v4f32 4856:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14778 : // Dst: (IMAGE_SAMPLE_C_LZ_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14779 : /*37541*/ /*Scope*/ 68, /*->37610*/
14780 : /*37542*/ OPC_CheckChild1Type, MVT::v2i32,
14781 : /*37544*/ OPC_RecordChild2, // #1 = $rsrc
14782 : /*37545*/ OPC_RecordChild3, // #2 = $sampler
14783 : /*37546*/ OPC_RecordChild4, // #3 = $dmask
14784 : /*37547*/ OPC_RecordChild5, // #4 = $unorm
14785 : /*37548*/ OPC_RecordChild6, // #5 = $r128
14786 : /*37549*/ OPC_RecordChild7, // #6 = $da
14787 : /*37550*/ OPC_MoveChild, 8,
14788 : /*37552*/ OPC_RecordNode, // #7 = $glc
14789 : /*37553*/ OPC_MoveParent,
14790 : /*37554*/ OPC_MoveChild, 9,
14791 : /*37556*/ OPC_RecordNode, // #8 = $slc
14792 : /*37557*/ OPC_MoveParent,
14793 : /*37558*/ OPC_MoveChild, 10,
14794 : /*37560*/ OPC_RecordNode, // #9 = $tfe
14795 : /*37561*/ OPC_MoveParent,
14796 : /*37562*/ OPC_MoveChild, 11,
14797 : /*37564*/ OPC_RecordNode, // #10 = $lwe
14798 : /*37565*/ OPC_MoveParent,
14799 : /*37566*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14800 : /*37568*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14801 : /*37571*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14802 : /*37574*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14803 : /*37577*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14804 : /*37580*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14805 : /*37583*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14806 : /*37586*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14807 : /*37589*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14808 : /*37592*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V2), 0,
14809 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14810 : // Src: (intrinsic_wo_chain:v4f32 4856:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14811 : // Dst: (IMAGE_SAMPLE_C_LZ_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14812 : /*37610*/ /*Scope*/ 68, /*->37679*/
14813 : /*37611*/ OPC_CheckChild1Type, MVT::v4i32,
14814 : /*37613*/ OPC_RecordChild2, // #1 = $rsrc
14815 : /*37614*/ OPC_RecordChild3, // #2 = $sampler
14816 : /*37615*/ OPC_RecordChild4, // #3 = $dmask
14817 : /*37616*/ OPC_RecordChild5, // #4 = $unorm
14818 : /*37617*/ OPC_RecordChild6, // #5 = $r128
14819 : /*37618*/ OPC_RecordChild7, // #6 = $da
14820 : /*37619*/ OPC_MoveChild, 8,
14821 : /*37621*/ OPC_RecordNode, // #7 = $glc
14822 : /*37622*/ OPC_MoveParent,
14823 : /*37623*/ OPC_MoveChild, 9,
14824 : /*37625*/ OPC_RecordNode, // #8 = $slc
14825 : /*37626*/ OPC_MoveParent,
14826 : /*37627*/ OPC_MoveChild, 10,
14827 : /*37629*/ OPC_RecordNode, // #9 = $tfe
14828 : /*37630*/ OPC_MoveParent,
14829 : /*37631*/ OPC_MoveChild, 11,
14830 : /*37633*/ OPC_RecordNode, // #10 = $lwe
14831 : /*37634*/ OPC_MoveParent,
14832 : /*37635*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14833 : /*37637*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14834 : /*37640*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14835 : /*37643*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14836 : /*37646*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14837 : /*37649*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14838 : /*37652*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14839 : /*37655*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14840 : /*37658*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14841 : /*37661*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4), 0,
14842 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14843 : // Src: (intrinsic_wo_chain:v4f32 4856:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14844 : // Dst: (IMAGE_SAMPLE_C_LZ_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14845 : /*37679*/ /*Scope*/ 68, /*->37748*/
14846 : /*37680*/ OPC_CheckChild1Type, MVT::v8i32,
14847 : /*37682*/ OPC_RecordChild2, // #1 = $rsrc
14848 : /*37683*/ OPC_RecordChild3, // #2 = $sampler
14849 : /*37684*/ OPC_RecordChild4, // #3 = $dmask
14850 : /*37685*/ OPC_RecordChild5, // #4 = $unorm
14851 : /*37686*/ OPC_RecordChild6, // #5 = $r128
14852 : /*37687*/ OPC_RecordChild7, // #6 = $da
14853 : /*37688*/ OPC_MoveChild, 8,
14854 : /*37690*/ OPC_RecordNode, // #7 = $glc
14855 : /*37691*/ OPC_MoveParent,
14856 : /*37692*/ OPC_MoveChild, 9,
14857 : /*37694*/ OPC_RecordNode, // #8 = $slc
14858 : /*37695*/ OPC_MoveParent,
14859 : /*37696*/ OPC_MoveChild, 10,
14860 : /*37698*/ OPC_RecordNode, // #9 = $tfe
14861 : /*37699*/ OPC_MoveParent,
14862 : /*37700*/ OPC_MoveChild, 11,
14863 : /*37702*/ OPC_RecordNode, // #10 = $lwe
14864 : /*37703*/ OPC_MoveParent,
14865 : /*37704*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14866 : /*37706*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14867 : /*37709*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14868 : /*37712*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14869 : /*37715*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14870 : /*37718*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14871 : /*37721*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14872 : /*37724*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14873 : /*37727*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14874 : /*37730*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8), 0,
14875 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14876 : // Src: (intrinsic_wo_chain:v4f32 4856:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14877 : // Dst: (IMAGE_SAMPLE_C_LZ_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14878 : /*37748*/ /*Scope*/ 68, /*->37817*/
14879 : /*37749*/ OPC_CheckChild1Type, MVT::v16i32,
14880 : /*37751*/ OPC_RecordChild2, // #1 = $rsrc
14881 : /*37752*/ OPC_RecordChild3, // #2 = $sampler
14882 : /*37753*/ OPC_RecordChild4, // #3 = $dmask
14883 : /*37754*/ OPC_RecordChild5, // #4 = $unorm
14884 : /*37755*/ OPC_RecordChild6, // #5 = $r128
14885 : /*37756*/ OPC_RecordChild7, // #6 = $da
14886 : /*37757*/ OPC_MoveChild, 8,
14887 : /*37759*/ OPC_RecordNode, // #7 = $glc
14888 : /*37760*/ OPC_MoveParent,
14889 : /*37761*/ OPC_MoveChild, 9,
14890 : /*37763*/ OPC_RecordNode, // #8 = $slc
14891 : /*37764*/ OPC_MoveParent,
14892 : /*37765*/ OPC_MoveChild, 10,
14893 : /*37767*/ OPC_RecordNode, // #9 = $tfe
14894 : /*37768*/ OPC_MoveParent,
14895 : /*37769*/ OPC_MoveChild, 11,
14896 : /*37771*/ OPC_RecordNode, // #10 = $lwe
14897 : /*37772*/ OPC_MoveParent,
14898 : /*37773*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14899 : /*37775*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14900 : /*37778*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14901 : /*37781*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14902 : /*37784*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14903 : /*37787*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14904 : /*37790*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14905 : /*37793*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14906 : /*37796*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14907 : /*37799*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V16), 0,
14908 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14909 : // Src: (intrinsic_wo_chain:v4f32 4856:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14910 : // Dst: (IMAGE_SAMPLE_C_LZ_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14911 : /*37817*/ 0, /*End of Scope*/
14912 : /*37818*/ /*Scope*/ 95|128,2/*351*/, /*->38171*/
14913 : /*37820*/ OPC_CheckChild0Integer, 110|128,37/*4846*/,
14914 : /*37823*/ OPC_RecordChild1, // #0 = $addr
14915 : /*37824*/ OPC_Scope, 68, /*->37894*/ // 5 children in Scope
14916 : /*37826*/ OPC_CheckChild1Type, MVT::i32,
14917 : /*37828*/ OPC_RecordChild2, // #1 = $rsrc
14918 : /*37829*/ OPC_RecordChild3, // #2 = $sampler
14919 : /*37830*/ OPC_RecordChild4, // #3 = $dmask
14920 : /*37831*/ OPC_RecordChild5, // #4 = $unorm
14921 : /*37832*/ OPC_RecordChild6, // #5 = $r128
14922 : /*37833*/ OPC_RecordChild7, // #6 = $da
14923 : /*37834*/ OPC_MoveChild, 8,
14924 : /*37836*/ OPC_RecordNode, // #7 = $glc
14925 : /*37837*/ OPC_MoveParent,
14926 : /*37838*/ OPC_MoveChild, 9,
14927 : /*37840*/ OPC_RecordNode, // #8 = $slc
14928 : /*37841*/ OPC_MoveParent,
14929 : /*37842*/ OPC_MoveChild, 10,
14930 : /*37844*/ OPC_RecordNode, // #9 = $tfe
14931 : /*37845*/ OPC_MoveParent,
14932 : /*37846*/ OPC_MoveChild, 11,
14933 : /*37848*/ OPC_RecordNode, // #10 = $lwe
14934 : /*37849*/ OPC_MoveParent,
14935 : /*37850*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14936 : /*37852*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14937 : /*37855*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14938 : /*37858*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14939 : /*37861*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14940 : /*37864*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14941 : /*37867*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14942 : /*37870*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14943 : /*37873*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14944 : /*37876*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V1), 0,
14945 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14946 : // Src: (intrinsic_wo_chain:v4f32 4846:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14947 : // Dst: (IMAGE_SAMPLE_C_CD_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14948 : /*37894*/ /*Scope*/ 68, /*->37963*/
14949 : /*37895*/ OPC_CheckChild1Type, MVT::v2i32,
14950 : /*37897*/ OPC_RecordChild2, // #1 = $rsrc
14951 : /*37898*/ OPC_RecordChild3, // #2 = $sampler
14952 : /*37899*/ OPC_RecordChild4, // #3 = $dmask
14953 : /*37900*/ OPC_RecordChild5, // #4 = $unorm
14954 : /*37901*/ OPC_RecordChild6, // #5 = $r128
14955 : /*37902*/ OPC_RecordChild7, // #6 = $da
14956 : /*37903*/ OPC_MoveChild, 8,
14957 : /*37905*/ OPC_RecordNode, // #7 = $glc
14958 : /*37906*/ OPC_MoveParent,
14959 : /*37907*/ OPC_MoveChild, 9,
14960 : /*37909*/ OPC_RecordNode, // #8 = $slc
14961 : /*37910*/ OPC_MoveParent,
14962 : /*37911*/ OPC_MoveChild, 10,
14963 : /*37913*/ OPC_RecordNode, // #9 = $tfe
14964 : /*37914*/ OPC_MoveParent,
14965 : /*37915*/ OPC_MoveChild, 11,
14966 : /*37917*/ OPC_RecordNode, // #10 = $lwe
14967 : /*37918*/ OPC_MoveParent,
14968 : /*37919*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
14969 : /*37921*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
14970 : /*37924*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
14971 : /*37927*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
14972 : /*37930*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
14973 : /*37933*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
14974 : /*37936*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
14975 : /*37939*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
14976 : /*37942*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
14977 : /*37945*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V2), 0,
14978 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
14979 : // Src: (intrinsic_wo_chain:v4f32 4846:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
14980 : // Dst: (IMAGE_SAMPLE_C_CD_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
14981 : /*37963*/ /*Scope*/ 68, /*->38032*/
14982 : /*37964*/ OPC_CheckChild1Type, MVT::v4i32,
14983 : /*37966*/ OPC_RecordChild2, // #1 = $rsrc
14984 : /*37967*/ OPC_RecordChild3, // #2 = $sampler
14985 : /*37968*/ OPC_RecordChild4, // #3 = $dmask
14986 : /*37969*/ OPC_RecordChild5, // #4 = $unorm
14987 : /*37970*/ OPC_RecordChild6, // #5 = $r128
14988 : /*37971*/ OPC_RecordChild7, // #6 = $da
14989 : /*37972*/ OPC_MoveChild, 8,
14990 : /*37974*/ OPC_RecordNode, // #7 = $glc
14991 : /*37975*/ OPC_MoveParent,
14992 : /*37976*/ OPC_MoveChild, 9,
14993 : /*37978*/ OPC_RecordNode, // #8 = $slc
14994 : /*37979*/ OPC_MoveParent,
14995 : /*37980*/ OPC_MoveChild, 10,
14996 : /*37982*/ OPC_RecordNode, // #9 = $tfe
14997 : /*37983*/ OPC_MoveParent,
14998 : /*37984*/ OPC_MoveChild, 11,
14999 : /*37986*/ OPC_RecordNode, // #10 = $lwe
15000 : /*37987*/ OPC_MoveParent,
15001 : /*37988*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15002 : /*37990*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15003 : /*37993*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15004 : /*37996*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15005 : /*37999*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15006 : /*38002*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15007 : /*38005*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15008 : /*38008*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15009 : /*38011*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15010 : /*38014*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4), 0,
15011 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15012 : // Src: (intrinsic_wo_chain:v4f32 4846:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15013 : // Dst: (IMAGE_SAMPLE_C_CD_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15014 : /*38032*/ /*Scope*/ 68, /*->38101*/
15015 : /*38033*/ OPC_CheckChild1Type, MVT::v8i32,
15016 : /*38035*/ OPC_RecordChild2, // #1 = $rsrc
15017 : /*38036*/ OPC_RecordChild3, // #2 = $sampler
15018 : /*38037*/ OPC_RecordChild4, // #3 = $dmask
15019 : /*38038*/ OPC_RecordChild5, // #4 = $unorm
15020 : /*38039*/ OPC_RecordChild6, // #5 = $r128
15021 : /*38040*/ OPC_RecordChild7, // #6 = $da
15022 : /*38041*/ OPC_MoveChild, 8,
15023 : /*38043*/ OPC_RecordNode, // #7 = $glc
15024 : /*38044*/ OPC_MoveParent,
15025 : /*38045*/ OPC_MoveChild, 9,
15026 : /*38047*/ OPC_RecordNode, // #8 = $slc
15027 : /*38048*/ OPC_MoveParent,
15028 : /*38049*/ OPC_MoveChild, 10,
15029 : /*38051*/ OPC_RecordNode, // #9 = $tfe
15030 : /*38052*/ OPC_MoveParent,
15031 : /*38053*/ OPC_MoveChild, 11,
15032 : /*38055*/ OPC_RecordNode, // #10 = $lwe
15033 : /*38056*/ OPC_MoveParent,
15034 : /*38057*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15035 : /*38059*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15036 : /*38062*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15037 : /*38065*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15038 : /*38068*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15039 : /*38071*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15040 : /*38074*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15041 : /*38077*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15042 : /*38080*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15043 : /*38083*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8), 0,
15044 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15045 : // Src: (intrinsic_wo_chain:v4f32 4846:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15046 : // Dst: (IMAGE_SAMPLE_C_CD_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15047 : /*38101*/ /*Scope*/ 68, /*->38170*/
15048 : /*38102*/ OPC_CheckChild1Type, MVT::v16i32,
15049 : /*38104*/ OPC_RecordChild2, // #1 = $rsrc
15050 : /*38105*/ OPC_RecordChild3, // #2 = $sampler
15051 : /*38106*/ OPC_RecordChild4, // #3 = $dmask
15052 : /*38107*/ OPC_RecordChild5, // #4 = $unorm
15053 : /*38108*/ OPC_RecordChild6, // #5 = $r128
15054 : /*38109*/ OPC_RecordChild7, // #6 = $da
15055 : /*38110*/ OPC_MoveChild, 8,
15056 : /*38112*/ OPC_RecordNode, // #7 = $glc
15057 : /*38113*/ OPC_MoveParent,
15058 : /*38114*/ OPC_MoveChild, 9,
15059 : /*38116*/ OPC_RecordNode, // #8 = $slc
15060 : /*38117*/ OPC_MoveParent,
15061 : /*38118*/ OPC_MoveChild, 10,
15062 : /*38120*/ OPC_RecordNode, // #9 = $tfe
15063 : /*38121*/ OPC_MoveParent,
15064 : /*38122*/ OPC_MoveChild, 11,
15065 : /*38124*/ OPC_RecordNode, // #10 = $lwe
15066 : /*38125*/ OPC_MoveParent,
15067 : /*38126*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15068 : /*38128*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15069 : /*38131*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15070 : /*38134*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15071 : /*38137*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15072 : /*38140*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15073 : /*38143*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15074 : /*38146*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15075 : /*38149*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15076 : /*38152*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V16), 0,
15077 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15078 : // Src: (intrinsic_wo_chain:v4f32 4846:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15079 : // Dst: (IMAGE_SAMPLE_C_CD_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15080 : /*38170*/ 0, /*End of Scope*/
15081 : /*38171*/ /*Scope*/ 95|128,2/*351*/, /*->38524*/
15082 : /*38173*/ OPC_CheckChild0Integer, 109|128,37/*4845*/,
15083 : /*38176*/ OPC_RecordChild1, // #0 = $addr
15084 : /*38177*/ OPC_Scope, 68, /*->38247*/ // 5 children in Scope
15085 : /*38179*/ OPC_CheckChild1Type, MVT::i32,
15086 : /*38181*/ OPC_RecordChild2, // #1 = $rsrc
15087 : /*38182*/ OPC_RecordChild3, // #2 = $sampler
15088 : /*38183*/ OPC_RecordChild4, // #3 = $dmask
15089 : /*38184*/ OPC_RecordChild5, // #4 = $unorm
15090 : /*38185*/ OPC_RecordChild6, // #5 = $r128
15091 : /*38186*/ OPC_RecordChild7, // #6 = $da
15092 : /*38187*/ OPC_MoveChild, 8,
15093 : /*38189*/ OPC_RecordNode, // #7 = $glc
15094 : /*38190*/ OPC_MoveParent,
15095 : /*38191*/ OPC_MoveChild, 9,
15096 : /*38193*/ OPC_RecordNode, // #8 = $slc
15097 : /*38194*/ OPC_MoveParent,
15098 : /*38195*/ OPC_MoveChild, 10,
15099 : /*38197*/ OPC_RecordNode, // #9 = $tfe
15100 : /*38198*/ OPC_MoveParent,
15101 : /*38199*/ OPC_MoveChild, 11,
15102 : /*38201*/ OPC_RecordNode, // #10 = $lwe
15103 : /*38202*/ OPC_MoveParent,
15104 : /*38203*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15105 : /*38205*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15106 : /*38208*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15107 : /*38211*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15108 : /*38214*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15109 : /*38217*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15110 : /*38220*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15111 : /*38223*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15112 : /*38226*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15113 : /*38229*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V1), 0,
15114 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15115 : // Src: (intrinsic_wo_chain:v4f32 4845:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15116 : // Dst: (IMAGE_SAMPLE_C_CD_CL_O_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15117 : /*38247*/ /*Scope*/ 68, /*->38316*/
15118 : /*38248*/ OPC_CheckChild1Type, MVT::v2i32,
15119 : /*38250*/ OPC_RecordChild2, // #1 = $rsrc
15120 : /*38251*/ OPC_RecordChild3, // #2 = $sampler
15121 : /*38252*/ OPC_RecordChild4, // #3 = $dmask
15122 : /*38253*/ OPC_RecordChild5, // #4 = $unorm
15123 : /*38254*/ OPC_RecordChild6, // #5 = $r128
15124 : /*38255*/ OPC_RecordChild7, // #6 = $da
15125 : /*38256*/ OPC_MoveChild, 8,
15126 : /*38258*/ OPC_RecordNode, // #7 = $glc
15127 : /*38259*/ OPC_MoveParent,
15128 : /*38260*/ OPC_MoveChild, 9,
15129 : /*38262*/ OPC_RecordNode, // #8 = $slc
15130 : /*38263*/ OPC_MoveParent,
15131 : /*38264*/ OPC_MoveChild, 10,
15132 : /*38266*/ OPC_RecordNode, // #9 = $tfe
15133 : /*38267*/ OPC_MoveParent,
15134 : /*38268*/ OPC_MoveChild, 11,
15135 : /*38270*/ OPC_RecordNode, // #10 = $lwe
15136 : /*38271*/ OPC_MoveParent,
15137 : /*38272*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15138 : /*38274*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15139 : /*38277*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15140 : /*38280*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15141 : /*38283*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15142 : /*38286*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15143 : /*38289*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15144 : /*38292*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15145 : /*38295*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15146 : /*38298*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V2), 0,
15147 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15148 : // Src: (intrinsic_wo_chain:v4f32 4845:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15149 : // Dst: (IMAGE_SAMPLE_C_CD_CL_O_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15150 : /*38316*/ /*Scope*/ 68, /*->38385*/
15151 : /*38317*/ OPC_CheckChild1Type, MVT::v4i32,
15152 : /*38319*/ OPC_RecordChild2, // #1 = $rsrc
15153 : /*38320*/ OPC_RecordChild3, // #2 = $sampler
15154 : /*38321*/ OPC_RecordChild4, // #3 = $dmask
15155 : /*38322*/ OPC_RecordChild5, // #4 = $unorm
15156 : /*38323*/ OPC_RecordChild6, // #5 = $r128
15157 : /*38324*/ OPC_RecordChild7, // #6 = $da
15158 : /*38325*/ OPC_MoveChild, 8,
15159 : /*38327*/ OPC_RecordNode, // #7 = $glc
15160 : /*38328*/ OPC_MoveParent,
15161 : /*38329*/ OPC_MoveChild, 9,
15162 : /*38331*/ OPC_RecordNode, // #8 = $slc
15163 : /*38332*/ OPC_MoveParent,
15164 : /*38333*/ OPC_MoveChild, 10,
15165 : /*38335*/ OPC_RecordNode, // #9 = $tfe
15166 : /*38336*/ OPC_MoveParent,
15167 : /*38337*/ OPC_MoveChild, 11,
15168 : /*38339*/ OPC_RecordNode, // #10 = $lwe
15169 : /*38340*/ OPC_MoveParent,
15170 : /*38341*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15171 : /*38343*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15172 : /*38346*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15173 : /*38349*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15174 : /*38352*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15175 : /*38355*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15176 : /*38358*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15177 : /*38361*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15178 : /*38364*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15179 : /*38367*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4), 0,
15180 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15181 : // Src: (intrinsic_wo_chain:v4f32 4845:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15182 : // Dst: (IMAGE_SAMPLE_C_CD_CL_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15183 : /*38385*/ /*Scope*/ 68, /*->38454*/
15184 : /*38386*/ OPC_CheckChild1Type, MVT::v8i32,
15185 : /*38388*/ OPC_RecordChild2, // #1 = $rsrc
15186 : /*38389*/ OPC_RecordChild3, // #2 = $sampler
15187 : /*38390*/ OPC_RecordChild4, // #3 = $dmask
15188 : /*38391*/ OPC_RecordChild5, // #4 = $unorm
15189 : /*38392*/ OPC_RecordChild6, // #5 = $r128
15190 : /*38393*/ OPC_RecordChild7, // #6 = $da
15191 : /*38394*/ OPC_MoveChild, 8,
15192 : /*38396*/ OPC_RecordNode, // #7 = $glc
15193 : /*38397*/ OPC_MoveParent,
15194 : /*38398*/ OPC_MoveChild, 9,
15195 : /*38400*/ OPC_RecordNode, // #8 = $slc
15196 : /*38401*/ OPC_MoveParent,
15197 : /*38402*/ OPC_MoveChild, 10,
15198 : /*38404*/ OPC_RecordNode, // #9 = $tfe
15199 : /*38405*/ OPC_MoveParent,
15200 : /*38406*/ OPC_MoveChild, 11,
15201 : /*38408*/ OPC_RecordNode, // #10 = $lwe
15202 : /*38409*/ OPC_MoveParent,
15203 : /*38410*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15204 : /*38412*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15205 : /*38415*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15206 : /*38418*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15207 : /*38421*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15208 : /*38424*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15209 : /*38427*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15210 : /*38430*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15211 : /*38433*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15212 : /*38436*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8), 0,
15213 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15214 : // Src: (intrinsic_wo_chain:v4f32 4845:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15215 : // Dst: (IMAGE_SAMPLE_C_CD_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15216 : /*38454*/ /*Scope*/ 68, /*->38523*/
15217 : /*38455*/ OPC_CheckChild1Type, MVT::v16i32,
15218 : /*38457*/ OPC_RecordChild2, // #1 = $rsrc
15219 : /*38458*/ OPC_RecordChild3, // #2 = $sampler
15220 : /*38459*/ OPC_RecordChild4, // #3 = $dmask
15221 : /*38460*/ OPC_RecordChild5, // #4 = $unorm
15222 : /*38461*/ OPC_RecordChild6, // #5 = $r128
15223 : /*38462*/ OPC_RecordChild7, // #6 = $da
15224 : /*38463*/ OPC_MoveChild, 8,
15225 : /*38465*/ OPC_RecordNode, // #7 = $glc
15226 : /*38466*/ OPC_MoveParent,
15227 : /*38467*/ OPC_MoveChild, 9,
15228 : /*38469*/ OPC_RecordNode, // #8 = $slc
15229 : /*38470*/ OPC_MoveParent,
15230 : /*38471*/ OPC_MoveChild, 10,
15231 : /*38473*/ OPC_RecordNode, // #9 = $tfe
15232 : /*38474*/ OPC_MoveParent,
15233 : /*38475*/ OPC_MoveChild, 11,
15234 : /*38477*/ OPC_RecordNode, // #10 = $lwe
15235 : /*38478*/ OPC_MoveParent,
15236 : /*38479*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15237 : /*38481*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15238 : /*38484*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15239 : /*38487*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15240 : /*38490*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15241 : /*38493*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15242 : /*38496*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15243 : /*38499*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15244 : /*38502*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15245 : /*38505*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V16), 0,
15246 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15247 : // Src: (intrinsic_wo_chain:v4f32 4845:iPTR, v16i32:v16i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15248 : // Dst: (IMAGE_SAMPLE_C_CD_CL_O_V4_V16:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v16i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15249 : /*38523*/ 0, /*End of Scope*/
15250 : /*38524*/ /*Scope*/ 16|128,1/*144*/, /*->38670*/
15251 : /*38526*/ OPC_CheckChild0Integer, 67|128,37/*4803*/,
15252 : /*38529*/ OPC_RecordChild1, // #0 = $addr
15253 : /*38530*/ OPC_Scope, 68, /*->38600*/ // 2 children in Scope
15254 : /*38532*/ OPC_CheckChild1Type, MVT::v2i32,
15255 : /*38534*/ OPC_RecordChild2, // #1 = $rsrc
15256 : /*38535*/ OPC_RecordChild3, // #2 = $sampler
15257 : /*38536*/ OPC_RecordChild4, // #3 = $dmask
15258 : /*38537*/ OPC_RecordChild5, // #4 = $unorm
15259 : /*38538*/ OPC_RecordChild6, // #5 = $r128
15260 : /*38539*/ OPC_RecordChild7, // #6 = $da
15261 : /*38540*/ OPC_MoveChild, 8,
15262 : /*38542*/ OPC_RecordNode, // #7 = $glc
15263 : /*38543*/ OPC_MoveParent,
15264 : /*38544*/ OPC_MoveChild, 9,
15265 : /*38546*/ OPC_RecordNode, // #8 = $slc
15266 : /*38547*/ OPC_MoveParent,
15267 : /*38548*/ OPC_MoveChild, 10,
15268 : /*38550*/ OPC_RecordNode, // #9 = $tfe
15269 : /*38551*/ OPC_MoveParent,
15270 : /*38552*/ OPC_MoveChild, 11,
15271 : /*38554*/ OPC_RecordNode, // #10 = $lwe
15272 : /*38555*/ OPC_MoveParent,
15273 : /*38556*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15274 : /*38558*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15275 : /*38561*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15276 : /*38564*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15277 : /*38567*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15278 : /*38570*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15279 : /*38573*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15280 : /*38576*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15281 : /*38579*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15282 : /*38582*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V4_V2), 0,
15283 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15284 : // Src: (intrinsic_wo_chain:v4f32 4803:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15285 : // Dst: (IMAGE_GATHER4_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15286 : /*38600*/ /*Scope*/ 68, /*->38669*/
15287 : /*38601*/ OPC_CheckChild1Type, MVT::v4i32,
15288 : /*38603*/ OPC_RecordChild2, // #1 = $rsrc
15289 : /*38604*/ OPC_RecordChild3, // #2 = $sampler
15290 : /*38605*/ OPC_RecordChild4, // #3 = $dmask
15291 : /*38606*/ OPC_RecordChild5, // #4 = $unorm
15292 : /*38607*/ OPC_RecordChild6, // #5 = $r128
15293 : /*38608*/ OPC_RecordChild7, // #6 = $da
15294 : /*38609*/ OPC_MoveChild, 8,
15295 : /*38611*/ OPC_RecordNode, // #7 = $glc
15296 : /*38612*/ OPC_MoveParent,
15297 : /*38613*/ OPC_MoveChild, 9,
15298 : /*38615*/ OPC_RecordNode, // #8 = $slc
15299 : /*38616*/ OPC_MoveParent,
15300 : /*38617*/ OPC_MoveChild, 10,
15301 : /*38619*/ OPC_RecordNode, // #9 = $tfe
15302 : /*38620*/ OPC_MoveParent,
15303 : /*38621*/ OPC_MoveChild, 11,
15304 : /*38623*/ OPC_RecordNode, // #10 = $lwe
15305 : /*38624*/ OPC_MoveParent,
15306 : /*38625*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15307 : /*38627*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15308 : /*38630*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15309 : /*38633*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15310 : /*38636*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15311 : /*38639*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15312 : /*38642*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15313 : /*38645*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15314 : /*38648*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15315 : /*38651*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_V4_V4), 0,
15316 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15317 : // Src: (intrinsic_wo_chain:v4f32 4803:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15318 : // Dst: (IMAGE_GATHER4_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15319 : /*38669*/ 0, /*End of Scope*/
15320 : /*38670*/ /*Scope*/ 72, /*->38743*/
15321 : /*38671*/ OPC_CheckChild0Integer, 84|128,37/*4820*/,
15322 : /*38674*/ OPC_RecordChild1, // #0 = $addr
15323 : /*38675*/ OPC_CheckChild1Type, MVT::v4i32,
15324 : /*38677*/ OPC_RecordChild2, // #1 = $rsrc
15325 : /*38678*/ OPC_RecordChild3, // #2 = $sampler
15326 : /*38679*/ OPC_RecordChild4, // #3 = $dmask
15327 : /*38680*/ OPC_RecordChild5, // #4 = $unorm
15328 : /*38681*/ OPC_RecordChild6, // #5 = $r128
15329 : /*38682*/ OPC_RecordChild7, // #6 = $da
15330 : /*38683*/ OPC_MoveChild, 8,
15331 : /*38685*/ OPC_RecordNode, // #7 = $glc
15332 : /*38686*/ OPC_MoveParent,
15333 : /*38687*/ OPC_MoveChild, 9,
15334 : /*38689*/ OPC_RecordNode, // #8 = $slc
15335 : /*38690*/ OPC_MoveParent,
15336 : /*38691*/ OPC_MoveChild, 10,
15337 : /*38693*/ OPC_RecordNode, // #9 = $tfe
15338 : /*38694*/ OPC_MoveParent,
15339 : /*38695*/ OPC_MoveChild, 11,
15340 : /*38697*/ OPC_RecordNode, // #10 = $lwe
15341 : /*38698*/ OPC_MoveParent,
15342 : /*38699*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15343 : /*38701*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15344 : /*38704*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15345 : /*38707*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15346 : /*38710*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15347 : /*38713*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15348 : /*38716*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15349 : /*38719*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15350 : /*38722*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15351 : /*38725*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_V4_V4), 0,
15352 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15353 : // Src: (intrinsic_wo_chain:v4f32 4820:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15354 : // Dst: (IMAGE_GATHER4_CL_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15355 : /*38743*/ /*Scope*/ 72, /*->38816*/
15356 : /*38744*/ OPC_CheckChild0Integer, 86|128,37/*4822*/,
15357 : /*38747*/ OPC_RecordChild1, // #0 = $addr
15358 : /*38748*/ OPC_CheckChild1Type, MVT::v4i32,
15359 : /*38750*/ OPC_RecordChild2, // #1 = $rsrc
15360 : /*38751*/ OPC_RecordChild3, // #2 = $sampler
15361 : /*38752*/ OPC_RecordChild4, // #3 = $dmask
15362 : /*38753*/ OPC_RecordChild5, // #4 = $unorm
15363 : /*38754*/ OPC_RecordChild6, // #5 = $r128
15364 : /*38755*/ OPC_RecordChild7, // #6 = $da
15365 : /*38756*/ OPC_MoveChild, 8,
15366 : /*38758*/ OPC_RecordNode, // #7 = $glc
15367 : /*38759*/ OPC_MoveParent,
15368 : /*38760*/ OPC_MoveChild, 9,
15369 : /*38762*/ OPC_RecordNode, // #8 = $slc
15370 : /*38763*/ OPC_MoveParent,
15371 : /*38764*/ OPC_MoveChild, 10,
15372 : /*38766*/ OPC_RecordNode, // #9 = $tfe
15373 : /*38767*/ OPC_MoveParent,
15374 : /*38768*/ OPC_MoveChild, 11,
15375 : /*38770*/ OPC_RecordNode, // #10 = $lwe
15376 : /*38771*/ OPC_MoveParent,
15377 : /*38772*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15378 : /*38774*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15379 : /*38777*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15380 : /*38780*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15381 : /*38783*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15382 : /*38786*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15383 : /*38789*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15384 : /*38792*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15385 : /*38795*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15386 : /*38798*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_V4_V4), 0,
15387 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15388 : // Src: (intrinsic_wo_chain:v4f32 4822:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15389 : // Dst: (IMAGE_GATHER4_L_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15390 : /*38816*/ /*Scope*/ 72, /*->38889*/
15391 : /*38817*/ OPC_CheckChild0Integer, 68|128,37/*4804*/,
15392 : /*38820*/ OPC_RecordChild1, // #0 = $addr
15393 : /*38821*/ OPC_CheckChild1Type, MVT::v4i32,
15394 : /*38823*/ OPC_RecordChild2, // #1 = $rsrc
15395 : /*38824*/ OPC_RecordChild3, // #2 = $sampler
15396 : /*38825*/ OPC_RecordChild4, // #3 = $dmask
15397 : /*38826*/ OPC_RecordChild5, // #4 = $unorm
15398 : /*38827*/ OPC_RecordChild6, // #5 = $r128
15399 : /*38828*/ OPC_RecordChild7, // #6 = $da
15400 : /*38829*/ OPC_MoveChild, 8,
15401 : /*38831*/ OPC_RecordNode, // #7 = $glc
15402 : /*38832*/ OPC_MoveParent,
15403 : /*38833*/ OPC_MoveChild, 9,
15404 : /*38835*/ OPC_RecordNode, // #8 = $slc
15405 : /*38836*/ OPC_MoveParent,
15406 : /*38837*/ OPC_MoveChild, 10,
15407 : /*38839*/ OPC_RecordNode, // #9 = $tfe
15408 : /*38840*/ OPC_MoveParent,
15409 : /*38841*/ OPC_MoveChild, 11,
15410 : /*38843*/ OPC_RecordNode, // #10 = $lwe
15411 : /*38844*/ OPC_MoveParent,
15412 : /*38845*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15413 : /*38847*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15414 : /*38850*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15415 : /*38853*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15416 : /*38856*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15417 : /*38859*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15418 : /*38862*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15419 : /*38865*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15420 : /*38868*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15421 : /*38871*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_V4_V4), 0,
15422 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15423 : // Src: (intrinsic_wo_chain:v4f32 4804:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15424 : // Dst: (IMAGE_GATHER4_B_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15425 : /*38889*/ /*Scope*/ 16|128,1/*144*/, /*->39035*/
15426 : /*38891*/ OPC_CheckChild0Integer, 69|128,37/*4805*/,
15427 : /*38894*/ OPC_RecordChild1, // #0 = $addr
15428 : /*38895*/ OPC_Scope, 68, /*->38965*/ // 2 children in Scope
15429 : /*38897*/ OPC_CheckChild1Type, MVT::v4i32,
15430 : /*38899*/ OPC_RecordChild2, // #1 = $rsrc
15431 : /*38900*/ OPC_RecordChild3, // #2 = $sampler
15432 : /*38901*/ OPC_RecordChild4, // #3 = $dmask
15433 : /*38902*/ OPC_RecordChild5, // #4 = $unorm
15434 : /*38903*/ OPC_RecordChild6, // #5 = $r128
15435 : /*38904*/ OPC_RecordChild7, // #6 = $da
15436 : /*38905*/ OPC_MoveChild, 8,
15437 : /*38907*/ OPC_RecordNode, // #7 = $glc
15438 : /*38908*/ OPC_MoveParent,
15439 : /*38909*/ OPC_MoveChild, 9,
15440 : /*38911*/ OPC_RecordNode, // #8 = $slc
15441 : /*38912*/ OPC_MoveParent,
15442 : /*38913*/ OPC_MoveChild, 10,
15443 : /*38915*/ OPC_RecordNode, // #9 = $tfe
15444 : /*38916*/ OPC_MoveParent,
15445 : /*38917*/ OPC_MoveChild, 11,
15446 : /*38919*/ OPC_RecordNode, // #10 = $lwe
15447 : /*38920*/ OPC_MoveParent,
15448 : /*38921*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15449 : /*38923*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15450 : /*38926*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15451 : /*38929*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15452 : /*38932*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15453 : /*38935*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15454 : /*38938*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15455 : /*38941*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15456 : /*38944*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15457 : /*38947*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V4_V4), 0,
15458 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15459 : // Src: (intrinsic_wo_chain:v4f32 4805:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15460 : // Dst: (IMAGE_GATHER4_B_CL_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15461 : /*38965*/ /*Scope*/ 68, /*->39034*/
15462 : /*38966*/ OPC_CheckChild1Type, MVT::v8i32,
15463 : /*38968*/ OPC_RecordChild2, // #1 = $rsrc
15464 : /*38969*/ OPC_RecordChild3, // #2 = $sampler
15465 : /*38970*/ OPC_RecordChild4, // #3 = $dmask
15466 : /*38971*/ OPC_RecordChild5, // #4 = $unorm
15467 : /*38972*/ OPC_RecordChild6, // #5 = $r128
15468 : /*38973*/ OPC_RecordChild7, // #6 = $da
15469 : /*38974*/ OPC_MoveChild, 8,
15470 : /*38976*/ OPC_RecordNode, // #7 = $glc
15471 : /*38977*/ OPC_MoveParent,
15472 : /*38978*/ OPC_MoveChild, 9,
15473 : /*38980*/ OPC_RecordNode, // #8 = $slc
15474 : /*38981*/ OPC_MoveParent,
15475 : /*38982*/ OPC_MoveChild, 10,
15476 : /*38984*/ OPC_RecordNode, // #9 = $tfe
15477 : /*38985*/ OPC_MoveParent,
15478 : /*38986*/ OPC_MoveChild, 11,
15479 : /*38988*/ OPC_RecordNode, // #10 = $lwe
15480 : /*38989*/ OPC_MoveParent,
15481 : /*38990*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15482 : /*38992*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15483 : /*38995*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15484 : /*38998*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15485 : /*39001*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15486 : /*39004*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15487 : /*39007*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15488 : /*39010*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15489 : /*39013*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15490 : /*39016*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_V4_V8), 0,
15491 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15492 : // Src: (intrinsic_wo_chain:v4f32 4805:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15493 : // Dst: (IMAGE_GATHER4_B_CL_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15494 : /*39034*/ 0, /*End of Scope*/
15495 : /*39035*/ /*Scope*/ 16|128,1/*144*/, /*->39181*/
15496 : /*39037*/ OPC_CheckChild0Integer, 88|128,37/*4824*/,
15497 : /*39040*/ OPC_RecordChild1, // #0 = $addr
15498 : /*39041*/ OPC_Scope, 68, /*->39111*/ // 2 children in Scope
15499 : /*39043*/ OPC_CheckChild1Type, MVT::v2i32,
15500 : /*39045*/ OPC_RecordChild2, // #1 = $rsrc
15501 : /*39046*/ OPC_RecordChild3, // #2 = $sampler
15502 : /*39047*/ OPC_RecordChild4, // #3 = $dmask
15503 : /*39048*/ OPC_RecordChild5, // #4 = $unorm
15504 : /*39049*/ OPC_RecordChild6, // #5 = $r128
15505 : /*39050*/ OPC_RecordChild7, // #6 = $da
15506 : /*39051*/ OPC_MoveChild, 8,
15507 : /*39053*/ OPC_RecordNode, // #7 = $glc
15508 : /*39054*/ OPC_MoveParent,
15509 : /*39055*/ OPC_MoveChild, 9,
15510 : /*39057*/ OPC_RecordNode, // #8 = $slc
15511 : /*39058*/ OPC_MoveParent,
15512 : /*39059*/ OPC_MoveChild, 10,
15513 : /*39061*/ OPC_RecordNode, // #9 = $tfe
15514 : /*39062*/ OPC_MoveParent,
15515 : /*39063*/ OPC_MoveChild, 11,
15516 : /*39065*/ OPC_RecordNode, // #10 = $lwe
15517 : /*39066*/ OPC_MoveParent,
15518 : /*39067*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15519 : /*39069*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15520 : /*39072*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15521 : /*39075*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15522 : /*39078*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15523 : /*39081*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15524 : /*39084*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15525 : /*39087*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15526 : /*39090*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15527 : /*39093*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V4_V2), 0,
15528 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15529 : // Src: (intrinsic_wo_chain:v4f32 4824:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15530 : // Dst: (IMAGE_GATHER4_LZ_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15531 : /*39111*/ /*Scope*/ 68, /*->39180*/
15532 : /*39112*/ OPC_CheckChild1Type, MVT::v4i32,
15533 : /*39114*/ OPC_RecordChild2, // #1 = $rsrc
15534 : /*39115*/ OPC_RecordChild3, // #2 = $sampler
15535 : /*39116*/ OPC_RecordChild4, // #3 = $dmask
15536 : /*39117*/ OPC_RecordChild5, // #4 = $unorm
15537 : /*39118*/ OPC_RecordChild6, // #5 = $r128
15538 : /*39119*/ OPC_RecordChild7, // #6 = $da
15539 : /*39120*/ OPC_MoveChild, 8,
15540 : /*39122*/ OPC_RecordNode, // #7 = $glc
15541 : /*39123*/ OPC_MoveParent,
15542 : /*39124*/ OPC_MoveChild, 9,
15543 : /*39126*/ OPC_RecordNode, // #8 = $slc
15544 : /*39127*/ OPC_MoveParent,
15545 : /*39128*/ OPC_MoveChild, 10,
15546 : /*39130*/ OPC_RecordNode, // #9 = $tfe
15547 : /*39131*/ OPC_MoveParent,
15548 : /*39132*/ OPC_MoveChild, 11,
15549 : /*39134*/ OPC_RecordNode, // #10 = $lwe
15550 : /*39135*/ OPC_MoveParent,
15551 : /*39136*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15552 : /*39138*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15553 : /*39141*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15554 : /*39144*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15555 : /*39147*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15556 : /*39150*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15557 : /*39153*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15558 : /*39156*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15559 : /*39159*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15560 : /*39162*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_V4_V4), 0,
15561 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15562 : // Src: (intrinsic_wo_chain:v4f32 4824:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15563 : // Dst: (IMAGE_GATHER4_LZ_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15564 : /*39180*/ 0, /*End of Scope*/
15565 : /*39181*/ /*Scope*/ 72, /*->39254*/
15566 : /*39182*/ OPC_CheckChild0Integer, 72|128,37/*4808*/,
15567 : /*39185*/ OPC_RecordChild1, // #0 = $addr
15568 : /*39186*/ OPC_CheckChild1Type, MVT::v4i32,
15569 : /*39188*/ OPC_RecordChild2, // #1 = $rsrc
15570 : /*39189*/ OPC_RecordChild3, // #2 = $sampler
15571 : /*39190*/ OPC_RecordChild4, // #3 = $dmask
15572 : /*39191*/ OPC_RecordChild5, // #4 = $unorm
15573 : /*39192*/ OPC_RecordChild6, // #5 = $r128
15574 : /*39193*/ OPC_RecordChild7, // #6 = $da
15575 : /*39194*/ OPC_MoveChild, 8,
15576 : /*39196*/ OPC_RecordNode, // #7 = $glc
15577 : /*39197*/ OPC_MoveParent,
15578 : /*39198*/ OPC_MoveChild, 9,
15579 : /*39200*/ OPC_RecordNode, // #8 = $slc
15580 : /*39201*/ OPC_MoveParent,
15581 : /*39202*/ OPC_MoveChild, 10,
15582 : /*39204*/ OPC_RecordNode, // #9 = $tfe
15583 : /*39205*/ OPC_MoveParent,
15584 : /*39206*/ OPC_MoveChild, 11,
15585 : /*39208*/ OPC_RecordNode, // #10 = $lwe
15586 : /*39209*/ OPC_MoveParent,
15587 : /*39210*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15588 : /*39212*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15589 : /*39215*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15590 : /*39218*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15591 : /*39221*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15592 : /*39224*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15593 : /*39227*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15594 : /*39230*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15595 : /*39233*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15596 : /*39236*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_V4_V4), 0,
15597 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15598 : // Src: (intrinsic_wo_chain:v4f32 4808:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15599 : // Dst: (IMAGE_GATHER4_C_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15600 : /*39254*/ /*Scope*/ 16|128,1/*144*/, /*->39400*/
15601 : /*39256*/ OPC_CheckChild0Integer, 77|128,37/*4813*/,
15602 : /*39259*/ OPC_RecordChild1, // #0 = $addr
15603 : /*39260*/ OPC_Scope, 68, /*->39330*/ // 2 children in Scope
15604 : /*39262*/ OPC_CheckChild1Type, MVT::v4i32,
15605 : /*39264*/ OPC_RecordChild2, // #1 = $rsrc
15606 : /*39265*/ OPC_RecordChild3, // #2 = $sampler
15607 : /*39266*/ OPC_RecordChild4, // #3 = $dmask
15608 : /*39267*/ OPC_RecordChild5, // #4 = $unorm
15609 : /*39268*/ OPC_RecordChild6, // #5 = $r128
15610 : /*39269*/ OPC_RecordChild7, // #6 = $da
15611 : /*39270*/ OPC_MoveChild, 8,
15612 : /*39272*/ OPC_RecordNode, // #7 = $glc
15613 : /*39273*/ OPC_MoveParent,
15614 : /*39274*/ OPC_MoveChild, 9,
15615 : /*39276*/ OPC_RecordNode, // #8 = $slc
15616 : /*39277*/ OPC_MoveParent,
15617 : /*39278*/ OPC_MoveChild, 10,
15618 : /*39280*/ OPC_RecordNode, // #9 = $tfe
15619 : /*39281*/ OPC_MoveParent,
15620 : /*39282*/ OPC_MoveChild, 11,
15621 : /*39284*/ OPC_RecordNode, // #10 = $lwe
15622 : /*39285*/ OPC_MoveParent,
15623 : /*39286*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15624 : /*39288*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15625 : /*39291*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15626 : /*39294*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15627 : /*39297*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15628 : /*39300*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15629 : /*39303*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15630 : /*39306*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15631 : /*39309*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15632 : /*39312*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V4_V4), 0,
15633 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15634 : // Src: (intrinsic_wo_chain:v4f32 4813:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15635 : // Dst: (IMAGE_GATHER4_C_CL_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15636 : /*39330*/ /*Scope*/ 68, /*->39399*/
15637 : /*39331*/ OPC_CheckChild1Type, MVT::v8i32,
15638 : /*39333*/ OPC_RecordChild2, // #1 = $rsrc
15639 : /*39334*/ OPC_RecordChild3, // #2 = $sampler
15640 : /*39335*/ OPC_RecordChild4, // #3 = $dmask
15641 : /*39336*/ OPC_RecordChild5, // #4 = $unorm
15642 : /*39337*/ OPC_RecordChild6, // #5 = $r128
15643 : /*39338*/ OPC_RecordChild7, // #6 = $da
15644 : /*39339*/ OPC_MoveChild, 8,
15645 : /*39341*/ OPC_RecordNode, // #7 = $glc
15646 : /*39342*/ OPC_MoveParent,
15647 : /*39343*/ OPC_MoveChild, 9,
15648 : /*39345*/ OPC_RecordNode, // #8 = $slc
15649 : /*39346*/ OPC_MoveParent,
15650 : /*39347*/ OPC_MoveChild, 10,
15651 : /*39349*/ OPC_RecordNode, // #9 = $tfe
15652 : /*39350*/ OPC_MoveParent,
15653 : /*39351*/ OPC_MoveChild, 11,
15654 : /*39353*/ OPC_RecordNode, // #10 = $lwe
15655 : /*39354*/ OPC_MoveParent,
15656 : /*39355*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15657 : /*39357*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15658 : /*39360*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15659 : /*39363*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15660 : /*39366*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15661 : /*39369*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15662 : /*39372*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15663 : /*39375*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15664 : /*39378*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15665 : /*39381*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_V4_V8), 0,
15666 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15667 : // Src: (intrinsic_wo_chain:v4f32 4813:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15668 : // Dst: (IMAGE_GATHER4_C_CL_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15669 : /*39399*/ 0, /*End of Scope*/
15670 : /*39400*/ /*Scope*/ 16|128,1/*144*/, /*->39546*/
15671 : /*39402*/ OPC_CheckChild0Integer, 79|128,37/*4815*/,
15672 : /*39405*/ OPC_RecordChild1, // #0 = $addr
15673 : /*39406*/ OPC_Scope, 68, /*->39476*/ // 2 children in Scope
15674 : /*39408*/ OPC_CheckChild1Type, MVT::v4i32,
15675 : /*39410*/ OPC_RecordChild2, // #1 = $rsrc
15676 : /*39411*/ OPC_RecordChild3, // #2 = $sampler
15677 : /*39412*/ OPC_RecordChild4, // #3 = $dmask
15678 : /*39413*/ OPC_RecordChild5, // #4 = $unorm
15679 : /*39414*/ OPC_RecordChild6, // #5 = $r128
15680 : /*39415*/ OPC_RecordChild7, // #6 = $da
15681 : /*39416*/ OPC_MoveChild, 8,
15682 : /*39418*/ OPC_RecordNode, // #7 = $glc
15683 : /*39419*/ OPC_MoveParent,
15684 : /*39420*/ OPC_MoveChild, 9,
15685 : /*39422*/ OPC_RecordNode, // #8 = $slc
15686 : /*39423*/ OPC_MoveParent,
15687 : /*39424*/ OPC_MoveChild, 10,
15688 : /*39426*/ OPC_RecordNode, // #9 = $tfe
15689 : /*39427*/ OPC_MoveParent,
15690 : /*39428*/ OPC_MoveChild, 11,
15691 : /*39430*/ OPC_RecordNode, // #10 = $lwe
15692 : /*39431*/ OPC_MoveParent,
15693 : /*39432*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15694 : /*39434*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15695 : /*39437*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15696 : /*39440*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15697 : /*39443*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15698 : /*39446*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15699 : /*39449*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15700 : /*39452*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15701 : /*39455*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15702 : /*39458*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V4_V4), 0,
15703 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15704 : // Src: (intrinsic_wo_chain:v4f32 4815:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15705 : // Dst: (IMAGE_GATHER4_C_L_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15706 : /*39476*/ /*Scope*/ 68, /*->39545*/
15707 : /*39477*/ OPC_CheckChild1Type, MVT::v8i32,
15708 : /*39479*/ OPC_RecordChild2, // #1 = $rsrc
15709 : /*39480*/ OPC_RecordChild3, // #2 = $sampler
15710 : /*39481*/ OPC_RecordChild4, // #3 = $dmask
15711 : /*39482*/ OPC_RecordChild5, // #4 = $unorm
15712 : /*39483*/ OPC_RecordChild6, // #5 = $r128
15713 : /*39484*/ OPC_RecordChild7, // #6 = $da
15714 : /*39485*/ OPC_MoveChild, 8,
15715 : /*39487*/ OPC_RecordNode, // #7 = $glc
15716 : /*39488*/ OPC_MoveParent,
15717 : /*39489*/ OPC_MoveChild, 9,
15718 : /*39491*/ OPC_RecordNode, // #8 = $slc
15719 : /*39492*/ OPC_MoveParent,
15720 : /*39493*/ OPC_MoveChild, 10,
15721 : /*39495*/ OPC_RecordNode, // #9 = $tfe
15722 : /*39496*/ OPC_MoveParent,
15723 : /*39497*/ OPC_MoveChild, 11,
15724 : /*39499*/ OPC_RecordNode, // #10 = $lwe
15725 : /*39500*/ OPC_MoveParent,
15726 : /*39501*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15727 : /*39503*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15728 : /*39506*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15729 : /*39509*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15730 : /*39512*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15731 : /*39515*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15732 : /*39518*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15733 : /*39521*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15734 : /*39524*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15735 : /*39527*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_V4_V8), 0,
15736 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15737 : // Src: (intrinsic_wo_chain:v4f32 4815:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15738 : // Dst: (IMAGE_GATHER4_C_L_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15739 : /*39545*/ 0, /*End of Scope*/
15740 : /*39546*/ /*Scope*/ 16|128,1/*144*/, /*->39692*/
15741 : /*39548*/ OPC_CheckChild0Integer, 73|128,37/*4809*/,
15742 : /*39551*/ OPC_RecordChild1, // #0 = $addr
15743 : /*39552*/ OPC_Scope, 68, /*->39622*/ // 2 children in Scope
15744 : /*39554*/ OPC_CheckChild1Type, MVT::v4i32,
15745 : /*39556*/ OPC_RecordChild2, // #1 = $rsrc
15746 : /*39557*/ OPC_RecordChild3, // #2 = $sampler
15747 : /*39558*/ OPC_RecordChild4, // #3 = $dmask
15748 : /*39559*/ OPC_RecordChild5, // #4 = $unorm
15749 : /*39560*/ OPC_RecordChild6, // #5 = $r128
15750 : /*39561*/ OPC_RecordChild7, // #6 = $da
15751 : /*39562*/ OPC_MoveChild, 8,
15752 : /*39564*/ OPC_RecordNode, // #7 = $glc
15753 : /*39565*/ OPC_MoveParent,
15754 : /*39566*/ OPC_MoveChild, 9,
15755 : /*39568*/ OPC_RecordNode, // #8 = $slc
15756 : /*39569*/ OPC_MoveParent,
15757 : /*39570*/ OPC_MoveChild, 10,
15758 : /*39572*/ OPC_RecordNode, // #9 = $tfe
15759 : /*39573*/ OPC_MoveParent,
15760 : /*39574*/ OPC_MoveChild, 11,
15761 : /*39576*/ OPC_RecordNode, // #10 = $lwe
15762 : /*39577*/ OPC_MoveParent,
15763 : /*39578*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15764 : /*39580*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15765 : /*39583*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15766 : /*39586*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15767 : /*39589*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15768 : /*39592*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15769 : /*39595*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15770 : /*39598*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15771 : /*39601*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15772 : /*39604*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V4_V4), 0,
15773 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15774 : // Src: (intrinsic_wo_chain:v4f32 4809:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15775 : // Dst: (IMAGE_GATHER4_C_B_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15776 : /*39622*/ /*Scope*/ 68, /*->39691*/
15777 : /*39623*/ OPC_CheckChild1Type, MVT::v8i32,
15778 : /*39625*/ OPC_RecordChild2, // #1 = $rsrc
15779 : /*39626*/ OPC_RecordChild3, // #2 = $sampler
15780 : /*39627*/ OPC_RecordChild4, // #3 = $dmask
15781 : /*39628*/ OPC_RecordChild5, // #4 = $unorm
15782 : /*39629*/ OPC_RecordChild6, // #5 = $r128
15783 : /*39630*/ OPC_RecordChild7, // #6 = $da
15784 : /*39631*/ OPC_MoveChild, 8,
15785 : /*39633*/ OPC_RecordNode, // #7 = $glc
15786 : /*39634*/ OPC_MoveParent,
15787 : /*39635*/ OPC_MoveChild, 9,
15788 : /*39637*/ OPC_RecordNode, // #8 = $slc
15789 : /*39638*/ OPC_MoveParent,
15790 : /*39639*/ OPC_MoveChild, 10,
15791 : /*39641*/ OPC_RecordNode, // #9 = $tfe
15792 : /*39642*/ OPC_MoveParent,
15793 : /*39643*/ OPC_MoveChild, 11,
15794 : /*39645*/ OPC_RecordNode, // #10 = $lwe
15795 : /*39646*/ OPC_MoveParent,
15796 : /*39647*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15797 : /*39649*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15798 : /*39652*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15799 : /*39655*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15800 : /*39658*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15801 : /*39661*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15802 : /*39664*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15803 : /*39667*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15804 : /*39670*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15805 : /*39673*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_V4_V8), 0,
15806 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15807 : // Src: (intrinsic_wo_chain:v4f32 4809:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15808 : // Dst: (IMAGE_GATHER4_C_B_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15809 : /*39691*/ 0, /*End of Scope*/
15810 : /*39692*/ /*Scope*/ 72, /*->39765*/
15811 : /*39693*/ OPC_CheckChild0Integer, 74|128,37/*4810*/,
15812 : /*39696*/ OPC_RecordChild1, // #0 = $addr
15813 : /*39697*/ OPC_CheckChild1Type, MVT::v8i32,
15814 : /*39699*/ OPC_RecordChild2, // #1 = $rsrc
15815 : /*39700*/ OPC_RecordChild3, // #2 = $sampler
15816 : /*39701*/ OPC_RecordChild4, // #3 = $dmask
15817 : /*39702*/ OPC_RecordChild5, // #4 = $unorm
15818 : /*39703*/ OPC_RecordChild6, // #5 = $r128
15819 : /*39704*/ OPC_RecordChild7, // #6 = $da
15820 : /*39705*/ OPC_MoveChild, 8,
15821 : /*39707*/ OPC_RecordNode, // #7 = $glc
15822 : /*39708*/ OPC_MoveParent,
15823 : /*39709*/ OPC_MoveChild, 9,
15824 : /*39711*/ OPC_RecordNode, // #8 = $slc
15825 : /*39712*/ OPC_MoveParent,
15826 : /*39713*/ OPC_MoveChild, 10,
15827 : /*39715*/ OPC_RecordNode, // #9 = $tfe
15828 : /*39716*/ OPC_MoveParent,
15829 : /*39717*/ OPC_MoveChild, 11,
15830 : /*39719*/ OPC_RecordNode, // #10 = $lwe
15831 : /*39720*/ OPC_MoveParent,
15832 : /*39721*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15833 : /*39723*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15834 : /*39726*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15835 : /*39729*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15836 : /*39732*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15837 : /*39735*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15838 : /*39738*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15839 : /*39741*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15840 : /*39744*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15841 : /*39747*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8), 0,
15842 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15843 : // Src: (intrinsic_wo_chain:v4f32 4810:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15844 : // Dst: (IMAGE_GATHER4_C_B_CL_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15845 : /*39765*/ /*Scope*/ 72, /*->39838*/
15846 : /*39766*/ OPC_CheckChild0Integer, 81|128,37/*4817*/,
15847 : /*39769*/ OPC_RecordChild1, // #0 = $addr
15848 : /*39770*/ OPC_CheckChild1Type, MVT::v4i32,
15849 : /*39772*/ OPC_RecordChild2, // #1 = $rsrc
15850 : /*39773*/ OPC_RecordChild3, // #2 = $sampler
15851 : /*39774*/ OPC_RecordChild4, // #3 = $dmask
15852 : /*39775*/ OPC_RecordChild5, // #4 = $unorm
15853 : /*39776*/ OPC_RecordChild6, // #5 = $r128
15854 : /*39777*/ OPC_RecordChild7, // #6 = $da
15855 : /*39778*/ OPC_MoveChild, 8,
15856 : /*39780*/ OPC_RecordNode, // #7 = $glc
15857 : /*39781*/ OPC_MoveParent,
15858 : /*39782*/ OPC_MoveChild, 9,
15859 : /*39784*/ OPC_RecordNode, // #8 = $slc
15860 : /*39785*/ OPC_MoveParent,
15861 : /*39786*/ OPC_MoveChild, 10,
15862 : /*39788*/ OPC_RecordNode, // #9 = $tfe
15863 : /*39789*/ OPC_MoveParent,
15864 : /*39790*/ OPC_MoveChild, 11,
15865 : /*39792*/ OPC_RecordNode, // #10 = $lwe
15866 : /*39793*/ OPC_MoveParent,
15867 : /*39794*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15868 : /*39796*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15869 : /*39799*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15870 : /*39802*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15871 : /*39805*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15872 : /*39808*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15873 : /*39811*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15874 : /*39814*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15875 : /*39817*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15876 : /*39820*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4), 0,
15877 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15878 : // Src: (intrinsic_wo_chain:v4f32 4817:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15879 : // Dst: (IMAGE_GATHER4_C_LZ_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15880 : /*39838*/ /*Scope*/ 72, /*->39911*/
15881 : /*39839*/ OPC_CheckChild0Integer, 90|128,37/*4826*/,
15882 : /*39842*/ OPC_RecordChild1, // #0 = $addr
15883 : /*39843*/ OPC_CheckChild1Type, MVT::v4i32,
15884 : /*39845*/ OPC_RecordChild2, // #1 = $rsrc
15885 : /*39846*/ OPC_RecordChild3, // #2 = $sampler
15886 : /*39847*/ OPC_RecordChild4, // #3 = $dmask
15887 : /*39848*/ OPC_RecordChild5, // #4 = $unorm
15888 : /*39849*/ OPC_RecordChild6, // #5 = $r128
15889 : /*39850*/ OPC_RecordChild7, // #6 = $da
15890 : /*39851*/ OPC_MoveChild, 8,
15891 : /*39853*/ OPC_RecordNode, // #7 = $glc
15892 : /*39854*/ OPC_MoveParent,
15893 : /*39855*/ OPC_MoveChild, 9,
15894 : /*39857*/ OPC_RecordNode, // #8 = $slc
15895 : /*39858*/ OPC_MoveParent,
15896 : /*39859*/ OPC_MoveChild, 10,
15897 : /*39861*/ OPC_RecordNode, // #9 = $tfe
15898 : /*39862*/ OPC_MoveParent,
15899 : /*39863*/ OPC_MoveChild, 11,
15900 : /*39865*/ OPC_RecordNode, // #10 = $lwe
15901 : /*39866*/ OPC_MoveParent,
15902 : /*39867*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15903 : /*39869*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15904 : /*39872*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15905 : /*39875*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15906 : /*39878*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15907 : /*39881*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15908 : /*39884*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15909 : /*39887*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15910 : /*39890*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15911 : /*39893*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_O_V4_V4), 0,
15912 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15913 : // Src: (intrinsic_wo_chain:v4f32 4826:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15914 : // Dst: (IMAGE_GATHER4_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15915 : /*39911*/ /*Scope*/ 16|128,1/*144*/, /*->40057*/
15916 : /*39913*/ OPC_CheckChild0Integer, 85|128,37/*4821*/,
15917 : /*39916*/ OPC_RecordChild1, // #0 = $addr
15918 : /*39917*/ OPC_Scope, 68, /*->39987*/ // 2 children in Scope
15919 : /*39919*/ OPC_CheckChild1Type, MVT::v4i32,
15920 : /*39921*/ OPC_RecordChild2, // #1 = $rsrc
15921 : /*39922*/ OPC_RecordChild3, // #2 = $sampler
15922 : /*39923*/ OPC_RecordChild4, // #3 = $dmask
15923 : /*39924*/ OPC_RecordChild5, // #4 = $unorm
15924 : /*39925*/ OPC_RecordChild6, // #5 = $r128
15925 : /*39926*/ OPC_RecordChild7, // #6 = $da
15926 : /*39927*/ OPC_MoveChild, 8,
15927 : /*39929*/ OPC_RecordNode, // #7 = $glc
15928 : /*39930*/ OPC_MoveParent,
15929 : /*39931*/ OPC_MoveChild, 9,
15930 : /*39933*/ OPC_RecordNode, // #8 = $slc
15931 : /*39934*/ OPC_MoveParent,
15932 : /*39935*/ OPC_MoveChild, 10,
15933 : /*39937*/ OPC_RecordNode, // #9 = $tfe
15934 : /*39938*/ OPC_MoveParent,
15935 : /*39939*/ OPC_MoveChild, 11,
15936 : /*39941*/ OPC_RecordNode, // #10 = $lwe
15937 : /*39942*/ OPC_MoveParent,
15938 : /*39943*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15939 : /*39945*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15940 : /*39948*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15941 : /*39951*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15942 : /*39954*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15943 : /*39957*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15944 : /*39960*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15945 : /*39963*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15946 : /*39966*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15947 : /*39969*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_O_V4_V4), 0,
15948 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15949 : // Src: (intrinsic_wo_chain:v4f32 4821:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15950 : // Dst: (IMAGE_GATHER4_CL_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15951 : /*39987*/ /*Scope*/ 68, /*->40056*/
15952 : /*39988*/ OPC_CheckChild1Type, MVT::v8i32,
15953 : /*39990*/ OPC_RecordChild2, // #1 = $rsrc
15954 : /*39991*/ OPC_RecordChild3, // #2 = $sampler
15955 : /*39992*/ OPC_RecordChild4, // #3 = $dmask
15956 : /*39993*/ OPC_RecordChild5, // #4 = $unorm
15957 : /*39994*/ OPC_RecordChild6, // #5 = $r128
15958 : /*39995*/ OPC_RecordChild7, // #6 = $da
15959 : /*39996*/ OPC_MoveChild, 8,
15960 : /*39998*/ OPC_RecordNode, // #7 = $glc
15961 : /*39999*/ OPC_MoveParent,
15962 : /*40000*/ OPC_MoveChild, 9,
15963 : /*40002*/ OPC_RecordNode, // #8 = $slc
15964 : /*40003*/ OPC_MoveParent,
15965 : /*40004*/ OPC_MoveChild, 10,
15966 : /*40006*/ OPC_RecordNode, // #9 = $tfe
15967 : /*40007*/ OPC_MoveParent,
15968 : /*40008*/ OPC_MoveChild, 11,
15969 : /*40010*/ OPC_RecordNode, // #10 = $lwe
15970 : /*40011*/ OPC_MoveParent,
15971 : /*40012*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
15972 : /*40014*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
15973 : /*40017*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
15974 : /*40020*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
15975 : /*40023*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
15976 : /*40026*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
15977 : /*40029*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
15978 : /*40032*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
15979 : /*40035*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
15980 : /*40038*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_CL_O_V4_V8), 0,
15981 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
15982 : // Src: (intrinsic_wo_chain:v4f32 4821:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
15983 : // Dst: (IMAGE_GATHER4_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
15984 : /*40056*/ 0, /*End of Scope*/
15985 : /*40057*/ /*Scope*/ 16|128,1/*144*/, /*->40203*/
15986 : /*40059*/ OPC_CheckChild0Integer, 87|128,37/*4823*/,
15987 : /*40062*/ OPC_RecordChild1, // #0 = $addr
15988 : /*40063*/ OPC_Scope, 68, /*->40133*/ // 2 children in Scope
15989 : /*40065*/ OPC_CheckChild1Type, MVT::v4i32,
15990 : /*40067*/ OPC_RecordChild2, // #1 = $rsrc
15991 : /*40068*/ OPC_RecordChild3, // #2 = $sampler
15992 : /*40069*/ OPC_RecordChild4, // #3 = $dmask
15993 : /*40070*/ OPC_RecordChild5, // #4 = $unorm
15994 : /*40071*/ OPC_RecordChild6, // #5 = $r128
15995 : /*40072*/ OPC_RecordChild7, // #6 = $da
15996 : /*40073*/ OPC_MoveChild, 8,
15997 : /*40075*/ OPC_RecordNode, // #7 = $glc
15998 : /*40076*/ OPC_MoveParent,
15999 : /*40077*/ OPC_MoveChild, 9,
16000 : /*40079*/ OPC_RecordNode, // #8 = $slc
16001 : /*40080*/ OPC_MoveParent,
16002 : /*40081*/ OPC_MoveChild, 10,
16003 : /*40083*/ OPC_RecordNode, // #9 = $tfe
16004 : /*40084*/ OPC_MoveParent,
16005 : /*40085*/ OPC_MoveChild, 11,
16006 : /*40087*/ OPC_RecordNode, // #10 = $lwe
16007 : /*40088*/ OPC_MoveParent,
16008 : /*40089*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16009 : /*40091*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16010 : /*40094*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16011 : /*40097*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16012 : /*40100*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16013 : /*40103*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16014 : /*40106*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16015 : /*40109*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16016 : /*40112*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16017 : /*40115*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_O_V4_V4), 0,
16018 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16019 : // Src: (intrinsic_wo_chain:v4f32 4823:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16020 : // Dst: (IMAGE_GATHER4_L_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16021 : /*40133*/ /*Scope*/ 68, /*->40202*/
16022 : /*40134*/ OPC_CheckChild1Type, MVT::v8i32,
16023 : /*40136*/ OPC_RecordChild2, // #1 = $rsrc
16024 : /*40137*/ OPC_RecordChild3, // #2 = $sampler
16025 : /*40138*/ OPC_RecordChild4, // #3 = $dmask
16026 : /*40139*/ OPC_RecordChild5, // #4 = $unorm
16027 : /*40140*/ OPC_RecordChild6, // #5 = $r128
16028 : /*40141*/ OPC_RecordChild7, // #6 = $da
16029 : /*40142*/ OPC_MoveChild, 8,
16030 : /*40144*/ OPC_RecordNode, // #7 = $glc
16031 : /*40145*/ OPC_MoveParent,
16032 : /*40146*/ OPC_MoveChild, 9,
16033 : /*40148*/ OPC_RecordNode, // #8 = $slc
16034 : /*40149*/ OPC_MoveParent,
16035 : /*40150*/ OPC_MoveChild, 10,
16036 : /*40152*/ OPC_RecordNode, // #9 = $tfe
16037 : /*40153*/ OPC_MoveParent,
16038 : /*40154*/ OPC_MoveChild, 11,
16039 : /*40156*/ OPC_RecordNode, // #10 = $lwe
16040 : /*40157*/ OPC_MoveParent,
16041 : /*40158*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16042 : /*40160*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16043 : /*40163*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16044 : /*40166*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16045 : /*40169*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16046 : /*40172*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16047 : /*40175*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16048 : /*40178*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16049 : /*40181*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16050 : /*40184*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_L_O_V4_V8), 0,
16051 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16052 : // Src: (intrinsic_wo_chain:v4f32 4823:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16053 : // Dst: (IMAGE_GATHER4_L_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16054 : /*40202*/ 0, /*End of Scope*/
16055 : /*40203*/ /*Scope*/ 16|128,1/*144*/, /*->40349*/
16056 : /*40205*/ OPC_CheckChild0Integer, 71|128,37/*4807*/,
16057 : /*40208*/ OPC_RecordChild1, // #0 = $addr
16058 : /*40209*/ OPC_Scope, 68, /*->40279*/ // 2 children in Scope
16059 : /*40211*/ OPC_CheckChild1Type, MVT::v4i32,
16060 : /*40213*/ OPC_RecordChild2, // #1 = $rsrc
16061 : /*40214*/ OPC_RecordChild3, // #2 = $sampler
16062 : /*40215*/ OPC_RecordChild4, // #3 = $dmask
16063 : /*40216*/ OPC_RecordChild5, // #4 = $unorm
16064 : /*40217*/ OPC_RecordChild6, // #5 = $r128
16065 : /*40218*/ OPC_RecordChild7, // #6 = $da
16066 : /*40219*/ OPC_MoveChild, 8,
16067 : /*40221*/ OPC_RecordNode, // #7 = $glc
16068 : /*40222*/ OPC_MoveParent,
16069 : /*40223*/ OPC_MoveChild, 9,
16070 : /*40225*/ OPC_RecordNode, // #8 = $slc
16071 : /*40226*/ OPC_MoveParent,
16072 : /*40227*/ OPC_MoveChild, 10,
16073 : /*40229*/ OPC_RecordNode, // #9 = $tfe
16074 : /*40230*/ OPC_MoveParent,
16075 : /*40231*/ OPC_MoveChild, 11,
16076 : /*40233*/ OPC_RecordNode, // #10 = $lwe
16077 : /*40234*/ OPC_MoveParent,
16078 : /*40235*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16079 : /*40237*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16080 : /*40240*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16081 : /*40243*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16082 : /*40246*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16083 : /*40249*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16084 : /*40252*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16085 : /*40255*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16086 : /*40258*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16087 : /*40261*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_O_V4_V4), 0,
16088 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16089 : // Src: (intrinsic_wo_chain:v4f32 4807:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16090 : // Dst: (IMAGE_GATHER4_B_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16091 : /*40279*/ /*Scope*/ 68, /*->40348*/
16092 : /*40280*/ OPC_CheckChild1Type, MVT::v8i32,
16093 : /*40282*/ OPC_RecordChild2, // #1 = $rsrc
16094 : /*40283*/ OPC_RecordChild3, // #2 = $sampler
16095 : /*40284*/ OPC_RecordChild4, // #3 = $dmask
16096 : /*40285*/ OPC_RecordChild5, // #4 = $unorm
16097 : /*40286*/ OPC_RecordChild6, // #5 = $r128
16098 : /*40287*/ OPC_RecordChild7, // #6 = $da
16099 : /*40288*/ OPC_MoveChild, 8,
16100 : /*40290*/ OPC_RecordNode, // #7 = $glc
16101 : /*40291*/ OPC_MoveParent,
16102 : /*40292*/ OPC_MoveChild, 9,
16103 : /*40294*/ OPC_RecordNode, // #8 = $slc
16104 : /*40295*/ OPC_MoveParent,
16105 : /*40296*/ OPC_MoveChild, 10,
16106 : /*40298*/ OPC_RecordNode, // #9 = $tfe
16107 : /*40299*/ OPC_MoveParent,
16108 : /*40300*/ OPC_MoveChild, 11,
16109 : /*40302*/ OPC_RecordNode, // #10 = $lwe
16110 : /*40303*/ OPC_MoveParent,
16111 : /*40304*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16112 : /*40306*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16113 : /*40309*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16114 : /*40312*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16115 : /*40315*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16116 : /*40318*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16117 : /*40321*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16118 : /*40324*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16119 : /*40327*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16120 : /*40330*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_O_V4_V8), 0,
16121 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16122 : // Src: (intrinsic_wo_chain:v4f32 4807:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16123 : // Dst: (IMAGE_GATHER4_B_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16124 : /*40348*/ 0, /*End of Scope*/
16125 : /*40349*/ /*Scope*/ 72, /*->40422*/
16126 : /*40350*/ OPC_CheckChild0Integer, 70|128,37/*4806*/,
16127 : /*40353*/ OPC_RecordChild1, // #0 = $addr
16128 : /*40354*/ OPC_CheckChild1Type, MVT::v8i32,
16129 : /*40356*/ OPC_RecordChild2, // #1 = $rsrc
16130 : /*40357*/ OPC_RecordChild3, // #2 = $sampler
16131 : /*40358*/ OPC_RecordChild4, // #3 = $dmask
16132 : /*40359*/ OPC_RecordChild5, // #4 = $unorm
16133 : /*40360*/ OPC_RecordChild6, // #5 = $r128
16134 : /*40361*/ OPC_RecordChild7, // #6 = $da
16135 : /*40362*/ OPC_MoveChild, 8,
16136 : /*40364*/ OPC_RecordNode, // #7 = $glc
16137 : /*40365*/ OPC_MoveParent,
16138 : /*40366*/ OPC_MoveChild, 9,
16139 : /*40368*/ OPC_RecordNode, // #8 = $slc
16140 : /*40369*/ OPC_MoveParent,
16141 : /*40370*/ OPC_MoveChild, 10,
16142 : /*40372*/ OPC_RecordNode, // #9 = $tfe
16143 : /*40373*/ OPC_MoveParent,
16144 : /*40374*/ OPC_MoveChild, 11,
16145 : /*40376*/ OPC_RecordNode, // #10 = $lwe
16146 : /*40377*/ OPC_MoveParent,
16147 : /*40378*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16148 : /*40380*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16149 : /*40383*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16150 : /*40386*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16151 : /*40389*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16152 : /*40392*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16153 : /*40395*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16154 : /*40398*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16155 : /*40401*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16156 : /*40404*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V8), 0,
16157 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16158 : // Src: (intrinsic_wo_chain:v4f32 4806:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16159 : // Dst: (IMAGE_GATHER4_B_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16160 : /*40422*/ /*Scope*/ 72, /*->40495*/
16161 : /*40423*/ OPC_CheckChild0Integer, 89|128,37/*4825*/,
16162 : /*40426*/ OPC_RecordChild1, // #0 = $addr
16163 : /*40427*/ OPC_CheckChild1Type, MVT::v4i32,
16164 : /*40429*/ OPC_RecordChild2, // #1 = $rsrc
16165 : /*40430*/ OPC_RecordChild3, // #2 = $sampler
16166 : /*40431*/ OPC_RecordChild4, // #3 = $dmask
16167 : /*40432*/ OPC_RecordChild5, // #4 = $unorm
16168 : /*40433*/ OPC_RecordChild6, // #5 = $r128
16169 : /*40434*/ OPC_RecordChild7, // #6 = $da
16170 : /*40435*/ OPC_MoveChild, 8,
16171 : /*40437*/ OPC_RecordNode, // #7 = $glc
16172 : /*40438*/ OPC_MoveParent,
16173 : /*40439*/ OPC_MoveChild, 9,
16174 : /*40441*/ OPC_RecordNode, // #8 = $slc
16175 : /*40442*/ OPC_MoveParent,
16176 : /*40443*/ OPC_MoveChild, 10,
16177 : /*40445*/ OPC_RecordNode, // #9 = $tfe
16178 : /*40446*/ OPC_MoveParent,
16179 : /*40447*/ OPC_MoveChild, 11,
16180 : /*40449*/ OPC_RecordNode, // #10 = $lwe
16181 : /*40450*/ OPC_MoveParent,
16182 : /*40451*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16183 : /*40453*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16184 : /*40456*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16185 : /*40459*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16186 : /*40462*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16187 : /*40465*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16188 : /*40468*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16189 : /*40471*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16190 : /*40474*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16191 : /*40477*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4), 0,
16192 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16193 : // Src: (intrinsic_wo_chain:v4f32 4825:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16194 : // Dst: (IMAGE_GATHER4_LZ_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16195 : /*40495*/ /*Scope*/ 16|128,1/*144*/, /*->40641*/
16196 : /*40497*/ OPC_CheckChild0Integer, 83|128,37/*4819*/,
16197 : /*40500*/ OPC_RecordChild1, // #0 = $addr
16198 : /*40501*/ OPC_Scope, 68, /*->40571*/ // 2 children in Scope
16199 : /*40503*/ OPC_CheckChild1Type, MVT::v4i32,
16200 : /*40505*/ OPC_RecordChild2, // #1 = $rsrc
16201 : /*40506*/ OPC_RecordChild3, // #2 = $sampler
16202 : /*40507*/ OPC_RecordChild4, // #3 = $dmask
16203 : /*40508*/ OPC_RecordChild5, // #4 = $unorm
16204 : /*40509*/ OPC_RecordChild6, // #5 = $r128
16205 : /*40510*/ OPC_RecordChild7, // #6 = $da
16206 : /*40511*/ OPC_MoveChild, 8,
16207 : /*40513*/ OPC_RecordNode, // #7 = $glc
16208 : /*40514*/ OPC_MoveParent,
16209 : /*40515*/ OPC_MoveChild, 9,
16210 : /*40517*/ OPC_RecordNode, // #8 = $slc
16211 : /*40518*/ OPC_MoveParent,
16212 : /*40519*/ OPC_MoveChild, 10,
16213 : /*40521*/ OPC_RecordNode, // #9 = $tfe
16214 : /*40522*/ OPC_MoveParent,
16215 : /*40523*/ OPC_MoveChild, 11,
16216 : /*40525*/ OPC_RecordNode, // #10 = $lwe
16217 : /*40526*/ OPC_MoveParent,
16218 : /*40527*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16219 : /*40529*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16220 : /*40532*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16221 : /*40535*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16222 : /*40538*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16223 : /*40541*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16224 : /*40544*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16225 : /*40547*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16226 : /*40550*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16227 : /*40553*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_O_V4_V4), 0,
16228 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16229 : // Src: (intrinsic_wo_chain:v4f32 4819:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16230 : // Dst: (IMAGE_GATHER4_C_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16231 : /*40571*/ /*Scope*/ 68, /*->40640*/
16232 : /*40572*/ OPC_CheckChild1Type, MVT::v8i32,
16233 : /*40574*/ OPC_RecordChild2, // #1 = $rsrc
16234 : /*40575*/ OPC_RecordChild3, // #2 = $sampler
16235 : /*40576*/ OPC_RecordChild4, // #3 = $dmask
16236 : /*40577*/ OPC_RecordChild5, // #4 = $unorm
16237 : /*40578*/ OPC_RecordChild6, // #5 = $r128
16238 : /*40579*/ OPC_RecordChild7, // #6 = $da
16239 : /*40580*/ OPC_MoveChild, 8,
16240 : /*40582*/ OPC_RecordNode, // #7 = $glc
16241 : /*40583*/ OPC_MoveParent,
16242 : /*40584*/ OPC_MoveChild, 9,
16243 : /*40586*/ OPC_RecordNode, // #8 = $slc
16244 : /*40587*/ OPC_MoveParent,
16245 : /*40588*/ OPC_MoveChild, 10,
16246 : /*40590*/ OPC_RecordNode, // #9 = $tfe
16247 : /*40591*/ OPC_MoveParent,
16248 : /*40592*/ OPC_MoveChild, 11,
16249 : /*40594*/ OPC_RecordNode, // #10 = $lwe
16250 : /*40595*/ OPC_MoveParent,
16251 : /*40596*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16252 : /*40598*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16253 : /*40601*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16254 : /*40604*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16255 : /*40607*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16256 : /*40610*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16257 : /*40613*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16258 : /*40616*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16259 : /*40619*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16260 : /*40622*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_O_V4_V8), 0,
16261 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16262 : // Src: (intrinsic_wo_chain:v4f32 4819:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16263 : // Dst: (IMAGE_GATHER4_C_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16264 : /*40640*/ 0, /*End of Scope*/
16265 : /*40641*/ /*Scope*/ 72, /*->40714*/
16266 : /*40642*/ OPC_CheckChild0Integer, 78|128,37/*4814*/,
16267 : /*40645*/ OPC_RecordChild1, // #0 = $addr
16268 : /*40646*/ OPC_CheckChild1Type, MVT::v8i32,
16269 : /*40648*/ OPC_RecordChild2, // #1 = $rsrc
16270 : /*40649*/ OPC_RecordChild3, // #2 = $sampler
16271 : /*40650*/ OPC_RecordChild4, // #3 = $dmask
16272 : /*40651*/ OPC_RecordChild5, // #4 = $unorm
16273 : /*40652*/ OPC_RecordChild6, // #5 = $r128
16274 : /*40653*/ OPC_RecordChild7, // #6 = $da
16275 : /*40654*/ OPC_MoveChild, 8,
16276 : /*40656*/ OPC_RecordNode, // #7 = $glc
16277 : /*40657*/ OPC_MoveParent,
16278 : /*40658*/ OPC_MoveChild, 9,
16279 : /*40660*/ OPC_RecordNode, // #8 = $slc
16280 : /*40661*/ OPC_MoveParent,
16281 : /*40662*/ OPC_MoveChild, 10,
16282 : /*40664*/ OPC_RecordNode, // #9 = $tfe
16283 : /*40665*/ OPC_MoveParent,
16284 : /*40666*/ OPC_MoveChild, 11,
16285 : /*40668*/ OPC_RecordNode, // #10 = $lwe
16286 : /*40669*/ OPC_MoveParent,
16287 : /*40670*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16288 : /*40672*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16289 : /*40675*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16290 : /*40678*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16291 : /*40681*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16292 : /*40684*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16293 : /*40687*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16294 : /*40690*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16295 : /*40693*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16296 : /*40696*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V8), 0,
16297 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16298 : // Src: (intrinsic_wo_chain:v4f32 4814:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16299 : // Dst: (IMAGE_GATHER4_C_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16300 : /*40714*/ /*Scope*/ 72, /*->40787*/
16301 : /*40715*/ OPC_CheckChild0Integer, 80|128,37/*4816*/,
16302 : /*40718*/ OPC_RecordChild1, // #0 = $addr
16303 : /*40719*/ OPC_CheckChild1Type, MVT::v8i32,
16304 : /*40721*/ OPC_RecordChild2, // #1 = $rsrc
16305 : /*40722*/ OPC_RecordChild3, // #2 = $sampler
16306 : /*40723*/ OPC_RecordChild4, // #3 = $dmask
16307 : /*40724*/ OPC_RecordChild5, // #4 = $unorm
16308 : /*40725*/ OPC_RecordChild6, // #5 = $r128
16309 : /*40726*/ OPC_RecordChild7, // #6 = $da
16310 : /*40727*/ OPC_MoveChild, 8,
16311 : /*40729*/ OPC_RecordNode, // #7 = $glc
16312 : /*40730*/ OPC_MoveParent,
16313 : /*40731*/ OPC_MoveChild, 9,
16314 : /*40733*/ OPC_RecordNode, // #8 = $slc
16315 : /*40734*/ OPC_MoveParent,
16316 : /*40735*/ OPC_MoveChild, 10,
16317 : /*40737*/ OPC_RecordNode, // #9 = $tfe
16318 : /*40738*/ OPC_MoveParent,
16319 : /*40739*/ OPC_MoveChild, 11,
16320 : /*40741*/ OPC_RecordNode, // #10 = $lwe
16321 : /*40742*/ OPC_MoveParent,
16322 : /*40743*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16323 : /*40745*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16324 : /*40748*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16325 : /*40751*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16326 : /*40754*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16327 : /*40757*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16328 : /*40760*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16329 : /*40763*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16330 : /*40766*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16331 : /*40769*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_L_O_V4_V8), 0,
16332 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16333 : // Src: (intrinsic_wo_chain:v4f32 4816:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16334 : // Dst: (IMAGE_GATHER4_C_L_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16335 : /*40787*/ /*Scope*/ 72, /*->40860*/
16336 : /*40788*/ OPC_CheckChild0Integer, 76|128,37/*4812*/,
16337 : /*40791*/ OPC_RecordChild1, // #0 = $addr
16338 : /*40792*/ OPC_CheckChild1Type, MVT::v8i32,
16339 : /*40794*/ OPC_RecordChild2, // #1 = $rsrc
16340 : /*40795*/ OPC_RecordChild3, // #2 = $sampler
16341 : /*40796*/ OPC_RecordChild4, // #3 = $dmask
16342 : /*40797*/ OPC_RecordChild5, // #4 = $unorm
16343 : /*40798*/ OPC_RecordChild6, // #5 = $r128
16344 : /*40799*/ OPC_RecordChild7, // #6 = $da
16345 : /*40800*/ OPC_MoveChild, 8,
16346 : /*40802*/ OPC_RecordNode, // #7 = $glc
16347 : /*40803*/ OPC_MoveParent,
16348 : /*40804*/ OPC_MoveChild, 9,
16349 : /*40806*/ OPC_RecordNode, // #8 = $slc
16350 : /*40807*/ OPC_MoveParent,
16351 : /*40808*/ OPC_MoveChild, 10,
16352 : /*40810*/ OPC_RecordNode, // #9 = $tfe
16353 : /*40811*/ OPC_MoveParent,
16354 : /*40812*/ OPC_MoveChild, 11,
16355 : /*40814*/ OPC_RecordNode, // #10 = $lwe
16356 : /*40815*/ OPC_MoveParent,
16357 : /*40816*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16358 : /*40818*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16359 : /*40821*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16360 : /*40824*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16361 : /*40827*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16362 : /*40830*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16363 : /*40833*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16364 : /*40836*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16365 : /*40839*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16366 : /*40842*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_O_V4_V8), 0,
16367 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16368 : // Src: (intrinsic_wo_chain:v4f32 4812:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16369 : // Dst: (IMAGE_GATHER4_C_B_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16370 : /*40860*/ /*Scope*/ 72, /*->40933*/
16371 : /*40861*/ OPC_CheckChild0Integer, 75|128,37/*4811*/,
16372 : /*40864*/ OPC_RecordChild1, // #0 = $addr
16373 : /*40865*/ OPC_CheckChild1Type, MVT::v8i32,
16374 : /*40867*/ OPC_RecordChild2, // #1 = $rsrc
16375 : /*40868*/ OPC_RecordChild3, // #2 = $sampler
16376 : /*40869*/ OPC_RecordChild4, // #3 = $dmask
16377 : /*40870*/ OPC_RecordChild5, // #4 = $unorm
16378 : /*40871*/ OPC_RecordChild6, // #5 = $r128
16379 : /*40872*/ OPC_RecordChild7, // #6 = $da
16380 : /*40873*/ OPC_MoveChild, 8,
16381 : /*40875*/ OPC_RecordNode, // #7 = $glc
16382 : /*40876*/ OPC_MoveParent,
16383 : /*40877*/ OPC_MoveChild, 9,
16384 : /*40879*/ OPC_RecordNode, // #8 = $slc
16385 : /*40880*/ OPC_MoveParent,
16386 : /*40881*/ OPC_MoveChild, 10,
16387 : /*40883*/ OPC_RecordNode, // #9 = $tfe
16388 : /*40884*/ OPC_MoveParent,
16389 : /*40885*/ OPC_MoveChild, 11,
16390 : /*40887*/ OPC_RecordNode, // #10 = $lwe
16391 : /*40888*/ OPC_MoveParent,
16392 : /*40889*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16393 : /*40891*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16394 : /*40894*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16395 : /*40897*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16396 : /*40900*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16397 : /*40903*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16398 : /*40906*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16399 : /*40909*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16400 : /*40912*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16401 : /*40915*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V8), 0,
16402 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16403 : // Src: (intrinsic_wo_chain:v4f32 4811:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16404 : // Dst: (IMAGE_GATHER4_C_B_CL_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16405 : /*40933*/ /*Scope*/ 16|128,1/*144*/, /*->41079*/
16406 : /*40935*/ OPC_CheckChild0Integer, 82|128,37/*4818*/,
16407 : /*40938*/ OPC_RecordChild1, // #0 = $addr
16408 : /*40939*/ OPC_Scope, 68, /*->41009*/ // 2 children in Scope
16409 : /*40941*/ OPC_CheckChild1Type, MVT::v4i32,
16410 : /*40943*/ OPC_RecordChild2, // #1 = $rsrc
16411 : /*40944*/ OPC_RecordChild3, // #2 = $sampler
16412 : /*40945*/ OPC_RecordChild4, // #3 = $dmask
16413 : /*40946*/ OPC_RecordChild5, // #4 = $unorm
16414 : /*40947*/ OPC_RecordChild6, // #5 = $r128
16415 : /*40948*/ OPC_RecordChild7, // #6 = $da
16416 : /*40949*/ OPC_MoveChild, 8,
16417 : /*40951*/ OPC_RecordNode, // #7 = $glc
16418 : /*40952*/ OPC_MoveParent,
16419 : /*40953*/ OPC_MoveChild, 9,
16420 : /*40955*/ OPC_RecordNode, // #8 = $slc
16421 : /*40956*/ OPC_MoveParent,
16422 : /*40957*/ OPC_MoveChild, 10,
16423 : /*40959*/ OPC_RecordNode, // #9 = $tfe
16424 : /*40960*/ OPC_MoveParent,
16425 : /*40961*/ OPC_MoveChild, 11,
16426 : /*40963*/ OPC_RecordNode, // #10 = $lwe
16427 : /*40964*/ OPC_MoveParent,
16428 : /*40965*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16429 : /*40967*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16430 : /*40970*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16431 : /*40973*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16432 : /*40976*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16433 : /*40979*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16434 : /*40982*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16435 : /*40985*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16436 : /*40988*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16437 : /*40991*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4), 0,
16438 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16439 : // Src: (intrinsic_wo_chain:v4f32 4818:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16440 : // Dst: (IMAGE_GATHER4_C_LZ_O_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16441 : /*41009*/ /*Scope*/ 68, /*->41078*/
16442 : /*41010*/ OPC_CheckChild1Type, MVT::v8i32,
16443 : /*41012*/ OPC_RecordChild2, // #1 = $rsrc
16444 : /*41013*/ OPC_RecordChild3, // #2 = $sampler
16445 : /*41014*/ OPC_RecordChild4, // #3 = $dmask
16446 : /*41015*/ OPC_RecordChild5, // #4 = $unorm
16447 : /*41016*/ OPC_RecordChild6, // #5 = $r128
16448 : /*41017*/ OPC_RecordChild7, // #6 = $da
16449 : /*41018*/ OPC_MoveChild, 8,
16450 : /*41020*/ OPC_RecordNode, // #7 = $glc
16451 : /*41021*/ OPC_MoveParent,
16452 : /*41022*/ OPC_MoveChild, 9,
16453 : /*41024*/ OPC_RecordNode, // #8 = $slc
16454 : /*41025*/ OPC_MoveParent,
16455 : /*41026*/ OPC_MoveChild, 10,
16456 : /*41028*/ OPC_RecordNode, // #9 = $tfe
16457 : /*41029*/ OPC_MoveParent,
16458 : /*41030*/ OPC_MoveChild, 11,
16459 : /*41032*/ OPC_RecordNode, // #10 = $lwe
16460 : /*41033*/ OPC_MoveParent,
16461 : /*41034*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16462 : /*41036*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16463 : /*41039*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16464 : /*41042*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16465 : /*41045*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16466 : /*41048*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16467 : /*41051*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16468 : /*41054*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16469 : /*41057*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16470 : /*41060*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8), 0,
16471 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16472 : // Src: (intrinsic_wo_chain:v4f32 4818:iPTR, v8i32:v8i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16473 : // Dst: (IMAGE_GATHER4_C_LZ_O_V4_V8:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v8i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16474 : /*41078*/ 0, /*End of Scope*/
16475 : /*41079*/ /*Scope*/ 85|128,1/*213*/, /*->41294*/
16476 : /*41081*/ OPC_CheckChild0Integer, 91|128,37/*4827*/,
16477 : /*41084*/ OPC_RecordChild1, // #0 = $addr
16478 : /*41085*/ OPC_Scope, 68, /*->41155*/ // 3 children in Scope
16479 : /*41087*/ OPC_CheckChild1Type, MVT::i32,
16480 : /*41089*/ OPC_RecordChild2, // #1 = $rsrc
16481 : /*41090*/ OPC_RecordChild3, // #2 = $sampler
16482 : /*41091*/ OPC_RecordChild4, // #3 = $dmask
16483 : /*41092*/ OPC_RecordChild5, // #4 = $unorm
16484 : /*41093*/ OPC_RecordChild6, // #5 = $r128
16485 : /*41094*/ OPC_RecordChild7, // #6 = $da
16486 : /*41095*/ OPC_MoveChild, 8,
16487 : /*41097*/ OPC_RecordNode, // #7 = $glc
16488 : /*41098*/ OPC_MoveParent,
16489 : /*41099*/ OPC_MoveChild, 9,
16490 : /*41101*/ OPC_RecordNode, // #8 = $slc
16491 : /*41102*/ OPC_MoveParent,
16492 : /*41103*/ OPC_MoveChild, 10,
16493 : /*41105*/ OPC_RecordNode, // #9 = $tfe
16494 : /*41106*/ OPC_MoveParent,
16495 : /*41107*/ OPC_MoveChild, 11,
16496 : /*41109*/ OPC_RecordNode, // #10 = $lwe
16497 : /*41110*/ OPC_MoveParent,
16498 : /*41111*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16499 : /*41113*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16500 : /*41116*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16501 : /*41119*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16502 : /*41122*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16503 : /*41125*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16504 : /*41128*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16505 : /*41131*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16506 : /*41134*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16507 : /*41137*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GET_LOD_V4_V1), 0,
16508 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16509 : // Src: (intrinsic_wo_chain:v4f32 4827:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16510 : // Dst: (IMAGE_GET_LOD_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16511 : /*41155*/ /*Scope*/ 68, /*->41224*/
16512 : /*41156*/ OPC_CheckChild1Type, MVT::v2i32,
16513 : /*41158*/ OPC_RecordChild2, // #1 = $rsrc
16514 : /*41159*/ OPC_RecordChild3, // #2 = $sampler
16515 : /*41160*/ OPC_RecordChild4, // #3 = $dmask
16516 : /*41161*/ OPC_RecordChild5, // #4 = $unorm
16517 : /*41162*/ OPC_RecordChild6, // #5 = $r128
16518 : /*41163*/ OPC_RecordChild7, // #6 = $da
16519 : /*41164*/ OPC_MoveChild, 8,
16520 : /*41166*/ OPC_RecordNode, // #7 = $glc
16521 : /*41167*/ OPC_MoveParent,
16522 : /*41168*/ OPC_MoveChild, 9,
16523 : /*41170*/ OPC_RecordNode, // #8 = $slc
16524 : /*41171*/ OPC_MoveParent,
16525 : /*41172*/ OPC_MoveChild, 10,
16526 : /*41174*/ OPC_RecordNode, // #9 = $tfe
16527 : /*41175*/ OPC_MoveParent,
16528 : /*41176*/ OPC_MoveChild, 11,
16529 : /*41178*/ OPC_RecordNode, // #10 = $lwe
16530 : /*41179*/ OPC_MoveParent,
16531 : /*41180*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16532 : /*41182*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16533 : /*41185*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16534 : /*41188*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16535 : /*41191*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16536 : /*41194*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16537 : /*41197*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16538 : /*41200*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16539 : /*41203*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16540 : /*41206*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GET_LOD_V4_V2), 0,
16541 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16542 : // Src: (intrinsic_wo_chain:v4f32 4827:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16543 : // Dst: (IMAGE_GET_LOD_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16544 : /*41224*/ /*Scope*/ 68, /*->41293*/
16545 : /*41225*/ OPC_CheckChild1Type, MVT::v4i32,
16546 : /*41227*/ OPC_RecordChild2, // #1 = $rsrc
16547 : /*41228*/ OPC_RecordChild3, // #2 = $sampler
16548 : /*41229*/ OPC_RecordChild4, // #3 = $dmask
16549 : /*41230*/ OPC_RecordChild5, // #4 = $unorm
16550 : /*41231*/ OPC_RecordChild6, // #5 = $r128
16551 : /*41232*/ OPC_RecordChild7, // #6 = $da
16552 : /*41233*/ OPC_MoveChild, 8,
16553 : /*41235*/ OPC_RecordNode, // #7 = $glc
16554 : /*41236*/ OPC_MoveParent,
16555 : /*41237*/ OPC_MoveChild, 9,
16556 : /*41239*/ OPC_RecordNode, // #8 = $slc
16557 : /*41240*/ OPC_MoveParent,
16558 : /*41241*/ OPC_MoveChild, 10,
16559 : /*41243*/ OPC_RecordNode, // #9 = $tfe
16560 : /*41244*/ OPC_MoveParent,
16561 : /*41245*/ OPC_MoveChild, 11,
16562 : /*41247*/ OPC_RecordNode, // #10 = $lwe
16563 : /*41248*/ OPC_MoveParent,
16564 : /*41249*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16565 : /*41251*/ OPC_EmitNodeXForm, 4, 3, // as_i32imm
16566 : /*41254*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16567 : /*41257*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16568 : /*41260*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16569 : /*41263*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16570 : /*41266*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16571 : /*41269*/ OPC_EmitNodeXForm, 1, 10, // as_i1imm
16572 : /*41272*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16573 : /*41275*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GET_LOD_V4_V4), 0,
16574 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 11, 12, 13, 14, 15, 16, 17, 18, 0, 1, 2,
16575 : // Src: (intrinsic_wo_chain:v4f32 4827:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, v4i32:v4i32:$sampler, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16576 : // Dst: (IMAGE_GET_LOD_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc, ?:v4i32:$sampler)
16577 : /*41293*/ 0, /*End of Scope*/
16578 : /*41294*/ /*Scope*/ 67, /*->41362*/
16579 : /*41295*/ OPC_CheckChild0Integer, 92|128,37/*4828*/,
16580 : /*41298*/ OPC_RecordChild1, // #0 = $addr
16581 : /*41299*/ OPC_CheckChild1Type, MVT::i32,
16582 : /*41301*/ OPC_RecordChild2, // #1 = $rsrc
16583 : /*41302*/ OPC_RecordChild3, // #2 = $dmask
16584 : /*41303*/ OPC_RecordChild4, // #3 = $unorm
16585 : /*41304*/ OPC_RecordChild5, // #4 = $r128
16586 : /*41305*/ OPC_RecordChild6, // #5 = $da
16587 : /*41306*/ OPC_RecordChild7, // #6 = $glc
16588 : /*41307*/ OPC_MoveChild, 8,
16589 : /*41309*/ OPC_RecordNode, // #7 = $slc
16590 : /*41310*/ OPC_MoveParent,
16591 : /*41311*/ OPC_MoveChild, 9,
16592 : /*41313*/ OPC_RecordNode, // #8 = $tfe
16593 : /*41314*/ OPC_MoveParent,
16594 : /*41315*/ OPC_MoveChild, 10,
16595 : /*41317*/ OPC_RecordNode, // #9 = $lwe
16596 : /*41318*/ OPC_MoveParent,
16597 : /*41319*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16598 : /*41321*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
16599 : /*41324*/ OPC_EmitNodeXForm, 1, 3, // as_i1imm
16600 : /*41327*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16601 : /*41330*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16602 : /*41333*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16603 : /*41336*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16604 : /*41339*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16605 : /*41342*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16606 : /*41345*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_GET_RESINFO_V4_V1), 0,
16607 : 1/*#VTs*/, MVT::v4f32, 10/*#Ops*/, 10, 11, 12, 13, 14, 15, 16, 17, 0, 1,
16608 : // Src: (intrinsic_wo_chain:v4f32 4828:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16609 : // Dst: (IMAGE_GET_RESINFO_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc)
16610 : /*41362*/ /*Scope*/ 70|128,1/*198*/, /*->41562*/
16611 : /*41364*/ OPC_CheckChild0Integer, 95|128,37/*4831*/,
16612 : /*41367*/ OPC_RecordChild1, // #0 = $addr
16613 : /*41368*/ OPC_Scope, 63, /*->41433*/ // 3 children in Scope
16614 : /*41370*/ OPC_CheckChild1Type, MVT::i32,
16615 : /*41372*/ OPC_RecordChild2, // #1 = $rsrc
16616 : /*41373*/ OPC_RecordChild3, // #2 = $dmask
16617 : /*41374*/ OPC_RecordChild4, // #3 = $unorm
16618 : /*41375*/ OPC_RecordChild5, // #4 = $r128
16619 : /*41376*/ OPC_RecordChild6, // #5 = $da
16620 : /*41377*/ OPC_RecordChild7, // #6 = $glc
16621 : /*41378*/ OPC_MoveChild, 8,
16622 : /*41380*/ OPC_RecordNode, // #7 = $slc
16623 : /*41381*/ OPC_MoveParent,
16624 : /*41382*/ OPC_MoveChild, 9,
16625 : /*41384*/ OPC_RecordNode, // #8 = $tfe
16626 : /*41385*/ OPC_MoveParent,
16627 : /*41386*/ OPC_MoveChild, 10,
16628 : /*41388*/ OPC_RecordNode, // #9 = $lwe
16629 : /*41389*/ OPC_MoveParent,
16630 : /*41390*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16631 : /*41392*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
16632 : /*41395*/ OPC_EmitNodeXForm, 1, 3, // as_i1imm
16633 : /*41398*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16634 : /*41401*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16635 : /*41404*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16636 : /*41407*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16637 : /*41410*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16638 : /*41413*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16639 : /*41416*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_V4_V1), 0,
16640 : 1/*#VTs*/, MVT::v4f32, 10/*#Ops*/, 10, 11, 12, 13, 14, 15, 16, 17, 0, 1,
16641 : // Src: (intrinsic_wo_chain:v4f32 4831:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16642 : // Dst: (IMAGE_LOAD_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc)
16643 : /*41433*/ /*Scope*/ 63, /*->41497*/
16644 : /*41434*/ OPC_CheckChild1Type, MVT::v2i32,
16645 : /*41436*/ OPC_RecordChild2, // #1 = $rsrc
16646 : /*41437*/ OPC_RecordChild3, // #2 = $dmask
16647 : /*41438*/ OPC_RecordChild4, // #3 = $unorm
16648 : /*41439*/ OPC_RecordChild5, // #4 = $r128
16649 : /*41440*/ OPC_RecordChild6, // #5 = $da
16650 : /*41441*/ OPC_RecordChild7, // #6 = $glc
16651 : /*41442*/ OPC_MoveChild, 8,
16652 : /*41444*/ OPC_RecordNode, // #7 = $slc
16653 : /*41445*/ OPC_MoveParent,
16654 : /*41446*/ OPC_MoveChild, 9,
16655 : /*41448*/ OPC_RecordNode, // #8 = $tfe
16656 : /*41449*/ OPC_MoveParent,
16657 : /*41450*/ OPC_MoveChild, 10,
16658 : /*41452*/ OPC_RecordNode, // #9 = $lwe
16659 : /*41453*/ OPC_MoveParent,
16660 : /*41454*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16661 : /*41456*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
16662 : /*41459*/ OPC_EmitNodeXForm, 1, 3, // as_i1imm
16663 : /*41462*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16664 : /*41465*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16665 : /*41468*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16666 : /*41471*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16667 : /*41474*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16668 : /*41477*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16669 : /*41480*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_V4_V2), 0,
16670 : 1/*#VTs*/, MVT::v4f32, 10/*#Ops*/, 10, 11, 12, 13, 14, 15, 16, 17, 0, 1,
16671 : // Src: (intrinsic_wo_chain:v4f32 4831:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16672 : // Dst: (IMAGE_LOAD_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc)
16673 : /*41497*/ /*Scope*/ 63, /*->41561*/
16674 : /*41498*/ OPC_CheckChild1Type, MVT::v4i32,
16675 : /*41500*/ OPC_RecordChild2, // #1 = $rsrc
16676 : /*41501*/ OPC_RecordChild3, // #2 = $dmask
16677 : /*41502*/ OPC_RecordChild4, // #3 = $unorm
16678 : /*41503*/ OPC_RecordChild5, // #4 = $r128
16679 : /*41504*/ OPC_RecordChild6, // #5 = $da
16680 : /*41505*/ OPC_RecordChild7, // #6 = $glc
16681 : /*41506*/ OPC_MoveChild, 8,
16682 : /*41508*/ OPC_RecordNode, // #7 = $slc
16683 : /*41509*/ OPC_MoveParent,
16684 : /*41510*/ OPC_MoveChild, 9,
16685 : /*41512*/ OPC_RecordNode, // #8 = $tfe
16686 : /*41513*/ OPC_MoveParent,
16687 : /*41514*/ OPC_MoveChild, 10,
16688 : /*41516*/ OPC_RecordNode, // #9 = $lwe
16689 : /*41517*/ OPC_MoveParent,
16690 : /*41518*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16691 : /*41520*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
16692 : /*41523*/ OPC_EmitNodeXForm, 1, 3, // as_i1imm
16693 : /*41526*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16694 : /*41529*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16695 : /*41532*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16696 : /*41535*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16697 : /*41538*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16698 : /*41541*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16699 : /*41544*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_V4_V4), 0,
16700 : 1/*#VTs*/, MVT::v4f32, 10/*#Ops*/, 10, 11, 12, 13, 14, 15, 16, 17, 0, 1,
16701 : // Src: (intrinsic_wo_chain:v4f32 4831:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16702 : // Dst: (IMAGE_LOAD_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc)
16703 : /*41561*/ 0, /*End of Scope*/
16704 : /*41562*/ /*Scope*/ 70|128,1/*198*/, /*->41762*/
16705 : /*41564*/ OPC_CheckChild0Integer, 96|128,37/*4832*/,
16706 : /*41567*/ OPC_RecordChild1, // #0 = $addr
16707 : /*41568*/ OPC_Scope, 63, /*->41633*/ // 3 children in Scope
16708 : /*41570*/ OPC_CheckChild1Type, MVT::i32,
16709 : /*41572*/ OPC_RecordChild2, // #1 = $rsrc
16710 : /*41573*/ OPC_RecordChild3, // #2 = $dmask
16711 : /*41574*/ OPC_RecordChild4, // #3 = $unorm
16712 : /*41575*/ OPC_RecordChild5, // #4 = $r128
16713 : /*41576*/ OPC_RecordChild6, // #5 = $da
16714 : /*41577*/ OPC_RecordChild7, // #6 = $glc
16715 : /*41578*/ OPC_MoveChild, 8,
16716 : /*41580*/ OPC_RecordNode, // #7 = $slc
16717 : /*41581*/ OPC_MoveParent,
16718 : /*41582*/ OPC_MoveChild, 9,
16719 : /*41584*/ OPC_RecordNode, // #8 = $tfe
16720 : /*41585*/ OPC_MoveParent,
16721 : /*41586*/ OPC_MoveChild, 10,
16722 : /*41588*/ OPC_RecordNode, // #9 = $lwe
16723 : /*41589*/ OPC_MoveParent,
16724 : /*41590*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16725 : /*41592*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
16726 : /*41595*/ OPC_EmitNodeXForm, 1, 3, // as_i1imm
16727 : /*41598*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16728 : /*41601*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16729 : /*41604*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16730 : /*41607*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16731 : /*41610*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16732 : /*41613*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16733 : /*41616*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_MIP_V4_V1), 0,
16734 : 1/*#VTs*/, MVT::v4f32, 10/*#Ops*/, 10, 11, 12, 13, 14, 15, 16, 17, 0, 1,
16735 : // Src: (intrinsic_wo_chain:v4f32 4832:iPTR, i32:i32:$addr, v8i32:v8i32:$rsrc, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16736 : // Dst: (IMAGE_LOAD_MIP_V4_V1:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:i32:$addr, ?:v8i32:$rsrc)
16737 : /*41633*/ /*Scope*/ 63, /*->41697*/
16738 : /*41634*/ OPC_CheckChild1Type, MVT::v2i32,
16739 : /*41636*/ OPC_RecordChild2, // #1 = $rsrc
16740 : /*41637*/ OPC_RecordChild3, // #2 = $dmask
16741 : /*41638*/ OPC_RecordChild4, // #3 = $unorm
16742 : /*41639*/ OPC_RecordChild5, // #4 = $r128
16743 : /*41640*/ OPC_RecordChild6, // #5 = $da
16744 : /*41641*/ OPC_RecordChild7, // #6 = $glc
16745 : /*41642*/ OPC_MoveChild, 8,
16746 : /*41644*/ OPC_RecordNode, // #7 = $slc
16747 : /*41645*/ OPC_MoveParent,
16748 : /*41646*/ OPC_MoveChild, 9,
16749 : /*41648*/ OPC_RecordNode, // #8 = $tfe
16750 : /*41649*/ OPC_MoveParent,
16751 : /*41650*/ OPC_MoveChild, 10,
16752 : /*41652*/ OPC_RecordNode, // #9 = $lwe
16753 : /*41653*/ OPC_MoveParent,
16754 : /*41654*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16755 : /*41656*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
16756 : /*41659*/ OPC_EmitNodeXForm, 1, 3, // as_i1imm
16757 : /*41662*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16758 : /*41665*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16759 : /*41668*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16760 : /*41671*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16761 : /*41674*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16762 : /*41677*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16763 : /*41680*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_MIP_V4_V2), 0,
16764 : 1/*#VTs*/, MVT::v4f32, 10/*#Ops*/, 10, 11, 12, 13, 14, 15, 16, 17, 0, 1,
16765 : // Src: (intrinsic_wo_chain:v4f32 4832:iPTR, v2i32:v2i32:$addr, v8i32:v8i32:$rsrc, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16766 : // Dst: (IMAGE_LOAD_MIP_V4_V2:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v2i32:$addr, ?:v8i32:$rsrc)
16767 : /*41697*/ /*Scope*/ 63, /*->41761*/
16768 : /*41698*/ OPC_CheckChild1Type, MVT::v4i32,
16769 : /*41700*/ OPC_RecordChild2, // #1 = $rsrc
16770 : /*41701*/ OPC_RecordChild3, // #2 = $dmask
16771 : /*41702*/ OPC_RecordChild4, // #3 = $unorm
16772 : /*41703*/ OPC_RecordChild5, // #4 = $r128
16773 : /*41704*/ OPC_RecordChild6, // #5 = $da
16774 : /*41705*/ OPC_RecordChild7, // #6 = $glc
16775 : /*41706*/ OPC_MoveChild, 8,
16776 : /*41708*/ OPC_RecordNode, // #7 = $slc
16777 : /*41709*/ OPC_MoveParent,
16778 : /*41710*/ OPC_MoveChild, 9,
16779 : /*41712*/ OPC_RecordNode, // #8 = $tfe
16780 : /*41713*/ OPC_MoveParent,
16781 : /*41714*/ OPC_MoveChild, 10,
16782 : /*41716*/ OPC_RecordNode, // #9 = $lwe
16783 : /*41717*/ OPC_MoveParent,
16784 : /*41718*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
16785 : /*41720*/ OPC_EmitNodeXForm, 4, 2, // as_i32imm
16786 : /*41723*/ OPC_EmitNodeXForm, 1, 3, // as_i1imm
16787 : /*41726*/ OPC_EmitNodeXForm, 1, 6, // as_i1imm
16788 : /*41729*/ OPC_EmitNodeXForm, 1, 5, // as_i1imm
16789 : /*41732*/ OPC_EmitNodeXForm, 1, 4, // as_i1imm
16790 : /*41735*/ OPC_EmitNodeXForm, 1, 8, // as_i1imm
16791 : /*41738*/ OPC_EmitNodeXForm, 1, 9, // as_i1imm
16792 : /*41741*/ OPC_EmitNodeXForm, 1, 7, // as_i1imm
16793 : /*41744*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_LOAD_MIP_V4_V4), 0,
16794 : 1/*#VTs*/, MVT::v4f32, 10/*#Ops*/, 10, 11, 12, 13, 14, 15, 16, 17, 0, 1,
16795 : // Src: (intrinsic_wo_chain:v4f32 4832:iPTR, v4i32:v4i32:$addr, v8i32:v8i32:$rsrc, i32:i32:$dmask, i32:i32:$unorm, i32:i32:$r128, i32:i32:$da, i32:i32:$glc, i32:i32:$slc, i32:i32:$tfe, i32:i32:$lwe) - Complexity = 8
16796 : // Dst: (IMAGE_LOAD_MIP_V4_V4:v4f32 (as_i32imm:i32 ?:i32:$dmask), (as_i1imm:i1 ?:i32:$unorm), (as_i1imm:i1 ?:i32:$glc), (as_i1imm:i1 ?:i32:$da), (as_i1imm:i1 ?:i32:$r128), (as_i1imm:i1 ?:i32:$tfe), (as_i1imm:i1 ?:i32:$lwe), (as_i1imm:i1 ?:i32:$slc), ?:v4i32:$addr, ?:v8i32:$rsrc)
16797 : /*41761*/ 0, /*End of Scope*/
16798 : /*41762*/ 0, /*End of Scope*/
16799 : /*41763*/ /*SwitchOpcode*/ 23, TARGET_VAL(AMDGPUISD::SENDMSG),// ->41789
16800 : /*41766*/ OPC_RecordNode, // #0 = 'AMDGPUsendmsg' chained node
16801 : /*41767*/ OPC_CaptureGlueInput,
16802 : /*41768*/ OPC_RecordChild1, // #1 = $simm16
16803 : /*41769*/ OPC_MoveChild, 1,
16804 : /*41771*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
16805 : /*41774*/ OPC_CheckType, MVT::i32,
16806 : /*41776*/ OPC_MoveParent,
16807 : /*41777*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
16808 : /*41779*/ OPC_EmitMergeInputChains1_0,
16809 : /*41780*/ OPC_EmitConvertToTarget, 1,
16810 : /*41782*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_SENDMSG), 0|OPFL_Chain|OPFL_GlueInput,
16811 : 0/*#VTs*/, 1/*#Ops*/, 2,
16812 : // Src: (AMDGPUsendmsg (imm:i32):$simm16) - Complexity = 6
16813 : // Dst: (S_SENDMSG (imm:i32):$simm16)
16814 : /*41789*/ /*SwitchOpcode*/ 21, TARGET_VAL(AMDGPUISD::STORE_MSKOR),// ->41813
16815 : /*41792*/ OPC_RecordMemRef,
16816 : /*41793*/ OPC_RecordNode, // #0 = 'AMDGPUstore_mskor' chained node
16817 : /*41794*/ OPC_RecordChild1, // #1 = $rw_gpr
16818 : /*41795*/ OPC_CheckChild1Type, MVT::v4i32,
16819 : /*41797*/ OPC_RecordChild2, // #2 = $index_gpr
16820 : /*41798*/ OPC_CheckChild2Type, MVT::i32,
16821 : /*41800*/ OPC_CheckPredicate, 120, // Predicate_mskor_global
16822 : /*41802*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
16823 : /*41804*/ OPC_EmitMergeInputChains1_0,
16824 : /*41805*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RAT_MSKOR), 0|OPFL_Chain|OPFL_MemRefs,
16825 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
16826 : // Src: (AMDGPUstore_mskor v4i32:v4i32:$rw_gpr, i32:i32:$index_gpr)<<P:Predicate_mskor_global>> - Complexity = 4
16827 : // Dst: (RAT_MSKOR v4i32:v4i32:$rw_gpr, i32:i32:$index_gpr)
16828 : /*41813*/ /*SwitchOpcode*/ 112|128,1/*240*/, TARGET_VAL(ISD::SRL),// ->42057
16829 : /*41817*/ OPC_RecordChild0, // #0 = $src0
16830 : /*41818*/ OPC_RecordChild1, // #1 = $src1
16831 : /*41819*/ OPC_CheckChild1Type, MVT::i32,
16832 : /*41821*/ OPC_SwitchType /*2 cases */, 90|128,1/*218*/, MVT::i32,// ->42043
16833 : /*41825*/ OPC_Scope, 11, /*->41838*/ // 3 children in Scope
16834 : /*41827*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
16835 : /*41829*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LSHR_B32), 0,
16836 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
16837 : // Src: (srl:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 4
16838 : // Dst: (S_LSHR_B32:i32 i32:i32:$src0, i32:i32:$src1)
16839 : /*41838*/ /*Scope*/ 101, /*->41940*/
16840 : /*41839*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
16841 : /*41841*/ OPC_EmitInteger, MVT::i32, 0,
16842 : /*41844*/ OPC_EmitInteger, MVT::i32, 0,
16843 : /*41847*/ OPC_EmitInteger, MVT::i32, 1,
16844 : /*41850*/ OPC_EmitInteger, MVT::i32, 0,
16845 : /*41853*/ OPC_EmitInteger, MVT::i32, 0,
16846 : /*41856*/ OPC_EmitInteger, MVT::i32, 0,
16847 : /*41859*/ OPC_EmitInteger, MVT::i32, 0,
16848 : /*41862*/ OPC_EmitInteger, MVT::i32, 0,
16849 : /*41865*/ OPC_EmitInteger, MVT::i32, 0,
16850 : /*41868*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
16851 : /*41880*/ OPC_EmitInteger, MVT::i32, 0,
16852 : /*41883*/ OPC_EmitInteger, MVT::i32, 0,
16853 : /*41886*/ OPC_EmitInteger, MVT::i32, 0,
16854 : /*41889*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
16855 : /*41901*/ OPC_EmitInteger, MVT::i32, 1,
16856 : /*41904*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
16857 : /*41907*/ OPC_EmitInteger, MVT::i32, 0,
16858 : /*41910*/ OPC_EmitInteger, MVT::i32, 0,
16859 : /*41913*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LSHR_r600), 0,
16860 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
16861 : // Src: (srl:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
16862 : // Dst: (LSHR_r600:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
16863 : /*41940*/ /*Scope*/ 101, /*->42042*/
16864 : /*41941*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
16865 : /*41943*/ OPC_EmitInteger, MVT::i32, 0,
16866 : /*41946*/ OPC_EmitInteger, MVT::i32, 0,
16867 : /*41949*/ OPC_EmitInteger, MVT::i32, 1,
16868 : /*41952*/ OPC_EmitInteger, MVT::i32, 0,
16869 : /*41955*/ OPC_EmitInteger, MVT::i32, 0,
16870 : /*41958*/ OPC_EmitInteger, MVT::i32, 0,
16871 : /*41961*/ OPC_EmitInteger, MVT::i32, 0,
16872 : /*41964*/ OPC_EmitInteger, MVT::i32, 0,
16873 : /*41967*/ OPC_EmitInteger, MVT::i32, 0,
16874 : /*41970*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
16875 : /*41982*/ OPC_EmitInteger, MVT::i32, 0,
16876 : /*41985*/ OPC_EmitInteger, MVT::i32, 0,
16877 : /*41988*/ OPC_EmitInteger, MVT::i32, 0,
16878 : /*41991*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
16879 : /*42003*/ OPC_EmitInteger, MVT::i32, 1,
16880 : /*42006*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
16881 : /*42009*/ OPC_EmitInteger, MVT::i32, 0,
16882 : /*42012*/ OPC_EmitInteger, MVT::i32, 0,
16883 : /*42015*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LSHR_eg), 0,
16884 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
16885 : // Src: (srl:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
16886 : // Dst: (LSHR_eg:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
16887 : /*42042*/ 0, /*End of Scope*/
16888 : /*42043*/ /*SwitchType*/ 11, MVT::i64,// ->42056
16889 : /*42045*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
16890 : /*42047*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_LSHR_B64), 0,
16891 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 0, 1,
16892 : // Src: (srl:i64 i64:i64:$src0, i32:i32:$src1) - Complexity = 4
16893 : // Dst: (S_LSHR_B64:i64 i64:i64:$src0, i32:i32:$src1)
16894 : /*42056*/ 0, // EndSwitchType
16895 : /*42057*/ /*SwitchOpcode*/ 112|128,1/*240*/, TARGET_VAL(ISD::SRA),// ->42301
16896 : /*42061*/ OPC_RecordChild0, // #0 = $src0
16897 : /*42062*/ OPC_RecordChild1, // #1 = $src1
16898 : /*42063*/ OPC_CheckChild1Type, MVT::i32,
16899 : /*42065*/ OPC_SwitchType /*2 cases */, 90|128,1/*218*/, MVT::i32,// ->42287
16900 : /*42069*/ OPC_Scope, 11, /*->42082*/ // 3 children in Scope
16901 : /*42071*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
16902 : /*42073*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_ASHR_I32), 0,
16903 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
16904 : // Src: (sra:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 4
16905 : // Dst: (S_ASHR_I32:i32 i32:i32:$src0, i32:i32:$src1)
16906 : /*42082*/ /*Scope*/ 101, /*->42184*/
16907 : /*42083*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
16908 : /*42085*/ OPC_EmitInteger, MVT::i32, 0,
16909 : /*42088*/ OPC_EmitInteger, MVT::i32, 0,
16910 : /*42091*/ OPC_EmitInteger, MVT::i32, 1,
16911 : /*42094*/ OPC_EmitInteger, MVT::i32, 0,
16912 : /*42097*/ OPC_EmitInteger, MVT::i32, 0,
16913 : /*42100*/ OPC_EmitInteger, MVT::i32, 0,
16914 : /*42103*/ OPC_EmitInteger, MVT::i32, 0,
16915 : /*42106*/ OPC_EmitInteger, MVT::i32, 0,
16916 : /*42109*/ OPC_EmitInteger, MVT::i32, 0,
16917 : /*42112*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
16918 : /*42124*/ OPC_EmitInteger, MVT::i32, 0,
16919 : /*42127*/ OPC_EmitInteger, MVT::i32, 0,
16920 : /*42130*/ OPC_EmitInteger, MVT::i32, 0,
16921 : /*42133*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
16922 : /*42145*/ OPC_EmitInteger, MVT::i32, 1,
16923 : /*42148*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
16924 : /*42151*/ OPC_EmitInteger, MVT::i32, 0,
16925 : /*42154*/ OPC_EmitInteger, MVT::i32, 0,
16926 : /*42157*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::ASHR_r600), 0,
16927 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
16928 : // Src: (sra:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
16929 : // Dst: (ASHR_r600:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
16930 : /*42184*/ /*Scope*/ 101, /*->42286*/
16931 : /*42185*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
16932 : /*42187*/ OPC_EmitInteger, MVT::i32, 0,
16933 : /*42190*/ OPC_EmitInteger, MVT::i32, 0,
16934 : /*42193*/ OPC_EmitInteger, MVT::i32, 1,
16935 : /*42196*/ OPC_EmitInteger, MVT::i32, 0,
16936 : /*42199*/ OPC_EmitInteger, MVT::i32, 0,
16937 : /*42202*/ OPC_EmitInteger, MVT::i32, 0,
16938 : /*42205*/ OPC_EmitInteger, MVT::i32, 0,
16939 : /*42208*/ OPC_EmitInteger, MVT::i32, 0,
16940 : /*42211*/ OPC_EmitInteger, MVT::i32, 0,
16941 : /*42214*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
16942 : /*42226*/ OPC_EmitInteger, MVT::i32, 0,
16943 : /*42229*/ OPC_EmitInteger, MVT::i32, 0,
16944 : /*42232*/ OPC_EmitInteger, MVT::i32, 0,
16945 : /*42235*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
16946 : /*42247*/ OPC_EmitInteger, MVT::i32, 1,
16947 : /*42250*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
16948 : /*42253*/ OPC_EmitInteger, MVT::i32, 0,
16949 : /*42256*/ OPC_EmitInteger, MVT::i32, 0,
16950 : /*42259*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::ASHR_eg), 0,
16951 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
16952 : // Src: (sra:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
16953 : // Dst: (ASHR_eg:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
16954 : /*42286*/ 0, /*End of Scope*/
16955 : /*42287*/ /*SwitchType*/ 11, MVT::i64,// ->42300
16956 : /*42289*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
16957 : /*42291*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_ASHR_I64), 0,
16958 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 0, 1,
16959 : // Src: (sra:i64 i64:i64:$src0, i32:i32:$src1) - Complexity = 4
16960 : // Dst: (S_ASHR_I64:i64 i64:i64:$src0, i32:i32:$src1)
16961 : /*42300*/ 0, // EndSwitchType
16962 : /*42301*/ /*SwitchOpcode*/ 120, TARGET_VAL(AMDGPUISD::BFM),// ->42424
16963 : /*42304*/ OPC_RecordChild0, // #0 = $src0
16964 : /*42305*/ OPC_RecordChild1, // #1 = $src1
16965 : /*42306*/ OPC_CheckType, MVT::i32,
16966 : /*42308*/ OPC_Scope, 11, /*->42321*/ // 2 children in Scope
16967 : /*42310*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
16968 : /*42312*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BFM_B32), 0,
16969 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
16970 : // Src: (AMDGPUbfm:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 4
16971 : // Dst: (S_BFM_B32:i32 i32:i32:$src0, i32:i32:$src1)
16972 : /*42321*/ /*Scope*/ 101, /*->42423*/
16973 : /*42322*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
16974 : /*42324*/ OPC_EmitInteger, MVT::i32, 0,
16975 : /*42327*/ OPC_EmitInteger, MVT::i32, 0,
16976 : /*42330*/ OPC_EmitInteger, MVT::i32, 1,
16977 : /*42333*/ OPC_EmitInteger, MVT::i32, 0,
16978 : /*42336*/ OPC_EmitInteger, MVT::i32, 0,
16979 : /*42339*/ OPC_EmitInteger, MVT::i32, 0,
16980 : /*42342*/ OPC_EmitInteger, MVT::i32, 0,
16981 : /*42345*/ OPC_EmitInteger, MVT::i32, 0,
16982 : /*42348*/ OPC_EmitInteger, MVT::i32, 0,
16983 : /*42351*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
16984 : /*42363*/ OPC_EmitInteger, MVT::i32, 0,
16985 : /*42366*/ OPC_EmitInteger, MVT::i32, 0,
16986 : /*42369*/ OPC_EmitInteger, MVT::i32, 0,
16987 : /*42372*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
16988 : /*42384*/ OPC_EmitInteger, MVT::i32, 1,
16989 : /*42387*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
16990 : /*42390*/ OPC_EmitInteger, MVT::i32, 0,
16991 : /*42393*/ OPC_EmitInteger, MVT::i32, 0,
16992 : /*42396*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFM_INT_eg), 0,
16993 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
16994 : // Src: (AMDGPUbfm:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
16995 : // Dst: (BFM_INT_eg:i32 i32:i32:$src0, i32:i32:$src1)
16996 : /*42423*/ 0, /*End of Scope*/
16997 : /*42424*/ /*SwitchOpcode*/ 68|128,2/*324*/, TARGET_VAL(ISD::MUL),// ->42752
16998 : /*42428*/ OPC_RecordChild0, // #0 = $src0
16999 : /*42429*/ OPC_RecordChild1, // #1 = $src1
17000 : /*42430*/ OPC_CheckType, MVT::i32,
17001 : /*42432*/ OPC_Scope, 11, /*->42445*/ // 4 children in Scope
17002 : /*42434*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
17003 : /*42436*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_MUL_I32), 0,
17004 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
17005 : // Src: (mul:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 4
17006 : // Dst: (S_MUL_I32:i32 i32:i32:$src0, i32:i32:$src1)
17007 : /*42445*/ /*Scope*/ 101, /*->42547*/
17008 : /*42446*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
17009 : /*42448*/ OPC_EmitInteger, MVT::i32, 0,
17010 : /*42451*/ OPC_EmitInteger, MVT::i32, 0,
17011 : /*42454*/ OPC_EmitInteger, MVT::i32, 1,
17012 : /*42457*/ OPC_EmitInteger, MVT::i32, 0,
17013 : /*42460*/ OPC_EmitInteger, MVT::i32, 0,
17014 : /*42463*/ OPC_EmitInteger, MVT::i32, 0,
17015 : /*42466*/ OPC_EmitInteger, MVT::i32, 0,
17016 : /*42469*/ OPC_EmitInteger, MVT::i32, 0,
17017 : /*42472*/ OPC_EmitInteger, MVT::i32, 0,
17018 : /*42475*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17019 : /*42487*/ OPC_EmitInteger, MVT::i32, 0,
17020 : /*42490*/ OPC_EmitInteger, MVT::i32, 0,
17021 : /*42493*/ OPC_EmitInteger, MVT::i32, 0,
17022 : /*42496*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17023 : /*42508*/ OPC_EmitInteger, MVT::i32, 1,
17024 : /*42511*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17025 : /*42514*/ OPC_EmitInteger, MVT::i32, 0,
17026 : /*42517*/ OPC_EmitInteger, MVT::i32, 0,
17027 : /*42520*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULLO_INT_r600), 0,
17028 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17029 : // Src: (mul:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17030 : // Dst: (MULLO_INT_r600:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17031 : /*42547*/ /*Scope*/ 101, /*->42649*/
17032 : /*42548*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
17033 : /*42550*/ OPC_EmitInteger, MVT::i32, 0,
17034 : /*42553*/ OPC_EmitInteger, MVT::i32, 0,
17035 : /*42556*/ OPC_EmitInteger, MVT::i32, 1,
17036 : /*42559*/ OPC_EmitInteger, MVT::i32, 0,
17037 : /*42562*/ OPC_EmitInteger, MVT::i32, 0,
17038 : /*42565*/ OPC_EmitInteger, MVT::i32, 0,
17039 : /*42568*/ OPC_EmitInteger, MVT::i32, 0,
17040 : /*42571*/ OPC_EmitInteger, MVT::i32, 0,
17041 : /*42574*/ OPC_EmitInteger, MVT::i32, 0,
17042 : /*42577*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17043 : /*42589*/ OPC_EmitInteger, MVT::i32, 0,
17044 : /*42592*/ OPC_EmitInteger, MVT::i32, 0,
17045 : /*42595*/ OPC_EmitInteger, MVT::i32, 0,
17046 : /*42598*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17047 : /*42610*/ OPC_EmitInteger, MVT::i32, 1,
17048 : /*42613*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17049 : /*42616*/ OPC_EmitInteger, MVT::i32, 0,
17050 : /*42619*/ OPC_EmitInteger, MVT::i32, 0,
17051 : /*42622*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULLO_INT_eg), 0,
17052 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17053 : // Src: (mul:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17054 : // Dst: (MULLO_INT_eg:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17055 : /*42649*/ /*Scope*/ 101, /*->42751*/
17056 : /*42650*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
17057 : /*42652*/ OPC_EmitInteger, MVT::i32, 0,
17058 : /*42655*/ OPC_EmitInteger, MVT::i32, 0,
17059 : /*42658*/ OPC_EmitInteger, MVT::i32, 1,
17060 : /*42661*/ OPC_EmitInteger, MVT::i32, 0,
17061 : /*42664*/ OPC_EmitInteger, MVT::i32, 0,
17062 : /*42667*/ OPC_EmitInteger, MVT::i32, 0,
17063 : /*42670*/ OPC_EmitInteger, MVT::i32, 0,
17064 : /*42673*/ OPC_EmitInteger, MVT::i32, 0,
17065 : /*42676*/ OPC_EmitInteger, MVT::i32, 0,
17066 : /*42679*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17067 : /*42691*/ OPC_EmitInteger, MVT::i32, 0,
17068 : /*42694*/ OPC_EmitInteger, MVT::i32, 0,
17069 : /*42697*/ OPC_EmitInteger, MVT::i32, 0,
17070 : /*42700*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17071 : /*42712*/ OPC_EmitInteger, MVT::i32, 1,
17072 : /*42715*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17073 : /*42718*/ OPC_EmitInteger, MVT::i32, 0,
17074 : /*42721*/ OPC_EmitInteger, MVT::i32, 0,
17075 : /*42724*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULLO_INT_cm), 0,
17076 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17077 : // Src: (mul:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17078 : // Dst: (MULLO_INT_cm:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17079 : /*42751*/ 0, /*End of Scope*/
17080 : /*42752*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::Constant),// ->42837
17081 : /*42755*/ OPC_RecordNode, // #0 = $imm
17082 : /*42756*/ OPC_SwitchType /*3 cases */, 46, MVT::i32,// ->42805
17083 : /*42759*/ OPC_Scope, 14, /*->42775*/ // 2 children in Scope
17084 : /*42761*/ OPC_CheckPredicate, 121, // Predicate_anonymous_1454
17085 : /*42763*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17086 : /*42765*/ OPC_EmitConvertToTarget, 0,
17087 : /*42767*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
17088 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1,
17089 : // Src: (imm:i32)<<P:Predicate_anonymous_1454>>:$imm - Complexity = 4
17090 : // Dst: (S_MOV_B32:i32 (imm:i32):$imm)
17091 : /*42775*/ /*Scope*/ 28, /*->42804*/
17092 : /*42776*/ OPC_Scope, 12, /*->42790*/ // 2 children in Scope
17093 : /*42778*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17094 : /*42780*/ OPC_EmitConvertToTarget, 0,
17095 : /*42782*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
17096 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1,
17097 : // Src: (imm:i32):$imm - Complexity = 3
17098 : // Dst: (V_MOV_B32_e32:i32 (imm:i32):$imm)
17099 : /*42790*/ /*Scope*/ 12, /*->42803*/
17100 : /*42791*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17101 : /*42793*/ OPC_EmitConvertToTarget, 0,
17102 : /*42795*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MOV_IMM_I32), 0,
17103 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1,
17104 : // Src: (imm:i32):$val - Complexity = 3
17105 : // Dst: (MOV_IMM_I32:i32 (imm:i32):$val)
17106 : /*42803*/ 0, /*End of Scope*/
17107 : /*42804*/ 0, /*End of Scope*/
17108 : /*42805*/ /*SwitchType*/ 14, MVT::i64,// ->42821
17109 : /*42807*/ OPC_CheckPredicate, 122, // Predicate_anonymous_1460
17110 : /*42809*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17111 : /*42811*/ OPC_EmitConvertToTarget, 0,
17112 : /*42813*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_MOV_B64), 0,
17113 : 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 1,
17114 : // Src: (imm:i64)<<P:Predicate_anonymous_1460>>:$imm - Complexity = 4
17115 : // Dst: (S_MOV_B64:i64 (imm:i64)<<P:Predicate_anonymous_1461>>:$imm)
17116 : /*42821*/ /*SwitchType*/ 13, MVT::i1,// ->42836
17117 : /*42823*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17118 : /*42825*/ OPC_EmitNodeXForm, 6, 0, // as_i64imm
17119 : /*42828*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_MOV_B64), 0,
17120 : 1/*#VTs*/, MVT::i1, 1/*#Ops*/, 1,
17121 : // Src: (imm:i1):$imm - Complexity = 3
17122 : // Dst: (S_MOV_B64:i1 (as_i64imm:i64 ?:i1:$imm))
17123 : /*42836*/ 0, // EndSwitchType
17124 : /*42837*/ /*SwitchOpcode*/ 32|128,2/*288*/, TARGET_VAL(ISD::BITCAST),// ->43129
17125 : /*42841*/ OPC_RecordChild0, // #0 = $src0
17126 : /*42842*/ OPC_Scope, 25, /*->42869*/ // 13 children in Scope
17127 : /*42844*/ OPC_CheckChild0Type, MVT::f32,
17128 : /*42846*/ OPC_CheckType, MVT::i32,
17129 : /*42848*/ OPC_Scope, 5, /*->42855*/ // 2 children in Scope
17130 : /*42850*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17131 : /*42852*/ OPC_CompleteMatch, 1, 0,
17132 : // Src: (bitconvert:i32 R600_Reg32:f32:$src0) - Complexity = 3
17133 : // Dst: R600_Reg32:i32:$src0
17134 : /*42855*/ /*Scope*/ 12, /*->42868*/
17135 : /*42856*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17136 : /*42858*/ OPC_Scope, 3, /*->42863*/ // 2 children in Scope
17137 : /*42860*/ OPC_CompleteMatch, 1, 0,
17138 : // Src: (bitconvert:i32 SReg_32:f32:$src0) - Complexity = 3
17139 : // Dst: SReg_32:i32:$src0
17140 : /*42863*/ /*Scope*/ 3, /*->42867*/
17141 : /*42864*/ OPC_CompleteMatch, 1, 0,
17142 : // Src: (bitconvert:i32 VGPR_32:f32:$src0) - Complexity = 3
17143 : // Dst: VGPR_32:i32:$src0
17144 : /*42867*/ 0, /*End of Scope*/
17145 : /*42868*/ 0, /*End of Scope*/
17146 : /*42869*/ /*Scope*/ 18, /*->42888*/
17147 : /*42870*/ OPC_CheckChild0Type, MVT::f64,
17148 : /*42872*/ OPC_SwitchType /*2 cases */, 5, MVT::i64,// ->42880
17149 : /*42875*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17150 : /*42877*/ OPC_CompleteMatch, 1, 0,
17151 : // Src: (bitconvert:i64 VReg_64:f64:$src0) - Complexity = 3
17152 : // Dst: VReg_64:i64:$src0
17153 : /*42880*/ /*SwitchType*/ 5, MVT::v2i32,// ->42887
17154 : /*42882*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17155 : /*42884*/ OPC_CompleteMatch, 1, 0,
17156 : // Src: (bitconvert:v2i32 VReg_64:f64:$src0) - Complexity = 3
17157 : // Dst: VReg_64:v2i32:$src0
17158 : /*42887*/ 0, // EndSwitchType
17159 : /*42888*/ /*Scope*/ 34, /*->42923*/
17160 : /*42889*/ OPC_CheckChild0Type, MVT::v2i32,
17161 : /*42891*/ OPC_SwitchType /*3 cases */, 5, MVT::i64,// ->42899
17162 : /*42894*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17163 : /*42896*/ OPC_CompleteMatch, 1, 0,
17164 : // Src: (bitconvert:i64 VReg_64:v2i32:$src0) - Complexity = 3
17165 : // Dst: VReg_64:i64:$src0
17166 : /*42899*/ /*SwitchType*/ 5, MVT::f64,// ->42906
17167 : /*42901*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17168 : /*42903*/ OPC_CompleteMatch, 1, 0,
17169 : // Src: (bitconvert:f64 VReg_64:v2i32:$src0) - Complexity = 3
17170 : // Dst: VReg_64:f64:$src0
17171 : /*42906*/ /*SwitchType*/ 14, MVT::v2f32,// ->42922
17172 : /*42908*/ OPC_Scope, 5, /*->42915*/ // 2 children in Scope
17173 : /*42910*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17174 : /*42912*/ OPC_CompleteMatch, 1, 0,
17175 : // Src: (bitconvert:v2f32 R600_Reg64:v2i32:$src0) - Complexity = 3
17176 : // Dst: R600_Reg64:v2f32:$src0
17177 : /*42915*/ /*Scope*/ 5, /*->42921*/
17178 : /*42916*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17179 : /*42918*/ OPC_CompleteMatch, 1, 0,
17180 : // Src: (bitconvert:v2f32 VReg_64:v2i32:$src0) - Complexity = 3
17181 : // Dst: VReg_64:v2f32:$src0
17182 : /*42921*/ 0, /*End of Scope*/
17183 : /*42922*/ 0, // EndSwitchType
17184 : /*42923*/ /*Scope*/ 27, /*->42951*/
17185 : /*42924*/ OPC_CheckChild0Type, MVT::v2f32,
17186 : /*42926*/ OPC_SwitchType /*2 cases */, 5, MVT::i64,// ->42934
17187 : /*42929*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17188 : /*42931*/ OPC_CompleteMatch, 1, 0,
17189 : // Src: (bitconvert:i64 VReg_64:v2f32:$src0) - Complexity = 3
17190 : // Dst: VReg_64:i64:$src0
17191 : /*42934*/ /*SwitchType*/ 14, MVT::v2i32,// ->42950
17192 : /*42936*/ OPC_Scope, 5, /*->42943*/ // 2 children in Scope
17193 : /*42938*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17194 : /*42940*/ OPC_CompleteMatch, 1, 0,
17195 : // Src: (bitconvert:v2i32 R600_Reg64:v2f32:$src0) - Complexity = 3
17196 : // Dst: R600_Reg64:v2i32:$src0
17197 : /*42943*/ /*Scope*/ 5, /*->42949*/
17198 : /*42944*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17199 : /*42946*/ OPC_CompleteMatch, 1, 0,
17200 : // Src: (bitconvert:v2i32 VReg_64:v2f32:$src0) - Complexity = 3
17201 : // Dst: VReg_64:v2i32:$src0
17202 : /*42949*/ 0, /*End of Scope*/
17203 : /*42950*/ 0, // EndSwitchType
17204 : /*42951*/ /*Scope*/ 25, /*->42977*/
17205 : /*42952*/ OPC_CheckChild0Type, MVT::i32,
17206 : /*42954*/ OPC_CheckType, MVT::f32,
17207 : /*42956*/ OPC_Scope, 5, /*->42963*/ // 2 children in Scope
17208 : /*42958*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17209 : /*42960*/ OPC_CompleteMatch, 1, 0,
17210 : // Src: (bitconvert:f32 R600_Reg32:i32:$src0) - Complexity = 3
17211 : // Dst: R600_Reg32:f32:$src0
17212 : /*42963*/ /*Scope*/ 12, /*->42976*/
17213 : /*42964*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17214 : /*42966*/ OPC_Scope, 3, /*->42971*/ // 2 children in Scope
17215 : /*42968*/ OPC_CompleteMatch, 1, 0,
17216 : // Src: (bitconvert:f32 SReg_32:i32:$src0) - Complexity = 3
17217 : // Dst: SReg_32:f32:$src0
17218 : /*42971*/ /*Scope*/ 3, /*->42975*/
17219 : /*42972*/ OPC_CompleteMatch, 1, 0,
17220 : // Src: (bitconvert:f32 VGPR_32:i32:$src0) - Complexity = 3
17221 : // Dst: VGPR_32:f32:$src0
17222 : /*42975*/ 0, /*End of Scope*/
17223 : /*42976*/ 0, /*End of Scope*/
17224 : /*42977*/ /*Scope*/ 25, /*->43003*/
17225 : /*42978*/ OPC_CheckChild0Type, MVT::i64,
17226 : /*42980*/ OPC_SwitchType /*3 cases */, 5, MVT::f64,// ->42988
17227 : /*42983*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17228 : /*42985*/ OPC_CompleteMatch, 1, 0,
17229 : // Src: (bitconvert:f64 VReg_64:i64:$src0) - Complexity = 3
17230 : // Dst: VReg_64:f64:$src0
17231 : /*42988*/ /*SwitchType*/ 5, MVT::v2i32,// ->42995
17232 : /*42990*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17233 : /*42992*/ OPC_CompleteMatch, 1, 0,
17234 : // Src: (bitconvert:v2i32 VReg_64:i64:$src0) - Complexity = 3
17235 : // Dst: VReg_64:v2i32:$src0
17236 : /*42995*/ /*SwitchType*/ 5, MVT::v2f32,// ->43002
17237 : /*42997*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17238 : /*42999*/ OPC_CompleteMatch, 1, 0,
17239 : // Src: (bitconvert:v2f32 VReg_64:i64:$src0) - Complexity = 3
17240 : // Dst: VReg_64:v2f32:$src0
17241 : /*43002*/ 0, // EndSwitchType
17242 : /*43003*/ /*Scope*/ 18, /*->43022*/
17243 : /*43004*/ OPC_CheckChild0Type, MVT::v4f32,
17244 : /*43006*/ OPC_CheckType, MVT::v4i32,
17245 : /*43008*/ OPC_Scope, 5, /*->43015*/ // 2 children in Scope
17246 : /*43010*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17247 : /*43012*/ OPC_CompleteMatch, 1, 0,
17248 : // Src: (bitconvert:v4i32 R600_Reg128:v4f32:$src0) - Complexity = 3
17249 : // Dst: R600_Reg128:v4i32:$src0
17250 : /*43015*/ /*Scope*/ 5, /*->43021*/
17251 : /*43016*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17252 : /*43018*/ OPC_CompleteMatch, 1, 0,
17253 : // Src: (bitconvert:v4i32 VReg_128:v4f32:$src0) - Complexity = 3
17254 : // Dst: VReg_128:v4i32:$src0
17255 : /*43021*/ 0, /*End of Scope*/
17256 : /*43022*/ /*Scope*/ 16, /*->43039*/
17257 : /*43023*/ OPC_CheckChild0Type, MVT::v8f32,
17258 : /*43025*/ OPC_CheckType, MVT::v8i32,
17259 : /*43027*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17260 : /*43029*/ OPC_Scope, 3, /*->43034*/ // 2 children in Scope
17261 : /*43031*/ OPC_CompleteMatch, 1, 0,
17262 : // Src: (bitconvert:v8i32 SReg_256:v8f32:$src0) - Complexity = 3
17263 : // Dst: SReg_256:v8i32:$src0
17264 : /*43034*/ /*Scope*/ 3, /*->43038*/
17265 : /*43035*/ OPC_CompleteMatch, 1, 0,
17266 : // Src: (bitconvert:v8i32 VReg_256:v8f32:$src0) - Complexity = 3
17267 : // Dst: VReg_256:v8i32:$src0
17268 : /*43038*/ 0, /*End of Scope*/
17269 : /*43039*/ /*Scope*/ 16, /*->43056*/
17270 : /*43040*/ OPC_CheckChild0Type, MVT::v32i8,
17271 : /*43042*/ OPC_CheckType, MVT::v8i32,
17272 : /*43044*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17273 : /*43046*/ OPC_Scope, 3, /*->43051*/ // 2 children in Scope
17274 : /*43048*/ OPC_CompleteMatch, 1, 0,
17275 : // Src: (bitconvert:v8i32 SReg_256:v32i8:$src0) - Complexity = 3
17276 : // Dst: SReg_256:v8i32:$src0
17277 : /*43051*/ /*Scope*/ 3, /*->43055*/
17278 : /*43052*/ OPC_CompleteMatch, 1, 0,
17279 : // Src: (bitconvert:v8i32 VReg_256:v32i8:$src0) - Complexity = 3
17280 : // Dst: VReg_256:v8i32:$src0
17281 : /*43055*/ 0, /*End of Scope*/
17282 : /*43056*/ /*Scope*/ 32, /*->43089*/
17283 : /*43057*/ OPC_CheckChild0Type, MVT::v8i32,
17284 : /*43059*/ OPC_SwitchType /*2 cases */, 12, MVT::v32i8,// ->43074
17285 : /*43062*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17286 : /*43064*/ OPC_Scope, 3, /*->43069*/ // 2 children in Scope
17287 : /*43066*/ OPC_CompleteMatch, 1, 0,
17288 : // Src: (bitconvert:v32i8 SReg_256:v8i32:$src0) - Complexity = 3
17289 : // Dst: SReg_256:v32i8:$src0
17290 : /*43069*/ /*Scope*/ 3, /*->43073*/
17291 : /*43070*/ OPC_CompleteMatch, 1, 0,
17292 : // Src: (bitconvert:v32i8 VReg_256:v8i32:$src0) - Complexity = 3
17293 : // Dst: VReg_256:v32i8:$src0
17294 : /*43073*/ 0, /*End of Scope*/
17295 : /*43074*/ /*SwitchType*/ 12, MVT::v8f32,// ->43088
17296 : /*43076*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17297 : /*43078*/ OPC_Scope, 3, /*->43083*/ // 2 children in Scope
17298 : /*43080*/ OPC_CompleteMatch, 1, 0,
17299 : // Src: (bitconvert:v8f32 SReg_256:v8i32:$src0) - Complexity = 3
17300 : // Dst: SReg_256:v8f32:$src0
17301 : /*43083*/ /*Scope*/ 3, /*->43087*/
17302 : /*43084*/ OPC_CompleteMatch, 1, 0,
17303 : // Src: (bitconvert:v8f32 VReg_256:v8i32:$src0) - Complexity = 3
17304 : // Dst: VReg_256:v8f32:$src0
17305 : /*43087*/ 0, /*End of Scope*/
17306 : /*43088*/ 0, // EndSwitchType
17307 : /*43089*/ /*Scope*/ 9, /*->43099*/
17308 : /*43090*/ OPC_CheckChild0Type, MVT::v16f32,
17309 : /*43092*/ OPC_CheckType, MVT::v16i32,
17310 : /*43094*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17311 : /*43096*/ OPC_CompleteMatch, 1, 0,
17312 : // Src: (bitconvert:v16i32 VReg_512:v16f32:$src0) - Complexity = 3
17313 : // Dst: VReg_512:v16i32:$src0
17314 : /*43099*/ /*Scope*/ 18, /*->43118*/
17315 : /*43100*/ OPC_CheckChild0Type, MVT::v4i32,
17316 : /*43102*/ OPC_CheckType, MVT::v4f32,
17317 : /*43104*/ OPC_Scope, 5, /*->43111*/ // 2 children in Scope
17318 : /*43106*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17319 : /*43108*/ OPC_CompleteMatch, 1, 0,
17320 : // Src: (bitconvert:v4f32 R600_Reg128:v4i32:$src0) - Complexity = 3
17321 : // Dst: R600_Reg128:v4f32:$src0
17322 : /*43111*/ /*Scope*/ 5, /*->43117*/
17323 : /*43112*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17324 : /*43114*/ OPC_CompleteMatch, 1, 0,
17325 : // Src: (bitconvert:v4f32 VReg_128:v4i32:$src0) - Complexity = 3
17326 : // Dst: VReg_128:v4f32:$src0
17327 : /*43117*/ 0, /*End of Scope*/
17328 : /*43118*/ /*Scope*/ 9, /*->43128*/
17329 : /*43119*/ OPC_CheckChild0Type, MVT::v16i32,
17330 : /*43121*/ OPC_CheckType, MVT::v16f32,
17331 : /*43123*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17332 : /*43125*/ OPC_CompleteMatch, 1, 0,
17333 : // Src: (bitconvert:v16f32 VReg_512:v16i32:$src0) - Complexity = 3
17334 : // Dst: VReg_512:v16f32:$src0
17335 : /*43128*/ 0, /*End of Scope*/
17336 : /*43129*/ /*SwitchOpcode*/ 8, TARGET_VAL(AMDGPUISD::DWORDADDR),// ->43140
17337 : /*43132*/ OPC_RecordChild0, // #0 = $addr
17338 : /*43133*/ OPC_CheckType, MVT::i32,
17339 : /*43135*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17340 : /*43137*/ OPC_CompleteMatch, 1, 0,
17341 : // Src: (AMDGPUdwordaddr:i32 R600_Reg32:i32:$addr) - Complexity = 3
17342 : // Dst: R600_Reg32:i32:$addr
17343 : /*43140*/ /*SwitchOpcode*/ 120, TARGET_VAL(ISD::SUB),// ->43263
17344 : /*43143*/ OPC_RecordChild0, // #0 = $src0
17345 : /*43144*/ OPC_RecordChild1, // #1 = $src1
17346 : /*43145*/ OPC_CheckType, MVT::i32,
17347 : /*43147*/ OPC_Scope, 101, /*->43250*/ // 2 children in Scope
17348 : /*43149*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17349 : /*43151*/ OPC_EmitInteger, MVT::i32, 0,
17350 : /*43154*/ OPC_EmitInteger, MVT::i32, 0,
17351 : /*43157*/ OPC_EmitInteger, MVT::i32, 1,
17352 : /*43160*/ OPC_EmitInteger, MVT::i32, 0,
17353 : /*43163*/ OPC_EmitInteger, MVT::i32, 0,
17354 : /*43166*/ OPC_EmitInteger, MVT::i32, 0,
17355 : /*43169*/ OPC_EmitInteger, MVT::i32, 0,
17356 : /*43172*/ OPC_EmitInteger, MVT::i32, 0,
17357 : /*43175*/ OPC_EmitInteger, MVT::i32, 0,
17358 : /*43178*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17359 : /*43190*/ OPC_EmitInteger, MVT::i32, 0,
17360 : /*43193*/ OPC_EmitInteger, MVT::i32, 0,
17361 : /*43196*/ OPC_EmitInteger, MVT::i32, 0,
17362 : /*43199*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17363 : /*43211*/ OPC_EmitInteger, MVT::i32, 1,
17364 : /*43214*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17365 : /*43217*/ OPC_EmitInteger, MVT::i32, 0,
17366 : /*43220*/ OPC_EmitInteger, MVT::i32, 0,
17367 : /*43223*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SUB_INT), 0,
17368 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17369 : // Src: (sub:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17370 : // Dst: (SUB_INT:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17371 : /*43250*/ /*Scope*/ 11, /*->43262*/
17372 : /*43251*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
17373 : /*43253*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_SUB_I32), 0,
17374 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
17375 : // Src: (sub:i32 SSrc_32:i32:$src0, SSrc_32:i32:$src1) - Complexity = 3
17376 : // Dst: (S_SUB_I32:i32 SSrc_32:i32:$src0, SSrc_32:i32:$src1)
17377 : /*43262*/ 0, /*End of Scope*/
17378 : /*43263*/ /*SwitchOpcode*/ 120, TARGET_VAL(ISD::SMAX),// ->43386
17379 : /*43266*/ OPC_RecordChild0, // #0 = $src0
17380 : /*43267*/ OPC_RecordChild1, // #1 = $src1
17381 : /*43268*/ OPC_CheckType, MVT::i32,
17382 : /*43270*/ OPC_Scope, 101, /*->43373*/ // 2 children in Scope
17383 : /*43272*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17384 : /*43274*/ OPC_EmitInteger, MVT::i32, 0,
17385 : /*43277*/ OPC_EmitInteger, MVT::i32, 0,
17386 : /*43280*/ OPC_EmitInteger, MVT::i32, 1,
17387 : /*43283*/ OPC_EmitInteger, MVT::i32, 0,
17388 : /*43286*/ OPC_EmitInteger, MVT::i32, 0,
17389 : /*43289*/ OPC_EmitInteger, MVT::i32, 0,
17390 : /*43292*/ OPC_EmitInteger, MVT::i32, 0,
17391 : /*43295*/ OPC_EmitInteger, MVT::i32, 0,
17392 : /*43298*/ OPC_EmitInteger, MVT::i32, 0,
17393 : /*43301*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17394 : /*43313*/ OPC_EmitInteger, MVT::i32, 0,
17395 : /*43316*/ OPC_EmitInteger, MVT::i32, 0,
17396 : /*43319*/ OPC_EmitInteger, MVT::i32, 0,
17397 : /*43322*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17398 : /*43334*/ OPC_EmitInteger, MVT::i32, 1,
17399 : /*43337*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17400 : /*43340*/ OPC_EmitInteger, MVT::i32, 0,
17401 : /*43343*/ OPC_EmitInteger, MVT::i32, 0,
17402 : /*43346*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MAX_INT), 0,
17403 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17404 : // Src: (smax:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17405 : // Dst: (MAX_INT:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17406 : /*43373*/ /*Scope*/ 11, /*->43385*/
17407 : /*43374*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
17408 : /*43376*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_MAX_I32), 0,
17409 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
17410 : // Src: (smax:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
17411 : // Dst: (S_MAX_I32:i32 i32:i32:$src0, i32:i32:$src1)
17412 : /*43385*/ 0, /*End of Scope*/
17413 : /*43386*/ /*SwitchOpcode*/ 120, TARGET_VAL(ISD::SMIN),// ->43509
17414 : /*43389*/ OPC_RecordChild0, // #0 = $src0
17415 : /*43390*/ OPC_RecordChild1, // #1 = $src1
17416 : /*43391*/ OPC_CheckType, MVT::i32,
17417 : /*43393*/ OPC_Scope, 101, /*->43496*/ // 2 children in Scope
17418 : /*43395*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17419 : /*43397*/ OPC_EmitInteger, MVT::i32, 0,
17420 : /*43400*/ OPC_EmitInteger, MVT::i32, 0,
17421 : /*43403*/ OPC_EmitInteger, MVT::i32, 1,
17422 : /*43406*/ OPC_EmitInteger, MVT::i32, 0,
17423 : /*43409*/ OPC_EmitInteger, MVT::i32, 0,
17424 : /*43412*/ OPC_EmitInteger, MVT::i32, 0,
17425 : /*43415*/ OPC_EmitInteger, MVT::i32, 0,
17426 : /*43418*/ OPC_EmitInteger, MVT::i32, 0,
17427 : /*43421*/ OPC_EmitInteger, MVT::i32, 0,
17428 : /*43424*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17429 : /*43436*/ OPC_EmitInteger, MVT::i32, 0,
17430 : /*43439*/ OPC_EmitInteger, MVT::i32, 0,
17431 : /*43442*/ OPC_EmitInteger, MVT::i32, 0,
17432 : /*43445*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17433 : /*43457*/ OPC_EmitInteger, MVT::i32, 1,
17434 : /*43460*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17435 : /*43463*/ OPC_EmitInteger, MVT::i32, 0,
17436 : /*43466*/ OPC_EmitInteger, MVT::i32, 0,
17437 : /*43469*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MIN_INT), 0,
17438 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17439 : // Src: (smin:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17440 : // Dst: (MIN_INT:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17441 : /*43496*/ /*Scope*/ 11, /*->43508*/
17442 : /*43497*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
17443 : /*43499*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_MIN_I32), 0,
17444 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
17445 : // Src: (smin:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
17446 : // Dst: (S_MIN_I32:i32 i32:i32:$src0, i32:i32:$src1)
17447 : /*43508*/ 0, /*End of Scope*/
17448 : /*43509*/ /*SwitchOpcode*/ 120, TARGET_VAL(ISD::UMAX),// ->43632
17449 : /*43512*/ OPC_RecordChild0, // #0 = $src0
17450 : /*43513*/ OPC_RecordChild1, // #1 = $src1
17451 : /*43514*/ OPC_CheckType, MVT::i32,
17452 : /*43516*/ OPC_Scope, 101, /*->43619*/ // 2 children in Scope
17453 : /*43518*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17454 : /*43520*/ OPC_EmitInteger, MVT::i32, 0,
17455 : /*43523*/ OPC_EmitInteger, MVT::i32, 0,
17456 : /*43526*/ OPC_EmitInteger, MVT::i32, 1,
17457 : /*43529*/ OPC_EmitInteger, MVT::i32, 0,
17458 : /*43532*/ OPC_EmitInteger, MVT::i32, 0,
17459 : /*43535*/ OPC_EmitInteger, MVT::i32, 0,
17460 : /*43538*/ OPC_EmitInteger, MVT::i32, 0,
17461 : /*43541*/ OPC_EmitInteger, MVT::i32, 0,
17462 : /*43544*/ OPC_EmitInteger, MVT::i32, 0,
17463 : /*43547*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17464 : /*43559*/ OPC_EmitInteger, MVT::i32, 0,
17465 : /*43562*/ OPC_EmitInteger, MVT::i32, 0,
17466 : /*43565*/ OPC_EmitInteger, MVT::i32, 0,
17467 : /*43568*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17468 : /*43580*/ OPC_EmitInteger, MVT::i32, 1,
17469 : /*43583*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17470 : /*43586*/ OPC_EmitInteger, MVT::i32, 0,
17471 : /*43589*/ OPC_EmitInteger, MVT::i32, 0,
17472 : /*43592*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MAX_UINT), 0,
17473 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17474 : // Src: (umax:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17475 : // Dst: (MAX_UINT:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17476 : /*43619*/ /*Scope*/ 11, /*->43631*/
17477 : /*43620*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
17478 : /*43622*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_MAX_U32), 0,
17479 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
17480 : // Src: (umax:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
17481 : // Dst: (S_MAX_U32:i32 i32:i32:$src0, i32:i32:$src1)
17482 : /*43631*/ 0, /*End of Scope*/
17483 : /*43632*/ /*SwitchOpcode*/ 120, TARGET_VAL(ISD::UMIN),// ->43755
17484 : /*43635*/ OPC_RecordChild0, // #0 = $src0
17485 : /*43636*/ OPC_RecordChild1, // #1 = $src1
17486 : /*43637*/ OPC_CheckType, MVT::i32,
17487 : /*43639*/ OPC_Scope, 101, /*->43742*/ // 2 children in Scope
17488 : /*43641*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
17489 : /*43643*/ OPC_EmitInteger, MVT::i32, 0,
17490 : /*43646*/ OPC_EmitInteger, MVT::i32, 0,
17491 : /*43649*/ OPC_EmitInteger, MVT::i32, 1,
17492 : /*43652*/ OPC_EmitInteger, MVT::i32, 0,
17493 : /*43655*/ OPC_EmitInteger, MVT::i32, 0,
17494 : /*43658*/ OPC_EmitInteger, MVT::i32, 0,
17495 : /*43661*/ OPC_EmitInteger, MVT::i32, 0,
17496 : /*43664*/ OPC_EmitInteger, MVT::i32, 0,
17497 : /*43667*/ OPC_EmitInteger, MVT::i32, 0,
17498 : /*43670*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17499 : /*43682*/ OPC_EmitInteger, MVT::i32, 0,
17500 : /*43685*/ OPC_EmitInteger, MVT::i32, 0,
17501 : /*43688*/ OPC_EmitInteger, MVT::i32, 0,
17502 : /*43691*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17503 : /*43703*/ OPC_EmitInteger, MVT::i32, 1,
17504 : /*43706*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17505 : /*43709*/ OPC_EmitInteger, MVT::i32, 0,
17506 : /*43712*/ OPC_EmitInteger, MVT::i32, 0,
17507 : /*43715*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MIN_UINT), 0,
17508 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17509 : // Src: (umin:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17510 : // Dst: (MIN_UINT:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17511 : /*43742*/ /*Scope*/ 11, /*->43754*/
17512 : /*43743*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
17513 : /*43745*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_MIN_U32), 0,
17514 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
17515 : // Src: (umin:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
17516 : // Dst: (S_MIN_U32:i32 i32:i32:$src0, i32:i32:$src1)
17517 : /*43754*/ 0, /*End of Scope*/
17518 : /*43755*/ /*SwitchOpcode*/ 100|128,2/*356*/, TARGET_VAL(ISD::FP_TO_SINT),// ->44115
17519 : /*43759*/ OPC_Scope, 81|128,1/*209*/, /*->43971*/ // 3 children in Scope
17520 : /*43762*/ OPC_RecordChild0, // #0 = $src0
17521 : /*43763*/ OPC_CheckChild0Type, MVT::f32,
17522 : /*43765*/ OPC_CheckType, MVT::i32,
17523 : /*43767*/ OPC_Scope, 67, /*->43836*/ // 2 children in Scope
17524 : /*43769*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
17525 : /*43771*/ OPC_EmitInteger, MVT::i32, 1,
17526 : /*43774*/ OPC_EmitInteger, MVT::i32, 0,
17527 : /*43777*/ OPC_EmitInteger, MVT::i32, 0,
17528 : /*43780*/ OPC_EmitInteger, MVT::i32, 0,
17529 : /*43783*/ OPC_EmitInteger, MVT::i32, 0,
17530 : /*43786*/ OPC_EmitInteger, MVT::i32, 0,
17531 : /*43789*/ OPC_EmitInteger, MVT::i32, 0,
17532 : /*43792*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17533 : /*43804*/ OPC_EmitInteger, MVT::i32, 1,
17534 : /*43807*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17535 : /*43810*/ OPC_EmitInteger, MVT::i32, 0,
17536 : /*43813*/ OPC_EmitInteger, MVT::i32, 0,
17537 : /*43816*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLT_TO_INT_r600), 0,
17538 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
17539 : // Src: (fp_to_sint:i32 R600_Reg32:f32:$src0) - Complexity = 3
17540 : // Dst: (FLT_TO_INT_r600:i32 R600_Reg32:f32:$src0)
17541 : /*43836*/ /*Scope*/ 4|128,1/*132*/, /*->43970*/
17542 : /*43838*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
17543 : /*43840*/ OPC_EmitInteger, MVT::i32, 1,
17544 : /*43843*/ OPC_EmitInteger, MVT::i32, 0,
17545 : /*43846*/ OPC_EmitInteger, MVT::i32, 0,
17546 : /*43849*/ OPC_EmitInteger, MVT::i32, 0,
17547 : /*43852*/ OPC_EmitInteger, MVT::i32, 1,
17548 : /*43855*/ OPC_EmitInteger, MVT::i32, 0,
17549 : /*43858*/ OPC_EmitInteger, MVT::i32, 0,
17550 : /*43861*/ OPC_EmitInteger, MVT::i32, 0,
17551 : /*43864*/ OPC_EmitInteger, MVT::i32, 0,
17552 : /*43867*/ OPC_EmitInteger, MVT::i32, 0,
17553 : /*43870*/ OPC_EmitInteger, MVT::i32, 0,
17554 : /*43873*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17555 : /*43885*/ OPC_EmitInteger, MVT::i32, 1,
17556 : /*43888*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17557 : /*43891*/ OPC_EmitInteger, MVT::i32, 0,
17558 : /*43894*/ OPC_EmitInteger, MVT::i32, 0,
17559 : /*43897*/ OPC_EmitNode, TARGET_VAL(AMDGPU::TRUNC), 0,
17560 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 5, 6, 7, 8, 0, 9, 10, 11, 12, 13, 14, 15, 16, // Results = #17
17561 : /*43917*/ OPC_EmitInteger, MVT::i32, 0,
17562 : /*43920*/ OPC_EmitInteger, MVT::i32, 0,
17563 : /*43923*/ OPC_EmitInteger, MVT::i32, 0,
17564 : /*43926*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17565 : /*43938*/ OPC_EmitInteger, MVT::i32, 1,
17566 : /*43941*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17567 : /*43944*/ OPC_EmitInteger, MVT::i32, 0,
17568 : /*43947*/ OPC_EmitInteger, MVT::i32, 0,
17569 : /*43950*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLT_TO_INT_eg), 0,
17570 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 1, 2, 3, 4, 17, 18, 19, 20, 21, 22, 23, 24, 25,
17571 : // Src: (fp_to_sint:i32 f32:f32:$src0) - Complexity = 3
17572 : // Dst: (FLT_TO_INT_eg:i32 (TRUNC:i32 ?:f32:$src0))
17573 : /*43970*/ 0, /*End of Scope*/
17574 : /*43971*/ /*Scope*/ 102, /*->44074*/
17575 : /*43972*/ OPC_MoveChild, 0,
17576 : /*43974*/ OPC_CheckOpcode, TARGET_VAL(ISD::FFLOOR),
17577 : /*43977*/ OPC_Scope, 71, /*->44050*/ // 2 children in Scope
17578 : /*43979*/ OPC_MoveChild, 0,
17579 : /*43981*/ OPC_CheckOpcode, TARGET_VAL(ISD::FADD),
17580 : /*43984*/ OPC_Scope, 31, /*->44017*/ // 2 children in Scope
17581 : /*43986*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
17582 : /*43987*/ OPC_MoveChild, 1,
17583 : /*43989*/ OPC_CheckOpcode, TARGET_VAL(ISD::ConstantFP),
17584 : /*43992*/ OPC_CheckPredicate, 123, // Predicate_FP_HALF
17585 : /*43994*/ OPC_MoveParent,
17586 : /*43995*/ OPC_MoveParent,
17587 : /*43996*/ OPC_CheckType, MVT::f32,
17588 : /*43998*/ OPC_MoveParent,
17589 : /*43999*/ OPC_CheckPredicate, 124, // Predicate_cvt_rpi_i32_f32
17590 : /*44001*/ OPC_CheckType, MVT::i32,
17591 : /*44003*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
17592 : /*44006*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_RPI_I32_F32_e64), 0,
17593 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 2, 1, 3, 4,
17594 : // Src: (fp_to_sint:i32 (ffloor:f32 (fadd:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (fpimm:f32)<<P:Predicate_FP_HALF>>)))<<P:Predicate_cvt_rpi_i32_f32>> - Complexity = -971
17595 : // Dst: (V_CVT_RPI_I32_F32_e64:i32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
17596 : /*44017*/ /*Scope*/ 31, /*->44049*/
17597 : /*44018*/ OPC_MoveChild, 0,
17598 : /*44020*/ OPC_CheckOpcode, TARGET_VAL(ISD::ConstantFP),
17599 : /*44023*/ OPC_CheckPredicate, 123, // Predicate_FP_HALF
17600 : /*44025*/ OPC_MoveParent,
17601 : /*44026*/ OPC_RecordChild1, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
17602 : /*44027*/ OPC_MoveParent,
17603 : /*44028*/ OPC_CheckType, MVT::f32,
17604 : /*44030*/ OPC_MoveParent,
17605 : /*44031*/ OPC_CheckPredicate, 124, // Predicate_cvt_rpi_i32_f32
17606 : /*44033*/ OPC_CheckType, MVT::i32,
17607 : /*44035*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
17608 : /*44038*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_RPI_I32_F32_e64), 0,
17609 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 2, 1, 3, 4,
17610 : // Src: (fp_to_sint:i32 (ffloor:f32 (fadd:f32 (fpimm:f32)<<P:Predicate_FP_HALF>>, (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod))))<<P:Predicate_cvt_rpi_i32_f32>> - Complexity = -971
17611 : // Dst: (V_CVT_RPI_I32_F32_e64:i32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
17612 : /*44049*/ 0, /*End of Scope*/
17613 : /*44050*/ /*Scope*/ 22, /*->44073*/
17614 : /*44051*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
17615 : /*44052*/ OPC_CheckType, MVT::f32,
17616 : /*44054*/ OPC_MoveParent,
17617 : /*44055*/ OPC_CheckPredicate, 125, // Predicate_cvt_flr_i32_f32
17618 : /*44057*/ OPC_CheckType, MVT::i32,
17619 : /*44059*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
17620 : /*44062*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_FLR_I32_F32_e64), 0,
17621 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 2, 1, 3, 4,
17622 : // Src: (fp_to_sint:i32 (ffloor:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)))<<P:Predicate_cvt_flr_i32_f32>> - Complexity = -978
17623 : // Dst: (V_CVT_FLR_I32_F32_e64:i32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
17624 : /*44073*/ 0, /*End of Scope*/
17625 : /*44074*/ /*Scope*/ 39, /*->44114*/
17626 : /*44075*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
17627 : /*44076*/ OPC_CheckType, MVT::i32,
17628 : /*44078*/ OPC_Scope, 16, /*->44096*/ // 2 children in Scope
17629 : /*44080*/ OPC_CheckChild0Type, MVT::f64,
17630 : /*44082*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
17631 : /*44085*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_I32_F64_e64), 0,
17632 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 2, 1, 3, 4,
17633 : // Src: (fp_to_sint:i32 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
17634 : // Dst: (V_CVT_I32_F64_e64:i32 i32:i32:$src0_modifiers, f64:f64:$src0, i1:i1:$clamp, i32:i32:$omod)
17635 : /*44096*/ /*Scope*/ 16, /*->44113*/
17636 : /*44097*/ OPC_CheckChild0Type, MVT::f32,
17637 : /*44099*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
17638 : /*44102*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_I32_F32_e64), 0,
17639 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 2, 1, 3, 4,
17640 : // Src: (fp_to_sint:i32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
17641 : // Dst: (V_CVT_I32_F32_e64:i32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
17642 : /*44113*/ 0, /*End of Scope*/
17643 : /*44114*/ 0, /*End of Scope*/
17644 : /*44115*/ /*SwitchOpcode*/ 117|128,1/*245*/, TARGET_VAL(ISD::FP_TO_UINT),// ->44364
17645 : /*44119*/ OPC_RecordChild0, // #0 = $src0
17646 : /*44120*/ OPC_CheckType, MVT::i32,
17647 : /*44122*/ OPC_Scope, 93|128,1/*221*/, /*->44346*/ // 2 children in Scope
17648 : /*44125*/ OPC_CheckChild0Type, MVT::f32,
17649 : /*44127*/ OPC_Scope, 67, /*->44196*/ // 3 children in Scope
17650 : /*44129*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
17651 : /*44131*/ OPC_EmitInteger, MVT::i32, 1,
17652 : /*44134*/ OPC_EmitInteger, MVT::i32, 0,
17653 : /*44137*/ OPC_EmitInteger, MVT::i32, 0,
17654 : /*44140*/ OPC_EmitInteger, MVT::i32, 0,
17655 : /*44143*/ OPC_EmitInteger, MVT::i32, 0,
17656 : /*44146*/ OPC_EmitInteger, MVT::i32, 0,
17657 : /*44149*/ OPC_EmitInteger, MVT::i32, 0,
17658 : /*44152*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17659 : /*44164*/ OPC_EmitInteger, MVT::i32, 1,
17660 : /*44167*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17661 : /*44170*/ OPC_EmitInteger, MVT::i32, 0,
17662 : /*44173*/ OPC_EmitInteger, MVT::i32, 0,
17663 : /*44176*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLT_TO_UINT_r600), 0,
17664 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
17665 : // Src: (fp_to_uint:i32 R600_Reg32:f32:$src0) - Complexity = 3
17666 : // Dst: (FLT_TO_UINT_r600:i32 R600_Reg32:f32:$src0)
17667 : /*44196*/ /*Scope*/ 4|128,1/*132*/, /*->44330*/
17668 : /*44198*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
17669 : /*44200*/ OPC_EmitInteger, MVT::i32, 1,
17670 : /*44203*/ OPC_EmitInteger, MVT::i32, 0,
17671 : /*44206*/ OPC_EmitInteger, MVT::i32, 0,
17672 : /*44209*/ OPC_EmitInteger, MVT::i32, 0,
17673 : /*44212*/ OPC_EmitInteger, MVT::i32, 1,
17674 : /*44215*/ OPC_EmitInteger, MVT::i32, 0,
17675 : /*44218*/ OPC_EmitInteger, MVT::i32, 0,
17676 : /*44221*/ OPC_EmitInteger, MVT::i32, 0,
17677 : /*44224*/ OPC_EmitInteger, MVT::i32, 0,
17678 : /*44227*/ OPC_EmitInteger, MVT::i32, 0,
17679 : /*44230*/ OPC_EmitInteger, MVT::i32, 0,
17680 : /*44233*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17681 : /*44245*/ OPC_EmitInteger, MVT::i32, 1,
17682 : /*44248*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17683 : /*44251*/ OPC_EmitInteger, MVT::i32, 0,
17684 : /*44254*/ OPC_EmitInteger, MVT::i32, 0,
17685 : /*44257*/ OPC_EmitNode, TARGET_VAL(AMDGPU::TRUNC), 0,
17686 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 5, 6, 7, 8, 0, 9, 10, 11, 12, 13, 14, 15, 16, // Results = #17
17687 : /*44277*/ OPC_EmitInteger, MVT::i32, 0,
17688 : /*44280*/ OPC_EmitInteger, MVT::i32, 0,
17689 : /*44283*/ OPC_EmitInteger, MVT::i32, 0,
17690 : /*44286*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17691 : /*44298*/ OPC_EmitInteger, MVT::i32, 1,
17692 : /*44301*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17693 : /*44304*/ OPC_EmitInteger, MVT::i32, 0,
17694 : /*44307*/ OPC_EmitInteger, MVT::i32, 0,
17695 : /*44310*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLT_TO_UINT_eg), 0,
17696 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 1, 2, 3, 4, 17, 18, 19, 20, 21, 22, 23, 24, 25,
17697 : // Src: (fp_to_uint:i32 f32:f32:$src0) - Complexity = 3
17698 : // Dst: (FLT_TO_UINT_eg:i32 (TRUNC:i32 ?:f32:$src0))
17699 : /*44330*/ /*Scope*/ 14, /*->44345*/
17700 : /*44331*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
17701 : /*44334*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_U32_F32_e64), 0,
17702 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 2, 1, 3, 4,
17703 : // Src: (fp_to_uint:i32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
17704 : // Dst: (V_CVT_U32_F32_e64:i32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
17705 : /*44345*/ 0, /*End of Scope*/
17706 : /*44346*/ /*Scope*/ 16, /*->44363*/
17707 : /*44347*/ OPC_CheckChild0Type, MVT::f64,
17708 : /*44349*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
17709 : /*44352*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_U32_F64_e64), 0,
17710 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 2, 1, 3, 4,
17711 : // Src: (fp_to_uint:i32 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
17712 : // Dst: (V_CVT_U32_F64_e64:i32 i32:i32:$src0_modifiers, f64:f64:$src0, i1:i1:$clamp, i32:i32:$omod)
17713 : /*44363*/ 0, /*End of Scope*/
17714 : /*44364*/ /*SwitchOpcode*/ 68|128,2/*324*/, TARGET_VAL(ISD::MULHS),// ->44692
17715 : /*44368*/ OPC_RecordChild0, // #0 = $src0
17716 : /*44369*/ OPC_RecordChild1, // #1 = $src1
17717 : /*44370*/ OPC_CheckType, MVT::i32,
17718 : /*44372*/ OPC_Scope, 101, /*->44475*/ // 4 children in Scope
17719 : /*44374*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
17720 : /*44376*/ OPC_EmitInteger, MVT::i32, 0,
17721 : /*44379*/ OPC_EmitInteger, MVT::i32, 0,
17722 : /*44382*/ OPC_EmitInteger, MVT::i32, 1,
17723 : /*44385*/ OPC_EmitInteger, MVT::i32, 0,
17724 : /*44388*/ OPC_EmitInteger, MVT::i32, 0,
17725 : /*44391*/ OPC_EmitInteger, MVT::i32, 0,
17726 : /*44394*/ OPC_EmitInteger, MVT::i32, 0,
17727 : /*44397*/ OPC_EmitInteger, MVT::i32, 0,
17728 : /*44400*/ OPC_EmitInteger, MVT::i32, 0,
17729 : /*44403*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17730 : /*44415*/ OPC_EmitInteger, MVT::i32, 0,
17731 : /*44418*/ OPC_EmitInteger, MVT::i32, 0,
17732 : /*44421*/ OPC_EmitInteger, MVT::i32, 0,
17733 : /*44424*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17734 : /*44436*/ OPC_EmitInteger, MVT::i32, 1,
17735 : /*44439*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17736 : /*44442*/ OPC_EmitInteger, MVT::i32, 0,
17737 : /*44445*/ OPC_EmitInteger, MVT::i32, 0,
17738 : /*44448*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULHI_INT_r600), 0,
17739 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17740 : // Src: (mulhs:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17741 : // Dst: (MULHI_INT_r600:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17742 : /*44475*/ /*Scope*/ 101, /*->44577*/
17743 : /*44476*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
17744 : /*44478*/ OPC_EmitInteger, MVT::i32, 0,
17745 : /*44481*/ OPC_EmitInteger, MVT::i32, 0,
17746 : /*44484*/ OPC_EmitInteger, MVT::i32, 1,
17747 : /*44487*/ OPC_EmitInteger, MVT::i32, 0,
17748 : /*44490*/ OPC_EmitInteger, MVT::i32, 0,
17749 : /*44493*/ OPC_EmitInteger, MVT::i32, 0,
17750 : /*44496*/ OPC_EmitInteger, MVT::i32, 0,
17751 : /*44499*/ OPC_EmitInteger, MVT::i32, 0,
17752 : /*44502*/ OPC_EmitInteger, MVT::i32, 0,
17753 : /*44505*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17754 : /*44517*/ OPC_EmitInteger, MVT::i32, 0,
17755 : /*44520*/ OPC_EmitInteger, MVT::i32, 0,
17756 : /*44523*/ OPC_EmitInteger, MVT::i32, 0,
17757 : /*44526*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17758 : /*44538*/ OPC_EmitInteger, MVT::i32, 1,
17759 : /*44541*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17760 : /*44544*/ OPC_EmitInteger, MVT::i32, 0,
17761 : /*44547*/ OPC_EmitInteger, MVT::i32, 0,
17762 : /*44550*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULHI_INT_eg), 0,
17763 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17764 : // Src: (mulhs:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17765 : // Dst: (MULHI_INT_eg:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17766 : /*44577*/ /*Scope*/ 101, /*->44679*/
17767 : /*44578*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
17768 : /*44580*/ OPC_EmitInteger, MVT::i32, 0,
17769 : /*44583*/ OPC_EmitInteger, MVT::i32, 0,
17770 : /*44586*/ OPC_EmitInteger, MVT::i32, 1,
17771 : /*44589*/ OPC_EmitInteger, MVT::i32, 0,
17772 : /*44592*/ OPC_EmitInteger, MVT::i32, 0,
17773 : /*44595*/ OPC_EmitInteger, MVT::i32, 0,
17774 : /*44598*/ OPC_EmitInteger, MVT::i32, 0,
17775 : /*44601*/ OPC_EmitInteger, MVT::i32, 0,
17776 : /*44604*/ OPC_EmitInteger, MVT::i32, 0,
17777 : /*44607*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17778 : /*44619*/ OPC_EmitInteger, MVT::i32, 0,
17779 : /*44622*/ OPC_EmitInteger, MVT::i32, 0,
17780 : /*44625*/ OPC_EmitInteger, MVT::i32, 0,
17781 : /*44628*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17782 : /*44640*/ OPC_EmitInteger, MVT::i32, 1,
17783 : /*44643*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17784 : /*44646*/ OPC_EmitInteger, MVT::i32, 0,
17785 : /*44649*/ OPC_EmitInteger, MVT::i32, 0,
17786 : /*44652*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULHI_INT_cm), 0,
17787 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17788 : // Src: (mulhs:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17789 : // Dst: (MULHI_INT_cm:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17790 : /*44679*/ /*Scope*/ 11, /*->44691*/
17791 : /*44680*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17792 : /*44682*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MUL_HI_I32), 0,
17793 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
17794 : // Src: (mulhs:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
17795 : // Dst: (V_MUL_HI_I32:i32 ?:i32:$src0, ?:i32:$src1)
17796 : /*44691*/ 0, /*End of Scope*/
17797 : /*44692*/ /*SwitchOpcode*/ 68|128,2/*324*/, TARGET_VAL(ISD::MULHU),// ->45020
17798 : /*44696*/ OPC_RecordChild0, // #0 = $src0
17799 : /*44697*/ OPC_RecordChild1, // #1 = $src1
17800 : /*44698*/ OPC_CheckType, MVT::i32,
17801 : /*44700*/ OPC_Scope, 101, /*->44803*/ // 4 children in Scope
17802 : /*44702*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
17803 : /*44704*/ OPC_EmitInteger, MVT::i32, 0,
17804 : /*44707*/ OPC_EmitInteger, MVT::i32, 0,
17805 : /*44710*/ OPC_EmitInteger, MVT::i32, 1,
17806 : /*44713*/ OPC_EmitInteger, MVT::i32, 0,
17807 : /*44716*/ OPC_EmitInteger, MVT::i32, 0,
17808 : /*44719*/ OPC_EmitInteger, MVT::i32, 0,
17809 : /*44722*/ OPC_EmitInteger, MVT::i32, 0,
17810 : /*44725*/ OPC_EmitInteger, MVT::i32, 0,
17811 : /*44728*/ OPC_EmitInteger, MVT::i32, 0,
17812 : /*44731*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17813 : /*44743*/ OPC_EmitInteger, MVT::i32, 0,
17814 : /*44746*/ OPC_EmitInteger, MVT::i32, 0,
17815 : /*44749*/ OPC_EmitInteger, MVT::i32, 0,
17816 : /*44752*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17817 : /*44764*/ OPC_EmitInteger, MVT::i32, 1,
17818 : /*44767*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17819 : /*44770*/ OPC_EmitInteger, MVT::i32, 0,
17820 : /*44773*/ OPC_EmitInteger, MVT::i32, 0,
17821 : /*44776*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULHI_UINT_r600), 0,
17822 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17823 : // Src: (mulhu:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17824 : // Dst: (MULHI_UINT_r600:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17825 : /*44803*/ /*Scope*/ 101, /*->44905*/
17826 : /*44804*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
17827 : /*44806*/ OPC_EmitInteger, MVT::i32, 0,
17828 : /*44809*/ OPC_EmitInteger, MVT::i32, 0,
17829 : /*44812*/ OPC_EmitInteger, MVT::i32, 1,
17830 : /*44815*/ OPC_EmitInteger, MVT::i32, 0,
17831 : /*44818*/ OPC_EmitInteger, MVT::i32, 0,
17832 : /*44821*/ OPC_EmitInteger, MVT::i32, 0,
17833 : /*44824*/ OPC_EmitInteger, MVT::i32, 0,
17834 : /*44827*/ OPC_EmitInteger, MVT::i32, 0,
17835 : /*44830*/ OPC_EmitInteger, MVT::i32, 0,
17836 : /*44833*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17837 : /*44845*/ OPC_EmitInteger, MVT::i32, 0,
17838 : /*44848*/ OPC_EmitInteger, MVT::i32, 0,
17839 : /*44851*/ OPC_EmitInteger, MVT::i32, 0,
17840 : /*44854*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17841 : /*44866*/ OPC_EmitInteger, MVT::i32, 1,
17842 : /*44869*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17843 : /*44872*/ OPC_EmitInteger, MVT::i32, 0,
17844 : /*44875*/ OPC_EmitInteger, MVT::i32, 0,
17845 : /*44878*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULHI_UINT_eg), 0,
17846 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17847 : // Src: (mulhu:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17848 : // Dst: (MULHI_UINT_eg:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17849 : /*44905*/ /*Scope*/ 101, /*->45007*/
17850 : /*44906*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
17851 : /*44908*/ OPC_EmitInteger, MVT::i32, 0,
17852 : /*44911*/ OPC_EmitInteger, MVT::i32, 0,
17853 : /*44914*/ OPC_EmitInteger, MVT::i32, 1,
17854 : /*44917*/ OPC_EmitInteger, MVT::i32, 0,
17855 : /*44920*/ OPC_EmitInteger, MVT::i32, 0,
17856 : /*44923*/ OPC_EmitInteger, MVT::i32, 0,
17857 : /*44926*/ OPC_EmitInteger, MVT::i32, 0,
17858 : /*44929*/ OPC_EmitInteger, MVT::i32, 0,
17859 : /*44932*/ OPC_EmitInteger, MVT::i32, 0,
17860 : /*44935*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17861 : /*44947*/ OPC_EmitInteger, MVT::i32, 0,
17862 : /*44950*/ OPC_EmitInteger, MVT::i32, 0,
17863 : /*44953*/ OPC_EmitInteger, MVT::i32, 0,
17864 : /*44956*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17865 : /*44968*/ OPC_EmitInteger, MVT::i32, 1,
17866 : /*44971*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17867 : /*44974*/ OPC_EmitInteger, MVT::i32, 0,
17868 : /*44977*/ OPC_EmitInteger, MVT::i32, 0,
17869 : /*44980*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULHI_UINT_cm), 0,
17870 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
17871 : // Src: (mulhu:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
17872 : // Dst: (MULHI_UINT_cm:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
17873 : /*45007*/ /*Scope*/ 11, /*->45019*/
17874 : /*45008*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17875 : /*45010*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MUL_HI_U32), 0,
17876 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
17877 : // Src: (mulhu:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
17878 : // Dst: (V_MUL_HI_U32:i32 ?:i32:$src0, ?:i32:$src1)
17879 : /*45019*/ 0, /*End of Scope*/
17880 : /*45020*/ /*SwitchOpcode*/ 113|128,3/*497*/, TARGET_VAL(AMDGPUISD::URECIP),// ->45521
17881 : /*45024*/ OPC_RecordChild0, // #0 = $src0
17882 : /*45025*/ OPC_CheckType, MVT::i32,
17883 : /*45027*/ OPC_Scope, 67, /*->45096*/ // 4 children in Scope
17884 : /*45029*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
17885 : /*45031*/ OPC_EmitInteger, MVT::i32, 1,
17886 : /*45034*/ OPC_EmitInteger, MVT::i32, 0,
17887 : /*45037*/ OPC_EmitInteger, MVT::i32, 0,
17888 : /*45040*/ OPC_EmitInteger, MVT::i32, 0,
17889 : /*45043*/ OPC_EmitInteger, MVT::i32, 0,
17890 : /*45046*/ OPC_EmitInteger, MVT::i32, 0,
17891 : /*45049*/ OPC_EmitInteger, MVT::i32, 0,
17892 : /*45052*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17893 : /*45064*/ OPC_EmitInteger, MVT::i32, 1,
17894 : /*45067*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17895 : /*45070*/ OPC_EmitInteger, MVT::i32, 0,
17896 : /*45073*/ OPC_EmitInteger, MVT::i32, 0,
17897 : /*45076*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIP_UINT_r600), 0,
17898 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
17899 : // Src: (AMDGPUurecip:i32 R600_Reg32:i32:$src0) - Complexity = 3
17900 : // Dst: (RECIP_UINT_r600:i32 R600_Reg32:i32:$src0)
17901 : /*45096*/ /*Scope*/ 67, /*->45164*/
17902 : /*45097*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
17903 : /*45099*/ OPC_EmitInteger, MVT::i32, 1,
17904 : /*45102*/ OPC_EmitInteger, MVT::i32, 0,
17905 : /*45105*/ OPC_EmitInteger, MVT::i32, 0,
17906 : /*45108*/ OPC_EmitInteger, MVT::i32, 0,
17907 : /*45111*/ OPC_EmitInteger, MVT::i32, 0,
17908 : /*45114*/ OPC_EmitInteger, MVT::i32, 0,
17909 : /*45117*/ OPC_EmitInteger, MVT::i32, 0,
17910 : /*45120*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17911 : /*45132*/ OPC_EmitInteger, MVT::i32, 1,
17912 : /*45135*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17913 : /*45138*/ OPC_EmitInteger, MVT::i32, 0,
17914 : /*45141*/ OPC_EmitInteger, MVT::i32, 0,
17915 : /*45144*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIP_UINT_eg), 0,
17916 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
17917 : // Src: (AMDGPUurecip:i32 R600_Reg32:i32:$src0) - Complexity = 3
17918 : // Dst: (RECIP_UINT_eg:i32 R600_Reg32:i32:$src0)
17919 : /*45164*/ /*Scope*/ 42, /*->45207*/
17920 : /*45165*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
17921 : /*45167*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,0|128,124|128,4/*1333788672*/,
17922 : /*45174*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CVT_F32_U32_e32), 0,
17923 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0, // Results = #2
17924 : /*45182*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_RCP_IFLAG_F32_e32), 0,
17925 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 2, // Results = #3
17926 : /*45190*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MUL_F32_e32), 0,
17927 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 3, // Results = #4
17928 : /*45199*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_U32_F32_e32), 0,
17929 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 4,
17930 : // Src: (AMDGPUurecip:i32 i32:i32:$src0) - Complexity = 3
17931 : // Dst: (V_CVT_U32_F32_e32:i32 (V_MUL_F32_e32:i32 1333788672:i32, (V_RCP_IFLAG_F32_e32:i32 (V_CVT_F32_U32_e32:i32 ?:i32:$src0))))
17932 : /*45207*/ /*Scope*/ 55|128,2/*311*/, /*->45520*/
17933 : /*45209*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
17934 : /*45211*/ OPC_EmitInteger, MVT::i32, 1,
17935 : /*45214*/ OPC_EmitInteger, MVT::i32, 0,
17936 : /*45217*/ OPC_EmitInteger, MVT::i32, 0,
17937 : /*45220*/ OPC_EmitInteger, MVT::i32, 0,
17938 : /*45223*/ OPC_EmitInteger, MVT::i32, 0,
17939 : /*45226*/ OPC_EmitInteger, MVT::i32, 0,
17940 : /*45229*/ OPC_EmitInteger, MVT::i32, 1,
17941 : /*45232*/ OPC_EmitInteger, MVT::i32, 0,
17942 : /*45235*/ OPC_EmitInteger, MVT::i32, 0,
17943 : /*45238*/ OPC_EmitInteger, MVT::i32, 0,
17944 : /*45241*/ OPC_EmitInteger, MVT::i32, 1,
17945 : /*45244*/ OPC_EmitInteger, MVT::i32, 0,
17946 : /*45247*/ OPC_EmitInteger, MVT::i32, 0,
17947 : /*45250*/ OPC_EmitInteger, MVT::i32, 0,
17948 : /*45253*/ OPC_EmitInteger, MVT::i32, 1,
17949 : /*45256*/ OPC_EmitInteger, MVT::i32, 0,
17950 : /*45259*/ OPC_EmitInteger, MVT::i32, 0,
17951 : /*45262*/ OPC_EmitInteger, MVT::i32, 0,
17952 : /*45265*/ OPC_EmitInteger, MVT::i32, 0,
17953 : /*45268*/ OPC_EmitInteger, MVT::i32, 0,
17954 : /*45271*/ OPC_EmitInteger, MVT::i32, 0,
17955 : /*45274*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17956 : /*45286*/ OPC_EmitInteger, MVT::i32, 1,
17957 : /*45289*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17958 : /*45292*/ OPC_EmitInteger, MVT::i32, 0,
17959 : /*45295*/ OPC_EmitInteger, MVT::i32, 0,
17960 : /*45298*/ OPC_EmitNode, TARGET_VAL(AMDGPU::UINT_TO_FLT_eg), 0,
17961 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 15, 16, 17, 18, 0, 19, 20, 21, 22, 23, 24, 25, 26, // Results = #27
17962 : /*45318*/ OPC_EmitInteger, MVT::i32, 0,
17963 : /*45321*/ OPC_EmitInteger, MVT::i32, 0,
17964 : /*45324*/ OPC_EmitInteger, MVT::i32, 0,
17965 : /*45327*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17966 : /*45339*/ OPC_EmitInteger, MVT::i32, 1,
17967 : /*45342*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17968 : /*45345*/ OPC_EmitInteger, MVT::i32, 0,
17969 : /*45348*/ OPC_EmitInteger, MVT::i32, 0,
17970 : /*45351*/ OPC_EmitNode, TARGET_VAL(AMDGPU::RECIP_IEEE_cm), 0,
17971 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 11, 12, 13, 14, 27, 28, 29, 30, 31, 32, 33, 34, 35, // Results = #36
17972 : /*45371*/ OPC_EmitInteger, MVT::i32, 0,
17973 : /*45374*/ OPC_EmitInteger, MVT::i32, 0,
17974 : /*45377*/ OPC_EmitInteger, MVT::i32, 0,
17975 : /*45380*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17976 : /*45392*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,0|128,124|128,4/*1333788672*/,
17977 : /*45399*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MOV_IMM_I32), 0,
17978 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 41, // Results = #42
17979 : /*45407*/ OPC_EmitInteger, MVT::i32, 0,
17980 : /*45410*/ OPC_EmitInteger, MVT::i32, 0,
17981 : /*45413*/ OPC_EmitInteger, MVT::i32, 0,
17982 : /*45416*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17983 : /*45428*/ OPC_EmitInteger, MVT::i32, 1,
17984 : /*45431*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17985 : /*45434*/ OPC_EmitInteger, MVT::i32, 0,
17986 : /*45437*/ OPC_EmitInteger, MVT::i32, 0,
17987 : /*45440*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MUL_IEEE), 0,
17988 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 5, 6, 7, 8, 9, 10, 36, 37, 38, 39, 40, 42, 43, 44, 45, 46, 47, 48, 49, 50, // Results = #51
17989 : /*45467*/ OPC_EmitInteger, MVT::i32, 0,
17990 : /*45470*/ OPC_EmitInteger, MVT::i32, 0,
17991 : /*45473*/ OPC_EmitInteger, MVT::i32, 0,
17992 : /*45476*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
17993 : /*45488*/ OPC_EmitInteger, MVT::i32, 1,
17994 : /*45491*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
17995 : /*45494*/ OPC_EmitInteger, MVT::i32, 0,
17996 : /*45497*/ OPC_EmitInteger, MVT::i32, 0,
17997 : /*45500*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLT_TO_UINT_eg), 0,
17998 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 1, 2, 3, 4, 51, 52, 53, 54, 55, 56, 57, 58, 59,
17999 : // Src: (AMDGPUurecip:i32 i32:i32:$src0) - Complexity = 3
18000 : // Dst: (FLT_TO_UINT_eg:i32 (MUL_IEEE:i32 (RECIP_IEEE_cm:i32 (UINT_TO_FLT_eg:i32 ?:i32:$src0)), (MOV_IMM_I32:i32 1333788672:i32)))
18001 : /*45520*/ 0, /*End of Scope*/
18002 : /*45521*/ /*SwitchOpcode*/ 66|128,2/*322*/, TARGET_VAL(AMDGPUISD::MUL_I24),// ->45847
18003 : /*45525*/ OPC_RecordChild0, // #0 = $src0
18004 : /*45526*/ OPC_RecordChild1, // #1 = $src1
18005 : /*45527*/ OPC_CheckType, MVT::i32,
18006 : /*45529*/ OPC_Scope, 101, /*->45632*/ // 4 children in Scope
18007 : /*45531*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
18008 : /*45533*/ OPC_EmitInteger, MVT::i32, 0,
18009 : /*45536*/ OPC_EmitInteger, MVT::i32, 0,
18010 : /*45539*/ OPC_EmitInteger, MVT::i32, 1,
18011 : /*45542*/ OPC_EmitInteger, MVT::i32, 0,
18012 : /*45545*/ OPC_EmitInteger, MVT::i32, 0,
18013 : /*45548*/ OPC_EmitInteger, MVT::i32, 0,
18014 : /*45551*/ OPC_EmitInteger, MVT::i32, 0,
18015 : /*45554*/ OPC_EmitInteger, MVT::i32, 0,
18016 : /*45557*/ OPC_EmitInteger, MVT::i32, 0,
18017 : /*45560*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18018 : /*45572*/ OPC_EmitInteger, MVT::i32, 0,
18019 : /*45575*/ OPC_EmitInteger, MVT::i32, 0,
18020 : /*45578*/ OPC_EmitInteger, MVT::i32, 0,
18021 : /*45581*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18022 : /*45593*/ OPC_EmitInteger, MVT::i32, 1,
18023 : /*45596*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18024 : /*45599*/ OPC_EmitInteger, MVT::i32, 0,
18025 : /*45602*/ OPC_EmitInteger, MVT::i32, 0,
18026 : /*45605*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULLO_INT_r600), 0,
18027 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
18028 : // Src: (AMDGPUmul_i24:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
18029 : // Dst: (MULLO_INT_r600:i32 ?:i32:$src0, ?:i32:$src1)
18030 : /*45632*/ /*Scope*/ 101, /*->45734*/
18031 : /*45633*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
18032 : /*45635*/ OPC_EmitInteger, MVT::i32, 0,
18033 : /*45638*/ OPC_EmitInteger, MVT::i32, 0,
18034 : /*45641*/ OPC_EmitInteger, MVT::i32, 1,
18035 : /*45644*/ OPC_EmitInteger, MVT::i32, 0,
18036 : /*45647*/ OPC_EmitInteger, MVT::i32, 0,
18037 : /*45650*/ OPC_EmitInteger, MVT::i32, 0,
18038 : /*45653*/ OPC_EmitInteger, MVT::i32, 0,
18039 : /*45656*/ OPC_EmitInteger, MVT::i32, 0,
18040 : /*45659*/ OPC_EmitInteger, MVT::i32, 0,
18041 : /*45662*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18042 : /*45674*/ OPC_EmitInteger, MVT::i32, 0,
18043 : /*45677*/ OPC_EmitInteger, MVT::i32, 0,
18044 : /*45680*/ OPC_EmitInteger, MVT::i32, 0,
18045 : /*45683*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18046 : /*45695*/ OPC_EmitInteger, MVT::i32, 1,
18047 : /*45698*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18048 : /*45701*/ OPC_EmitInteger, MVT::i32, 0,
18049 : /*45704*/ OPC_EmitInteger, MVT::i32, 0,
18050 : /*45707*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULLO_INT_eg), 0,
18051 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
18052 : // Src: (AMDGPUmul_i24:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
18053 : // Dst: (MULLO_INT_eg:i32 ?:i32:$src0, ?:i32:$src1)
18054 : /*45734*/ /*Scope*/ 101, /*->45836*/
18055 : /*45735*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
18056 : /*45737*/ OPC_EmitInteger, MVT::i32, 0,
18057 : /*45740*/ OPC_EmitInteger, MVT::i32, 0,
18058 : /*45743*/ OPC_EmitInteger, MVT::i32, 1,
18059 : /*45746*/ OPC_EmitInteger, MVT::i32, 0,
18060 : /*45749*/ OPC_EmitInteger, MVT::i32, 0,
18061 : /*45752*/ OPC_EmitInteger, MVT::i32, 0,
18062 : /*45755*/ OPC_EmitInteger, MVT::i32, 0,
18063 : /*45758*/ OPC_EmitInteger, MVT::i32, 0,
18064 : /*45761*/ OPC_EmitInteger, MVT::i32, 0,
18065 : /*45764*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18066 : /*45776*/ OPC_EmitInteger, MVT::i32, 0,
18067 : /*45779*/ OPC_EmitInteger, MVT::i32, 0,
18068 : /*45782*/ OPC_EmitInteger, MVT::i32, 0,
18069 : /*45785*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18070 : /*45797*/ OPC_EmitInteger, MVT::i32, 1,
18071 : /*45800*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18072 : /*45803*/ OPC_EmitInteger, MVT::i32, 0,
18073 : /*45806*/ OPC_EmitInteger, MVT::i32, 0,
18074 : /*45809*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL_INT24_cm), 0,
18075 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
18076 : // Src: (AMDGPUmul_i24:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
18077 : // Dst: (MUL_INT24_cm:i32 i32:i32:$src0, i32:i32:$src1)
18078 : /*45836*/ /*Scope*/ 9, /*->45846*/
18079 : /*45837*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MUL_I32_I24_e64), 0,
18080 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
18081 : // Src: (AMDGPUmul_i24:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = -997
18082 : // Dst: (V_MUL_I32_I24_e64:i32 i32:i32:$src0, i32:i32:$src1)
18083 : /*45846*/ 0, /*End of Scope*/
18084 : /*45847*/ /*SwitchOpcode*/ 66|128,2/*322*/, TARGET_VAL(AMDGPUISD::MUL_U24),// ->46173
18085 : /*45851*/ OPC_RecordChild0, // #0 = $src0
18086 : /*45852*/ OPC_RecordChild1, // #1 = $src1
18087 : /*45853*/ OPC_CheckType, MVT::i32,
18088 : /*45855*/ OPC_Scope, 101, /*->45958*/ // 4 children in Scope
18089 : /*45857*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
18090 : /*45859*/ OPC_EmitInteger, MVT::i32, 0,
18091 : /*45862*/ OPC_EmitInteger, MVT::i32, 0,
18092 : /*45865*/ OPC_EmitInteger, MVT::i32, 1,
18093 : /*45868*/ OPC_EmitInteger, MVT::i32, 0,
18094 : /*45871*/ OPC_EmitInteger, MVT::i32, 0,
18095 : /*45874*/ OPC_EmitInteger, MVT::i32, 0,
18096 : /*45877*/ OPC_EmitInteger, MVT::i32, 0,
18097 : /*45880*/ OPC_EmitInteger, MVT::i32, 0,
18098 : /*45883*/ OPC_EmitInteger, MVT::i32, 0,
18099 : /*45886*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18100 : /*45898*/ OPC_EmitInteger, MVT::i32, 0,
18101 : /*45901*/ OPC_EmitInteger, MVT::i32, 0,
18102 : /*45904*/ OPC_EmitInteger, MVT::i32, 0,
18103 : /*45907*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18104 : /*45919*/ OPC_EmitInteger, MVT::i32, 1,
18105 : /*45922*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18106 : /*45925*/ OPC_EmitInteger, MVT::i32, 0,
18107 : /*45928*/ OPC_EmitInteger, MVT::i32, 0,
18108 : /*45931*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULLO_UINT_r600), 0,
18109 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
18110 : // Src: (AMDGPUmul_u24:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
18111 : // Dst: (MULLO_UINT_r600:i32 ?:i32:$src0, ?:i32:$src1)
18112 : /*45958*/ /*Scope*/ 101, /*->46060*/
18113 : /*45959*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18114 : /*45961*/ OPC_EmitInteger, MVT::i32, 0,
18115 : /*45964*/ OPC_EmitInteger, MVT::i32, 0,
18116 : /*45967*/ OPC_EmitInteger, MVT::i32, 1,
18117 : /*45970*/ OPC_EmitInteger, MVT::i32, 0,
18118 : /*45973*/ OPC_EmitInteger, MVT::i32, 0,
18119 : /*45976*/ OPC_EmitInteger, MVT::i32, 0,
18120 : /*45979*/ OPC_EmitInteger, MVT::i32, 0,
18121 : /*45982*/ OPC_EmitInteger, MVT::i32, 0,
18122 : /*45985*/ OPC_EmitInteger, MVT::i32, 0,
18123 : /*45988*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18124 : /*46000*/ OPC_EmitInteger, MVT::i32, 0,
18125 : /*46003*/ OPC_EmitInteger, MVT::i32, 0,
18126 : /*46006*/ OPC_EmitInteger, MVT::i32, 0,
18127 : /*46009*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18128 : /*46021*/ OPC_EmitInteger, MVT::i32, 1,
18129 : /*46024*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18130 : /*46027*/ OPC_EmitInteger, MVT::i32, 0,
18131 : /*46030*/ OPC_EmitInteger, MVT::i32, 0,
18132 : /*46033*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL_UINT24_eg), 0,
18133 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
18134 : // Src: (AMDGPUmul_u24:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
18135 : // Dst: (MUL_UINT24_eg:i32 i32:i32:$src0, i32:i32:$src1)
18136 : /*46060*/ /*Scope*/ 101, /*->46162*/
18137 : /*46061*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
18138 : /*46063*/ OPC_EmitInteger, MVT::i32, 0,
18139 : /*46066*/ OPC_EmitInteger, MVT::i32, 0,
18140 : /*46069*/ OPC_EmitInteger, MVT::i32, 1,
18141 : /*46072*/ OPC_EmitInteger, MVT::i32, 0,
18142 : /*46075*/ OPC_EmitInteger, MVT::i32, 0,
18143 : /*46078*/ OPC_EmitInteger, MVT::i32, 0,
18144 : /*46081*/ OPC_EmitInteger, MVT::i32, 0,
18145 : /*46084*/ OPC_EmitInteger, MVT::i32, 0,
18146 : /*46087*/ OPC_EmitInteger, MVT::i32, 0,
18147 : /*46090*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18148 : /*46102*/ OPC_EmitInteger, MVT::i32, 0,
18149 : /*46105*/ OPC_EmitInteger, MVT::i32, 0,
18150 : /*46108*/ OPC_EmitInteger, MVT::i32, 0,
18151 : /*46111*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18152 : /*46123*/ OPC_EmitInteger, MVT::i32, 1,
18153 : /*46126*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18154 : /*46129*/ OPC_EmitInteger, MVT::i32, 0,
18155 : /*46132*/ OPC_EmitInteger, MVT::i32, 0,
18156 : /*46135*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULLO_UINT_cm), 0,
18157 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
18158 : // Src: (AMDGPUmul_u24:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
18159 : // Dst: (MULLO_UINT_cm:i32 ?:i32:$src0, ?:i32:$src1)
18160 : /*46162*/ /*Scope*/ 9, /*->46172*/
18161 : /*46163*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MUL_U32_U24_e64), 0,
18162 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
18163 : // Src: (AMDGPUmul_u24:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = -997
18164 : // Dst: (V_MUL_U32_U24_e64:i32 i32:i32:$src0, i32:i32:$src1)
18165 : /*46172*/ 0, /*End of Scope*/
18166 : /*46173*/ /*SwitchOpcode*/ 120, TARGET_VAL(AMDGPUISD::BFE_U32),// ->46296
18167 : /*46176*/ OPC_RecordChild0, // #0 = $src0
18168 : /*46177*/ OPC_RecordChild1, // #1 = $src1
18169 : /*46178*/ OPC_RecordChild2, // #2 = $src2
18170 : /*46179*/ OPC_CheckChild2Type, MVT::i32,
18171 : /*46181*/ OPC_CheckType, MVT::i32,
18172 : /*46183*/ OPC_Scope, 99, /*->46284*/ // 2 children in Scope
18173 : /*46185*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18174 : /*46187*/ OPC_EmitInteger, MVT::i32, 0,
18175 : /*46190*/ OPC_EmitInteger, MVT::i32, 0,
18176 : /*46193*/ OPC_EmitInteger, MVT::i32, 0,
18177 : /*46196*/ OPC_EmitInteger, MVT::i32, 0,
18178 : /*46199*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18179 : /*46211*/ OPC_EmitInteger, MVT::i32, 0,
18180 : /*46214*/ OPC_EmitInteger, MVT::i32, 0,
18181 : /*46217*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18182 : /*46229*/ OPC_EmitInteger, MVT::i32, 0,
18183 : /*46232*/ OPC_EmitInteger, MVT::i32, 0,
18184 : /*46235*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18185 : /*46247*/ OPC_EmitInteger, MVT::i32, 1,
18186 : /*46250*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18187 : /*46253*/ OPC_EmitInteger, MVT::i32, 0,
18188 : /*46256*/ OPC_EmitInteger, MVT::i32, 0,
18189 : /*46259*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFE_UINT_eg), 0,
18190 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
18191 : // Src: (AMDGPUbfe_u32:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = 3
18192 : // Dst: (BFE_UINT_eg:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
18193 : /*46284*/ /*Scope*/ 10, /*->46295*/
18194 : /*46285*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFE_U32), 0,
18195 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
18196 : // Src: (AMDGPUbfe_u32:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = -997
18197 : // Dst: (V_BFE_U32:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
18198 : /*46295*/ 0, /*End of Scope*/
18199 : /*46296*/ /*SwitchOpcode*/ 120, TARGET_VAL(AMDGPUISD::BFE_I32),// ->46419
18200 : /*46299*/ OPC_RecordChild0, // #0 = $src0
18201 : /*46300*/ OPC_RecordChild1, // #1 = $src1
18202 : /*46301*/ OPC_RecordChild2, // #2 = $src2
18203 : /*46302*/ OPC_CheckChild2Type, MVT::i32,
18204 : /*46304*/ OPC_CheckType, MVT::i32,
18205 : /*46306*/ OPC_Scope, 99, /*->46407*/ // 2 children in Scope
18206 : /*46308*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18207 : /*46310*/ OPC_EmitInteger, MVT::i32, 0,
18208 : /*46313*/ OPC_EmitInteger, MVT::i32, 0,
18209 : /*46316*/ OPC_EmitInteger, MVT::i32, 0,
18210 : /*46319*/ OPC_EmitInteger, MVT::i32, 0,
18211 : /*46322*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18212 : /*46334*/ OPC_EmitInteger, MVT::i32, 0,
18213 : /*46337*/ OPC_EmitInteger, MVT::i32, 0,
18214 : /*46340*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18215 : /*46352*/ OPC_EmitInteger, MVT::i32, 0,
18216 : /*46355*/ OPC_EmitInteger, MVT::i32, 0,
18217 : /*46358*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18218 : /*46370*/ OPC_EmitInteger, MVT::i32, 1,
18219 : /*46373*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18220 : /*46376*/ OPC_EmitInteger, MVT::i32, 0,
18221 : /*46379*/ OPC_EmitInteger, MVT::i32, 0,
18222 : /*46382*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFE_INT_eg), 0,
18223 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
18224 : // Src: (AMDGPUbfe_i32:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = 3
18225 : // Dst: (BFE_INT_eg:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
18226 : /*46407*/ /*Scope*/ 10, /*->46418*/
18227 : /*46408*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFE_I32), 0,
18228 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
18229 : // Src: (AMDGPUbfe_i32:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = -997
18230 : // Dst: (V_BFE_I32:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
18231 : /*46418*/ 0, /*End of Scope*/
18232 : /*46419*/ /*SwitchOpcode*/ 120, TARGET_VAL(AMDGPUISD::BFI),// ->46542
18233 : /*46422*/ OPC_RecordChild0, // #0 = $src0
18234 : /*46423*/ OPC_RecordChild1, // #1 = $src1
18235 : /*46424*/ OPC_RecordChild2, // #2 = $src2
18236 : /*46425*/ OPC_CheckChild2Type, MVT::i32,
18237 : /*46427*/ OPC_CheckType, MVT::i32,
18238 : /*46429*/ OPC_Scope, 99, /*->46530*/ // 2 children in Scope
18239 : /*46431*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18240 : /*46433*/ OPC_EmitInteger, MVT::i32, 0,
18241 : /*46436*/ OPC_EmitInteger, MVT::i32, 0,
18242 : /*46439*/ OPC_EmitInteger, MVT::i32, 0,
18243 : /*46442*/ OPC_EmitInteger, MVT::i32, 0,
18244 : /*46445*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18245 : /*46457*/ OPC_EmitInteger, MVT::i32, 0,
18246 : /*46460*/ OPC_EmitInteger, MVT::i32, 0,
18247 : /*46463*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18248 : /*46475*/ OPC_EmitInteger, MVT::i32, 0,
18249 : /*46478*/ OPC_EmitInteger, MVT::i32, 0,
18250 : /*46481*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18251 : /*46493*/ OPC_EmitInteger, MVT::i32, 1,
18252 : /*46496*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18253 : /*46499*/ OPC_EmitInteger, MVT::i32, 0,
18254 : /*46502*/ OPC_EmitInteger, MVT::i32, 0,
18255 : /*46505*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
18256 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
18257 : // Src: (AMDGPUbfi:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = 3
18258 : // Dst: (BFI_INT_eg:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
18259 : /*46530*/ /*Scope*/ 10, /*->46541*/
18260 : /*46531*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
18261 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
18262 : // Src: (AMDGPUbfi:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = -997
18263 : // Dst: (V_BFI_B32:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
18264 : /*46541*/ 0, /*End of Scope*/
18265 : /*46542*/ /*SwitchOpcode*/ 102|128,3/*486*/, TARGET_VAL(ISD::SIGN_EXTEND_INREG),// ->47032
18266 : /*46546*/ OPC_RecordChild0, // #0 = $src
18267 : /*46547*/ OPC_MoveChild, 1,
18268 : /*46549*/ OPC_Scope, 22|128,1/*150*/, /*->46702*/ // 4 children in Scope
18269 : /*46552*/ OPC_CheckValueType, MVT::i1,
18270 : /*46554*/ OPC_MoveParent,
18271 : /*46555*/ OPC_SwitchType /*2 cases */, 125, MVT::i32,// ->46683
18272 : /*46558*/ OPC_Scope, 105, /*->46665*/ // 2 children in Scope
18273 : /*46560*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18274 : /*46562*/ OPC_EmitInteger, MVT::i32, 0,
18275 : /*46565*/ OPC_EmitInteger, MVT::i32, 0,
18276 : /*46568*/ OPC_EmitInteger, MVT::i32, 0,
18277 : /*46571*/ OPC_EmitInteger, MVT::i32, 0,
18278 : /*46574*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18279 : /*46586*/ OPC_EmitRegister, MVT::i32, AMDGPU::ZERO,
18280 : /*46589*/ OPC_EmitInteger, MVT::i32, 0,
18281 : /*46592*/ OPC_EmitInteger, MVT::i32, 0,
18282 : /*46595*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18283 : /*46607*/ OPC_EmitRegister, MVT::i32, AMDGPU::ONE_INT,
18284 : /*46610*/ OPC_EmitInteger, MVT::i32, 0,
18285 : /*46613*/ OPC_EmitInteger, MVT::i32, 0,
18286 : /*46616*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18287 : /*46628*/ OPC_EmitInteger, MVT::i32, 1,
18288 : /*46631*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18289 : /*46634*/ OPC_EmitInteger, MVT::i32, 0,
18290 : /*46637*/ OPC_EmitInteger, MVT::i32, 0,
18291 : /*46640*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFE_INT_eg), 0,
18292 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 1, 2, 0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
18293 : // Src: (sext_inreg:i32 i32:i32:$src, i1:Other) - Complexity = 3
18294 : // Dst: (BFE_INT_eg:i32 i32:i32:$src, ZERO:i32, ONE_INT:i32)
18295 : /*46665*/ /*Scope*/ 16, /*->46682*/
18296 : /*46666*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18297 : /*46668*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,4/*65536*/,
18298 : /*46673*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BFE_I32), 0,
18299 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
18300 : // Src: (sext_inreg:i32 i32:i32:$src, i1:Other) - Complexity = 3
18301 : // Dst: (S_BFE_I32:i32 i32:i32:$src, 65536:i32)
18302 : /*46682*/ 0, /*End of Scope*/
18303 : /*46683*/ /*SwitchType*/ 16, MVT::i64,// ->46701
18304 : /*46685*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18305 : /*46687*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,4/*65536*/,
18306 : /*46692*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BFE_I64), 0,
18307 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 0, 1,
18308 : // Src: (sext_inreg:i64 i64:i64:$src, i1:Other) - Complexity = 3
18309 : // Dst: (S_BFE_I64:i64 i64:i64:$src, 65536:i32)
18310 : /*46701*/ 0, // EndSwitchType
18311 : /*46702*/ /*Scope*/ 24|128,1/*152*/, /*->46856*/
18312 : /*46704*/ OPC_CheckValueType, MVT::i8,
18313 : /*46706*/ OPC_MoveParent,
18314 : /*46707*/ OPC_SwitchType /*2 cases */, 127, MVT::i32,// ->46837
18315 : /*46710*/ OPC_Scope, 10, /*->46722*/ // 2 children in Scope
18316 : /*46712*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
18317 : /*46714*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_SEXT_I32_I8), 0,
18318 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0,
18319 : // Src: (sext_inreg:i32 i32:i32:$src0, i8:Other) - Complexity = 3
18320 : // Dst: (S_SEXT_I32_I8:i32 i32:i32:$src0)
18321 : /*46722*/ /*Scope*/ 113, /*->46836*/
18322 : /*46723*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18323 : /*46725*/ OPC_EmitInteger, MVT::i32, 0,
18324 : /*46728*/ OPC_EmitInteger, MVT::i32, 0,
18325 : /*46731*/ OPC_EmitInteger, MVT::i32, 0,
18326 : /*46734*/ OPC_EmitInteger, MVT::i32, 0,
18327 : /*46737*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18328 : /*46749*/ OPC_EmitRegister, MVT::i32, AMDGPU::ZERO,
18329 : /*46752*/ OPC_EmitInteger, MVT::i32, 0,
18330 : /*46755*/ OPC_EmitInteger, MVT::i32, 0,
18331 : /*46758*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18332 : /*46770*/ OPC_EmitInteger, MVT::i32, 8,
18333 : /*46773*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MOV_IMM_I32), 0,
18334 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 10, // Results = #11
18335 : /*46781*/ OPC_EmitInteger, MVT::i32, 0,
18336 : /*46784*/ OPC_EmitInteger, MVT::i32, 0,
18337 : /*46787*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18338 : /*46799*/ OPC_EmitInteger, MVT::i32, 1,
18339 : /*46802*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18340 : /*46805*/ OPC_EmitInteger, MVT::i32, 0,
18341 : /*46808*/ OPC_EmitInteger, MVT::i32, 0,
18342 : /*46811*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFE_INT_eg), 0,
18343 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 1, 2, 0, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18,
18344 : // Src: (sext_inreg:i32 i32:i32:$src, i8:Other) - Complexity = 3
18345 : // Dst: (BFE_INT_eg:i32 i32:i32:$src, ZERO:i32, (MOV_IMM_I32:i32 8:i32))
18346 : /*46836*/ 0, /*End of Scope*/
18347 : /*46837*/ /*SwitchType*/ 16, MVT::i64,// ->46855
18348 : /*46839*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18349 : /*46841*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,32/*524288*/,
18350 : /*46846*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BFE_I64), 0,
18351 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 0, 1,
18352 : // Src: (sext_inreg:i64 i64:i64:$src, i8:Other) - Complexity = 3
18353 : // Dst: (S_BFE_I64:i64 i64:i64:$src, 524288:i32)
18354 : /*46855*/ 0, // EndSwitchType
18355 : /*46856*/ /*Scope*/ 24|128,1/*152*/, /*->47010*/
18356 : /*46858*/ OPC_CheckValueType, MVT::i16,
18357 : /*46860*/ OPC_MoveParent,
18358 : /*46861*/ OPC_SwitchType /*2 cases */, 127, MVT::i32,// ->46991
18359 : /*46864*/ OPC_Scope, 10, /*->46876*/ // 2 children in Scope
18360 : /*46866*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
18361 : /*46868*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_SEXT_I32_I16), 0,
18362 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0,
18363 : // Src: (sext_inreg:i32 i32:i32:$src0, i16:Other) - Complexity = 3
18364 : // Dst: (S_SEXT_I32_I16:i32 i32:i32:$src0)
18365 : /*46876*/ /*Scope*/ 113, /*->46990*/
18366 : /*46877*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18367 : /*46879*/ OPC_EmitInteger, MVT::i32, 0,
18368 : /*46882*/ OPC_EmitInteger, MVT::i32, 0,
18369 : /*46885*/ OPC_EmitInteger, MVT::i32, 0,
18370 : /*46888*/ OPC_EmitInteger, MVT::i32, 0,
18371 : /*46891*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18372 : /*46903*/ OPC_EmitRegister, MVT::i32, AMDGPU::ZERO,
18373 : /*46906*/ OPC_EmitInteger, MVT::i32, 0,
18374 : /*46909*/ OPC_EmitInteger, MVT::i32, 0,
18375 : /*46912*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18376 : /*46924*/ OPC_EmitInteger, MVT::i32, 16,
18377 : /*46927*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MOV_IMM_I32), 0,
18378 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 10, // Results = #11
18379 : /*46935*/ OPC_EmitInteger, MVT::i32, 0,
18380 : /*46938*/ OPC_EmitInteger, MVT::i32, 0,
18381 : /*46941*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18382 : /*46953*/ OPC_EmitInteger, MVT::i32, 1,
18383 : /*46956*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18384 : /*46959*/ OPC_EmitInteger, MVT::i32, 0,
18385 : /*46962*/ OPC_EmitInteger, MVT::i32, 0,
18386 : /*46965*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFE_INT_eg), 0,
18387 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 1, 2, 0, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18,
18388 : // Src: (sext_inreg:i32 i32:i32:$src, i16:Other) - Complexity = 3
18389 : // Dst: (BFE_INT_eg:i32 i32:i32:$src, ZERO:i32, (MOV_IMM_I32:i32 16:i32))
18390 : /*46990*/ 0, /*End of Scope*/
18391 : /*46991*/ /*SwitchType*/ 16, MVT::i64,// ->47009
18392 : /*46993*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18393 : /*46995*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,64/*1048576*/,
18394 : /*47000*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BFE_I64), 0,
18395 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 0, 1,
18396 : // Src: (sext_inreg:i64 i64:i64:$src, i16:Other) - Complexity = 3
18397 : // Dst: (S_BFE_I64:i64 i64:i64:$src, 1048576:i32)
18398 : /*47009*/ 0, // EndSwitchType
18399 : /*47010*/ /*Scope*/ 20, /*->47031*/
18400 : /*47011*/ OPC_CheckValueType, MVT::i32,
18401 : /*47013*/ OPC_MoveParent,
18402 : /*47014*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18403 : /*47016*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,0|128,1/*2097152*/,
18404 : /*47022*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BFE_I64), 0,
18405 : 1/*#VTs*/, MVT::i64, 2/*#Ops*/, 0, 1,
18406 : // Src: (sext_inreg:i64 i64:i64:$src, i32:Other) - Complexity = 3
18407 : // Dst: (S_BFE_I64:i64 i64:i64:$src, 2097152:i32)
18408 : /*47031*/ 0, /*End of Scope*/
18409 : /*47032*/ /*SwitchOpcode*/ 12|128,4/*524*/, TARGET_VAL(AMDGPUISD::MAD_U24),// ->47560
18410 : /*47036*/ OPC_RecordChild0, // #0 = $src0
18411 : /*47037*/ OPC_RecordChild1, // #1 = $src1
18412 : /*47038*/ OPC_RecordChild2, // #2 = $src2
18413 : /*47039*/ OPC_CheckChild2Type, MVT::i32,
18414 : /*47041*/ OPC_CheckType, MVT::i32,
18415 : /*47043*/ OPC_Scope, 99, /*->47144*/ // 4 children in Scope
18416 : /*47045*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18417 : /*47047*/ OPC_EmitInteger, MVT::i32, 0,
18418 : /*47050*/ OPC_EmitInteger, MVT::i32, 0,
18419 : /*47053*/ OPC_EmitInteger, MVT::i32, 0,
18420 : /*47056*/ OPC_EmitInteger, MVT::i32, 0,
18421 : /*47059*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18422 : /*47071*/ OPC_EmitInteger, MVT::i32, 0,
18423 : /*47074*/ OPC_EmitInteger, MVT::i32, 0,
18424 : /*47077*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18425 : /*47089*/ OPC_EmitInteger, MVT::i32, 0,
18426 : /*47092*/ OPC_EmitInteger, MVT::i32, 0,
18427 : /*47095*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18428 : /*47107*/ OPC_EmitInteger, MVT::i32, 1,
18429 : /*47110*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18430 : /*47113*/ OPC_EmitInteger, MVT::i32, 0,
18431 : /*47116*/ OPC_EmitInteger, MVT::i32, 0,
18432 : /*47119*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULADD_UINT24_eg), 0,
18433 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
18434 : // Src: (AMDGPUmad_u24:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = 3
18435 : // Dst: (MULADD_UINT24_eg:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
18436 : /*47144*/ /*Scope*/ 72|128,1/*200*/, /*->47346*/
18437 : /*47146*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
18438 : /*47148*/ OPC_EmitInteger, MVT::i32, 0,
18439 : /*47151*/ OPC_EmitInteger, MVT::i32, 0,
18440 : /*47154*/ OPC_EmitInteger, MVT::i32, 1,
18441 : /*47157*/ OPC_EmitInteger, MVT::i32, 0,
18442 : /*47160*/ OPC_EmitInteger, MVT::i32, 0,
18443 : /*47163*/ OPC_EmitInteger, MVT::i32, 0,
18444 : /*47166*/ OPC_EmitInteger, MVT::i32, 0,
18445 : /*47169*/ OPC_EmitInteger, MVT::i32, 0,
18446 : /*47172*/ OPC_EmitInteger, MVT::i32, 1,
18447 : /*47175*/ OPC_EmitInteger, MVT::i32, 0,
18448 : /*47178*/ OPC_EmitInteger, MVT::i32, 0,
18449 : /*47181*/ OPC_EmitInteger, MVT::i32, 0,
18450 : /*47184*/ OPC_EmitInteger, MVT::i32, 0,
18451 : /*47187*/ OPC_EmitInteger, MVT::i32, 0,
18452 : /*47190*/ OPC_EmitInteger, MVT::i32, 0,
18453 : /*47193*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18454 : /*47205*/ OPC_EmitInteger, MVT::i32, 0,
18455 : /*47208*/ OPC_EmitInteger, MVT::i32, 0,
18456 : /*47211*/ OPC_EmitInteger, MVT::i32, 0,
18457 : /*47214*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18458 : /*47226*/ OPC_EmitInteger, MVT::i32, 1,
18459 : /*47229*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18460 : /*47232*/ OPC_EmitInteger, MVT::i32, 0,
18461 : /*47235*/ OPC_EmitInteger, MVT::i32, 0,
18462 : /*47238*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MULLO_UINT_r600), 0,
18463 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 9, 10, 11, 12, 13, 14, 0, 15, 16, 17, 18, 1, 19, 20, 21, 22, 23, 24, 25, 26, // Results = #27
18464 : /*47265*/ OPC_EmitInteger, MVT::i32, 0,
18465 : /*47268*/ OPC_EmitInteger, MVT::i32, 0,
18466 : /*47271*/ OPC_EmitInteger, MVT::i32, 0,
18467 : /*47274*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18468 : /*47286*/ OPC_EmitInteger, MVT::i32, 0,
18469 : /*47289*/ OPC_EmitInteger, MVT::i32, 0,
18470 : /*47292*/ OPC_EmitInteger, MVT::i32, 0,
18471 : /*47295*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18472 : /*47307*/ OPC_EmitInteger, MVT::i32, 1,
18473 : /*47310*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18474 : /*47313*/ OPC_EmitInteger, MVT::i32, 0,
18475 : /*47316*/ OPC_EmitInteger, MVT::i32, 0,
18476 : /*47319*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::ADD_INT), 0,
18477 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 3, 4, 5, 6, 7, 8, 27, 28, 29, 30, 31, 2, 32, 33, 34, 35, 36, 37, 38, 39,
18478 : // Src: (AMDGPUmad_u24:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = 3
18479 : // Dst: (ADD_INT:i32 (MULLO_UINT_r600:i32 ?:i32:$src0, ?:i32:$src1), ?:i32:$src2)
18480 : /*47346*/ /*Scope*/ 72|128,1/*200*/, /*->47548*/
18481 : /*47348*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
18482 : /*47350*/ OPC_EmitInteger, MVT::i32, 0,
18483 : /*47353*/ OPC_EmitInteger, MVT::i32, 0,
18484 : /*47356*/ OPC_EmitInteger, MVT::i32, 1,
18485 : /*47359*/ OPC_EmitInteger, MVT::i32, 0,
18486 : /*47362*/ OPC_EmitInteger, MVT::i32, 0,
18487 : /*47365*/ OPC_EmitInteger, MVT::i32, 0,
18488 : /*47368*/ OPC_EmitInteger, MVT::i32, 0,
18489 : /*47371*/ OPC_EmitInteger, MVT::i32, 0,
18490 : /*47374*/ OPC_EmitInteger, MVT::i32, 1,
18491 : /*47377*/ OPC_EmitInteger, MVT::i32, 0,
18492 : /*47380*/ OPC_EmitInteger, MVT::i32, 0,
18493 : /*47383*/ OPC_EmitInteger, MVT::i32, 0,
18494 : /*47386*/ OPC_EmitInteger, MVT::i32, 0,
18495 : /*47389*/ OPC_EmitInteger, MVT::i32, 0,
18496 : /*47392*/ OPC_EmitInteger, MVT::i32, 0,
18497 : /*47395*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18498 : /*47407*/ OPC_EmitInteger, MVT::i32, 0,
18499 : /*47410*/ OPC_EmitInteger, MVT::i32, 0,
18500 : /*47413*/ OPC_EmitInteger, MVT::i32, 0,
18501 : /*47416*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18502 : /*47428*/ OPC_EmitInteger, MVT::i32, 1,
18503 : /*47431*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18504 : /*47434*/ OPC_EmitInteger, MVT::i32, 0,
18505 : /*47437*/ OPC_EmitInteger, MVT::i32, 0,
18506 : /*47440*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MULLO_UINT_cm), 0,
18507 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 9, 10, 11, 12, 13, 14, 0, 15, 16, 17, 18, 1, 19, 20, 21, 22, 23, 24, 25, 26, // Results = #27
18508 : /*47467*/ OPC_EmitInteger, MVT::i32, 0,
18509 : /*47470*/ OPC_EmitInteger, MVT::i32, 0,
18510 : /*47473*/ OPC_EmitInteger, MVT::i32, 0,
18511 : /*47476*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18512 : /*47488*/ OPC_EmitInteger, MVT::i32, 0,
18513 : /*47491*/ OPC_EmitInteger, MVT::i32, 0,
18514 : /*47494*/ OPC_EmitInteger, MVT::i32, 0,
18515 : /*47497*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18516 : /*47509*/ OPC_EmitInteger, MVT::i32, 1,
18517 : /*47512*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18518 : /*47515*/ OPC_EmitInteger, MVT::i32, 0,
18519 : /*47518*/ OPC_EmitInteger, MVT::i32, 0,
18520 : /*47521*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::ADD_INT), 0,
18521 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 3, 4, 5, 6, 7, 8, 27, 28, 29, 30, 31, 2, 32, 33, 34, 35, 36, 37, 38, 39,
18522 : // Src: (AMDGPUmad_u24:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = 3
18523 : // Dst: (ADD_INT:i32 (MULLO_UINT_cm:i32 ?:i32:$src0, ?:i32:$src1), ?:i32:$src2)
18524 : /*47548*/ /*Scope*/ 10, /*->47559*/
18525 : /*47549*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAD_U32_U24), 0,
18526 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
18527 : // Src: (AMDGPUmad_u24:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = -997
18528 : // Dst: (V_MAD_U32_U24:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
18529 : /*47559*/ 0, /*End of Scope*/
18530 : /*47560*/ /*SwitchOpcode*/ 121, TARGET_VAL(ISD::ROTR),// ->47684
18531 : /*47563*/ OPC_RecordChild0, // #0 = $src0
18532 : /*47564*/ OPC_RecordChild1, // #1 = $src1
18533 : /*47565*/ OPC_CheckChild1Type, MVT::i32,
18534 : /*47567*/ OPC_CheckType, MVT::i32,
18535 : /*47569*/ OPC_Scope, 99, /*->47670*/ // 2 children in Scope
18536 : /*47571*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18537 : /*47573*/ OPC_EmitInteger, MVT::i32, 0,
18538 : /*47576*/ OPC_EmitInteger, MVT::i32, 0,
18539 : /*47579*/ OPC_EmitInteger, MVT::i32, 0,
18540 : /*47582*/ OPC_EmitInteger, MVT::i32, 0,
18541 : /*47585*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18542 : /*47597*/ OPC_EmitInteger, MVT::i32, 0,
18543 : /*47600*/ OPC_EmitInteger, MVT::i32, 0,
18544 : /*47603*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18545 : /*47615*/ OPC_EmitInteger, MVT::i32, 0,
18546 : /*47618*/ OPC_EmitInteger, MVT::i32, 0,
18547 : /*47621*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18548 : /*47633*/ OPC_EmitInteger, MVT::i32, 1,
18549 : /*47636*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18550 : /*47639*/ OPC_EmitInteger, MVT::i32, 0,
18551 : /*47642*/ OPC_EmitInteger, MVT::i32, 0,
18552 : /*47645*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BIT_ALIGN_INT_eg), 0,
18553 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 2, 3, 0, 4, 5, 6, 0, 7, 8, 9, 1, 10, 11, 12, 13, 14, 15, 16,
18554 : // Src: (rotr:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
18555 : // Dst: (BIT_ALIGN_INT_eg:i32 ?:i32:$src0, ?:i32:$src0, ?:i32:$src1)
18556 : /*47670*/ /*Scope*/ 12, /*->47683*/
18557 : /*47671*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18558 : /*47673*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_ALIGNBIT_B32), 0,
18559 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 0, 1,
18560 : // Src: (rotr:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
18561 : // Dst: (V_ALIGNBIT_B32:i32 ?:i32:$src0, ?:i32:$src0, ?:i32:$src1)
18562 : /*47683*/ 0, /*End of Scope*/
18563 : /*47684*/ /*SwitchOpcode*/ 2|128,1/*130*/, TARGET_VAL(ISD::CTPOP),// ->47818
18564 : /*47688*/ OPC_RecordChild0, // #0 = $src0
18565 : /*47689*/ OPC_SwitchType /*2 cases */, 81, MVT::i32,// ->47773
18566 : /*47692*/ OPC_Scope, 67, /*->47761*/ // 2 children in Scope
18567 : /*47694*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18568 : /*47696*/ OPC_EmitInteger, MVT::i32, 1,
18569 : /*47699*/ OPC_EmitInteger, MVT::i32, 0,
18570 : /*47702*/ OPC_EmitInteger, MVT::i32, 0,
18571 : /*47705*/ OPC_EmitInteger, MVT::i32, 0,
18572 : /*47708*/ OPC_EmitInteger, MVT::i32, 0,
18573 : /*47711*/ OPC_EmitInteger, MVT::i32, 0,
18574 : /*47714*/ OPC_EmitInteger, MVT::i32, 0,
18575 : /*47717*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18576 : /*47729*/ OPC_EmitInteger, MVT::i32, 1,
18577 : /*47732*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18578 : /*47735*/ OPC_EmitInteger, MVT::i32, 0,
18579 : /*47738*/ OPC_EmitInteger, MVT::i32, 0,
18580 : /*47741*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BCNT_INT), 0,
18581 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
18582 : // Src: (ctpop:i32 R600_Reg32:i32:$src0) - Complexity = 3
18583 : // Dst: (BCNT_INT:i32 R600_Reg32:i32:$src0)
18584 : /*47761*/ /*Scope*/ 10, /*->47772*/
18585 : /*47762*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
18586 : /*47764*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BCNT1_I32_B32), 0,
18587 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0,
18588 : // Src: (ctpop:i32 i32:i32:$src0) - Complexity = 3
18589 : // Dst: (S_BCNT1_I32_B32:i32 i32:i32:$src0)
18590 : /*47772*/ 0, /*End of Scope*/
18591 : /*47773*/ /*SwitchType*/ 42, MVT::i64,// ->47817
18592 : /*47775*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18593 : /*47777*/ OPC_EmitInteger, MVT::i32, AMDGPU::SReg_64RegClassID,
18594 : /*47780*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_BCNT1_I32_B64), 0,
18595 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0, // Results = #2
18596 : /*47788*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
18597 : /*47791*/ OPC_EmitInteger, MVT::i32, 0,
18598 : /*47794*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
18599 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 4, // Results = #5
18600 : /*47802*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
18601 : /*47805*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
18602 : 1/*#VTs*/, MVT::i64, 5/*#Ops*/, 1, 2, 3, 5, 6,
18603 : // Src: (ctpop:i64 i64:i64:$src) - Complexity = 3
18604 : // Dst: (REG_SEQUENCE:i64 SReg_64:i32, (S_BCNT1_I32_B64:i32 ?:i64:$src), sub0:i32, (S_MOV_B32:i32 0:i32), sub1:i32)
18605 : /*47817*/ 0, // EndSwitchType
18606 : /*47818*/ /*SwitchOpcode*/ 105, TARGET_VAL(AMDGPUISD::CARRY),// ->47926
18607 : /*47821*/ OPC_RecordChild0, // #0 = $src0
18608 : /*47822*/ OPC_RecordChild1, // #1 = $src1
18609 : /*47823*/ OPC_CheckType, MVT::i32,
18610 : /*47825*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18611 : /*47827*/ OPC_EmitInteger, MVT::i32, 0,
18612 : /*47830*/ OPC_EmitInteger, MVT::i32, 0,
18613 : /*47833*/ OPC_EmitInteger, MVT::i32, 1,
18614 : /*47836*/ OPC_EmitInteger, MVT::i32, 0,
18615 : /*47839*/ OPC_EmitInteger, MVT::i32, 0,
18616 : /*47842*/ OPC_EmitInteger, MVT::i32, 0,
18617 : /*47845*/ OPC_EmitInteger, MVT::i32, 0,
18618 : /*47848*/ OPC_EmitInteger, MVT::i32, 0,
18619 : /*47851*/ OPC_EmitInteger, MVT::i32, 0,
18620 : /*47854*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18621 : /*47866*/ OPC_EmitInteger, MVT::i32, 0,
18622 : /*47869*/ OPC_EmitInteger, MVT::i32, 0,
18623 : /*47872*/ OPC_EmitInteger, MVT::i32, 0,
18624 : /*47875*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18625 : /*47887*/ OPC_EmitInteger, MVT::i32, 1,
18626 : /*47890*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18627 : /*47893*/ OPC_EmitInteger, MVT::i32, 0,
18628 : /*47896*/ OPC_EmitInteger, MVT::i32, 0,
18629 : /*47899*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::ADDC_UINT), 0,
18630 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
18631 : // Src: (AMDGPUcarry:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
18632 : // Dst: (ADDC_UINT:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
18633 : /*47926*/ /*SwitchOpcode*/ 105, TARGET_VAL(AMDGPUISD::BORROW),// ->48034
18634 : /*47929*/ OPC_RecordChild0, // #0 = $src0
18635 : /*47930*/ OPC_RecordChild1, // #1 = $src1
18636 : /*47931*/ OPC_CheckType, MVT::i32,
18637 : /*47933*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18638 : /*47935*/ OPC_EmitInteger, MVT::i32, 0,
18639 : /*47938*/ OPC_EmitInteger, MVT::i32, 0,
18640 : /*47941*/ OPC_EmitInteger, MVT::i32, 1,
18641 : /*47944*/ OPC_EmitInteger, MVT::i32, 0,
18642 : /*47947*/ OPC_EmitInteger, MVT::i32, 0,
18643 : /*47950*/ OPC_EmitInteger, MVT::i32, 0,
18644 : /*47953*/ OPC_EmitInteger, MVT::i32, 0,
18645 : /*47956*/ OPC_EmitInteger, MVT::i32, 0,
18646 : /*47959*/ OPC_EmitInteger, MVT::i32, 0,
18647 : /*47962*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18648 : /*47974*/ OPC_EmitInteger, MVT::i32, 0,
18649 : /*47977*/ OPC_EmitInteger, MVT::i32, 0,
18650 : /*47980*/ OPC_EmitInteger, MVT::i32, 0,
18651 : /*47983*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18652 : /*47995*/ OPC_EmitInteger, MVT::i32, 1,
18653 : /*47998*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18654 : /*48001*/ OPC_EmitInteger, MVT::i32, 0,
18655 : /*48004*/ OPC_EmitInteger, MVT::i32, 0,
18656 : /*48007*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SUBB_UINT), 0,
18657 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
18658 : // Src: (AMDGPUborrow:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1) - Complexity = 3
18659 : // Dst: (SUBB_UINT:i32 R600_Reg32:i32:$src0, R600_Reg32:i32:$src1)
18660 : /*48034*/ /*SwitchOpcode*/ 84, TARGET_VAL(ISD::CTLZ_ZERO_UNDEF),// ->48121
18661 : /*48037*/ OPC_RecordChild0, // #0 = $src0
18662 : /*48038*/ OPC_CheckType, MVT::i32,
18663 : /*48040*/ OPC_Scope, 67, /*->48109*/ // 2 children in Scope
18664 : /*48042*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18665 : /*48044*/ OPC_EmitInteger, MVT::i32, 1,
18666 : /*48047*/ OPC_EmitInteger, MVT::i32, 0,
18667 : /*48050*/ OPC_EmitInteger, MVT::i32, 0,
18668 : /*48053*/ OPC_EmitInteger, MVT::i32, 0,
18669 : /*48056*/ OPC_EmitInteger, MVT::i32, 0,
18670 : /*48059*/ OPC_EmitInteger, MVT::i32, 0,
18671 : /*48062*/ OPC_EmitInteger, MVT::i32, 0,
18672 : /*48065*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18673 : /*48077*/ OPC_EmitInteger, MVT::i32, 1,
18674 : /*48080*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18675 : /*48083*/ OPC_EmitInteger, MVT::i32, 0,
18676 : /*48086*/ OPC_EmitInteger, MVT::i32, 0,
18677 : /*48089*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FFBH_UINT), 0,
18678 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
18679 : // Src: (ctlz_zero_undef:i32 R600_Reg32:i32:$src0) - Complexity = 3
18680 : // Dst: (FFBH_UINT:i32 R600_Reg32:i32:$src0)
18681 : /*48109*/ /*Scope*/ 10, /*->48120*/
18682 : /*48110*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
18683 : /*48112*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_FLBIT_I32_B32), 0,
18684 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0,
18685 : // Src: (ctlz_zero_undef:i32 i32:i32:$src0) - Complexity = 3
18686 : // Dst: (S_FLBIT_I32_B32:i32 i32:i32:$src0)
18687 : /*48120*/ 0, /*End of Scope*/
18688 : /*48121*/ /*SwitchOpcode*/ 84, TARGET_VAL(ISD::CTTZ_ZERO_UNDEF),// ->48208
18689 : /*48124*/ OPC_RecordChild0, // #0 = $src0
18690 : /*48125*/ OPC_CheckType, MVT::i32,
18691 : /*48127*/ OPC_Scope, 67, /*->48196*/ // 2 children in Scope
18692 : /*48129*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
18693 : /*48131*/ OPC_EmitInteger, MVT::i32, 1,
18694 : /*48134*/ OPC_EmitInteger, MVT::i32, 0,
18695 : /*48137*/ OPC_EmitInteger, MVT::i32, 0,
18696 : /*48140*/ OPC_EmitInteger, MVT::i32, 0,
18697 : /*48143*/ OPC_EmitInteger, MVT::i32, 0,
18698 : /*48146*/ OPC_EmitInteger, MVT::i32, 0,
18699 : /*48149*/ OPC_EmitInteger, MVT::i32, 0,
18700 : /*48152*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18701 : /*48164*/ OPC_EmitInteger, MVT::i32, 1,
18702 : /*48167*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18703 : /*48170*/ OPC_EmitInteger, MVT::i32, 0,
18704 : /*48173*/ OPC_EmitInteger, MVT::i32, 0,
18705 : /*48176*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FFBL_INT), 0,
18706 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
18707 : // Src: (cttz_zero_undef:i32 R600_Reg32:i32:$src0) - Complexity = 3
18708 : // Dst: (FFBL_INT:i32 R600_Reg32:i32:$src0)
18709 : /*48196*/ /*Scope*/ 10, /*->48207*/
18710 : /*48197*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
18711 : /*48199*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_FF1_I32_B32), 0,
18712 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0,
18713 : // Src: (cttz_zero_undef:i32 i32:i32:$src0) - Complexity = 3
18714 : // Dst: (S_FF1_I32_B32:i32 i32:i32:$src0)
18715 : /*48207*/ 0, /*End of Scope*/
18716 : /*48208*/ /*SwitchOpcode*/ 12|128,4/*524*/, TARGET_VAL(AMDGPUISD::MAD_I24),// ->48736
18717 : /*48212*/ OPC_RecordChild0, // #0 = $src0
18718 : /*48213*/ OPC_RecordChild1, // #1 = $src1
18719 : /*48214*/ OPC_RecordChild2, // #2 = $src2
18720 : /*48215*/ OPC_CheckChild2Type, MVT::i32,
18721 : /*48217*/ OPC_CheckType, MVT::i32,
18722 : /*48219*/ OPC_Scope, 99, /*->48320*/ // 4 children in Scope
18723 : /*48221*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
18724 : /*48223*/ OPC_EmitInteger, MVT::i32, 0,
18725 : /*48226*/ OPC_EmitInteger, MVT::i32, 0,
18726 : /*48229*/ OPC_EmitInteger, MVT::i32, 0,
18727 : /*48232*/ OPC_EmitInteger, MVT::i32, 0,
18728 : /*48235*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18729 : /*48247*/ OPC_EmitInteger, MVT::i32, 0,
18730 : /*48250*/ OPC_EmitInteger, MVT::i32, 0,
18731 : /*48253*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18732 : /*48265*/ OPC_EmitInteger, MVT::i32, 0,
18733 : /*48268*/ OPC_EmitInteger, MVT::i32, 0,
18734 : /*48271*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18735 : /*48283*/ OPC_EmitInteger, MVT::i32, 1,
18736 : /*48286*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18737 : /*48289*/ OPC_EmitInteger, MVT::i32, 0,
18738 : /*48292*/ OPC_EmitInteger, MVT::i32, 0,
18739 : /*48295*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULADD_INT24_cm), 0,
18740 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
18741 : // Src: (AMDGPUmad_i24:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = 3
18742 : // Dst: (MULADD_INT24_cm:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
18743 : /*48320*/ /*Scope*/ 72|128,1/*200*/, /*->48522*/
18744 : /*48322*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
18745 : /*48324*/ OPC_EmitInteger, MVT::i32, 0,
18746 : /*48327*/ OPC_EmitInteger, MVT::i32, 0,
18747 : /*48330*/ OPC_EmitInteger, MVT::i32, 1,
18748 : /*48333*/ OPC_EmitInteger, MVT::i32, 0,
18749 : /*48336*/ OPC_EmitInteger, MVT::i32, 0,
18750 : /*48339*/ OPC_EmitInteger, MVT::i32, 0,
18751 : /*48342*/ OPC_EmitInteger, MVT::i32, 0,
18752 : /*48345*/ OPC_EmitInteger, MVT::i32, 0,
18753 : /*48348*/ OPC_EmitInteger, MVT::i32, 1,
18754 : /*48351*/ OPC_EmitInteger, MVT::i32, 0,
18755 : /*48354*/ OPC_EmitInteger, MVT::i32, 0,
18756 : /*48357*/ OPC_EmitInteger, MVT::i32, 0,
18757 : /*48360*/ OPC_EmitInteger, MVT::i32, 0,
18758 : /*48363*/ OPC_EmitInteger, MVT::i32, 0,
18759 : /*48366*/ OPC_EmitInteger, MVT::i32, 0,
18760 : /*48369*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18761 : /*48381*/ OPC_EmitInteger, MVT::i32, 0,
18762 : /*48384*/ OPC_EmitInteger, MVT::i32, 0,
18763 : /*48387*/ OPC_EmitInteger, MVT::i32, 0,
18764 : /*48390*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18765 : /*48402*/ OPC_EmitInteger, MVT::i32, 1,
18766 : /*48405*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18767 : /*48408*/ OPC_EmitInteger, MVT::i32, 0,
18768 : /*48411*/ OPC_EmitInteger, MVT::i32, 0,
18769 : /*48414*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MULLO_INT_r600), 0,
18770 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 9, 10, 11, 12, 13, 14, 0, 15, 16, 17, 18, 1, 19, 20, 21, 22, 23, 24, 25, 26, // Results = #27
18771 : /*48441*/ OPC_EmitInteger, MVT::i32, 0,
18772 : /*48444*/ OPC_EmitInteger, MVT::i32, 0,
18773 : /*48447*/ OPC_EmitInteger, MVT::i32, 0,
18774 : /*48450*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18775 : /*48462*/ OPC_EmitInteger, MVT::i32, 0,
18776 : /*48465*/ OPC_EmitInteger, MVT::i32, 0,
18777 : /*48468*/ OPC_EmitInteger, MVT::i32, 0,
18778 : /*48471*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18779 : /*48483*/ OPC_EmitInteger, MVT::i32, 1,
18780 : /*48486*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18781 : /*48489*/ OPC_EmitInteger, MVT::i32, 0,
18782 : /*48492*/ OPC_EmitInteger, MVT::i32, 0,
18783 : /*48495*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::ADD_INT), 0,
18784 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 3, 4, 5, 6, 7, 8, 27, 28, 29, 30, 31, 2, 32, 33, 34, 35, 36, 37, 38, 39,
18785 : // Src: (AMDGPUmad_i24:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = 3
18786 : // Dst: (ADD_INT:i32 (MULLO_INT_r600:i32 ?:i32:$src0, ?:i32:$src1), ?:i32:$src2)
18787 : /*48522*/ /*Scope*/ 72|128,1/*200*/, /*->48724*/
18788 : /*48524*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
18789 : /*48526*/ OPC_EmitInteger, MVT::i32, 0,
18790 : /*48529*/ OPC_EmitInteger, MVT::i32, 0,
18791 : /*48532*/ OPC_EmitInteger, MVT::i32, 1,
18792 : /*48535*/ OPC_EmitInteger, MVT::i32, 0,
18793 : /*48538*/ OPC_EmitInteger, MVT::i32, 0,
18794 : /*48541*/ OPC_EmitInteger, MVT::i32, 0,
18795 : /*48544*/ OPC_EmitInteger, MVT::i32, 0,
18796 : /*48547*/ OPC_EmitInteger, MVT::i32, 0,
18797 : /*48550*/ OPC_EmitInteger, MVT::i32, 1,
18798 : /*48553*/ OPC_EmitInteger, MVT::i32, 0,
18799 : /*48556*/ OPC_EmitInteger, MVT::i32, 0,
18800 : /*48559*/ OPC_EmitInteger, MVT::i32, 0,
18801 : /*48562*/ OPC_EmitInteger, MVT::i32, 0,
18802 : /*48565*/ OPC_EmitInteger, MVT::i32, 0,
18803 : /*48568*/ OPC_EmitInteger, MVT::i32, 0,
18804 : /*48571*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18805 : /*48583*/ OPC_EmitInteger, MVT::i32, 0,
18806 : /*48586*/ OPC_EmitInteger, MVT::i32, 0,
18807 : /*48589*/ OPC_EmitInteger, MVT::i32, 0,
18808 : /*48592*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18809 : /*48604*/ OPC_EmitInteger, MVT::i32, 1,
18810 : /*48607*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18811 : /*48610*/ OPC_EmitInteger, MVT::i32, 0,
18812 : /*48613*/ OPC_EmitInteger, MVT::i32, 0,
18813 : /*48616*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MULLO_INT_eg), 0,
18814 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 9, 10, 11, 12, 13, 14, 0, 15, 16, 17, 18, 1, 19, 20, 21, 22, 23, 24, 25, 26, // Results = #27
18815 : /*48643*/ OPC_EmitInteger, MVT::i32, 0,
18816 : /*48646*/ OPC_EmitInteger, MVT::i32, 0,
18817 : /*48649*/ OPC_EmitInteger, MVT::i32, 0,
18818 : /*48652*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18819 : /*48664*/ OPC_EmitInteger, MVT::i32, 0,
18820 : /*48667*/ OPC_EmitInteger, MVT::i32, 0,
18821 : /*48670*/ OPC_EmitInteger, MVT::i32, 0,
18822 : /*48673*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18823 : /*48685*/ OPC_EmitInteger, MVT::i32, 1,
18824 : /*48688*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
18825 : /*48691*/ OPC_EmitInteger, MVT::i32, 0,
18826 : /*48694*/ OPC_EmitInteger, MVT::i32, 0,
18827 : /*48697*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::ADD_INT), 0,
18828 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 3, 4, 5, 6, 7, 8, 27, 28, 29, 30, 31, 2, 32, 33, 34, 35, 36, 37, 38, 39,
18829 : // Src: (AMDGPUmad_i24:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = 3
18830 : // Dst: (ADD_INT:i32 (MULLO_INT_eg:i32 ?:i32:$src0, ?:i32:$src1), ?:i32:$src2)
18831 : /*48724*/ /*Scope*/ 10, /*->48735*/
18832 : /*48725*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAD_I32_I24), 0,
18833 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
18834 : // Src: (AMDGPUmad_i24:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = -997
18835 : // Dst: (V_MAD_I32_I24:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
18836 : /*48735*/ 0, /*End of Scope*/
18837 : /*48736*/ /*SwitchOpcode*/ 13, TARGET_VAL(AMDGPUISD::BREV),// ->48752
18838 : /*48739*/ OPC_RecordChild0, // #0 = $src0
18839 : /*48740*/ OPC_CheckType, MVT::i32,
18840 : /*48742*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
18841 : /*48744*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BREV_B32), 0,
18842 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0,
18843 : // Src: (AMDGPUbrev:i32 i32:i32:$src0) - Complexity = 3
18844 : // Dst: (S_BREV_B32:i32 i32:i32:$src0)
18845 : /*48752*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::ADDE),// ->48771
18846 : /*48755*/ OPC_CaptureGlueInput,
18847 : /*48756*/ OPC_RecordChild0, // #0 = $src0
18848 : /*48757*/ OPC_RecordChild1, // #1 = $src1
18849 : /*48758*/ OPC_CheckType, MVT::i32,
18850 : /*48760*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
18851 : /*48762*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_ADDC_U32), 0|OPFL_GlueInput|OPFL_GlueOutput,
18852 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
18853 : // Src: (adde:i32 SSrc_32:i32:$src0, SSrc_32:i32:$src1) - Complexity = 3
18854 : // Dst: (S_ADDC_U32:i32 SSrc_32:i32:$src0, SSrc_32:i32:$src1)
18855 : /*48771*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::SUBE),// ->48790
18856 : /*48774*/ OPC_CaptureGlueInput,
18857 : /*48775*/ OPC_RecordChild0, // #0 = $src0
18858 : /*48776*/ OPC_RecordChild1, // #1 = $src1
18859 : /*48777*/ OPC_CheckType, MVT::i32,
18860 : /*48779*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
18861 : /*48781*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_SUBB_U32), 0|OPFL_GlueInput|OPFL_GlueOutput,
18862 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
18863 : // Src: (sube:i32 SSrc_32:i32:$src0, SSrc_32:i32:$src1) - Complexity = 3
18864 : // Dst: (S_SUBB_U32:i32 SSrc_32:i32:$src0, SSrc_32:i32:$src1)
18865 : /*48790*/ /*SwitchOpcode*/ 24, TARGET_VAL(AMDGPUISD::RET_FLAG),// ->48817
18866 : /*48793*/ OPC_RecordNode, // #0 = 'IL_retflag' chained node
18867 : /*48794*/ OPC_CaptureGlueInput,
18868 : /*48795*/ OPC_Scope, 9, /*->48806*/ // 2 children in Scope
18869 : /*48797*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
18870 : /*48799*/ OPC_EmitMergeInputChains1_0,
18871 : /*48800*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_ENDPGM), 0|OPFL_Chain|OPFL_GlueInput,
18872 : 0/*#VTs*/, 0/*#Ops*/,
18873 : // Src: (IL_retflag) - Complexity = 3
18874 : // Dst: (S_ENDPGM)
18875 : /*48806*/ /*Scope*/ 9, /*->48816*/
18876 : /*48807*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
18877 : /*48809*/ OPC_EmitMergeInputChains1_0,
18878 : /*48810*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RETURN), 0|OPFL_Chain|OPFL_GlueInput,
18879 : 0/*#VTs*/, 0/*#Ops*/,
18880 : // Src: (IL_retflag) - Complexity = 3
18881 : // Dst: (RETURN)
18882 : /*48816*/ 0, /*End of Scope*/
18883 : /*48817*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::BR),// ->48852
18884 : /*48820*/ OPC_RecordNode, // #0 = 'br' chained node
18885 : /*48821*/ OPC_RecordChild1, // #1 = $simm16
18886 : /*48822*/ OPC_MoveChild, 1,
18887 : /*48824*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
18888 : /*48827*/ OPC_MoveParent,
18889 : /*48828*/ OPC_Scope, 10, /*->48840*/ // 2 children in Scope
18890 : /*48830*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
18891 : /*48832*/ OPC_EmitMergeInputChains1_0,
18892 : /*48833*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BRANCH), 0|OPFL_Chain,
18893 : 0/*#VTs*/, 1/*#Ops*/, 1,
18894 : // Src: (br (bb:Other):$simm16) - Complexity = 3
18895 : // Dst: (S_BRANCH (bb:Other):$simm16)
18896 : /*48840*/ /*Scope*/ 10, /*->48851*/
18897 : /*48841*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
18898 : /*48843*/ OPC_EmitMergeInputChains1_0,
18899 : /*48844*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BRANCH), 0|OPFL_Chain,
18900 : 0/*#VTs*/, 1/*#Ops*/, 1,
18901 : // Src: (br (bb:Other):$target) - Complexity = 3
18902 : // Dst: (BRANCH (bb:Other):$target)
18903 : /*48851*/ 0, /*End of Scope*/
18904 : /*48852*/ /*SwitchOpcode*/ 9, TARGET_VAL(AMDGPUISD::CONST_DATA_PTR),// ->48864
18905 : /*48855*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
18906 : /*48857*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_CONSTDATA_PTR), 0,
18907 : 1/*#VTs*/, MVT::i64, 0/*#Ops*/,
18908 : // Src: (SIconstdata_ptr:i64) - Complexity = 3
18909 : // Dst: (SI_CONSTDATA_PTR:i64)
18910 : /*48864*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::ADDC),// ->48882
18911 : /*48867*/ OPC_RecordChild0, // #0 = $src0
18912 : /*48868*/ OPC_RecordChild1, // #1 = $src1
18913 : /*48869*/ OPC_CheckType, MVT::i32,
18914 : /*48871*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18915 : /*48873*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_ADD_U32), 0|OPFL_GlueOutput,
18916 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
18917 : // Src: (addc:i32 i32:i32:$src0, i32:i32:$src1) - Complexity = 3
18918 : // Dst: (S_ADD_U32:i32 ?:i32:$src0, ?:i32:$src1)
18919 : /*48882*/ /*SwitchOpcode*/ 35, TARGET_VAL(ISD::SELECT),// ->48920
18920 : /*48885*/ OPC_RecordChild0, // #0 = $src0
18921 : /*48886*/ OPC_CheckChild0Type, MVT::i1,
18922 : /*48888*/ OPC_RecordChild1, // #1 = $src1
18923 : /*48889*/ OPC_RecordChild2, // #2 = $src2
18924 : /*48890*/ OPC_SwitchType /*2 cases */, 12, MVT::i32,// ->48905
18925 : /*48893*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18926 : /*48895*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
18927 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 1, 0,
18928 : // Src: (select:i32 i1:i1:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = 3
18929 : // Dst: (V_CNDMASK_B32_e64:i32 ?:i32:$src2, ?:i32:$src1, ?:i1:$src0)
18930 : /*48905*/ /*SwitchType*/ 12, MVT::f32,// ->48919
18931 : /*48907*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18932 : /*48909*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
18933 : 1/*#VTs*/, MVT::f32, 3/*#Ops*/, 2, 1, 0,
18934 : // Src: (select:f32 i1:i1:$src2, f32:f32:$src1, f32:f32:$src0) - Complexity = 3
18935 : // Dst: (V_CNDMASK_B32_e64:f32 ?:f32:$src0, ?:f32:$src1, ?:i1:$src2)
18936 : /*48919*/ 0, // EndSwitchType
18937 : /*48920*/ /*SwitchOpcode*/ 22|128,1/*150*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->49074
18938 : /*48924*/ OPC_RecordChild0, // #0 = $src0
18939 : /*48925*/ OPC_SwitchType /*2 cases */, 27, MVT::i32,// ->48955
18940 : /*48928*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18941 : /*48930*/ OPC_EmitInteger, MVT::i32, 0,
18942 : /*48933*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18943 : /*48945*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
18944 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 2, 0,
18945 : // Src: (sext:i32 i1:i1:$src0) - Complexity = 3
18946 : // Dst: (V_CNDMASK_B32_e64:i32 0:i32, -1:i32, ?:i1:$src0)
18947 : /*48955*/ /*SwitchType*/ 116, MVT::i64,// ->49073
18948 : /*48957*/ OPC_Scope, 37, /*->48996*/ // 2 children in Scope
18949 : /*48959*/ OPC_CheckChild0Type, MVT::i32,
18950 : /*48961*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18951 : /*48963*/ OPC_EmitInteger, MVT::i32, AMDGPU::SReg_64RegClassID,
18952 : /*48966*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
18953 : /*48969*/ OPC_EmitInteger, MVT::i32, 31,
18954 : /*48972*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_ASHR_I32), 0,
18955 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 3, // Results = #4
18956 : /*48981*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
18957 : /*48984*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
18958 : 1/*#VTs*/, MVT::i64, 5/*#Ops*/, 1, 0, 2, 4, 5,
18959 : // Src: (sext:i64 i32:i32:$src) - Complexity = 3
18960 : // Dst: (REG_SEQUENCE:i64 SReg_64:i32, ?:i32:$src, sub0:i32, (S_ASHR_I32:i32 ?:i32:$src, 31:i32), sub1:i32)
18961 : /*48996*/ /*Scope*/ 75, /*->49072*/
18962 : /*48997*/ OPC_CheckChild0Type, MVT::i1,
18963 : /*48999*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18964 : /*49001*/ OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
18965 : /*49004*/ OPC_EmitInteger, MVT::i32, 0,
18966 : /*49007*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18967 : /*49019*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
18968 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 3, 0, // Results = #4
18969 : /*49029*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
18970 : /*49032*/ OPC_EmitInteger, MVT::i32, 0,
18971 : /*49035*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
18972 : /*49047*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
18973 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 6, 7, 0, // Results = #8
18974 : /*49057*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
18975 : /*49060*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
18976 : 1/*#VTs*/, MVT::i64, 5/*#Ops*/, 1, 4, 5, 8, 9,
18977 : // Src: (sext:i64 i1:i1:$src) - Complexity = 3
18978 : // Dst: (REG_SEQUENCE:i64 VReg_64:i32, (V_CNDMASK_B32_e64:i32 0:i32, -1:i32, ?:i1:$src), sub0:i32, (V_CNDMASK_B32_e64:i32 0:i32, -1:i32, ?:i1:$src), sub1:i32)
18979 : /*49072*/ 0, /*End of Scope*/
18980 : /*49073*/ 0, // EndSwitchType
18981 : /*49074*/ /*SwitchOpcode*/ 117, TARGET_VAL(ISD::ZERO_EXTEND),// ->49194
18982 : /*49077*/ OPC_RecordChild0, // #0 = $src0
18983 : /*49078*/ OPC_SwitchType /*2 cases */, 18, MVT::i32,// ->49099
18984 : /*49081*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18985 : /*49083*/ OPC_EmitInteger, MVT::i32, 0,
18986 : /*49086*/ OPC_EmitInteger, MVT::i32, 1,
18987 : /*49089*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
18988 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 2, 0,
18989 : // Src: (zext:i32 i1:i1:$src0) - Complexity = 3
18990 : // Dst: (V_CNDMASK_B32_e64:i32 0:i32, 1:i32, ?:i1:$src0)
18991 : /*49099*/ /*SwitchType*/ 92, MVT::i64,// ->49193
18992 : /*49101*/ OPC_Scope, 36, /*->49139*/ // 2 children in Scope
18993 : /*49103*/ OPC_CheckChild0Type, MVT::i32,
18994 : /*49105*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
18995 : /*49107*/ OPC_EmitInteger, MVT::i32, AMDGPU::SReg_64RegClassID,
18996 : /*49110*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
18997 : /*49113*/ OPC_EmitInteger, MVT::i32, 0,
18998 : /*49116*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
18999 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
19000 : /*49124*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
19001 : /*49127*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
19002 : 1/*#VTs*/, MVT::i64, 5/*#Ops*/, 1, 0, 2, 4, 5,
19003 : // Src: (zext:i64 i32:i32:$src) - Complexity = 3
19004 : // Dst: (REG_SEQUENCE:i64 SReg_64:i32, ?:i32:$src, sub0:i32, (S_MOV_B32:i32 0:i32), sub1:i32)
19005 : /*49139*/ /*Scope*/ 52, /*->49192*/
19006 : /*49140*/ OPC_CheckChild0Type, MVT::i1,
19007 : /*49142*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
19008 : /*49144*/ OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
19009 : /*49147*/ OPC_EmitInteger, MVT::i32, 0,
19010 : /*49150*/ OPC_EmitInteger, MVT::i32, 1,
19011 : /*49153*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
19012 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 3, 0, // Results = #4
19013 : /*49163*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
19014 : /*49166*/ OPC_EmitInteger, MVT::i32, 0,
19015 : /*49169*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
19016 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 6, // Results = #7
19017 : /*49177*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
19018 : /*49180*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
19019 : 1/*#VTs*/, MVT::i64, 5/*#Ops*/, 1, 4, 5, 7, 8,
19020 : // Src: (zext:i64 i1:i1:$src) - Complexity = 3
19021 : // Dst: (REG_SEQUENCE:i64 VReg_64:i32, (V_CNDMASK_B32_e64:i32 0:i32, 1:i32, ?:i1:$src), sub0:i32, (S_MOV_B32:i32 0:i32), sub1:i32)
19022 : /*49192*/ 0, /*End of Scope*/
19023 : /*49193*/ 0, // EndSwitchType
19024 : /*49194*/ /*SwitchOpcode*/ 117, TARGET_VAL(ISD::ANY_EXTEND),// ->49314
19025 : /*49197*/ OPC_RecordChild0, // #0 = $src0
19026 : /*49198*/ OPC_SwitchType /*2 cases */, 18, MVT::i32,// ->49219
19027 : /*49201*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
19028 : /*49203*/ OPC_EmitInteger, MVT::i32, 0,
19029 : /*49206*/ OPC_EmitInteger, MVT::i32, 1,
19030 : /*49209*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
19031 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 2, 0,
19032 : // Src: (anyext:i32 i1:i1:$src0) - Complexity = 3
19033 : // Dst: (V_CNDMASK_B32_e64:i32 0:i32, 1:i32, ?:i1:$src0)
19034 : /*49219*/ /*SwitchType*/ 92, MVT::i64,// ->49313
19035 : /*49221*/ OPC_Scope, 36, /*->49259*/ // 2 children in Scope
19036 : /*49223*/ OPC_CheckChild0Type, MVT::i32,
19037 : /*49225*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
19038 : /*49227*/ OPC_EmitInteger, MVT::i32, AMDGPU::SReg_64RegClassID,
19039 : /*49230*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
19040 : /*49233*/ OPC_EmitInteger, MVT::i32, 0,
19041 : /*49236*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
19042 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 3, // Results = #4
19043 : /*49244*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
19044 : /*49247*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
19045 : 1/*#VTs*/, MVT::i64, 5/*#Ops*/, 1, 0, 2, 4, 5,
19046 : // Src: (anyext:i64 i32:i32:$src) - Complexity = 3
19047 : // Dst: (REG_SEQUENCE:i64 SReg_64:i32, ?:i32:$src, sub0:i32, (S_MOV_B32:i32 0:i32), sub1:i32)
19048 : /*49259*/ /*Scope*/ 52, /*->49312*/
19049 : /*49260*/ OPC_CheckChild0Type, MVT::i1,
19050 : /*49262*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
19051 : /*49264*/ OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
19052 : /*49267*/ OPC_EmitInteger, MVT::i32, 0,
19053 : /*49270*/ OPC_EmitInteger, MVT::i32, 1,
19054 : /*49273*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
19055 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 3, 0, // Results = #4
19056 : /*49283*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
19057 : /*49286*/ OPC_EmitInteger, MVT::i32, 0,
19058 : /*49289*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
19059 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 6, // Results = #7
19060 : /*49297*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
19061 : /*49300*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
19062 : 1/*#VTs*/, MVT::i64, 5/*#Ops*/, 1, 4, 5, 7, 8,
19063 : // Src: (anyext:i64 i1:i1:$src) - Complexity = 3
19064 : // Dst: (REG_SEQUENCE:i64 VReg_64:i32, (V_CNDMASK_B32_e64:i32 0:i32, 1:i32, ?:i1:$src), sub0:i32, (S_MOV_B32:i32 0:i32), sub1:i32)
19065 : /*49312*/ 0, /*End of Scope*/
19066 : /*49313*/ 0, // EndSwitchType
19067 : /*49314*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::TRUNCATE),// ->49410
19068 : /*49317*/ OPC_RecordChild0, // #0 = $a
19069 : /*49318*/ OPC_SwitchType /*2 cases */, 14, MVT::i32,// ->49335
19070 : /*49321*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
19071 : /*49323*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
19072 : /*49326*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
19073 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 1,
19074 : // Src: (trunc:i32 i64:i64:$a) - Complexity = 3
19075 : // Dst: (EXTRACT_SUBREG:i32 ?:i64:$a, sub0:i32)
19076 : /*49335*/ /*SwitchType*/ 72, MVT::i1,// ->49409
19077 : /*49337*/ OPC_Scope, 28, /*->49367*/ // 2 children in Scope
19078 : /*49339*/ OPC_CheckChild0Type, MVT::i32,
19079 : /*49341*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
19080 : /*49343*/ OPC_EmitInteger, MVT::i32, 1,
19081 : /*49346*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_AND_B32_e64), 0,
19082 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
19083 : /*49355*/ OPC_EmitInteger, MVT::i32, 1,
19084 : /*49358*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_EQ_I32_e64), 0,
19085 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 2, 3,
19086 : // Src: (trunc:i1 i32:i32:$a) - Complexity = 3
19087 : // Dst: (V_CMP_EQ_I32_e64:i1 (V_AND_B32_e64:i32 1:i32, ?:i32:$a), 1:i32)
19088 : /*49367*/ /*Scope*/ 40, /*->49408*/
19089 : /*49368*/ OPC_CheckChild0Type, MVT::i64,
19090 : /*49370*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
19091 : /*49372*/ OPC_EmitInteger, MVT::i32, 1,
19092 : /*49375*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
19093 : /*49378*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
19094 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
19095 : /*49387*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_AND_B32_e64), 0,
19096 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 3, // Results = #4
19097 : /*49396*/ OPC_EmitInteger, MVT::i32, 1,
19098 : /*49399*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_EQ_I32_e64), 0,
19099 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 4, 5,
19100 : // Src: (trunc:i1 i64:i64:$a) - Complexity = 3
19101 : // Dst: (V_CMP_EQ_I32_e64:i1 (V_AND_B32_e64:i32 1:i32, (EXTRACT_SUBREG:i32 ?:i64:$a, sub0:i32)), 1:i32)
19102 : /*49408*/ 0, /*End of Scope*/
19103 : /*49409*/ 0, // EndSwitchType
19104 : /*49410*/ /*SwitchOpcode*/ 55, TARGET_VAL(ISD::BSWAP),// ->49468
19105 : /*49413*/ OPC_RecordChild0, // #0 = $a
19106 : /*49414*/ OPC_CheckType, MVT::i32,
19107 : /*49416*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
19108 : /*49418*/ OPC_EmitInteger, MVT::i32, 127|128,1|128,124|128,7/*16711935*/,
19109 : /*49424*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
19110 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1, // Results = #2
19111 : /*49432*/ OPC_EmitInteger, MVT::i32, 24,
19112 : /*49435*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_ALIGNBIT_B32), 0,
19113 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 0, 3, // Results = #4
19114 : /*49445*/ OPC_EmitInteger, MVT::i32, 8,
19115 : /*49448*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_ALIGNBIT_B32), 0,
19116 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 0, 5, // Results = #6
19117 : /*49458*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
19118 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 2, 4, 6,
19119 : // Src: (bswap:i32 i32:i32:$a) - Complexity = 3
19120 : // Dst: (V_BFI_B32:i32 (S_MOV_B32:i32 16711935:i32), (V_ALIGNBIT_B32:i32 ?:i32:$a, ?:i32:$a, 24:i32), (V_ALIGNBIT_B32:i32 ?:i32:$a, ?:i32:$a, 8:i32))
19121 : /*49468*/ /*SwitchOpcode*/ 39, TARGET_VAL(AMDGPUISD::BRANCH_COND),// ->49510
19122 : /*49471*/ OPC_RecordNode, // #0 = 'IL_brcond' chained node
19123 : /*49472*/ OPC_RecordChild1, // #1 = $target
19124 : /*49473*/ OPC_MoveChild, 1,
19125 : /*49475*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
19126 : /*49478*/ OPC_MoveParent,
19127 : /*49479*/ OPC_RecordChild2, // #2 = $src0
19128 : /*49480*/ OPC_Scope, 13, /*->49495*/ // 2 children in Scope
19129 : /*49482*/ OPC_CheckChild2Type, MVT::i32,
19130 : /*49484*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
19131 : /*49486*/ OPC_EmitMergeInputChains1_0,
19132 : /*49487*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BRANCH_COND_i32), 0|OPFL_Chain,
19133 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
19134 : // Src: (IL_brcond (bb:Other):$target, R600_Reg32:i32:$src0) - Complexity = 3
19135 : // Dst: (BRANCH_COND_i32 (bb:Other):$target, R600_Reg32:i32:$src0)
19136 : /*49495*/ /*Scope*/ 13, /*->49509*/
19137 : /*49496*/ OPC_CheckChild2Type, MVT::f32,
19138 : /*49498*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
19139 : /*49500*/ OPC_EmitMergeInputChains1_0,
19140 : /*49501*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BRANCH_COND_f32), 0|OPFL_Chain,
19141 : 0/*#VTs*/, 2/*#Ops*/, 1, 2,
19142 : // Src: (IL_brcond (bb:Other):$target, R600_Reg32:f32:$src0) - Complexity = 3
19143 : // Dst: (BRANCH_COND_f32 (bb:Other):$target, R600_Reg32:f32:$src0)
19144 : /*49509*/ 0, /*End of Scope*/
19145 : /*49510*/ /*SwitchOpcode*/ 61|128,23/*3005*/, TARGET_VAL(ISD::SETCC),// ->52519
19146 : /*49514*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
19147 : /*49515*/ OPC_Scope, 62|128,8/*1086*/, /*->50604*/ // 4 children in Scope
19148 : /*49518*/ OPC_CheckChild0Type, MVT::f32,
19149 : /*49520*/ OPC_RecordChild1, // #1 = $VOP3Mods:src1:src1_modifiers
19150 : /*49521*/ OPC_MoveChild, 2,
19151 : /*49523*/ OPC_CheckOpcode, TARGET_VAL(ISD::CONDCODE),
19152 : /*49526*/ OPC_Scope, 24, /*->49552*/ // 16 children in Scope
19153 : /*49528*/ OPC_CheckPredicate, 126, // Predicate_COND_NULL
19154 : /*49530*/ OPC_MoveParent,
19155 : /*49531*/ OPC_CheckType, MVT::i1,
19156 : /*49533*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19157 : /*49536*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19158 : /*49539*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_F_F32_e64), 0,
19159 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19160 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19161 : // Dst: (V_CMP_F_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19162 : /*49552*/ /*Scope*/ 24, /*->49577*/
19163 : /*49553*/ OPC_CheckPredicate, 127, // Predicate_COND_OLT
19164 : /*49555*/ OPC_MoveParent,
19165 : /*49556*/ OPC_CheckType, MVT::i1,
19166 : /*49558*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19167 : /*49561*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19168 : /*49564*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LT_F32_e64), 0,
19169 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19170 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_OLT>>) - Complexity = -973
19171 : // Dst: (V_CMP_LT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19172 : /*49577*/ /*Scope*/ 24, /*->49602*/
19173 : /*49578*/ OPC_CheckPredicate, 103, // Predicate_COND_OEQ
19174 : /*49580*/ OPC_MoveParent,
19175 : /*49581*/ OPC_CheckType, MVT::i1,
19176 : /*49583*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19177 : /*49586*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19178 : /*49589*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_EQ_F32_e64), 0,
19179 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19180 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_OEQ>>) - Complexity = -973
19181 : // Dst: (V_CMP_EQ_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19182 : /*49602*/ /*Scope*/ 24, /*->49627*/
19183 : /*49603*/ OPC_CheckPredicate, 128, // Predicate_COND_OLE
19184 : /*49605*/ OPC_MoveParent,
19185 : /*49606*/ OPC_CheckType, MVT::i1,
19186 : /*49608*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19187 : /*49611*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19188 : /*49614*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LE_F32_e64), 0,
19189 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19190 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_OLE>>) - Complexity = -973
19191 : // Dst: (V_CMP_LE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19192 : /*49627*/ /*Scope*/ 24, /*->49652*/
19193 : /*49628*/ OPC_CheckPredicate, 104, // Predicate_COND_OGT
19194 : /*49630*/ OPC_MoveParent,
19195 : /*49631*/ OPC_CheckType, MVT::i1,
19196 : /*49633*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19197 : /*49636*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19198 : /*49639*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GT_F32_e64), 0,
19199 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19200 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_OGT>>) - Complexity = -973
19201 : // Dst: (V_CMP_GT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19202 : /*49652*/ /*Scope*/ 24, /*->49677*/
19203 : /*49653*/ OPC_CheckPredicate, 129, // Predicate_COND_ONE
19204 : /*49655*/ OPC_MoveParent,
19205 : /*49656*/ OPC_CheckType, MVT::i1,
19206 : /*49658*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19207 : /*49661*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19208 : /*49664*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LG_F32_e64), 0,
19209 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19210 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_ONE>>) - Complexity = -973
19211 : // Dst: (V_CMP_LG_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19212 : /*49677*/ /*Scope*/ 24, /*->49702*/
19213 : /*49678*/ OPC_CheckPredicate, 105, // Predicate_COND_OGE
19214 : /*49680*/ OPC_MoveParent,
19215 : /*49681*/ OPC_CheckType, MVT::i1,
19216 : /*49683*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19217 : /*49686*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19218 : /*49689*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GE_F32_e64), 0,
19219 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19220 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_OGE>>) - Complexity = -973
19221 : // Dst: (V_CMP_GE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19222 : /*49702*/ /*Scope*/ 24, /*->49727*/
19223 : /*49703*/ OPC_CheckPredicate, 130, // Predicate_COND_O
19224 : /*49705*/ OPC_MoveParent,
19225 : /*49706*/ OPC_CheckType, MVT::i1,
19226 : /*49708*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19227 : /*49711*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19228 : /*49714*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_O_F32_e64), 0,
19229 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19230 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_O>>) - Complexity = -973
19231 : // Dst: (V_CMP_O_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19232 : /*49727*/ /*Scope*/ 24, /*->49752*/
19233 : /*49728*/ OPC_CheckPredicate, 131, // Predicate_COND_UO
19234 : /*49730*/ OPC_MoveParent,
19235 : /*49731*/ OPC_CheckType, MVT::i1,
19236 : /*49733*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19237 : /*49736*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19238 : /*49739*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_U_F32_e64), 0,
19239 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19240 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_UO>>) - Complexity = -973
19241 : // Dst: (V_CMP_U_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19242 : /*49752*/ /*Scope*/ 24, /*->49777*/
19243 : /*49753*/ OPC_CheckPredicate, 132, // Predicate_COND_ULT
19244 : /*49755*/ OPC_MoveParent,
19245 : /*49756*/ OPC_CheckType, MVT::i1,
19246 : /*49758*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19247 : /*49761*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19248 : /*49764*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NGE_F32_e64), 0,
19249 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19250 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_ULT>>) - Complexity = -973
19251 : // Dst: (V_CMP_NGE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19252 : /*49777*/ /*Scope*/ 24, /*->49802*/
19253 : /*49778*/ OPC_CheckPredicate, 133, // Predicate_COND_UEQ
19254 : /*49780*/ OPC_MoveParent,
19255 : /*49781*/ OPC_CheckType, MVT::i1,
19256 : /*49783*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19257 : /*49786*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19258 : /*49789*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NLG_F32_e64), 0,
19259 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19260 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_UEQ>>) - Complexity = -973
19261 : // Dst: (V_CMP_NLG_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19262 : /*49802*/ /*Scope*/ 24, /*->49827*/
19263 : /*49803*/ OPC_CheckPredicate, 134, // Predicate_COND_ULE
19264 : /*49805*/ OPC_MoveParent,
19265 : /*49806*/ OPC_CheckType, MVT::i1,
19266 : /*49808*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19267 : /*49811*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19268 : /*49814*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NGT_F32_e64), 0,
19269 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19270 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_ULE>>) - Complexity = -973
19271 : // Dst: (V_CMP_NGT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19272 : /*49827*/ /*Scope*/ 24, /*->49852*/
19273 : /*49828*/ OPC_CheckPredicate, 135, // Predicate_COND_UGT
19274 : /*49830*/ OPC_MoveParent,
19275 : /*49831*/ OPC_CheckType, MVT::i1,
19276 : /*49833*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19277 : /*49836*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19278 : /*49839*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NLE_F32_e64), 0,
19279 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19280 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_UGT>>) - Complexity = -973
19281 : // Dst: (V_CMP_NLE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19282 : /*49852*/ /*Scope*/ 24, /*->49877*/
19283 : /*49853*/ OPC_CheckPredicate, 136, // Predicate_COND_UNE
19284 : /*49855*/ OPC_MoveParent,
19285 : /*49856*/ OPC_CheckType, MVT::i1,
19286 : /*49858*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19287 : /*49861*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19288 : /*49864*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NEQ_F32_e64), 0,
19289 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19290 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_UNE>>) - Complexity = -973
19291 : // Dst: (V_CMP_NEQ_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19292 : /*49877*/ /*Scope*/ 24, /*->49902*/
19293 : /*49878*/ OPC_CheckPredicate, 137, // Predicate_COND_UGE
19294 : /*49880*/ OPC_MoveParent,
19295 : /*49881*/ OPC_CheckType, MVT::i1,
19296 : /*49883*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19297 : /*49886*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19298 : /*49889*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NLT_F32_e64), 0,
19299 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19300 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_UGE>>) - Complexity = -973
19301 : // Dst: (V_CMP_NLT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19302 : /*49902*/ /*Scope*/ 59|128,5/*699*/, /*->50603*/
19303 : /*49904*/ OPC_CheckPredicate, 126, // Predicate_COND_NULL
19304 : /*49906*/ OPC_MoveParent,
19305 : /*49907*/ OPC_CheckType, MVT::i1,
19306 : /*49909*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19307 : /*49912*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19308 : /*49915*/ OPC_Scope, 13, /*->49930*/ // 49 children in Scope
19309 : /*49917*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_TRU_F32_e64), 0,
19310 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19311 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19312 : // Dst: (V_CMP_TRU_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19313 : /*49930*/ /*Scope*/ 13, /*->49944*/
19314 : /*49931*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_F_F32_e64), 0,
19315 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19316 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19317 : // Dst: (V_CMPX_F_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19318 : /*49944*/ /*Scope*/ 13, /*->49958*/
19319 : /*49945*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LT_F32_e64), 0,
19320 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19321 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19322 : // Dst: (V_CMPX_LT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19323 : /*49958*/ /*Scope*/ 13, /*->49972*/
19324 : /*49959*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_EQ_F32_e64), 0,
19325 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19326 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19327 : // Dst: (V_CMPX_EQ_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19328 : /*49972*/ /*Scope*/ 13, /*->49986*/
19329 : /*49973*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LE_F32_e64), 0,
19330 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19331 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19332 : // Dst: (V_CMPX_LE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19333 : /*49986*/ /*Scope*/ 13, /*->50000*/
19334 : /*49987*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GT_F32_e64), 0,
19335 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19336 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19337 : // Dst: (V_CMPX_GT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19338 : /*50000*/ /*Scope*/ 13, /*->50014*/
19339 : /*50001*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LG_F32_e64), 0,
19340 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19341 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19342 : // Dst: (V_CMPX_LG_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19343 : /*50014*/ /*Scope*/ 13, /*->50028*/
19344 : /*50015*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GE_F32_e64), 0,
19345 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19346 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19347 : // Dst: (V_CMPX_GE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19348 : /*50028*/ /*Scope*/ 13, /*->50042*/
19349 : /*50029*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_O_F32_e64), 0,
19350 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19351 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19352 : // Dst: (V_CMPX_O_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19353 : /*50042*/ /*Scope*/ 13, /*->50056*/
19354 : /*50043*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_U_F32_e64), 0,
19355 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19356 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19357 : // Dst: (V_CMPX_U_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19358 : /*50056*/ /*Scope*/ 13, /*->50070*/
19359 : /*50057*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NGE_F32_e64), 0,
19360 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19361 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19362 : // Dst: (V_CMPX_NGE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19363 : /*50070*/ /*Scope*/ 13, /*->50084*/
19364 : /*50071*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NLG_F32_e64), 0,
19365 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19366 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19367 : // Dst: (V_CMPX_NLG_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19368 : /*50084*/ /*Scope*/ 13, /*->50098*/
19369 : /*50085*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NGT_F32_e64), 0,
19370 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19371 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19372 : // Dst: (V_CMPX_NGT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19373 : /*50098*/ /*Scope*/ 13, /*->50112*/
19374 : /*50099*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NLE_F32_e64), 0,
19375 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19376 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19377 : // Dst: (V_CMPX_NLE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19378 : /*50112*/ /*Scope*/ 13, /*->50126*/
19379 : /*50113*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NEQ_F32_e64), 0,
19380 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19381 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19382 : // Dst: (V_CMPX_NEQ_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19383 : /*50126*/ /*Scope*/ 13, /*->50140*/
19384 : /*50127*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NLT_F32_e64), 0,
19385 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19386 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19387 : // Dst: (V_CMPX_NLT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19388 : /*50140*/ /*Scope*/ 13, /*->50154*/
19389 : /*50141*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_TRU_F32_e64), 0,
19390 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19391 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19392 : // Dst: (V_CMPX_TRU_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19393 : /*50154*/ /*Scope*/ 13, /*->50168*/
19394 : /*50155*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_F_F32_e64), 0,
19395 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19396 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19397 : // Dst: (V_CMPS_F_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19398 : /*50168*/ /*Scope*/ 13, /*->50182*/
19399 : /*50169*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_LT_F32_e64), 0,
19400 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19401 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19402 : // Dst: (V_CMPS_LT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19403 : /*50182*/ /*Scope*/ 13, /*->50196*/
19404 : /*50183*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_EQ_F32_e64), 0,
19405 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19406 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19407 : // Dst: (V_CMPS_EQ_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19408 : /*50196*/ /*Scope*/ 13, /*->50210*/
19409 : /*50197*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_LE_F32_e64), 0,
19410 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19411 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19412 : // Dst: (V_CMPS_LE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19413 : /*50210*/ /*Scope*/ 13, /*->50224*/
19414 : /*50211*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_GT_F32_e64), 0,
19415 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19416 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19417 : // Dst: (V_CMPS_GT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19418 : /*50224*/ /*Scope*/ 13, /*->50238*/
19419 : /*50225*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_LG_F32_e64), 0,
19420 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19421 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19422 : // Dst: (V_CMPS_LG_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19423 : /*50238*/ /*Scope*/ 13, /*->50252*/
19424 : /*50239*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_GE_F32_e64), 0,
19425 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19426 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19427 : // Dst: (V_CMPS_GE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19428 : /*50252*/ /*Scope*/ 13, /*->50266*/
19429 : /*50253*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_O_F32_e64), 0,
19430 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19431 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19432 : // Dst: (V_CMPS_O_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19433 : /*50266*/ /*Scope*/ 13, /*->50280*/
19434 : /*50267*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_U_F32_e64), 0,
19435 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19436 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19437 : // Dst: (V_CMPS_U_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19438 : /*50280*/ /*Scope*/ 13, /*->50294*/
19439 : /*50281*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NGE_F32_e64), 0,
19440 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19441 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19442 : // Dst: (V_CMPS_NGE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19443 : /*50294*/ /*Scope*/ 13, /*->50308*/
19444 : /*50295*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NLG_F32_e64), 0,
19445 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19446 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19447 : // Dst: (V_CMPS_NLG_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19448 : /*50308*/ /*Scope*/ 13, /*->50322*/
19449 : /*50309*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NGT_F32_e64), 0,
19450 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19451 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19452 : // Dst: (V_CMPS_NGT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19453 : /*50322*/ /*Scope*/ 13, /*->50336*/
19454 : /*50323*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NLE_F32_e64), 0,
19455 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19456 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19457 : // Dst: (V_CMPS_NLE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19458 : /*50336*/ /*Scope*/ 13, /*->50350*/
19459 : /*50337*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NEQ_F32_e64), 0,
19460 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19461 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19462 : // Dst: (V_CMPS_NEQ_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19463 : /*50350*/ /*Scope*/ 13, /*->50364*/
19464 : /*50351*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NLT_F32_e64), 0,
19465 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19466 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19467 : // Dst: (V_CMPS_NLT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19468 : /*50364*/ /*Scope*/ 13, /*->50378*/
19469 : /*50365*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_TRU_F32_e64), 0,
19470 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19471 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19472 : // Dst: (V_CMPS_TRU_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19473 : /*50378*/ /*Scope*/ 13, /*->50392*/
19474 : /*50379*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_F_F32_e64), 0,
19475 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19476 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19477 : // Dst: (V_CMPSX_F_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19478 : /*50392*/ /*Scope*/ 13, /*->50406*/
19479 : /*50393*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_LT_F32_e64), 0,
19480 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19481 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19482 : // Dst: (V_CMPSX_LT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19483 : /*50406*/ /*Scope*/ 13, /*->50420*/
19484 : /*50407*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_EQ_F32_e64), 0,
19485 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19486 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19487 : // Dst: (V_CMPSX_EQ_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19488 : /*50420*/ /*Scope*/ 13, /*->50434*/
19489 : /*50421*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_LE_F32_e64), 0,
19490 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19491 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19492 : // Dst: (V_CMPSX_LE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19493 : /*50434*/ /*Scope*/ 13, /*->50448*/
19494 : /*50435*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_GT_F32_e64), 0,
19495 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19496 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19497 : // Dst: (V_CMPSX_GT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19498 : /*50448*/ /*Scope*/ 13, /*->50462*/
19499 : /*50449*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_LG_F32_e64), 0,
19500 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19501 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19502 : // Dst: (V_CMPSX_LG_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19503 : /*50462*/ /*Scope*/ 13, /*->50476*/
19504 : /*50463*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_GE_F32_e64), 0,
19505 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19506 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19507 : // Dst: (V_CMPSX_GE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19508 : /*50476*/ /*Scope*/ 13, /*->50490*/
19509 : /*50477*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_O_F32_e64), 0,
19510 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19511 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19512 : // Dst: (V_CMPSX_O_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19513 : /*50490*/ /*Scope*/ 13, /*->50504*/
19514 : /*50491*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_U_F32_e64), 0,
19515 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19516 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19517 : // Dst: (V_CMPSX_U_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19518 : /*50504*/ /*Scope*/ 13, /*->50518*/
19519 : /*50505*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NGE_F32_e64), 0,
19520 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19521 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19522 : // Dst: (V_CMPSX_NGE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19523 : /*50518*/ /*Scope*/ 13, /*->50532*/
19524 : /*50519*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NLG_F32_e64), 0,
19525 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19526 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19527 : // Dst: (V_CMPSX_NLG_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19528 : /*50532*/ /*Scope*/ 13, /*->50546*/
19529 : /*50533*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NGT_F32_e64), 0,
19530 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19531 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19532 : // Dst: (V_CMPSX_NGT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19533 : /*50546*/ /*Scope*/ 13, /*->50560*/
19534 : /*50547*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NLE_F32_e64), 0,
19535 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19536 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19537 : // Dst: (V_CMPSX_NLE_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19538 : /*50560*/ /*Scope*/ 13, /*->50574*/
19539 : /*50561*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NEQ_F32_e64), 0,
19540 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19541 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19542 : // Dst: (V_CMPSX_NEQ_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19543 : /*50574*/ /*Scope*/ 13, /*->50588*/
19544 : /*50575*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NLT_F32_e64), 0,
19545 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19546 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19547 : // Dst: (V_CMPSX_NLT_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19548 : /*50588*/ /*Scope*/ 13, /*->50602*/
19549 : /*50589*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_TRU_F32_e64), 0,
19550 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19551 : // Src: (setcc:i1 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19552 : // Dst: (V_CMPSX_TRU_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
19553 : /*50602*/ 0, /*End of Scope*/
19554 : /*50603*/ 0, /*End of Scope*/
19555 : /*50604*/ /*Scope*/ 62|128,8/*1086*/, /*->51692*/
19556 : /*50606*/ OPC_CheckChild0Type, MVT::f64,
19557 : /*50608*/ OPC_RecordChild1, // #1 = $VOP3Mods:src1:src1_modifiers
19558 : /*50609*/ OPC_MoveChild, 2,
19559 : /*50611*/ OPC_CheckOpcode, TARGET_VAL(ISD::CONDCODE),
19560 : /*50614*/ OPC_Scope, 24, /*->50640*/ // 16 children in Scope
19561 : /*50616*/ OPC_CheckPredicate, 126, // Predicate_COND_NULL
19562 : /*50618*/ OPC_MoveParent,
19563 : /*50619*/ OPC_CheckType, MVT::i1,
19564 : /*50621*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19565 : /*50624*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19566 : /*50627*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_F_F64_e64), 0,
19567 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19568 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19569 : // Dst: (V_CMP_F_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19570 : /*50640*/ /*Scope*/ 24, /*->50665*/
19571 : /*50641*/ OPC_CheckPredicate, 127, // Predicate_COND_OLT
19572 : /*50643*/ OPC_MoveParent,
19573 : /*50644*/ OPC_CheckType, MVT::i1,
19574 : /*50646*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19575 : /*50649*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19576 : /*50652*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LT_F64_e64), 0,
19577 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19578 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_OLT>>) - Complexity = -973
19579 : // Dst: (V_CMP_LT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19580 : /*50665*/ /*Scope*/ 24, /*->50690*/
19581 : /*50666*/ OPC_CheckPredicate, 103, // Predicate_COND_OEQ
19582 : /*50668*/ OPC_MoveParent,
19583 : /*50669*/ OPC_CheckType, MVT::i1,
19584 : /*50671*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19585 : /*50674*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19586 : /*50677*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_EQ_F64_e64), 0,
19587 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19588 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_OEQ>>) - Complexity = -973
19589 : // Dst: (V_CMP_EQ_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19590 : /*50690*/ /*Scope*/ 24, /*->50715*/
19591 : /*50691*/ OPC_CheckPredicate, 128, // Predicate_COND_OLE
19592 : /*50693*/ OPC_MoveParent,
19593 : /*50694*/ OPC_CheckType, MVT::i1,
19594 : /*50696*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19595 : /*50699*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19596 : /*50702*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LE_F64_e64), 0,
19597 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19598 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_OLE>>) - Complexity = -973
19599 : // Dst: (V_CMP_LE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19600 : /*50715*/ /*Scope*/ 24, /*->50740*/
19601 : /*50716*/ OPC_CheckPredicate, 104, // Predicate_COND_OGT
19602 : /*50718*/ OPC_MoveParent,
19603 : /*50719*/ OPC_CheckType, MVT::i1,
19604 : /*50721*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19605 : /*50724*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19606 : /*50727*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GT_F64_e64), 0,
19607 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19608 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_OGT>>) - Complexity = -973
19609 : // Dst: (V_CMP_GT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19610 : /*50740*/ /*Scope*/ 24, /*->50765*/
19611 : /*50741*/ OPC_CheckPredicate, 129, // Predicate_COND_ONE
19612 : /*50743*/ OPC_MoveParent,
19613 : /*50744*/ OPC_CheckType, MVT::i1,
19614 : /*50746*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19615 : /*50749*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19616 : /*50752*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LG_F64_e64), 0,
19617 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19618 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_ONE>>) - Complexity = -973
19619 : // Dst: (V_CMP_LG_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19620 : /*50765*/ /*Scope*/ 24, /*->50790*/
19621 : /*50766*/ OPC_CheckPredicate, 105, // Predicate_COND_OGE
19622 : /*50768*/ OPC_MoveParent,
19623 : /*50769*/ OPC_CheckType, MVT::i1,
19624 : /*50771*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19625 : /*50774*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19626 : /*50777*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GE_F64_e64), 0,
19627 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19628 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_OGE>>) - Complexity = -973
19629 : // Dst: (V_CMP_GE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19630 : /*50790*/ /*Scope*/ 24, /*->50815*/
19631 : /*50791*/ OPC_CheckPredicate, 130, // Predicate_COND_O
19632 : /*50793*/ OPC_MoveParent,
19633 : /*50794*/ OPC_CheckType, MVT::i1,
19634 : /*50796*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19635 : /*50799*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19636 : /*50802*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_O_F64_e64), 0,
19637 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19638 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_O>>) - Complexity = -973
19639 : // Dst: (V_CMP_O_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19640 : /*50815*/ /*Scope*/ 24, /*->50840*/
19641 : /*50816*/ OPC_CheckPredicate, 131, // Predicate_COND_UO
19642 : /*50818*/ OPC_MoveParent,
19643 : /*50819*/ OPC_CheckType, MVT::i1,
19644 : /*50821*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19645 : /*50824*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19646 : /*50827*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_U_F64_e64), 0,
19647 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19648 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_UO>>) - Complexity = -973
19649 : // Dst: (V_CMP_U_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19650 : /*50840*/ /*Scope*/ 24, /*->50865*/
19651 : /*50841*/ OPC_CheckPredicate, 132, // Predicate_COND_ULT
19652 : /*50843*/ OPC_MoveParent,
19653 : /*50844*/ OPC_CheckType, MVT::i1,
19654 : /*50846*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19655 : /*50849*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19656 : /*50852*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NGE_F64_e64), 0,
19657 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19658 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_ULT>>) - Complexity = -973
19659 : // Dst: (V_CMP_NGE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19660 : /*50865*/ /*Scope*/ 24, /*->50890*/
19661 : /*50866*/ OPC_CheckPredicate, 133, // Predicate_COND_UEQ
19662 : /*50868*/ OPC_MoveParent,
19663 : /*50869*/ OPC_CheckType, MVT::i1,
19664 : /*50871*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19665 : /*50874*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19666 : /*50877*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NLG_F64_e64), 0,
19667 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19668 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_UEQ>>) - Complexity = -973
19669 : // Dst: (V_CMP_NLG_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19670 : /*50890*/ /*Scope*/ 24, /*->50915*/
19671 : /*50891*/ OPC_CheckPredicate, 134, // Predicate_COND_ULE
19672 : /*50893*/ OPC_MoveParent,
19673 : /*50894*/ OPC_CheckType, MVT::i1,
19674 : /*50896*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19675 : /*50899*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19676 : /*50902*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NGT_F64_e64), 0,
19677 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19678 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_ULE>>) - Complexity = -973
19679 : // Dst: (V_CMP_NGT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19680 : /*50915*/ /*Scope*/ 24, /*->50940*/
19681 : /*50916*/ OPC_CheckPredicate, 135, // Predicate_COND_UGT
19682 : /*50918*/ OPC_MoveParent,
19683 : /*50919*/ OPC_CheckType, MVT::i1,
19684 : /*50921*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19685 : /*50924*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19686 : /*50927*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NLE_F64_e64), 0,
19687 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19688 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_UGT>>) - Complexity = -973
19689 : // Dst: (V_CMP_NLE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19690 : /*50940*/ /*Scope*/ 24, /*->50965*/
19691 : /*50941*/ OPC_CheckPredicate, 136, // Predicate_COND_UNE
19692 : /*50943*/ OPC_MoveParent,
19693 : /*50944*/ OPC_CheckType, MVT::i1,
19694 : /*50946*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19695 : /*50949*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19696 : /*50952*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NEQ_F64_e64), 0,
19697 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19698 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_UNE>>) - Complexity = -973
19699 : // Dst: (V_CMP_NEQ_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19700 : /*50965*/ /*Scope*/ 24, /*->50990*/
19701 : /*50966*/ OPC_CheckPredicate, 137, // Predicate_COND_UGE
19702 : /*50968*/ OPC_MoveParent,
19703 : /*50969*/ OPC_CheckType, MVT::i1,
19704 : /*50971*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19705 : /*50974*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19706 : /*50977*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NLT_F64_e64), 0,
19707 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19708 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_UGE>>) - Complexity = -973
19709 : // Dst: (V_CMP_NLT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19710 : /*50990*/ /*Scope*/ 59|128,5/*699*/, /*->51691*/
19711 : /*50992*/ OPC_CheckPredicate, 126, // Predicate_COND_NULL
19712 : /*50994*/ OPC_MoveParent,
19713 : /*50995*/ OPC_CheckType, MVT::i1,
19714 : /*50997*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
19715 : /*51000*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
19716 : /*51003*/ OPC_Scope, 13, /*->51018*/ // 49 children in Scope
19717 : /*51005*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_TRU_F64_e64), 0,
19718 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19719 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19720 : // Dst: (V_CMP_TRU_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19721 : /*51018*/ /*Scope*/ 13, /*->51032*/
19722 : /*51019*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_F_F64_e64), 0,
19723 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19724 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19725 : // Dst: (V_CMPX_F_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19726 : /*51032*/ /*Scope*/ 13, /*->51046*/
19727 : /*51033*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LT_F64_e64), 0,
19728 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19729 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19730 : // Dst: (V_CMPX_LT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19731 : /*51046*/ /*Scope*/ 13, /*->51060*/
19732 : /*51047*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_EQ_F64_e64), 0,
19733 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19734 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19735 : // Dst: (V_CMPX_EQ_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19736 : /*51060*/ /*Scope*/ 13, /*->51074*/
19737 : /*51061*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LE_F64_e64), 0,
19738 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19739 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19740 : // Dst: (V_CMPX_LE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19741 : /*51074*/ /*Scope*/ 13, /*->51088*/
19742 : /*51075*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GT_F64_e64), 0,
19743 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19744 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19745 : // Dst: (V_CMPX_GT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19746 : /*51088*/ /*Scope*/ 13, /*->51102*/
19747 : /*51089*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LG_F64_e64), 0,
19748 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19749 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19750 : // Dst: (V_CMPX_LG_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19751 : /*51102*/ /*Scope*/ 13, /*->51116*/
19752 : /*51103*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GE_F64_e64), 0,
19753 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19754 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19755 : // Dst: (V_CMPX_GE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19756 : /*51116*/ /*Scope*/ 13, /*->51130*/
19757 : /*51117*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_O_F64_e64), 0,
19758 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19759 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19760 : // Dst: (V_CMPX_O_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19761 : /*51130*/ /*Scope*/ 13, /*->51144*/
19762 : /*51131*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_U_F64_e64), 0,
19763 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19764 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19765 : // Dst: (V_CMPX_U_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19766 : /*51144*/ /*Scope*/ 13, /*->51158*/
19767 : /*51145*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NGE_F64_e64), 0,
19768 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19769 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19770 : // Dst: (V_CMPX_NGE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19771 : /*51158*/ /*Scope*/ 13, /*->51172*/
19772 : /*51159*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NLG_F64_e64), 0,
19773 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19774 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19775 : // Dst: (V_CMPX_NLG_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19776 : /*51172*/ /*Scope*/ 13, /*->51186*/
19777 : /*51173*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NGT_F64_e64), 0,
19778 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19779 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19780 : // Dst: (V_CMPX_NGT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19781 : /*51186*/ /*Scope*/ 13, /*->51200*/
19782 : /*51187*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NLE_F64_e64), 0,
19783 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19784 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19785 : // Dst: (V_CMPX_NLE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19786 : /*51200*/ /*Scope*/ 13, /*->51214*/
19787 : /*51201*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NEQ_F64_e64), 0,
19788 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19789 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19790 : // Dst: (V_CMPX_NEQ_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19791 : /*51214*/ /*Scope*/ 13, /*->51228*/
19792 : /*51215*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NLT_F64_e64), 0,
19793 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19794 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19795 : // Dst: (V_CMPX_NLT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19796 : /*51228*/ /*Scope*/ 13, /*->51242*/
19797 : /*51229*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_TRU_F64_e64), 0,
19798 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19799 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19800 : // Dst: (V_CMPX_TRU_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19801 : /*51242*/ /*Scope*/ 13, /*->51256*/
19802 : /*51243*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_F_F64_e64), 0,
19803 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19804 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19805 : // Dst: (V_CMPS_F_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19806 : /*51256*/ /*Scope*/ 13, /*->51270*/
19807 : /*51257*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_LT_F64_e64), 0,
19808 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19809 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19810 : // Dst: (V_CMPS_LT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19811 : /*51270*/ /*Scope*/ 13, /*->51284*/
19812 : /*51271*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_EQ_F64_e64), 0,
19813 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19814 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19815 : // Dst: (V_CMPS_EQ_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19816 : /*51284*/ /*Scope*/ 13, /*->51298*/
19817 : /*51285*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_LE_F64_e64), 0,
19818 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19819 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19820 : // Dst: (V_CMPS_LE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19821 : /*51298*/ /*Scope*/ 13, /*->51312*/
19822 : /*51299*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_GT_F64_e64), 0,
19823 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19824 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19825 : // Dst: (V_CMPS_GT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19826 : /*51312*/ /*Scope*/ 13, /*->51326*/
19827 : /*51313*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_LG_F64_e64), 0,
19828 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19829 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19830 : // Dst: (V_CMPS_LG_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19831 : /*51326*/ /*Scope*/ 13, /*->51340*/
19832 : /*51327*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_GE_F64_e64), 0,
19833 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19834 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19835 : // Dst: (V_CMPS_GE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19836 : /*51340*/ /*Scope*/ 13, /*->51354*/
19837 : /*51341*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_O_F64_e64), 0,
19838 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19839 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19840 : // Dst: (V_CMPS_O_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19841 : /*51354*/ /*Scope*/ 13, /*->51368*/
19842 : /*51355*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_U_F64_e64), 0,
19843 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19844 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19845 : // Dst: (V_CMPS_U_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19846 : /*51368*/ /*Scope*/ 13, /*->51382*/
19847 : /*51369*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NGE_F64_e64), 0,
19848 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19849 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19850 : // Dst: (V_CMPS_NGE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19851 : /*51382*/ /*Scope*/ 13, /*->51396*/
19852 : /*51383*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NLG_F64_e64), 0,
19853 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19854 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19855 : // Dst: (V_CMPS_NLG_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19856 : /*51396*/ /*Scope*/ 13, /*->51410*/
19857 : /*51397*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NGT_F64_e64), 0,
19858 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19859 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19860 : // Dst: (V_CMPS_NGT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19861 : /*51410*/ /*Scope*/ 13, /*->51424*/
19862 : /*51411*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NLE_F64_e64), 0,
19863 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19864 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19865 : // Dst: (V_CMPS_NLE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19866 : /*51424*/ /*Scope*/ 13, /*->51438*/
19867 : /*51425*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NEQ_F64_e64), 0,
19868 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19869 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19870 : // Dst: (V_CMPS_NEQ_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19871 : /*51438*/ /*Scope*/ 13, /*->51452*/
19872 : /*51439*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_NLT_F64_e64), 0,
19873 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19874 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19875 : // Dst: (V_CMPS_NLT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19876 : /*51452*/ /*Scope*/ 13, /*->51466*/
19877 : /*51453*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPS_TRU_F64_e64), 0,
19878 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19879 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19880 : // Dst: (V_CMPS_TRU_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19881 : /*51466*/ /*Scope*/ 13, /*->51480*/
19882 : /*51467*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_F_F64_e64), 0,
19883 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19884 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19885 : // Dst: (V_CMPSX_F_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19886 : /*51480*/ /*Scope*/ 13, /*->51494*/
19887 : /*51481*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_LT_F64_e64), 0,
19888 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19889 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19890 : // Dst: (V_CMPSX_LT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19891 : /*51494*/ /*Scope*/ 13, /*->51508*/
19892 : /*51495*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_EQ_F64_e64), 0,
19893 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19894 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19895 : // Dst: (V_CMPSX_EQ_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19896 : /*51508*/ /*Scope*/ 13, /*->51522*/
19897 : /*51509*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_LE_F64_e64), 0,
19898 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19899 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19900 : // Dst: (V_CMPSX_LE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19901 : /*51522*/ /*Scope*/ 13, /*->51536*/
19902 : /*51523*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_GT_F64_e64), 0,
19903 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19904 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19905 : // Dst: (V_CMPSX_GT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19906 : /*51536*/ /*Scope*/ 13, /*->51550*/
19907 : /*51537*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_LG_F64_e64), 0,
19908 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19909 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19910 : // Dst: (V_CMPSX_LG_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19911 : /*51550*/ /*Scope*/ 13, /*->51564*/
19912 : /*51551*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_GE_F64_e64), 0,
19913 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19914 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19915 : // Dst: (V_CMPSX_GE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19916 : /*51564*/ /*Scope*/ 13, /*->51578*/
19917 : /*51565*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_O_F64_e64), 0,
19918 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19919 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19920 : // Dst: (V_CMPSX_O_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19921 : /*51578*/ /*Scope*/ 13, /*->51592*/
19922 : /*51579*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_U_F64_e64), 0,
19923 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19924 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19925 : // Dst: (V_CMPSX_U_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19926 : /*51592*/ /*Scope*/ 13, /*->51606*/
19927 : /*51593*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NGE_F64_e64), 0,
19928 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19929 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19930 : // Dst: (V_CMPSX_NGE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19931 : /*51606*/ /*Scope*/ 13, /*->51620*/
19932 : /*51607*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NLG_F64_e64), 0,
19933 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19934 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19935 : // Dst: (V_CMPSX_NLG_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19936 : /*51620*/ /*Scope*/ 13, /*->51634*/
19937 : /*51621*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NGT_F64_e64), 0,
19938 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19939 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19940 : // Dst: (V_CMPSX_NGT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19941 : /*51634*/ /*Scope*/ 13, /*->51648*/
19942 : /*51635*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NLE_F64_e64), 0,
19943 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19944 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19945 : // Dst: (V_CMPSX_NLE_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19946 : /*51648*/ /*Scope*/ 13, /*->51662*/
19947 : /*51649*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NEQ_F64_e64), 0,
19948 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19949 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19950 : // Dst: (V_CMPSX_NEQ_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19951 : /*51662*/ /*Scope*/ 13, /*->51676*/
19952 : /*51663*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_NLT_F64_e64), 0,
19953 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19954 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19955 : // Dst: (V_CMPSX_NLT_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19956 : /*51676*/ /*Scope*/ 13, /*->51690*/
19957 : /*51677*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPSX_TRU_F64_e64), 0,
19958 : 1/*#VTs*/, MVT::i1, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
19959 : // Src: (setcc:i1 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -973
19960 : // Dst: (V_CMPSX_TRU_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
19961 : /*51690*/ 0, /*End of Scope*/
19962 : /*51691*/ 0, /*End of Scope*/
19963 : /*51692*/ /*Scope*/ 27|128,3/*411*/, /*->52105*/
19964 : /*51694*/ OPC_CheckChild0Type, MVT::i32,
19965 : /*51696*/ OPC_RecordChild1, // #1 = $src1
19966 : /*51697*/ OPC_MoveChild, 2,
19967 : /*51699*/ OPC_CheckOpcode, TARGET_VAL(ISD::CONDCODE),
19968 : /*51702*/ OPC_Scope, 14, /*->51718*/ // 15 children in Scope
19969 : /*51704*/ OPC_CheckPredicate, 126, // Predicate_COND_NULL
19970 : /*51706*/ OPC_MoveParent,
19971 : /*51707*/ OPC_CheckType, MVT::i1,
19972 : /*51709*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_F_I32_e64), 0,
19973 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
19974 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
19975 : // Dst: (V_CMP_F_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
19976 : /*51718*/ /*Scope*/ 14, /*->51733*/
19977 : /*51719*/ OPC_CheckPredicate, 138, // Predicate_COND_SLT
19978 : /*51721*/ OPC_MoveParent,
19979 : /*51722*/ OPC_CheckType, MVT::i1,
19980 : /*51724*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LT_I32_e64), 0,
19981 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
19982 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_SLT>>) - Complexity = -997
19983 : // Dst: (V_CMP_LT_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
19984 : /*51733*/ /*Scope*/ 14, /*->51748*/
19985 : /*51734*/ OPC_CheckPredicate, 109, // Predicate_COND_EQ
19986 : /*51736*/ OPC_MoveParent,
19987 : /*51737*/ OPC_CheckType, MVT::i1,
19988 : /*51739*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_EQ_I32_e64), 0,
19989 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
19990 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_EQ>>) - Complexity = -997
19991 : // Dst: (V_CMP_EQ_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
19992 : /*51748*/ /*Scope*/ 14, /*->51763*/
19993 : /*51749*/ OPC_CheckPredicate, 139, // Predicate_COND_SLE
19994 : /*51751*/ OPC_MoveParent,
19995 : /*51752*/ OPC_CheckType, MVT::i1,
19996 : /*51754*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LE_I32_e64), 0,
19997 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
19998 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_SLE>>) - Complexity = -997
19999 : // Dst: (V_CMP_LE_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20000 : /*51763*/ /*Scope*/ 14, /*->51778*/
20001 : /*51764*/ OPC_CheckPredicate, 111, // Predicate_COND_SGT
20002 : /*51766*/ OPC_MoveParent,
20003 : /*51767*/ OPC_CheckType, MVT::i1,
20004 : /*51769*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GT_I32_e64), 0,
20005 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20006 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_SGT>>) - Complexity = -997
20007 : // Dst: (V_CMP_GT_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20008 : /*51778*/ /*Scope*/ 14, /*->51793*/
20009 : /*51779*/ OPC_CheckPredicate, 140, // Predicate_COND_NE
20010 : /*51781*/ OPC_MoveParent,
20011 : /*51782*/ OPC_CheckType, MVT::i1,
20012 : /*51784*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NE_I32_e64), 0,
20013 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20014 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NE>>) - Complexity = -997
20015 : // Dst: (V_CMP_NE_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20016 : /*51793*/ /*Scope*/ 14, /*->51808*/
20017 : /*51794*/ OPC_CheckPredicate, 110, // Predicate_COND_SGE
20018 : /*51796*/ OPC_MoveParent,
20019 : /*51797*/ OPC_CheckType, MVT::i1,
20020 : /*51799*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GE_I32_e64), 0,
20021 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20022 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_SGE>>) - Complexity = -997
20023 : // Dst: (V_CMP_GE_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20024 : /*51808*/ /*Scope*/ 107, /*->51916*/
20025 : /*51809*/ OPC_CheckPredicate, 126, // Predicate_COND_NULL
20026 : /*51811*/ OPC_MoveParent,
20027 : /*51812*/ OPC_CheckType, MVT::i1,
20028 : /*51814*/ OPC_Scope, 9, /*->51825*/ // 10 children in Scope
20029 : /*51816*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_T_I32_e64), 0,
20030 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20031 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20032 : // Dst: (V_CMP_T_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20033 : /*51825*/ /*Scope*/ 9, /*->51835*/
20034 : /*51826*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_F_I32_e64), 0,
20035 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20036 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20037 : // Dst: (V_CMPX_F_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20038 : /*51835*/ /*Scope*/ 9, /*->51845*/
20039 : /*51836*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LT_I32_e64), 0,
20040 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20041 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20042 : // Dst: (V_CMPX_LT_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20043 : /*51845*/ /*Scope*/ 9, /*->51855*/
20044 : /*51846*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_EQ_I32_e64), 0,
20045 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20046 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20047 : // Dst: (V_CMPX_EQ_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20048 : /*51855*/ /*Scope*/ 9, /*->51865*/
20049 : /*51856*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LE_I32_e64), 0,
20050 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20051 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20052 : // Dst: (V_CMPX_LE_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20053 : /*51865*/ /*Scope*/ 9, /*->51875*/
20054 : /*51866*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GT_I32_e64), 0,
20055 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20056 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20057 : // Dst: (V_CMPX_GT_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20058 : /*51875*/ /*Scope*/ 9, /*->51885*/
20059 : /*51876*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NE_I32_e64), 0,
20060 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20061 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20062 : // Dst: (V_CMPX_NE_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20063 : /*51885*/ /*Scope*/ 9, /*->51895*/
20064 : /*51886*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GE_I32_e64), 0,
20065 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20066 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20067 : // Dst: (V_CMPX_GE_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20068 : /*51895*/ /*Scope*/ 9, /*->51905*/
20069 : /*51896*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_T_I32_e64), 0,
20070 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20071 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20072 : // Dst: (V_CMPX_T_I32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20073 : /*51905*/ /*Scope*/ 9, /*->51915*/
20074 : /*51906*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_F_U32_e64), 0,
20075 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20076 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20077 : // Dst: (V_CMP_F_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20078 : /*51915*/ 0, /*End of Scope*/
20079 : /*51916*/ /*Scope*/ 14, /*->51931*/
20080 : /*51917*/ OPC_CheckPredicate, 132, // Predicate_COND_ULT
20081 : /*51919*/ OPC_MoveParent,
20082 : /*51920*/ OPC_CheckType, MVT::i1,
20083 : /*51922*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LT_U32_e64), 0,
20084 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20085 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_ULT>>) - Complexity = -997
20086 : // Dst: (V_CMP_LT_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20087 : /*51931*/ /*Scope*/ 14, /*->51946*/
20088 : /*51932*/ OPC_CheckPredicate, 109, // Predicate_COND_EQ
20089 : /*51934*/ OPC_MoveParent,
20090 : /*51935*/ OPC_CheckType, MVT::i1,
20091 : /*51937*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_EQ_U32_e64), 0,
20092 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20093 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_EQ>>) - Complexity = -997
20094 : // Dst: (V_CMP_EQ_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20095 : /*51946*/ /*Scope*/ 14, /*->51961*/
20096 : /*51947*/ OPC_CheckPredicate, 134, // Predicate_COND_ULE
20097 : /*51949*/ OPC_MoveParent,
20098 : /*51950*/ OPC_CheckType, MVT::i1,
20099 : /*51952*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LE_U32_e64), 0,
20100 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20101 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_ULE>>) - Complexity = -997
20102 : // Dst: (V_CMP_LE_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20103 : /*51961*/ /*Scope*/ 14, /*->51976*/
20104 : /*51962*/ OPC_CheckPredicate, 135, // Predicate_COND_UGT
20105 : /*51964*/ OPC_MoveParent,
20106 : /*51965*/ OPC_CheckType, MVT::i1,
20107 : /*51967*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GT_U32_e64), 0,
20108 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20109 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_UGT>>) - Complexity = -997
20110 : // Dst: (V_CMP_GT_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20111 : /*51976*/ /*Scope*/ 14, /*->51991*/
20112 : /*51977*/ OPC_CheckPredicate, 140, // Predicate_COND_NE
20113 : /*51979*/ OPC_MoveParent,
20114 : /*51980*/ OPC_CheckType, MVT::i1,
20115 : /*51982*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NE_U32_e64), 0,
20116 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20117 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NE>>) - Complexity = -997
20118 : // Dst: (V_CMP_NE_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20119 : /*51991*/ /*Scope*/ 14, /*->52006*/
20120 : /*51992*/ OPC_CheckPredicate, 137, // Predicate_COND_UGE
20121 : /*51994*/ OPC_MoveParent,
20122 : /*51995*/ OPC_CheckType, MVT::i1,
20123 : /*51997*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GE_U32_e64), 0,
20124 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20125 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_UGE>>) - Complexity = -997
20126 : // Dst: (V_CMP_GE_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20127 : /*52006*/ /*Scope*/ 97, /*->52104*/
20128 : /*52007*/ OPC_CheckPredicate, 126, // Predicate_COND_NULL
20129 : /*52009*/ OPC_MoveParent,
20130 : /*52010*/ OPC_CheckType, MVT::i1,
20131 : /*52012*/ OPC_Scope, 9, /*->52023*/ // 9 children in Scope
20132 : /*52014*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_T_U32_e64), 0,
20133 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20134 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20135 : // Dst: (V_CMP_T_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20136 : /*52023*/ /*Scope*/ 9, /*->52033*/
20137 : /*52024*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_F_U32_e64), 0,
20138 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20139 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20140 : // Dst: (V_CMPX_F_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20141 : /*52033*/ /*Scope*/ 9, /*->52043*/
20142 : /*52034*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LT_U32_e64), 0,
20143 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20144 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20145 : // Dst: (V_CMPX_LT_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20146 : /*52043*/ /*Scope*/ 9, /*->52053*/
20147 : /*52044*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_EQ_U32_e64), 0,
20148 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20149 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20150 : // Dst: (V_CMPX_EQ_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20151 : /*52053*/ /*Scope*/ 9, /*->52063*/
20152 : /*52054*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LE_U32_e64), 0,
20153 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20154 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20155 : // Dst: (V_CMPX_LE_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20156 : /*52063*/ /*Scope*/ 9, /*->52073*/
20157 : /*52064*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GT_U32_e64), 0,
20158 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20159 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20160 : // Dst: (V_CMPX_GT_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20161 : /*52073*/ /*Scope*/ 9, /*->52083*/
20162 : /*52074*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NE_U32_e64), 0,
20163 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20164 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20165 : // Dst: (V_CMPX_NE_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20166 : /*52083*/ /*Scope*/ 9, /*->52093*/
20167 : /*52084*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GE_U32_e64), 0,
20168 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20169 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20170 : // Dst: (V_CMPX_GE_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20171 : /*52093*/ /*Scope*/ 9, /*->52103*/
20172 : /*52094*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_T_U32_e64), 0,
20173 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20174 : // Src: (setcc:i1 i32:i32:$src0, i32:i32:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20175 : // Dst: (V_CMPX_T_U32_e64:i1 i32:i32:$src0, i32:i32:$src1)
20176 : /*52103*/ 0, /*End of Scope*/
20177 : /*52104*/ 0, /*End of Scope*/
20178 : /*52105*/ /*Scope*/ 27|128,3/*411*/, /*->52518*/
20179 : /*52107*/ OPC_CheckChild0Type, MVT::i64,
20180 : /*52109*/ OPC_RecordChild1, // #1 = $src1
20181 : /*52110*/ OPC_MoveChild, 2,
20182 : /*52112*/ OPC_CheckOpcode, TARGET_VAL(ISD::CONDCODE),
20183 : /*52115*/ OPC_Scope, 14, /*->52131*/ // 15 children in Scope
20184 : /*52117*/ OPC_CheckPredicate, 126, // Predicate_COND_NULL
20185 : /*52119*/ OPC_MoveParent,
20186 : /*52120*/ OPC_CheckType, MVT::i1,
20187 : /*52122*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_F_I64_e64), 0,
20188 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20189 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20190 : // Dst: (V_CMP_F_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20191 : /*52131*/ /*Scope*/ 14, /*->52146*/
20192 : /*52132*/ OPC_CheckPredicate, 138, // Predicate_COND_SLT
20193 : /*52134*/ OPC_MoveParent,
20194 : /*52135*/ OPC_CheckType, MVT::i1,
20195 : /*52137*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LT_I64_e64), 0,
20196 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20197 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_SLT>>) - Complexity = -997
20198 : // Dst: (V_CMP_LT_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20199 : /*52146*/ /*Scope*/ 14, /*->52161*/
20200 : /*52147*/ OPC_CheckPredicate, 109, // Predicate_COND_EQ
20201 : /*52149*/ OPC_MoveParent,
20202 : /*52150*/ OPC_CheckType, MVT::i1,
20203 : /*52152*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_EQ_I64_e64), 0,
20204 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20205 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_EQ>>) - Complexity = -997
20206 : // Dst: (V_CMP_EQ_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20207 : /*52161*/ /*Scope*/ 14, /*->52176*/
20208 : /*52162*/ OPC_CheckPredicate, 139, // Predicate_COND_SLE
20209 : /*52164*/ OPC_MoveParent,
20210 : /*52165*/ OPC_CheckType, MVT::i1,
20211 : /*52167*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LE_I64_e64), 0,
20212 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20213 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_SLE>>) - Complexity = -997
20214 : // Dst: (V_CMP_LE_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20215 : /*52176*/ /*Scope*/ 14, /*->52191*/
20216 : /*52177*/ OPC_CheckPredicate, 111, // Predicate_COND_SGT
20217 : /*52179*/ OPC_MoveParent,
20218 : /*52180*/ OPC_CheckType, MVT::i1,
20219 : /*52182*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GT_I64_e64), 0,
20220 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20221 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_SGT>>) - Complexity = -997
20222 : // Dst: (V_CMP_GT_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20223 : /*52191*/ /*Scope*/ 14, /*->52206*/
20224 : /*52192*/ OPC_CheckPredicate, 140, // Predicate_COND_NE
20225 : /*52194*/ OPC_MoveParent,
20226 : /*52195*/ OPC_CheckType, MVT::i1,
20227 : /*52197*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NE_I64_e64), 0,
20228 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20229 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NE>>) - Complexity = -997
20230 : // Dst: (V_CMP_NE_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20231 : /*52206*/ /*Scope*/ 14, /*->52221*/
20232 : /*52207*/ OPC_CheckPredicate, 110, // Predicate_COND_SGE
20233 : /*52209*/ OPC_MoveParent,
20234 : /*52210*/ OPC_CheckType, MVT::i1,
20235 : /*52212*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GE_I64_e64), 0,
20236 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20237 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_SGE>>) - Complexity = -997
20238 : // Dst: (V_CMP_GE_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20239 : /*52221*/ /*Scope*/ 107, /*->52329*/
20240 : /*52222*/ OPC_CheckPredicate, 126, // Predicate_COND_NULL
20241 : /*52224*/ OPC_MoveParent,
20242 : /*52225*/ OPC_CheckType, MVT::i1,
20243 : /*52227*/ OPC_Scope, 9, /*->52238*/ // 10 children in Scope
20244 : /*52229*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_T_I64_e64), 0,
20245 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20246 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20247 : // Dst: (V_CMP_T_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20248 : /*52238*/ /*Scope*/ 9, /*->52248*/
20249 : /*52239*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_F_I64_e64), 0,
20250 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20251 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20252 : // Dst: (V_CMPX_F_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20253 : /*52248*/ /*Scope*/ 9, /*->52258*/
20254 : /*52249*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LT_I64_e64), 0,
20255 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20256 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20257 : // Dst: (V_CMPX_LT_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20258 : /*52258*/ /*Scope*/ 9, /*->52268*/
20259 : /*52259*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_EQ_I64_e64), 0,
20260 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20261 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20262 : // Dst: (V_CMPX_EQ_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20263 : /*52268*/ /*Scope*/ 9, /*->52278*/
20264 : /*52269*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LE_I64_e64), 0,
20265 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20266 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20267 : // Dst: (V_CMPX_LE_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20268 : /*52278*/ /*Scope*/ 9, /*->52288*/
20269 : /*52279*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GT_I64_e64), 0,
20270 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20271 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20272 : // Dst: (V_CMPX_GT_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20273 : /*52288*/ /*Scope*/ 9, /*->52298*/
20274 : /*52289*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NE_I64_e64), 0,
20275 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20276 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20277 : // Dst: (V_CMPX_NE_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20278 : /*52298*/ /*Scope*/ 9, /*->52308*/
20279 : /*52299*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GE_I64_e64), 0,
20280 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20281 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20282 : // Dst: (V_CMPX_GE_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20283 : /*52308*/ /*Scope*/ 9, /*->52318*/
20284 : /*52309*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_T_I64_e64), 0,
20285 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20286 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20287 : // Dst: (V_CMPX_T_I64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20288 : /*52318*/ /*Scope*/ 9, /*->52328*/
20289 : /*52319*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_F_U64_e64), 0,
20290 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20291 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20292 : // Dst: (V_CMP_F_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20293 : /*52328*/ 0, /*End of Scope*/
20294 : /*52329*/ /*Scope*/ 14, /*->52344*/
20295 : /*52330*/ OPC_CheckPredicate, 132, // Predicate_COND_ULT
20296 : /*52332*/ OPC_MoveParent,
20297 : /*52333*/ OPC_CheckType, MVT::i1,
20298 : /*52335*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LT_U64_e64), 0,
20299 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20300 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_ULT>>) - Complexity = -997
20301 : // Dst: (V_CMP_LT_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20302 : /*52344*/ /*Scope*/ 14, /*->52359*/
20303 : /*52345*/ OPC_CheckPredicate, 109, // Predicate_COND_EQ
20304 : /*52347*/ OPC_MoveParent,
20305 : /*52348*/ OPC_CheckType, MVT::i1,
20306 : /*52350*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_EQ_U64_e64), 0,
20307 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20308 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_EQ>>) - Complexity = -997
20309 : // Dst: (V_CMP_EQ_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20310 : /*52359*/ /*Scope*/ 14, /*->52374*/
20311 : /*52360*/ OPC_CheckPredicate, 134, // Predicate_COND_ULE
20312 : /*52362*/ OPC_MoveParent,
20313 : /*52363*/ OPC_CheckType, MVT::i1,
20314 : /*52365*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_LE_U64_e64), 0,
20315 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20316 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_ULE>>) - Complexity = -997
20317 : // Dst: (V_CMP_LE_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20318 : /*52374*/ /*Scope*/ 14, /*->52389*/
20319 : /*52375*/ OPC_CheckPredicate, 135, // Predicate_COND_UGT
20320 : /*52377*/ OPC_MoveParent,
20321 : /*52378*/ OPC_CheckType, MVT::i1,
20322 : /*52380*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GT_U64_e64), 0,
20323 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20324 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_UGT>>) - Complexity = -997
20325 : // Dst: (V_CMP_GT_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20326 : /*52389*/ /*Scope*/ 14, /*->52404*/
20327 : /*52390*/ OPC_CheckPredicate, 140, // Predicate_COND_NE
20328 : /*52392*/ OPC_MoveParent,
20329 : /*52393*/ OPC_CheckType, MVT::i1,
20330 : /*52395*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_NE_U64_e64), 0,
20331 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20332 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NE>>) - Complexity = -997
20333 : // Dst: (V_CMP_NE_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20334 : /*52404*/ /*Scope*/ 14, /*->52419*/
20335 : /*52405*/ OPC_CheckPredicate, 137, // Predicate_COND_UGE
20336 : /*52407*/ OPC_MoveParent,
20337 : /*52408*/ OPC_CheckType, MVT::i1,
20338 : /*52410*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_GE_U64_e64), 0,
20339 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20340 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_UGE>>) - Complexity = -997
20341 : // Dst: (V_CMP_GE_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20342 : /*52419*/ /*Scope*/ 97, /*->52517*/
20343 : /*52420*/ OPC_CheckPredicate, 126, // Predicate_COND_NULL
20344 : /*52422*/ OPC_MoveParent,
20345 : /*52423*/ OPC_CheckType, MVT::i1,
20346 : /*52425*/ OPC_Scope, 9, /*->52436*/ // 9 children in Scope
20347 : /*52427*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_T_U64_e64), 0,
20348 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20349 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20350 : // Dst: (V_CMP_T_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20351 : /*52436*/ /*Scope*/ 9, /*->52446*/
20352 : /*52437*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_F_U64_e64), 0,
20353 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20354 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20355 : // Dst: (V_CMPX_F_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20356 : /*52446*/ /*Scope*/ 9, /*->52456*/
20357 : /*52447*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LT_U64_e64), 0,
20358 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20359 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20360 : // Dst: (V_CMPX_LT_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20361 : /*52456*/ /*Scope*/ 9, /*->52466*/
20362 : /*52457*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_EQ_U64_e64), 0,
20363 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20364 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20365 : // Dst: (V_CMPX_EQ_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20366 : /*52466*/ /*Scope*/ 9, /*->52476*/
20367 : /*52467*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_LE_U64_e64), 0,
20368 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20369 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20370 : // Dst: (V_CMPX_LE_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20371 : /*52476*/ /*Scope*/ 9, /*->52486*/
20372 : /*52477*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GT_U64_e64), 0,
20373 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20374 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20375 : // Dst: (V_CMPX_GT_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20376 : /*52486*/ /*Scope*/ 9, /*->52496*/
20377 : /*52487*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_NE_U64_e64), 0,
20378 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20379 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20380 : // Dst: (V_CMPX_NE_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20381 : /*52496*/ /*Scope*/ 9, /*->52506*/
20382 : /*52497*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_GE_U64_e64), 0,
20383 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20384 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20385 : // Dst: (V_CMPX_GE_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20386 : /*52506*/ /*Scope*/ 9, /*->52516*/
20387 : /*52507*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_T_U64_e64), 0,
20388 : 1/*#VTs*/, MVT::i1, 2/*#Ops*/, 0, 1,
20389 : // Src: (setcc:i1 i64:i64:$src0, i64:i64:$src1, (cond:Other)<<P:Predicate_COND_NULL>>) - Complexity = -997
20390 : // Dst: (V_CMPX_T_U64_e64:i1 i64:i64:$src0, i64:i64:$src1)
20391 : /*52516*/ 0, /*End of Scope*/
20392 : /*52517*/ 0, /*End of Scope*/
20393 : /*52518*/ 0, /*End of Scope*/
20394 : /*52519*/ /*SwitchOpcode*/ 71, TARGET_VAL(AMDGPUISD::FP_CLASS),// ->52593
20395 : /*52522*/ OPC_RecordChild0, // #0 = $VOP3Mods0Clamp0OMod:src0:src0_modifiers
20396 : /*52523*/ OPC_CheckType, MVT::i1,
20397 : /*52525*/ OPC_Scope, 32, /*->52559*/ // 2 children in Scope
20398 : /*52527*/ OPC_CheckChild0Type, MVT::f32,
20399 : /*52529*/ OPC_RecordChild1, // #1 = $src1
20400 : /*52530*/ OPC_CheckChild1Type, MVT::i32,
20401 : /*52532*/ OPC_CheckComplexPat, /*CP*/13, /*#*/0, // SelectVOP3Mods0Clamp0OMod:$ #2 #3 #4 #5
20402 : /*52535*/ OPC_Scope, 10, /*->52547*/ // 2 children in Scope
20403 : /*52537*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_CLASS_F32_e64), 0,
20404 : 1/*#VTs*/, MVT::i1, 3/*#Ops*/, 3, 2, 1,
20405 : // Src: (AMDGPUfp_class:i1 (VOP3Mods0Clamp0OMod:f32 f32:f32:$src0, i32:i32:$src0_modifiers), i32:i32:$src1) - Complexity = -982
20406 : // Dst: (V_CMP_CLASS_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1)
20407 : /*52547*/ /*Scope*/ 10, /*->52558*/
20408 : /*52548*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_CLASS_F32_e64), 0,
20409 : 1/*#VTs*/, MVT::i1, 3/*#Ops*/, 3, 2, 1,
20410 : // Src: (AMDGPUfp_class:i1 (VOP3Mods0Clamp0OMod:f32 f32:f32:$src0, i32:i32:$src0_modifiers), i32:i32:$src1) - Complexity = -982
20411 : // Dst: (V_CMPX_CLASS_F32_e64:i1 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1)
20412 : /*52558*/ 0, /*End of Scope*/
20413 : /*52559*/ /*Scope*/ 32, /*->52592*/
20414 : /*52560*/ OPC_CheckChild0Type, MVT::f64,
20415 : /*52562*/ OPC_RecordChild1, // #1 = $src1
20416 : /*52563*/ OPC_CheckChild1Type, MVT::i32,
20417 : /*52565*/ OPC_CheckComplexPat, /*CP*/13, /*#*/0, // SelectVOP3Mods0Clamp0OMod:$ #2 #3 #4 #5
20418 : /*52568*/ OPC_Scope, 10, /*->52580*/ // 2 children in Scope
20419 : /*52570*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMP_CLASS_F64_e64), 0,
20420 : 1/*#VTs*/, MVT::i1, 3/*#Ops*/, 3, 2, 1,
20421 : // Src: (AMDGPUfp_class:i1 (VOP3Mods0Clamp0OMod:f64 f64:f64:$src0, i32:i32:$src0_modifiers), i32:i32:$src1) - Complexity = -982
20422 : // Dst: (V_CMP_CLASS_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1)
20423 : /*52580*/ /*Scope*/ 10, /*->52591*/
20424 : /*52581*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CMPX_CLASS_F64_e64), 0,
20425 : 1/*#VTs*/, MVT::i1, 3/*#Ops*/, 3, 2, 1,
20426 : // Src: (AMDGPUfp_class:i1 (VOP3Mods0Clamp0OMod:f64 f64:f64:$src0, i32:i32:$src0_modifiers), i32:i32:$src1) - Complexity = -982
20427 : // Dst: (V_CMPX_CLASS_F64_e64:i1 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1)
20428 : /*52591*/ 0, /*End of Scope*/
20429 : /*52592*/ 0, /*End of Scope*/
20430 : /*52593*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::FP_TO_FP16),// ->52615
20431 : /*52596*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
20432 : /*52597*/ OPC_CheckChild0Type, MVT::f32,
20433 : /*52599*/ OPC_CheckType, MVT::i32,
20434 : /*52601*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
20435 : /*52604*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F16_F32_e64), 0,
20436 : 1/*#VTs*/, MVT::i32, 4/*#Ops*/, 2, 1, 3, 4,
20437 : // Src: (fp_to_f16:i32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
20438 : // Dst: (V_CVT_F16_F32_e64:i32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
20439 : /*52615*/ /*SwitchOpcode*/ 17, TARGET_VAL(AMDGPUISD::SMIN3),// ->52635
20440 : /*52618*/ OPC_RecordChild0, // #0 = $src0
20441 : /*52619*/ OPC_RecordChild1, // #1 = $src1
20442 : /*52620*/ OPC_RecordChild2, // #2 = $src2
20443 : /*52621*/ OPC_CheckChild2Type, MVT::i32,
20444 : /*52623*/ OPC_CheckType, MVT::i32,
20445 : /*52625*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MIN3_I32), 0,
20446 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
20447 : // Src: (AMDGPUsmin3:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = -997
20448 : // Dst: (V_MIN3_I32:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
20449 : /*52635*/ /*SwitchOpcode*/ 17, TARGET_VAL(AMDGPUISD::UMIN3),// ->52655
20450 : /*52638*/ OPC_RecordChild0, // #0 = $src0
20451 : /*52639*/ OPC_RecordChild1, // #1 = $src1
20452 : /*52640*/ OPC_RecordChild2, // #2 = $src2
20453 : /*52641*/ OPC_CheckChild2Type, MVT::i32,
20454 : /*52643*/ OPC_CheckType, MVT::i32,
20455 : /*52645*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MIN3_U32), 0,
20456 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
20457 : // Src: (AMDGPUumin3:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = -997
20458 : // Dst: (V_MIN3_U32:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
20459 : /*52655*/ /*SwitchOpcode*/ 17, TARGET_VAL(AMDGPUISD::SMAX3),// ->52675
20460 : /*52658*/ OPC_RecordChild0, // #0 = $src0
20461 : /*52659*/ OPC_RecordChild1, // #1 = $src1
20462 : /*52660*/ OPC_RecordChild2, // #2 = $src2
20463 : /*52661*/ OPC_CheckChild2Type, MVT::i32,
20464 : /*52663*/ OPC_CheckType, MVT::i32,
20465 : /*52665*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAX3_I32), 0,
20466 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
20467 : // Src: (AMDGPUsmax3:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = -997
20468 : // Dst: (V_MAX3_I32:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
20469 : /*52675*/ /*SwitchOpcode*/ 17, TARGET_VAL(AMDGPUISD::UMAX3),// ->52695
20470 : /*52678*/ OPC_RecordChild0, // #0 = $src0
20471 : /*52679*/ OPC_RecordChild1, // #1 = $src1
20472 : /*52680*/ OPC_RecordChild2, // #2 = $src2
20473 : /*52681*/ OPC_CheckChild2Type, MVT::i32,
20474 : /*52683*/ OPC_CheckType, MVT::i32,
20475 : /*52685*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAX3_U32), 0,
20476 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 0, 1, 2,
20477 : // Src: (AMDGPUumax3:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2) - Complexity = -997
20478 : // Dst: (V_MAX3_U32:i32 i32:i32:$src0, i32:i32:$src1, i32:i32:$src2)
20479 : /*52695*/ /*SwitchOpcode*/ 115|128,3/*499*/, TARGET_VAL(ISD::FADD),// ->53198
20480 : /*52699*/ OPC_Scope, 39, /*->52740*/ // 5 children in Scope
20481 : /*52701*/ OPC_RecordChild0, // #0 = $VOP3Mods:x:mods
20482 : /*52702*/ OPC_MoveChild, 1,
20483 : /*52704*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
20484 : /*52707*/ OPC_MoveChild, 0,
20485 : /*52709*/ OPC_CheckOpcode, TARGET_VAL(ISD::FFLOOR),
20486 : /*52712*/ OPC_CheckChild0Same, 0,
20487 : /*52714*/ OPC_MoveParent,
20488 : /*52715*/ OPC_MoveParent,
20489 : /*52716*/ OPC_CheckType, MVT::f64,
20490 : /*52718*/ OPC_CheckPatternPredicate, 10, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
20491 : /*52720*/ OPC_CheckComplexPat, /*CP*/12, /*#*/0, // SelectVOP3Mods:$ #1 #2
20492 : /*52723*/ OPC_EmitInteger, MVT::i1, 0,
20493 : /*52726*/ OPC_EmitInteger, MVT::i32, 0,
20494 : /*52729*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_FRACT_F64_e64), 0,
20495 : 1/*#VTs*/, MVT::f64, 4/*#Ops*/, 2, 1, 3, 4,
20496 : // Src: (fadd:f64 (VOP3Mods:f64 f64:f64:$x, i32:i32:$mods), (fneg:f64 (ffloor:f64 (VOP3Mods:f64 f64:f64:$x, i32:i32:$mods)))) - Complexity = 27
20497 : // Dst: (V_FRACT_F64_e64:f64 ?:i32:$mods, ?:f64:$x, 0:i1, 0:i32)
20498 : /*52740*/ /*Scope*/ 39, /*->52780*/
20499 : /*52741*/ OPC_MoveChild, 0,
20500 : /*52743*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
20501 : /*52746*/ OPC_MoveChild, 0,
20502 : /*52748*/ OPC_CheckOpcode, TARGET_VAL(ISD::FFLOOR),
20503 : /*52751*/ OPC_RecordChild0, // #0 = $VOP3Mods:x:mods
20504 : /*52752*/ OPC_MoveParent,
20505 : /*52753*/ OPC_MoveParent,
20506 : /*52754*/ OPC_CheckChild1Same, 0,
20507 : /*52756*/ OPC_CheckType, MVT::f64,
20508 : /*52758*/ OPC_CheckPatternPredicate, 10, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
20509 : /*52760*/ OPC_CheckComplexPat, /*CP*/12, /*#*/0, // SelectVOP3Mods:$ #1 #2
20510 : /*52763*/ OPC_EmitInteger, MVT::i1, 0,
20511 : /*52766*/ OPC_EmitInteger, MVT::i32, 0,
20512 : /*52769*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_FRACT_F64_e64), 0,
20513 : 1/*#VTs*/, MVT::f64, 4/*#Ops*/, 2, 1, 3, 4,
20514 : // Src: (fadd:f64 (fneg:f64 (ffloor:f64 (VOP3Mods:f64 f64:f64:$x, i32:i32:$mods))), (VOP3Mods:f64 f64:f64:$x, i32:i32:$mods)) - Complexity = 27
20515 : // Dst: (V_FRACT_F64_e64:f64 ?:i32:$mods, ?:f64:$x, 0:i1, 0:i32)
20516 : /*52780*/ /*Scope*/ 109, /*->52890*/
20517 : /*52781*/ OPC_RecordChild0, // #0 = $VOP3Mods:x:mods
20518 : /*52782*/ OPC_MoveChild, 1,
20519 : /*52784*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
20520 : /*52787*/ OPC_MoveChild, 0,
20521 : /*52789*/ OPC_CheckOpcode, TARGET_VAL(ISD::FFLOOR),
20522 : /*52792*/ OPC_CheckChild0Same, 0,
20523 : /*52794*/ OPC_MoveParent,
20524 : /*52795*/ OPC_MoveParent,
20525 : /*52796*/ OPC_CheckType, MVT::f64,
20526 : /*52798*/ OPC_CheckPatternPredicate, 11, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
20527 : /*52800*/ OPC_CheckComplexPat, /*CP*/12, /*#*/0, // SelectVOP3Mods:$ #1 #2
20528 : /*52803*/ OPC_EmitInteger, MVT::i32, 0,
20529 : /*52806*/ OPC_EmitInteger, MVT::i1, 0,
20530 : /*52809*/ OPC_EmitInteger, MVT::i32, 0,
20531 : /*52812*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_FRACT_F64_e64), 0,
20532 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 2, 1, 4, 5, // Results = #6
20533 : /*52823*/ OPC_EmitInteger, MVT::i32, 0,
20534 : /*52826*/ OPC_EmitInteger, MVT::i64, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,119|128,63/*4607182418800017407*/,
20535 : /*52837*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B64_PSEUDO), 0,
20536 : 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 8, // Results = #9
20537 : /*52845*/ OPC_EmitInteger, MVT::i1, 0,
20538 : /*52848*/ OPC_EmitInteger, MVT::i32, 0,
20539 : /*52851*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MIN_F64), 0,
20540 : 1/*#VTs*/, MVT::i64, 6/*#Ops*/, 3, 6, 7, 9, 10, 11, // Results = #12
20541 : /*52864*/ OPC_EmitInteger, MVT::i32, 0,
20542 : /*52867*/ OPC_EmitInteger, MVT::i32, 3,
20543 : /*52870*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CMP_CLASS_F64_e64), 0,
20544 : 1/*#VTs*/, MVT::i1, 3/*#Ops*/, 13, 1, 14, // Results = #15
20545 : /*52880*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CNDMASK_B64_PSEUDO), 0,
20546 : 1/*#VTs*/, MVT::f64, 3/*#Ops*/, 1, 12, 15,
20547 : // Src: (fadd:f64 (VOP3Mods:f64 f64:f64:$x, i32:i32:$mods), (fneg:f64 (ffloor:f64 (VOP3Mods:f64 f64:f64:$x, i32:i32:$mods)))) - Complexity = 27
20548 : // Dst: (V_CNDMASK_B64_PSEUDO:f64 ?:f64:$x, (V_MIN_F64:i64 0:i32, (V_FRACT_F64_e64:i64 ?:i32:$mods, ?:f64:$x, 0:i1, 0:i32), 0:i32, (V_MOV_B64_PSEUDO:i64 4607182418800017407:i64), 0:i1, 0:i32), (V_CMP_CLASS_F64_e64:i1 0:i32, ?:f64:$x, 3:i32))
20549 : /*52890*/ /*Scope*/ 109, /*->53000*/
20550 : /*52891*/ OPC_MoveChild, 0,
20551 : /*52893*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
20552 : /*52896*/ OPC_MoveChild, 0,
20553 : /*52898*/ OPC_CheckOpcode, TARGET_VAL(ISD::FFLOOR),
20554 : /*52901*/ OPC_RecordChild0, // #0 = $VOP3Mods:x:mods
20555 : /*52902*/ OPC_MoveParent,
20556 : /*52903*/ OPC_MoveParent,
20557 : /*52904*/ OPC_CheckChild1Same, 0,
20558 : /*52906*/ OPC_CheckType, MVT::f64,
20559 : /*52908*/ OPC_CheckPatternPredicate, 11, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
20560 : /*52910*/ OPC_CheckComplexPat, /*CP*/12, /*#*/0, // SelectVOP3Mods:$ #1 #2
20561 : /*52913*/ OPC_EmitInteger, MVT::i32, 0,
20562 : /*52916*/ OPC_EmitInteger, MVT::i1, 0,
20563 : /*52919*/ OPC_EmitInteger, MVT::i32, 0,
20564 : /*52922*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_FRACT_F64_e64), 0,
20565 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 2, 1, 4, 5, // Results = #6
20566 : /*52933*/ OPC_EmitInteger, MVT::i32, 0,
20567 : /*52936*/ OPC_EmitInteger, MVT::i64, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,119|128,63/*4607182418800017407*/,
20568 : /*52947*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B64_PSEUDO), 0,
20569 : 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 8, // Results = #9
20570 : /*52955*/ OPC_EmitInteger, MVT::i1, 0,
20571 : /*52958*/ OPC_EmitInteger, MVT::i32, 0,
20572 : /*52961*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MIN_F64), 0,
20573 : 1/*#VTs*/, MVT::i64, 6/*#Ops*/, 3, 6, 7, 9, 10, 11, // Results = #12
20574 : /*52974*/ OPC_EmitInteger, MVT::i32, 0,
20575 : /*52977*/ OPC_EmitInteger, MVT::i32, 3,
20576 : /*52980*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CMP_CLASS_F64_e64), 0,
20577 : 1/*#VTs*/, MVT::i1, 3/*#Ops*/, 13, 1, 14, // Results = #15
20578 : /*52990*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CNDMASK_B64_PSEUDO), 0,
20579 : 1/*#VTs*/, MVT::f64, 3/*#Ops*/, 1, 12, 15,
20580 : // Src: (fadd:f64 (fneg:f64 (ffloor:f64 (VOP3Mods:f64 f64:f64:$x, i32:i32:$mods))), (VOP3Mods:f64 f64:f64:$x, i32:i32:$mods)) - Complexity = 27
20581 : // Dst: (V_CNDMASK_B64_PSEUDO:f64 ?:f64:$x, (V_MIN_F64:i64 0:i32, (V_FRACT_F64_e64:i64 ?:i32:$mods, ?:f64:$x, 0:i1, 0:i32), 0:i32, (V_MOV_B64_PSEUDO:i64 4607182418800017407:i64), 0:i1, 0:i32), (V_CMP_CLASS_F64_e64:i1 0:i32, ?:f64:$x, 3:i32))
20582 : /*53000*/ /*Scope*/ 67|128,1/*195*/, /*->53197*/
20583 : /*53002*/ OPC_RecordChild0, // #0 = $src0
20584 : /*53003*/ OPC_RecordChild1, // #1 = $src1
20585 : /*53004*/ OPC_SwitchType /*2 cases */, 16|128,1/*144*/, MVT::f32,// ->53152
20586 : /*53008*/ OPC_Scope, 101, /*->53111*/ // 3 children in Scope
20587 : /*53010*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
20588 : /*53012*/ OPC_EmitInteger, MVT::i32, 0,
20589 : /*53015*/ OPC_EmitInteger, MVT::i32, 0,
20590 : /*53018*/ OPC_EmitInteger, MVT::i32, 1,
20591 : /*53021*/ OPC_EmitInteger, MVT::i32, 0,
20592 : /*53024*/ OPC_EmitInteger, MVT::i32, 0,
20593 : /*53027*/ OPC_EmitInteger, MVT::i32, 0,
20594 : /*53030*/ OPC_EmitInteger, MVT::i32, 0,
20595 : /*53033*/ OPC_EmitInteger, MVT::i32, 0,
20596 : /*53036*/ OPC_EmitInteger, MVT::i32, 0,
20597 : /*53039*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20598 : /*53051*/ OPC_EmitInteger, MVT::i32, 0,
20599 : /*53054*/ OPC_EmitInteger, MVT::i32, 0,
20600 : /*53057*/ OPC_EmitInteger, MVT::i32, 0,
20601 : /*53060*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20602 : /*53072*/ OPC_EmitInteger, MVT::i32, 1,
20603 : /*53075*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
20604 : /*53078*/ OPC_EmitInteger, MVT::i32, 0,
20605 : /*53081*/ OPC_EmitInteger, MVT::i32, 0,
20606 : /*53084*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::ADD), 0,
20607 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
20608 : // Src: (fadd:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1) - Complexity = 3
20609 : // Dst: (ADD:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1)
20610 : /*53111*/ /*Scope*/ 19, /*->53131*/
20611 : /*53112*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
20612 : /*53115*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
20613 : /*53118*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_ADD_F32_e64), 0,
20614 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
20615 : // Src: (fadd:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
20616 : // Dst: (V_ADD_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
20617 : /*53131*/ /*Scope*/ 19, /*->53151*/
20618 : /*53132*/ OPC_CheckComplexPat, /*CP*/12, /*#*/0, // SelectVOP3Mods:$ #2 #3
20619 : /*53135*/ OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectVOP3Mods0:$ #4 #5 #6 #7
20620 : /*53138*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_ADD_F32_e64), 0,
20621 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 5, 4, 3, 2, 6, 7,
20622 : // Src: (fadd:f32 (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -973
20623 : // Dst: (V_ADD_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
20624 : /*53151*/ 0, /*End of Scope*/
20625 : /*53152*/ /*SwitchType*/ 42, MVT::f64,// ->53196
20626 : /*53154*/ OPC_Scope, 19, /*->53175*/ // 2 children in Scope
20627 : /*53156*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
20628 : /*53159*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
20629 : /*53162*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_ADD_F64), 0,
20630 : 1/*#VTs*/, MVT::f64, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
20631 : // Src: (fadd:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
20632 : // Dst: (V_ADD_F64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
20633 : /*53175*/ /*Scope*/ 19, /*->53195*/
20634 : /*53176*/ OPC_CheckComplexPat, /*CP*/12, /*#*/0, // SelectVOP3Mods:$ #2 #3
20635 : /*53179*/ OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectVOP3Mods0:$ #4 #5 #6 #7
20636 : /*53182*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_ADD_F64), 0,
20637 : 1/*#VTs*/, MVT::f64, 6/*#Ops*/, 5, 4, 3, 2, 6, 7,
20638 : // Src: (fadd:f64 (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -973
20639 : // Dst: (V_ADD_F64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
20640 : /*53195*/ 0, /*End of Scope*/
20641 : /*53196*/ 0, // EndSwitchType
20642 : /*53197*/ 0, /*End of Scope*/
20643 : /*53198*/ /*SwitchOpcode*/ 59, TARGET_VAL(ISD::FSUB),// ->53260
20644 : /*53201*/ OPC_RecordChild0, // #0 = $VOP3Mods:x:mods
20645 : /*53202*/ OPC_Scope, 32, /*->53236*/ // 2 children in Scope
20646 : /*53204*/ OPC_MoveChild, 1,
20647 : /*53206*/ OPC_CheckOpcode, TARGET_VAL(ISD::FFLOOR),
20648 : /*53209*/ OPC_CheckChild0Same, 0,
20649 : /*53211*/ OPC_MoveParent,
20650 : /*53212*/ OPC_CheckType, MVT::f32,
20651 : /*53214*/ OPC_CheckPatternPredicate, 10, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
20652 : /*53216*/ OPC_CheckComplexPat, /*CP*/12, /*#*/0, // SelectVOP3Mods:$ #1 #2
20653 : /*53219*/ OPC_EmitInteger, MVT::i1, 0,
20654 : /*53222*/ OPC_EmitInteger, MVT::i32, 0,
20655 : /*53225*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_FRACT_F32_e64), 0,
20656 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
20657 : // Src: (fsub:f32 (VOP3Mods:f32 f32:f32:$x, i32:i32:$mods), (ffloor:f32 (VOP3Mods:f32 f32:f32:$x, i32:i32:$mods))) - Complexity = 24
20658 : // Dst: (V_FRACT_F32_e64:f32 ?:i32:$mods, ?:f32:$x, 0:i1, 0:i32)
20659 : /*53236*/ /*Scope*/ 22, /*->53259*/
20660 : /*53237*/ OPC_RecordChild1, // #1 = $VOP3Mods:src1:src1_modifiers
20661 : /*53238*/ OPC_CheckType, MVT::f32,
20662 : /*53240*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
20663 : /*53243*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
20664 : /*53246*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_SUB_F32_e64), 0,
20665 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
20666 : // Src: (fsub:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
20667 : // Dst: (V_SUB_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
20668 : /*53259*/ 0, /*End of Scope*/
20669 : /*53260*/ /*SwitchOpcode*/ 60, TARGET_VAL(AMDGPUISD::CLAMP),// ->53323
20670 : /*53263*/ OPC_RecordChild0, // #0 = $VOP3Mods0Clamp:src0:src0_modifiers:omod
20671 : /*53264*/ OPC_MoveChild, 1,
20672 : /*53266*/ OPC_CheckOpcode, TARGET_VAL(ISD::ConstantFP),
20673 : /*53269*/ OPC_CheckPredicate, 108, // Predicate_FP_ZERO
20674 : /*53271*/ OPC_MoveParent,
20675 : /*53272*/ OPC_MoveChild, 2,
20676 : /*53274*/ OPC_CheckOpcode, TARGET_VAL(ISD::ConstantFP),
20677 : /*53277*/ OPC_CheckPredicate, 107, // Predicate_FP_ONE
20678 : /*53279*/ OPC_MoveParent,
20679 : /*53280*/ OPC_CheckType, MVT::f32,
20680 : /*53282*/ OPC_Scope, 27, /*->53311*/ // 2 children in Scope
20681 : /*53284*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
20682 : /*53286*/ OPC_CheckComplexPat, /*CP*/14, /*#*/0, // SelectVOP3Mods0Clamp:$ #1 #2 #3
20683 : /*53289*/ OPC_EmitInteger, MVT::i32, 0,
20684 : /*53292*/ OPC_EmitInteger, MVT::i32, 0,
20685 : /*53295*/ OPC_EmitInteger, MVT::i1, 1,
20686 : /*53298*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_ADD_F32_e64), 0,
20687 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 2, 1, 4, 5, 6, 3,
20688 : // Src: (AMDGPUclamp:f32 (VOP3Mods0Clamp:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i32:i32:$omod), (fpimm:f32)<<P:Predicate_FP_ZERO>>, (fpimm:f32)<<P:Predicate_FP_ONE>>) - Complexity = 23
20689 : // Dst: (V_ADD_F32_e64:f32 ?:i32:$src0_modifiers, ?:f32:$src0, 0:i32, 0:i32, 1:i1, ?:i32:$omod)
20690 : /*53311*/ /*Scope*/ 10, /*->53322*/
20691 : /*53312*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
20692 : /*53314*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CLAMP_R600), 0,
20693 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 0,
20694 : // Src: (AMDGPUclamp:f32 f32:f32:$src0, (fpimm:f32)<<P:Predicate_FP_ZERO>>, (fpimm:f32)<<P:Predicate_FP_ONE>>) - Complexity = 11
20695 : // Dst: (CLAMP_R600:f32 f32:f32:$src0)
20696 : /*53322*/ 0, /*End of Scope*/
20697 : /*53323*/ /*SwitchOpcode*/ 48, TARGET_VAL(AMDGPUISD::INTERP_MOV),// ->53374
20698 : /*53326*/ OPC_CaptureGlueInput,
20699 : /*53327*/ OPC_RecordChild0, // #0 = $src0
20700 : /*53328*/ OPC_MoveChild, 0,
20701 : /*53330*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
20702 : /*53333*/ OPC_CheckType, MVT::i32,
20703 : /*53335*/ OPC_MoveParent,
20704 : /*53336*/ OPC_RecordChild1, // #1 = $attr_chan
20705 : /*53337*/ OPC_MoveChild, 1,
20706 : /*53339*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
20707 : /*53342*/ OPC_CheckType, MVT::i32,
20708 : /*53344*/ OPC_MoveParent,
20709 : /*53345*/ OPC_RecordChild2, // #2 = $attr
20710 : /*53346*/ OPC_MoveChild, 2,
20711 : /*53348*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
20712 : /*53351*/ OPC_CheckType, MVT::i32,
20713 : /*53353*/ OPC_MoveParent,
20714 : /*53354*/ OPC_CheckType, MVT::f32,
20715 : /*53356*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
20716 : /*53358*/ OPC_EmitConvertToTarget, 0,
20717 : /*53360*/ OPC_EmitConvertToTarget, 1,
20718 : /*53362*/ OPC_EmitConvertToTarget, 2,
20719 : /*53364*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_INTERP_MOV_F32), 0|OPFL_GlueInput,
20720 : 1/*#VTs*/, MVT::f32, 3/*#Ops*/, 3, 4, 5,
20721 : // Src: (AMDGPUinterp_mov:f32 (imm:i32):$src0, (imm:i32):$attr_chan, (imm:i32):$attr) - Complexity = 12
20722 : // Dst: (V_INTERP_MOV_F32:f32 (imm:i32):$src0, (imm:i32):$attr_chan, (imm:i32):$attr)
20723 : /*53374*/ /*SwitchOpcode*/ 97|128,1/*225*/, TARGET_VAL(ISD::FFLOOR),// ->53603
20724 : /*53378*/ OPC_RecordChild0, // #0 = $VOP3Mods:x:mods
20725 : /*53379*/ OPC_SwitchType /*2 cases */, 4|128,1/*132*/, MVT::f64,// ->53515
20726 : /*53383*/ OPC_Scope, 114, /*->53499*/ // 2 children in Scope
20727 : /*53385*/ OPC_CheckPatternPredicate, 11, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
20728 : /*53387*/ OPC_CheckComplexPat, /*CP*/12, /*#*/0, // SelectVOP3Mods:$ #1 #2
20729 : /*53390*/ OPC_EmitInteger, MVT::i32, 1,
20730 : /*53393*/ OPC_EmitInteger, MVT::i32, 0,
20731 : /*53396*/ OPC_EmitInteger, MVT::i1, 0,
20732 : /*53399*/ OPC_EmitInteger, MVT::i32, 0,
20733 : /*53402*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_FRACT_F64_e64), 0,
20734 : 1/*#VTs*/, MVT::i64, 4/*#Ops*/, 2, 1, 5, 6, // Results = #7
20735 : /*53413*/ OPC_EmitInteger, MVT::i32, 0,
20736 : /*53416*/ OPC_EmitInteger, MVT::i64, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,119|128,63/*4607182418800017407*/,
20737 : /*53427*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B64_PSEUDO), 0,
20738 : 1/*#VTs*/, MVT::i64, 1/*#Ops*/, 9, // Results = #10
20739 : /*53435*/ OPC_EmitInteger, MVT::i1, 0,
20740 : /*53438*/ OPC_EmitInteger, MVT::i32, 0,
20741 : /*53441*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MIN_F64), 0,
20742 : 1/*#VTs*/, MVT::i64, 6/*#Ops*/, 4, 7, 8, 10, 11, 12, // Results = #13
20743 : /*53454*/ OPC_EmitInteger, MVT::i32, 0,
20744 : /*53457*/ OPC_EmitInteger, MVT::i32, 3,
20745 : /*53460*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CMP_CLASS_F64_e64), 0,
20746 : 1/*#VTs*/, MVT::i1, 3/*#Ops*/, 14, 1, 15, // Results = #16
20747 : /*53470*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CNDMASK_B64_PSEUDO), 0,
20748 : 1/*#VTs*/, MVT::i64, 3/*#Ops*/, 1, 13, 16, // Results = #17
20749 : /*53480*/ OPC_EmitInteger, MVT::i1, 0,
20750 : /*53483*/ OPC_EmitInteger, MVT::i32, 0,
20751 : /*53486*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_ADD_F64), 0,
20752 : 1/*#VTs*/, MVT::f64, 6/*#Ops*/, 2, 1, 3, 17, 18, 19,
20753 : // Src: (ffloor:f64 (VOP3Mods:f64 f64:f64:$x, i32:i32:$mods)) - Complexity = 12
20754 : // Dst: (V_ADD_F64:f64 ?:i32:$mods, ?:f64:$x, 1:i32, (V_CNDMASK_B64_PSEUDO:i64 ?:f64:$x, (V_MIN_F64:i64 0:i32, (V_FRACT_F64_e64:i64 ?:i32:$mods, ?:f64:$x, 0:i1, 0:i32), 0:i32, (V_MOV_B64_PSEUDO:i64 4607182418800017407:i64), 0:i1, 0:i32), (V_CMP_CLASS_F64_e64:i1 0:i32, ?:f64:$x, 3:i32)), 0:i1, 0:i32)
20755 : /*53499*/ /*Scope*/ 14, /*->53514*/
20756 : /*53500*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
20757 : /*53503*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_FLOOR_F64_e64), 0,
20758 : 1/*#VTs*/, MVT::f64, 4/*#Ops*/, 2, 1, 3, 4,
20759 : // Src: (ffloor:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
20760 : // Dst: (V_FLOOR_F64_e64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i1:i1:$clamp, i32:i32:$omod)
20761 : /*53514*/ 0, /*End of Scope*/
20762 : /*53515*/ /*SwitchType*/ 85, MVT::f32,// ->53602
20763 : /*53517*/ OPC_Scope, 67, /*->53586*/ // 2 children in Scope
20764 : /*53519*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
20765 : /*53521*/ OPC_EmitInteger, MVT::i32, 1,
20766 : /*53524*/ OPC_EmitInteger, MVT::i32, 0,
20767 : /*53527*/ OPC_EmitInteger, MVT::i32, 0,
20768 : /*53530*/ OPC_EmitInteger, MVT::i32, 0,
20769 : /*53533*/ OPC_EmitInteger, MVT::i32, 0,
20770 : /*53536*/ OPC_EmitInteger, MVT::i32, 0,
20771 : /*53539*/ OPC_EmitInteger, MVT::i32, 0,
20772 : /*53542*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20773 : /*53554*/ OPC_EmitInteger, MVT::i32, 1,
20774 : /*53557*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
20775 : /*53560*/ OPC_EmitInteger, MVT::i32, 0,
20776 : /*53563*/ OPC_EmitInteger, MVT::i32, 0,
20777 : /*53566*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FLOOR), 0,
20778 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
20779 : // Src: (ffloor:f32 R600_Reg32:f32:$src0) - Complexity = 3
20780 : // Dst: (FLOOR:f32 R600_Reg32:f32:$src0)
20781 : /*53586*/ /*Scope*/ 14, /*->53601*/
20782 : /*53587*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
20783 : /*53590*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_FLOOR_F32_e64), 0,
20784 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
20785 : // Src: (ffloor:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
20786 : // Dst: (V_FLOOR_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
20787 : /*53601*/ 0, /*End of Scope*/
20788 : /*53602*/ 0, // EndSwitchType
20789 : /*53603*/ /*SwitchOpcode*/ 60, TARGET_VAL(AMDGPUISD::INTERP_P1),// ->53666
20790 : /*53606*/ OPC_CaptureGlueInput,
20791 : /*53607*/ OPC_RecordChild0, // #0 = $i
20792 : /*53608*/ OPC_CheckChild0Type, MVT::i32,
20793 : /*53610*/ OPC_RecordChild1, // #1 = $attr_chan
20794 : /*53611*/ OPC_MoveChild, 1,
20795 : /*53613*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
20796 : /*53616*/ OPC_CheckType, MVT::i32,
20797 : /*53618*/ OPC_MoveParent,
20798 : /*53619*/ OPC_RecordChild2, // #2 = $attr
20799 : /*53620*/ OPC_MoveChild, 2,
20800 : /*53622*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
20801 : /*53625*/ OPC_CheckType, MVT::i32,
20802 : /*53627*/ OPC_MoveParent,
20803 : /*53628*/ OPC_CheckType, MVT::f32,
20804 : /*53630*/ OPC_Scope, 16, /*->53648*/ // 2 children in Scope
20805 : /*53632*/ OPC_CheckPatternPredicate, 12, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true) && (Subtarget->getLDSBankCount() == 32)
20806 : /*53634*/ OPC_EmitConvertToTarget, 1,
20807 : /*53636*/ OPC_EmitConvertToTarget, 2,
20808 : /*53638*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_INTERP_P1_F32), 0|OPFL_GlueInput|OPFL_GlueOutput,
20809 : 1/*#VTs*/, MVT::f32, 3/*#Ops*/, 0, 3, 4,
20810 : // Src: (AMDGPUinterp_p1:f32 i32:i32:$i, (imm:i32):$attr_chan, (imm:i32):$attr) - Complexity = 9
20811 : // Dst: (V_INTERP_P1_F32:f32 i32:i32:$i, (imm:i32):$attr_chan, (imm:i32):$attr)
20812 : /*53648*/ /*Scope*/ 16, /*->53665*/
20813 : /*53649*/ OPC_CheckPatternPredicate, 13, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true) && (Subtarget->getLDSBankCount() == 16)
20814 : /*53651*/ OPC_EmitConvertToTarget, 1,
20815 : /*53653*/ OPC_EmitConvertToTarget, 2,
20816 : /*53655*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_INTERP_P1_F32_16bank), 0|OPFL_GlueInput|OPFL_GlueOutput,
20817 : 1/*#VTs*/, MVT::f32, 3/*#Ops*/, 0, 3, 4,
20818 : // Src: (AMDGPUinterp_p1:f32 i32:i32:$i, (imm:i32):$attr_chan, (imm:i32):$attr) - Complexity = 9
20819 : // Dst: (V_INTERP_P1_F32_16bank:f32 i32:i32:$i, (imm:i32):$attr_chan, (imm:i32):$attr)
20820 : /*53665*/ 0, /*End of Scope*/
20821 : /*53666*/ /*SwitchOpcode*/ 44, TARGET_VAL(AMDGPUISD::INTERP_P2),// ->53713
20822 : /*53669*/ OPC_CaptureGlueInput,
20823 : /*53670*/ OPC_RecordChild0, // #0 = $src0
20824 : /*53671*/ OPC_CheckChild0Type, MVT::f32,
20825 : /*53673*/ OPC_RecordChild1, // #1 = $j
20826 : /*53674*/ OPC_CheckChild1Type, MVT::i32,
20827 : /*53676*/ OPC_RecordChild2, // #2 = $attr_chan
20828 : /*53677*/ OPC_MoveChild, 2,
20829 : /*53679*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
20830 : /*53682*/ OPC_CheckType, MVT::i32,
20831 : /*53684*/ OPC_MoveParent,
20832 : /*53685*/ OPC_RecordChild3, // #3 = $attr
20833 : /*53686*/ OPC_MoveChild, 3,
20834 : /*53688*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
20835 : /*53691*/ OPC_CheckType, MVT::i32,
20836 : /*53693*/ OPC_MoveParent,
20837 : /*53694*/ OPC_CheckType, MVT::f32,
20838 : /*53696*/ OPC_CheckPatternPredicate, 1, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true)
20839 : /*53698*/ OPC_EmitConvertToTarget, 2,
20840 : /*53700*/ OPC_EmitConvertToTarget, 3,
20841 : /*53702*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_INTERP_P2_F32), 0|OPFL_GlueInput,
20842 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 0, 1, 4, 5,
20843 : // Src: (AMDGPUinterp_p2:f32 f32:f32:$src0, i32:i32:$j, (imm:i32):$attr_chan, (imm:i32):$attr) - Complexity = 9
20844 : // Dst: (V_INTERP_P2_F32:f32 f32:f32:$src0, i32:i32:$j, (imm:i32):$attr_chan, (imm:i32):$attr)
20845 : /*53713*/ /*SwitchOpcode*/ 93|128,5/*733*/, TARGET_VAL(ISD::FDIV),// ->54450
20846 : /*53717*/ OPC_Scope, 89|128,1/*217*/, /*->53937*/ // 2 children in Scope
20847 : /*53720*/ OPC_MoveChild, 0,
20848 : /*53722*/ OPC_CheckOpcode, TARGET_VAL(ISD::ConstantFP),
20849 : /*53725*/ OPC_CheckPredicate, 107, // Predicate_FP_ONE
20850 : /*53727*/ OPC_MoveParent,
20851 : /*53728*/ OPC_RecordChild1, // #0 = $src
20852 : /*53729*/ OPC_CheckType, MVT::f32,
20853 : /*53731*/ OPC_Scope, 67, /*->53800*/ // 3 children in Scope
20854 : /*53733*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
20855 : /*53735*/ OPC_EmitInteger, MVT::i32, 1,
20856 : /*53738*/ OPC_EmitInteger, MVT::i32, 0,
20857 : /*53741*/ OPC_EmitInteger, MVT::i32, 0,
20858 : /*53744*/ OPC_EmitInteger, MVT::i32, 0,
20859 : /*53747*/ OPC_EmitInteger, MVT::i32, 0,
20860 : /*53750*/ OPC_EmitInteger, MVT::i32, 0,
20861 : /*53753*/ OPC_EmitInteger, MVT::i32, 0,
20862 : /*53756*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20863 : /*53768*/ OPC_EmitInteger, MVT::i32, 1,
20864 : /*53771*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
20865 : /*53774*/ OPC_EmitInteger, MVT::i32, 0,
20866 : /*53777*/ OPC_EmitInteger, MVT::i32, 0,
20867 : /*53780*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIP_IEEE_r600), 0,
20868 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
20869 : // Src: (fdiv:f32 (fpimm:f32)<<P:Predicate_FP_ONE>>, f32:f32:$src) - Complexity = 7
20870 : // Dst: (RECIP_IEEE_r600:f32 ?:f32:$src)
20871 : /*53800*/ /*Scope*/ 67, /*->53868*/
20872 : /*53801*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
20873 : /*53803*/ OPC_EmitInteger, MVT::i32, 1,
20874 : /*53806*/ OPC_EmitInteger, MVT::i32, 0,
20875 : /*53809*/ OPC_EmitInteger, MVT::i32, 0,
20876 : /*53812*/ OPC_EmitInteger, MVT::i32, 0,
20877 : /*53815*/ OPC_EmitInteger, MVT::i32, 0,
20878 : /*53818*/ OPC_EmitInteger, MVT::i32, 0,
20879 : /*53821*/ OPC_EmitInteger, MVT::i32, 0,
20880 : /*53824*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20881 : /*53836*/ OPC_EmitInteger, MVT::i32, 1,
20882 : /*53839*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
20883 : /*53842*/ OPC_EmitInteger, MVT::i32, 0,
20884 : /*53845*/ OPC_EmitInteger, MVT::i32, 0,
20885 : /*53848*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIP_IEEE_eg), 0,
20886 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
20887 : // Src: (fdiv:f32 (fpimm:f32)<<P:Predicate_FP_ONE>>, f32:f32:$src) - Complexity = 7
20888 : // Dst: (RECIP_IEEE_eg:f32 ?:f32:$src)
20889 : /*53868*/ /*Scope*/ 67, /*->53936*/
20890 : /*53869*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
20891 : /*53871*/ OPC_EmitInteger, MVT::i32, 1,
20892 : /*53874*/ OPC_EmitInteger, MVT::i32, 0,
20893 : /*53877*/ OPC_EmitInteger, MVT::i32, 0,
20894 : /*53880*/ OPC_EmitInteger, MVT::i32, 0,
20895 : /*53883*/ OPC_EmitInteger, MVT::i32, 0,
20896 : /*53886*/ OPC_EmitInteger, MVT::i32, 0,
20897 : /*53889*/ OPC_EmitInteger, MVT::i32, 0,
20898 : /*53892*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20899 : /*53904*/ OPC_EmitInteger, MVT::i32, 1,
20900 : /*53907*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
20901 : /*53910*/ OPC_EmitInteger, MVT::i32, 0,
20902 : /*53913*/ OPC_EmitInteger, MVT::i32, 0,
20903 : /*53916*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIP_IEEE_cm), 0,
20904 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
20905 : // Src: (fdiv:f32 (fpimm:f32)<<P:Predicate_FP_ONE>>, f32:f32:$src) - Complexity = 7
20906 : // Dst: (RECIP_IEEE_cm:f32 ?:f32:$src)
20907 : /*53936*/ 0, /*End of Scope*/
20908 : /*53937*/ /*Scope*/ 126|128,3/*510*/, /*->54449*/
20909 : /*53939*/ OPC_RecordChild0, // #0 = $src0
20910 : /*53940*/ OPC_RecordChild1, // #1 = $src1
20911 : /*53941*/ OPC_CheckType, MVT::f32,
20912 : /*53943*/ OPC_Scope, 38|128,1/*166*/, /*->54112*/ // 3 children in Scope
20913 : /*53946*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
20914 : /*53948*/ OPC_EmitInteger, MVT::i32, 0,
20915 : /*53951*/ OPC_EmitInteger, MVT::i32, 0,
20916 : /*53954*/ OPC_EmitInteger, MVT::i32, 1,
20917 : /*53957*/ OPC_EmitInteger, MVT::i32, 0,
20918 : /*53960*/ OPC_EmitInteger, MVT::i32, 0,
20919 : /*53963*/ OPC_EmitInteger, MVT::i32, 0,
20920 : /*53966*/ OPC_EmitInteger, MVT::i32, 0,
20921 : /*53969*/ OPC_EmitInteger, MVT::i32, 0,
20922 : /*53972*/ OPC_EmitInteger, MVT::i32, 0,
20923 : /*53975*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20924 : /*53987*/ OPC_EmitInteger, MVT::i32, 1,
20925 : /*53990*/ OPC_EmitInteger, MVT::i32, 0,
20926 : /*53993*/ OPC_EmitInteger, MVT::i32, 0,
20927 : /*53996*/ OPC_EmitInteger, MVT::i32, 0,
20928 : /*53999*/ OPC_EmitInteger, MVT::i32, 0,
20929 : /*54002*/ OPC_EmitInteger, MVT::i32, 0,
20930 : /*54005*/ OPC_EmitInteger, MVT::i32, 0,
20931 : /*54008*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20932 : /*54020*/ OPC_EmitInteger, MVT::i32, 1,
20933 : /*54023*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
20934 : /*54026*/ OPC_EmitInteger, MVT::i32, 0,
20935 : /*54029*/ OPC_EmitInteger, MVT::i32, 0,
20936 : /*54032*/ OPC_EmitNode, TARGET_VAL(AMDGPU::RECIP_IEEE_r600), 0,
20937 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 12, 13, 14, 15, 1, 16, 17, 18, 19, 20, 21, 22, 23, // Results = #24
20938 : /*54052*/ OPC_EmitInteger, MVT::i32, 0,
20939 : /*54055*/ OPC_EmitInteger, MVT::i32, 0,
20940 : /*54058*/ OPC_EmitInteger, MVT::i32, 0,
20941 : /*54061*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20942 : /*54073*/ OPC_EmitInteger, MVT::i32, 1,
20943 : /*54076*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
20944 : /*54079*/ OPC_EmitInteger, MVT::i32, 0,
20945 : /*54082*/ OPC_EmitInteger, MVT::i32, 0,
20946 : /*54085*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL_IEEE), 0,
20947 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31, 32,
20948 : // Src: (fdiv:f32 f32:f32:$src0, f32:f32:$src1) - Complexity = 3
20949 : // Dst: (MUL_IEEE:f32 ?:f32:$src0, (RECIP_IEEE_r600:i32 ?:f32:$src1))
20950 : /*54112*/ /*Scope*/ 38|128,1/*166*/, /*->54280*/
20951 : /*54114*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
20952 : /*54116*/ OPC_EmitInteger, MVT::i32, 0,
20953 : /*54119*/ OPC_EmitInteger, MVT::i32, 0,
20954 : /*54122*/ OPC_EmitInteger, MVT::i32, 1,
20955 : /*54125*/ OPC_EmitInteger, MVT::i32, 0,
20956 : /*54128*/ OPC_EmitInteger, MVT::i32, 0,
20957 : /*54131*/ OPC_EmitInteger, MVT::i32, 0,
20958 : /*54134*/ OPC_EmitInteger, MVT::i32, 0,
20959 : /*54137*/ OPC_EmitInteger, MVT::i32, 0,
20960 : /*54140*/ OPC_EmitInteger, MVT::i32, 0,
20961 : /*54143*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20962 : /*54155*/ OPC_EmitInteger, MVT::i32, 1,
20963 : /*54158*/ OPC_EmitInteger, MVT::i32, 0,
20964 : /*54161*/ OPC_EmitInteger, MVT::i32, 0,
20965 : /*54164*/ OPC_EmitInteger, MVT::i32, 0,
20966 : /*54167*/ OPC_EmitInteger, MVT::i32, 0,
20967 : /*54170*/ OPC_EmitInteger, MVT::i32, 0,
20968 : /*54173*/ OPC_EmitInteger, MVT::i32, 0,
20969 : /*54176*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20970 : /*54188*/ OPC_EmitInteger, MVT::i32, 1,
20971 : /*54191*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
20972 : /*54194*/ OPC_EmitInteger, MVT::i32, 0,
20973 : /*54197*/ OPC_EmitInteger, MVT::i32, 0,
20974 : /*54200*/ OPC_EmitNode, TARGET_VAL(AMDGPU::RECIP_IEEE_eg), 0,
20975 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 12, 13, 14, 15, 1, 16, 17, 18, 19, 20, 21, 22, 23, // Results = #24
20976 : /*54220*/ OPC_EmitInteger, MVT::i32, 0,
20977 : /*54223*/ OPC_EmitInteger, MVT::i32, 0,
20978 : /*54226*/ OPC_EmitInteger, MVT::i32, 0,
20979 : /*54229*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
20980 : /*54241*/ OPC_EmitInteger, MVT::i32, 1,
20981 : /*54244*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
20982 : /*54247*/ OPC_EmitInteger, MVT::i32, 0,
20983 : /*54250*/ OPC_EmitInteger, MVT::i32, 0,
20984 : /*54253*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL_IEEE), 0,
20985 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31, 32,
20986 : // Src: (fdiv:f32 f32:f32:$src0, f32:f32:$src1) - Complexity = 3
20987 : // Dst: (MUL_IEEE:f32 ?:f32:$src0, (RECIP_IEEE_eg:i32 ?:f32:$src1))
20988 : /*54280*/ /*Scope*/ 38|128,1/*166*/, /*->54448*/
20989 : /*54282*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
20990 : /*54284*/ OPC_EmitInteger, MVT::i32, 0,
20991 : /*54287*/ OPC_EmitInteger, MVT::i32, 0,
20992 : /*54290*/ OPC_EmitInteger, MVT::i32, 1,
20993 : /*54293*/ OPC_EmitInteger, MVT::i32, 0,
20994 : /*54296*/ OPC_EmitInteger, MVT::i32, 0,
20995 : /*54299*/ OPC_EmitInteger, MVT::i32, 0,
20996 : /*54302*/ OPC_EmitInteger, MVT::i32, 0,
20997 : /*54305*/ OPC_EmitInteger, MVT::i32, 0,
20998 : /*54308*/ OPC_EmitInteger, MVT::i32, 0,
20999 : /*54311*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21000 : /*54323*/ OPC_EmitInteger, MVT::i32, 1,
21001 : /*54326*/ OPC_EmitInteger, MVT::i32, 0,
21002 : /*54329*/ OPC_EmitInteger, MVT::i32, 0,
21003 : /*54332*/ OPC_EmitInteger, MVT::i32, 0,
21004 : /*54335*/ OPC_EmitInteger, MVT::i32, 0,
21005 : /*54338*/ OPC_EmitInteger, MVT::i32, 0,
21006 : /*54341*/ OPC_EmitInteger, MVT::i32, 0,
21007 : /*54344*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21008 : /*54356*/ OPC_EmitInteger, MVT::i32, 1,
21009 : /*54359*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21010 : /*54362*/ OPC_EmitInteger, MVT::i32, 0,
21011 : /*54365*/ OPC_EmitInteger, MVT::i32, 0,
21012 : /*54368*/ OPC_EmitNode, TARGET_VAL(AMDGPU::RECIP_IEEE_cm), 0,
21013 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 12, 13, 14, 15, 1, 16, 17, 18, 19, 20, 21, 22, 23, // Results = #24
21014 : /*54388*/ OPC_EmitInteger, MVT::i32, 0,
21015 : /*54391*/ OPC_EmitInteger, MVT::i32, 0,
21016 : /*54394*/ OPC_EmitInteger, MVT::i32, 0,
21017 : /*54397*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21018 : /*54409*/ OPC_EmitInteger, MVT::i32, 1,
21019 : /*54412*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21020 : /*54415*/ OPC_EmitInteger, MVT::i32, 0,
21021 : /*54418*/ OPC_EmitInteger, MVT::i32, 0,
21022 : /*54421*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL_IEEE), 0,
21023 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 24, 25, 26, 27, 28, 29, 30, 31, 32,
21024 : // Src: (fdiv:f32 f32:f32:$src0, f32:f32:$src1) - Complexity = 3
21025 : // Dst: (MUL_IEEE:f32 ?:f32:$src0, (RECIP_IEEE_cm:i32 ?:f32:$src1))
21026 : /*54448*/ 0, /*End of Scope*/
21027 : /*54449*/ 0, /*End of Scope*/
21028 : /*54450*/ /*SwitchOpcode*/ 104, TARGET_VAL(AMDGPUISD::LOAD_CONSTANT),// ->54557
21029 : /*54453*/ OPC_RecordMemRef,
21030 : /*54454*/ OPC_RecordChild0, // #0 = $sbase
21031 : /*54455*/ OPC_RecordChild1, // #1 = $offset
21032 : /*54456*/ OPC_Scope, 66, /*->54524*/ // 2 children in Scope
21033 : /*54458*/ OPC_MoveChild, 1,
21034 : /*54460*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
21035 : /*54463*/ OPC_Scope, 17, /*->54482*/ // 3 children in Scope
21036 : /*54465*/ OPC_CheckPredicate, 57, // Predicate_IMM8bitDWORD
21037 : /*54467*/ OPC_MoveParent,
21038 : /*54468*/ OPC_CheckPatternPredicate, 6, // (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
21039 : /*54470*/ OPC_EmitNodeXForm, 3, 1, // as_dword_i32imm
21040 : /*54473*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BUFFER_LOAD_DWORD_IMM), 0|OPFL_MemRefs,
21041 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 2,
21042 : // Src: (SIload_constant:f32 v4i32:v4i32:$sbase, (imm:i32)<<P:Predicate_IMM8bitDWORD>>:$offset) - Complexity = 7
21043 : // Dst: (S_BUFFER_LOAD_DWORD_IMM:f32 ?:v4i32:$sbase, (as_dword_i32imm:i32 ?:i32:$offset))
21044 : /*54482*/ /*Scope*/ 17, /*->54500*/
21045 : /*54483*/ OPC_CheckPredicate, 58, // Predicate_IMM20bit
21046 : /*54485*/ OPC_MoveParent,
21047 : /*54486*/ OPC_CheckPatternPredicate, 7, // (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
21048 : /*54488*/ OPC_EmitNodeXForm, 4, 1, // as_i32imm
21049 : /*54491*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BUFFER_LOAD_DWORD_IMM), 0|OPFL_MemRefs,
21050 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 2,
21051 : // Src: (SIload_constant:f32 v4i32:v4i32:$sbase, (imm:i32)<<P:Predicate_IMM20bit>>:$offset) - Complexity = 7
21052 : // Dst: (S_BUFFER_LOAD_DWORD_IMM:f32 ?:v4i32:$sbase, (as_i32imm:i32 ?:i32:$offset))
21053 : /*54500*/ /*Scope*/ 22, /*->54523*/
21054 : /*54501*/ OPC_MoveParent,
21055 : /*54502*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
21056 : /*54504*/ OPC_EmitConvertToTarget, 1,
21057 : /*54506*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
21058 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 2, // Results = #3
21059 : /*54514*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR), 0|OPFL_MemRefs,
21060 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 3,
21061 : // Src: (SIload_constant:f32 v4i32:v4i32:$sbase, (imm:i32):$offset) - Complexity = 6
21062 : // Dst: (S_BUFFER_LOAD_DWORD_SGPR:f32 ?:v4i32:$sbase, (S_MOV_B32:i32 (imm:i32):$offset))
21063 : /*54523*/ 0, /*End of Scope*/
21064 : /*54524*/ /*Scope*/ 31, /*->54556*/
21065 : /*54525*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
21066 : /*54527*/ OPC_EmitInteger, MVT::i32, 0,
21067 : /*54530*/ OPC_EmitInteger, MVT::i16, 0,
21068 : /*54533*/ OPC_EmitInteger, MVT::i1, 0,
21069 : /*54536*/ OPC_EmitInteger, MVT::i1, 0,
21070 : /*54539*/ OPC_EmitInteger, MVT::i1, 0,
21071 : /*54542*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), 0|OPFL_MemRefs,
21072 : 1/*#VTs*/, MVT::f32, 7/*#Ops*/, 1, 0, 2, 3, 4, 5, 6,
21073 : // Src: (SIload_constant:f32 v4i32:v4i32:$sbase, i32:i32:$voff) - Complexity = 3
21074 : // Dst: (BUFFER_LOAD_DWORD_OFFEN:f32 ?:i32:$voff, ?:v4i32:$sbase, 0:i32, 0:i16, 0:i1, 0:i1, 0:i1)
21075 : /*54556*/ 0, /*End of Scope*/
21076 : /*54557*/ /*SwitchOpcode*/ 106|128,3/*490*/, TARGET_VAL(AMDGPUISD::RCP),// ->55051
21077 : /*54561*/ OPC_Scope, 113|128,1/*241*/, /*->54805*/ // 2 children in Scope
21078 : /*54564*/ OPC_MoveChild, 0,
21079 : /*54566*/ OPC_CheckOpcode, TARGET_VAL(ISD::FSQRT),
21080 : /*54569*/ OPC_RecordChild0, // #0 = $src
21081 : /*54570*/ OPC_MoveParent,
21082 : /*54571*/ OPC_SwitchType /*2 cases */, 89|128,1/*217*/, MVT::f32,// ->54792
21083 : /*54575*/ OPC_Scope, 67, /*->54644*/ // 4 children in Scope
21084 : /*54577*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
21085 : /*54579*/ OPC_EmitInteger, MVT::i32, 1,
21086 : /*54582*/ OPC_EmitInteger, MVT::i32, 0,
21087 : /*54585*/ OPC_EmitInteger, MVT::i32, 0,
21088 : /*54588*/ OPC_EmitInteger, MVT::i32, 0,
21089 : /*54591*/ OPC_EmitInteger, MVT::i32, 0,
21090 : /*54594*/ OPC_EmitInteger, MVT::i32, 0,
21091 : /*54597*/ OPC_EmitInteger, MVT::i32, 0,
21092 : /*54600*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21093 : /*54612*/ OPC_EmitInteger, MVT::i32, 1,
21094 : /*54615*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21095 : /*54618*/ OPC_EmitInteger, MVT::i32, 0,
21096 : /*54621*/ OPC_EmitInteger, MVT::i32, 0,
21097 : /*54624*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIPSQRT_IEEE_r600), 0,
21098 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21099 : // Src: (AMDGPUrcp:f32 (fsqrt:f32 f32:f32:$src)) - Complexity = 6
21100 : // Dst: (RECIPSQRT_IEEE_r600:f32 ?:f32:$src)
21101 : /*54644*/ /*Scope*/ 67, /*->54712*/
21102 : /*54645*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
21103 : /*54647*/ OPC_EmitInteger, MVT::i32, 1,
21104 : /*54650*/ OPC_EmitInteger, MVT::i32, 0,
21105 : /*54653*/ OPC_EmitInteger, MVT::i32, 0,
21106 : /*54656*/ OPC_EmitInteger, MVT::i32, 0,
21107 : /*54659*/ OPC_EmitInteger, MVT::i32, 0,
21108 : /*54662*/ OPC_EmitInteger, MVT::i32, 0,
21109 : /*54665*/ OPC_EmitInteger, MVT::i32, 0,
21110 : /*54668*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21111 : /*54680*/ OPC_EmitInteger, MVT::i32, 1,
21112 : /*54683*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21113 : /*54686*/ OPC_EmitInteger, MVT::i32, 0,
21114 : /*54689*/ OPC_EmitInteger, MVT::i32, 0,
21115 : /*54692*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIPSQRT_IEEE_eg), 0,
21116 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21117 : // Src: (AMDGPUrcp:f32 (fsqrt:f32 f32:f32:$src)) - Complexity = 6
21118 : // Dst: (RECIPSQRT_IEEE_eg:f32 ?:f32:$src)
21119 : /*54712*/ /*Scope*/ 67, /*->54780*/
21120 : /*54713*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
21121 : /*54715*/ OPC_EmitInteger, MVT::i32, 1,
21122 : /*54718*/ OPC_EmitInteger, MVT::i32, 0,
21123 : /*54721*/ OPC_EmitInteger, MVT::i32, 0,
21124 : /*54724*/ OPC_EmitInteger, MVT::i32, 0,
21125 : /*54727*/ OPC_EmitInteger, MVT::i32, 0,
21126 : /*54730*/ OPC_EmitInteger, MVT::i32, 0,
21127 : /*54733*/ OPC_EmitInteger, MVT::i32, 0,
21128 : /*54736*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21129 : /*54748*/ OPC_EmitInteger, MVT::i32, 1,
21130 : /*54751*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21131 : /*54754*/ OPC_EmitInteger, MVT::i32, 0,
21132 : /*54757*/ OPC_EmitInteger, MVT::i32, 0,
21133 : /*54760*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIPSQRT_IEEE_cm), 0,
21134 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21135 : // Src: (AMDGPUrcp:f32 (fsqrt:f32 f32:f32:$src)) - Complexity = 6
21136 : // Dst: (RECIPSQRT_IEEE_cm:f32 ?:f32:$src)
21137 : /*54780*/ /*Scope*/ 10, /*->54791*/
21138 : /*54781*/ OPC_CheckPatternPredicate, 14, // (TM.Options.UnsafeFPMath)
21139 : /*54783*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_RSQ_F32_e32), 0,
21140 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 0,
21141 : // Src: (AMDGPUrcp:f32 (fsqrt:f32 f32:f32:$src)) - Complexity = 6
21142 : // Dst: (V_RSQ_F32_e32:f32 ?:f32:$src)
21143 : /*54791*/ 0, /*End of Scope*/
21144 : /*54792*/ /*SwitchType*/ 10, MVT::f64,// ->54804
21145 : /*54794*/ OPC_CheckPatternPredicate, 14, // (TM.Options.UnsafeFPMath)
21146 : /*54796*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_RSQ_F64_e32), 0,
21147 : 1/*#VTs*/, MVT::f64, 1/*#Ops*/, 0,
21148 : // Src: (AMDGPUrcp:f64 (fsqrt:f64 f64:f64:$src)) - Complexity = 6
21149 : // Dst: (V_RSQ_F64_e32:f64 ?:f64:$src)
21150 : /*54804*/ 0, // EndSwitchType
21151 : /*54805*/ /*Scope*/ 115|128,1/*243*/, /*->55050*/
21152 : /*54807*/ OPC_RecordChild0, // #0 = $src0
21153 : /*54808*/ OPC_SwitchType /*2 cases */, 93|128,1/*221*/, MVT::f32,// ->55033
21154 : /*54812*/ OPC_Scope, 67, /*->54881*/ // 4 children in Scope
21155 : /*54814*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
21156 : /*54816*/ OPC_EmitInteger, MVT::i32, 1,
21157 : /*54819*/ OPC_EmitInteger, MVT::i32, 0,
21158 : /*54822*/ OPC_EmitInteger, MVT::i32, 0,
21159 : /*54825*/ OPC_EmitInteger, MVT::i32, 0,
21160 : /*54828*/ OPC_EmitInteger, MVT::i32, 0,
21161 : /*54831*/ OPC_EmitInteger, MVT::i32, 0,
21162 : /*54834*/ OPC_EmitInteger, MVT::i32, 0,
21163 : /*54837*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21164 : /*54849*/ OPC_EmitInteger, MVT::i32, 1,
21165 : /*54852*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21166 : /*54855*/ OPC_EmitInteger, MVT::i32, 0,
21167 : /*54858*/ OPC_EmitInteger, MVT::i32, 0,
21168 : /*54861*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIP_IEEE_r600), 0,
21169 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21170 : // Src: (AMDGPUrcp:f32 f32:f32:$src0) - Complexity = 3
21171 : // Dst: (RECIP_IEEE_r600:f32 f32:f32:$src0)
21172 : /*54881*/ /*Scope*/ 67, /*->54949*/
21173 : /*54882*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
21174 : /*54884*/ OPC_EmitInteger, MVT::i32, 1,
21175 : /*54887*/ OPC_EmitInteger, MVT::i32, 0,
21176 : /*54890*/ OPC_EmitInteger, MVT::i32, 0,
21177 : /*54893*/ OPC_EmitInteger, MVT::i32, 0,
21178 : /*54896*/ OPC_EmitInteger, MVT::i32, 0,
21179 : /*54899*/ OPC_EmitInteger, MVT::i32, 0,
21180 : /*54902*/ OPC_EmitInteger, MVT::i32, 0,
21181 : /*54905*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21182 : /*54917*/ OPC_EmitInteger, MVT::i32, 1,
21183 : /*54920*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21184 : /*54923*/ OPC_EmitInteger, MVT::i32, 0,
21185 : /*54926*/ OPC_EmitInteger, MVT::i32, 0,
21186 : /*54929*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIP_IEEE_eg), 0,
21187 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21188 : // Src: (AMDGPUrcp:f32 f32:f32:$src0) - Complexity = 3
21189 : // Dst: (RECIP_IEEE_eg:f32 f32:f32:$src0)
21190 : /*54949*/ /*Scope*/ 67, /*->55017*/
21191 : /*54950*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
21192 : /*54952*/ OPC_EmitInteger, MVT::i32, 1,
21193 : /*54955*/ OPC_EmitInteger, MVT::i32, 0,
21194 : /*54958*/ OPC_EmitInteger, MVT::i32, 0,
21195 : /*54961*/ OPC_EmitInteger, MVT::i32, 0,
21196 : /*54964*/ OPC_EmitInteger, MVT::i32, 0,
21197 : /*54967*/ OPC_EmitInteger, MVT::i32, 0,
21198 : /*54970*/ OPC_EmitInteger, MVT::i32, 0,
21199 : /*54973*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21200 : /*54985*/ OPC_EmitInteger, MVT::i32, 1,
21201 : /*54988*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21202 : /*54991*/ OPC_EmitInteger, MVT::i32, 0,
21203 : /*54994*/ OPC_EmitInteger, MVT::i32, 0,
21204 : /*54997*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIP_IEEE_cm), 0,
21205 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21206 : // Src: (AMDGPUrcp:f32 f32:f32:$src0) - Complexity = 3
21207 : // Dst: (RECIP_IEEE_cm:f32 f32:f32:$src0)
21208 : /*55017*/ /*Scope*/ 14, /*->55032*/
21209 : /*55018*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
21210 : /*55021*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_RCP_F32_e64), 0,
21211 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
21212 : // Src: (AMDGPUrcp:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
21213 : // Dst: (V_RCP_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
21214 : /*55032*/ 0, /*End of Scope*/
21215 : /*55033*/ /*SwitchType*/ 14, MVT::f64,// ->55049
21216 : /*55035*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
21217 : /*55038*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_RCP_F64_e64), 0,
21218 : 1/*#VTs*/, MVT::f64, 4/*#Ops*/, 2, 1, 3, 4,
21219 : // Src: (AMDGPUrcp:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
21220 : // Dst: (V_RCP_F64_e64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i1:i1:$clamp, i32:i32:$omod)
21221 : /*55049*/ 0, // EndSwitchType
21222 : /*55050*/ 0, /*End of Scope*/
21223 : /*55051*/ /*SwitchOpcode*/ 104|128,1/*232*/, TARGET_VAL(ISD::FNEG),// ->55287
21224 : /*55055*/ OPC_Scope, 110, /*->55167*/ // 2 children in Scope
21225 : /*55057*/ OPC_MoveChild, 0,
21226 : /*55059*/ OPC_CheckOpcode, TARGET_VAL(ISD::FABS),
21227 : /*55062*/ OPC_RecordChild0, // #0 = $src
21228 : /*55063*/ OPC_MoveParent,
21229 : /*55064*/ OPC_SwitchType /*2 cases */, 26, MVT::f32,// ->55093
21230 : /*55067*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
21231 : /*55069*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,0|128,0|128,8/*2147483648*/,
21232 : /*55076*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
21233 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1, // Results = #2
21234 : /*55084*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_OR_B32_e32), 0,
21235 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 2,
21236 : // Src: (fneg:f32 (fabs:f32 f32:f32:$src)) - Complexity = 6
21237 : // Dst: (V_OR_B32_e32:f32 ?:f32:$src, (V_MOV_B32_e32:i32 2147483648:i32))
21238 : /*55093*/ /*SwitchType*/ 71, MVT::f64,// ->55166
21239 : /*55095*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
21240 : /*55097*/ OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
21241 : /*55100*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
21242 : /*55103*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
21243 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
21244 : /*55112*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
21245 : /*55115*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
21246 : /*55118*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
21247 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
21248 : /*55127*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,0|128,0|128,8/*2147483648*/,
21249 : /*55134*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
21250 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 7, // Results = #8
21251 : /*55142*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_OR_B32_e32), 0,
21252 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 6, 8, // Results = #9
21253 : /*55151*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
21254 : /*55154*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
21255 : 1/*#VTs*/, MVT::f64, 5/*#Ops*/, 1, 3, 4, 9, 10,
21256 : // Src: (fneg:f64 (fabs:f64 f64:f64:$src)) - Complexity = 6
21257 : // Dst: (REG_SEQUENCE:f64 VReg_64:i32, (EXTRACT_SUBREG:i32 f64:f64:$src, sub0:i32), sub0:i32, (V_OR_B32_e32:i32 (EXTRACT_SUBREG:i32 f64:f64:$src, sub1:i32), (V_MOV_B32_e32:i32 2147483648:i32)), sub1:i32)
21258 : /*55166*/ 0, // EndSwitchType
21259 : /*55167*/ /*Scope*/ 118, /*->55286*/
21260 : /*55168*/ OPC_RecordChild0, // #0 = $src
21261 : /*55169*/ OPC_SwitchType /*2 cases */, 40, MVT::f32,// ->55212
21262 : /*55172*/ OPC_Scope, 26, /*->55200*/ // 2 children in Scope
21263 : /*55174*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
21264 : /*55176*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,0|128,0|128,8/*2147483648*/,
21265 : /*55183*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
21266 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1, // Results = #2
21267 : /*55191*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_XOR_B32_e32), 0,
21268 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 2,
21269 : // Src: (fneg:f32 f32:f32:$src) - Complexity = 3
21270 : // Dst: (V_XOR_B32_e32:f32 ?:f32:$src, (V_MOV_B32_e32:i32 2147483648:i32))
21271 : /*55200*/ /*Scope*/ 10, /*->55211*/
21272 : /*55201*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21273 : /*55203*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FNEG_R600), 0,
21274 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 0,
21275 : // Src: (fneg:f32 f32:f32:$src0) - Complexity = 3
21276 : // Dst: (FNEG_R600:f32 f32:f32:$src0)
21277 : /*55211*/ 0, /*End of Scope*/
21278 : /*55212*/ /*SwitchType*/ 71, MVT::f64,// ->55285
21279 : /*55214*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
21280 : /*55216*/ OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
21281 : /*55219*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
21282 : /*55222*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
21283 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
21284 : /*55231*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
21285 : /*55234*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
21286 : /*55237*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
21287 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
21288 : /*55246*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,0|128,0|128,8/*2147483648*/,
21289 : /*55253*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
21290 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 7, // Results = #8
21291 : /*55261*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_XOR_B32_e32), 0,
21292 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 6, 8, // Results = #9
21293 : /*55270*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
21294 : /*55273*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
21295 : 1/*#VTs*/, MVT::f64, 5/*#Ops*/, 1, 3, 4, 9, 10,
21296 : // Src: (fneg:f64 f64:f64:$src) - Complexity = 3
21297 : // Dst: (REG_SEQUENCE:f64 VReg_64:i32, (EXTRACT_SUBREG:i32 f64:f64:$src, sub0:i32), sub0:i32, (V_XOR_B32_e32:i32 (EXTRACT_SUBREG:i32 f64:f64:$src, sub1:i32), (V_MOV_B32_e32:i32 2147483648:i32)), sub1:i32)
21298 : /*55285*/ 0, // EndSwitchType
21299 : /*55286*/ 0, /*End of Scope*/
21300 : /*55287*/ /*SwitchOpcode*/ 72, TARGET_VAL(ISD::ConstantFP),// ->55362
21301 : /*55290*/ OPC_RecordNode, // #0 = $imm
21302 : /*55291*/ OPC_SwitchType /*2 cases */, 48, MVT::f32,// ->55342
21303 : /*55294*/ OPC_Scope, 15, /*->55311*/ // 2 children in Scope
21304 : /*55296*/ OPC_CheckPredicate, 141, // Predicate_anonymous_1456
21305 : /*55298*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
21306 : /*55300*/ OPC_EmitNodeXForm, 7, 0, // bitcast_fpimm_to_i32
21307 : /*55303*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
21308 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 1,
21309 : // Src: (fpimm:f32)<<P:Predicate_anonymous_1456>>:$imm - Complexity = 4
21310 : // Dst: (S_MOV_B32:f32 (bitcast_fpimm_to_i32:f32 ?:f32:$imm))
21311 : /*55311*/ /*Scope*/ 29, /*->55341*/
21312 : /*55312*/ OPC_Scope, 13, /*->55327*/ // 2 children in Scope
21313 : /*55314*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
21314 : /*55316*/ OPC_EmitNodeXForm, 7, 0, // bitcast_fpimm_to_i32
21315 : /*55319*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
21316 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 1,
21317 : // Src: (fpimm:f32):$imm - Complexity = 3
21318 : // Dst: (V_MOV_B32_e32:f32 (bitcast_fpimm_to_i32:f32 ?:f32:$imm))
21319 : /*55327*/ /*Scope*/ 12, /*->55340*/
21320 : /*55328*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21321 : /*55330*/ OPC_EmitConvertToTarget, 0,
21322 : /*55332*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MOV_IMM_F32), 0,
21323 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 1,
21324 : // Src: (fpimm:f32):$val - Complexity = 3
21325 : // Dst: (MOV_IMM_F32:f32 (fpimm:f32):$val)
21326 : /*55340*/ 0, /*End of Scope*/
21327 : /*55341*/ 0, /*End of Scope*/
21328 : /*55342*/ /*SwitchType*/ 17, MVT::f64,// ->55361
21329 : /*55344*/ OPC_CheckPredicate, 142, // Predicate_anonymous_1464
21330 : /*55346*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
21331 : /*55348*/ OPC_EmitConvertToTarget, 0,
21332 : /*55350*/ OPC_EmitNodeXForm, 8, 1, // bitcast_fpimm_to_i64
21333 : /*55353*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::S_MOV_B64), 0,
21334 : 1/*#VTs*/, MVT::f64, 1/*#Ops*/, 2,
21335 : // Src: (fpimm:f64)<<P:Predicate_anonymous_1464>>:$imm - Complexity = 4
21336 : // Dst: (S_MOV_B64:f64 (bitcast_fpimm_to_i64:f64 (fpimm:f64)<<P:Predicate_anonymous_1465>>:$imm))
21337 : /*55361*/ 0, // EndSwitchType
21338 : /*55362*/ /*SwitchOpcode*/ 67|128,1/*195*/, TARGET_VAL(ISD::FMUL),// ->55561
21339 : /*55366*/ OPC_RecordChild0, // #0 = $src0
21340 : /*55367*/ OPC_RecordChild1, // #1 = $src1
21341 : /*55368*/ OPC_SwitchType /*2 cases */, 16|128,1/*144*/, MVT::f32,// ->55516
21342 : /*55372*/ OPC_Scope, 101, /*->55475*/ // 3 children in Scope
21343 : /*55374*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21344 : /*55376*/ OPC_EmitInteger, MVT::i32, 0,
21345 : /*55379*/ OPC_EmitInteger, MVT::i32, 0,
21346 : /*55382*/ OPC_EmitInteger, MVT::i32, 1,
21347 : /*55385*/ OPC_EmitInteger, MVT::i32, 0,
21348 : /*55388*/ OPC_EmitInteger, MVT::i32, 0,
21349 : /*55391*/ OPC_EmitInteger, MVT::i32, 0,
21350 : /*55394*/ OPC_EmitInteger, MVT::i32, 0,
21351 : /*55397*/ OPC_EmitInteger, MVT::i32, 0,
21352 : /*55400*/ OPC_EmitInteger, MVT::i32, 0,
21353 : /*55403*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21354 : /*55415*/ OPC_EmitInteger, MVT::i32, 0,
21355 : /*55418*/ OPC_EmitInteger, MVT::i32, 0,
21356 : /*55421*/ OPC_EmitInteger, MVT::i32, 0,
21357 : /*55424*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21358 : /*55436*/ OPC_EmitInteger, MVT::i32, 1,
21359 : /*55439*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21360 : /*55442*/ OPC_EmitInteger, MVT::i32, 0,
21361 : /*55445*/ OPC_EmitInteger, MVT::i32, 0,
21362 : /*55448*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL_IEEE), 0,
21363 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
21364 : // Src: (fmul:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1) - Complexity = 3
21365 : // Dst: (MUL_IEEE:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1)
21366 : /*55475*/ /*Scope*/ 19, /*->55495*/
21367 : /*55476*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
21368 : /*55479*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
21369 : /*55482*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MUL_F32_e64), 0,
21370 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
21371 : // Src: (fmul:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
21372 : // Dst: (V_MUL_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
21373 : /*55495*/ /*Scope*/ 19, /*->55515*/
21374 : /*55496*/ OPC_CheckComplexPat, /*CP*/12, /*#*/0, // SelectVOP3Mods:$ #2 #3
21375 : /*55499*/ OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectVOP3Mods0:$ #4 #5 #6 #7
21376 : /*55502*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MUL_F32_e64), 0,
21377 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 5, 4, 3, 2, 6, 7,
21378 : // Src: (fmul:f32 (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -973
21379 : // Dst: (V_MUL_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
21380 : /*55515*/ 0, /*End of Scope*/
21381 : /*55516*/ /*SwitchType*/ 42, MVT::f64,// ->55560
21382 : /*55518*/ OPC_Scope, 19, /*->55539*/ // 2 children in Scope
21383 : /*55520*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
21384 : /*55523*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
21385 : /*55526*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MUL_F64), 0,
21386 : 1/*#VTs*/, MVT::f64, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
21387 : // Src: (fmul:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
21388 : // Dst: (V_MUL_F64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
21389 : /*55539*/ /*Scope*/ 19, /*->55559*/
21390 : /*55540*/ OPC_CheckComplexPat, /*CP*/12, /*#*/0, // SelectVOP3Mods:$ #2 #3
21391 : /*55543*/ OPC_CheckComplexPat, /*CP*/11, /*#*/1, // SelectVOP3Mods0:$ #4 #5 #6 #7
21392 : /*55546*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MUL_F64), 0,
21393 : 1/*#VTs*/, MVT::f64, 6/*#Ops*/, 5, 4, 3, 2, 6, 7,
21394 : // Src: (fmul:f64 (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -973
21395 : // Dst: (V_MUL_F64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
21396 : /*55559*/ 0, /*End of Scope*/
21397 : /*55560*/ 0, // EndSwitchType
21398 : /*55561*/ /*SwitchOpcode*/ 0|128,1/*128*/, TARGET_VAL(AMDGPUISD::FMAX_LEGACY),// ->55693
21399 : /*55565*/ OPC_RecordChild0, // #0 = $src0
21400 : /*55566*/ OPC_RecordChild1, // #1 = $src1
21401 : /*55567*/ OPC_CheckType, MVT::f32,
21402 : /*55569*/ OPC_Scope, 101, /*->55672*/ // 2 children in Scope
21403 : /*55571*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21404 : /*55573*/ OPC_EmitInteger, MVT::i32, 0,
21405 : /*55576*/ OPC_EmitInteger, MVT::i32, 0,
21406 : /*55579*/ OPC_EmitInteger, MVT::i32, 1,
21407 : /*55582*/ OPC_EmitInteger, MVT::i32, 0,
21408 : /*55585*/ OPC_EmitInteger, MVT::i32, 0,
21409 : /*55588*/ OPC_EmitInteger, MVT::i32, 0,
21410 : /*55591*/ OPC_EmitInteger, MVT::i32, 0,
21411 : /*55594*/ OPC_EmitInteger, MVT::i32, 0,
21412 : /*55597*/ OPC_EmitInteger, MVT::i32, 0,
21413 : /*55600*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21414 : /*55612*/ OPC_EmitInteger, MVT::i32, 0,
21415 : /*55615*/ OPC_EmitInteger, MVT::i32, 0,
21416 : /*55618*/ OPC_EmitInteger, MVT::i32, 0,
21417 : /*55621*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21418 : /*55633*/ OPC_EmitInteger, MVT::i32, 1,
21419 : /*55636*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21420 : /*55639*/ OPC_EmitInteger, MVT::i32, 0,
21421 : /*55642*/ OPC_EmitInteger, MVT::i32, 0,
21422 : /*55645*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MAX), 0,
21423 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
21424 : // Src: (AMDGPUfmax_legacy:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1) - Complexity = 3
21425 : // Dst: (MAX:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1)
21426 : /*55672*/ /*Scope*/ 19, /*->55692*/
21427 : /*55673*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
21428 : /*55676*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
21429 : /*55679*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAX_LEGACY_F32_e64), 0,
21430 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
21431 : // Src: (AMDGPUfmax_legacy:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
21432 : // Dst: (V_MAX_LEGACY_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
21433 : /*55692*/ 0, /*End of Scope*/
21434 : /*55693*/ /*SwitchOpcode*/ 0|128,1/*128*/, TARGET_VAL(AMDGPUISD::FMIN_LEGACY),// ->55825
21435 : /*55697*/ OPC_RecordChild0, // #0 = $src0
21436 : /*55698*/ OPC_RecordChild1, // #1 = $src1
21437 : /*55699*/ OPC_CheckType, MVT::f32,
21438 : /*55701*/ OPC_Scope, 101, /*->55804*/ // 2 children in Scope
21439 : /*55703*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21440 : /*55705*/ OPC_EmitInteger, MVT::i32, 0,
21441 : /*55708*/ OPC_EmitInteger, MVT::i32, 0,
21442 : /*55711*/ OPC_EmitInteger, MVT::i32, 1,
21443 : /*55714*/ OPC_EmitInteger, MVT::i32, 0,
21444 : /*55717*/ OPC_EmitInteger, MVT::i32, 0,
21445 : /*55720*/ OPC_EmitInteger, MVT::i32, 0,
21446 : /*55723*/ OPC_EmitInteger, MVT::i32, 0,
21447 : /*55726*/ OPC_EmitInteger, MVT::i32, 0,
21448 : /*55729*/ OPC_EmitInteger, MVT::i32, 0,
21449 : /*55732*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21450 : /*55744*/ OPC_EmitInteger, MVT::i32, 0,
21451 : /*55747*/ OPC_EmitInteger, MVT::i32, 0,
21452 : /*55750*/ OPC_EmitInteger, MVT::i32, 0,
21453 : /*55753*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21454 : /*55765*/ OPC_EmitInteger, MVT::i32, 1,
21455 : /*55768*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21456 : /*55771*/ OPC_EmitInteger, MVT::i32, 0,
21457 : /*55774*/ OPC_EmitInteger, MVT::i32, 0,
21458 : /*55777*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MIN), 0,
21459 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
21460 : // Src: (AMDGPUfmin_legacy:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1) - Complexity = 3
21461 : // Dst: (MIN:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1)
21462 : /*55804*/ /*Scope*/ 19, /*->55824*/
21463 : /*55805*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
21464 : /*55808*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
21465 : /*55811*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MIN_LEGACY_F32_e64), 0,
21466 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
21467 : // Src: (AMDGPUfmin_legacy:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
21468 : // Dst: (V_MIN_LEGACY_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
21469 : /*55824*/ 0, /*End of Scope*/
21470 : /*55825*/ /*SwitchOpcode*/ 23|128,1/*151*/, TARGET_VAL(ISD::FMAXNUM),// ->55980
21471 : /*55829*/ OPC_RecordChild0, // #0 = $src0
21472 : /*55830*/ OPC_RecordChild1, // #1 = $src1
21473 : /*55831*/ OPC_SwitchType /*2 cases */, 124, MVT::f32,// ->55958
21474 : /*55834*/ OPC_Scope, 101, /*->55937*/ // 2 children in Scope
21475 : /*55836*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21476 : /*55838*/ OPC_EmitInteger, MVT::i32, 0,
21477 : /*55841*/ OPC_EmitInteger, MVT::i32, 0,
21478 : /*55844*/ OPC_EmitInteger, MVT::i32, 1,
21479 : /*55847*/ OPC_EmitInteger, MVT::i32, 0,
21480 : /*55850*/ OPC_EmitInteger, MVT::i32, 0,
21481 : /*55853*/ OPC_EmitInteger, MVT::i32, 0,
21482 : /*55856*/ OPC_EmitInteger, MVT::i32, 0,
21483 : /*55859*/ OPC_EmitInteger, MVT::i32, 0,
21484 : /*55862*/ OPC_EmitInteger, MVT::i32, 0,
21485 : /*55865*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21486 : /*55877*/ OPC_EmitInteger, MVT::i32, 0,
21487 : /*55880*/ OPC_EmitInteger, MVT::i32, 0,
21488 : /*55883*/ OPC_EmitInteger, MVT::i32, 0,
21489 : /*55886*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21490 : /*55898*/ OPC_EmitInteger, MVT::i32, 1,
21491 : /*55901*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21492 : /*55904*/ OPC_EmitInteger, MVT::i32, 0,
21493 : /*55907*/ OPC_EmitInteger, MVT::i32, 0,
21494 : /*55910*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MAX_DX10), 0,
21495 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
21496 : // Src: (fmaxnum:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1) - Complexity = 3
21497 : // Dst: (MAX_DX10:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1)
21498 : /*55937*/ /*Scope*/ 19, /*->55957*/
21499 : /*55938*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
21500 : /*55941*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
21501 : /*55944*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAX_F32_e64), 0,
21502 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
21503 : // Src: (fmaxnum:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
21504 : // Dst: (V_MAX_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
21505 : /*55957*/ 0, /*End of Scope*/
21506 : /*55958*/ /*SwitchType*/ 19, MVT::f64,// ->55979
21507 : /*55960*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
21508 : /*55963*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
21509 : /*55966*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAX_F64), 0,
21510 : 1/*#VTs*/, MVT::f64, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
21511 : // Src: (fmaxnum:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
21512 : // Dst: (V_MAX_F64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
21513 : /*55979*/ 0, // EndSwitchType
21514 : /*55980*/ /*SwitchOpcode*/ 23|128,1/*151*/, TARGET_VAL(ISD::FMINNUM),// ->56135
21515 : /*55984*/ OPC_RecordChild0, // #0 = $src0
21516 : /*55985*/ OPC_RecordChild1, // #1 = $src1
21517 : /*55986*/ OPC_SwitchType /*2 cases */, 124, MVT::f32,// ->56113
21518 : /*55989*/ OPC_Scope, 101, /*->56092*/ // 2 children in Scope
21519 : /*55991*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21520 : /*55993*/ OPC_EmitInteger, MVT::i32, 0,
21521 : /*55996*/ OPC_EmitInteger, MVT::i32, 0,
21522 : /*55999*/ OPC_EmitInteger, MVT::i32, 1,
21523 : /*56002*/ OPC_EmitInteger, MVT::i32, 0,
21524 : /*56005*/ OPC_EmitInteger, MVT::i32, 0,
21525 : /*56008*/ OPC_EmitInteger, MVT::i32, 0,
21526 : /*56011*/ OPC_EmitInteger, MVT::i32, 0,
21527 : /*56014*/ OPC_EmitInteger, MVT::i32, 0,
21528 : /*56017*/ OPC_EmitInteger, MVT::i32, 0,
21529 : /*56020*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21530 : /*56032*/ OPC_EmitInteger, MVT::i32, 0,
21531 : /*56035*/ OPC_EmitInteger, MVT::i32, 0,
21532 : /*56038*/ OPC_EmitInteger, MVT::i32, 0,
21533 : /*56041*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21534 : /*56053*/ OPC_EmitInteger, MVT::i32, 1,
21535 : /*56056*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21536 : /*56059*/ OPC_EmitInteger, MVT::i32, 0,
21537 : /*56062*/ OPC_EmitInteger, MVT::i32, 0,
21538 : /*56065*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MIN_DX10), 0,
21539 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 2, 3, 4, 5, 6, 7, 0, 8, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18, 19,
21540 : // Src: (fminnum:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1) - Complexity = 3
21541 : // Dst: (MIN_DX10:f32 R600_Reg32:f32:$src0, R600_Reg32:f32:$src1)
21542 : /*56092*/ /*Scope*/ 19, /*->56112*/
21543 : /*56093*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
21544 : /*56096*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
21545 : /*56099*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MIN_F32_e64), 0,
21546 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
21547 : // Src: (fminnum:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
21548 : // Dst: (V_MIN_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i1:i1:$clamp, i32:i32:$omod)
21549 : /*56112*/ 0, /*End of Scope*/
21550 : /*56113*/ /*SwitchType*/ 19, MVT::f64,// ->56134
21551 : /*56115*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
21552 : /*56118*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
21553 : /*56121*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MIN_F64), 0,
21554 : 1/*#VTs*/, MVT::f64, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
21555 : // Src: (fminnum:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
21556 : // Dst: (V_MIN_F64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i1:i1:$clamp, i32:i32:$omod)
21557 : /*56134*/ 0, // EndSwitchType
21558 : /*56135*/ /*SwitchOpcode*/ 88, TARGET_VAL(AMDGPUISD::FRACT),// ->56226
21559 : /*56138*/ OPC_RecordChild0, // #0 = $src0
21560 : /*56139*/ OPC_CheckType, MVT::f32,
21561 : /*56141*/ OPC_Scope, 67, /*->56210*/ // 2 children in Scope
21562 : /*56143*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21563 : /*56145*/ OPC_EmitInteger, MVT::i32, 1,
21564 : /*56148*/ OPC_EmitInteger, MVT::i32, 0,
21565 : /*56151*/ OPC_EmitInteger, MVT::i32, 0,
21566 : /*56154*/ OPC_EmitInteger, MVT::i32, 0,
21567 : /*56157*/ OPC_EmitInteger, MVT::i32, 0,
21568 : /*56160*/ OPC_EmitInteger, MVT::i32, 0,
21569 : /*56163*/ OPC_EmitInteger, MVT::i32, 0,
21570 : /*56166*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21571 : /*56178*/ OPC_EmitInteger, MVT::i32, 1,
21572 : /*56181*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21573 : /*56184*/ OPC_EmitInteger, MVT::i32, 0,
21574 : /*56187*/ OPC_EmitInteger, MVT::i32, 0,
21575 : /*56190*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FRACT), 0,
21576 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21577 : // Src: (AMDGPUfract:f32 R600_Reg32:f32:$src0) - Complexity = 3
21578 : // Dst: (FRACT:f32 R600_Reg32:f32:$src0)
21579 : /*56210*/ /*Scope*/ 14, /*->56225*/
21580 : /*56211*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
21581 : /*56214*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_FRACT_F32_e64), 0,
21582 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
21583 : // Src: (AMDGPUfract:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
21584 : // Dst: (V_FRACT_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
21585 : /*56225*/ 0, /*End of Scope*/
21586 : /*56226*/ /*SwitchOpcode*/ 106, TARGET_VAL(ISD::FTRUNC),// ->56335
21587 : /*56229*/ OPC_RecordChild0, // #0 = $src0
21588 : /*56230*/ OPC_SwitchType /*2 cases */, 85, MVT::f32,// ->56318
21589 : /*56233*/ OPC_Scope, 67, /*->56302*/ // 2 children in Scope
21590 : /*56235*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21591 : /*56237*/ OPC_EmitInteger, MVT::i32, 1,
21592 : /*56240*/ OPC_EmitInteger, MVT::i32, 0,
21593 : /*56243*/ OPC_EmitInteger, MVT::i32, 0,
21594 : /*56246*/ OPC_EmitInteger, MVT::i32, 0,
21595 : /*56249*/ OPC_EmitInteger, MVT::i32, 0,
21596 : /*56252*/ OPC_EmitInteger, MVT::i32, 0,
21597 : /*56255*/ OPC_EmitInteger, MVT::i32, 0,
21598 : /*56258*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21599 : /*56270*/ OPC_EmitInteger, MVT::i32, 1,
21600 : /*56273*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21601 : /*56276*/ OPC_EmitInteger, MVT::i32, 0,
21602 : /*56279*/ OPC_EmitInteger, MVT::i32, 0,
21603 : /*56282*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TRUNC), 0,
21604 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21605 : // Src: (ftrunc:f32 R600_Reg32:f32:$src0) - Complexity = 3
21606 : // Dst: (TRUNC:f32 R600_Reg32:f32:$src0)
21607 : /*56302*/ /*Scope*/ 14, /*->56317*/
21608 : /*56303*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
21609 : /*56306*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_TRUNC_F32_e64), 0,
21610 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
21611 : // Src: (ftrunc:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
21612 : // Dst: (V_TRUNC_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
21613 : /*56317*/ 0, /*End of Scope*/
21614 : /*56318*/ /*SwitchType*/ 14, MVT::f64,// ->56334
21615 : /*56320*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
21616 : /*56323*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_TRUNC_F64_e64), 0,
21617 : 1/*#VTs*/, MVT::f64, 4/*#Ops*/, 2, 1, 3, 4,
21618 : // Src: (ftrunc:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
21619 : // Dst: (V_TRUNC_F64_e64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i1:i1:$clamp, i32:i32:$omod)
21620 : /*56334*/ 0, // EndSwitchType
21621 : /*56335*/ /*SwitchOpcode*/ 106, TARGET_VAL(ISD::FCEIL),// ->56444
21622 : /*56338*/ OPC_RecordChild0, // #0 = $src0
21623 : /*56339*/ OPC_SwitchType /*2 cases */, 85, MVT::f32,// ->56427
21624 : /*56342*/ OPC_Scope, 67, /*->56411*/ // 2 children in Scope
21625 : /*56344*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21626 : /*56346*/ OPC_EmitInteger, MVT::i32, 1,
21627 : /*56349*/ OPC_EmitInteger, MVT::i32, 0,
21628 : /*56352*/ OPC_EmitInteger, MVT::i32, 0,
21629 : /*56355*/ OPC_EmitInteger, MVT::i32, 0,
21630 : /*56358*/ OPC_EmitInteger, MVT::i32, 0,
21631 : /*56361*/ OPC_EmitInteger, MVT::i32, 0,
21632 : /*56364*/ OPC_EmitInteger, MVT::i32, 0,
21633 : /*56367*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21634 : /*56379*/ OPC_EmitInteger, MVT::i32, 1,
21635 : /*56382*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21636 : /*56385*/ OPC_EmitInteger, MVT::i32, 0,
21637 : /*56388*/ OPC_EmitInteger, MVT::i32, 0,
21638 : /*56391*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::CEIL), 0,
21639 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21640 : // Src: (fceil:f32 R600_Reg32:f32:$src0) - Complexity = 3
21641 : // Dst: (CEIL:f32 R600_Reg32:f32:$src0)
21642 : /*56411*/ /*Scope*/ 14, /*->56426*/
21643 : /*56412*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
21644 : /*56415*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CEIL_F32_e64), 0,
21645 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
21646 : // Src: (fceil:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
21647 : // Dst: (V_CEIL_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
21648 : /*56426*/ 0, /*End of Scope*/
21649 : /*56427*/ /*SwitchType*/ 14, MVT::f64,// ->56443
21650 : /*56429*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
21651 : /*56432*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CEIL_F64_e64), 0,
21652 : 1/*#VTs*/, MVT::f64, 4/*#Ops*/, 2, 1, 3, 4,
21653 : // Src: (fceil:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
21654 : // Dst: (V_CEIL_F64_e64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i1:i1:$clamp, i32:i32:$omod)
21655 : /*56443*/ 0, // EndSwitchType
21656 : /*56444*/ /*SwitchOpcode*/ 106, TARGET_VAL(ISD::FRINT),// ->56553
21657 : /*56447*/ OPC_RecordChild0, // #0 = $src0
21658 : /*56448*/ OPC_SwitchType /*2 cases */, 85, MVT::f32,// ->56536
21659 : /*56451*/ OPC_Scope, 67, /*->56520*/ // 2 children in Scope
21660 : /*56453*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21661 : /*56455*/ OPC_EmitInteger, MVT::i32, 1,
21662 : /*56458*/ OPC_EmitInteger, MVT::i32, 0,
21663 : /*56461*/ OPC_EmitInteger, MVT::i32, 0,
21664 : /*56464*/ OPC_EmitInteger, MVT::i32, 0,
21665 : /*56467*/ OPC_EmitInteger, MVT::i32, 0,
21666 : /*56470*/ OPC_EmitInteger, MVT::i32, 0,
21667 : /*56473*/ OPC_EmitInteger, MVT::i32, 0,
21668 : /*56476*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21669 : /*56488*/ OPC_EmitInteger, MVT::i32, 1,
21670 : /*56491*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21671 : /*56494*/ OPC_EmitInteger, MVT::i32, 0,
21672 : /*56497*/ OPC_EmitInteger, MVT::i32, 0,
21673 : /*56500*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RNDNE), 0,
21674 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21675 : // Src: (frint:f32 R600_Reg32:f32:$src0) - Complexity = 3
21676 : // Dst: (RNDNE:f32 R600_Reg32:f32:$src0)
21677 : /*56520*/ /*Scope*/ 14, /*->56535*/
21678 : /*56521*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
21679 : /*56524*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_RNDNE_F32_e64), 0,
21680 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
21681 : // Src: (frint:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
21682 : // Dst: (V_RNDNE_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
21683 : /*56535*/ 0, /*End of Scope*/
21684 : /*56536*/ /*SwitchType*/ 14, MVT::f64,// ->56552
21685 : /*56538*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
21686 : /*56541*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_RNDNE_F64_e64), 0,
21687 : 1/*#VTs*/, MVT::f64, 4/*#Ops*/, 2, 1, 3, 4,
21688 : // Src: (frint:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
21689 : // Dst: (V_RNDNE_F64_e64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i1:i1:$clamp, i32:i32:$omod)
21690 : /*56552*/ 0, // EndSwitchType
21691 : /*56553*/ /*SwitchOpcode*/ 91|128,2/*347*/, TARGET_VAL(AMDGPUISD::DOT4),// ->56904
21692 : /*56557*/ OPC_RecordChild0, // #0 = $src0_X
21693 : /*56558*/ OPC_RecordChild1, // #1 = $src1_X
21694 : /*56559*/ OPC_RecordChild2, // #2 = $src0_Y
21695 : /*56560*/ OPC_RecordChild3, // #3 = $src1_Y
21696 : /*56561*/ OPC_RecordChild4, // #4 = $src0_Z
21697 : /*56562*/ OPC_RecordChild5, // #5 = $src1_Z
21698 : /*56563*/ OPC_RecordChild6, // #6 = $src0_W
21699 : /*56564*/ OPC_RecordChild7, // #7 = $src1_W
21700 : /*56565*/ OPC_CheckType, MVT::f32,
21701 : /*56567*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
21702 : /*56569*/ OPC_EmitInteger, MVT::i32, 0,
21703 : /*56572*/ OPC_EmitInteger, MVT::i32, 0,
21704 : /*56575*/ OPC_EmitInteger, MVT::i32, 1,
21705 : /*56578*/ OPC_EmitInteger, MVT::i32, 0,
21706 : /*56581*/ OPC_EmitInteger, MVT::i32, 0,
21707 : /*56584*/ OPC_EmitInteger, MVT::i32, 0,
21708 : /*56587*/ OPC_EmitInteger, MVT::i32, 0,
21709 : /*56590*/ OPC_EmitInteger, MVT::i32, 0,
21710 : /*56593*/ OPC_EmitInteger, MVT::i32, 0,
21711 : /*56596*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21712 : /*56608*/ OPC_EmitInteger, MVT::i32, 0,
21713 : /*56611*/ OPC_EmitInteger, MVT::i32, 0,
21714 : /*56614*/ OPC_EmitInteger, MVT::i32, 0,
21715 : /*56617*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21716 : /*56629*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21717 : /*56632*/ OPC_EmitInteger, MVT::i32, 0,
21718 : /*56635*/ OPC_EmitInteger, MVT::i32, 0,
21719 : /*56638*/ OPC_EmitInteger, MVT::i32, 1,
21720 : /*56641*/ OPC_EmitInteger, MVT::i32, 0,
21721 : /*56644*/ OPC_EmitInteger, MVT::i32, 0,
21722 : /*56647*/ OPC_EmitInteger, MVT::i32, 0,
21723 : /*56650*/ OPC_EmitInteger, MVT::i32, 0,
21724 : /*56653*/ OPC_EmitInteger, MVT::i32, 0,
21725 : /*56656*/ OPC_EmitInteger, MVT::i32, 0,
21726 : /*56659*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21727 : /*56671*/ OPC_EmitInteger, MVT::i32, 0,
21728 : /*56674*/ OPC_EmitInteger, MVT::i32, 0,
21729 : /*56677*/ OPC_EmitInteger, MVT::i32, 0,
21730 : /*56680*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21731 : /*56692*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21732 : /*56695*/ OPC_EmitInteger, MVT::i32, 0,
21733 : /*56698*/ OPC_EmitInteger, MVT::i32, 0,
21734 : /*56701*/ OPC_EmitInteger, MVT::i32, 1,
21735 : /*56704*/ OPC_EmitInteger, MVT::i32, 0,
21736 : /*56707*/ OPC_EmitInteger, MVT::i32, 0,
21737 : /*56710*/ OPC_EmitInteger, MVT::i32, 0,
21738 : /*56713*/ OPC_EmitInteger, MVT::i32, 0,
21739 : /*56716*/ OPC_EmitInteger, MVT::i32, 0,
21740 : /*56719*/ OPC_EmitInteger, MVT::i32, 0,
21741 : /*56722*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21742 : /*56734*/ OPC_EmitInteger, MVT::i32, 0,
21743 : /*56737*/ OPC_EmitInteger, MVT::i32, 0,
21744 : /*56740*/ OPC_EmitInteger, MVT::i32, 0,
21745 : /*56743*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21746 : /*56755*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21747 : /*56758*/ OPC_EmitInteger, MVT::i32, 0,
21748 : /*56761*/ OPC_EmitInteger, MVT::i32, 0,
21749 : /*56764*/ OPC_EmitInteger, MVT::i32, 1,
21750 : /*56767*/ OPC_EmitInteger, MVT::i32, 0,
21751 : /*56770*/ OPC_EmitInteger, MVT::i32, 0,
21752 : /*56773*/ OPC_EmitInteger, MVT::i32, 0,
21753 : /*56776*/ OPC_EmitInteger, MVT::i32, 0,
21754 : /*56779*/ OPC_EmitInteger, MVT::i32, 0,
21755 : /*56782*/ OPC_EmitInteger, MVT::i32, 0,
21756 : /*56785*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21757 : /*56797*/ OPC_EmitInteger, MVT::i32, 0,
21758 : /*56800*/ OPC_EmitInteger, MVT::i32, 0,
21759 : /*56803*/ OPC_EmitInteger, MVT::i32, 0,
21760 : /*56806*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21761 : /*56818*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21762 : /*56821*/ OPC_EmitInteger, MVT::i32, 0,
21763 : /*56824*/ OPC_EmitInteger, MVT::i32, 0,
21764 : /*56827*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::DOT_4), 0,
21765 : 1/*#VTs*/, MVT::f32, 70/*#Ops*/, 8, 9, 10, 11, 12, 13, 0, 14, 15, 16, 17, 1, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 2, 29, 30, 31, 32, 3, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 4, 44, 45, 46, 47, 5, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 6, 59, 60, 61, 62, 7, 63, 64, 65, 66, 67, 68, 69,
21766 : // Src: (DOT4:f32 R600_TReg32_X:f32:$src0_X, R600_TReg32_X:f32:$src1_X, R600_TReg32_Y:f32:$src0_Y, R600_TReg32_Y:f32:$src1_Y, R600_TReg32_Z:f32:$src0_Z, R600_TReg32_Z:f32:$src1_Z, R600_TReg32_W:f32:$src0_W, R600_TReg32_W:f32:$src1_W) - Complexity = 3
21767 : // Dst: (DOT_4:f32 R600_TReg32_X:f32:$src0_X, R600_TReg32_X:f32:$src1_X, R600_TReg32_Y:f32:$src0_Y, R600_TReg32_Y:f32:$src1_Y, R600_TReg32_Z:f32:$src0_Z, R600_TReg32_Z:f32:$src1_Z, R600_TReg32_W:f32:$src0_W, R600_TReg32_W:f32:$src1_W)
21768 : /*56904*/ /*SwitchOpcode*/ 104|128,1/*232*/, TARGET_VAL(ISD::FMAD),// ->57140
21769 : /*56908*/ OPC_RecordChild0, // #0 = $src0
21770 : /*56909*/ OPC_RecordChild1, // #1 = $src1
21771 : /*56910*/ OPC_RecordChild2, // #2 = $src2
21772 : /*56911*/ OPC_CheckType, MVT::f32,
21773 : /*56913*/ OPC_Scope, 99, /*->57014*/ // 3 children in Scope
21774 : /*56915*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
21775 : /*56917*/ OPC_EmitInteger, MVT::i32, 0,
21776 : /*56920*/ OPC_EmitInteger, MVT::i32, 0,
21777 : /*56923*/ OPC_EmitInteger, MVT::i32, 0,
21778 : /*56926*/ OPC_EmitInteger, MVT::i32, 0,
21779 : /*56929*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21780 : /*56941*/ OPC_EmitInteger, MVT::i32, 0,
21781 : /*56944*/ OPC_EmitInteger, MVT::i32, 0,
21782 : /*56947*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21783 : /*56959*/ OPC_EmitInteger, MVT::i32, 0,
21784 : /*56962*/ OPC_EmitInteger, MVT::i32, 0,
21785 : /*56965*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21786 : /*56977*/ OPC_EmitInteger, MVT::i32, 1,
21787 : /*56980*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21788 : /*56983*/ OPC_EmitInteger, MVT::i32, 0,
21789 : /*56986*/ OPC_EmitInteger, MVT::i32, 0,
21790 : /*56989*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULADD_IEEE_r600), 0,
21791 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
21792 : // Src: (fmad:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2) - Complexity = 3
21793 : // Dst: (MULADD_IEEE_r600:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2)
21794 : /*57014*/ /*Scope*/ 99, /*->57114*/
21795 : /*57015*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
21796 : /*57017*/ OPC_EmitInteger, MVT::i32, 0,
21797 : /*57020*/ OPC_EmitInteger, MVT::i32, 0,
21798 : /*57023*/ OPC_EmitInteger, MVT::i32, 0,
21799 : /*57026*/ OPC_EmitInteger, MVT::i32, 0,
21800 : /*57029*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21801 : /*57041*/ OPC_EmitInteger, MVT::i32, 0,
21802 : /*57044*/ OPC_EmitInteger, MVT::i32, 0,
21803 : /*57047*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21804 : /*57059*/ OPC_EmitInteger, MVT::i32, 0,
21805 : /*57062*/ OPC_EmitInteger, MVT::i32, 0,
21806 : /*57065*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21807 : /*57077*/ OPC_EmitInteger, MVT::i32, 1,
21808 : /*57080*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21809 : /*57083*/ OPC_EmitInteger, MVT::i32, 0,
21810 : /*57086*/ OPC_EmitInteger, MVT::i32, 0,
21811 : /*57089*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MULADD_IEEE_eg), 0,
21812 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
21813 : // Src: (fmad:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2) - Complexity = 3
21814 : // Dst: (MULADD_IEEE_eg:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2)
21815 : /*57114*/ /*Scope*/ 24, /*->57139*/
21816 : /*57115*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #3 #4 #5 #6
21817 : /*57118*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #7 #8
21818 : /*57121*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // SelectVOP3Mods:$ #9 #10
21819 : /*57124*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAD_F32), 0,
21820 : 1/*#VTs*/, MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
21821 : // Src: (fmad:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (VOP3Mods:f32 f32:f32:$src2, i32:i32:$src2_modifiers)) - Complexity = -964
21822 : // Dst: (V_MAD_F32:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i32:i32:$src2_modifiers, f32:f32:$src2, i1:i1:$clamp, i32:i32:$omod)
21823 : /*57139*/ 0, /*End of Scope*/
21824 : /*57140*/ /*SwitchOpcode*/ 96|128,1/*224*/, TARGET_VAL(ISD::FEXP2),// ->57368
21825 : /*57144*/ OPC_RecordChild0, // #0 = $src0
21826 : /*57145*/ OPC_CheckType, MVT::f32,
21827 : /*57147*/ OPC_Scope, 67, /*->57216*/ // 4 children in Scope
21828 : /*57149*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
21829 : /*57151*/ OPC_EmitInteger, MVT::i32, 1,
21830 : /*57154*/ OPC_EmitInteger, MVT::i32, 0,
21831 : /*57157*/ OPC_EmitInteger, MVT::i32, 0,
21832 : /*57160*/ OPC_EmitInteger, MVT::i32, 0,
21833 : /*57163*/ OPC_EmitInteger, MVT::i32, 0,
21834 : /*57166*/ OPC_EmitInteger, MVT::i32, 0,
21835 : /*57169*/ OPC_EmitInteger, MVT::i32, 0,
21836 : /*57172*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21837 : /*57184*/ OPC_EmitInteger, MVT::i32, 1,
21838 : /*57187*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21839 : /*57190*/ OPC_EmitInteger, MVT::i32, 0,
21840 : /*57193*/ OPC_EmitInteger, MVT::i32, 0,
21841 : /*57196*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EXP_IEEE_r600), 0,
21842 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21843 : // Src: (fexp2:f32 R600_Reg32:f32:$src0) - Complexity = 3
21844 : // Dst: (EXP_IEEE_r600:f32 R600_Reg32:f32:$src0)
21845 : /*57216*/ /*Scope*/ 67, /*->57284*/
21846 : /*57217*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
21847 : /*57219*/ OPC_EmitInteger, MVT::i32, 1,
21848 : /*57222*/ OPC_EmitInteger, MVT::i32, 0,
21849 : /*57225*/ OPC_EmitInteger, MVT::i32, 0,
21850 : /*57228*/ OPC_EmitInteger, MVT::i32, 0,
21851 : /*57231*/ OPC_EmitInteger, MVT::i32, 0,
21852 : /*57234*/ OPC_EmitInteger, MVT::i32, 0,
21853 : /*57237*/ OPC_EmitInteger, MVT::i32, 0,
21854 : /*57240*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21855 : /*57252*/ OPC_EmitInteger, MVT::i32, 1,
21856 : /*57255*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21857 : /*57258*/ OPC_EmitInteger, MVT::i32, 0,
21858 : /*57261*/ OPC_EmitInteger, MVT::i32, 0,
21859 : /*57264*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EXP_IEEE_eg), 0,
21860 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21861 : // Src: (fexp2:f32 R600_Reg32:f32:$src0) - Complexity = 3
21862 : // Dst: (EXP_IEEE_eg:f32 R600_Reg32:f32:$src0)
21863 : /*57284*/ /*Scope*/ 67, /*->57352*/
21864 : /*57285*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
21865 : /*57287*/ OPC_EmitInteger, MVT::i32, 1,
21866 : /*57290*/ OPC_EmitInteger, MVT::i32, 0,
21867 : /*57293*/ OPC_EmitInteger, MVT::i32, 0,
21868 : /*57296*/ OPC_EmitInteger, MVT::i32, 0,
21869 : /*57299*/ OPC_EmitInteger, MVT::i32, 0,
21870 : /*57302*/ OPC_EmitInteger, MVT::i32, 0,
21871 : /*57305*/ OPC_EmitInteger, MVT::i32, 0,
21872 : /*57308*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21873 : /*57320*/ OPC_EmitInteger, MVT::i32, 1,
21874 : /*57323*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21875 : /*57326*/ OPC_EmitInteger, MVT::i32, 0,
21876 : /*57329*/ OPC_EmitInteger, MVT::i32, 0,
21877 : /*57332*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EXP_IEEE_cm), 0,
21878 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21879 : // Src: (fexp2:f32 R600_Reg32:f32:$src0) - Complexity = 3
21880 : // Dst: (EXP_IEEE_cm:f32 R600_Reg32:f32:$src0)
21881 : /*57352*/ /*Scope*/ 14, /*->57367*/
21882 : /*57353*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
21883 : /*57356*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_EXP_F32_e64), 0,
21884 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
21885 : // Src: (fexp2:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
21886 : // Dst: (V_EXP_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
21887 : /*57367*/ 0, /*End of Scope*/
21888 : /*57368*/ /*SwitchOpcode*/ 96|128,1/*224*/, TARGET_VAL(ISD::FLOG2),// ->57596
21889 : /*57372*/ OPC_RecordChild0, // #0 = $src0
21890 : /*57373*/ OPC_CheckType, MVT::f32,
21891 : /*57375*/ OPC_Scope, 67, /*->57444*/ // 4 children in Scope
21892 : /*57377*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
21893 : /*57379*/ OPC_EmitInteger, MVT::i32, 1,
21894 : /*57382*/ OPC_EmitInteger, MVT::i32, 0,
21895 : /*57385*/ OPC_EmitInteger, MVT::i32, 0,
21896 : /*57388*/ OPC_EmitInteger, MVT::i32, 0,
21897 : /*57391*/ OPC_EmitInteger, MVT::i32, 0,
21898 : /*57394*/ OPC_EmitInteger, MVT::i32, 0,
21899 : /*57397*/ OPC_EmitInteger, MVT::i32, 0,
21900 : /*57400*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21901 : /*57412*/ OPC_EmitInteger, MVT::i32, 1,
21902 : /*57415*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21903 : /*57418*/ OPC_EmitInteger, MVT::i32, 0,
21904 : /*57421*/ OPC_EmitInteger, MVT::i32, 0,
21905 : /*57424*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LOG_IEEE_r600), 0,
21906 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21907 : // Src: (flog2:f32 R600_Reg32:f32:$src0) - Complexity = 3
21908 : // Dst: (LOG_IEEE_r600:f32 R600_Reg32:f32:$src0)
21909 : /*57444*/ /*Scope*/ 67, /*->57512*/
21910 : /*57445*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
21911 : /*57447*/ OPC_EmitInteger, MVT::i32, 1,
21912 : /*57450*/ OPC_EmitInteger, MVT::i32, 0,
21913 : /*57453*/ OPC_EmitInteger, MVT::i32, 0,
21914 : /*57456*/ OPC_EmitInteger, MVT::i32, 0,
21915 : /*57459*/ OPC_EmitInteger, MVT::i32, 0,
21916 : /*57462*/ OPC_EmitInteger, MVT::i32, 0,
21917 : /*57465*/ OPC_EmitInteger, MVT::i32, 0,
21918 : /*57468*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21919 : /*57480*/ OPC_EmitInteger, MVT::i32, 1,
21920 : /*57483*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21921 : /*57486*/ OPC_EmitInteger, MVT::i32, 0,
21922 : /*57489*/ OPC_EmitInteger, MVT::i32, 0,
21923 : /*57492*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LOG_IEEE_eg), 0,
21924 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21925 : // Src: (flog2:f32 R600_Reg32:f32:$src0) - Complexity = 3
21926 : // Dst: (LOG_IEEE_eg:f32 R600_Reg32:f32:$src0)
21927 : /*57512*/ /*Scope*/ 67, /*->57580*/
21928 : /*57513*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
21929 : /*57515*/ OPC_EmitInteger, MVT::i32, 1,
21930 : /*57518*/ OPC_EmitInteger, MVT::i32, 0,
21931 : /*57521*/ OPC_EmitInteger, MVT::i32, 0,
21932 : /*57524*/ OPC_EmitInteger, MVT::i32, 0,
21933 : /*57527*/ OPC_EmitInteger, MVT::i32, 0,
21934 : /*57530*/ OPC_EmitInteger, MVT::i32, 0,
21935 : /*57533*/ OPC_EmitInteger, MVT::i32, 0,
21936 : /*57536*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21937 : /*57548*/ OPC_EmitInteger, MVT::i32, 1,
21938 : /*57551*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21939 : /*57554*/ OPC_EmitInteger, MVT::i32, 0,
21940 : /*57557*/ OPC_EmitInteger, MVT::i32, 0,
21941 : /*57560*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::LOG_IEEE_cm), 0,
21942 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21943 : // Src: (flog2:f32 R600_Reg32:f32:$src0) - Complexity = 3
21944 : // Dst: (LOG_IEEE_cm:f32 R600_Reg32:f32:$src0)
21945 : /*57580*/ /*Scope*/ 14, /*->57595*/
21946 : /*57581*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
21947 : /*57584*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_LOG_F32_e64), 0,
21948 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
21949 : // Src: (flog2:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
21950 : // Dst: (V_LOG_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
21951 : /*57595*/ 0, /*End of Scope*/
21952 : /*57596*/ /*SwitchOpcode*/ 115|128,1/*243*/, TARGET_VAL(AMDGPUISD::RSQ_CLAMPED),// ->57843
21953 : /*57600*/ OPC_RecordChild0, // #0 = $src0
21954 : /*57601*/ OPC_SwitchType /*2 cases */, 93|128,1/*221*/, MVT::f32,// ->57826
21955 : /*57605*/ OPC_Scope, 67, /*->57674*/ // 4 children in Scope
21956 : /*57607*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
21957 : /*57609*/ OPC_EmitInteger, MVT::i32, 1,
21958 : /*57612*/ OPC_EmitInteger, MVT::i32, 0,
21959 : /*57615*/ OPC_EmitInteger, MVT::i32, 0,
21960 : /*57618*/ OPC_EmitInteger, MVT::i32, 0,
21961 : /*57621*/ OPC_EmitInteger, MVT::i32, 0,
21962 : /*57624*/ OPC_EmitInteger, MVT::i32, 0,
21963 : /*57627*/ OPC_EmitInteger, MVT::i32, 0,
21964 : /*57630*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21965 : /*57642*/ OPC_EmitInteger, MVT::i32, 1,
21966 : /*57645*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21967 : /*57648*/ OPC_EmitInteger, MVT::i32, 0,
21968 : /*57651*/ OPC_EmitInteger, MVT::i32, 0,
21969 : /*57654*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIPSQRT_CLAMPED_r600), 0,
21970 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21971 : // Src: (AMDGPUrsq_clamped:f32 R600_Reg32:f32:$src0) - Complexity = 3
21972 : // Dst: (RECIPSQRT_CLAMPED_r600:f32 R600_Reg32:f32:$src0)
21973 : /*57674*/ /*Scope*/ 67, /*->57742*/
21974 : /*57675*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
21975 : /*57677*/ OPC_EmitInteger, MVT::i32, 1,
21976 : /*57680*/ OPC_EmitInteger, MVT::i32, 0,
21977 : /*57683*/ OPC_EmitInteger, MVT::i32, 0,
21978 : /*57686*/ OPC_EmitInteger, MVT::i32, 0,
21979 : /*57689*/ OPC_EmitInteger, MVT::i32, 0,
21980 : /*57692*/ OPC_EmitInteger, MVT::i32, 0,
21981 : /*57695*/ OPC_EmitInteger, MVT::i32, 0,
21982 : /*57698*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
21983 : /*57710*/ OPC_EmitInteger, MVT::i32, 1,
21984 : /*57713*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
21985 : /*57716*/ OPC_EmitInteger, MVT::i32, 0,
21986 : /*57719*/ OPC_EmitInteger, MVT::i32, 0,
21987 : /*57722*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIPSQRT_CLAMPED_eg), 0,
21988 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
21989 : // Src: (AMDGPUrsq_clamped:f32 R600_Reg32:f32:$src0) - Complexity = 3
21990 : // Dst: (RECIPSQRT_CLAMPED_eg:f32 R600_Reg32:f32:$src0)
21991 : /*57742*/ /*Scope*/ 67, /*->57810*/
21992 : /*57743*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
21993 : /*57745*/ OPC_EmitInteger, MVT::i32, 1,
21994 : /*57748*/ OPC_EmitInteger, MVT::i32, 0,
21995 : /*57751*/ OPC_EmitInteger, MVT::i32, 0,
21996 : /*57754*/ OPC_EmitInteger, MVT::i32, 0,
21997 : /*57757*/ OPC_EmitInteger, MVT::i32, 0,
21998 : /*57760*/ OPC_EmitInteger, MVT::i32, 0,
21999 : /*57763*/ OPC_EmitInteger, MVT::i32, 0,
22000 : /*57766*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22001 : /*57778*/ OPC_EmitInteger, MVT::i32, 1,
22002 : /*57781*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22003 : /*57784*/ OPC_EmitInteger, MVT::i32, 0,
22004 : /*57787*/ OPC_EmitInteger, MVT::i32, 0,
22005 : /*57790*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIPSQRT_CLAMPED_cm), 0,
22006 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22007 : // Src: (AMDGPUrsq_clamped:f32 R600_Reg32:f32:$src0) - Complexity = 3
22008 : // Dst: (RECIPSQRT_CLAMPED_cm:f32 R600_Reg32:f32:$src0)
22009 : /*57810*/ /*Scope*/ 14, /*->57825*/
22010 : /*57811*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
22011 : /*57814*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_RSQ_CLAMP_F32_e64), 0,
22012 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
22013 : // Src: (AMDGPUrsq_clamped:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
22014 : // Dst: (V_RSQ_CLAMP_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
22015 : /*57825*/ 0, /*End of Scope*/
22016 : /*57826*/ /*SwitchType*/ 14, MVT::f64,// ->57842
22017 : /*57828*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
22018 : /*57831*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_RSQ_CLAMP_F64_e64), 0,
22019 : 1/*#VTs*/, MVT::f64, 4/*#Ops*/, 2, 1, 3, 4,
22020 : // Src: (AMDGPUrsq_clamped:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
22021 : // Dst: (V_RSQ_CLAMP_F64_e64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i1:i1:$clamp, i32:i32:$omod)
22022 : /*57842*/ 0, // EndSwitchType
22023 : /*57843*/ /*SwitchOpcode*/ 96|128,1/*224*/, TARGET_VAL(AMDGPUISD::RSQ_LEGACY),// ->58071
22024 : /*57847*/ OPC_RecordChild0, // #0 = $src0
22025 : /*57848*/ OPC_CheckType, MVT::f32,
22026 : /*57850*/ OPC_Scope, 67, /*->57919*/ // 4 children in Scope
22027 : /*57852*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
22028 : /*57854*/ OPC_EmitInteger, MVT::i32, 1,
22029 : /*57857*/ OPC_EmitInteger, MVT::i32, 0,
22030 : /*57860*/ OPC_EmitInteger, MVT::i32, 0,
22031 : /*57863*/ OPC_EmitInteger, MVT::i32, 0,
22032 : /*57866*/ OPC_EmitInteger, MVT::i32, 0,
22033 : /*57869*/ OPC_EmitInteger, MVT::i32, 0,
22034 : /*57872*/ OPC_EmitInteger, MVT::i32, 0,
22035 : /*57875*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22036 : /*57887*/ OPC_EmitInteger, MVT::i32, 1,
22037 : /*57890*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22038 : /*57893*/ OPC_EmitInteger, MVT::i32, 0,
22039 : /*57896*/ OPC_EmitInteger, MVT::i32, 0,
22040 : /*57899*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIPSQRT_IEEE_r600), 0,
22041 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22042 : // Src: (AMDGPUrsq_legacy:f32 R600_Reg32:f32:$src0) - Complexity = 3
22043 : // Dst: (RECIPSQRT_IEEE_r600:f32 R600_Reg32:f32:$src0)
22044 : /*57919*/ /*Scope*/ 67, /*->57987*/
22045 : /*57920*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
22046 : /*57922*/ OPC_EmitInteger, MVT::i32, 1,
22047 : /*57925*/ OPC_EmitInteger, MVT::i32, 0,
22048 : /*57928*/ OPC_EmitInteger, MVT::i32, 0,
22049 : /*57931*/ OPC_EmitInteger, MVT::i32, 0,
22050 : /*57934*/ OPC_EmitInteger, MVT::i32, 0,
22051 : /*57937*/ OPC_EmitInteger, MVT::i32, 0,
22052 : /*57940*/ OPC_EmitInteger, MVT::i32, 0,
22053 : /*57943*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22054 : /*57955*/ OPC_EmitInteger, MVT::i32, 1,
22055 : /*57958*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22056 : /*57961*/ OPC_EmitInteger, MVT::i32, 0,
22057 : /*57964*/ OPC_EmitInteger, MVT::i32, 0,
22058 : /*57967*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIPSQRT_IEEE_eg), 0,
22059 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22060 : // Src: (AMDGPUrsq_legacy:f32 R600_Reg32:f32:$src0) - Complexity = 3
22061 : // Dst: (RECIPSQRT_IEEE_eg:f32 R600_Reg32:f32:$src0)
22062 : /*57987*/ /*Scope*/ 67, /*->58055*/
22063 : /*57988*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
22064 : /*57990*/ OPC_EmitInteger, MVT::i32, 1,
22065 : /*57993*/ OPC_EmitInteger, MVT::i32, 0,
22066 : /*57996*/ OPC_EmitInteger, MVT::i32, 0,
22067 : /*57999*/ OPC_EmitInteger, MVT::i32, 0,
22068 : /*58002*/ OPC_EmitInteger, MVT::i32, 0,
22069 : /*58005*/ OPC_EmitInteger, MVT::i32, 0,
22070 : /*58008*/ OPC_EmitInteger, MVT::i32, 0,
22071 : /*58011*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22072 : /*58023*/ OPC_EmitInteger, MVT::i32, 1,
22073 : /*58026*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22074 : /*58029*/ OPC_EmitInteger, MVT::i32, 0,
22075 : /*58032*/ OPC_EmitInteger, MVT::i32, 0,
22076 : /*58035*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::RECIPSQRT_IEEE_cm), 0,
22077 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22078 : // Src: (AMDGPUrsq_legacy:f32 R600_Reg32:f32:$src0) - Complexity = 3
22079 : // Dst: (RECIPSQRT_IEEE_cm:f32 R600_Reg32:f32:$src0)
22080 : /*58055*/ /*Scope*/ 14, /*->58070*/
22081 : /*58056*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
22082 : /*58059*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_RSQ_LEGACY_F32_e64), 0,
22083 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
22084 : // Src: (AMDGPUrsq_legacy:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
22085 : // Dst: (V_RSQ_LEGACY_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
22086 : /*58070*/ 0, /*End of Scope*/
22087 : /*58071*/ /*SwitchOpcode*/ 107|128,1/*235*/, TARGET_VAL(ISD::SINT_TO_FP),// ->58310
22088 : /*58075*/ OPC_RecordChild0, // #0 = $src0
22089 : /*58076*/ OPC_Scope, 36|128,1/*164*/, /*->58243*/ // 2 children in Scope
22090 : /*58079*/ OPC_CheckChild0Type, MVT::i32,
22091 : /*58081*/ OPC_SwitchType /*2 cases */, 19|128,1/*147*/, MVT::f32,// ->58232
22092 : /*58085*/ OPC_Scope, 67, /*->58154*/ // 3 children in Scope
22093 : /*58087*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
22094 : /*58089*/ OPC_EmitInteger, MVT::i32, 1,
22095 : /*58092*/ OPC_EmitInteger, MVT::i32, 0,
22096 : /*58095*/ OPC_EmitInteger, MVT::i32, 0,
22097 : /*58098*/ OPC_EmitInteger, MVT::i32, 0,
22098 : /*58101*/ OPC_EmitInteger, MVT::i32, 0,
22099 : /*58104*/ OPC_EmitInteger, MVT::i32, 0,
22100 : /*58107*/ OPC_EmitInteger, MVT::i32, 0,
22101 : /*58110*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22102 : /*58122*/ OPC_EmitInteger, MVT::i32, 1,
22103 : /*58125*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22104 : /*58128*/ OPC_EmitInteger, MVT::i32, 0,
22105 : /*58131*/ OPC_EmitInteger, MVT::i32, 0,
22106 : /*58134*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::INT_TO_FLT_r600), 0,
22107 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22108 : // Src: (sint_to_fp:f32 R600_Reg32:i32:$src0) - Complexity = 3
22109 : // Dst: (INT_TO_FLT_r600:f32 R600_Reg32:i32:$src0)
22110 : /*58154*/ /*Scope*/ 67, /*->58222*/
22111 : /*58155*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
22112 : /*58157*/ OPC_EmitInteger, MVT::i32, 1,
22113 : /*58160*/ OPC_EmitInteger, MVT::i32, 0,
22114 : /*58163*/ OPC_EmitInteger, MVT::i32, 0,
22115 : /*58166*/ OPC_EmitInteger, MVT::i32, 0,
22116 : /*58169*/ OPC_EmitInteger, MVT::i32, 0,
22117 : /*58172*/ OPC_EmitInteger, MVT::i32, 0,
22118 : /*58175*/ OPC_EmitInteger, MVT::i32, 0,
22119 : /*58178*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22120 : /*58190*/ OPC_EmitInteger, MVT::i32, 1,
22121 : /*58193*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22122 : /*58196*/ OPC_EmitInteger, MVT::i32, 0,
22123 : /*58199*/ OPC_EmitInteger, MVT::i32, 0,
22124 : /*58202*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::INT_TO_FLT_eg), 0,
22125 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22126 : // Src: (sint_to_fp:f32 R600_Reg32:i32:$src0) - Complexity = 3
22127 : // Dst: (INT_TO_FLT_eg:f32 R600_Reg32:i32:$src0)
22128 : /*58222*/ /*Scope*/ 8, /*->58231*/
22129 : /*58223*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F32_I32_e64), 0,
22130 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 0,
22131 : // Src: (sint_to_fp:f32 i32:i32:$src0) - Complexity = -997
22132 : // Dst: (V_CVT_F32_I32_e64:f32 i32:i32:$src0)
22133 : /*58231*/ 0, /*End of Scope*/
22134 : /*58232*/ /*SwitchType*/ 8, MVT::f64,// ->58242
22135 : /*58234*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F64_I32_e64), 0,
22136 : 1/*#VTs*/, MVT::f64, 1/*#Ops*/, 0,
22137 : // Src: (sint_to_fp:f64 i32:i32:$src0) - Complexity = -997
22138 : // Dst: (V_CVT_F64_I32_e64:f64 i32:i32:$src0)
22139 : /*58242*/ 0, // EndSwitchType
22140 : /*58243*/ /*Scope*/ 65, /*->58309*/
22141 : /*58244*/ OPC_CheckChild0Type, MVT::i1,
22142 : /*58246*/ OPC_SwitchType /*2 cases */, 22, MVT::f32,// ->58271
22143 : /*58249*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
22144 : /*58251*/ OPC_EmitInteger, MVT::i32, 0,
22145 : /*58254*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,0|128,124|128,11/*3212836864*/,
22146 : /*58261*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
22147 : 1/*#VTs*/, MVT::f32, 3/*#Ops*/, 1, 2, 0,
22148 : // Src: (sint_to_fp:f32 i1:i1:$src) - Complexity = 3
22149 : // Dst: (V_CNDMASK_B32_e64:f32 0:i32, 3212836864:i32, ?:i1:$src)
22150 : /*58271*/ /*SwitchType*/ 35, MVT::f64,// ->58308
22151 : /*58273*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
22152 : /*58275*/ OPC_EmitInteger, MVT::i32, 0,
22153 : /*58278*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22154 : /*58290*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
22155 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 2, 0, // Results = #3
22156 : /*58300*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F64_I32_e32), 0,
22157 : 1/*#VTs*/, MVT::f64, 1/*#Ops*/, 3,
22158 : // Src: (sint_to_fp:f64 i1:i1:$src) - Complexity = 3
22159 : // Dst: (V_CVT_F64_I32_e32:f64 (V_CNDMASK_B32_e64:i32 0:i32, -1:i32, ?:i1:$src))
22160 : /*58308*/ 0, // EndSwitchType
22161 : /*58309*/ 0, /*End of Scope*/
22162 : /*58310*/ /*SwitchOpcode*/ 98|128,1/*226*/, TARGET_VAL(ISD::UINT_TO_FP),// ->58540
22163 : /*58314*/ OPC_RecordChild0, // #0 = $src0
22164 : /*58315*/ OPC_Scope, 36|128,1/*164*/, /*->58482*/ // 2 children in Scope
22165 : /*58318*/ OPC_CheckChild0Type, MVT::i32,
22166 : /*58320*/ OPC_SwitchType /*2 cases */, 19|128,1/*147*/, MVT::f32,// ->58471
22167 : /*58324*/ OPC_Scope, 67, /*->58393*/ // 3 children in Scope
22168 : /*58326*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
22169 : /*58328*/ OPC_EmitInteger, MVT::i32, 1,
22170 : /*58331*/ OPC_EmitInteger, MVT::i32, 0,
22171 : /*58334*/ OPC_EmitInteger, MVT::i32, 0,
22172 : /*58337*/ OPC_EmitInteger, MVT::i32, 0,
22173 : /*58340*/ OPC_EmitInteger, MVT::i32, 0,
22174 : /*58343*/ OPC_EmitInteger, MVT::i32, 0,
22175 : /*58346*/ OPC_EmitInteger, MVT::i32, 0,
22176 : /*58349*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22177 : /*58361*/ OPC_EmitInteger, MVT::i32, 1,
22178 : /*58364*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22179 : /*58367*/ OPC_EmitInteger, MVT::i32, 0,
22180 : /*58370*/ OPC_EmitInteger, MVT::i32, 0,
22181 : /*58373*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::UINT_TO_FLT_r600), 0,
22182 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22183 : // Src: (uint_to_fp:f32 R600_Reg32:i32:$src0) - Complexity = 3
22184 : // Dst: (UINT_TO_FLT_r600:f32 R600_Reg32:i32:$src0)
22185 : /*58393*/ /*Scope*/ 67, /*->58461*/
22186 : /*58394*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
22187 : /*58396*/ OPC_EmitInteger, MVT::i32, 1,
22188 : /*58399*/ OPC_EmitInteger, MVT::i32, 0,
22189 : /*58402*/ OPC_EmitInteger, MVT::i32, 0,
22190 : /*58405*/ OPC_EmitInteger, MVT::i32, 0,
22191 : /*58408*/ OPC_EmitInteger, MVT::i32, 0,
22192 : /*58411*/ OPC_EmitInteger, MVT::i32, 0,
22193 : /*58414*/ OPC_EmitInteger, MVT::i32, 0,
22194 : /*58417*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22195 : /*58429*/ OPC_EmitInteger, MVT::i32, 1,
22196 : /*58432*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22197 : /*58435*/ OPC_EmitInteger, MVT::i32, 0,
22198 : /*58438*/ OPC_EmitInteger, MVT::i32, 0,
22199 : /*58441*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::UINT_TO_FLT_eg), 0,
22200 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22201 : // Src: (uint_to_fp:f32 R600_Reg32:i32:$src0) - Complexity = 3
22202 : // Dst: (UINT_TO_FLT_eg:f32 R600_Reg32:i32:$src0)
22203 : /*58461*/ /*Scope*/ 8, /*->58470*/
22204 : /*58462*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F32_U32_e64), 0,
22205 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 0,
22206 : // Src: (uint_to_fp:f32 i32:i32:$src0) - Complexity = -997
22207 : // Dst: (V_CVT_F32_U32_e64:f32 i32:i32:$src0)
22208 : /*58470*/ 0, /*End of Scope*/
22209 : /*58471*/ /*SwitchType*/ 8, MVT::f64,// ->58481
22210 : /*58473*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F64_U32_e64), 0,
22211 : 1/*#VTs*/, MVT::f64, 1/*#Ops*/, 0,
22212 : // Src: (uint_to_fp:f64 i32:i32:$src0) - Complexity = -997
22213 : // Dst: (V_CVT_F64_U32_e64:f64 i32:i32:$src0)
22214 : /*58481*/ 0, // EndSwitchType
22215 : /*58482*/ /*Scope*/ 56, /*->58539*/
22216 : /*58483*/ OPC_CheckChild0Type, MVT::i1,
22217 : /*58485*/ OPC_SwitchType /*2 cases */, 22, MVT::f32,// ->58510
22218 : /*58488*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
22219 : /*58490*/ OPC_EmitInteger, MVT::i32, 0,
22220 : /*58493*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,0|128,124|128,3/*1065353216*/,
22221 : /*58500*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
22222 : 1/*#VTs*/, MVT::f32, 3/*#Ops*/, 1, 2, 0,
22223 : // Src: (uint_to_fp:f32 i1:i1:$src) - Complexity = 3
22224 : // Dst: (V_CNDMASK_B32_e64:f32 0:i32, 1065353216:i32, ?:i1:$src)
22225 : /*58510*/ /*SwitchType*/ 26, MVT::f64,// ->58538
22226 : /*58512*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
22227 : /*58514*/ OPC_EmitInteger, MVT::i32, 0,
22228 : /*58517*/ OPC_EmitInteger, MVT::i32, 1,
22229 : /*58520*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_CNDMASK_B32_e64), 0,
22230 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 1, 2, 0, // Results = #3
22231 : /*58530*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F64_U32_e32), 0,
22232 : 1/*#VTs*/, MVT::f64, 1/*#Ops*/, 3,
22233 : // Src: (uint_to_fp:f64 i1:i1:$src) - Complexity = 3
22234 : // Dst: (V_CVT_F64_U32_e32:f64 (V_CNDMASK_B32_e64:i32 0:i32, 1:i32, ?:i1:$src))
22235 : /*58538*/ 0, // EndSwitchType
22236 : /*58539*/ 0, /*End of Scope*/
22237 : /*58540*/ /*SwitchOpcode*/ 42|128,2/*298*/, TARGET_VAL(AMDGPUISD::SIN_HW),// ->58842
22238 : /*58544*/ OPC_RecordChild0, // #0 = $src0
22239 : /*58545*/ OPC_CheckType, MVT::f32,
22240 : /*58547*/ OPC_Scope, 20|128,2/*276*/, /*->58826*/ // 2 children in Scope
22241 : /*58550*/ OPC_CheckChild0Type, MVT::f32,
22242 : /*58552*/ OPC_Scope, 67, /*->58621*/ // 4 children in Scope
22243 : /*58554*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
22244 : /*58556*/ OPC_EmitInteger, MVT::i32, 1,
22245 : /*58559*/ OPC_EmitInteger, MVT::i32, 0,
22246 : /*58562*/ OPC_EmitInteger, MVT::i32, 0,
22247 : /*58565*/ OPC_EmitInteger, MVT::i32, 0,
22248 : /*58568*/ OPC_EmitInteger, MVT::i32, 0,
22249 : /*58571*/ OPC_EmitInteger, MVT::i32, 0,
22250 : /*58574*/ OPC_EmitInteger, MVT::i32, 0,
22251 : /*58577*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22252 : /*58589*/ OPC_EmitInteger, MVT::i32, 1,
22253 : /*58592*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22254 : /*58595*/ OPC_EmitInteger, MVT::i32, 0,
22255 : /*58598*/ OPC_EmitInteger, MVT::i32, 0,
22256 : /*58601*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SIN_r600), 0,
22257 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22258 : // Src: (SIN_HW:f32 f32:f32:$src0) - Complexity = 3
22259 : // Dst: (SIN_r600:f32 f32:f32:$src0)
22260 : /*58621*/ /*Scope*/ 67, /*->58689*/
22261 : /*58622*/ OPC_CheckPatternPredicate, 15, // (Subtarget->getGeneration() == AMDGPUSubtarget::R700)
22262 : /*58624*/ OPC_EmitInteger, MVT::i32, 1,
22263 : /*58627*/ OPC_EmitInteger, MVT::i32, 0,
22264 : /*58630*/ OPC_EmitInteger, MVT::i32, 0,
22265 : /*58633*/ OPC_EmitInteger, MVT::i32, 0,
22266 : /*58636*/ OPC_EmitInteger, MVT::i32, 0,
22267 : /*58639*/ OPC_EmitInteger, MVT::i32, 0,
22268 : /*58642*/ OPC_EmitInteger, MVT::i32, 0,
22269 : /*58645*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22270 : /*58657*/ OPC_EmitInteger, MVT::i32, 1,
22271 : /*58660*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22272 : /*58663*/ OPC_EmitInteger, MVT::i32, 0,
22273 : /*58666*/ OPC_EmitInteger, MVT::i32, 0,
22274 : /*58669*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SIN_r700), 0,
22275 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22276 : // Src: (SIN_HW:f32 f32:f32:$src0) - Complexity = 3
22277 : // Dst: (SIN_r700:f32 f32:f32:$src0)
22278 : /*58689*/ /*Scope*/ 67, /*->58757*/
22279 : /*58690*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
22280 : /*58692*/ OPC_EmitInteger, MVT::i32, 1,
22281 : /*58695*/ OPC_EmitInteger, MVT::i32, 0,
22282 : /*58698*/ OPC_EmitInteger, MVT::i32, 0,
22283 : /*58701*/ OPC_EmitInteger, MVT::i32, 0,
22284 : /*58704*/ OPC_EmitInteger, MVT::i32, 0,
22285 : /*58707*/ OPC_EmitInteger, MVT::i32, 0,
22286 : /*58710*/ OPC_EmitInteger, MVT::i32, 0,
22287 : /*58713*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22288 : /*58725*/ OPC_EmitInteger, MVT::i32, 1,
22289 : /*58728*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22290 : /*58731*/ OPC_EmitInteger, MVT::i32, 0,
22291 : /*58734*/ OPC_EmitInteger, MVT::i32, 0,
22292 : /*58737*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SIN_eg), 0,
22293 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22294 : // Src: (SIN_HW:f32 f32:f32:$src0) - Complexity = 3
22295 : // Dst: (SIN_eg:f32 f32:f32:$src0)
22296 : /*58757*/ /*Scope*/ 67, /*->58825*/
22297 : /*58758*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
22298 : /*58760*/ OPC_EmitInteger, MVT::i32, 1,
22299 : /*58763*/ OPC_EmitInteger, MVT::i32, 0,
22300 : /*58766*/ OPC_EmitInteger, MVT::i32, 0,
22301 : /*58769*/ OPC_EmitInteger, MVT::i32, 0,
22302 : /*58772*/ OPC_EmitInteger, MVT::i32, 0,
22303 : /*58775*/ OPC_EmitInteger, MVT::i32, 0,
22304 : /*58778*/ OPC_EmitInteger, MVT::i32, 0,
22305 : /*58781*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22306 : /*58793*/ OPC_EmitInteger, MVT::i32, 1,
22307 : /*58796*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22308 : /*58799*/ OPC_EmitInteger, MVT::i32, 0,
22309 : /*58802*/ OPC_EmitInteger, MVT::i32, 0,
22310 : /*58805*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SIN_cm), 0,
22311 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22312 : // Src: (SIN_HW:f32 f32:f32:$src0) - Complexity = 3
22313 : // Dst: (SIN_cm:f32 f32:f32:$src0)
22314 : /*58825*/ 0, /*End of Scope*/
22315 : /*58826*/ /*Scope*/ 14, /*->58841*/
22316 : /*58827*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
22317 : /*58830*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_SIN_F32_e64), 0,
22318 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
22319 : // Src: (AMDGPUsin:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
22320 : // Dst: (V_SIN_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
22321 : /*58841*/ 0, /*End of Scope*/
22322 : /*58842*/ /*SwitchOpcode*/ 42|128,2/*298*/, TARGET_VAL(AMDGPUISD::COS_HW),// ->59144
22323 : /*58846*/ OPC_RecordChild0, // #0 = $src0
22324 : /*58847*/ OPC_CheckType, MVT::f32,
22325 : /*58849*/ OPC_Scope, 20|128,2/*276*/, /*->59128*/ // 2 children in Scope
22326 : /*58852*/ OPC_CheckChild0Type, MVT::f32,
22327 : /*58854*/ OPC_Scope, 67, /*->58923*/ // 4 children in Scope
22328 : /*58856*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
22329 : /*58858*/ OPC_EmitInteger, MVT::i32, 1,
22330 : /*58861*/ OPC_EmitInteger, MVT::i32, 0,
22331 : /*58864*/ OPC_EmitInteger, MVT::i32, 0,
22332 : /*58867*/ OPC_EmitInteger, MVT::i32, 0,
22333 : /*58870*/ OPC_EmitInteger, MVT::i32, 0,
22334 : /*58873*/ OPC_EmitInteger, MVT::i32, 0,
22335 : /*58876*/ OPC_EmitInteger, MVT::i32, 0,
22336 : /*58879*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22337 : /*58891*/ OPC_EmitInteger, MVT::i32, 1,
22338 : /*58894*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22339 : /*58897*/ OPC_EmitInteger, MVT::i32, 0,
22340 : /*58900*/ OPC_EmitInteger, MVT::i32, 0,
22341 : /*58903*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::COS_r600), 0,
22342 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22343 : // Src: (COS_HW:f32 f32:f32:$src0) - Complexity = 3
22344 : // Dst: (COS_r600:f32 f32:f32:$src0)
22345 : /*58923*/ /*Scope*/ 67, /*->58991*/
22346 : /*58924*/ OPC_CheckPatternPredicate, 15, // (Subtarget->getGeneration() == AMDGPUSubtarget::R700)
22347 : /*58926*/ OPC_EmitInteger, MVT::i32, 1,
22348 : /*58929*/ OPC_EmitInteger, MVT::i32, 0,
22349 : /*58932*/ OPC_EmitInteger, MVT::i32, 0,
22350 : /*58935*/ OPC_EmitInteger, MVT::i32, 0,
22351 : /*58938*/ OPC_EmitInteger, MVT::i32, 0,
22352 : /*58941*/ OPC_EmitInteger, MVT::i32, 0,
22353 : /*58944*/ OPC_EmitInteger, MVT::i32, 0,
22354 : /*58947*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22355 : /*58959*/ OPC_EmitInteger, MVT::i32, 1,
22356 : /*58962*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22357 : /*58965*/ OPC_EmitInteger, MVT::i32, 0,
22358 : /*58968*/ OPC_EmitInteger, MVT::i32, 0,
22359 : /*58971*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::COS_r700), 0,
22360 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22361 : // Src: (COS_HW:f32 f32:f32:$src0) - Complexity = 3
22362 : // Dst: (COS_r700:f32 f32:f32:$src0)
22363 : /*58991*/ /*Scope*/ 67, /*->59059*/
22364 : /*58992*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
22365 : /*58994*/ OPC_EmitInteger, MVT::i32, 1,
22366 : /*58997*/ OPC_EmitInteger, MVT::i32, 0,
22367 : /*59000*/ OPC_EmitInteger, MVT::i32, 0,
22368 : /*59003*/ OPC_EmitInteger, MVT::i32, 0,
22369 : /*59006*/ OPC_EmitInteger, MVT::i32, 0,
22370 : /*59009*/ OPC_EmitInteger, MVT::i32, 0,
22371 : /*59012*/ OPC_EmitInteger, MVT::i32, 0,
22372 : /*59015*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22373 : /*59027*/ OPC_EmitInteger, MVT::i32, 1,
22374 : /*59030*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22375 : /*59033*/ OPC_EmitInteger, MVT::i32, 0,
22376 : /*59036*/ OPC_EmitInteger, MVT::i32, 0,
22377 : /*59039*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::COS_eg), 0,
22378 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22379 : // Src: (COS_HW:f32 f32:f32:$src0) - Complexity = 3
22380 : // Dst: (COS_eg:f32 f32:f32:$src0)
22381 : /*59059*/ /*Scope*/ 67, /*->59127*/
22382 : /*59060*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
22383 : /*59062*/ OPC_EmitInteger, MVT::i32, 1,
22384 : /*59065*/ OPC_EmitInteger, MVT::i32, 0,
22385 : /*59068*/ OPC_EmitInteger, MVT::i32, 0,
22386 : /*59071*/ OPC_EmitInteger, MVT::i32, 0,
22387 : /*59074*/ OPC_EmitInteger, MVT::i32, 0,
22388 : /*59077*/ OPC_EmitInteger, MVT::i32, 0,
22389 : /*59080*/ OPC_EmitInteger, MVT::i32, 0,
22390 : /*59083*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22391 : /*59095*/ OPC_EmitInteger, MVT::i32, 1,
22392 : /*59098*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22393 : /*59101*/ OPC_EmitInteger, MVT::i32, 0,
22394 : /*59104*/ OPC_EmitInteger, MVT::i32, 0,
22395 : /*59107*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::COS_cm), 0,
22396 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 1, 2, 3, 4, 0, 5, 6, 7, 8, 9, 10, 11, 12,
22397 : // Src: (COS_HW:f32 f32:f32:$src0) - Complexity = 3
22398 : // Dst: (COS_cm:f32 f32:f32:$src0)
22399 : /*59127*/ 0, /*End of Scope*/
22400 : /*59128*/ /*Scope*/ 14, /*->59143*/
22401 : /*59129*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
22402 : /*59132*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_COS_F32_e64), 0,
22403 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
22404 : // Src: (AMDGPUcos:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
22405 : // Dst: (V_COS_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
22406 : /*59143*/ 0, /*End of Scope*/
22407 : /*59144*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::FMA),// ->59308
22408 : /*59148*/ OPC_RecordChild0, // #0 = $src0
22409 : /*59149*/ OPC_RecordChild1, // #1 = $src1
22410 : /*59150*/ OPC_RecordChild2, // #2 = $src2
22411 : /*59151*/ OPC_SwitchType /*2 cases */, 127, MVT::f32,// ->59281
22412 : /*59154*/ OPC_Scope, 99, /*->59255*/ // 2 children in Scope
22413 : /*59156*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
22414 : /*59158*/ OPC_EmitInteger, MVT::i32, 0,
22415 : /*59161*/ OPC_EmitInteger, MVT::i32, 0,
22416 : /*59164*/ OPC_EmitInteger, MVT::i32, 0,
22417 : /*59167*/ OPC_EmitInteger, MVT::i32, 0,
22418 : /*59170*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22419 : /*59182*/ OPC_EmitInteger, MVT::i32, 0,
22420 : /*59185*/ OPC_EmitInteger, MVT::i32, 0,
22421 : /*59188*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22422 : /*59200*/ OPC_EmitInteger, MVT::i32, 0,
22423 : /*59203*/ OPC_EmitInteger, MVT::i32, 0,
22424 : /*59206*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22425 : /*59218*/ OPC_EmitInteger, MVT::i32, 1,
22426 : /*59221*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22427 : /*59224*/ OPC_EmitInteger, MVT::i32, 0,
22428 : /*59227*/ OPC_EmitInteger, MVT::i32, 0,
22429 : /*59230*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FMA_eg), 0,
22430 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 3, 4, 0, 5, 6, 7, 1, 8, 9, 10, 2, 11, 12, 13, 14, 15, 16, 17,
22431 : // Src: (fma:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2) - Complexity = 3
22432 : // Dst: (FMA_eg:f32 f32:f32:$src0, f32:f32:$src1, f32:f32:$src2)
22433 : /*59255*/ /*Scope*/ 24, /*->59280*/
22434 : /*59256*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #3 #4 #5 #6
22435 : /*59259*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #7 #8
22436 : /*59262*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // SelectVOP3Mods:$ #9 #10
22437 : /*59265*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_FMA_F32), 0,
22438 : 1/*#VTs*/, MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
22439 : // Src: (fma:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (VOP3Mods:f32 f32:f32:$src2, i32:i32:$src2_modifiers)) - Complexity = -964
22440 : // Dst: (V_FMA_F32:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i32:i32:$src2_modifiers, f32:f32:$src2, i1:i1:$clamp, i32:i32:$omod)
22441 : /*59280*/ 0, /*End of Scope*/
22442 : /*59281*/ /*SwitchType*/ 24, MVT::f64,// ->59307
22443 : /*59283*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #3 #4 #5 #6
22444 : /*59286*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #7 #8
22445 : /*59289*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // SelectVOP3Mods:$ #9 #10
22446 : /*59292*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_FMA_F64), 0,
22447 : 1/*#VTs*/, MVT::f64, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
22448 : // Src: (fma:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (VOP3Mods:f64 f64:f64:$src2, i32:i32:$src2_modifiers)) - Complexity = -964
22449 : // Dst: (V_FMA_F64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i32:i32:$src2_modifiers, f64:f64:$src2, i1:i1:$clamp, i32:i32:$omod)
22450 : /*59307*/ 0, // EndSwitchType
22451 : /*59308*/ /*SwitchOpcode*/ 31|128,4/*543*/, TARGET_VAL(ISD::FSQRT),// ->59855
22452 : /*59312*/ OPC_RecordChild0, // #0 = $src
22453 : /*59313*/ OPC_SwitchType /*2 cases */, 9|128,4/*521*/, MVT::f32,// ->59838
22454 : /*59317*/ OPC_Scope, 38|128,1/*166*/, /*->59486*/ // 4 children in Scope
22455 : /*59320*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
22456 : /*59322*/ OPC_EmitInteger, MVT::i32, 0,
22457 : /*59325*/ OPC_EmitInteger, MVT::i32, 0,
22458 : /*59328*/ OPC_EmitInteger, MVT::i32, 1,
22459 : /*59331*/ OPC_EmitInteger, MVT::i32, 0,
22460 : /*59334*/ OPC_EmitInteger, MVT::i32, 0,
22461 : /*59337*/ OPC_EmitInteger, MVT::i32, 0,
22462 : /*59340*/ OPC_EmitInteger, MVT::i32, 0,
22463 : /*59343*/ OPC_EmitInteger, MVT::i32, 0,
22464 : /*59346*/ OPC_EmitInteger, MVT::i32, 0,
22465 : /*59349*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22466 : /*59361*/ OPC_EmitInteger, MVT::i32, 1,
22467 : /*59364*/ OPC_EmitInteger, MVT::i32, 0,
22468 : /*59367*/ OPC_EmitInteger, MVT::i32, 0,
22469 : /*59370*/ OPC_EmitInteger, MVT::i32, 0,
22470 : /*59373*/ OPC_EmitInteger, MVT::i32, 0,
22471 : /*59376*/ OPC_EmitInteger, MVT::i32, 0,
22472 : /*59379*/ OPC_EmitInteger, MVT::i32, 0,
22473 : /*59382*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22474 : /*59394*/ OPC_EmitInteger, MVT::i32, 1,
22475 : /*59397*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22476 : /*59400*/ OPC_EmitInteger, MVT::i32, 0,
22477 : /*59403*/ OPC_EmitInteger, MVT::i32, 0,
22478 : /*59406*/ OPC_EmitNode, TARGET_VAL(AMDGPU::RECIPSQRT_CLAMPED_r600), 0,
22479 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 11, 12, 13, 14, 0, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
22480 : /*59426*/ OPC_EmitInteger, MVT::i32, 0,
22481 : /*59429*/ OPC_EmitInteger, MVT::i32, 0,
22482 : /*59432*/ OPC_EmitInteger, MVT::i32, 0,
22483 : /*59435*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22484 : /*59447*/ OPC_EmitInteger, MVT::i32, 1,
22485 : /*59450*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22486 : /*59453*/ OPC_EmitInteger, MVT::i32, 0,
22487 : /*59456*/ OPC_EmitInteger, MVT::i32, 0,
22488 : /*59459*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL), 0,
22489 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 1, 2, 3, 4, 5, 6, 0, 7, 8, 9, 10, 23, 24, 25, 26, 27, 28, 29, 30, 31,
22490 : // Src: (fsqrt:f32 f32:f32:$src) - Complexity = 3
22491 : // Dst: (MUL:f32 ?:f32:$src, (RECIPSQRT_CLAMPED_r600:i32 ?:f32:$src))
22492 : /*59486*/ /*Scope*/ 38|128,1/*166*/, /*->59654*/
22493 : /*59488*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
22494 : /*59490*/ OPC_EmitInteger, MVT::i32, 0,
22495 : /*59493*/ OPC_EmitInteger, MVT::i32, 0,
22496 : /*59496*/ OPC_EmitInteger, MVT::i32, 1,
22497 : /*59499*/ OPC_EmitInteger, MVT::i32, 0,
22498 : /*59502*/ OPC_EmitInteger, MVT::i32, 0,
22499 : /*59505*/ OPC_EmitInteger, MVT::i32, 0,
22500 : /*59508*/ OPC_EmitInteger, MVT::i32, 0,
22501 : /*59511*/ OPC_EmitInteger, MVT::i32, 0,
22502 : /*59514*/ OPC_EmitInteger, MVT::i32, 0,
22503 : /*59517*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22504 : /*59529*/ OPC_EmitInteger, MVT::i32, 1,
22505 : /*59532*/ OPC_EmitInteger, MVT::i32, 0,
22506 : /*59535*/ OPC_EmitInteger, MVT::i32, 0,
22507 : /*59538*/ OPC_EmitInteger, MVT::i32, 0,
22508 : /*59541*/ OPC_EmitInteger, MVT::i32, 0,
22509 : /*59544*/ OPC_EmitInteger, MVT::i32, 0,
22510 : /*59547*/ OPC_EmitInteger, MVT::i32, 0,
22511 : /*59550*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22512 : /*59562*/ OPC_EmitInteger, MVT::i32, 1,
22513 : /*59565*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22514 : /*59568*/ OPC_EmitInteger, MVT::i32, 0,
22515 : /*59571*/ OPC_EmitInteger, MVT::i32, 0,
22516 : /*59574*/ OPC_EmitNode, TARGET_VAL(AMDGPU::RECIPSQRT_CLAMPED_eg), 0,
22517 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 11, 12, 13, 14, 0, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
22518 : /*59594*/ OPC_EmitInteger, MVT::i32, 0,
22519 : /*59597*/ OPC_EmitInteger, MVT::i32, 0,
22520 : /*59600*/ OPC_EmitInteger, MVT::i32, 0,
22521 : /*59603*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22522 : /*59615*/ OPC_EmitInteger, MVT::i32, 1,
22523 : /*59618*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22524 : /*59621*/ OPC_EmitInteger, MVT::i32, 0,
22525 : /*59624*/ OPC_EmitInteger, MVT::i32, 0,
22526 : /*59627*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL), 0,
22527 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 1, 2, 3, 4, 5, 6, 0, 7, 8, 9, 10, 23, 24, 25, 26, 27, 28, 29, 30, 31,
22528 : // Src: (fsqrt:f32 f32:f32:$src) - Complexity = 3
22529 : // Dst: (MUL:f32 ?:f32:$src, (RECIPSQRT_CLAMPED_eg:i32 ?:f32:$src))
22530 : /*59654*/ /*Scope*/ 38|128,1/*166*/, /*->59822*/
22531 : /*59656*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
22532 : /*59658*/ OPC_EmitInteger, MVT::i32, 0,
22533 : /*59661*/ OPC_EmitInteger, MVT::i32, 0,
22534 : /*59664*/ OPC_EmitInteger, MVT::i32, 1,
22535 : /*59667*/ OPC_EmitInteger, MVT::i32, 0,
22536 : /*59670*/ OPC_EmitInteger, MVT::i32, 0,
22537 : /*59673*/ OPC_EmitInteger, MVT::i32, 0,
22538 : /*59676*/ OPC_EmitInteger, MVT::i32, 0,
22539 : /*59679*/ OPC_EmitInteger, MVT::i32, 0,
22540 : /*59682*/ OPC_EmitInteger, MVT::i32, 0,
22541 : /*59685*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22542 : /*59697*/ OPC_EmitInteger, MVT::i32, 1,
22543 : /*59700*/ OPC_EmitInteger, MVT::i32, 0,
22544 : /*59703*/ OPC_EmitInteger, MVT::i32, 0,
22545 : /*59706*/ OPC_EmitInteger, MVT::i32, 0,
22546 : /*59709*/ OPC_EmitInteger, MVT::i32, 0,
22547 : /*59712*/ OPC_EmitInteger, MVT::i32, 0,
22548 : /*59715*/ OPC_EmitInteger, MVT::i32, 0,
22549 : /*59718*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22550 : /*59730*/ OPC_EmitInteger, MVT::i32, 1,
22551 : /*59733*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22552 : /*59736*/ OPC_EmitInteger, MVT::i32, 0,
22553 : /*59739*/ OPC_EmitInteger, MVT::i32, 0,
22554 : /*59742*/ OPC_EmitNode, TARGET_VAL(AMDGPU::RECIPSQRT_CLAMPED_cm), 0,
22555 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 11, 12, 13, 14, 0, 15, 16, 17, 18, 19, 20, 21, 22, // Results = #23
22556 : /*59762*/ OPC_EmitInteger, MVT::i32, 0,
22557 : /*59765*/ OPC_EmitInteger, MVT::i32, 0,
22558 : /*59768*/ OPC_EmitInteger, MVT::i32, 0,
22559 : /*59771*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22560 : /*59783*/ OPC_EmitInteger, MVT::i32, 1,
22561 : /*59786*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22562 : /*59789*/ OPC_EmitInteger, MVT::i32, 0,
22563 : /*59792*/ OPC_EmitInteger, MVT::i32, 0,
22564 : /*59795*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::MUL), 0,
22565 : 1/*#VTs*/, MVT::f32, 20/*#Ops*/, 1, 2, 3, 4, 5, 6, 0, 7, 8, 9, 10, 23, 24, 25, 26, 27, 28, 29, 30, 31,
22566 : // Src: (fsqrt:f32 f32:f32:$src) - Complexity = 3
22567 : // Dst: (MUL:f32 R600_Reg32:f32:$src, (RECIPSQRT_CLAMPED_cm:i32 ?:f32:$src))
22568 : /*59822*/ /*Scope*/ 14, /*->59837*/
22569 : /*59823*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
22570 : /*59826*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_SQRT_F32_e64), 0,
22571 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
22572 : // Src: (fsqrt:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
22573 : // Dst: (V_SQRT_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
22574 : /*59837*/ 0, /*End of Scope*/
22575 : /*59838*/ /*SwitchType*/ 14, MVT::f64,// ->59854
22576 : /*59840*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
22577 : /*59843*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_SQRT_F64_e64), 0,
22578 : 1/*#VTs*/, MVT::f64, 4/*#Ops*/, 2, 1, 3, 4,
22579 : // Src: (fsqrt:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
22580 : // Dst: (V_SQRT_F64_e64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i1:i1:$clamp, i32:i32:$omod)
22581 : /*59854*/ 0, // EndSwitchType
22582 : /*59855*/ /*SwitchOpcode*/ 118, TARGET_VAL(ISD::FABS),// ->59976
22583 : /*59858*/ OPC_RecordChild0, // #0 = $src
22584 : /*59859*/ OPC_SwitchType /*2 cases */, 40, MVT::f32,// ->59902
22585 : /*59862*/ OPC_Scope, 26, /*->59890*/ // 2 children in Scope
22586 : /*59864*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
22587 : /*59866*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,7/*2147483647*/,
22588 : /*59873*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
22589 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 1, // Results = #2
22590 : /*59881*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_AND_B32_e32), 0,
22591 : 1/*#VTs*/, MVT::f32, 2/*#Ops*/, 0, 2,
22592 : // Src: (fabs:f32 f32:f32:$src) - Complexity = 3
22593 : // Dst: (V_AND_B32_e32:f32 ?:f32:$src, (V_MOV_B32_e32:i32 2147483647:i32))
22594 : /*59890*/ /*Scope*/ 10, /*->59901*/
22595 : /*59891*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
22596 : /*59893*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::FABS_R600), 0,
22597 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 0,
22598 : // Src: (fabs:f32 f32:f32:$src0) - Complexity = 3
22599 : // Dst: (FABS_R600:f32 f32:f32:$src0)
22600 : /*59901*/ 0, /*End of Scope*/
22601 : /*59902*/ /*SwitchType*/ 71, MVT::f64,// ->59975
22602 : /*59904*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
22603 : /*59906*/ OPC_EmitInteger, MVT::i32, AMDGPU::VReg_64RegClassID,
22604 : /*59909*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
22605 : /*59912*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
22606 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
22607 : /*59921*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
22608 : /*59924*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
22609 : /*59927*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
22610 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
22611 : /*59936*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,7/*2147483647*/,
22612 : /*59943*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MOV_B32_e32), 0,
22613 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 7, // Results = #8
22614 : /*59951*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_AND_B32_e32), 0,
22615 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 6, 8, // Results = #9
22616 : /*59960*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
22617 : /*59963*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
22618 : 1/*#VTs*/, MVT::f64, 5/*#Ops*/, 1, 3, 4, 9, 10,
22619 : // Src: (fabs:f64 f64:f64:$src) - Complexity = 3
22620 : // Dst: (REG_SEQUENCE:f64 VReg_64:i32, (EXTRACT_SUBREG:i32 f64:f64:$src, sub0:i32), sub0:i32, (V_AND_B32_e32:i32 (EXTRACT_SUBREG:i32 f64:f64:$src, sub1:i32), (V_MOV_B32_e32:i32 2147483647:i32)), sub1:i32)
22621 : /*59975*/ 0, // EndSwitchType
22622 : /*59976*/ /*SwitchOpcode*/ 35|128,3/*419*/, TARGET_VAL(ISD::FCOPYSIGN),// ->60399
22623 : /*59980*/ OPC_RecordChild0, // #0 = $src0
22624 : /*59981*/ OPC_RecordChild1, // #1 = $src1
22625 : /*59982*/ OPC_SwitchType /*2 cases */, 19|128,1/*147*/, MVT::f32,// ->60133
22626 : /*59986*/ OPC_CheckChild1Type, MVT::f32,
22627 : /*59988*/ OPC_Scope, 27, /*->60017*/ // 2 children in Scope
22628 : /*59990*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
22629 : /*59992*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,7/*2147483647*/,
22630 : /*59999*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
22631 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 2, // Results = #3
22632 : /*60007*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
22633 : 1/*#VTs*/, MVT::f32, 3/*#Ops*/, 3, 0, 1,
22634 : // Src: (fcopysign:f32 f32:f32:$src0, f32:f32:$src1) - Complexity = 3
22635 : // Dst: (V_BFI_B32:f32 (S_MOV_B32:i32 2147483647:i32), ?:f32:$src0, ?:f32:$src1)
22636 : /*60017*/ /*Scope*/ 114, /*->60132*/
22637 : /*60018*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
22638 : /*60020*/ OPC_EmitInteger, MVT::i32, 0,
22639 : /*60023*/ OPC_EmitInteger, MVT::i32, 0,
22640 : /*60026*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,7/*2147483647*/,
22641 : /*60033*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MOV_IMM_I32), 0,
22642 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 4, // Results = #5
22643 : /*60041*/ OPC_EmitInteger, MVT::i32, 0,
22644 : /*60044*/ OPC_EmitInteger, MVT::i32, 0,
22645 : /*60047*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22646 : /*60059*/ OPC_EmitInteger, MVT::i32, 0,
22647 : /*60062*/ OPC_EmitInteger, MVT::i32, 0,
22648 : /*60065*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22649 : /*60077*/ OPC_EmitInteger, MVT::i32, 0,
22650 : /*60080*/ OPC_EmitInteger, MVT::i32, 0,
22651 : /*60083*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22652 : /*60095*/ OPC_EmitInteger, MVT::i32, 1,
22653 : /*60098*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22654 : /*60101*/ OPC_EmitInteger, MVT::i32, 0,
22655 : /*60104*/ OPC_EmitInteger, MVT::i32, 0,
22656 : /*60107*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
22657 : 1/*#VTs*/, MVT::f32, 18/*#Ops*/, 2, 3, 5, 6, 7, 8, 0, 9, 10, 11, 1, 12, 13, 14, 15, 16, 17, 18,
22658 : // Src: (fcopysign:f32 f32:f32:$src0, f32:f32:$src1) - Complexity = 3
22659 : // Dst: (BFI_INT_eg:f32 (MOV_IMM_I32:i32 2147483647:i32), ?:f32:$src0, ?:f32:$src1)
22660 : /*60132*/ 0, /*End of Scope*/
22661 : /*60133*/ /*SwitchType*/ 6|128,2/*262*/, MVT::f64,// ->60398
22662 : /*60136*/ OPC_CheckChild1Type, MVT::f64,
22663 : /*60138*/ OPC_Scope, 84, /*->60224*/ // 2 children in Scope
22664 : /*60140*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
22665 : /*60142*/ OPC_EmitInteger, MVT::i32, AMDGPU::SReg_64RegClassID,
22666 : /*60145*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
22667 : /*60148*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
22668 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 3, // Results = #4
22669 : /*60157*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
22670 : /*60160*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,7/*2147483647*/,
22671 : /*60167*/ OPC_EmitNode, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
22672 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 6, // Results = #7
22673 : /*60175*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
22674 : /*60178*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
22675 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 8, // Results = #9
22676 : /*60187*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
22677 : /*60190*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
22678 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 10, // Results = #11
22679 : /*60199*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_BFI_B32), 0,
22680 : 1/*#VTs*/, MVT::i32, 3/*#Ops*/, 7, 9, 11, // Results = #12
22681 : /*60209*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
22682 : /*60212*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
22683 : 1/*#VTs*/, MVT::f64, 5/*#Ops*/, 2, 4, 5, 12, 13,
22684 : // Src: (fcopysign:f64 f64:f64:$src0, f64:f64:$src1) - Complexity = 3
22685 : // Dst: (REG_SEQUENCE:f64 SReg_64:i32, (EXTRACT_SUBREG:i32 ?:f64:$src0, sub0:i32), sub0:i32, (V_BFI_B32:i32 (S_MOV_B32:i32 2147483647:i32), (EXTRACT_SUBREG:i32 ?:f64:$src0, sub1:i32), (EXTRACT_SUBREG:i32 ?:f64:$src1, sub1:i32)), sub1:i32)
22686 : /*60224*/ /*Scope*/ 43|128,1/*171*/, /*->60397*/
22687 : /*60226*/ OPC_CheckPatternPredicate, 2, // (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS)
22688 : /*60228*/ OPC_EmitInteger, MVT::i32, AMDGPU::R600_Reg64RegClassID,
22689 : /*60231*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
22690 : /*60234*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
22691 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 3, // Results = #4
22692 : /*60243*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
22693 : /*60246*/ OPC_EmitInteger, MVT::i32, 0,
22694 : /*60249*/ OPC_EmitInteger, MVT::i32, 0,
22695 : /*60252*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,7/*2147483647*/,
22696 : /*60259*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MOV_IMM_I32), 0,
22697 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 8, // Results = #9
22698 : /*60267*/ OPC_EmitInteger, MVT::i32, 0,
22699 : /*60270*/ OPC_EmitInteger, MVT::i32, 0,
22700 : /*60273*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22701 : /*60285*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
22702 : /*60288*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
22703 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 13, // Results = #14
22704 : /*60297*/ OPC_EmitInteger, MVT::i32, 0,
22705 : /*60300*/ OPC_EmitInteger, MVT::i32, 0,
22706 : /*60303*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22707 : /*60315*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
22708 : /*60318*/ OPC_EmitNode, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
22709 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 18, // Results = #19
22710 : /*60327*/ OPC_EmitInteger, MVT::i32, 0,
22711 : /*60330*/ OPC_EmitInteger, MVT::i32, 0,
22712 : /*60333*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22713 : /*60345*/ OPC_EmitInteger, MVT::i32, 1,
22714 : /*60348*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22715 : /*60351*/ OPC_EmitInteger, MVT::i32, 0,
22716 : /*60354*/ OPC_EmitInteger, MVT::i32, 0,
22717 : /*60357*/ OPC_EmitNode, TARGET_VAL(AMDGPU::BFI_INT_eg), 0,
22718 : 1/*#VTs*/, MVT::i32, 18/*#Ops*/, 6, 7, 9, 10, 11, 12, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, // Results = #27
22719 : /*60382*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
22720 : /*60385*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::REG_SEQUENCE), 0,
22721 : 1/*#VTs*/, MVT::f64, 5/*#Ops*/, 2, 4, 5, 27, 28,
22722 : // Src: (fcopysign:f64 f64:f64:$src0, f64:f64:$src1) - Complexity = 3
22723 : // Dst: (REG_SEQUENCE:f64 R600_Reg64:i32, (EXTRACT_SUBREG:i32 ?:f64:$src0, sub0:i32), sub0:i32, (BFI_INT_eg:i32 (MOV_IMM_I32:i32 2147483647:i32), (EXTRACT_SUBREG:i32 ?:f64:$src0, sub1:i32), (EXTRACT_SUBREG:i32 ?:f64:$src1, sub1:i32)), sub1:i32)
22724 : /*60397*/ 0, /*End of Scope*/
22725 : /*60398*/ 0, // EndSwitchType
22726 : /*60399*/ /*SwitchOpcode*/ 93|128,5/*733*/, TARGET_VAL(ISD::FPOW),// ->61136
22727 : /*60403*/ OPC_RecordChild0, // #0 = $src0
22728 : /*60404*/ OPC_RecordChild1, // #1 = $src1
22729 : /*60405*/ OPC_CheckType, MVT::f32,
22730 : /*60407*/ OPC_Scope, 103|128,1/*231*/, /*->60641*/ // 4 children in Scope
22731 : /*60410*/ OPC_CheckPatternPredicate, 8, // (Subtarget->getGeneration() <= AMDGPUSubtarget::R700)
22732 : /*60412*/ OPC_EmitInteger, MVT::i32, 1,
22733 : /*60415*/ OPC_EmitInteger, MVT::i32, 0,
22734 : /*60418*/ OPC_EmitInteger, MVT::i32, 0,
22735 : /*60421*/ OPC_EmitInteger, MVT::i32, 0,
22736 : /*60424*/ OPC_EmitInteger, MVT::i32, 0,
22737 : /*60427*/ OPC_EmitInteger, MVT::i32, 0,
22738 : /*60430*/ OPC_EmitInteger, MVT::i32, 1,
22739 : /*60433*/ OPC_EmitInteger, MVT::i32, 0,
22740 : /*60436*/ OPC_EmitInteger, MVT::i32, 0,
22741 : /*60439*/ OPC_EmitInteger, MVT::i32, 0,
22742 : /*60442*/ OPC_EmitInteger, MVT::i32, 0,
22743 : /*60445*/ OPC_EmitInteger, MVT::i32, 0,
22744 : /*60448*/ OPC_EmitInteger, MVT::i32, 0,
22745 : /*60451*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22746 : /*60463*/ OPC_EmitInteger, MVT::i32, 1,
22747 : /*60466*/ OPC_EmitInteger, MVT::i32, 0,
22748 : /*60469*/ OPC_EmitInteger, MVT::i32, 0,
22749 : /*60472*/ OPC_EmitInteger, MVT::i32, 0,
22750 : /*60475*/ OPC_EmitInteger, MVT::i32, 0,
22751 : /*60478*/ OPC_EmitInteger, MVT::i32, 0,
22752 : /*60481*/ OPC_EmitInteger, MVT::i32, 0,
22753 : /*60484*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22754 : /*60496*/ OPC_EmitInteger, MVT::i32, 1,
22755 : /*60499*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22756 : /*60502*/ OPC_EmitInteger, MVT::i32, 0,
22757 : /*60505*/ OPC_EmitInteger, MVT::i32, 0,
22758 : /*60508*/ OPC_EmitNode, TARGET_VAL(AMDGPU::LOG_IEEE_r600), 0,
22759 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 16, 17, 18, 19, 0, 20, 21, 22, 23, 24, 25, 26, 27, // Results = #28
22760 : /*60528*/ OPC_EmitInteger, MVT::i32, 0,
22761 : /*60531*/ OPC_EmitInteger, MVT::i32, 0,
22762 : /*60534*/ OPC_EmitInteger, MVT::i32, 0,
22763 : /*60537*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22764 : /*60549*/ OPC_EmitInteger, MVT::i32, 1,
22765 : /*60552*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22766 : /*60555*/ OPC_EmitInteger, MVT::i32, 0,
22767 : /*60558*/ OPC_EmitInteger, MVT::i32, 0,
22768 : /*60561*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MUL), 0,
22769 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 6, 7, 8, 9, 10, 11, 1, 12, 13, 14, 15, 28, 29, 30, 31, 32, 33, 34, 35, 36, // Results = #37
22770 : /*60588*/ OPC_EmitInteger, MVT::i32, 0,
22771 : /*60591*/ OPC_EmitInteger, MVT::i32, 0,
22772 : /*60594*/ OPC_EmitInteger, MVT::i32, 0,
22773 : /*60597*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22774 : /*60609*/ OPC_EmitInteger, MVT::i32, 1,
22775 : /*60612*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22776 : /*60615*/ OPC_EmitInteger, MVT::i32, 0,
22777 : /*60618*/ OPC_EmitInteger, MVT::i32, 0,
22778 : /*60621*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EXP_IEEE_r600), 0,
22779 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 2, 3, 4, 5, 37, 38, 39, 40, 41, 42, 43, 44, 45,
22780 : // Src: (fpow:f32 f32:f32:$src0, f32:f32:$src1) - Complexity = 3
22781 : // Dst: (EXP_IEEE_r600:f32 (MUL:i32 f32:f32:$src1, (LOG_IEEE_r600:i32 f32:f32:$src0)))
22782 : /*60641*/ /*Scope*/ 103|128,1/*231*/, /*->60874*/
22783 : /*60643*/ OPC_CheckPatternPredicate, 4, // (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA())
22784 : /*60645*/ OPC_EmitInteger, MVT::i32, 1,
22785 : /*60648*/ OPC_EmitInteger, MVT::i32, 0,
22786 : /*60651*/ OPC_EmitInteger, MVT::i32, 0,
22787 : /*60654*/ OPC_EmitInteger, MVT::i32, 0,
22788 : /*60657*/ OPC_EmitInteger, MVT::i32, 0,
22789 : /*60660*/ OPC_EmitInteger, MVT::i32, 0,
22790 : /*60663*/ OPC_EmitInteger, MVT::i32, 1,
22791 : /*60666*/ OPC_EmitInteger, MVT::i32, 0,
22792 : /*60669*/ OPC_EmitInteger, MVT::i32, 0,
22793 : /*60672*/ OPC_EmitInteger, MVT::i32, 0,
22794 : /*60675*/ OPC_EmitInteger, MVT::i32, 0,
22795 : /*60678*/ OPC_EmitInteger, MVT::i32, 0,
22796 : /*60681*/ OPC_EmitInteger, MVT::i32, 0,
22797 : /*60684*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22798 : /*60696*/ OPC_EmitInteger, MVT::i32, 1,
22799 : /*60699*/ OPC_EmitInteger, MVT::i32, 0,
22800 : /*60702*/ OPC_EmitInteger, MVT::i32, 0,
22801 : /*60705*/ OPC_EmitInteger, MVT::i32, 0,
22802 : /*60708*/ OPC_EmitInteger, MVT::i32, 0,
22803 : /*60711*/ OPC_EmitInteger, MVT::i32, 0,
22804 : /*60714*/ OPC_EmitInteger, MVT::i32, 0,
22805 : /*60717*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22806 : /*60729*/ OPC_EmitInteger, MVT::i32, 1,
22807 : /*60732*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22808 : /*60735*/ OPC_EmitInteger, MVT::i32, 0,
22809 : /*60738*/ OPC_EmitInteger, MVT::i32, 0,
22810 : /*60741*/ OPC_EmitNode, TARGET_VAL(AMDGPU::LOG_IEEE_eg), 0,
22811 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 16, 17, 18, 19, 0, 20, 21, 22, 23, 24, 25, 26, 27, // Results = #28
22812 : /*60761*/ OPC_EmitInteger, MVT::i32, 0,
22813 : /*60764*/ OPC_EmitInteger, MVT::i32, 0,
22814 : /*60767*/ OPC_EmitInteger, MVT::i32, 0,
22815 : /*60770*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22816 : /*60782*/ OPC_EmitInteger, MVT::i32, 1,
22817 : /*60785*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22818 : /*60788*/ OPC_EmitInteger, MVT::i32, 0,
22819 : /*60791*/ OPC_EmitInteger, MVT::i32, 0,
22820 : /*60794*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MUL), 0,
22821 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 6, 7, 8, 9, 10, 11, 1, 12, 13, 14, 15, 28, 29, 30, 31, 32, 33, 34, 35, 36, // Results = #37
22822 : /*60821*/ OPC_EmitInteger, MVT::i32, 0,
22823 : /*60824*/ OPC_EmitInteger, MVT::i32, 0,
22824 : /*60827*/ OPC_EmitInteger, MVT::i32, 0,
22825 : /*60830*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22826 : /*60842*/ OPC_EmitInteger, MVT::i32, 1,
22827 : /*60845*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22828 : /*60848*/ OPC_EmitInteger, MVT::i32, 0,
22829 : /*60851*/ OPC_EmitInteger, MVT::i32, 0,
22830 : /*60854*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EXP_IEEE_eg), 0,
22831 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 2, 3, 4, 5, 37, 38, 39, 40, 41, 42, 43, 44, 45,
22832 : // Src: (fpow:f32 f32:f32:$src0, f32:f32:$src1) - Complexity = 3
22833 : // Dst: (EXP_IEEE_eg:f32 (MUL:i32 f32:f32:$src1, (LOG_IEEE_eg:i32 f32:f32:$src0)))
22834 : /*60874*/ /*Scope*/ 103|128,1/*231*/, /*->61107*/
22835 : /*60876*/ OPC_CheckPatternPredicate, 3, // (Subtarget->hasCaymanISA())
22836 : /*60878*/ OPC_EmitInteger, MVT::i32, 1,
22837 : /*60881*/ OPC_EmitInteger, MVT::i32, 0,
22838 : /*60884*/ OPC_EmitInteger, MVT::i32, 0,
22839 : /*60887*/ OPC_EmitInteger, MVT::i32, 0,
22840 : /*60890*/ OPC_EmitInteger, MVT::i32, 0,
22841 : /*60893*/ OPC_EmitInteger, MVT::i32, 0,
22842 : /*60896*/ OPC_EmitInteger, MVT::i32, 1,
22843 : /*60899*/ OPC_EmitInteger, MVT::i32, 0,
22844 : /*60902*/ OPC_EmitInteger, MVT::i32, 0,
22845 : /*60905*/ OPC_EmitInteger, MVT::i32, 0,
22846 : /*60908*/ OPC_EmitInteger, MVT::i32, 0,
22847 : /*60911*/ OPC_EmitInteger, MVT::i32, 0,
22848 : /*60914*/ OPC_EmitInteger, MVT::i32, 0,
22849 : /*60917*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22850 : /*60929*/ OPC_EmitInteger, MVT::i32, 1,
22851 : /*60932*/ OPC_EmitInteger, MVT::i32, 0,
22852 : /*60935*/ OPC_EmitInteger, MVT::i32, 0,
22853 : /*60938*/ OPC_EmitInteger, MVT::i32, 0,
22854 : /*60941*/ OPC_EmitInteger, MVT::i32, 0,
22855 : /*60944*/ OPC_EmitInteger, MVT::i32, 0,
22856 : /*60947*/ OPC_EmitInteger, MVT::i32, 0,
22857 : /*60950*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22858 : /*60962*/ OPC_EmitInteger, MVT::i32, 1,
22859 : /*60965*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22860 : /*60968*/ OPC_EmitInteger, MVT::i32, 0,
22861 : /*60971*/ OPC_EmitInteger, MVT::i32, 0,
22862 : /*60974*/ OPC_EmitNode, TARGET_VAL(AMDGPU::LOG_IEEE_cm), 0,
22863 : 1/*#VTs*/, MVT::i32, 13/*#Ops*/, 16, 17, 18, 19, 0, 20, 21, 22, 23, 24, 25, 26, 27, // Results = #28
22864 : /*60994*/ OPC_EmitInteger, MVT::i32, 0,
22865 : /*60997*/ OPC_EmitInteger, MVT::i32, 0,
22866 : /*61000*/ OPC_EmitInteger, MVT::i32, 0,
22867 : /*61003*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22868 : /*61015*/ OPC_EmitInteger, MVT::i32, 1,
22869 : /*61018*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22870 : /*61021*/ OPC_EmitInteger, MVT::i32, 0,
22871 : /*61024*/ OPC_EmitInteger, MVT::i32, 0,
22872 : /*61027*/ OPC_EmitNode, TARGET_VAL(AMDGPU::MUL), 0,
22873 : 1/*#VTs*/, MVT::i32, 20/*#Ops*/, 6, 7, 8, 9, 10, 11, 1, 12, 13, 14, 15, 28, 29, 30, 31, 32, 33, 34, 35, 36, // Results = #37
22874 : /*61054*/ OPC_EmitInteger, MVT::i32, 0,
22875 : /*61057*/ OPC_EmitInteger, MVT::i32, 0,
22876 : /*61060*/ OPC_EmitInteger, MVT::i32, 0,
22877 : /*61063*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
22878 : /*61075*/ OPC_EmitInteger, MVT::i32, 1,
22879 : /*61078*/ OPC_EmitRegister, MVT::i32, AMDGPU::PRED_SEL_OFF,
22880 : /*61081*/ OPC_EmitInteger, MVT::i32, 0,
22881 : /*61084*/ OPC_EmitInteger, MVT::i32, 0,
22882 : /*61087*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::EXP_IEEE_cm), 0,
22883 : 1/*#VTs*/, MVT::f32, 13/*#Ops*/, 2, 3, 4, 5, 37, 38, 39, 40, 41, 42, 43, 44, 45,
22884 : // Src: (fpow:f32 f32:f32:$src0, f32:f32:$src1) - Complexity = 3
22885 : // Dst: (EXP_IEEE_cm:f32 (MUL:i32 f32:f32:$src1, (LOG_IEEE_cm:i32 f32:f32:$src0)))
22886 : /*61107*/ /*Scope*/ 27, /*->61135*/
22887 : /*61108*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
22888 : /*61110*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_LOG_F32_e32), 0,
22889 : 1/*#VTs*/, MVT::i32, 1/*#Ops*/, 0, // Results = #2
22890 : /*61118*/ OPC_EmitNode, TARGET_VAL(AMDGPU::V_MUL_LEGACY_F32_e32), 0,
22891 : 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
22892 : /*61127*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_EXP_F32_e32), 0,
22893 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 3,
22894 : // Src: (fpow:f32 f32:f32:$src0, f32:f32:$src1) - Complexity = 3
22895 : // Dst: (V_EXP_F32_e32:f32 (V_MUL_LEGACY_F32_e32:i32 f32:f32:$src1, (V_LOG_F32_e32:i32 f32:f32:$src0)))
22896 : /*61135*/ 0, /*End of Scope*/
22897 : /*61136*/ /*SwitchOpcode*/ 29, TARGET_VAL(AMDGPUISD::FMIN3),// ->61168
22898 : /*61139*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
22899 : /*61140*/ OPC_RecordChild1, // #1 = $VOP3Mods:src1:src1_modifiers
22900 : /*61141*/ OPC_RecordChild2, // #2 = $VOP3Mods:src2:src2_modifiers
22901 : /*61142*/ OPC_CheckType, MVT::f32,
22902 : /*61144*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #3 #4 #5 #6
22903 : /*61147*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #7 #8
22904 : /*61150*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // SelectVOP3Mods:$ #9 #10
22905 : /*61153*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MIN3_F32), 0,
22906 : 1/*#VTs*/, MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
22907 : // Src: (AMDGPUfmin3:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (VOP3Mods:f32 f32:f32:$src2, i32:i32:$src2_modifiers)) - Complexity = -964
22908 : // Dst: (V_MIN3_F32:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i32:i32:$src2_modifiers, f32:f32:$src2, i1:i1:$clamp, i32:i32:$omod)
22909 : /*61168*/ /*SwitchOpcode*/ 29, TARGET_VAL(AMDGPUISD::FMAX3),// ->61200
22910 : /*61171*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
22911 : /*61172*/ OPC_RecordChild1, // #1 = $VOP3Mods:src1:src1_modifiers
22912 : /*61173*/ OPC_RecordChild2, // #2 = $VOP3Mods:src2:src2_modifiers
22913 : /*61174*/ OPC_CheckType, MVT::f32,
22914 : /*61176*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #3 #4 #5 #6
22915 : /*61179*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #7 #8
22916 : /*61182*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // SelectVOP3Mods:$ #9 #10
22917 : /*61185*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_MAX3_F32), 0,
22918 : 1/*#VTs*/, MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
22919 : // Src: (AMDGPUfmax3:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (VOP3Mods:f32 f32:f32:$src2, i32:i32:$src2_modifiers)) - Complexity = -964
22920 : // Dst: (V_MAX3_F32:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i32:i32:$src2_modifiers, f32:f32:$src2, i1:i1:$clamp, i32:i32:$omod)
22921 : /*61200*/ /*SwitchOpcode*/ 57, TARGET_VAL(AMDGPUISD::DIV_FIXUP),// ->61260
22922 : /*61203*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
22923 : /*61204*/ OPC_RecordChild1, // #1 = $VOP3Mods:src1:src1_modifiers
22924 : /*61205*/ OPC_RecordChild2, // #2 = $VOP3Mods:src2:src2_modifiers
22925 : /*61206*/ OPC_SwitchType /*2 cases */, 24, MVT::f32,// ->61233
22926 : /*61209*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #3 #4 #5 #6
22927 : /*61212*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #7 #8
22928 : /*61215*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // SelectVOP3Mods:$ #9 #10
22929 : /*61218*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_DIV_FIXUP_F32), 0,
22930 : 1/*#VTs*/, MVT::f32, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
22931 : // Src: (AMDGPUdiv_fixup:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (VOP3Mods:f32 f32:f32:$src2, i32:i32:$src2_modifiers)) - Complexity = -964
22932 : // Dst: (V_DIV_FIXUP_F32:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i32:i32:$src2_modifiers, f32:f32:$src2, i1:i1:$clamp, i32:i32:$omod)
22933 : /*61233*/ /*SwitchType*/ 24, MVT::f64,// ->61259
22934 : /*61235*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #3 #4 #5 #6
22935 : /*61238*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #7 #8
22936 : /*61241*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // SelectVOP3Mods:$ #9 #10
22937 : /*61244*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_DIV_FIXUP_F64), 0,
22938 : 1/*#VTs*/, MVT::f64, 8/*#Ops*/, 4, 3, 8, 7, 10, 9, 5, 6,
22939 : // Src: (AMDGPUdiv_fixup:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (VOP3Mods:f64 f64:f64:$src2, i32:i32:$src2_modifiers)) - Complexity = -964
22940 : // Dst: (V_DIV_FIXUP_F64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i32:i32:$src2_modifiers, f64:f64:$src2, i1:i1:$clamp, i32:i32:$omod)
22941 : /*61259*/ 0, // EndSwitchType
22942 : /*61260*/ /*SwitchOpcode*/ 66, TARGET_VAL(AMDGPUISD::DIV_FMAS),// ->61329
22943 : /*61263*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
22944 : /*61264*/ OPC_RecordChild1, // #1 = $VOP3Mods:src1:src1_modifiers
22945 : /*61265*/ OPC_RecordChild2, // #2 = $VOP3Mods:src2:src2_modifiers
22946 : /*61266*/ OPC_RecordChild3, // #3 = physreg input VCC
22947 : /*61267*/ OPC_CheckChild3Type, MVT::i1,
22948 : /*61269*/ OPC_SwitchType /*2 cases */, 27, MVT::f32,// ->61299
22949 : /*61272*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #4 #5 #6 #7
22950 : /*61275*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #8 #9
22951 : /*61278*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // SelectVOP3Mods:$ #10 #11
22952 : /*61281*/ OPC_EmitCopyToReg, 3, AMDGPU::VCC,
22953 : /*61284*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_DIV_FMAS_F32), 0|OPFL_GlueInput,
22954 : 1/*#VTs*/, MVT::f32, 8/*#Ops*/, 5, 4, 9, 8, 11, 10, 6, 7,
22955 : // Src: (AMDGPUdiv_fmas:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f32 f32:f32:$src1, i32:i32:$src1_modifiers), (VOP3Mods:f32 f32:f32:$src2, i32:i32:$src2_modifiers), VCC:i1) - Complexity = -964
22956 : // Dst: (V_DIV_FMAS_F32:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, f32:f32:$src1, i32:i32:$src2_modifiers, f32:f32:$src2, i1:i1:$clamp, i32:i32:$omod)
22957 : /*61299*/ /*SwitchType*/ 27, MVT::f64,// ->61328
22958 : /*61301*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #4 #5 #6 #7
22959 : /*61304*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #8 #9
22960 : /*61307*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // SelectVOP3Mods:$ #10 #11
22961 : /*61310*/ OPC_EmitCopyToReg, 3, AMDGPU::VCC,
22962 : /*61313*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_DIV_FMAS_F64), 0|OPFL_GlueInput,
22963 : 1/*#VTs*/, MVT::f64, 8/*#Ops*/, 5, 4, 9, 8, 11, 10, 6, 7,
22964 : // Src: (AMDGPUdiv_fmas:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:f64 f64:f64:$src1, i32:i32:$src1_modifiers), (VOP3Mods:f64 f64:f64:$src2, i32:i32:$src2_modifiers), VCC:i1) - Complexity = -964
22965 : // Dst: (V_DIV_FMAS_F64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, f64:f64:$src1, i32:i32:$src2_modifiers, f64:f64:$src2, i1:i1:$clamp, i32:i32:$omod)
22966 : /*61328*/ 0, // EndSwitchType
22967 : /*61329*/ /*SwitchOpcode*/ 48, TARGET_VAL(AMDGPUISD::LDEXP),// ->61380
22968 : /*61332*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
22969 : /*61333*/ OPC_RecordChild1, // #1 = $VOP3Mods:src1:src1_modifiers
22970 : /*61334*/ OPC_CheckChild1Type, MVT::i32,
22971 : /*61336*/ OPC_SwitchType /*2 cases */, 19, MVT::f32,// ->61358
22972 : /*61339*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
22973 : /*61342*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
22974 : /*61345*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_LDEXP_F32_e64), 0,
22975 : 1/*#VTs*/, MVT::f32, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
22976 : // Src: (AMDGPUldexp:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:i32 i32:i32:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
22977 : // Dst: (V_LDEXP_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i32:i32:$src1_modifiers, i32:i32:$src1, i1:i1:$clamp, i32:i32:$omod)
22978 : /*61358*/ /*SwitchType*/ 19, MVT::f64,// ->61379
22979 : /*61360*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
22980 : /*61363*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
22981 : /*61366*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_LDEXP_F64), 0,
22982 : 1/*#VTs*/, MVT::f64, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
22983 : // Src: (AMDGPUldexp:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:i32 i32:i32:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
22984 : // Dst: (V_LDEXP_F64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, i32:i32:$src1, i1:i1:$clamp, i32:i32:$omod)
22985 : /*61379*/ 0, // EndSwitchType
22986 : /*61380*/ /*SwitchOpcode*/ 25, TARGET_VAL(AMDGPUISD::TRIG_PREOP),// ->61408
22987 : /*61383*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
22988 : /*61384*/ OPC_RecordChild1, // #1 = $VOP3Mods:src1:src1_modifiers
22989 : /*61385*/ OPC_CheckChild1Type, MVT::i32,
22990 : /*61387*/ OPC_CheckType, MVT::f64,
22991 : /*61389*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #2 #3 #4 #5
22992 : /*61392*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // SelectVOP3Mods:$ #6 #7
22993 : /*61395*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_TRIG_PREOP_F64), 0,
22994 : 1/*#VTs*/, MVT::f64, 6/*#Ops*/, 3, 2, 7, 6, 4, 5,
22995 : // Src: (AMDGPUtrig_preop:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod), (VOP3Mods:i32 i32:i32:$src1, i32:i32:$src1_modifiers)) - Complexity = -973
22996 : // Dst: (V_TRIG_PREOP_F64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i32:i32:$src1_modifiers, i32:i32:$src1, i1:i1:$clamp, i32:i32:$omod)
22997 : /*61408*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::FP_ROUND),// ->61426
22998 : /*61411*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
22999 : /*61412*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
23000 : /*61415*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F32_F64_e64), 0,
23001 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
23002 : // Src: (fround:f32 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
23003 : // Dst: (V_CVT_F32_F64_e64:f32 i32:i32:$src0_modifiers, f64:f64:$src0, i1:i1:$clamp, i32:i32:$omod)
23004 : /*61426*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::FP_EXTEND),// ->61444
23005 : /*61429*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
23006 : /*61430*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
23007 : /*61433*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F64_F32_e64), 0,
23008 : 1/*#VTs*/, MVT::f64, 4/*#Ops*/, 2, 1, 3, 4,
23009 : // Src: (fextend:f64 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
23010 : // Dst: (V_CVT_F64_F32_e64:f64 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
23011 : /*61444*/ /*SwitchOpcode*/ 35, TARGET_VAL(AMDGPUISD::RSQ),// ->61482
23012 : /*61447*/ OPC_RecordChild0, // #0 = $VOP3Mods0:src0:src0_modifiers:clamp:omod
23013 : /*61448*/ OPC_SwitchType /*2 cases */, 14, MVT::f32,// ->61465
23014 : /*61451*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
23015 : /*61454*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_RSQ_F32_e64), 0,
23016 : 1/*#VTs*/, MVT::f32, 4/*#Ops*/, 2, 1, 3, 4,
23017 : // Src: (AMDGPUrsq:f32 (VOP3Mods0:f32 f32:f32:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
23018 : // Dst: (V_RSQ_F32_e64:f32 i32:i32:$src0_modifiers, f32:f32:$src0, i1:i1:$clamp, i32:i32:$omod)
23019 : /*61465*/ /*SwitchType*/ 14, MVT::f64,// ->61481
23020 : /*61467*/ OPC_CheckComplexPat, /*CP*/11, /*#*/0, // SelectVOP3Mods0:$ #1 #2 #3 #4
23021 : /*61470*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_RSQ_F64_e64), 0,
23022 : 1/*#VTs*/, MVT::f64, 4/*#Ops*/, 2, 1, 3, 4,
23023 : // Src: (AMDGPUrsq:f64 (VOP3Mods0:f64 f64:f64:$src0, i32:i32:$src0_modifiers, i1:i1:$clamp, i32:i32:$omod)) - Complexity = -982
23024 : // Dst: (V_RSQ_F64_e64:f64 i32:i32:$src0_modifiers, f64:f64:$src0, i1:i1:$clamp, i32:i32:$omod)
23025 : /*61481*/ 0, // EndSwitchType
23026 : /*61482*/ /*SwitchOpcode*/ 13, TARGET_VAL(ISD::FP16_TO_FP),// ->61498
23027 : /*61485*/ OPC_RecordChild0, // #0 = $src0
23028 : /*61486*/ OPC_CheckChild0Type, MVT::i32,
23029 : /*61488*/ OPC_CheckType, MVT::f32,
23030 : /*61490*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F32_F16_e64), 0,
23031 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 0,
23032 : // Src: (f16_to_fp:f32 i32:i32:$src0) - Complexity = -997
23033 : // Dst: (V_CVT_F32_F16_e64:f32 i32:i32:$src0)
23034 : /*61498*/ /*SwitchOpcode*/ 13, TARGET_VAL(AMDGPUISD::CVT_F32_UBYTE0),// ->61514
23035 : /*61501*/ OPC_RecordChild0, // #0 = $src0
23036 : /*61502*/ OPC_CheckChild0Type, MVT::i32,
23037 : /*61504*/ OPC_CheckType, MVT::f32,
23038 : /*61506*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F32_UBYTE0_e64), 0,
23039 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 0,
23040 : // Src: (AMDGPUcvt_f32_ubyte0:f32 i32:i32:$src0) - Complexity = -997
23041 : // Dst: (V_CVT_F32_UBYTE0_e64:f32 i32:i32:$src0)
23042 : /*61514*/ /*SwitchOpcode*/ 13, TARGET_VAL(AMDGPUISD::CVT_F32_UBYTE1),// ->61530
23043 : /*61517*/ OPC_RecordChild0, // #0 = $src0
23044 : /*61518*/ OPC_CheckChild0Type, MVT::i32,
23045 : /*61520*/ OPC_CheckType, MVT::f32,
23046 : /*61522*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F32_UBYTE1_e64), 0,
23047 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 0,
23048 : // Src: (AMDGPUcvt_f32_ubyte1:f32 i32:i32:$src0) - Complexity = -997
23049 : // Dst: (V_CVT_F32_UBYTE1_e64:f32 i32:i32:$src0)
23050 : /*61530*/ /*SwitchOpcode*/ 13, TARGET_VAL(AMDGPUISD::CVT_F32_UBYTE2),// ->61546
23051 : /*61533*/ OPC_RecordChild0, // #0 = $src0
23052 : /*61534*/ OPC_CheckChild0Type, MVT::i32,
23053 : /*61536*/ OPC_CheckType, MVT::f32,
23054 : /*61538*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F32_UBYTE2_e64), 0,
23055 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 0,
23056 : // Src: (AMDGPUcvt_f32_ubyte2:f32 i32:i32:$src0) - Complexity = -997
23057 : // Dst: (V_CVT_F32_UBYTE2_e64:f32 i32:i32:$src0)
23058 : /*61546*/ /*SwitchOpcode*/ 13, TARGET_VAL(AMDGPUISD::CVT_F32_UBYTE3),// ->61562
23059 : /*61549*/ OPC_RecordChild0, // #0 = $src0
23060 : /*61550*/ OPC_CheckChild0Type, MVT::i32,
23061 : /*61552*/ OPC_CheckType, MVT::f32,
23062 : /*61554*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::V_CVT_F32_UBYTE3_e64), 0,
23063 : 1/*#VTs*/, MVT::f32, 1/*#Ops*/, 0,
23064 : // Src: (AMDGPUcvt_f32_ubyte3:f32 i32:i32:$src0) - Complexity = -997
23065 : // Dst: (V_CVT_F32_UBYTE3_e64:f32 i32:i32:$src0)
23066 : /*61562*/ /*SwitchOpcode*/ 52|128,14/*1844*/, TARGET_VAL(ISD::INSERT_VECTOR_ELT),// ->63410
23067 : /*61566*/ OPC_RecordChild0, // #0 = $vec
23068 : /*61567*/ OPC_RecordChild1, // #1 = $val
23069 : /*61568*/ OPC_Scope, 32|128,6/*800*/, /*->62371*/ // 6 children in Scope
23070 : /*61571*/ OPC_CheckChild1Type, MVT::i32,
23071 : /*61573*/ OPC_Scope, 90, /*->61665*/ // 17 children in Scope
23072 : /*61575*/ OPC_MoveChild, 2,
23073 : /*61577*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
23074 : /*61580*/ OPC_RecordChild0, // #2 = $idx
23075 : /*61581*/ OPC_RecordChild1, // #3 = $off
23076 : /*61582*/ OPC_MoveChild, 1,
23077 : /*61584*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23078 : /*61587*/ OPC_MoveParent,
23079 : /*61588*/ OPC_CheckType, MVT::i32,
23080 : /*61590*/ OPC_MoveParent,
23081 : /*61591*/ OPC_SwitchType /*4 cases */, 16, MVT::v2i32,// ->61610
23082 : /*61594*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23083 : /*61596*/ OPC_EmitConvertToTarget, 3,
23084 : /*61598*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V2), 0,
23085 : 2/*#VTs*/, MVT::v2i32, MVT::i1, 4/*#Ops*/, 0, 2, 4, 1,
23086 : // Src: (vector_insert:v2i32 v2i32:v2i32:$vec, i32:i32:$val, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
23087 : // Dst: (SI_INDIRECT_DST_V2:v2i32:i1 ?:v2i32:$vec, ?:i32:$idx, (imm:i32):$off, ?:i32:$val)
23088 : /*61610*/ /*SwitchType*/ 16, MVT::v4i32,// ->61628
23089 : /*61612*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23090 : /*61614*/ OPC_EmitConvertToTarget, 3,
23091 : /*61616*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V4), 0,
23092 : 2/*#VTs*/, MVT::v4i32, MVT::i1, 4/*#Ops*/, 0, 2, 4, 1,
23093 : // Src: (vector_insert:v4i32 v4i32:v4i32:$vec, i32:i32:$val, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
23094 : // Dst: (SI_INDIRECT_DST_V4:v4i32:i1 ?:v4i32:$vec, ?:i32:$idx, (imm:i32):$off, ?:i32:$val)
23095 : /*61628*/ /*SwitchType*/ 16, MVT::v8i32,// ->61646
23096 : /*61630*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23097 : /*61632*/ OPC_EmitConvertToTarget, 3,
23098 : /*61634*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V8), 0,
23099 : 2/*#VTs*/, MVT::v8i32, MVT::i1, 4/*#Ops*/, 0, 2, 4, 1,
23100 : // Src: (vector_insert:v8i32 v8i32:v8i32:$vec, i32:i32:$val, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
23101 : // Dst: (SI_INDIRECT_DST_V8:v8i32:i1 ?:v8i32:$vec, ?:i32:$idx, (imm:i32):$off, ?:i32:$val)
23102 : /*61646*/ /*SwitchType*/ 16, MVT::v16i32,// ->61664
23103 : /*61648*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23104 : /*61650*/ OPC_EmitConvertToTarget, 3,
23105 : /*61652*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V16), 0,
23106 : 2/*#VTs*/, MVT::v16i32, MVT::i1, 4/*#Ops*/, 0, 2, 4, 1,
23107 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$val, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
23108 : // Dst: (SI_INDIRECT_DST_V16:v16i32:i1 ?:v16i32:$vec, ?:i32:$idx, (imm:i32):$off, ?:i32:$val)
23109 : /*61664*/ 0, // EndSwitchType
23110 : /*61665*/ /*Scope*/ 110, /*->61776*/
23111 : /*61666*/ OPC_CheckChild2Integer, 0,
23112 : /*61668*/ OPC_SwitchType /*4 cases */, 34, MVT::v4i32,// ->61705
23113 : /*61671*/ OPC_Scope, 15, /*->61688*/ // 2 children in Scope
23114 : /*61673*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23115 : /*61675*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23116 : /*61678*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23117 : 1/*#VTs*/, MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
23118 : // Src: (vector_insert:v4i32 v4i32:v4i32:$vec, i32:i32:$elem, 0:iPTR) - Complexity = 8
23119 : // Dst: (INSERT_SUBREG:v4i32 ?:v4i32:$vec, ?:i32:$elem, sub0:i32)
23120 : /*61688*/ /*Scope*/ 15, /*->61704*/
23121 : /*61689*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23122 : /*61691*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23123 : /*61694*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23124 : 1/*#VTs*/, MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
23125 : // Src: (vector_insert:v4i32 v4i32:v4i32:$vec, i32:i32:$elem, 0:iPTR) - Complexity = 8
23126 : // Dst: (INSERT_SUBREG:v4i32 ?:v4i32:$vec, ?:i32:$elem, sub0:i32)
23127 : /*61704*/ 0, /*End of Scope*/
23128 : /*61705*/ /*SwitchType*/ 34, MVT::v2i32,// ->61741
23129 : /*61707*/ OPC_Scope, 15, /*->61724*/ // 2 children in Scope
23130 : /*61709*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23131 : /*61711*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23132 : /*61714*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23133 : 1/*#VTs*/, MVT::v2i32, 3/*#Ops*/, 0, 1, 2,
23134 : // Src: (vector_insert:v2i32 v2i32:v2i32:$vec, i32:i32:$elem, 0:iPTR) - Complexity = 8
23135 : // Dst: (INSERT_SUBREG:v2i32 ?:v2i32:$vec, ?:i32:$elem, sub0:i32)
23136 : /*61724*/ /*Scope*/ 15, /*->61740*/
23137 : /*61725*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23138 : /*61727*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23139 : /*61730*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23140 : 1/*#VTs*/, MVT::v2i32, 3/*#Ops*/, 0, 1, 2,
23141 : // Src: (vector_insert:v2i32 v2i32:v2i32:$vec, i32:i32:$elem, 0:iPTR) - Complexity = 8
23142 : // Dst: (INSERT_SUBREG:v2i32 ?:v2i32:$vec, ?:i32:$elem, sub0:i32)
23143 : /*61740*/ 0, /*End of Scope*/
23144 : /*61741*/ /*SwitchType*/ 15, MVT::v8i32,// ->61758
23145 : /*61743*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23146 : /*61745*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23147 : /*61748*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23148 : 1/*#VTs*/, MVT::v8i32, 3/*#Ops*/, 0, 1, 2,
23149 : // Src: (vector_insert:v8i32 v8i32:v8i32:$vec, i32:i32:$elem, 0:iPTR) - Complexity = 8
23150 : // Dst: (INSERT_SUBREG:v8i32 ?:v8i32:$vec, ?:i32:$elem, sub0:i32)
23151 : /*61758*/ /*SwitchType*/ 15, MVT::v16i32,// ->61775
23152 : /*61760*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23153 : /*61762*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23154 : /*61765*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23155 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23156 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 0:iPTR) - Complexity = 8
23157 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub0:i32)
23158 : /*61775*/ 0, // EndSwitchType
23159 : /*61776*/ /*Scope*/ 110, /*->61887*/
23160 : /*61777*/ OPC_CheckChild2Integer, 1,
23161 : /*61779*/ OPC_SwitchType /*4 cases */, 34, MVT::v4i32,// ->61816
23162 : /*61782*/ OPC_Scope, 15, /*->61799*/ // 2 children in Scope
23163 : /*61784*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23164 : /*61786*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23165 : /*61789*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23166 : 1/*#VTs*/, MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
23167 : // Src: (vector_insert:v4i32 v4i32:v4i32:$vec, i32:i32:$elem, 1:iPTR) - Complexity = 8
23168 : // Dst: (INSERT_SUBREG:v4i32 ?:v4i32:$vec, ?:i32:$elem, sub1:i32)
23169 : /*61799*/ /*Scope*/ 15, /*->61815*/
23170 : /*61800*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23171 : /*61802*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23172 : /*61805*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23173 : 1/*#VTs*/, MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
23174 : // Src: (vector_insert:v4i32 v4i32:v4i32:$vec, i32:i32:$elem, 1:iPTR) - Complexity = 8
23175 : // Dst: (INSERT_SUBREG:v4i32 ?:v4i32:$vec, ?:i32:$elem, sub1:i32)
23176 : /*61815*/ 0, /*End of Scope*/
23177 : /*61816*/ /*SwitchType*/ 34, MVT::v2i32,// ->61852
23178 : /*61818*/ OPC_Scope, 15, /*->61835*/ // 2 children in Scope
23179 : /*61820*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23180 : /*61822*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23181 : /*61825*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23182 : 1/*#VTs*/, MVT::v2i32, 3/*#Ops*/, 0, 1, 2,
23183 : // Src: (vector_insert:v2i32 v2i32:v2i32:$vec, i32:i32:$elem, 1:iPTR) - Complexity = 8
23184 : // Dst: (INSERT_SUBREG:v2i32 ?:v2i32:$vec, ?:i32:$elem, sub1:i32)
23185 : /*61835*/ /*Scope*/ 15, /*->61851*/
23186 : /*61836*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23187 : /*61838*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23188 : /*61841*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23189 : 1/*#VTs*/, MVT::v2i32, 3/*#Ops*/, 0, 1, 2,
23190 : // Src: (vector_insert:v2i32 v2i32:v2i32:$vec, i32:i32:$elem, 1:iPTR) - Complexity = 8
23191 : // Dst: (INSERT_SUBREG:v2i32 ?:v2i32:$vec, ?:i32:$elem, sub1:i32)
23192 : /*61851*/ 0, /*End of Scope*/
23193 : /*61852*/ /*SwitchType*/ 15, MVT::v8i32,// ->61869
23194 : /*61854*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23195 : /*61856*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23196 : /*61859*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23197 : 1/*#VTs*/, MVT::v8i32, 3/*#Ops*/, 0, 1, 2,
23198 : // Src: (vector_insert:v8i32 v8i32:v8i32:$vec, i32:i32:$elem, 1:iPTR) - Complexity = 8
23199 : // Dst: (INSERT_SUBREG:v8i32 ?:v8i32:$vec, ?:i32:$elem, sub1:i32)
23200 : /*61869*/ /*SwitchType*/ 15, MVT::v16i32,// ->61886
23201 : /*61871*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23202 : /*61873*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23203 : /*61876*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23204 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23205 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 1:iPTR) - Complexity = 8
23206 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub1:i32)
23207 : /*61886*/ 0, // EndSwitchType
23208 : /*61887*/ /*Scope*/ 91, /*->61979*/
23209 : /*61888*/ OPC_CheckChild2Integer, 2,
23210 : /*61890*/ OPC_SwitchType /*4 cases */, 34, MVT::v4i32,// ->61927
23211 : /*61893*/ OPC_Scope, 15, /*->61910*/ // 2 children in Scope
23212 : /*61895*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23213 : /*61897*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
23214 : /*61900*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23215 : 1/*#VTs*/, MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
23216 : // Src: (vector_insert:v4i32 v4i32:v4i32:$vec, i32:i32:$elem, 2:iPTR) - Complexity = 8
23217 : // Dst: (INSERT_SUBREG:v4i32 ?:v4i32:$vec, ?:i32:$elem, sub2:i32)
23218 : /*61910*/ /*Scope*/ 15, /*->61926*/
23219 : /*61911*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23220 : /*61913*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
23221 : /*61916*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23222 : 1/*#VTs*/, MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
23223 : // Src: (vector_insert:v4i32 v4i32:v4i32:$vec, i32:i32:$elem, 2:iPTR) - Complexity = 8
23224 : // Dst: (INSERT_SUBREG:v4i32 ?:v4i32:$vec, ?:i32:$elem, sub2:i32)
23225 : /*61926*/ 0, /*End of Scope*/
23226 : /*61927*/ /*SwitchType*/ 15, MVT::v2i32,// ->61944
23227 : /*61929*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23228 : /*61931*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
23229 : /*61934*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23230 : 1/*#VTs*/, MVT::v2i32, 3/*#Ops*/, 0, 1, 2,
23231 : // Src: (vector_insert:v2i32 v2i32:v2i32:$vec, i32:i32:$elem, 2:iPTR) - Complexity = 8
23232 : // Dst: (INSERT_SUBREG:v2i32 ?:v2i32:$vec, ?:i32:$elem, sub2:i32)
23233 : /*61944*/ /*SwitchType*/ 15, MVT::v8i32,// ->61961
23234 : /*61946*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23235 : /*61948*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
23236 : /*61951*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23237 : 1/*#VTs*/, MVT::v8i32, 3/*#Ops*/, 0, 1, 2,
23238 : // Src: (vector_insert:v8i32 v8i32:v8i32:$vec, i32:i32:$elem, 2:iPTR) - Complexity = 8
23239 : // Dst: (INSERT_SUBREG:v8i32 ?:v8i32:$vec, ?:i32:$elem, sub2:i32)
23240 : /*61961*/ /*SwitchType*/ 15, MVT::v16i32,// ->61978
23241 : /*61963*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23242 : /*61965*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
23243 : /*61968*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23244 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23245 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 2:iPTR) - Complexity = 8
23246 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub2:i32)
23247 : /*61978*/ 0, // EndSwitchType
23248 : /*61979*/ /*Scope*/ 74, /*->62054*/
23249 : /*61980*/ OPC_CheckChild2Integer, 3,
23250 : /*61982*/ OPC_SwitchType /*3 cases */, 34, MVT::v4i32,// ->62019
23251 : /*61985*/ OPC_Scope, 15, /*->62002*/ // 2 children in Scope
23252 : /*61987*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23253 : /*61989*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
23254 : /*61992*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23255 : 1/*#VTs*/, MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
23256 : // Src: (vector_insert:v4i32 v4i32:v4i32:$vec, i32:i32:$elem, 3:iPTR) - Complexity = 8
23257 : // Dst: (INSERT_SUBREG:v4i32 ?:v4i32:$vec, ?:i32:$elem, sub3:i32)
23258 : /*62002*/ /*Scope*/ 15, /*->62018*/
23259 : /*62003*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23260 : /*62005*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
23261 : /*62008*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23262 : 1/*#VTs*/, MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
23263 : // Src: (vector_insert:v4i32 v4i32:v4i32:$vec, i32:i32:$elem, 3:iPTR) - Complexity = 8
23264 : // Dst: (INSERT_SUBREG:v4i32 ?:v4i32:$vec, ?:i32:$elem, sub3:i32)
23265 : /*62018*/ 0, /*End of Scope*/
23266 : /*62019*/ /*SwitchType*/ 15, MVT::v8i32,// ->62036
23267 : /*62021*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23268 : /*62023*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
23269 : /*62026*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23270 : 1/*#VTs*/, MVT::v8i32, 3/*#Ops*/, 0, 1, 2,
23271 : // Src: (vector_insert:v8i32 v8i32:v8i32:$vec, i32:i32:$elem, 3:iPTR) - Complexity = 8
23272 : // Dst: (INSERT_SUBREG:v8i32 ?:v8i32:$vec, ?:i32:$elem, sub3:i32)
23273 : /*62036*/ /*SwitchType*/ 15, MVT::v16i32,// ->62053
23274 : /*62038*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23275 : /*62040*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
23276 : /*62043*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23277 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23278 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 3:iPTR) - Complexity = 8
23279 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub3:i32)
23280 : /*62053*/ 0, // EndSwitchType
23281 : /*62054*/ /*Scope*/ 38, /*->62093*/
23282 : /*62055*/ OPC_CheckChild2Integer, 4,
23283 : /*62057*/ OPC_SwitchType /*2 cases */, 15, MVT::v8i32,// ->62075
23284 : /*62060*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23285 : /*62062*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub4,
23286 : /*62065*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23287 : 1/*#VTs*/, MVT::v8i32, 3/*#Ops*/, 0, 1, 2,
23288 : // Src: (vector_insert:v8i32 v8i32:v8i32:$vec, i32:i32:$elem, 4:iPTR) - Complexity = 8
23289 : // Dst: (INSERT_SUBREG:v8i32 ?:v8i32:$vec, ?:i32:$elem, sub4:i32)
23290 : /*62075*/ /*SwitchType*/ 15, MVT::v16i32,// ->62092
23291 : /*62077*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23292 : /*62079*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub4,
23293 : /*62082*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23294 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23295 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 4:iPTR) - Complexity = 8
23296 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub4:i32)
23297 : /*62092*/ 0, // EndSwitchType
23298 : /*62093*/ /*Scope*/ 38, /*->62132*/
23299 : /*62094*/ OPC_CheckChild2Integer, 5,
23300 : /*62096*/ OPC_SwitchType /*2 cases */, 15, MVT::v8i32,// ->62114
23301 : /*62099*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23302 : /*62101*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub5,
23303 : /*62104*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23304 : 1/*#VTs*/, MVT::v8i32, 3/*#Ops*/, 0, 1, 2,
23305 : // Src: (vector_insert:v8i32 v8i32:v8i32:$vec, i32:i32:$elem, 5:iPTR) - Complexity = 8
23306 : // Dst: (INSERT_SUBREG:v8i32 ?:v8i32:$vec, ?:i32:$elem, sub5:i32)
23307 : /*62114*/ /*SwitchType*/ 15, MVT::v16i32,// ->62131
23308 : /*62116*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23309 : /*62118*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub5,
23310 : /*62121*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23311 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23312 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 5:iPTR) - Complexity = 8
23313 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub5:i32)
23314 : /*62131*/ 0, // EndSwitchType
23315 : /*62132*/ /*Scope*/ 38, /*->62171*/
23316 : /*62133*/ OPC_CheckChild2Integer, 6,
23317 : /*62135*/ OPC_SwitchType /*2 cases */, 15, MVT::v8i32,// ->62153
23318 : /*62138*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23319 : /*62140*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub6,
23320 : /*62143*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23321 : 1/*#VTs*/, MVT::v8i32, 3/*#Ops*/, 0, 1, 2,
23322 : // Src: (vector_insert:v8i32 v8i32:v8i32:$vec, i32:i32:$elem, 6:iPTR) - Complexity = 8
23323 : // Dst: (INSERT_SUBREG:v8i32 ?:v8i32:$vec, ?:i32:$elem, sub6:i32)
23324 : /*62153*/ /*SwitchType*/ 15, MVT::v16i32,// ->62170
23325 : /*62155*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23326 : /*62157*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub6,
23327 : /*62160*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23328 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23329 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 6:iPTR) - Complexity = 8
23330 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub6:i32)
23331 : /*62170*/ 0, // EndSwitchType
23332 : /*62171*/ /*Scope*/ 38, /*->62210*/
23333 : /*62172*/ OPC_CheckChild2Integer, 7,
23334 : /*62174*/ OPC_SwitchType /*2 cases */, 15, MVT::v8i32,// ->62192
23335 : /*62177*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23336 : /*62179*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub7,
23337 : /*62182*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23338 : 1/*#VTs*/, MVT::v8i32, 3/*#Ops*/, 0, 1, 2,
23339 : // Src: (vector_insert:v8i32 v8i32:v8i32:$vec, i32:i32:$elem, 7:iPTR) - Complexity = 8
23340 : // Dst: (INSERT_SUBREG:v8i32 ?:v8i32:$vec, ?:i32:$elem, sub7:i32)
23341 : /*62192*/ /*SwitchType*/ 15, MVT::v16i32,// ->62209
23342 : /*62194*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23343 : /*62196*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub7,
23344 : /*62199*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23345 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23346 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 7:iPTR) - Complexity = 8
23347 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub7:i32)
23348 : /*62209*/ 0, // EndSwitchType
23349 : /*62210*/ /*Scope*/ 19, /*->62230*/
23350 : /*62211*/ OPC_CheckChild2Integer, 8,
23351 : /*62213*/ OPC_CheckType, MVT::v16i32,
23352 : /*62215*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23353 : /*62217*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub8,
23354 : /*62220*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23355 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23356 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 8:iPTR) - Complexity = 8
23357 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub8:i32)
23358 : /*62230*/ /*Scope*/ 19, /*->62250*/
23359 : /*62231*/ OPC_CheckChild2Integer, 9,
23360 : /*62233*/ OPC_CheckType, MVT::v16i32,
23361 : /*62235*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23362 : /*62237*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub9,
23363 : /*62240*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23364 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23365 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 9:iPTR) - Complexity = 8
23366 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub9:i32)
23367 : /*62250*/ /*Scope*/ 19, /*->62270*/
23368 : /*62251*/ OPC_CheckChild2Integer, 10,
23369 : /*62253*/ OPC_CheckType, MVT::v16i32,
23370 : /*62255*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23371 : /*62257*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub10,
23372 : /*62260*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23373 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23374 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 10:iPTR) - Complexity = 8
23375 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub10:i32)
23376 : /*62270*/ /*Scope*/ 19, /*->62290*/
23377 : /*62271*/ OPC_CheckChild2Integer, 11,
23378 : /*62273*/ OPC_CheckType, MVT::v16i32,
23379 : /*62275*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23380 : /*62277*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub11,
23381 : /*62280*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23382 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23383 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 11:iPTR) - Complexity = 8
23384 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub11:i32)
23385 : /*62290*/ /*Scope*/ 19, /*->62310*/
23386 : /*62291*/ OPC_CheckChild2Integer, 12,
23387 : /*62293*/ OPC_CheckType, MVT::v16i32,
23388 : /*62295*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23389 : /*62297*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub12,
23390 : /*62300*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23391 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23392 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 12:iPTR) - Complexity = 8
23393 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub12:i32)
23394 : /*62310*/ /*Scope*/ 19, /*->62330*/
23395 : /*62311*/ OPC_CheckChild2Integer, 13,
23396 : /*62313*/ OPC_CheckType, MVT::v16i32,
23397 : /*62315*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23398 : /*62317*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub13,
23399 : /*62320*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23400 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23401 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 13:iPTR) - Complexity = 8
23402 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub13:i32)
23403 : /*62330*/ /*Scope*/ 19, /*->62350*/
23404 : /*62331*/ OPC_CheckChild2Integer, 14,
23405 : /*62333*/ OPC_CheckType, MVT::v16i32,
23406 : /*62335*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23407 : /*62337*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub14,
23408 : /*62340*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23409 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23410 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 14:iPTR) - Complexity = 8
23411 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub14:i32)
23412 : /*62350*/ /*Scope*/ 19, /*->62370*/
23413 : /*62351*/ OPC_CheckChild2Integer, 15,
23414 : /*62353*/ OPC_CheckType, MVT::v16i32,
23415 : /*62355*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23416 : /*62357*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub15,
23417 : /*62360*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23418 : 1/*#VTs*/, MVT::v16i32, 3/*#Ops*/, 0, 1, 2,
23419 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$elem, 15:iPTR) - Complexity = 8
23420 : // Dst: (INSERT_SUBREG:v16i32 ?:v16i32:$vec, ?:i32:$elem, sub15:i32)
23421 : /*62370*/ 0, /*End of Scope*/
23422 : /*62371*/ /*Scope*/ 33, /*->62405*/
23423 : /*62372*/ OPC_RecordChild2, // #2 = $index
23424 : /*62373*/ OPC_CheckChild2Type, MVT::i32,
23425 : /*62375*/ OPC_SwitchType /*2 cases */, 12, MVT::v2i32,// ->62390
23426 : /*62378*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23427 : /*62380*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_INSERT_ELT_V2), 0,
23428 : 1/*#VTs*/, MVT::v2i32, 3/*#Ops*/, 0, 1, 2,
23429 : // Src: (insertelt:v2i32 v2i32:v2i32:$vec, i32:i32:$value, i32:i32:$index) - Complexity = 3
23430 : // Dst: (R600_INSERT_ELT_V2:v2i32 ?:v2i32:$vec, ?:i32:$value, ?:i32:$index)
23431 : /*62390*/ /*SwitchType*/ 12, MVT::v4i32,// ->62404
23432 : /*62392*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23433 : /*62394*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_INSERT_ELT_V4), 0,
23434 : 1/*#VTs*/, MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
23435 : // Src: (insertelt:v4i32 v4i32:v4i32:$vec, i32:i32:$value, i32:i32:$index) - Complexity = 3
23436 : // Dst: (R600_INSERT_ELT_V4:v4i32 ?:v4i32:$vec, ?:i32:$value, ?:i32:$index)
23437 : /*62404*/ 0, // EndSwitchType
23438 : /*62405*/ /*Scope*/ 83, /*->62489*/
23439 : /*62406*/ OPC_CheckChild1Type, MVT::i32,
23440 : /*62408*/ OPC_RecordChild2, // #2 = $idx
23441 : /*62409*/ OPC_CheckChild2Type, MVT::i32,
23442 : /*62411*/ OPC_SwitchType /*4 cases */, 17, MVT::v2i32,// ->62431
23443 : /*62414*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23444 : /*62416*/ OPC_EmitInteger, MVT::i32, 0,
23445 : /*62419*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V2), 0,
23446 : 2/*#VTs*/, MVT::v2i32, MVT::i1, 4/*#Ops*/, 0, 2, 3, 1,
23447 : // Src: (vector_insert:v2i32 v2i32:v2i32:$vec, i32:i32:$val, i32:i32:$idx) - Complexity = 3
23448 : // Dst: (SI_INDIRECT_DST_V2:v2i32:i1 ?:v2i32:$vec, ?:i32:$idx, 0:i32, ?:i32:$val)
23449 : /*62431*/ /*SwitchType*/ 17, MVT::v4i32,// ->62450
23450 : /*62433*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23451 : /*62435*/ OPC_EmitInteger, MVT::i32, 0,
23452 : /*62438*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V4), 0,
23453 : 2/*#VTs*/, MVT::v4i32, MVT::i1, 4/*#Ops*/, 0, 2, 3, 1,
23454 : // Src: (vector_insert:v4i32 v4i32:v4i32:$vec, i32:i32:$val, i32:i32:$idx) - Complexity = 3
23455 : // Dst: (SI_INDIRECT_DST_V4:v4i32:i1 ?:v4i32:$vec, ?:i32:$idx, 0:i32, ?:i32:$val)
23456 : /*62450*/ /*SwitchType*/ 17, MVT::v8i32,// ->62469
23457 : /*62452*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23458 : /*62454*/ OPC_EmitInteger, MVT::i32, 0,
23459 : /*62457*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V8), 0,
23460 : 2/*#VTs*/, MVT::v8i32, MVT::i1, 4/*#Ops*/, 0, 2, 3, 1,
23461 : // Src: (vector_insert:v8i32 v8i32:v8i32:$vec, i32:i32:$val, i32:i32:$idx) - Complexity = 3
23462 : // Dst: (SI_INDIRECT_DST_V8:v8i32:i1 ?:v8i32:$vec, ?:i32:$idx, 0:i32, ?:i32:$val)
23463 : /*62469*/ /*SwitchType*/ 17, MVT::v16i32,// ->62488
23464 : /*62471*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23465 : /*62473*/ OPC_EmitInteger, MVT::i32, 0,
23466 : /*62476*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V16), 0,
23467 : 2/*#VTs*/, MVT::v16i32, MVT::i1, 4/*#Ops*/, 0, 2, 3, 1,
23468 : // Src: (vector_insert:v16i32 v16i32:v16i32:$vec, i32:i32:$val, i32:i32:$idx) - Complexity = 3
23469 : // Dst: (SI_INDIRECT_DST_V16:v16i32:i1 ?:v16i32:$vec, ?:i32:$idx, 0:i32, ?:i32:$val)
23470 : /*62488*/ 0, // EndSwitchType
23471 : /*62489*/ /*Scope*/ 32|128,6/*800*/, /*->63291*/
23472 : /*62491*/ OPC_CheckChild1Type, MVT::f32,
23473 : /*62493*/ OPC_Scope, 90, /*->62585*/ // 17 children in Scope
23474 : /*62495*/ OPC_MoveChild, 2,
23475 : /*62497*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
23476 : /*62500*/ OPC_RecordChild0, // #2 = $idx
23477 : /*62501*/ OPC_RecordChild1, // #3 = $off
23478 : /*62502*/ OPC_MoveChild, 1,
23479 : /*62504*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23480 : /*62507*/ OPC_MoveParent,
23481 : /*62508*/ OPC_CheckType, MVT::i32,
23482 : /*62510*/ OPC_MoveParent,
23483 : /*62511*/ OPC_SwitchType /*4 cases */, 16, MVT::v2f32,// ->62530
23484 : /*62514*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23485 : /*62516*/ OPC_EmitConvertToTarget, 3,
23486 : /*62518*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V2), 0,
23487 : 2/*#VTs*/, MVT::v2f32, MVT::i1, 4/*#Ops*/, 0, 2, 4, 1,
23488 : // Src: (vector_insert:v2f32 v2f32:v2f32:$vec, f32:f32:$val, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
23489 : // Dst: (SI_INDIRECT_DST_V2:v2f32:i1 ?:v2f32:$vec, ?:i32:$idx, (imm:i32):$off, ?:f32:$val)
23490 : /*62530*/ /*SwitchType*/ 16, MVT::v4f32,// ->62548
23491 : /*62532*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23492 : /*62534*/ OPC_EmitConvertToTarget, 3,
23493 : /*62536*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V4), 0,
23494 : 2/*#VTs*/, MVT::v4f32, MVT::i1, 4/*#Ops*/, 0, 2, 4, 1,
23495 : // Src: (vector_insert:v4f32 v4f32:v4f32:$vec, f32:f32:$val, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
23496 : // Dst: (SI_INDIRECT_DST_V4:v4f32:i1 ?:v4f32:$vec, ?:i32:$idx, (imm:i32):$off, ?:f32:$val)
23497 : /*62548*/ /*SwitchType*/ 16, MVT::v8f32,// ->62566
23498 : /*62550*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23499 : /*62552*/ OPC_EmitConvertToTarget, 3,
23500 : /*62554*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V8), 0,
23501 : 2/*#VTs*/, MVT::v8f32, MVT::i1, 4/*#Ops*/, 0, 2, 4, 1,
23502 : // Src: (vector_insert:v8f32 v8f32:v8f32:$vec, f32:f32:$val, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
23503 : // Dst: (SI_INDIRECT_DST_V8:v8f32:i1 ?:v8f32:$vec, ?:i32:$idx, (imm:i32):$off, ?:f32:$val)
23504 : /*62566*/ /*SwitchType*/ 16, MVT::v16f32,// ->62584
23505 : /*62568*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23506 : /*62570*/ OPC_EmitConvertToTarget, 3,
23507 : /*62572*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V16), 0,
23508 : 2/*#VTs*/, MVT::v16f32, MVT::i1, 4/*#Ops*/, 0, 2, 4, 1,
23509 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$val, (add:i32 i32:i32:$idx, (imm:i32):$off)) - Complexity = 9
23510 : // Dst: (SI_INDIRECT_DST_V16:v16f32:i1 ?:v16f32:$vec, ?:i32:$idx, (imm:i32):$off, ?:f32:$val)
23511 : /*62584*/ 0, // EndSwitchType
23512 : /*62585*/ /*Scope*/ 110, /*->62696*/
23513 : /*62586*/ OPC_CheckChild2Integer, 0,
23514 : /*62588*/ OPC_SwitchType /*4 cases */, 34, MVT::v4f32,// ->62625
23515 : /*62591*/ OPC_Scope, 15, /*->62608*/ // 2 children in Scope
23516 : /*62593*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23517 : /*62595*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23518 : /*62598*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23519 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
23520 : // Src: (vector_insert:v4f32 v4f32:v4f32:$vec, f32:f32:$elem, 0:iPTR) - Complexity = 8
23521 : // Dst: (INSERT_SUBREG:v4f32 ?:v4f32:$vec, ?:f32:$elem, sub0:i32)
23522 : /*62608*/ /*Scope*/ 15, /*->62624*/
23523 : /*62609*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23524 : /*62611*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23525 : /*62614*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23526 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
23527 : // Src: (vector_insert:v4f32 v4f32:v4f32:$vec, f32:f32:$elem, 0:iPTR) - Complexity = 8
23528 : // Dst: (INSERT_SUBREG:v4f32 ?:v4f32:$vec, ?:f32:$elem, sub0:i32)
23529 : /*62624*/ 0, /*End of Scope*/
23530 : /*62625*/ /*SwitchType*/ 34, MVT::v2f32,// ->62661
23531 : /*62627*/ OPC_Scope, 15, /*->62644*/ // 2 children in Scope
23532 : /*62629*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23533 : /*62631*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23534 : /*62634*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23535 : 1/*#VTs*/, MVT::v2f32, 3/*#Ops*/, 0, 1, 2,
23536 : // Src: (vector_insert:v2f32 v2f32:v2f32:$vec, f32:f32:$elem, 0:iPTR) - Complexity = 8
23537 : // Dst: (INSERT_SUBREG:v2f32 ?:v2f32:$vec, ?:f32:$elem, sub0:i32)
23538 : /*62644*/ /*Scope*/ 15, /*->62660*/
23539 : /*62645*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23540 : /*62647*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23541 : /*62650*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23542 : 1/*#VTs*/, MVT::v2f32, 3/*#Ops*/, 0, 1, 2,
23543 : // Src: (vector_insert:v2f32 v2f32:v2f32:$vec, f32:f32:$elem, 0:iPTR) - Complexity = 8
23544 : // Dst: (INSERT_SUBREG:v2f32 ?:v2f32:$vec, ?:f32:$elem, sub0:i32)
23545 : /*62660*/ 0, /*End of Scope*/
23546 : /*62661*/ /*SwitchType*/ 15, MVT::v8f32,// ->62678
23547 : /*62663*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23548 : /*62665*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23549 : /*62668*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23550 : 1/*#VTs*/, MVT::v8f32, 3/*#Ops*/, 0, 1, 2,
23551 : // Src: (vector_insert:v8f32 v8f32:v8f32:$vec, f32:f32:$elem, 0:iPTR) - Complexity = 8
23552 : // Dst: (INSERT_SUBREG:v8f32 ?:v8f32:$vec, ?:f32:$elem, sub0:i32)
23553 : /*62678*/ /*SwitchType*/ 15, MVT::v16f32,// ->62695
23554 : /*62680*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23555 : /*62682*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub0,
23556 : /*62685*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23557 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23558 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 0:iPTR) - Complexity = 8
23559 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub0:i32)
23560 : /*62695*/ 0, // EndSwitchType
23561 : /*62696*/ /*Scope*/ 110, /*->62807*/
23562 : /*62697*/ OPC_CheckChild2Integer, 1,
23563 : /*62699*/ OPC_SwitchType /*4 cases */, 34, MVT::v4f32,// ->62736
23564 : /*62702*/ OPC_Scope, 15, /*->62719*/ // 2 children in Scope
23565 : /*62704*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23566 : /*62706*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23567 : /*62709*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23568 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
23569 : // Src: (vector_insert:v4f32 v4f32:v4f32:$vec, f32:f32:$elem, 1:iPTR) - Complexity = 8
23570 : // Dst: (INSERT_SUBREG:v4f32 ?:v4f32:$vec, ?:f32:$elem, sub1:i32)
23571 : /*62719*/ /*Scope*/ 15, /*->62735*/
23572 : /*62720*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23573 : /*62722*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23574 : /*62725*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23575 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
23576 : // Src: (vector_insert:v4f32 v4f32:v4f32:$vec, f32:f32:$elem, 1:iPTR) - Complexity = 8
23577 : // Dst: (INSERT_SUBREG:v4f32 ?:v4f32:$vec, ?:f32:$elem, sub1:i32)
23578 : /*62735*/ 0, /*End of Scope*/
23579 : /*62736*/ /*SwitchType*/ 34, MVT::v2f32,// ->62772
23580 : /*62738*/ OPC_Scope, 15, /*->62755*/ // 2 children in Scope
23581 : /*62740*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23582 : /*62742*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23583 : /*62745*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23584 : 1/*#VTs*/, MVT::v2f32, 3/*#Ops*/, 0, 1, 2,
23585 : // Src: (vector_insert:v2f32 v2f32:v2f32:$vec, f32:f32:$elem, 1:iPTR) - Complexity = 8
23586 : // Dst: (INSERT_SUBREG:v2f32 ?:v2f32:$vec, ?:f32:$elem, sub1:i32)
23587 : /*62755*/ /*Scope*/ 15, /*->62771*/
23588 : /*62756*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23589 : /*62758*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23590 : /*62761*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23591 : 1/*#VTs*/, MVT::v2f32, 3/*#Ops*/, 0, 1, 2,
23592 : // Src: (vector_insert:v2f32 v2f32:v2f32:$vec, f32:f32:$elem, 1:iPTR) - Complexity = 8
23593 : // Dst: (INSERT_SUBREG:v2f32 ?:v2f32:$vec, ?:f32:$elem, sub1:i32)
23594 : /*62771*/ 0, /*End of Scope*/
23595 : /*62772*/ /*SwitchType*/ 15, MVT::v8f32,// ->62789
23596 : /*62774*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23597 : /*62776*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23598 : /*62779*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23599 : 1/*#VTs*/, MVT::v8f32, 3/*#Ops*/, 0, 1, 2,
23600 : // Src: (vector_insert:v8f32 v8f32:v8f32:$vec, f32:f32:$elem, 1:iPTR) - Complexity = 8
23601 : // Dst: (INSERT_SUBREG:v8f32 ?:v8f32:$vec, ?:f32:$elem, sub1:i32)
23602 : /*62789*/ /*SwitchType*/ 15, MVT::v16f32,// ->62806
23603 : /*62791*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23604 : /*62793*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub1,
23605 : /*62796*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23606 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23607 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 1:iPTR) - Complexity = 8
23608 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub1:i32)
23609 : /*62806*/ 0, // EndSwitchType
23610 : /*62807*/ /*Scope*/ 91, /*->62899*/
23611 : /*62808*/ OPC_CheckChild2Integer, 2,
23612 : /*62810*/ OPC_SwitchType /*4 cases */, 34, MVT::v4f32,// ->62847
23613 : /*62813*/ OPC_Scope, 15, /*->62830*/ // 2 children in Scope
23614 : /*62815*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23615 : /*62817*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
23616 : /*62820*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23617 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
23618 : // Src: (vector_insert:v4f32 v4f32:v4f32:$vec, f32:f32:$elem, 2:iPTR) - Complexity = 8
23619 : // Dst: (INSERT_SUBREG:v4f32 ?:v4f32:$vec, ?:f32:$elem, sub2:i32)
23620 : /*62830*/ /*Scope*/ 15, /*->62846*/
23621 : /*62831*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23622 : /*62833*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
23623 : /*62836*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23624 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
23625 : // Src: (vector_insert:v4f32 v4f32:v4f32:$vec, f32:f32:$elem, 2:iPTR) - Complexity = 8
23626 : // Dst: (INSERT_SUBREG:v4f32 ?:v4f32:$vec, ?:f32:$elem, sub2:i32)
23627 : /*62846*/ 0, /*End of Scope*/
23628 : /*62847*/ /*SwitchType*/ 15, MVT::v2f32,// ->62864
23629 : /*62849*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23630 : /*62851*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
23631 : /*62854*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23632 : 1/*#VTs*/, MVT::v2f32, 3/*#Ops*/, 0, 1, 2,
23633 : // Src: (vector_insert:v2f32 v2f32:v2f32:$vec, f32:f32:$elem, 2:iPTR) - Complexity = 8
23634 : // Dst: (INSERT_SUBREG:v2f32 ?:v2f32:$vec, ?:f32:$elem, sub2:i32)
23635 : /*62864*/ /*SwitchType*/ 15, MVT::v8f32,// ->62881
23636 : /*62866*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23637 : /*62868*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
23638 : /*62871*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23639 : 1/*#VTs*/, MVT::v8f32, 3/*#Ops*/, 0, 1, 2,
23640 : // Src: (vector_insert:v8f32 v8f32:v8f32:$vec, f32:f32:$elem, 2:iPTR) - Complexity = 8
23641 : // Dst: (INSERT_SUBREG:v8f32 ?:v8f32:$vec, ?:f32:$elem, sub2:i32)
23642 : /*62881*/ /*SwitchType*/ 15, MVT::v16f32,// ->62898
23643 : /*62883*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23644 : /*62885*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub2,
23645 : /*62888*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23646 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23647 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 2:iPTR) - Complexity = 8
23648 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub2:i32)
23649 : /*62898*/ 0, // EndSwitchType
23650 : /*62899*/ /*Scope*/ 74, /*->62974*/
23651 : /*62900*/ OPC_CheckChild2Integer, 3,
23652 : /*62902*/ OPC_SwitchType /*3 cases */, 34, MVT::v4f32,// ->62939
23653 : /*62905*/ OPC_Scope, 15, /*->62922*/ // 2 children in Scope
23654 : /*62907*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23655 : /*62909*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
23656 : /*62912*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23657 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
23658 : // Src: (vector_insert:v4f32 v4f32:v4f32:$vec, f32:f32:$elem, 3:iPTR) - Complexity = 8
23659 : // Dst: (INSERT_SUBREG:v4f32 ?:v4f32:$vec, ?:f32:$elem, sub3:i32)
23660 : /*62922*/ /*Scope*/ 15, /*->62938*/
23661 : /*62923*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23662 : /*62925*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
23663 : /*62928*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23664 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
23665 : // Src: (vector_insert:v4f32 v4f32:v4f32:$vec, f32:f32:$elem, 3:iPTR) - Complexity = 8
23666 : // Dst: (INSERT_SUBREG:v4f32 ?:v4f32:$vec, ?:f32:$elem, sub3:i32)
23667 : /*62938*/ 0, /*End of Scope*/
23668 : /*62939*/ /*SwitchType*/ 15, MVT::v8f32,// ->62956
23669 : /*62941*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23670 : /*62943*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
23671 : /*62946*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23672 : 1/*#VTs*/, MVT::v8f32, 3/*#Ops*/, 0, 1, 2,
23673 : // Src: (vector_insert:v8f32 v8f32:v8f32:$vec, f32:f32:$elem, 3:iPTR) - Complexity = 8
23674 : // Dst: (INSERT_SUBREG:v8f32 ?:v8f32:$vec, ?:f32:$elem, sub3:i32)
23675 : /*62956*/ /*SwitchType*/ 15, MVT::v16f32,// ->62973
23676 : /*62958*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23677 : /*62960*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub3,
23678 : /*62963*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23679 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23680 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 3:iPTR) - Complexity = 8
23681 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub3:i32)
23682 : /*62973*/ 0, // EndSwitchType
23683 : /*62974*/ /*Scope*/ 38, /*->63013*/
23684 : /*62975*/ OPC_CheckChild2Integer, 4,
23685 : /*62977*/ OPC_SwitchType /*2 cases */, 15, MVT::v8f32,// ->62995
23686 : /*62980*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23687 : /*62982*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub4,
23688 : /*62985*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23689 : 1/*#VTs*/, MVT::v8f32, 3/*#Ops*/, 0, 1, 2,
23690 : // Src: (vector_insert:v8f32 v8f32:v8f32:$vec, f32:f32:$elem, 4:iPTR) - Complexity = 8
23691 : // Dst: (INSERT_SUBREG:v8f32 ?:v8f32:$vec, ?:f32:$elem, sub4:i32)
23692 : /*62995*/ /*SwitchType*/ 15, MVT::v16f32,// ->63012
23693 : /*62997*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23694 : /*62999*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub4,
23695 : /*63002*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23696 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23697 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 4:iPTR) - Complexity = 8
23698 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub4:i32)
23699 : /*63012*/ 0, // EndSwitchType
23700 : /*63013*/ /*Scope*/ 38, /*->63052*/
23701 : /*63014*/ OPC_CheckChild2Integer, 5,
23702 : /*63016*/ OPC_SwitchType /*2 cases */, 15, MVT::v8f32,// ->63034
23703 : /*63019*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23704 : /*63021*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub5,
23705 : /*63024*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23706 : 1/*#VTs*/, MVT::v8f32, 3/*#Ops*/, 0, 1, 2,
23707 : // Src: (vector_insert:v8f32 v8f32:v8f32:$vec, f32:f32:$elem, 5:iPTR) - Complexity = 8
23708 : // Dst: (INSERT_SUBREG:v8f32 ?:v8f32:$vec, ?:f32:$elem, sub5:i32)
23709 : /*63034*/ /*SwitchType*/ 15, MVT::v16f32,// ->63051
23710 : /*63036*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23711 : /*63038*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub5,
23712 : /*63041*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23713 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23714 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 5:iPTR) - Complexity = 8
23715 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub5:i32)
23716 : /*63051*/ 0, // EndSwitchType
23717 : /*63052*/ /*Scope*/ 38, /*->63091*/
23718 : /*63053*/ OPC_CheckChild2Integer, 6,
23719 : /*63055*/ OPC_SwitchType /*2 cases */, 15, MVT::v8f32,// ->63073
23720 : /*63058*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23721 : /*63060*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub6,
23722 : /*63063*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23723 : 1/*#VTs*/, MVT::v8f32, 3/*#Ops*/, 0, 1, 2,
23724 : // Src: (vector_insert:v8f32 v8f32:v8f32:$vec, f32:f32:$elem, 6:iPTR) - Complexity = 8
23725 : // Dst: (INSERT_SUBREG:v8f32 ?:v8f32:$vec, ?:f32:$elem, sub6:i32)
23726 : /*63073*/ /*SwitchType*/ 15, MVT::v16f32,// ->63090
23727 : /*63075*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23728 : /*63077*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub6,
23729 : /*63080*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23730 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23731 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 6:iPTR) - Complexity = 8
23732 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub6:i32)
23733 : /*63090*/ 0, // EndSwitchType
23734 : /*63091*/ /*Scope*/ 38, /*->63130*/
23735 : /*63092*/ OPC_CheckChild2Integer, 7,
23736 : /*63094*/ OPC_SwitchType /*2 cases */, 15, MVT::v8f32,// ->63112
23737 : /*63097*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23738 : /*63099*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub7,
23739 : /*63102*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23740 : 1/*#VTs*/, MVT::v8f32, 3/*#Ops*/, 0, 1, 2,
23741 : // Src: (vector_insert:v8f32 v8f32:v8f32:$vec, f32:f32:$elem, 7:iPTR) - Complexity = 8
23742 : // Dst: (INSERT_SUBREG:v8f32 ?:v8f32:$vec, ?:f32:$elem, sub7:i32)
23743 : /*63112*/ /*SwitchType*/ 15, MVT::v16f32,// ->63129
23744 : /*63114*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23745 : /*63116*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub7,
23746 : /*63119*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23747 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23748 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 7:iPTR) - Complexity = 8
23749 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub7:i32)
23750 : /*63129*/ 0, // EndSwitchType
23751 : /*63130*/ /*Scope*/ 19, /*->63150*/
23752 : /*63131*/ OPC_CheckChild2Integer, 8,
23753 : /*63133*/ OPC_CheckType, MVT::v16f32,
23754 : /*63135*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23755 : /*63137*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub8,
23756 : /*63140*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23757 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23758 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 8:iPTR) - Complexity = 8
23759 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub8:i32)
23760 : /*63150*/ /*Scope*/ 19, /*->63170*/
23761 : /*63151*/ OPC_CheckChild2Integer, 9,
23762 : /*63153*/ OPC_CheckType, MVT::v16f32,
23763 : /*63155*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23764 : /*63157*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub9,
23765 : /*63160*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23766 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23767 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 9:iPTR) - Complexity = 8
23768 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub9:i32)
23769 : /*63170*/ /*Scope*/ 19, /*->63190*/
23770 : /*63171*/ OPC_CheckChild2Integer, 10,
23771 : /*63173*/ OPC_CheckType, MVT::v16f32,
23772 : /*63175*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23773 : /*63177*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub10,
23774 : /*63180*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23775 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23776 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 10:iPTR) - Complexity = 8
23777 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub10:i32)
23778 : /*63190*/ /*Scope*/ 19, /*->63210*/
23779 : /*63191*/ OPC_CheckChild2Integer, 11,
23780 : /*63193*/ OPC_CheckType, MVT::v16f32,
23781 : /*63195*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23782 : /*63197*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub11,
23783 : /*63200*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23784 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23785 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 11:iPTR) - Complexity = 8
23786 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub11:i32)
23787 : /*63210*/ /*Scope*/ 19, /*->63230*/
23788 : /*63211*/ OPC_CheckChild2Integer, 12,
23789 : /*63213*/ OPC_CheckType, MVT::v16f32,
23790 : /*63215*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23791 : /*63217*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub12,
23792 : /*63220*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23793 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23794 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 12:iPTR) - Complexity = 8
23795 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub12:i32)
23796 : /*63230*/ /*Scope*/ 19, /*->63250*/
23797 : /*63231*/ OPC_CheckChild2Integer, 13,
23798 : /*63233*/ OPC_CheckType, MVT::v16f32,
23799 : /*63235*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23800 : /*63237*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub13,
23801 : /*63240*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23802 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23803 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 13:iPTR) - Complexity = 8
23804 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub13:i32)
23805 : /*63250*/ /*Scope*/ 19, /*->63270*/
23806 : /*63251*/ OPC_CheckChild2Integer, 14,
23807 : /*63253*/ OPC_CheckType, MVT::v16f32,
23808 : /*63255*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23809 : /*63257*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub14,
23810 : /*63260*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23811 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23812 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 14:iPTR) - Complexity = 8
23813 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub14:i32)
23814 : /*63270*/ /*Scope*/ 19, /*->63290*/
23815 : /*63271*/ OPC_CheckChild2Integer, 15,
23816 : /*63273*/ OPC_CheckType, MVT::v16f32,
23817 : /*63275*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23818 : /*63277*/ OPC_EmitInteger, MVT::i32, AMDGPU::sub15,
23819 : /*63280*/ OPC_MorphNodeTo, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
23820 : 1/*#VTs*/, MVT::v16f32, 3/*#Ops*/, 0, 1, 2,
23821 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$elem, 15:iPTR) - Complexity = 8
23822 : // Dst: (INSERT_SUBREG:v16f32 ?:v16f32:$vec, ?:f32:$elem, sub15:i32)
23823 : /*63290*/ 0, /*End of Scope*/
23824 : /*63291*/ /*Scope*/ 33, /*->63325*/
23825 : /*63292*/ OPC_RecordChild2, // #2 = $index
23826 : /*63293*/ OPC_CheckChild2Type, MVT::i32,
23827 : /*63295*/ OPC_SwitchType /*2 cases */, 12, MVT::v2f32,// ->63310
23828 : /*63298*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23829 : /*63300*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_INSERT_ELT_V2), 0,
23830 : 1/*#VTs*/, MVT::v2f32, 3/*#Ops*/, 0, 1, 2,
23831 : // Src: (insertelt:v2f32 v2f32:v2f32:$vec, f32:f32:$value, i32:i32:$index) - Complexity = 3
23832 : // Dst: (R600_INSERT_ELT_V2:v2f32 ?:v2f32:$vec, ?:f32:$value, ?:i32:$index)
23833 : /*63310*/ /*SwitchType*/ 12, MVT::v4f32,// ->63324
23834 : /*63312*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23835 : /*63314*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::R600_INSERT_ELT_V4), 0,
23836 : 1/*#VTs*/, MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
23837 : // Src: (insertelt:v4f32 v4f32:v4f32:$vec, f32:f32:$value, i32:i32:$index) - Complexity = 3
23838 : // Dst: (R600_INSERT_ELT_V4:v4f32 ?:v4f32:$vec, ?:f32:$value, ?:i32:$index)
23839 : /*63324*/ 0, // EndSwitchType
23840 : /*63325*/ /*Scope*/ 83, /*->63409*/
23841 : /*63326*/ OPC_CheckChild1Type, MVT::f32,
23842 : /*63328*/ OPC_RecordChild2, // #2 = $idx
23843 : /*63329*/ OPC_CheckChild2Type, MVT::i32,
23844 : /*63331*/ OPC_SwitchType /*4 cases */, 17, MVT::v2f32,// ->63351
23845 : /*63334*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23846 : /*63336*/ OPC_EmitInteger, MVT::i32, 0,
23847 : /*63339*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V2), 0,
23848 : 2/*#VTs*/, MVT::v2f32, MVT::i1, 4/*#Ops*/, 0, 2, 3, 1,
23849 : // Src: (vector_insert:v2f32 v2f32:v2f32:$vec, f32:f32:$val, i32:i32:$idx) - Complexity = 3
23850 : // Dst: (SI_INDIRECT_DST_V2:v2f32:i1 ?:v2f32:$vec, ?:i32:$idx, 0:i32, ?:f32:$val)
23851 : /*63351*/ /*SwitchType*/ 17, MVT::v4f32,// ->63370
23852 : /*63353*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23853 : /*63355*/ OPC_EmitInteger, MVT::i32, 0,
23854 : /*63358*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V4), 0,
23855 : 2/*#VTs*/, MVT::v4f32, MVT::i1, 4/*#Ops*/, 0, 2, 3, 1,
23856 : // Src: (vector_insert:v4f32 v4f32:v4f32:$vec, f32:f32:$val, i32:i32:$idx) - Complexity = 3
23857 : // Dst: (SI_INDIRECT_DST_V4:v4f32:i1 ?:v4f32:$vec, ?:i32:$idx, 0:i32, ?:f32:$val)
23858 : /*63370*/ /*SwitchType*/ 17, MVT::v8f32,// ->63389
23859 : /*63372*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23860 : /*63374*/ OPC_EmitInteger, MVT::i32, 0,
23861 : /*63377*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V8), 0,
23862 : 2/*#VTs*/, MVT::v8f32, MVT::i1, 4/*#Ops*/, 0, 2, 3, 1,
23863 : // Src: (vector_insert:v8f32 v8f32:v8f32:$vec, f32:f32:$val, i32:i32:$idx) - Complexity = 3
23864 : // Dst: (SI_INDIRECT_DST_V8:v8f32:i1 ?:v8f32:$vec, ?:i32:$idx, 0:i32, ?:f32:$val)
23865 : /*63389*/ /*SwitchType*/ 17, MVT::v16f32,// ->63408
23866 : /*63391*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
23867 : /*63393*/ OPC_EmitInteger, MVT::i32, 0,
23868 : /*63396*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::SI_INDIRECT_DST_V16), 0,
23869 : 2/*#VTs*/, MVT::v16f32, MVT::i1, 4/*#Ops*/, 0, 2, 3, 1,
23870 : // Src: (vector_insert:v16f32 v16f32:v16f32:$vec, f32:f32:$val, i32:i32:$idx) - Complexity = 3
23871 : // Dst: (SI_INDIRECT_DST_V16:v16f32:i1 ?:v16f32:$vec, ?:i32:$idx, 0:i32, ?:f32:$val)
23872 : /*63408*/ 0, // EndSwitchType
23873 : /*63409*/ 0, /*End of Scope*/
23874 : /*63410*/ /*SwitchOpcode*/ 45|128,19/*2477*/, TARGET_VAL(AMDGPUISD::TEXTURE_FETCH),// ->65891
23875 : /*63414*/ OPC_Scope, 95|128,1/*223*/, /*->63640*/ // 11 children in Scope
23876 : /*63417*/ OPC_CheckChild0Integer, 0,
23877 : /*63419*/ OPC_CheckChild0Type, MVT::i32,
23878 : /*63421*/ OPC_RecordChild1, // #0 = $SRC_GPR
23879 : /*63422*/ OPC_CheckChild1Type, MVT::v4f32,
23880 : /*63424*/ OPC_RecordChild2, // #1 = $srcx
23881 : /*63425*/ OPC_MoveChild, 2,
23882 : /*63427*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23883 : /*63430*/ OPC_CheckType, MVT::i32,
23884 : /*63432*/ OPC_MoveParent,
23885 : /*63433*/ OPC_RecordChild3, // #2 = $srcy
23886 : /*63434*/ OPC_MoveChild, 3,
23887 : /*63436*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23888 : /*63439*/ OPC_CheckType, MVT::i32,
23889 : /*63441*/ OPC_MoveParent,
23890 : /*63442*/ OPC_RecordChild4, // #3 = $srcz
23891 : /*63443*/ OPC_MoveChild, 4,
23892 : /*63445*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23893 : /*63448*/ OPC_CheckType, MVT::i32,
23894 : /*63450*/ OPC_MoveParent,
23895 : /*63451*/ OPC_RecordChild5, // #4 = $srcw
23896 : /*63452*/ OPC_MoveChild, 5,
23897 : /*63454*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23898 : /*63457*/ OPC_CheckType, MVT::i32,
23899 : /*63459*/ OPC_MoveParent,
23900 : /*63460*/ OPC_RecordChild6, // #5 = $offsetx
23901 : /*63461*/ OPC_MoveChild, 6,
23902 : /*63463*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23903 : /*63466*/ OPC_CheckType, MVT::i32,
23904 : /*63468*/ OPC_MoveParent,
23905 : /*63469*/ OPC_RecordChild7, // #6 = $offsety
23906 : /*63470*/ OPC_MoveChild, 7,
23907 : /*63472*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23908 : /*63475*/ OPC_CheckType, MVT::i32,
23909 : /*63477*/ OPC_MoveParent,
23910 : /*63478*/ OPC_MoveChild, 8,
23911 : /*63480*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23912 : /*63483*/ OPC_RecordNode, // #7 = $offsetz
23913 : /*63484*/ OPC_CheckType, MVT::i32,
23914 : /*63486*/ OPC_MoveParent,
23915 : /*63487*/ OPC_MoveChild, 9,
23916 : /*63489*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23917 : /*63492*/ OPC_RecordNode, // #8 = $DST_SEL_X
23918 : /*63493*/ OPC_CheckType, MVT::i32,
23919 : /*63495*/ OPC_MoveParent,
23920 : /*63496*/ OPC_MoveChild, 10,
23921 : /*63498*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23922 : /*63501*/ OPC_RecordNode, // #9 = $DST_SEL_Y
23923 : /*63502*/ OPC_CheckType, MVT::i32,
23924 : /*63504*/ OPC_MoveParent,
23925 : /*63505*/ OPC_MoveChild, 11,
23926 : /*63507*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23927 : /*63510*/ OPC_RecordNode, // #10 = $DST_SEL_Z
23928 : /*63511*/ OPC_CheckType, MVT::i32,
23929 : /*63513*/ OPC_MoveParent,
23930 : /*63514*/ OPC_MoveChild, 12,
23931 : /*63516*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23932 : /*63519*/ OPC_RecordNode, // #11 = $DST_SEL_W
23933 : /*63520*/ OPC_CheckType, MVT::i32,
23934 : /*63522*/ OPC_MoveParent,
23935 : /*63523*/ OPC_MoveChild, 13,
23936 : /*63525*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23937 : /*63528*/ OPC_RecordNode, // #12 = $RESOURCE_ID
23938 : /*63529*/ OPC_CheckType, MVT::i32,
23939 : /*63531*/ OPC_MoveParent,
23940 : /*63532*/ OPC_MoveChild, 14,
23941 : /*63534*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23942 : /*63537*/ OPC_RecordNode, // #13 = $SAMPLER_ID
23943 : /*63538*/ OPC_CheckType, MVT::i32,
23944 : /*63540*/ OPC_MoveParent,
23945 : /*63541*/ OPC_MoveChild, 15,
23946 : /*63543*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23947 : /*63546*/ OPC_RecordNode, // #14 = $COORD_TYPE_X
23948 : /*63547*/ OPC_CheckType, MVT::i32,
23949 : /*63549*/ OPC_MoveParent,
23950 : /*63550*/ OPC_MoveChild, 16,
23951 : /*63552*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23952 : /*63555*/ OPC_RecordNode, // #15 = $COORD_TYPE_Y
23953 : /*63556*/ OPC_CheckType, MVT::i32,
23954 : /*63558*/ OPC_MoveParent,
23955 : /*63559*/ OPC_MoveChild, 17,
23956 : /*63561*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23957 : /*63564*/ OPC_RecordNode, // #16 = $COORD_TYPE_Z
23958 : /*63565*/ OPC_CheckType, MVT::i32,
23959 : /*63567*/ OPC_MoveParent,
23960 : /*63568*/ OPC_MoveChild, 18,
23961 : /*63570*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23962 : /*63573*/ OPC_RecordNode, // #17 = $COORD_TYPE_W
23963 : /*63574*/ OPC_CheckType, MVT::i32,
23964 : /*63576*/ OPC_MoveParent,
23965 : /*63577*/ OPC_CheckType, MVT::v4f32,
23966 : /*63579*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
23967 : /*63581*/ OPC_EmitConvertToTarget, 1,
23968 : /*63583*/ OPC_EmitConvertToTarget, 2,
23969 : /*63585*/ OPC_EmitConvertToTarget, 3,
23970 : /*63587*/ OPC_EmitConvertToTarget, 4,
23971 : /*63589*/ OPC_EmitConvertToTarget, 5,
23972 : /*63591*/ OPC_EmitConvertToTarget, 6,
23973 : /*63593*/ OPC_EmitConvertToTarget, 7,
23974 : /*63595*/ OPC_EmitConvertToTarget, 8,
23975 : /*63597*/ OPC_EmitConvertToTarget, 9,
23976 : /*63599*/ OPC_EmitConvertToTarget, 10,
23977 : /*63601*/ OPC_EmitConvertToTarget, 11,
23978 : /*63603*/ OPC_EmitConvertToTarget, 12,
23979 : /*63605*/ OPC_EmitConvertToTarget, 13,
23980 : /*63607*/ OPC_EmitConvertToTarget, 14,
23981 : /*63609*/ OPC_EmitConvertToTarget, 15,
23982 : /*63611*/ OPC_EmitConvertToTarget, 16,
23983 : /*63613*/ OPC_EmitConvertToTarget, 17,
23984 : /*63615*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_SAMPLE), 0,
23985 : 1/*#VTs*/, MVT::v4f32, 18/*#Ops*/, 0, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
23986 : // Src: (TEXTURE_FETCH:v4f32 0:i32, v4f32:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W) - Complexity = 59
23987 : // Dst: (TEX_SAMPLE:v4f32 R600_Reg128:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W)
23988 : /*63640*/ /*Scope*/ 95|128,1/*223*/, /*->63865*/
23989 : /*63642*/ OPC_CheckChild0Integer, 1,
23990 : /*63644*/ OPC_CheckChild0Type, MVT::i32,
23991 : /*63646*/ OPC_RecordChild1, // #0 = $SRC_GPR
23992 : /*63647*/ OPC_CheckChild1Type, MVT::v4f32,
23993 : /*63649*/ OPC_RecordChild2, // #1 = $srcx
23994 : /*63650*/ OPC_MoveChild, 2,
23995 : /*63652*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
23996 : /*63655*/ OPC_CheckType, MVT::i32,
23997 : /*63657*/ OPC_MoveParent,
23998 : /*63658*/ OPC_RecordChild3, // #2 = $srcy
23999 : /*63659*/ OPC_MoveChild, 3,
24000 : /*63661*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24001 : /*63664*/ OPC_CheckType, MVT::i32,
24002 : /*63666*/ OPC_MoveParent,
24003 : /*63667*/ OPC_RecordChild4, // #3 = $srcz
24004 : /*63668*/ OPC_MoveChild, 4,
24005 : /*63670*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24006 : /*63673*/ OPC_CheckType, MVT::i32,
24007 : /*63675*/ OPC_MoveParent,
24008 : /*63676*/ OPC_RecordChild5, // #4 = $srcw
24009 : /*63677*/ OPC_MoveChild, 5,
24010 : /*63679*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24011 : /*63682*/ OPC_CheckType, MVT::i32,
24012 : /*63684*/ OPC_MoveParent,
24013 : /*63685*/ OPC_RecordChild6, // #5 = $offsetx
24014 : /*63686*/ OPC_MoveChild, 6,
24015 : /*63688*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24016 : /*63691*/ OPC_CheckType, MVT::i32,
24017 : /*63693*/ OPC_MoveParent,
24018 : /*63694*/ OPC_RecordChild7, // #6 = $offsety
24019 : /*63695*/ OPC_MoveChild, 7,
24020 : /*63697*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24021 : /*63700*/ OPC_CheckType, MVT::i32,
24022 : /*63702*/ OPC_MoveParent,
24023 : /*63703*/ OPC_MoveChild, 8,
24024 : /*63705*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24025 : /*63708*/ OPC_RecordNode, // #7 = $offsetz
24026 : /*63709*/ OPC_CheckType, MVT::i32,
24027 : /*63711*/ OPC_MoveParent,
24028 : /*63712*/ OPC_MoveChild, 9,
24029 : /*63714*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24030 : /*63717*/ OPC_RecordNode, // #8 = $DST_SEL_X
24031 : /*63718*/ OPC_CheckType, MVT::i32,
24032 : /*63720*/ OPC_MoveParent,
24033 : /*63721*/ OPC_MoveChild, 10,
24034 : /*63723*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24035 : /*63726*/ OPC_RecordNode, // #9 = $DST_SEL_Y
24036 : /*63727*/ OPC_CheckType, MVT::i32,
24037 : /*63729*/ OPC_MoveParent,
24038 : /*63730*/ OPC_MoveChild, 11,
24039 : /*63732*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24040 : /*63735*/ OPC_RecordNode, // #10 = $DST_SEL_Z
24041 : /*63736*/ OPC_CheckType, MVT::i32,
24042 : /*63738*/ OPC_MoveParent,
24043 : /*63739*/ OPC_MoveChild, 12,
24044 : /*63741*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24045 : /*63744*/ OPC_RecordNode, // #11 = $DST_SEL_W
24046 : /*63745*/ OPC_CheckType, MVT::i32,
24047 : /*63747*/ OPC_MoveParent,
24048 : /*63748*/ OPC_MoveChild, 13,
24049 : /*63750*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24050 : /*63753*/ OPC_RecordNode, // #12 = $RESOURCE_ID
24051 : /*63754*/ OPC_CheckType, MVT::i32,
24052 : /*63756*/ OPC_MoveParent,
24053 : /*63757*/ OPC_MoveChild, 14,
24054 : /*63759*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24055 : /*63762*/ OPC_RecordNode, // #13 = $SAMPLER_ID
24056 : /*63763*/ OPC_CheckType, MVT::i32,
24057 : /*63765*/ OPC_MoveParent,
24058 : /*63766*/ OPC_MoveChild, 15,
24059 : /*63768*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24060 : /*63771*/ OPC_RecordNode, // #14 = $COORD_TYPE_X
24061 : /*63772*/ OPC_CheckType, MVT::i32,
24062 : /*63774*/ OPC_MoveParent,
24063 : /*63775*/ OPC_MoveChild, 16,
24064 : /*63777*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24065 : /*63780*/ OPC_RecordNode, // #15 = $COORD_TYPE_Y
24066 : /*63781*/ OPC_CheckType, MVT::i32,
24067 : /*63783*/ OPC_MoveParent,
24068 : /*63784*/ OPC_MoveChild, 17,
24069 : /*63786*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24070 : /*63789*/ OPC_RecordNode, // #16 = $COORD_TYPE_Z
24071 : /*63790*/ OPC_CheckType, MVT::i32,
24072 : /*63792*/ OPC_MoveParent,
24073 : /*63793*/ OPC_MoveChild, 18,
24074 : /*63795*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24075 : /*63798*/ OPC_RecordNode, // #17 = $COORD_TYPE_W
24076 : /*63799*/ OPC_CheckType, MVT::i32,
24077 : /*63801*/ OPC_MoveParent,
24078 : /*63802*/ OPC_CheckType, MVT::v4f32,
24079 : /*63804*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
24080 : /*63806*/ OPC_EmitConvertToTarget, 1,
24081 : /*63808*/ OPC_EmitConvertToTarget, 2,
24082 : /*63810*/ OPC_EmitConvertToTarget, 3,
24083 : /*63812*/ OPC_EmitConvertToTarget, 4,
24084 : /*63814*/ OPC_EmitConvertToTarget, 5,
24085 : /*63816*/ OPC_EmitConvertToTarget, 6,
24086 : /*63818*/ OPC_EmitConvertToTarget, 7,
24087 : /*63820*/ OPC_EmitConvertToTarget, 8,
24088 : /*63822*/ OPC_EmitConvertToTarget, 9,
24089 : /*63824*/ OPC_EmitConvertToTarget, 10,
24090 : /*63826*/ OPC_EmitConvertToTarget, 11,
24091 : /*63828*/ OPC_EmitConvertToTarget, 12,
24092 : /*63830*/ OPC_EmitConvertToTarget, 13,
24093 : /*63832*/ OPC_EmitConvertToTarget, 14,
24094 : /*63834*/ OPC_EmitConvertToTarget, 15,
24095 : /*63836*/ OPC_EmitConvertToTarget, 16,
24096 : /*63838*/ OPC_EmitConvertToTarget, 17,
24097 : /*63840*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_SAMPLE_C), 0,
24098 : 1/*#VTs*/, MVT::v4f32, 18/*#Ops*/, 0, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
24099 : // Src: (TEXTURE_FETCH:v4f32 1:i32, v4f32:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W) - Complexity = 59
24100 : // Dst: (TEX_SAMPLE_C:v4f32 R600_Reg128:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W)
24101 : /*63865*/ /*Scope*/ 95|128,1/*223*/, /*->64090*/
24102 : /*63867*/ OPC_CheckChild0Integer, 2,
24103 : /*63869*/ OPC_CheckChild0Type, MVT::i32,
24104 : /*63871*/ OPC_RecordChild1, // #0 = $SRC_GPR
24105 : /*63872*/ OPC_CheckChild1Type, MVT::v4f32,
24106 : /*63874*/ OPC_RecordChild2, // #1 = $srcx
24107 : /*63875*/ OPC_MoveChild, 2,
24108 : /*63877*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24109 : /*63880*/ OPC_CheckType, MVT::i32,
24110 : /*63882*/ OPC_MoveParent,
24111 : /*63883*/ OPC_RecordChild3, // #2 = $srcy
24112 : /*63884*/ OPC_MoveChild, 3,
24113 : /*63886*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24114 : /*63889*/ OPC_CheckType, MVT::i32,
24115 : /*63891*/ OPC_MoveParent,
24116 : /*63892*/ OPC_RecordChild4, // #3 = $srcz
24117 : /*63893*/ OPC_MoveChild, 4,
24118 : /*63895*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24119 : /*63898*/ OPC_CheckType, MVT::i32,
24120 : /*63900*/ OPC_MoveParent,
24121 : /*63901*/ OPC_RecordChild5, // #4 = $srcw
24122 : /*63902*/ OPC_MoveChild, 5,
24123 : /*63904*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24124 : /*63907*/ OPC_CheckType, MVT::i32,
24125 : /*63909*/ OPC_MoveParent,
24126 : /*63910*/ OPC_RecordChild6, // #5 = $offsetx
24127 : /*63911*/ OPC_MoveChild, 6,
24128 : /*63913*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24129 : /*63916*/ OPC_CheckType, MVT::i32,
24130 : /*63918*/ OPC_MoveParent,
24131 : /*63919*/ OPC_RecordChild7, // #6 = $offsety
24132 : /*63920*/ OPC_MoveChild, 7,
24133 : /*63922*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24134 : /*63925*/ OPC_CheckType, MVT::i32,
24135 : /*63927*/ OPC_MoveParent,
24136 : /*63928*/ OPC_MoveChild, 8,
24137 : /*63930*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24138 : /*63933*/ OPC_RecordNode, // #7 = $offsetz
24139 : /*63934*/ OPC_CheckType, MVT::i32,
24140 : /*63936*/ OPC_MoveParent,
24141 : /*63937*/ OPC_MoveChild, 9,
24142 : /*63939*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24143 : /*63942*/ OPC_RecordNode, // #8 = $DST_SEL_X
24144 : /*63943*/ OPC_CheckType, MVT::i32,
24145 : /*63945*/ OPC_MoveParent,
24146 : /*63946*/ OPC_MoveChild, 10,
24147 : /*63948*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24148 : /*63951*/ OPC_RecordNode, // #9 = $DST_SEL_Y
24149 : /*63952*/ OPC_CheckType, MVT::i32,
24150 : /*63954*/ OPC_MoveParent,
24151 : /*63955*/ OPC_MoveChild, 11,
24152 : /*63957*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24153 : /*63960*/ OPC_RecordNode, // #10 = $DST_SEL_Z
24154 : /*63961*/ OPC_CheckType, MVT::i32,
24155 : /*63963*/ OPC_MoveParent,
24156 : /*63964*/ OPC_MoveChild, 12,
24157 : /*63966*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24158 : /*63969*/ OPC_RecordNode, // #11 = $DST_SEL_W
24159 : /*63970*/ OPC_CheckType, MVT::i32,
24160 : /*63972*/ OPC_MoveParent,
24161 : /*63973*/ OPC_MoveChild, 13,
24162 : /*63975*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24163 : /*63978*/ OPC_RecordNode, // #12 = $RESOURCE_ID
24164 : /*63979*/ OPC_CheckType, MVT::i32,
24165 : /*63981*/ OPC_MoveParent,
24166 : /*63982*/ OPC_MoveChild, 14,
24167 : /*63984*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24168 : /*63987*/ OPC_RecordNode, // #13 = $SAMPLER_ID
24169 : /*63988*/ OPC_CheckType, MVT::i32,
24170 : /*63990*/ OPC_MoveParent,
24171 : /*63991*/ OPC_MoveChild, 15,
24172 : /*63993*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24173 : /*63996*/ OPC_RecordNode, // #14 = $COORD_TYPE_X
24174 : /*63997*/ OPC_CheckType, MVT::i32,
24175 : /*63999*/ OPC_MoveParent,
24176 : /*64000*/ OPC_MoveChild, 16,
24177 : /*64002*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24178 : /*64005*/ OPC_RecordNode, // #15 = $COORD_TYPE_Y
24179 : /*64006*/ OPC_CheckType, MVT::i32,
24180 : /*64008*/ OPC_MoveParent,
24181 : /*64009*/ OPC_MoveChild, 17,
24182 : /*64011*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24183 : /*64014*/ OPC_RecordNode, // #16 = $COORD_TYPE_Z
24184 : /*64015*/ OPC_CheckType, MVT::i32,
24185 : /*64017*/ OPC_MoveParent,
24186 : /*64018*/ OPC_MoveChild, 18,
24187 : /*64020*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24188 : /*64023*/ OPC_RecordNode, // #17 = $COORD_TYPE_W
24189 : /*64024*/ OPC_CheckType, MVT::i32,
24190 : /*64026*/ OPC_MoveParent,
24191 : /*64027*/ OPC_CheckType, MVT::v4f32,
24192 : /*64029*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
24193 : /*64031*/ OPC_EmitConvertToTarget, 1,
24194 : /*64033*/ OPC_EmitConvertToTarget, 2,
24195 : /*64035*/ OPC_EmitConvertToTarget, 3,
24196 : /*64037*/ OPC_EmitConvertToTarget, 4,
24197 : /*64039*/ OPC_EmitConvertToTarget, 5,
24198 : /*64041*/ OPC_EmitConvertToTarget, 6,
24199 : /*64043*/ OPC_EmitConvertToTarget, 7,
24200 : /*64045*/ OPC_EmitConvertToTarget, 8,
24201 : /*64047*/ OPC_EmitConvertToTarget, 9,
24202 : /*64049*/ OPC_EmitConvertToTarget, 10,
24203 : /*64051*/ OPC_EmitConvertToTarget, 11,
24204 : /*64053*/ OPC_EmitConvertToTarget, 12,
24205 : /*64055*/ OPC_EmitConvertToTarget, 13,
24206 : /*64057*/ OPC_EmitConvertToTarget, 14,
24207 : /*64059*/ OPC_EmitConvertToTarget, 15,
24208 : /*64061*/ OPC_EmitConvertToTarget, 16,
24209 : /*64063*/ OPC_EmitConvertToTarget, 17,
24210 : /*64065*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_SAMPLE_L), 0,
24211 : 1/*#VTs*/, MVT::v4f32, 18/*#Ops*/, 0, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
24212 : // Src: (TEXTURE_FETCH:v4f32 2:i32, v4f32:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W) - Complexity = 59
24213 : // Dst: (TEX_SAMPLE_L:v4f32 R600_Reg128:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W)
24214 : /*64090*/ /*Scope*/ 95|128,1/*223*/, /*->64315*/
24215 : /*64092*/ OPC_CheckChild0Integer, 3,
24216 : /*64094*/ OPC_CheckChild0Type, MVT::i32,
24217 : /*64096*/ OPC_RecordChild1, // #0 = $SRC_GPR
24218 : /*64097*/ OPC_CheckChild1Type, MVT::v4f32,
24219 : /*64099*/ OPC_RecordChild2, // #1 = $srcx
24220 : /*64100*/ OPC_MoveChild, 2,
24221 : /*64102*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24222 : /*64105*/ OPC_CheckType, MVT::i32,
24223 : /*64107*/ OPC_MoveParent,
24224 : /*64108*/ OPC_RecordChild3, // #2 = $srcy
24225 : /*64109*/ OPC_MoveChild, 3,
24226 : /*64111*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24227 : /*64114*/ OPC_CheckType, MVT::i32,
24228 : /*64116*/ OPC_MoveParent,
24229 : /*64117*/ OPC_RecordChild4, // #3 = $srcz
24230 : /*64118*/ OPC_MoveChild, 4,
24231 : /*64120*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24232 : /*64123*/ OPC_CheckType, MVT::i32,
24233 : /*64125*/ OPC_MoveParent,
24234 : /*64126*/ OPC_RecordChild5, // #4 = $srcw
24235 : /*64127*/ OPC_MoveChild, 5,
24236 : /*64129*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24237 : /*64132*/ OPC_CheckType, MVT::i32,
24238 : /*64134*/ OPC_MoveParent,
24239 : /*64135*/ OPC_RecordChild6, // #5 = $offsetx
24240 : /*64136*/ OPC_MoveChild, 6,
24241 : /*64138*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24242 : /*64141*/ OPC_CheckType, MVT::i32,
24243 : /*64143*/ OPC_MoveParent,
24244 : /*64144*/ OPC_RecordChild7, // #6 = $offsety
24245 : /*64145*/ OPC_MoveChild, 7,
24246 : /*64147*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24247 : /*64150*/ OPC_CheckType, MVT::i32,
24248 : /*64152*/ OPC_MoveParent,
24249 : /*64153*/ OPC_MoveChild, 8,
24250 : /*64155*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24251 : /*64158*/ OPC_RecordNode, // #7 = $offsetz
24252 : /*64159*/ OPC_CheckType, MVT::i32,
24253 : /*64161*/ OPC_MoveParent,
24254 : /*64162*/ OPC_MoveChild, 9,
24255 : /*64164*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24256 : /*64167*/ OPC_RecordNode, // #8 = $DST_SEL_X
24257 : /*64168*/ OPC_CheckType, MVT::i32,
24258 : /*64170*/ OPC_MoveParent,
24259 : /*64171*/ OPC_MoveChild, 10,
24260 : /*64173*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24261 : /*64176*/ OPC_RecordNode, // #9 = $DST_SEL_Y
24262 : /*64177*/ OPC_CheckType, MVT::i32,
24263 : /*64179*/ OPC_MoveParent,
24264 : /*64180*/ OPC_MoveChild, 11,
24265 : /*64182*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24266 : /*64185*/ OPC_RecordNode, // #10 = $DST_SEL_Z
24267 : /*64186*/ OPC_CheckType, MVT::i32,
24268 : /*64188*/ OPC_MoveParent,
24269 : /*64189*/ OPC_MoveChild, 12,
24270 : /*64191*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24271 : /*64194*/ OPC_RecordNode, // #11 = $DST_SEL_W
24272 : /*64195*/ OPC_CheckType, MVT::i32,
24273 : /*64197*/ OPC_MoveParent,
24274 : /*64198*/ OPC_MoveChild, 13,
24275 : /*64200*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24276 : /*64203*/ OPC_RecordNode, // #12 = $RESOURCE_ID
24277 : /*64204*/ OPC_CheckType, MVT::i32,
24278 : /*64206*/ OPC_MoveParent,
24279 : /*64207*/ OPC_MoveChild, 14,
24280 : /*64209*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24281 : /*64212*/ OPC_RecordNode, // #13 = $SAMPLER_ID
24282 : /*64213*/ OPC_CheckType, MVT::i32,
24283 : /*64215*/ OPC_MoveParent,
24284 : /*64216*/ OPC_MoveChild, 15,
24285 : /*64218*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24286 : /*64221*/ OPC_RecordNode, // #14 = $COORD_TYPE_X
24287 : /*64222*/ OPC_CheckType, MVT::i32,
24288 : /*64224*/ OPC_MoveParent,
24289 : /*64225*/ OPC_MoveChild, 16,
24290 : /*64227*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24291 : /*64230*/ OPC_RecordNode, // #15 = $COORD_TYPE_Y
24292 : /*64231*/ OPC_CheckType, MVT::i32,
24293 : /*64233*/ OPC_MoveParent,
24294 : /*64234*/ OPC_MoveChild, 17,
24295 : /*64236*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24296 : /*64239*/ OPC_RecordNode, // #16 = $COORD_TYPE_Z
24297 : /*64240*/ OPC_CheckType, MVT::i32,
24298 : /*64242*/ OPC_MoveParent,
24299 : /*64243*/ OPC_MoveChild, 18,
24300 : /*64245*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24301 : /*64248*/ OPC_RecordNode, // #17 = $COORD_TYPE_W
24302 : /*64249*/ OPC_CheckType, MVT::i32,
24303 : /*64251*/ OPC_MoveParent,
24304 : /*64252*/ OPC_CheckType, MVT::v4f32,
24305 : /*64254*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
24306 : /*64256*/ OPC_EmitConvertToTarget, 1,
24307 : /*64258*/ OPC_EmitConvertToTarget, 2,
24308 : /*64260*/ OPC_EmitConvertToTarget, 3,
24309 : /*64262*/ OPC_EmitConvertToTarget, 4,
24310 : /*64264*/ OPC_EmitConvertToTarget, 5,
24311 : /*64266*/ OPC_EmitConvertToTarget, 6,
24312 : /*64268*/ OPC_EmitConvertToTarget, 7,
24313 : /*64270*/ OPC_EmitConvertToTarget, 8,
24314 : /*64272*/ OPC_EmitConvertToTarget, 9,
24315 : /*64274*/ OPC_EmitConvertToTarget, 10,
24316 : /*64276*/ OPC_EmitConvertToTarget, 11,
24317 : /*64278*/ OPC_EmitConvertToTarget, 12,
24318 : /*64280*/ OPC_EmitConvertToTarget, 13,
24319 : /*64282*/ OPC_EmitConvertToTarget, 14,
24320 : /*64284*/ OPC_EmitConvertToTarget, 15,
24321 : /*64286*/ OPC_EmitConvertToTarget, 16,
24322 : /*64288*/ OPC_EmitConvertToTarget, 17,
24323 : /*64290*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_SAMPLE_C_L), 0,
24324 : 1/*#VTs*/, MVT::v4f32, 18/*#Ops*/, 0, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
24325 : // Src: (TEXTURE_FETCH:v4f32 3:i32, v4f32:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W) - Complexity = 59
24326 : // Dst: (TEX_SAMPLE_C_L:v4f32 R600_Reg128:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W)
24327 : /*64315*/ /*Scope*/ 95|128,1/*223*/, /*->64540*/
24328 : /*64317*/ OPC_CheckChild0Integer, 4,
24329 : /*64319*/ OPC_CheckChild0Type, MVT::i32,
24330 : /*64321*/ OPC_RecordChild1, // #0 = $SRC_GPR
24331 : /*64322*/ OPC_CheckChild1Type, MVT::v4f32,
24332 : /*64324*/ OPC_RecordChild2, // #1 = $srcx
24333 : /*64325*/ OPC_MoveChild, 2,
24334 : /*64327*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24335 : /*64330*/ OPC_CheckType, MVT::i32,
24336 : /*64332*/ OPC_MoveParent,
24337 : /*64333*/ OPC_RecordChild3, // #2 = $srcy
24338 : /*64334*/ OPC_MoveChild, 3,
24339 : /*64336*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24340 : /*64339*/ OPC_CheckType, MVT::i32,
24341 : /*64341*/ OPC_MoveParent,
24342 : /*64342*/ OPC_RecordChild4, // #3 = $srcz
24343 : /*64343*/ OPC_MoveChild, 4,
24344 : /*64345*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24345 : /*64348*/ OPC_CheckType, MVT::i32,
24346 : /*64350*/ OPC_MoveParent,
24347 : /*64351*/ OPC_RecordChild5, // #4 = $srcw
24348 : /*64352*/ OPC_MoveChild, 5,
24349 : /*64354*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24350 : /*64357*/ OPC_CheckType, MVT::i32,
24351 : /*64359*/ OPC_MoveParent,
24352 : /*64360*/ OPC_RecordChild6, // #5 = $offsetx
24353 : /*64361*/ OPC_MoveChild, 6,
24354 : /*64363*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24355 : /*64366*/ OPC_CheckType, MVT::i32,
24356 : /*64368*/ OPC_MoveParent,
24357 : /*64369*/ OPC_RecordChild7, // #6 = $offsety
24358 : /*64370*/ OPC_MoveChild, 7,
24359 : /*64372*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24360 : /*64375*/ OPC_CheckType, MVT::i32,
24361 : /*64377*/ OPC_MoveParent,
24362 : /*64378*/ OPC_MoveChild, 8,
24363 : /*64380*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24364 : /*64383*/ OPC_RecordNode, // #7 = $offsetz
24365 : /*64384*/ OPC_CheckType, MVT::i32,
24366 : /*64386*/ OPC_MoveParent,
24367 : /*64387*/ OPC_MoveChild, 9,
24368 : /*64389*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24369 : /*64392*/ OPC_RecordNode, // #8 = $DST_SEL_X
24370 : /*64393*/ OPC_CheckType, MVT::i32,
24371 : /*64395*/ OPC_MoveParent,
24372 : /*64396*/ OPC_MoveChild, 10,
24373 : /*64398*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24374 : /*64401*/ OPC_RecordNode, // #9 = $DST_SEL_Y
24375 : /*64402*/ OPC_CheckType, MVT::i32,
24376 : /*64404*/ OPC_MoveParent,
24377 : /*64405*/ OPC_MoveChild, 11,
24378 : /*64407*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24379 : /*64410*/ OPC_RecordNode, // #10 = $DST_SEL_Z
24380 : /*64411*/ OPC_CheckType, MVT::i32,
24381 : /*64413*/ OPC_MoveParent,
24382 : /*64414*/ OPC_MoveChild, 12,
24383 : /*64416*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24384 : /*64419*/ OPC_RecordNode, // #11 = $DST_SEL_W
24385 : /*64420*/ OPC_CheckType, MVT::i32,
24386 : /*64422*/ OPC_MoveParent,
24387 : /*64423*/ OPC_MoveChild, 13,
24388 : /*64425*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24389 : /*64428*/ OPC_RecordNode, // #12 = $RESOURCE_ID
24390 : /*64429*/ OPC_CheckType, MVT::i32,
24391 : /*64431*/ OPC_MoveParent,
24392 : /*64432*/ OPC_MoveChild, 14,
24393 : /*64434*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24394 : /*64437*/ OPC_RecordNode, // #13 = $SAMPLER_ID
24395 : /*64438*/ OPC_CheckType, MVT::i32,
24396 : /*64440*/ OPC_MoveParent,
24397 : /*64441*/ OPC_MoveChild, 15,
24398 : /*64443*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24399 : /*64446*/ OPC_RecordNode, // #14 = $COORD_TYPE_X
24400 : /*64447*/ OPC_CheckType, MVT::i32,
24401 : /*64449*/ OPC_MoveParent,
24402 : /*64450*/ OPC_MoveChild, 16,
24403 : /*64452*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24404 : /*64455*/ OPC_RecordNode, // #15 = $COORD_TYPE_Y
24405 : /*64456*/ OPC_CheckType, MVT::i32,
24406 : /*64458*/ OPC_MoveParent,
24407 : /*64459*/ OPC_MoveChild, 17,
24408 : /*64461*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24409 : /*64464*/ OPC_RecordNode, // #16 = $COORD_TYPE_Z
24410 : /*64465*/ OPC_CheckType, MVT::i32,
24411 : /*64467*/ OPC_MoveParent,
24412 : /*64468*/ OPC_MoveChild, 18,
24413 : /*64470*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24414 : /*64473*/ OPC_RecordNode, // #17 = $COORD_TYPE_W
24415 : /*64474*/ OPC_CheckType, MVT::i32,
24416 : /*64476*/ OPC_MoveParent,
24417 : /*64477*/ OPC_CheckType, MVT::v4f32,
24418 : /*64479*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
24419 : /*64481*/ OPC_EmitConvertToTarget, 1,
24420 : /*64483*/ OPC_EmitConvertToTarget, 2,
24421 : /*64485*/ OPC_EmitConvertToTarget, 3,
24422 : /*64487*/ OPC_EmitConvertToTarget, 4,
24423 : /*64489*/ OPC_EmitConvertToTarget, 5,
24424 : /*64491*/ OPC_EmitConvertToTarget, 6,
24425 : /*64493*/ OPC_EmitConvertToTarget, 7,
24426 : /*64495*/ OPC_EmitConvertToTarget, 8,
24427 : /*64497*/ OPC_EmitConvertToTarget, 9,
24428 : /*64499*/ OPC_EmitConvertToTarget, 10,
24429 : /*64501*/ OPC_EmitConvertToTarget, 11,
24430 : /*64503*/ OPC_EmitConvertToTarget, 12,
24431 : /*64505*/ OPC_EmitConvertToTarget, 13,
24432 : /*64507*/ OPC_EmitConvertToTarget, 14,
24433 : /*64509*/ OPC_EmitConvertToTarget, 15,
24434 : /*64511*/ OPC_EmitConvertToTarget, 16,
24435 : /*64513*/ OPC_EmitConvertToTarget, 17,
24436 : /*64515*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_SAMPLE_LB), 0,
24437 : 1/*#VTs*/, MVT::v4f32, 18/*#Ops*/, 0, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
24438 : // Src: (TEXTURE_FETCH:v4f32 4:i32, v4f32:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W) - Complexity = 59
24439 : // Dst: (TEX_SAMPLE_LB:v4f32 R600_Reg128:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W)
24440 : /*64540*/ /*Scope*/ 95|128,1/*223*/, /*->64765*/
24441 : /*64542*/ OPC_CheckChild0Integer, 5,
24442 : /*64544*/ OPC_CheckChild0Type, MVT::i32,
24443 : /*64546*/ OPC_RecordChild1, // #0 = $SRC_GPR
24444 : /*64547*/ OPC_CheckChild1Type, MVT::v4f32,
24445 : /*64549*/ OPC_RecordChild2, // #1 = $srcx
24446 : /*64550*/ OPC_MoveChild, 2,
24447 : /*64552*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24448 : /*64555*/ OPC_CheckType, MVT::i32,
24449 : /*64557*/ OPC_MoveParent,
24450 : /*64558*/ OPC_RecordChild3, // #2 = $srcy
24451 : /*64559*/ OPC_MoveChild, 3,
24452 : /*64561*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24453 : /*64564*/ OPC_CheckType, MVT::i32,
24454 : /*64566*/ OPC_MoveParent,
24455 : /*64567*/ OPC_RecordChild4, // #3 = $srcz
24456 : /*64568*/ OPC_MoveChild, 4,
24457 : /*64570*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24458 : /*64573*/ OPC_CheckType, MVT::i32,
24459 : /*64575*/ OPC_MoveParent,
24460 : /*64576*/ OPC_RecordChild5, // #4 = $srcw
24461 : /*64577*/ OPC_MoveChild, 5,
24462 : /*64579*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24463 : /*64582*/ OPC_CheckType, MVT::i32,
24464 : /*64584*/ OPC_MoveParent,
24465 : /*64585*/ OPC_RecordChild6, // #5 = $offsetx
24466 : /*64586*/ OPC_MoveChild, 6,
24467 : /*64588*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24468 : /*64591*/ OPC_CheckType, MVT::i32,
24469 : /*64593*/ OPC_MoveParent,
24470 : /*64594*/ OPC_RecordChild7, // #6 = $offsety
24471 : /*64595*/ OPC_MoveChild, 7,
24472 : /*64597*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24473 : /*64600*/ OPC_CheckType, MVT::i32,
24474 : /*64602*/ OPC_MoveParent,
24475 : /*64603*/ OPC_MoveChild, 8,
24476 : /*64605*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24477 : /*64608*/ OPC_RecordNode, // #7 = $offsetz
24478 : /*64609*/ OPC_CheckType, MVT::i32,
24479 : /*64611*/ OPC_MoveParent,
24480 : /*64612*/ OPC_MoveChild, 9,
24481 : /*64614*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24482 : /*64617*/ OPC_RecordNode, // #8 = $DST_SEL_X
24483 : /*64618*/ OPC_CheckType, MVT::i32,
24484 : /*64620*/ OPC_MoveParent,
24485 : /*64621*/ OPC_MoveChild, 10,
24486 : /*64623*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24487 : /*64626*/ OPC_RecordNode, // #9 = $DST_SEL_Y
24488 : /*64627*/ OPC_CheckType, MVT::i32,
24489 : /*64629*/ OPC_MoveParent,
24490 : /*64630*/ OPC_MoveChild, 11,
24491 : /*64632*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24492 : /*64635*/ OPC_RecordNode, // #10 = $DST_SEL_Z
24493 : /*64636*/ OPC_CheckType, MVT::i32,
24494 : /*64638*/ OPC_MoveParent,
24495 : /*64639*/ OPC_MoveChild, 12,
24496 : /*64641*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24497 : /*64644*/ OPC_RecordNode, // #11 = $DST_SEL_W
24498 : /*64645*/ OPC_CheckType, MVT::i32,
24499 : /*64647*/ OPC_MoveParent,
24500 : /*64648*/ OPC_MoveChild, 13,
24501 : /*64650*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24502 : /*64653*/ OPC_RecordNode, // #12 = $RESOURCE_ID
24503 : /*64654*/ OPC_CheckType, MVT::i32,
24504 : /*64656*/ OPC_MoveParent,
24505 : /*64657*/ OPC_MoveChild, 14,
24506 : /*64659*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24507 : /*64662*/ OPC_RecordNode, // #13 = $SAMPLER_ID
24508 : /*64663*/ OPC_CheckType, MVT::i32,
24509 : /*64665*/ OPC_MoveParent,
24510 : /*64666*/ OPC_MoveChild, 15,
24511 : /*64668*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24512 : /*64671*/ OPC_RecordNode, // #14 = $COORD_TYPE_X
24513 : /*64672*/ OPC_CheckType, MVT::i32,
24514 : /*64674*/ OPC_MoveParent,
24515 : /*64675*/ OPC_MoveChild, 16,
24516 : /*64677*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24517 : /*64680*/ OPC_RecordNode, // #15 = $COORD_TYPE_Y
24518 : /*64681*/ OPC_CheckType, MVT::i32,
24519 : /*64683*/ OPC_MoveParent,
24520 : /*64684*/ OPC_MoveChild, 17,
24521 : /*64686*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24522 : /*64689*/ OPC_RecordNode, // #16 = $COORD_TYPE_Z
24523 : /*64690*/ OPC_CheckType, MVT::i32,
24524 : /*64692*/ OPC_MoveParent,
24525 : /*64693*/ OPC_MoveChild, 18,
24526 : /*64695*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24527 : /*64698*/ OPC_RecordNode, // #17 = $COORD_TYPE_W
24528 : /*64699*/ OPC_CheckType, MVT::i32,
24529 : /*64701*/ OPC_MoveParent,
24530 : /*64702*/ OPC_CheckType, MVT::v4f32,
24531 : /*64704*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
24532 : /*64706*/ OPC_EmitConvertToTarget, 1,
24533 : /*64708*/ OPC_EmitConvertToTarget, 2,
24534 : /*64710*/ OPC_EmitConvertToTarget, 3,
24535 : /*64712*/ OPC_EmitConvertToTarget, 4,
24536 : /*64714*/ OPC_EmitConvertToTarget, 5,
24537 : /*64716*/ OPC_EmitConvertToTarget, 6,
24538 : /*64718*/ OPC_EmitConvertToTarget, 7,
24539 : /*64720*/ OPC_EmitConvertToTarget, 8,
24540 : /*64722*/ OPC_EmitConvertToTarget, 9,
24541 : /*64724*/ OPC_EmitConvertToTarget, 10,
24542 : /*64726*/ OPC_EmitConvertToTarget, 11,
24543 : /*64728*/ OPC_EmitConvertToTarget, 12,
24544 : /*64730*/ OPC_EmitConvertToTarget, 13,
24545 : /*64732*/ OPC_EmitConvertToTarget, 14,
24546 : /*64734*/ OPC_EmitConvertToTarget, 15,
24547 : /*64736*/ OPC_EmitConvertToTarget, 16,
24548 : /*64738*/ OPC_EmitConvertToTarget, 17,
24549 : /*64740*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_SAMPLE_C_LB), 0,
24550 : 1/*#VTs*/, MVT::v4f32, 18/*#Ops*/, 0, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
24551 : // Src: (TEXTURE_FETCH:v4f32 5:i32, v4f32:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W) - Complexity = 59
24552 : // Dst: (TEX_SAMPLE_C_LB:v4f32 R600_Reg128:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W)
24553 : /*64765*/ /*Scope*/ 95|128,1/*223*/, /*->64990*/
24554 : /*64767*/ OPC_CheckChild0Integer, 6,
24555 : /*64769*/ OPC_CheckChild0Type, MVT::i32,
24556 : /*64771*/ OPC_RecordChild1, // #0 = $SRC_GPR
24557 : /*64772*/ OPC_CheckChild1Type, MVT::v4i32,
24558 : /*64774*/ OPC_RecordChild2, // #1 = $srcx
24559 : /*64775*/ OPC_MoveChild, 2,
24560 : /*64777*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24561 : /*64780*/ OPC_CheckType, MVT::i32,
24562 : /*64782*/ OPC_MoveParent,
24563 : /*64783*/ OPC_RecordChild3, // #2 = $srcy
24564 : /*64784*/ OPC_MoveChild, 3,
24565 : /*64786*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24566 : /*64789*/ OPC_CheckType, MVT::i32,
24567 : /*64791*/ OPC_MoveParent,
24568 : /*64792*/ OPC_RecordChild4, // #3 = $srcz
24569 : /*64793*/ OPC_MoveChild, 4,
24570 : /*64795*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24571 : /*64798*/ OPC_CheckType, MVT::i32,
24572 : /*64800*/ OPC_MoveParent,
24573 : /*64801*/ OPC_RecordChild5, // #4 = $srcw
24574 : /*64802*/ OPC_MoveChild, 5,
24575 : /*64804*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24576 : /*64807*/ OPC_CheckType, MVT::i32,
24577 : /*64809*/ OPC_MoveParent,
24578 : /*64810*/ OPC_RecordChild6, // #5 = $offsetx
24579 : /*64811*/ OPC_MoveChild, 6,
24580 : /*64813*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24581 : /*64816*/ OPC_CheckType, MVT::i32,
24582 : /*64818*/ OPC_MoveParent,
24583 : /*64819*/ OPC_RecordChild7, // #6 = $offsety
24584 : /*64820*/ OPC_MoveChild, 7,
24585 : /*64822*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24586 : /*64825*/ OPC_CheckType, MVT::i32,
24587 : /*64827*/ OPC_MoveParent,
24588 : /*64828*/ OPC_MoveChild, 8,
24589 : /*64830*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24590 : /*64833*/ OPC_RecordNode, // #7 = $offsetz
24591 : /*64834*/ OPC_CheckType, MVT::i32,
24592 : /*64836*/ OPC_MoveParent,
24593 : /*64837*/ OPC_MoveChild, 9,
24594 : /*64839*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24595 : /*64842*/ OPC_RecordNode, // #8 = $DST_SEL_X
24596 : /*64843*/ OPC_CheckType, MVT::i32,
24597 : /*64845*/ OPC_MoveParent,
24598 : /*64846*/ OPC_MoveChild, 10,
24599 : /*64848*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24600 : /*64851*/ OPC_RecordNode, // #9 = $DST_SEL_Y
24601 : /*64852*/ OPC_CheckType, MVT::i32,
24602 : /*64854*/ OPC_MoveParent,
24603 : /*64855*/ OPC_MoveChild, 11,
24604 : /*64857*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24605 : /*64860*/ OPC_RecordNode, // #10 = $DST_SEL_Z
24606 : /*64861*/ OPC_CheckType, MVT::i32,
24607 : /*64863*/ OPC_MoveParent,
24608 : /*64864*/ OPC_MoveChild, 12,
24609 : /*64866*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24610 : /*64869*/ OPC_RecordNode, // #11 = $DST_SEL_W
24611 : /*64870*/ OPC_CheckType, MVT::i32,
24612 : /*64872*/ OPC_MoveParent,
24613 : /*64873*/ OPC_MoveChild, 13,
24614 : /*64875*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24615 : /*64878*/ OPC_RecordNode, // #12 = $RESOURCE_ID
24616 : /*64879*/ OPC_CheckType, MVT::i32,
24617 : /*64881*/ OPC_MoveParent,
24618 : /*64882*/ OPC_MoveChild, 14,
24619 : /*64884*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24620 : /*64887*/ OPC_RecordNode, // #13 = $SAMPLER_ID
24621 : /*64888*/ OPC_CheckType, MVT::i32,
24622 : /*64890*/ OPC_MoveParent,
24623 : /*64891*/ OPC_MoveChild, 15,
24624 : /*64893*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24625 : /*64896*/ OPC_RecordNode, // #14 = $COORD_TYPE_X
24626 : /*64897*/ OPC_CheckType, MVT::i32,
24627 : /*64899*/ OPC_MoveParent,
24628 : /*64900*/ OPC_MoveChild, 16,
24629 : /*64902*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24630 : /*64905*/ OPC_RecordNode, // #15 = $COORD_TYPE_Y
24631 : /*64906*/ OPC_CheckType, MVT::i32,
24632 : /*64908*/ OPC_MoveParent,
24633 : /*64909*/ OPC_MoveChild, 17,
24634 : /*64911*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24635 : /*64914*/ OPC_RecordNode, // #16 = $COORD_TYPE_Z
24636 : /*64915*/ OPC_CheckType, MVT::i32,
24637 : /*64917*/ OPC_MoveParent,
24638 : /*64918*/ OPC_MoveChild, 18,
24639 : /*64920*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24640 : /*64923*/ OPC_RecordNode, // #17 = $COORD_TYPE_W
24641 : /*64924*/ OPC_CheckType, MVT::i32,
24642 : /*64926*/ OPC_MoveParent,
24643 : /*64927*/ OPC_CheckType, MVT::v4f32,
24644 : /*64929*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
24645 : /*64931*/ OPC_EmitConvertToTarget, 1,
24646 : /*64933*/ OPC_EmitConvertToTarget, 2,
24647 : /*64935*/ OPC_EmitConvertToTarget, 3,
24648 : /*64937*/ OPC_EmitConvertToTarget, 4,
24649 : /*64939*/ OPC_EmitConvertToTarget, 5,
24650 : /*64941*/ OPC_EmitConvertToTarget, 6,
24651 : /*64943*/ OPC_EmitConvertToTarget, 7,
24652 : /*64945*/ OPC_EmitConvertToTarget, 8,
24653 : /*64947*/ OPC_EmitConvertToTarget, 9,
24654 : /*64949*/ OPC_EmitConvertToTarget, 10,
24655 : /*64951*/ OPC_EmitConvertToTarget, 11,
24656 : /*64953*/ OPC_EmitConvertToTarget, 12,
24657 : /*64955*/ OPC_EmitConvertToTarget, 13,
24658 : /*64957*/ OPC_EmitConvertToTarget, 14,
24659 : /*64959*/ OPC_EmitConvertToTarget, 15,
24660 : /*64961*/ OPC_EmitConvertToTarget, 16,
24661 : /*64963*/ OPC_EmitConvertToTarget, 17,
24662 : /*64965*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_LD), 0,
24663 : 1/*#VTs*/, MVT::v4f32, 18/*#Ops*/, 0, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
24664 : // Src: (TEXTURE_FETCH:v4f32 6:i32, v4i32:v4i32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W) - Complexity = 59
24665 : // Dst: (TEX_LD:v4f32 R600_Reg128:v4i32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W)
24666 : /*64990*/ /*Scope*/ 95|128,1/*223*/, /*->65215*/
24667 : /*64992*/ OPC_CheckChild0Integer, 7,
24668 : /*64994*/ OPC_CheckChild0Type, MVT::i32,
24669 : /*64996*/ OPC_RecordChild1, // #0 = $SRC_GPR
24670 : /*64997*/ OPC_CheckChild1Type, MVT::v4i32,
24671 : /*64999*/ OPC_RecordChild2, // #1 = $srcx
24672 : /*65000*/ OPC_MoveChild, 2,
24673 : /*65002*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24674 : /*65005*/ OPC_CheckType, MVT::i32,
24675 : /*65007*/ OPC_MoveParent,
24676 : /*65008*/ OPC_RecordChild3, // #2 = $srcy
24677 : /*65009*/ OPC_MoveChild, 3,
24678 : /*65011*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24679 : /*65014*/ OPC_CheckType, MVT::i32,
24680 : /*65016*/ OPC_MoveParent,
24681 : /*65017*/ OPC_RecordChild4, // #3 = $srcz
24682 : /*65018*/ OPC_MoveChild, 4,
24683 : /*65020*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24684 : /*65023*/ OPC_CheckType, MVT::i32,
24685 : /*65025*/ OPC_MoveParent,
24686 : /*65026*/ OPC_RecordChild5, // #4 = $srcw
24687 : /*65027*/ OPC_MoveChild, 5,
24688 : /*65029*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24689 : /*65032*/ OPC_CheckType, MVT::i32,
24690 : /*65034*/ OPC_MoveParent,
24691 : /*65035*/ OPC_RecordChild6, // #5 = $offsetx
24692 : /*65036*/ OPC_MoveChild, 6,
24693 : /*65038*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24694 : /*65041*/ OPC_CheckType, MVT::i32,
24695 : /*65043*/ OPC_MoveParent,
24696 : /*65044*/ OPC_RecordChild7, // #6 = $offsety
24697 : /*65045*/ OPC_MoveChild, 7,
24698 : /*65047*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24699 : /*65050*/ OPC_CheckType, MVT::i32,
24700 : /*65052*/ OPC_MoveParent,
24701 : /*65053*/ OPC_MoveChild, 8,
24702 : /*65055*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24703 : /*65058*/ OPC_RecordNode, // #7 = $offsetz
24704 : /*65059*/ OPC_CheckType, MVT::i32,
24705 : /*65061*/ OPC_MoveParent,
24706 : /*65062*/ OPC_MoveChild, 9,
24707 : /*65064*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24708 : /*65067*/ OPC_RecordNode, // #8 = $DST_SEL_X
24709 : /*65068*/ OPC_CheckType, MVT::i32,
24710 : /*65070*/ OPC_MoveParent,
24711 : /*65071*/ OPC_MoveChild, 10,
24712 : /*65073*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24713 : /*65076*/ OPC_RecordNode, // #9 = $DST_SEL_Y
24714 : /*65077*/ OPC_CheckType, MVT::i32,
24715 : /*65079*/ OPC_MoveParent,
24716 : /*65080*/ OPC_MoveChild, 11,
24717 : /*65082*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24718 : /*65085*/ OPC_RecordNode, // #10 = $DST_SEL_Z
24719 : /*65086*/ OPC_CheckType, MVT::i32,
24720 : /*65088*/ OPC_MoveParent,
24721 : /*65089*/ OPC_MoveChild, 12,
24722 : /*65091*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24723 : /*65094*/ OPC_RecordNode, // #11 = $DST_SEL_W
24724 : /*65095*/ OPC_CheckType, MVT::i32,
24725 : /*65097*/ OPC_MoveParent,
24726 : /*65098*/ OPC_MoveChild, 13,
24727 : /*65100*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24728 : /*65103*/ OPC_RecordNode, // #12 = $RESOURCE_ID
24729 : /*65104*/ OPC_CheckType, MVT::i32,
24730 : /*65106*/ OPC_MoveParent,
24731 : /*65107*/ OPC_MoveChild, 14,
24732 : /*65109*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24733 : /*65112*/ OPC_RecordNode, // #13 = $SAMPLER_ID
24734 : /*65113*/ OPC_CheckType, MVT::i32,
24735 : /*65115*/ OPC_MoveParent,
24736 : /*65116*/ OPC_MoveChild, 15,
24737 : /*65118*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24738 : /*65121*/ OPC_RecordNode, // #14 = $COORD_TYPE_X
24739 : /*65122*/ OPC_CheckType, MVT::i32,
24740 : /*65124*/ OPC_MoveParent,
24741 : /*65125*/ OPC_MoveChild, 16,
24742 : /*65127*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24743 : /*65130*/ OPC_RecordNode, // #15 = $COORD_TYPE_Y
24744 : /*65131*/ OPC_CheckType, MVT::i32,
24745 : /*65133*/ OPC_MoveParent,
24746 : /*65134*/ OPC_MoveChild, 17,
24747 : /*65136*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24748 : /*65139*/ OPC_RecordNode, // #16 = $COORD_TYPE_Z
24749 : /*65140*/ OPC_CheckType, MVT::i32,
24750 : /*65142*/ OPC_MoveParent,
24751 : /*65143*/ OPC_MoveChild, 18,
24752 : /*65145*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24753 : /*65148*/ OPC_RecordNode, // #17 = $COORD_TYPE_W
24754 : /*65149*/ OPC_CheckType, MVT::i32,
24755 : /*65151*/ OPC_MoveParent,
24756 : /*65152*/ OPC_CheckType, MVT::v4f32,
24757 : /*65154*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
24758 : /*65156*/ OPC_EmitConvertToTarget, 1,
24759 : /*65158*/ OPC_EmitConvertToTarget, 2,
24760 : /*65160*/ OPC_EmitConvertToTarget, 3,
24761 : /*65162*/ OPC_EmitConvertToTarget, 4,
24762 : /*65164*/ OPC_EmitConvertToTarget, 5,
24763 : /*65166*/ OPC_EmitConvertToTarget, 6,
24764 : /*65168*/ OPC_EmitConvertToTarget, 7,
24765 : /*65170*/ OPC_EmitConvertToTarget, 8,
24766 : /*65172*/ OPC_EmitConvertToTarget, 9,
24767 : /*65174*/ OPC_EmitConvertToTarget, 10,
24768 : /*65176*/ OPC_EmitConvertToTarget, 11,
24769 : /*65178*/ OPC_EmitConvertToTarget, 12,
24770 : /*65180*/ OPC_EmitConvertToTarget, 13,
24771 : /*65182*/ OPC_EmitConvertToTarget, 14,
24772 : /*65184*/ OPC_EmitConvertToTarget, 15,
24773 : /*65186*/ OPC_EmitConvertToTarget, 16,
24774 : /*65188*/ OPC_EmitConvertToTarget, 17,
24775 : /*65190*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_GET_TEXTURE_RESINFO), 0,
24776 : 1/*#VTs*/, MVT::v4f32, 18/*#Ops*/, 0, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
24777 : // Src: (TEXTURE_FETCH:v4f32 7:i32, v4i32:v4i32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W) - Complexity = 59
24778 : // Dst: (TEX_GET_TEXTURE_RESINFO:v4f32 R600_Reg128:v4i32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W)
24779 : /*65215*/ /*Scope*/ 95|128,1/*223*/, /*->65440*/
24780 : /*65217*/ OPC_CheckChild0Integer, 8,
24781 : /*65219*/ OPC_CheckChild0Type, MVT::i32,
24782 : /*65221*/ OPC_RecordChild1, // #0 = $SRC_GPR
24783 : /*65222*/ OPC_CheckChild1Type, MVT::v4f32,
24784 : /*65224*/ OPC_RecordChild2, // #1 = $srcx
24785 : /*65225*/ OPC_MoveChild, 2,
24786 : /*65227*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24787 : /*65230*/ OPC_CheckType, MVT::i32,
24788 : /*65232*/ OPC_MoveParent,
24789 : /*65233*/ OPC_RecordChild3, // #2 = $srcy
24790 : /*65234*/ OPC_MoveChild, 3,
24791 : /*65236*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24792 : /*65239*/ OPC_CheckType, MVT::i32,
24793 : /*65241*/ OPC_MoveParent,
24794 : /*65242*/ OPC_RecordChild4, // #3 = $srcz
24795 : /*65243*/ OPC_MoveChild, 4,
24796 : /*65245*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24797 : /*65248*/ OPC_CheckType, MVT::i32,
24798 : /*65250*/ OPC_MoveParent,
24799 : /*65251*/ OPC_RecordChild5, // #4 = $srcw
24800 : /*65252*/ OPC_MoveChild, 5,
24801 : /*65254*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24802 : /*65257*/ OPC_CheckType, MVT::i32,
24803 : /*65259*/ OPC_MoveParent,
24804 : /*65260*/ OPC_RecordChild6, // #5 = $offsetx
24805 : /*65261*/ OPC_MoveChild, 6,
24806 : /*65263*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24807 : /*65266*/ OPC_CheckType, MVT::i32,
24808 : /*65268*/ OPC_MoveParent,
24809 : /*65269*/ OPC_RecordChild7, // #6 = $offsety
24810 : /*65270*/ OPC_MoveChild, 7,
24811 : /*65272*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24812 : /*65275*/ OPC_CheckType, MVT::i32,
24813 : /*65277*/ OPC_MoveParent,
24814 : /*65278*/ OPC_MoveChild, 8,
24815 : /*65280*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24816 : /*65283*/ OPC_RecordNode, // #7 = $offsetz
24817 : /*65284*/ OPC_CheckType, MVT::i32,
24818 : /*65286*/ OPC_MoveParent,
24819 : /*65287*/ OPC_MoveChild, 9,
24820 : /*65289*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24821 : /*65292*/ OPC_RecordNode, // #8 = $DST_SEL_X
24822 : /*65293*/ OPC_CheckType, MVT::i32,
24823 : /*65295*/ OPC_MoveParent,
24824 : /*65296*/ OPC_MoveChild, 10,
24825 : /*65298*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24826 : /*65301*/ OPC_RecordNode, // #9 = $DST_SEL_Y
24827 : /*65302*/ OPC_CheckType, MVT::i32,
24828 : /*65304*/ OPC_MoveParent,
24829 : /*65305*/ OPC_MoveChild, 11,
24830 : /*65307*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24831 : /*65310*/ OPC_RecordNode, // #10 = $DST_SEL_Z
24832 : /*65311*/ OPC_CheckType, MVT::i32,
24833 : /*65313*/ OPC_MoveParent,
24834 : /*65314*/ OPC_MoveChild, 12,
24835 : /*65316*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24836 : /*65319*/ OPC_RecordNode, // #11 = $DST_SEL_W
24837 : /*65320*/ OPC_CheckType, MVT::i32,
24838 : /*65322*/ OPC_MoveParent,
24839 : /*65323*/ OPC_MoveChild, 13,
24840 : /*65325*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24841 : /*65328*/ OPC_RecordNode, // #12 = $RESOURCE_ID
24842 : /*65329*/ OPC_CheckType, MVT::i32,
24843 : /*65331*/ OPC_MoveParent,
24844 : /*65332*/ OPC_MoveChild, 14,
24845 : /*65334*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24846 : /*65337*/ OPC_RecordNode, // #13 = $SAMPLER_ID
24847 : /*65338*/ OPC_CheckType, MVT::i32,
24848 : /*65340*/ OPC_MoveParent,
24849 : /*65341*/ OPC_MoveChild, 15,
24850 : /*65343*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24851 : /*65346*/ OPC_RecordNode, // #14 = $COORD_TYPE_X
24852 : /*65347*/ OPC_CheckType, MVT::i32,
24853 : /*65349*/ OPC_MoveParent,
24854 : /*65350*/ OPC_MoveChild, 16,
24855 : /*65352*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24856 : /*65355*/ OPC_RecordNode, // #15 = $COORD_TYPE_Y
24857 : /*65356*/ OPC_CheckType, MVT::i32,
24858 : /*65358*/ OPC_MoveParent,
24859 : /*65359*/ OPC_MoveChild, 17,
24860 : /*65361*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24861 : /*65364*/ OPC_RecordNode, // #16 = $COORD_TYPE_Z
24862 : /*65365*/ OPC_CheckType, MVT::i32,
24863 : /*65367*/ OPC_MoveParent,
24864 : /*65368*/ OPC_MoveChild, 18,
24865 : /*65370*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24866 : /*65373*/ OPC_RecordNode, // #17 = $COORD_TYPE_W
24867 : /*65374*/ OPC_CheckType, MVT::i32,
24868 : /*65376*/ OPC_MoveParent,
24869 : /*65377*/ OPC_CheckType, MVT::v4f32,
24870 : /*65379*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
24871 : /*65381*/ OPC_EmitConvertToTarget, 1,
24872 : /*65383*/ OPC_EmitConvertToTarget, 2,
24873 : /*65385*/ OPC_EmitConvertToTarget, 3,
24874 : /*65387*/ OPC_EmitConvertToTarget, 4,
24875 : /*65389*/ OPC_EmitConvertToTarget, 5,
24876 : /*65391*/ OPC_EmitConvertToTarget, 6,
24877 : /*65393*/ OPC_EmitConvertToTarget, 7,
24878 : /*65395*/ OPC_EmitConvertToTarget, 8,
24879 : /*65397*/ OPC_EmitConvertToTarget, 9,
24880 : /*65399*/ OPC_EmitConvertToTarget, 10,
24881 : /*65401*/ OPC_EmitConvertToTarget, 11,
24882 : /*65403*/ OPC_EmitConvertToTarget, 12,
24883 : /*65405*/ OPC_EmitConvertToTarget, 13,
24884 : /*65407*/ OPC_EmitConvertToTarget, 14,
24885 : /*65409*/ OPC_EmitConvertToTarget, 15,
24886 : /*65411*/ OPC_EmitConvertToTarget, 16,
24887 : /*65413*/ OPC_EmitConvertToTarget, 17,
24888 : /*65415*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_GET_GRADIENTS_H), 0,
24889 : 1/*#VTs*/, MVT::v4f32, 18/*#Ops*/, 0, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
24890 : // Src: (TEXTURE_FETCH:v4f32 8:i32, v4f32:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W) - Complexity = 59
24891 : // Dst: (TEX_GET_GRADIENTS_H:v4f32 R600_Reg128:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W)
24892 : /*65440*/ /*Scope*/ 95|128,1/*223*/, /*->65665*/
24893 : /*65442*/ OPC_CheckChild0Integer, 9,
24894 : /*65444*/ OPC_CheckChild0Type, MVT::i32,
24895 : /*65446*/ OPC_RecordChild1, // #0 = $SRC_GPR
24896 : /*65447*/ OPC_CheckChild1Type, MVT::v4f32,
24897 : /*65449*/ OPC_RecordChild2, // #1 = $srcx
24898 : /*65450*/ OPC_MoveChild, 2,
24899 : /*65452*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24900 : /*65455*/ OPC_CheckType, MVT::i32,
24901 : /*65457*/ OPC_MoveParent,
24902 : /*65458*/ OPC_RecordChild3, // #2 = $srcy
24903 : /*65459*/ OPC_MoveChild, 3,
24904 : /*65461*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24905 : /*65464*/ OPC_CheckType, MVT::i32,
24906 : /*65466*/ OPC_MoveParent,
24907 : /*65467*/ OPC_RecordChild4, // #3 = $srcz
24908 : /*65468*/ OPC_MoveChild, 4,
24909 : /*65470*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24910 : /*65473*/ OPC_CheckType, MVT::i32,
24911 : /*65475*/ OPC_MoveParent,
24912 : /*65476*/ OPC_RecordChild5, // #4 = $srcw
24913 : /*65477*/ OPC_MoveChild, 5,
24914 : /*65479*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24915 : /*65482*/ OPC_CheckType, MVT::i32,
24916 : /*65484*/ OPC_MoveParent,
24917 : /*65485*/ OPC_RecordChild6, // #5 = $offsetx
24918 : /*65486*/ OPC_MoveChild, 6,
24919 : /*65488*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24920 : /*65491*/ OPC_CheckType, MVT::i32,
24921 : /*65493*/ OPC_MoveParent,
24922 : /*65494*/ OPC_RecordChild7, // #6 = $offsety
24923 : /*65495*/ OPC_MoveChild, 7,
24924 : /*65497*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24925 : /*65500*/ OPC_CheckType, MVT::i32,
24926 : /*65502*/ OPC_MoveParent,
24927 : /*65503*/ OPC_MoveChild, 8,
24928 : /*65505*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24929 : /*65508*/ OPC_RecordNode, // #7 = $offsetz
24930 : /*65509*/ OPC_CheckType, MVT::i32,
24931 : /*65511*/ OPC_MoveParent,
24932 : /*65512*/ OPC_MoveChild, 9,
24933 : /*65514*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24934 : /*65517*/ OPC_RecordNode, // #8 = $DST_SEL_X
24935 : /*65518*/ OPC_CheckType, MVT::i32,
24936 : /*65520*/ OPC_MoveParent,
24937 : /*65521*/ OPC_MoveChild, 10,
24938 : /*65523*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24939 : /*65526*/ OPC_RecordNode, // #9 = $DST_SEL_Y
24940 : /*65527*/ OPC_CheckType, MVT::i32,
24941 : /*65529*/ OPC_MoveParent,
24942 : /*65530*/ OPC_MoveChild, 11,
24943 : /*65532*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24944 : /*65535*/ OPC_RecordNode, // #10 = $DST_SEL_Z
24945 : /*65536*/ OPC_CheckType, MVT::i32,
24946 : /*65538*/ OPC_MoveParent,
24947 : /*65539*/ OPC_MoveChild, 12,
24948 : /*65541*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24949 : /*65544*/ OPC_RecordNode, // #11 = $DST_SEL_W
24950 : /*65545*/ OPC_CheckType, MVT::i32,
24951 : /*65547*/ OPC_MoveParent,
24952 : /*65548*/ OPC_MoveChild, 13,
24953 : /*65550*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24954 : /*65553*/ OPC_RecordNode, // #12 = $RESOURCE_ID
24955 : /*65554*/ OPC_CheckType, MVT::i32,
24956 : /*65556*/ OPC_MoveParent,
24957 : /*65557*/ OPC_MoveChild, 14,
24958 : /*65559*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24959 : /*65562*/ OPC_RecordNode, // #13 = $SAMPLER_ID
24960 : /*65563*/ OPC_CheckType, MVT::i32,
24961 : /*65565*/ OPC_MoveParent,
24962 : /*65566*/ OPC_MoveChild, 15,
24963 : /*65568*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24964 : /*65571*/ OPC_RecordNode, // #14 = $COORD_TYPE_X
24965 : /*65572*/ OPC_CheckType, MVT::i32,
24966 : /*65574*/ OPC_MoveParent,
24967 : /*65575*/ OPC_MoveChild, 16,
24968 : /*65577*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24969 : /*65580*/ OPC_RecordNode, // #15 = $COORD_TYPE_Y
24970 : /*65581*/ OPC_CheckType, MVT::i32,
24971 : /*65583*/ OPC_MoveParent,
24972 : /*65584*/ OPC_MoveChild, 17,
24973 : /*65586*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24974 : /*65589*/ OPC_RecordNode, // #16 = $COORD_TYPE_Z
24975 : /*65590*/ OPC_CheckType, MVT::i32,
24976 : /*65592*/ OPC_MoveParent,
24977 : /*65593*/ OPC_MoveChild, 18,
24978 : /*65595*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
24979 : /*65598*/ OPC_RecordNode, // #17 = $COORD_TYPE_W
24980 : /*65599*/ OPC_CheckType, MVT::i32,
24981 : /*65601*/ OPC_MoveParent,
24982 : /*65602*/ OPC_CheckType, MVT::v4f32,
24983 : /*65604*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
24984 : /*65606*/ OPC_EmitConvertToTarget, 1,
24985 : /*65608*/ OPC_EmitConvertToTarget, 2,
24986 : /*65610*/ OPC_EmitConvertToTarget, 3,
24987 : /*65612*/ OPC_EmitConvertToTarget, 4,
24988 : /*65614*/ OPC_EmitConvertToTarget, 5,
24989 : /*65616*/ OPC_EmitConvertToTarget, 6,
24990 : /*65618*/ OPC_EmitConvertToTarget, 7,
24991 : /*65620*/ OPC_EmitConvertToTarget, 8,
24992 : /*65622*/ OPC_EmitConvertToTarget, 9,
24993 : /*65624*/ OPC_EmitConvertToTarget, 10,
24994 : /*65626*/ OPC_EmitConvertToTarget, 11,
24995 : /*65628*/ OPC_EmitConvertToTarget, 12,
24996 : /*65630*/ OPC_EmitConvertToTarget, 13,
24997 : /*65632*/ OPC_EmitConvertToTarget, 14,
24998 : /*65634*/ OPC_EmitConvertToTarget, 15,
24999 : /*65636*/ OPC_EmitConvertToTarget, 16,
25000 : /*65638*/ OPC_EmitConvertToTarget, 17,
25001 : /*65640*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_GET_GRADIENTS_V), 0,
25002 : 1/*#VTs*/, MVT::v4f32, 18/*#Ops*/, 0, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
25003 : // Src: (TEXTURE_FETCH:v4f32 9:i32, v4f32:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W) - Complexity = 59
25004 : // Dst: (TEX_GET_GRADIENTS_V:v4f32 R600_Reg128:v4f32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W)
25005 : /*65665*/ /*Scope*/ 95|128,1/*223*/, /*->65890*/
25006 : /*65667*/ OPC_CheckChild0Integer, 10,
25007 : /*65669*/ OPC_CheckChild0Type, MVT::i32,
25008 : /*65671*/ OPC_RecordChild1, // #0 = $SRC_GPR
25009 : /*65672*/ OPC_CheckChild1Type, MVT::v4i32,
25010 : /*65674*/ OPC_RecordChild2, // #1 = $srcx
25011 : /*65675*/ OPC_MoveChild, 2,
25012 : /*65677*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25013 : /*65680*/ OPC_CheckType, MVT::i32,
25014 : /*65682*/ OPC_MoveParent,
25015 : /*65683*/ OPC_RecordChild3, // #2 = $srcy
25016 : /*65684*/ OPC_MoveChild, 3,
25017 : /*65686*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25018 : /*65689*/ OPC_CheckType, MVT::i32,
25019 : /*65691*/ OPC_MoveParent,
25020 : /*65692*/ OPC_RecordChild4, // #3 = $srcz
25021 : /*65693*/ OPC_MoveChild, 4,
25022 : /*65695*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25023 : /*65698*/ OPC_CheckType, MVT::i32,
25024 : /*65700*/ OPC_MoveParent,
25025 : /*65701*/ OPC_RecordChild5, // #4 = $srcw
25026 : /*65702*/ OPC_MoveChild, 5,
25027 : /*65704*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25028 : /*65707*/ OPC_CheckType, MVT::i32,
25029 : /*65709*/ OPC_MoveParent,
25030 : /*65710*/ OPC_RecordChild6, // #5 = $offsetx
25031 : /*65711*/ OPC_MoveChild, 6,
25032 : /*65713*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25033 : /*65716*/ OPC_CheckType, MVT::i32,
25034 : /*65718*/ OPC_MoveParent,
25035 : /*65719*/ OPC_RecordChild7, // #6 = $offsety
25036 : /*65720*/ OPC_MoveChild, 7,
25037 : /*65722*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25038 : /*65725*/ OPC_CheckType, MVT::i32,
25039 : /*65727*/ OPC_MoveParent,
25040 : /*65728*/ OPC_MoveChild, 8,
25041 : /*65730*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25042 : /*65733*/ OPC_RecordNode, // #7 = $offsetz
25043 : /*65734*/ OPC_CheckType, MVT::i32,
25044 : /*65736*/ OPC_MoveParent,
25045 : /*65737*/ OPC_MoveChild, 9,
25046 : /*65739*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25047 : /*65742*/ OPC_RecordNode, // #8 = $DST_SEL_X
25048 : /*65743*/ OPC_CheckType, MVT::i32,
25049 : /*65745*/ OPC_MoveParent,
25050 : /*65746*/ OPC_MoveChild, 10,
25051 : /*65748*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25052 : /*65751*/ OPC_RecordNode, // #9 = $DST_SEL_Y
25053 : /*65752*/ OPC_CheckType, MVT::i32,
25054 : /*65754*/ OPC_MoveParent,
25055 : /*65755*/ OPC_MoveChild, 11,
25056 : /*65757*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25057 : /*65760*/ OPC_RecordNode, // #10 = $DST_SEL_Z
25058 : /*65761*/ OPC_CheckType, MVT::i32,
25059 : /*65763*/ OPC_MoveParent,
25060 : /*65764*/ OPC_MoveChild, 12,
25061 : /*65766*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25062 : /*65769*/ OPC_RecordNode, // #11 = $DST_SEL_W
25063 : /*65770*/ OPC_CheckType, MVT::i32,
25064 : /*65772*/ OPC_MoveParent,
25065 : /*65773*/ OPC_MoveChild, 13,
25066 : /*65775*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25067 : /*65778*/ OPC_RecordNode, // #12 = $RESOURCE_ID
25068 : /*65779*/ OPC_CheckType, MVT::i32,
25069 : /*65781*/ OPC_MoveParent,
25070 : /*65782*/ OPC_MoveChild, 14,
25071 : /*65784*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25072 : /*65787*/ OPC_RecordNode, // #13 = $SAMPLER_ID
25073 : /*65788*/ OPC_CheckType, MVT::i32,
25074 : /*65790*/ OPC_MoveParent,
25075 : /*65791*/ OPC_MoveChild, 15,
25076 : /*65793*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25077 : /*65796*/ OPC_RecordNode, // #14 = $COORD_TYPE_X
25078 : /*65797*/ OPC_CheckType, MVT::i32,
25079 : /*65799*/ OPC_MoveParent,
25080 : /*65800*/ OPC_MoveChild, 16,
25081 : /*65802*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25082 : /*65805*/ OPC_RecordNode, // #15 = $COORD_TYPE_Y
25083 : /*65806*/ OPC_CheckType, MVT::i32,
25084 : /*65808*/ OPC_MoveParent,
25085 : /*65809*/ OPC_MoveChild, 17,
25086 : /*65811*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25087 : /*65814*/ OPC_RecordNode, // #16 = $COORD_TYPE_Z
25088 : /*65815*/ OPC_CheckType, MVT::i32,
25089 : /*65817*/ OPC_MoveParent,
25090 : /*65818*/ OPC_MoveChild, 18,
25091 : /*65820*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25092 : /*65823*/ OPC_RecordNode, // #17 = $COORD_TYPE_W
25093 : /*65824*/ OPC_CheckType, MVT::i32,
25094 : /*65826*/ OPC_MoveParent,
25095 : /*65827*/ OPC_CheckType, MVT::v4f32,
25096 : /*65829*/ OPC_CheckPatternPredicate, 9, // (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
25097 : /*65831*/ OPC_EmitConvertToTarget, 1,
25098 : /*65833*/ OPC_EmitConvertToTarget, 2,
25099 : /*65835*/ OPC_EmitConvertToTarget, 3,
25100 : /*65837*/ OPC_EmitConvertToTarget, 4,
25101 : /*65839*/ OPC_EmitConvertToTarget, 5,
25102 : /*65841*/ OPC_EmitConvertToTarget, 6,
25103 : /*65843*/ OPC_EmitConvertToTarget, 7,
25104 : /*65845*/ OPC_EmitConvertToTarget, 8,
25105 : /*65847*/ OPC_EmitConvertToTarget, 9,
25106 : /*65849*/ OPC_EmitConvertToTarget, 10,
25107 : /*65851*/ OPC_EmitConvertToTarget, 11,
25108 : /*65853*/ OPC_EmitConvertToTarget, 12,
25109 : /*65855*/ OPC_EmitConvertToTarget, 13,
25110 : /*65857*/ OPC_EmitConvertToTarget, 14,
25111 : /*65859*/ OPC_EmitConvertToTarget, 15,
25112 : /*65861*/ OPC_EmitConvertToTarget, 16,
25113 : /*65863*/ OPC_EmitConvertToTarget, 17,
25114 : /*65865*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::TEX_LDPTR), 0,
25115 : 1/*#VTs*/, MVT::v4f32, 18/*#Ops*/, 0, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
25116 : // Src: (TEXTURE_FETCH:v4f32 10:i32, v4i32:v4i32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W) - Complexity = 59
25117 : // Dst: (TEX_LDPTR:v4f32 R600_Reg128:v4i32:$SRC_GPR, (imm:i32):$srcx, (imm:i32):$srcy, (imm:i32):$srcz, (imm:i32):$srcw, (imm:i32):$offsetx, (imm:i32):$offsety, (imm:i32):$offsetz, (imm:i32):$DST_SEL_X, (imm:i32):$DST_SEL_Y, (imm:i32):$DST_SEL_Z, (imm:i32):$DST_SEL_W, (imm:i32):$RESOURCE_ID, (imm:i32):$SAMPLER_ID, (imm:i32):$COORD_TYPE_X, (imm:i32):$COORD_TYPE_Y, (imm:i32):$COORD_TYPE_Z, (imm:i32):$COORD_TYPE_W)
25118 : /*65890*/ 0, /*End of Scope*/
25119 : /*65891*/ /*SwitchOpcode*/ 38|128,8/*1062*/, TARGET_VAL(AMDGPUISD::SAMPLE),// ->66957
25120 : /*65895*/ OPC_RecordChild0, // #0 = $addr
25121 : /*65896*/ OPC_Scope, 121|128,1/*249*/, /*->66148*/ // 5 children in Scope
25122 : /*65899*/ OPC_CheckChild0Type, MVT::v2i32,
25123 : /*65901*/ OPC_RecordChild1, // #1 = $rsrc
25124 : /*65902*/ OPC_RecordChild2, // #2 = $sampler
25125 : /*65903*/ OPC_MoveChild, 3,
25126 : /*65905*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25127 : /*65908*/ OPC_Scope, 47, /*->65957*/ // 5 children in Scope
25128 : /*65910*/ OPC_CheckPredicate, 143, // Predicate_TEX_RECT
25129 : /*65912*/ OPC_MoveParent,
25130 : /*65913*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25131 : /*65915*/ OPC_EmitInteger, MVT::i32, 15,
25132 : /*65918*/ OPC_EmitInteger, MVT::i1, 1,
25133 : /*65921*/ OPC_EmitInteger, MVT::i1, 0,
25134 : /*65924*/ OPC_EmitInteger, MVT::i1, 0,
25135 : /*65927*/ OPC_EmitInteger, MVT::i1, 0,
25136 : /*65930*/ OPC_EmitInteger, MVT::i1, 0,
25137 : /*65933*/ OPC_EmitInteger, MVT::i1, 0,
25138 : /*65936*/ OPC_EmitInteger, MVT::i1, 0,
25139 : /*65939*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V2), 0,
25140 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25141 : // Src: (SIsample:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_RECT>>) - Complexity = 7
25142 : // Dst: (IMAGE_SAMPLE_V4_V2:v4f32 15:i32, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25143 : /*65957*/ /*Scope*/ 47, /*->66005*/
25144 : /*65958*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25145 : /*65960*/ OPC_MoveParent,
25146 : /*65961*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25147 : /*65963*/ OPC_EmitInteger, MVT::i32, 15,
25148 : /*65966*/ OPC_EmitInteger, MVT::i1, 0,
25149 : /*65969*/ OPC_EmitInteger, MVT::i1, 0,
25150 : /*65972*/ OPC_EmitInteger, MVT::i1, 1,
25151 : /*65975*/ OPC_EmitInteger, MVT::i1, 0,
25152 : /*65978*/ OPC_EmitInteger, MVT::i1, 0,
25153 : /*65981*/ OPC_EmitInteger, MVT::i1, 0,
25154 : /*65984*/ OPC_EmitInteger, MVT::i1, 0,
25155 : /*65987*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V2), 0,
25156 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25157 : // Src: (SIsample:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
25158 : // Dst: (IMAGE_SAMPLE_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25159 : /*66005*/ /*Scope*/ 47, /*->66053*/
25160 : /*66006*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
25161 : /*66008*/ OPC_MoveParent,
25162 : /*66009*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25163 : /*66011*/ OPC_EmitInteger, MVT::i32, 15,
25164 : /*66014*/ OPC_EmitInteger, MVT::i1, 0,
25165 : /*66017*/ OPC_EmitInteger, MVT::i1, 0,
25166 : /*66020*/ OPC_EmitInteger, MVT::i1, 0,
25167 : /*66023*/ OPC_EmitInteger, MVT::i1, 0,
25168 : /*66026*/ OPC_EmitInteger, MVT::i1, 0,
25169 : /*66029*/ OPC_EmitInteger, MVT::i1, 0,
25170 : /*66032*/ OPC_EmitInteger, MVT::i1, 0,
25171 : /*66035*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V2), 0,
25172 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25173 : // Src: (SIsample:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
25174 : // Dst: (IMAGE_SAMPLE_C_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25175 : /*66053*/ /*Scope*/ 47, /*->66101*/
25176 : /*66054*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
25177 : /*66056*/ OPC_MoveParent,
25178 : /*66057*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25179 : /*66059*/ OPC_EmitInteger, MVT::i32, 15,
25180 : /*66062*/ OPC_EmitInteger, MVT::i1, 0,
25181 : /*66065*/ OPC_EmitInteger, MVT::i1, 0,
25182 : /*66068*/ OPC_EmitInteger, MVT::i1, 1,
25183 : /*66071*/ OPC_EmitInteger, MVT::i1, 0,
25184 : /*66074*/ OPC_EmitInteger, MVT::i1, 0,
25185 : /*66077*/ OPC_EmitInteger, MVT::i1, 0,
25186 : /*66080*/ OPC_EmitInteger, MVT::i1, 0,
25187 : /*66083*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V2), 0,
25188 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25189 : // Src: (SIsample:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
25190 : // Dst: (IMAGE_SAMPLE_C_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25191 : /*66101*/ /*Scope*/ 45, /*->66147*/
25192 : /*66102*/ OPC_MoveParent,
25193 : /*66103*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25194 : /*66105*/ OPC_EmitInteger, MVT::i32, 15,
25195 : /*66108*/ OPC_EmitInteger, MVT::i1, 0,
25196 : /*66111*/ OPC_EmitInteger, MVT::i1, 0,
25197 : /*66114*/ OPC_EmitInteger, MVT::i1, 0,
25198 : /*66117*/ OPC_EmitInteger, MVT::i1, 0,
25199 : /*66120*/ OPC_EmitInteger, MVT::i1, 0,
25200 : /*66123*/ OPC_EmitInteger, MVT::i1, 0,
25201 : /*66126*/ OPC_EmitInteger, MVT::i1, 0,
25202 : /*66129*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V2), 0,
25203 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25204 : // Src: (SIsample:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25205 : // Dst: (IMAGE_SAMPLE_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25206 : /*66147*/ 0, /*End of Scope*/
25207 : /*66148*/ /*Scope*/ 121|128,1/*249*/, /*->66399*/
25208 : /*66150*/ OPC_CheckChild0Type, MVT::v4i32,
25209 : /*66152*/ OPC_RecordChild1, // #1 = $rsrc
25210 : /*66153*/ OPC_RecordChild2, // #2 = $sampler
25211 : /*66154*/ OPC_MoveChild, 3,
25212 : /*66156*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25213 : /*66159*/ OPC_Scope, 47, /*->66208*/ // 5 children in Scope
25214 : /*66161*/ OPC_CheckPredicate, 143, // Predicate_TEX_RECT
25215 : /*66163*/ OPC_MoveParent,
25216 : /*66164*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25217 : /*66166*/ OPC_EmitInteger, MVT::i32, 15,
25218 : /*66169*/ OPC_EmitInteger, MVT::i1, 1,
25219 : /*66172*/ OPC_EmitInteger, MVT::i1, 0,
25220 : /*66175*/ OPC_EmitInteger, MVT::i1, 0,
25221 : /*66178*/ OPC_EmitInteger, MVT::i1, 0,
25222 : /*66181*/ OPC_EmitInteger, MVT::i1, 0,
25223 : /*66184*/ OPC_EmitInteger, MVT::i1, 0,
25224 : /*66187*/ OPC_EmitInteger, MVT::i1, 0,
25225 : /*66190*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V4), 0,
25226 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25227 : // Src: (SIsample:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_RECT>>) - Complexity = 7
25228 : // Dst: (IMAGE_SAMPLE_V4_V4:v4f32 15:i32, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25229 : /*66208*/ /*Scope*/ 47, /*->66256*/
25230 : /*66209*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25231 : /*66211*/ OPC_MoveParent,
25232 : /*66212*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25233 : /*66214*/ OPC_EmitInteger, MVT::i32, 15,
25234 : /*66217*/ OPC_EmitInteger, MVT::i1, 0,
25235 : /*66220*/ OPC_EmitInteger, MVT::i1, 0,
25236 : /*66223*/ OPC_EmitInteger, MVT::i1, 1,
25237 : /*66226*/ OPC_EmitInteger, MVT::i1, 0,
25238 : /*66229*/ OPC_EmitInteger, MVT::i1, 0,
25239 : /*66232*/ OPC_EmitInteger, MVT::i1, 0,
25240 : /*66235*/ OPC_EmitInteger, MVT::i1, 0,
25241 : /*66238*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V4), 0,
25242 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25243 : // Src: (SIsample:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
25244 : // Dst: (IMAGE_SAMPLE_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25245 : /*66256*/ /*Scope*/ 47, /*->66304*/
25246 : /*66257*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
25247 : /*66259*/ OPC_MoveParent,
25248 : /*66260*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25249 : /*66262*/ OPC_EmitInteger, MVT::i32, 15,
25250 : /*66265*/ OPC_EmitInteger, MVT::i1, 0,
25251 : /*66268*/ OPC_EmitInteger, MVT::i1, 0,
25252 : /*66271*/ OPC_EmitInteger, MVT::i1, 0,
25253 : /*66274*/ OPC_EmitInteger, MVT::i1, 0,
25254 : /*66277*/ OPC_EmitInteger, MVT::i1, 0,
25255 : /*66280*/ OPC_EmitInteger, MVT::i1, 0,
25256 : /*66283*/ OPC_EmitInteger, MVT::i1, 0,
25257 : /*66286*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V4), 0,
25258 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25259 : // Src: (SIsample:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
25260 : // Dst: (IMAGE_SAMPLE_C_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25261 : /*66304*/ /*Scope*/ 47, /*->66352*/
25262 : /*66305*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
25263 : /*66307*/ OPC_MoveParent,
25264 : /*66308*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25265 : /*66310*/ OPC_EmitInteger, MVT::i32, 15,
25266 : /*66313*/ OPC_EmitInteger, MVT::i1, 0,
25267 : /*66316*/ OPC_EmitInteger, MVT::i1, 0,
25268 : /*66319*/ OPC_EmitInteger, MVT::i1, 1,
25269 : /*66322*/ OPC_EmitInteger, MVT::i1, 0,
25270 : /*66325*/ OPC_EmitInteger, MVT::i1, 0,
25271 : /*66328*/ OPC_EmitInteger, MVT::i1, 0,
25272 : /*66331*/ OPC_EmitInteger, MVT::i1, 0,
25273 : /*66334*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V4), 0,
25274 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25275 : // Src: (SIsample:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
25276 : // Dst: (IMAGE_SAMPLE_C_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25277 : /*66352*/ /*Scope*/ 45, /*->66398*/
25278 : /*66353*/ OPC_MoveParent,
25279 : /*66354*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25280 : /*66356*/ OPC_EmitInteger, MVT::i32, 15,
25281 : /*66359*/ OPC_EmitInteger, MVT::i1, 0,
25282 : /*66362*/ OPC_EmitInteger, MVT::i1, 0,
25283 : /*66365*/ OPC_EmitInteger, MVT::i1, 0,
25284 : /*66368*/ OPC_EmitInteger, MVT::i1, 0,
25285 : /*66371*/ OPC_EmitInteger, MVT::i1, 0,
25286 : /*66374*/ OPC_EmitInteger, MVT::i1, 0,
25287 : /*66377*/ OPC_EmitInteger, MVT::i1, 0,
25288 : /*66380*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V4), 0,
25289 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25290 : // Src: (SIsample:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25291 : // Dst: (IMAGE_SAMPLE_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25292 : /*66398*/ 0, /*End of Scope*/
25293 : /*66399*/ /*Scope*/ 121|128,1/*249*/, /*->66650*/
25294 : /*66401*/ OPC_CheckChild0Type, MVT::v8i32,
25295 : /*66403*/ OPC_RecordChild1, // #1 = $rsrc
25296 : /*66404*/ OPC_RecordChild2, // #2 = $sampler
25297 : /*66405*/ OPC_MoveChild, 3,
25298 : /*66407*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25299 : /*66410*/ OPC_Scope, 47, /*->66459*/ // 5 children in Scope
25300 : /*66412*/ OPC_CheckPredicate, 143, // Predicate_TEX_RECT
25301 : /*66414*/ OPC_MoveParent,
25302 : /*66415*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25303 : /*66417*/ OPC_EmitInteger, MVT::i32, 15,
25304 : /*66420*/ OPC_EmitInteger, MVT::i1, 1,
25305 : /*66423*/ OPC_EmitInteger, MVT::i1, 0,
25306 : /*66426*/ OPC_EmitInteger, MVT::i1, 0,
25307 : /*66429*/ OPC_EmitInteger, MVT::i1, 0,
25308 : /*66432*/ OPC_EmitInteger, MVT::i1, 0,
25309 : /*66435*/ OPC_EmitInteger, MVT::i1, 0,
25310 : /*66438*/ OPC_EmitInteger, MVT::i1, 0,
25311 : /*66441*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V8), 0,
25312 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25313 : // Src: (SIsample:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_RECT>>) - Complexity = 7
25314 : // Dst: (IMAGE_SAMPLE_V4_V8:v4f32 15:i32, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25315 : /*66459*/ /*Scope*/ 47, /*->66507*/
25316 : /*66460*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25317 : /*66462*/ OPC_MoveParent,
25318 : /*66463*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25319 : /*66465*/ OPC_EmitInteger, MVT::i32, 15,
25320 : /*66468*/ OPC_EmitInteger, MVT::i1, 0,
25321 : /*66471*/ OPC_EmitInteger, MVT::i1, 0,
25322 : /*66474*/ OPC_EmitInteger, MVT::i1, 1,
25323 : /*66477*/ OPC_EmitInteger, MVT::i1, 0,
25324 : /*66480*/ OPC_EmitInteger, MVT::i1, 0,
25325 : /*66483*/ OPC_EmitInteger, MVT::i1, 0,
25326 : /*66486*/ OPC_EmitInteger, MVT::i1, 0,
25327 : /*66489*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V8), 0,
25328 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25329 : // Src: (SIsample:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
25330 : // Dst: (IMAGE_SAMPLE_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25331 : /*66507*/ /*Scope*/ 47, /*->66555*/
25332 : /*66508*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
25333 : /*66510*/ OPC_MoveParent,
25334 : /*66511*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25335 : /*66513*/ OPC_EmitInteger, MVT::i32, 15,
25336 : /*66516*/ OPC_EmitInteger, MVT::i1, 0,
25337 : /*66519*/ OPC_EmitInteger, MVT::i1, 0,
25338 : /*66522*/ OPC_EmitInteger, MVT::i1, 0,
25339 : /*66525*/ OPC_EmitInteger, MVT::i1, 0,
25340 : /*66528*/ OPC_EmitInteger, MVT::i1, 0,
25341 : /*66531*/ OPC_EmitInteger, MVT::i1, 0,
25342 : /*66534*/ OPC_EmitInteger, MVT::i1, 0,
25343 : /*66537*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V8), 0,
25344 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25345 : // Src: (SIsample:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
25346 : // Dst: (IMAGE_SAMPLE_C_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25347 : /*66555*/ /*Scope*/ 47, /*->66603*/
25348 : /*66556*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
25349 : /*66558*/ OPC_MoveParent,
25350 : /*66559*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25351 : /*66561*/ OPC_EmitInteger, MVT::i32, 15,
25352 : /*66564*/ OPC_EmitInteger, MVT::i1, 0,
25353 : /*66567*/ OPC_EmitInteger, MVT::i1, 0,
25354 : /*66570*/ OPC_EmitInteger, MVT::i1, 1,
25355 : /*66573*/ OPC_EmitInteger, MVT::i1, 0,
25356 : /*66576*/ OPC_EmitInteger, MVT::i1, 0,
25357 : /*66579*/ OPC_EmitInteger, MVT::i1, 0,
25358 : /*66582*/ OPC_EmitInteger, MVT::i1, 0,
25359 : /*66585*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V8), 0,
25360 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25361 : // Src: (SIsample:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
25362 : // Dst: (IMAGE_SAMPLE_C_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25363 : /*66603*/ /*Scope*/ 45, /*->66649*/
25364 : /*66604*/ OPC_MoveParent,
25365 : /*66605*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25366 : /*66607*/ OPC_EmitInteger, MVT::i32, 15,
25367 : /*66610*/ OPC_EmitInteger, MVT::i1, 0,
25368 : /*66613*/ OPC_EmitInteger, MVT::i1, 0,
25369 : /*66616*/ OPC_EmitInteger, MVT::i1, 0,
25370 : /*66619*/ OPC_EmitInteger, MVT::i1, 0,
25371 : /*66622*/ OPC_EmitInteger, MVT::i1, 0,
25372 : /*66625*/ OPC_EmitInteger, MVT::i1, 0,
25373 : /*66628*/ OPC_EmitInteger, MVT::i1, 0,
25374 : /*66631*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V8), 0,
25375 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25376 : // Src: (SIsample:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25377 : // Dst: (IMAGE_SAMPLE_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25378 : /*66649*/ 0, /*End of Scope*/
25379 : /*66650*/ /*Scope*/ 121|128,1/*249*/, /*->66901*/
25380 : /*66652*/ OPC_CheckChild0Type, MVT::v16i32,
25381 : /*66654*/ OPC_RecordChild1, // #1 = $rsrc
25382 : /*66655*/ OPC_RecordChild2, // #2 = $sampler
25383 : /*66656*/ OPC_MoveChild, 3,
25384 : /*66658*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25385 : /*66661*/ OPC_Scope, 47, /*->66710*/ // 5 children in Scope
25386 : /*66663*/ OPC_CheckPredicate, 143, // Predicate_TEX_RECT
25387 : /*66665*/ OPC_MoveParent,
25388 : /*66666*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25389 : /*66668*/ OPC_EmitInteger, MVT::i32, 15,
25390 : /*66671*/ OPC_EmitInteger, MVT::i1, 1,
25391 : /*66674*/ OPC_EmitInteger, MVT::i1, 0,
25392 : /*66677*/ OPC_EmitInteger, MVT::i1, 0,
25393 : /*66680*/ OPC_EmitInteger, MVT::i1, 0,
25394 : /*66683*/ OPC_EmitInteger, MVT::i1, 0,
25395 : /*66686*/ OPC_EmitInteger, MVT::i1, 0,
25396 : /*66689*/ OPC_EmitInteger, MVT::i1, 0,
25397 : /*66692*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V16), 0,
25398 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25399 : // Src: (SIsample:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_RECT>>) - Complexity = 7
25400 : // Dst: (IMAGE_SAMPLE_V4_V16:v4f32 15:i32, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25401 : /*66710*/ /*Scope*/ 47, /*->66758*/
25402 : /*66711*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25403 : /*66713*/ OPC_MoveParent,
25404 : /*66714*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25405 : /*66716*/ OPC_EmitInteger, MVT::i32, 15,
25406 : /*66719*/ OPC_EmitInteger, MVT::i1, 0,
25407 : /*66722*/ OPC_EmitInteger, MVT::i1, 0,
25408 : /*66725*/ OPC_EmitInteger, MVT::i1, 1,
25409 : /*66728*/ OPC_EmitInteger, MVT::i1, 0,
25410 : /*66731*/ OPC_EmitInteger, MVT::i1, 0,
25411 : /*66734*/ OPC_EmitInteger, MVT::i1, 0,
25412 : /*66737*/ OPC_EmitInteger, MVT::i1, 0,
25413 : /*66740*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V16), 0,
25414 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25415 : // Src: (SIsample:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
25416 : // Dst: (IMAGE_SAMPLE_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25417 : /*66758*/ /*Scope*/ 47, /*->66806*/
25418 : /*66759*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
25419 : /*66761*/ OPC_MoveParent,
25420 : /*66762*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25421 : /*66764*/ OPC_EmitInteger, MVT::i32, 15,
25422 : /*66767*/ OPC_EmitInteger, MVT::i1, 0,
25423 : /*66770*/ OPC_EmitInteger, MVT::i1, 0,
25424 : /*66773*/ OPC_EmitInteger, MVT::i1, 0,
25425 : /*66776*/ OPC_EmitInteger, MVT::i1, 0,
25426 : /*66779*/ OPC_EmitInteger, MVT::i1, 0,
25427 : /*66782*/ OPC_EmitInteger, MVT::i1, 0,
25428 : /*66785*/ OPC_EmitInteger, MVT::i1, 0,
25429 : /*66788*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V16), 0,
25430 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25431 : // Src: (SIsample:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
25432 : // Dst: (IMAGE_SAMPLE_C_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25433 : /*66806*/ /*Scope*/ 47, /*->66854*/
25434 : /*66807*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
25435 : /*66809*/ OPC_MoveParent,
25436 : /*66810*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25437 : /*66812*/ OPC_EmitInteger, MVT::i32, 15,
25438 : /*66815*/ OPC_EmitInteger, MVT::i1, 0,
25439 : /*66818*/ OPC_EmitInteger, MVT::i1, 0,
25440 : /*66821*/ OPC_EmitInteger, MVT::i1, 1,
25441 : /*66824*/ OPC_EmitInteger, MVT::i1, 0,
25442 : /*66827*/ OPC_EmitInteger, MVT::i1, 0,
25443 : /*66830*/ OPC_EmitInteger, MVT::i1, 0,
25444 : /*66833*/ OPC_EmitInteger, MVT::i1, 0,
25445 : /*66836*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_V4_V16), 0,
25446 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25447 : // Src: (SIsample:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
25448 : // Dst: (IMAGE_SAMPLE_C_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25449 : /*66854*/ /*Scope*/ 45, /*->66900*/
25450 : /*66855*/ OPC_MoveParent,
25451 : /*66856*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25452 : /*66858*/ OPC_EmitInteger, MVT::i32, 15,
25453 : /*66861*/ OPC_EmitInteger, MVT::i1, 0,
25454 : /*66864*/ OPC_EmitInteger, MVT::i1, 0,
25455 : /*66867*/ OPC_EmitInteger, MVT::i1, 0,
25456 : /*66870*/ OPC_EmitInteger, MVT::i1, 0,
25457 : /*66873*/ OPC_EmitInteger, MVT::i1, 0,
25458 : /*66876*/ OPC_EmitInteger, MVT::i1, 0,
25459 : /*66879*/ OPC_EmitInteger, MVT::i1, 0,
25460 : /*66882*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V16), 0,
25461 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25462 : // Src: (SIsample:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25463 : // Dst: (IMAGE_SAMPLE_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25464 : /*66900*/ 0, /*End of Scope*/
25465 : /*66901*/ /*Scope*/ 54, /*->66956*/
25466 : /*66902*/ OPC_CheckChild0Type, MVT::i32,
25467 : /*66904*/ OPC_RecordChild1, // #1 = $rsrc
25468 : /*66905*/ OPC_RecordChild2, // #2 = $sampler
25469 : /*66906*/ OPC_MoveChild, 3,
25470 : /*66908*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25471 : /*66911*/ OPC_MoveParent,
25472 : /*66912*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25473 : /*66914*/ OPC_EmitInteger, MVT::i32, 15,
25474 : /*66917*/ OPC_EmitInteger, MVT::i1, 0,
25475 : /*66920*/ OPC_EmitInteger, MVT::i1, 0,
25476 : /*66923*/ OPC_EmitInteger, MVT::i1, 0,
25477 : /*66926*/ OPC_EmitInteger, MVT::i1, 0,
25478 : /*66929*/ OPC_EmitInteger, MVT::i1, 0,
25479 : /*66932*/ OPC_EmitInteger, MVT::i1, 0,
25480 : /*66935*/ OPC_EmitInteger, MVT::i1, 0,
25481 : /*66938*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_V4_V1), 0,
25482 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25483 : // Src: (SIsample:v4f32 i32:i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25484 : // Dst: (IMAGE_SAMPLE_V4_V1:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25485 : /*66956*/ 0, /*End of Scope*/
25486 : /*66957*/ /*SwitchOpcode*/ 47|128,6/*815*/, TARGET_VAL(AMDGPUISD::SAMPLEL),// ->67776
25487 : /*66961*/ OPC_RecordChild0, // #0 = $addr
25488 : /*66962*/ OPC_Scope, 73|128,1/*201*/, /*->67166*/ // 4 children in Scope
25489 : /*66965*/ OPC_CheckChild0Type, MVT::v2i32,
25490 : /*66967*/ OPC_RecordChild1, // #1 = $rsrc
25491 : /*66968*/ OPC_RecordChild2, // #2 = $sampler
25492 : /*66969*/ OPC_MoveChild, 3,
25493 : /*66971*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25494 : /*66974*/ OPC_Scope, 47, /*->67023*/ // 4 children in Scope
25495 : /*66976*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25496 : /*66978*/ OPC_MoveParent,
25497 : /*66979*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25498 : /*66981*/ OPC_EmitInteger, MVT::i32, 15,
25499 : /*66984*/ OPC_EmitInteger, MVT::i1, 0,
25500 : /*66987*/ OPC_EmitInteger, MVT::i1, 0,
25501 : /*66990*/ OPC_EmitInteger, MVT::i1, 1,
25502 : /*66993*/ OPC_EmitInteger, MVT::i1, 0,
25503 : /*66996*/ OPC_EmitInteger, MVT::i1, 0,
25504 : /*66999*/ OPC_EmitInteger, MVT::i1, 0,
25505 : /*67002*/ OPC_EmitInteger, MVT::i1, 0,
25506 : /*67005*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V2), 0,
25507 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25508 : // Src: (SIsamplel:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
25509 : // Dst: (IMAGE_SAMPLE_L_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25510 : /*67023*/ /*Scope*/ 47, /*->67071*/
25511 : /*67024*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
25512 : /*67026*/ OPC_MoveParent,
25513 : /*67027*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25514 : /*67029*/ OPC_EmitInteger, MVT::i32, 15,
25515 : /*67032*/ OPC_EmitInteger, MVT::i1, 0,
25516 : /*67035*/ OPC_EmitInteger, MVT::i1, 0,
25517 : /*67038*/ OPC_EmitInteger, MVT::i1, 0,
25518 : /*67041*/ OPC_EmitInteger, MVT::i1, 0,
25519 : /*67044*/ OPC_EmitInteger, MVT::i1, 0,
25520 : /*67047*/ OPC_EmitInteger, MVT::i1, 0,
25521 : /*67050*/ OPC_EmitInteger, MVT::i1, 0,
25522 : /*67053*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V2), 0,
25523 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25524 : // Src: (SIsamplel:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
25525 : // Dst: (IMAGE_SAMPLE_C_L_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25526 : /*67071*/ /*Scope*/ 47, /*->67119*/
25527 : /*67072*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
25528 : /*67074*/ OPC_MoveParent,
25529 : /*67075*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25530 : /*67077*/ OPC_EmitInteger, MVT::i32, 15,
25531 : /*67080*/ OPC_EmitInteger, MVT::i1, 0,
25532 : /*67083*/ OPC_EmitInteger, MVT::i1, 0,
25533 : /*67086*/ OPC_EmitInteger, MVT::i1, 1,
25534 : /*67089*/ OPC_EmitInteger, MVT::i1, 0,
25535 : /*67092*/ OPC_EmitInteger, MVT::i1, 0,
25536 : /*67095*/ OPC_EmitInteger, MVT::i1, 0,
25537 : /*67098*/ OPC_EmitInteger, MVT::i1, 0,
25538 : /*67101*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V2), 0,
25539 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25540 : // Src: (SIsamplel:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
25541 : // Dst: (IMAGE_SAMPLE_C_L_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25542 : /*67119*/ /*Scope*/ 45, /*->67165*/
25543 : /*67120*/ OPC_MoveParent,
25544 : /*67121*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25545 : /*67123*/ OPC_EmitInteger, MVT::i32, 15,
25546 : /*67126*/ OPC_EmitInteger, MVT::i1, 0,
25547 : /*67129*/ OPC_EmitInteger, MVT::i1, 0,
25548 : /*67132*/ OPC_EmitInteger, MVT::i1, 0,
25549 : /*67135*/ OPC_EmitInteger, MVT::i1, 0,
25550 : /*67138*/ OPC_EmitInteger, MVT::i1, 0,
25551 : /*67141*/ OPC_EmitInteger, MVT::i1, 0,
25552 : /*67144*/ OPC_EmitInteger, MVT::i1, 0,
25553 : /*67147*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V2), 0,
25554 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25555 : // Src: (SIsamplel:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25556 : // Dst: (IMAGE_SAMPLE_L_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25557 : /*67165*/ 0, /*End of Scope*/
25558 : /*67166*/ /*Scope*/ 73|128,1/*201*/, /*->67369*/
25559 : /*67168*/ OPC_CheckChild0Type, MVT::v4i32,
25560 : /*67170*/ OPC_RecordChild1, // #1 = $rsrc
25561 : /*67171*/ OPC_RecordChild2, // #2 = $sampler
25562 : /*67172*/ OPC_MoveChild, 3,
25563 : /*67174*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25564 : /*67177*/ OPC_Scope, 47, /*->67226*/ // 4 children in Scope
25565 : /*67179*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25566 : /*67181*/ OPC_MoveParent,
25567 : /*67182*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25568 : /*67184*/ OPC_EmitInteger, MVT::i32, 15,
25569 : /*67187*/ OPC_EmitInteger, MVT::i1, 0,
25570 : /*67190*/ OPC_EmitInteger, MVT::i1, 0,
25571 : /*67193*/ OPC_EmitInteger, MVT::i1, 1,
25572 : /*67196*/ OPC_EmitInteger, MVT::i1, 0,
25573 : /*67199*/ OPC_EmitInteger, MVT::i1, 0,
25574 : /*67202*/ OPC_EmitInteger, MVT::i1, 0,
25575 : /*67205*/ OPC_EmitInteger, MVT::i1, 0,
25576 : /*67208*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V4), 0,
25577 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25578 : // Src: (SIsamplel:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
25579 : // Dst: (IMAGE_SAMPLE_L_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25580 : /*67226*/ /*Scope*/ 47, /*->67274*/
25581 : /*67227*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
25582 : /*67229*/ OPC_MoveParent,
25583 : /*67230*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25584 : /*67232*/ OPC_EmitInteger, MVT::i32, 15,
25585 : /*67235*/ OPC_EmitInteger, MVT::i1, 0,
25586 : /*67238*/ OPC_EmitInteger, MVT::i1, 0,
25587 : /*67241*/ OPC_EmitInteger, MVT::i1, 0,
25588 : /*67244*/ OPC_EmitInteger, MVT::i1, 0,
25589 : /*67247*/ OPC_EmitInteger, MVT::i1, 0,
25590 : /*67250*/ OPC_EmitInteger, MVT::i1, 0,
25591 : /*67253*/ OPC_EmitInteger, MVT::i1, 0,
25592 : /*67256*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V4), 0,
25593 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25594 : // Src: (SIsamplel:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
25595 : // Dst: (IMAGE_SAMPLE_C_L_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25596 : /*67274*/ /*Scope*/ 47, /*->67322*/
25597 : /*67275*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
25598 : /*67277*/ OPC_MoveParent,
25599 : /*67278*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25600 : /*67280*/ OPC_EmitInteger, MVT::i32, 15,
25601 : /*67283*/ OPC_EmitInteger, MVT::i1, 0,
25602 : /*67286*/ OPC_EmitInteger, MVT::i1, 0,
25603 : /*67289*/ OPC_EmitInteger, MVT::i1, 1,
25604 : /*67292*/ OPC_EmitInteger, MVT::i1, 0,
25605 : /*67295*/ OPC_EmitInteger, MVT::i1, 0,
25606 : /*67298*/ OPC_EmitInteger, MVT::i1, 0,
25607 : /*67301*/ OPC_EmitInteger, MVT::i1, 0,
25608 : /*67304*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V4), 0,
25609 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25610 : // Src: (SIsamplel:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
25611 : // Dst: (IMAGE_SAMPLE_C_L_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25612 : /*67322*/ /*Scope*/ 45, /*->67368*/
25613 : /*67323*/ OPC_MoveParent,
25614 : /*67324*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25615 : /*67326*/ OPC_EmitInteger, MVT::i32, 15,
25616 : /*67329*/ OPC_EmitInteger, MVT::i1, 0,
25617 : /*67332*/ OPC_EmitInteger, MVT::i1, 0,
25618 : /*67335*/ OPC_EmitInteger, MVT::i1, 0,
25619 : /*67338*/ OPC_EmitInteger, MVT::i1, 0,
25620 : /*67341*/ OPC_EmitInteger, MVT::i1, 0,
25621 : /*67344*/ OPC_EmitInteger, MVT::i1, 0,
25622 : /*67347*/ OPC_EmitInteger, MVT::i1, 0,
25623 : /*67350*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V4), 0,
25624 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25625 : // Src: (SIsamplel:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25626 : // Dst: (IMAGE_SAMPLE_L_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25627 : /*67368*/ 0, /*End of Scope*/
25628 : /*67369*/ /*Scope*/ 73|128,1/*201*/, /*->67572*/
25629 : /*67371*/ OPC_CheckChild0Type, MVT::v8i32,
25630 : /*67373*/ OPC_RecordChild1, // #1 = $rsrc
25631 : /*67374*/ OPC_RecordChild2, // #2 = $sampler
25632 : /*67375*/ OPC_MoveChild, 3,
25633 : /*67377*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25634 : /*67380*/ OPC_Scope, 47, /*->67429*/ // 4 children in Scope
25635 : /*67382*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25636 : /*67384*/ OPC_MoveParent,
25637 : /*67385*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25638 : /*67387*/ OPC_EmitInteger, MVT::i32, 15,
25639 : /*67390*/ OPC_EmitInteger, MVT::i1, 0,
25640 : /*67393*/ OPC_EmitInteger, MVT::i1, 0,
25641 : /*67396*/ OPC_EmitInteger, MVT::i1, 1,
25642 : /*67399*/ OPC_EmitInteger, MVT::i1, 0,
25643 : /*67402*/ OPC_EmitInteger, MVT::i1, 0,
25644 : /*67405*/ OPC_EmitInteger, MVT::i1, 0,
25645 : /*67408*/ OPC_EmitInteger, MVT::i1, 0,
25646 : /*67411*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V8), 0,
25647 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25648 : // Src: (SIsamplel:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
25649 : // Dst: (IMAGE_SAMPLE_L_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25650 : /*67429*/ /*Scope*/ 47, /*->67477*/
25651 : /*67430*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
25652 : /*67432*/ OPC_MoveParent,
25653 : /*67433*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25654 : /*67435*/ OPC_EmitInteger, MVT::i32, 15,
25655 : /*67438*/ OPC_EmitInteger, MVT::i1, 0,
25656 : /*67441*/ OPC_EmitInteger, MVT::i1, 0,
25657 : /*67444*/ OPC_EmitInteger, MVT::i1, 0,
25658 : /*67447*/ OPC_EmitInteger, MVT::i1, 0,
25659 : /*67450*/ OPC_EmitInteger, MVT::i1, 0,
25660 : /*67453*/ OPC_EmitInteger, MVT::i1, 0,
25661 : /*67456*/ OPC_EmitInteger, MVT::i1, 0,
25662 : /*67459*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V8), 0,
25663 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25664 : // Src: (SIsamplel:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
25665 : // Dst: (IMAGE_SAMPLE_C_L_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25666 : /*67477*/ /*Scope*/ 47, /*->67525*/
25667 : /*67478*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
25668 : /*67480*/ OPC_MoveParent,
25669 : /*67481*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25670 : /*67483*/ OPC_EmitInteger, MVT::i32, 15,
25671 : /*67486*/ OPC_EmitInteger, MVT::i1, 0,
25672 : /*67489*/ OPC_EmitInteger, MVT::i1, 0,
25673 : /*67492*/ OPC_EmitInteger, MVT::i1, 1,
25674 : /*67495*/ OPC_EmitInteger, MVT::i1, 0,
25675 : /*67498*/ OPC_EmitInteger, MVT::i1, 0,
25676 : /*67501*/ OPC_EmitInteger, MVT::i1, 0,
25677 : /*67504*/ OPC_EmitInteger, MVT::i1, 0,
25678 : /*67507*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V8), 0,
25679 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25680 : // Src: (SIsamplel:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
25681 : // Dst: (IMAGE_SAMPLE_C_L_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25682 : /*67525*/ /*Scope*/ 45, /*->67571*/
25683 : /*67526*/ OPC_MoveParent,
25684 : /*67527*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25685 : /*67529*/ OPC_EmitInteger, MVT::i32, 15,
25686 : /*67532*/ OPC_EmitInteger, MVT::i1, 0,
25687 : /*67535*/ OPC_EmitInteger, MVT::i1, 0,
25688 : /*67538*/ OPC_EmitInteger, MVT::i1, 0,
25689 : /*67541*/ OPC_EmitInteger, MVT::i1, 0,
25690 : /*67544*/ OPC_EmitInteger, MVT::i1, 0,
25691 : /*67547*/ OPC_EmitInteger, MVT::i1, 0,
25692 : /*67550*/ OPC_EmitInteger, MVT::i1, 0,
25693 : /*67553*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V8), 0,
25694 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25695 : // Src: (SIsamplel:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25696 : // Dst: (IMAGE_SAMPLE_L_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25697 : /*67571*/ 0, /*End of Scope*/
25698 : /*67572*/ /*Scope*/ 73|128,1/*201*/, /*->67775*/
25699 : /*67574*/ OPC_CheckChild0Type, MVT::v16i32,
25700 : /*67576*/ OPC_RecordChild1, // #1 = $rsrc
25701 : /*67577*/ OPC_RecordChild2, // #2 = $sampler
25702 : /*67578*/ OPC_MoveChild, 3,
25703 : /*67580*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25704 : /*67583*/ OPC_Scope, 47, /*->67632*/ // 4 children in Scope
25705 : /*67585*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25706 : /*67587*/ OPC_MoveParent,
25707 : /*67588*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25708 : /*67590*/ OPC_EmitInteger, MVT::i32, 15,
25709 : /*67593*/ OPC_EmitInteger, MVT::i1, 0,
25710 : /*67596*/ OPC_EmitInteger, MVT::i1, 0,
25711 : /*67599*/ OPC_EmitInteger, MVT::i1, 1,
25712 : /*67602*/ OPC_EmitInteger, MVT::i1, 0,
25713 : /*67605*/ OPC_EmitInteger, MVT::i1, 0,
25714 : /*67608*/ OPC_EmitInteger, MVT::i1, 0,
25715 : /*67611*/ OPC_EmitInteger, MVT::i1, 0,
25716 : /*67614*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V16), 0,
25717 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25718 : // Src: (SIsamplel:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
25719 : // Dst: (IMAGE_SAMPLE_L_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25720 : /*67632*/ /*Scope*/ 47, /*->67680*/
25721 : /*67633*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
25722 : /*67635*/ OPC_MoveParent,
25723 : /*67636*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25724 : /*67638*/ OPC_EmitInteger, MVT::i32, 15,
25725 : /*67641*/ OPC_EmitInteger, MVT::i1, 0,
25726 : /*67644*/ OPC_EmitInteger, MVT::i1, 0,
25727 : /*67647*/ OPC_EmitInteger, MVT::i1, 0,
25728 : /*67650*/ OPC_EmitInteger, MVT::i1, 0,
25729 : /*67653*/ OPC_EmitInteger, MVT::i1, 0,
25730 : /*67656*/ OPC_EmitInteger, MVT::i1, 0,
25731 : /*67659*/ OPC_EmitInteger, MVT::i1, 0,
25732 : /*67662*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V16), 0,
25733 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25734 : // Src: (SIsamplel:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
25735 : // Dst: (IMAGE_SAMPLE_C_L_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25736 : /*67680*/ /*Scope*/ 47, /*->67728*/
25737 : /*67681*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
25738 : /*67683*/ OPC_MoveParent,
25739 : /*67684*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25740 : /*67686*/ OPC_EmitInteger, MVT::i32, 15,
25741 : /*67689*/ OPC_EmitInteger, MVT::i1, 0,
25742 : /*67692*/ OPC_EmitInteger, MVT::i1, 0,
25743 : /*67695*/ OPC_EmitInteger, MVT::i1, 1,
25744 : /*67698*/ OPC_EmitInteger, MVT::i1, 0,
25745 : /*67701*/ OPC_EmitInteger, MVT::i1, 0,
25746 : /*67704*/ OPC_EmitInteger, MVT::i1, 0,
25747 : /*67707*/ OPC_EmitInteger, MVT::i1, 0,
25748 : /*67710*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_L_V4_V16), 0,
25749 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25750 : // Src: (SIsamplel:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
25751 : // Dst: (IMAGE_SAMPLE_C_L_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25752 : /*67728*/ /*Scope*/ 45, /*->67774*/
25753 : /*67729*/ OPC_MoveParent,
25754 : /*67730*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25755 : /*67732*/ OPC_EmitInteger, MVT::i32, 15,
25756 : /*67735*/ OPC_EmitInteger, MVT::i1, 0,
25757 : /*67738*/ OPC_EmitInteger, MVT::i1, 0,
25758 : /*67741*/ OPC_EmitInteger, MVT::i1, 0,
25759 : /*67744*/ OPC_EmitInteger, MVT::i1, 0,
25760 : /*67747*/ OPC_EmitInteger, MVT::i1, 0,
25761 : /*67750*/ OPC_EmitInteger, MVT::i1, 0,
25762 : /*67753*/ OPC_EmitInteger, MVT::i1, 0,
25763 : /*67756*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_L_V4_V16), 0,
25764 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25765 : // Src: (SIsamplel:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25766 : // Dst: (IMAGE_SAMPLE_L_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25767 : /*67774*/ 0, /*End of Scope*/
25768 : /*67775*/ 0, /*End of Scope*/
25769 : /*67776*/ /*SwitchOpcode*/ 47|128,6/*815*/, TARGET_VAL(AMDGPUISD::SAMPLEB),// ->68595
25770 : /*67780*/ OPC_RecordChild0, // #0 = $addr
25771 : /*67781*/ OPC_Scope, 73|128,1/*201*/, /*->67985*/ // 4 children in Scope
25772 : /*67784*/ OPC_CheckChild0Type, MVT::v2i32,
25773 : /*67786*/ OPC_RecordChild1, // #1 = $rsrc
25774 : /*67787*/ OPC_RecordChild2, // #2 = $sampler
25775 : /*67788*/ OPC_MoveChild, 3,
25776 : /*67790*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25777 : /*67793*/ OPC_Scope, 47, /*->67842*/ // 4 children in Scope
25778 : /*67795*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25779 : /*67797*/ OPC_MoveParent,
25780 : /*67798*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25781 : /*67800*/ OPC_EmitInteger, MVT::i32, 15,
25782 : /*67803*/ OPC_EmitInteger, MVT::i1, 0,
25783 : /*67806*/ OPC_EmitInteger, MVT::i1, 0,
25784 : /*67809*/ OPC_EmitInteger, MVT::i1, 1,
25785 : /*67812*/ OPC_EmitInteger, MVT::i1, 0,
25786 : /*67815*/ OPC_EmitInteger, MVT::i1, 0,
25787 : /*67818*/ OPC_EmitInteger, MVT::i1, 0,
25788 : /*67821*/ OPC_EmitInteger, MVT::i1, 0,
25789 : /*67824*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V2), 0,
25790 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25791 : // Src: (SIsampleb:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
25792 : // Dst: (IMAGE_SAMPLE_B_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25793 : /*67842*/ /*Scope*/ 47, /*->67890*/
25794 : /*67843*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
25795 : /*67845*/ OPC_MoveParent,
25796 : /*67846*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25797 : /*67848*/ OPC_EmitInteger, MVT::i32, 15,
25798 : /*67851*/ OPC_EmitInteger, MVT::i1, 0,
25799 : /*67854*/ OPC_EmitInteger, MVT::i1, 0,
25800 : /*67857*/ OPC_EmitInteger, MVT::i1, 0,
25801 : /*67860*/ OPC_EmitInteger, MVT::i1, 0,
25802 : /*67863*/ OPC_EmitInteger, MVT::i1, 0,
25803 : /*67866*/ OPC_EmitInteger, MVT::i1, 0,
25804 : /*67869*/ OPC_EmitInteger, MVT::i1, 0,
25805 : /*67872*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V2), 0,
25806 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25807 : // Src: (SIsampleb:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
25808 : // Dst: (IMAGE_SAMPLE_C_B_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25809 : /*67890*/ /*Scope*/ 47, /*->67938*/
25810 : /*67891*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
25811 : /*67893*/ OPC_MoveParent,
25812 : /*67894*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25813 : /*67896*/ OPC_EmitInteger, MVT::i32, 15,
25814 : /*67899*/ OPC_EmitInteger, MVT::i1, 0,
25815 : /*67902*/ OPC_EmitInteger, MVT::i1, 0,
25816 : /*67905*/ OPC_EmitInteger, MVT::i1, 1,
25817 : /*67908*/ OPC_EmitInteger, MVT::i1, 0,
25818 : /*67911*/ OPC_EmitInteger, MVT::i1, 0,
25819 : /*67914*/ OPC_EmitInteger, MVT::i1, 0,
25820 : /*67917*/ OPC_EmitInteger, MVT::i1, 0,
25821 : /*67920*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V2), 0,
25822 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25823 : // Src: (SIsampleb:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
25824 : // Dst: (IMAGE_SAMPLE_C_B_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25825 : /*67938*/ /*Scope*/ 45, /*->67984*/
25826 : /*67939*/ OPC_MoveParent,
25827 : /*67940*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25828 : /*67942*/ OPC_EmitInteger, MVT::i32, 15,
25829 : /*67945*/ OPC_EmitInteger, MVT::i1, 0,
25830 : /*67948*/ OPC_EmitInteger, MVT::i1, 0,
25831 : /*67951*/ OPC_EmitInteger, MVT::i1, 0,
25832 : /*67954*/ OPC_EmitInteger, MVT::i1, 0,
25833 : /*67957*/ OPC_EmitInteger, MVT::i1, 0,
25834 : /*67960*/ OPC_EmitInteger, MVT::i1, 0,
25835 : /*67963*/ OPC_EmitInteger, MVT::i1, 0,
25836 : /*67966*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V2), 0,
25837 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25838 : // Src: (SIsampleb:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25839 : // Dst: (IMAGE_SAMPLE_B_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25840 : /*67984*/ 0, /*End of Scope*/
25841 : /*67985*/ /*Scope*/ 73|128,1/*201*/, /*->68188*/
25842 : /*67987*/ OPC_CheckChild0Type, MVT::v4i32,
25843 : /*67989*/ OPC_RecordChild1, // #1 = $rsrc
25844 : /*67990*/ OPC_RecordChild2, // #2 = $sampler
25845 : /*67991*/ OPC_MoveChild, 3,
25846 : /*67993*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25847 : /*67996*/ OPC_Scope, 47, /*->68045*/ // 4 children in Scope
25848 : /*67998*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25849 : /*68000*/ OPC_MoveParent,
25850 : /*68001*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25851 : /*68003*/ OPC_EmitInteger, MVT::i32, 15,
25852 : /*68006*/ OPC_EmitInteger, MVT::i1, 0,
25853 : /*68009*/ OPC_EmitInteger, MVT::i1, 0,
25854 : /*68012*/ OPC_EmitInteger, MVT::i1, 1,
25855 : /*68015*/ OPC_EmitInteger, MVT::i1, 0,
25856 : /*68018*/ OPC_EmitInteger, MVT::i1, 0,
25857 : /*68021*/ OPC_EmitInteger, MVT::i1, 0,
25858 : /*68024*/ OPC_EmitInteger, MVT::i1, 0,
25859 : /*68027*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V4), 0,
25860 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25861 : // Src: (SIsampleb:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
25862 : // Dst: (IMAGE_SAMPLE_B_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25863 : /*68045*/ /*Scope*/ 47, /*->68093*/
25864 : /*68046*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
25865 : /*68048*/ OPC_MoveParent,
25866 : /*68049*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25867 : /*68051*/ OPC_EmitInteger, MVT::i32, 15,
25868 : /*68054*/ OPC_EmitInteger, MVT::i1, 0,
25869 : /*68057*/ OPC_EmitInteger, MVT::i1, 0,
25870 : /*68060*/ OPC_EmitInteger, MVT::i1, 0,
25871 : /*68063*/ OPC_EmitInteger, MVT::i1, 0,
25872 : /*68066*/ OPC_EmitInteger, MVT::i1, 0,
25873 : /*68069*/ OPC_EmitInteger, MVT::i1, 0,
25874 : /*68072*/ OPC_EmitInteger, MVT::i1, 0,
25875 : /*68075*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V4), 0,
25876 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25877 : // Src: (SIsampleb:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
25878 : // Dst: (IMAGE_SAMPLE_C_B_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25879 : /*68093*/ /*Scope*/ 47, /*->68141*/
25880 : /*68094*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
25881 : /*68096*/ OPC_MoveParent,
25882 : /*68097*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25883 : /*68099*/ OPC_EmitInteger, MVT::i32, 15,
25884 : /*68102*/ OPC_EmitInteger, MVT::i1, 0,
25885 : /*68105*/ OPC_EmitInteger, MVT::i1, 0,
25886 : /*68108*/ OPC_EmitInteger, MVT::i1, 1,
25887 : /*68111*/ OPC_EmitInteger, MVT::i1, 0,
25888 : /*68114*/ OPC_EmitInteger, MVT::i1, 0,
25889 : /*68117*/ OPC_EmitInteger, MVT::i1, 0,
25890 : /*68120*/ OPC_EmitInteger, MVT::i1, 0,
25891 : /*68123*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V4), 0,
25892 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25893 : // Src: (SIsampleb:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
25894 : // Dst: (IMAGE_SAMPLE_C_B_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25895 : /*68141*/ /*Scope*/ 45, /*->68187*/
25896 : /*68142*/ OPC_MoveParent,
25897 : /*68143*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25898 : /*68145*/ OPC_EmitInteger, MVT::i32, 15,
25899 : /*68148*/ OPC_EmitInteger, MVT::i1, 0,
25900 : /*68151*/ OPC_EmitInteger, MVT::i1, 0,
25901 : /*68154*/ OPC_EmitInteger, MVT::i1, 0,
25902 : /*68157*/ OPC_EmitInteger, MVT::i1, 0,
25903 : /*68160*/ OPC_EmitInteger, MVT::i1, 0,
25904 : /*68163*/ OPC_EmitInteger, MVT::i1, 0,
25905 : /*68166*/ OPC_EmitInteger, MVT::i1, 0,
25906 : /*68169*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V4), 0,
25907 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25908 : // Src: (SIsampleb:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25909 : // Dst: (IMAGE_SAMPLE_B_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25910 : /*68187*/ 0, /*End of Scope*/
25911 : /*68188*/ /*Scope*/ 73|128,1/*201*/, /*->68391*/
25912 : /*68190*/ OPC_CheckChild0Type, MVT::v8i32,
25913 : /*68192*/ OPC_RecordChild1, // #1 = $rsrc
25914 : /*68193*/ OPC_RecordChild2, // #2 = $sampler
25915 : /*68194*/ OPC_MoveChild, 3,
25916 : /*68196*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25917 : /*68199*/ OPC_Scope, 47, /*->68248*/ // 4 children in Scope
25918 : /*68201*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25919 : /*68203*/ OPC_MoveParent,
25920 : /*68204*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25921 : /*68206*/ OPC_EmitInteger, MVT::i32, 15,
25922 : /*68209*/ OPC_EmitInteger, MVT::i1, 0,
25923 : /*68212*/ OPC_EmitInteger, MVT::i1, 0,
25924 : /*68215*/ OPC_EmitInteger, MVT::i1, 1,
25925 : /*68218*/ OPC_EmitInteger, MVT::i1, 0,
25926 : /*68221*/ OPC_EmitInteger, MVT::i1, 0,
25927 : /*68224*/ OPC_EmitInteger, MVT::i1, 0,
25928 : /*68227*/ OPC_EmitInteger, MVT::i1, 0,
25929 : /*68230*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V8), 0,
25930 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25931 : // Src: (SIsampleb:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
25932 : // Dst: (IMAGE_SAMPLE_B_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25933 : /*68248*/ /*Scope*/ 47, /*->68296*/
25934 : /*68249*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
25935 : /*68251*/ OPC_MoveParent,
25936 : /*68252*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25937 : /*68254*/ OPC_EmitInteger, MVT::i32, 15,
25938 : /*68257*/ OPC_EmitInteger, MVT::i1, 0,
25939 : /*68260*/ OPC_EmitInteger, MVT::i1, 0,
25940 : /*68263*/ OPC_EmitInteger, MVT::i1, 0,
25941 : /*68266*/ OPC_EmitInteger, MVT::i1, 0,
25942 : /*68269*/ OPC_EmitInteger, MVT::i1, 0,
25943 : /*68272*/ OPC_EmitInteger, MVT::i1, 0,
25944 : /*68275*/ OPC_EmitInteger, MVT::i1, 0,
25945 : /*68278*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V8), 0,
25946 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25947 : // Src: (SIsampleb:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
25948 : // Dst: (IMAGE_SAMPLE_C_B_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25949 : /*68296*/ /*Scope*/ 47, /*->68344*/
25950 : /*68297*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
25951 : /*68299*/ OPC_MoveParent,
25952 : /*68300*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25953 : /*68302*/ OPC_EmitInteger, MVT::i32, 15,
25954 : /*68305*/ OPC_EmitInteger, MVT::i1, 0,
25955 : /*68308*/ OPC_EmitInteger, MVT::i1, 0,
25956 : /*68311*/ OPC_EmitInteger, MVT::i1, 1,
25957 : /*68314*/ OPC_EmitInteger, MVT::i1, 0,
25958 : /*68317*/ OPC_EmitInteger, MVT::i1, 0,
25959 : /*68320*/ OPC_EmitInteger, MVT::i1, 0,
25960 : /*68323*/ OPC_EmitInteger, MVT::i1, 0,
25961 : /*68326*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V8), 0,
25962 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25963 : // Src: (SIsampleb:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
25964 : // Dst: (IMAGE_SAMPLE_C_B_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25965 : /*68344*/ /*Scope*/ 45, /*->68390*/
25966 : /*68345*/ OPC_MoveParent,
25967 : /*68346*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25968 : /*68348*/ OPC_EmitInteger, MVT::i32, 15,
25969 : /*68351*/ OPC_EmitInteger, MVT::i1, 0,
25970 : /*68354*/ OPC_EmitInteger, MVT::i1, 0,
25971 : /*68357*/ OPC_EmitInteger, MVT::i1, 0,
25972 : /*68360*/ OPC_EmitInteger, MVT::i1, 0,
25973 : /*68363*/ OPC_EmitInteger, MVT::i1, 0,
25974 : /*68366*/ OPC_EmitInteger, MVT::i1, 0,
25975 : /*68369*/ OPC_EmitInteger, MVT::i1, 0,
25976 : /*68372*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V8), 0,
25977 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
25978 : // Src: (SIsampleb:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
25979 : // Dst: (IMAGE_SAMPLE_B_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
25980 : /*68390*/ 0, /*End of Scope*/
25981 : /*68391*/ /*Scope*/ 73|128,1/*201*/, /*->68594*/
25982 : /*68393*/ OPC_CheckChild0Type, MVT::v16i32,
25983 : /*68395*/ OPC_RecordChild1, // #1 = $rsrc
25984 : /*68396*/ OPC_RecordChild2, // #2 = $sampler
25985 : /*68397*/ OPC_MoveChild, 3,
25986 : /*68399*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
25987 : /*68402*/ OPC_Scope, 47, /*->68451*/ // 4 children in Scope
25988 : /*68404*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
25989 : /*68406*/ OPC_MoveParent,
25990 : /*68407*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
25991 : /*68409*/ OPC_EmitInteger, MVT::i32, 15,
25992 : /*68412*/ OPC_EmitInteger, MVT::i1, 0,
25993 : /*68415*/ OPC_EmitInteger, MVT::i1, 0,
25994 : /*68418*/ OPC_EmitInteger, MVT::i1, 1,
25995 : /*68421*/ OPC_EmitInteger, MVT::i1, 0,
25996 : /*68424*/ OPC_EmitInteger, MVT::i1, 0,
25997 : /*68427*/ OPC_EmitInteger, MVT::i1, 0,
25998 : /*68430*/ OPC_EmitInteger, MVT::i1, 0,
25999 : /*68433*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V16), 0,
26000 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26001 : // Src: (SIsampleb:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
26002 : // Dst: (IMAGE_SAMPLE_B_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26003 : /*68451*/ /*Scope*/ 47, /*->68499*/
26004 : /*68452*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
26005 : /*68454*/ OPC_MoveParent,
26006 : /*68455*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26007 : /*68457*/ OPC_EmitInteger, MVT::i32, 15,
26008 : /*68460*/ OPC_EmitInteger, MVT::i1, 0,
26009 : /*68463*/ OPC_EmitInteger, MVT::i1, 0,
26010 : /*68466*/ OPC_EmitInteger, MVT::i1, 0,
26011 : /*68469*/ OPC_EmitInteger, MVT::i1, 0,
26012 : /*68472*/ OPC_EmitInteger, MVT::i1, 0,
26013 : /*68475*/ OPC_EmitInteger, MVT::i1, 0,
26014 : /*68478*/ OPC_EmitInteger, MVT::i1, 0,
26015 : /*68481*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V16), 0,
26016 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26017 : // Src: (SIsampleb:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
26018 : // Dst: (IMAGE_SAMPLE_C_B_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26019 : /*68499*/ /*Scope*/ 47, /*->68547*/
26020 : /*68500*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
26021 : /*68502*/ OPC_MoveParent,
26022 : /*68503*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26023 : /*68505*/ OPC_EmitInteger, MVT::i32, 15,
26024 : /*68508*/ OPC_EmitInteger, MVT::i1, 0,
26025 : /*68511*/ OPC_EmitInteger, MVT::i1, 0,
26026 : /*68514*/ OPC_EmitInteger, MVT::i1, 1,
26027 : /*68517*/ OPC_EmitInteger, MVT::i1, 0,
26028 : /*68520*/ OPC_EmitInteger, MVT::i1, 0,
26029 : /*68523*/ OPC_EmitInteger, MVT::i1, 0,
26030 : /*68526*/ OPC_EmitInteger, MVT::i1, 0,
26031 : /*68529*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_B_V4_V16), 0,
26032 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26033 : // Src: (SIsampleb:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
26034 : // Dst: (IMAGE_SAMPLE_C_B_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26035 : /*68547*/ /*Scope*/ 45, /*->68593*/
26036 : /*68548*/ OPC_MoveParent,
26037 : /*68549*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26038 : /*68551*/ OPC_EmitInteger, MVT::i32, 15,
26039 : /*68554*/ OPC_EmitInteger, MVT::i1, 0,
26040 : /*68557*/ OPC_EmitInteger, MVT::i1, 0,
26041 : /*68560*/ OPC_EmitInteger, MVT::i1, 0,
26042 : /*68563*/ OPC_EmitInteger, MVT::i1, 0,
26043 : /*68566*/ OPC_EmitInteger, MVT::i1, 0,
26044 : /*68569*/ OPC_EmitInteger, MVT::i1, 0,
26045 : /*68572*/ OPC_EmitInteger, MVT::i1, 0,
26046 : /*68575*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_B_V4_V16), 0,
26047 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26048 : // Src: (SIsampleb:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
26049 : // Dst: (IMAGE_SAMPLE_B_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26050 : /*68593*/ 0, /*End of Scope*/
26051 : /*68594*/ 0, /*End of Scope*/
26052 : /*68595*/ /*SwitchOpcode*/ 47|128,6/*815*/, TARGET_VAL(AMDGPUISD::SAMPLED),// ->69414
26053 : /*68599*/ OPC_RecordChild0, // #0 = $addr
26054 : /*68600*/ OPC_Scope, 73|128,1/*201*/, /*->68804*/ // 4 children in Scope
26055 : /*68603*/ OPC_CheckChild0Type, MVT::v2i32,
26056 : /*68605*/ OPC_RecordChild1, // #1 = $rsrc
26057 : /*68606*/ OPC_RecordChild2, // #2 = $sampler
26058 : /*68607*/ OPC_MoveChild, 3,
26059 : /*68609*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
26060 : /*68612*/ OPC_Scope, 47, /*->68661*/ // 4 children in Scope
26061 : /*68614*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
26062 : /*68616*/ OPC_MoveParent,
26063 : /*68617*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26064 : /*68619*/ OPC_EmitInteger, MVT::i32, 15,
26065 : /*68622*/ OPC_EmitInteger, MVT::i1, 0,
26066 : /*68625*/ OPC_EmitInteger, MVT::i1, 0,
26067 : /*68628*/ OPC_EmitInteger, MVT::i1, 1,
26068 : /*68631*/ OPC_EmitInteger, MVT::i1, 0,
26069 : /*68634*/ OPC_EmitInteger, MVT::i1, 0,
26070 : /*68637*/ OPC_EmitInteger, MVT::i1, 0,
26071 : /*68640*/ OPC_EmitInteger, MVT::i1, 0,
26072 : /*68643*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V2), 0,
26073 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26074 : // Src: (SIsampled:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
26075 : // Dst: (IMAGE_SAMPLE_D_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26076 : /*68661*/ /*Scope*/ 47, /*->68709*/
26077 : /*68662*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
26078 : /*68664*/ OPC_MoveParent,
26079 : /*68665*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26080 : /*68667*/ OPC_EmitInteger, MVT::i32, 15,
26081 : /*68670*/ OPC_EmitInteger, MVT::i1, 0,
26082 : /*68673*/ OPC_EmitInteger, MVT::i1, 0,
26083 : /*68676*/ OPC_EmitInteger, MVT::i1, 0,
26084 : /*68679*/ OPC_EmitInteger, MVT::i1, 0,
26085 : /*68682*/ OPC_EmitInteger, MVT::i1, 0,
26086 : /*68685*/ OPC_EmitInteger, MVT::i1, 0,
26087 : /*68688*/ OPC_EmitInteger, MVT::i1, 0,
26088 : /*68691*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V2), 0,
26089 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26090 : // Src: (SIsampled:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
26091 : // Dst: (IMAGE_SAMPLE_C_D_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26092 : /*68709*/ /*Scope*/ 47, /*->68757*/
26093 : /*68710*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
26094 : /*68712*/ OPC_MoveParent,
26095 : /*68713*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26096 : /*68715*/ OPC_EmitInteger, MVT::i32, 15,
26097 : /*68718*/ OPC_EmitInteger, MVT::i1, 0,
26098 : /*68721*/ OPC_EmitInteger, MVT::i1, 0,
26099 : /*68724*/ OPC_EmitInteger, MVT::i1, 1,
26100 : /*68727*/ OPC_EmitInteger, MVT::i1, 0,
26101 : /*68730*/ OPC_EmitInteger, MVT::i1, 0,
26102 : /*68733*/ OPC_EmitInteger, MVT::i1, 0,
26103 : /*68736*/ OPC_EmitInteger, MVT::i1, 0,
26104 : /*68739*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V2), 0,
26105 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26106 : // Src: (SIsampled:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
26107 : // Dst: (IMAGE_SAMPLE_C_D_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26108 : /*68757*/ /*Scope*/ 45, /*->68803*/
26109 : /*68758*/ OPC_MoveParent,
26110 : /*68759*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26111 : /*68761*/ OPC_EmitInteger, MVT::i32, 15,
26112 : /*68764*/ OPC_EmitInteger, MVT::i1, 0,
26113 : /*68767*/ OPC_EmitInteger, MVT::i1, 0,
26114 : /*68770*/ OPC_EmitInteger, MVT::i1, 0,
26115 : /*68773*/ OPC_EmitInteger, MVT::i1, 0,
26116 : /*68776*/ OPC_EmitInteger, MVT::i1, 0,
26117 : /*68779*/ OPC_EmitInteger, MVT::i1, 0,
26118 : /*68782*/ OPC_EmitInteger, MVT::i1, 0,
26119 : /*68785*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V2), 0,
26120 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26121 : // Src: (SIsampled:v4f32 v2i32:v2i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
26122 : // Dst: (IMAGE_SAMPLE_D_V4_V2:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v2i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26123 : /*68803*/ 0, /*End of Scope*/
26124 : /*68804*/ /*Scope*/ 73|128,1/*201*/, /*->69007*/
26125 : /*68806*/ OPC_CheckChild0Type, MVT::v4i32,
26126 : /*68808*/ OPC_RecordChild1, // #1 = $rsrc
26127 : /*68809*/ OPC_RecordChild2, // #2 = $sampler
26128 : /*68810*/ OPC_MoveChild, 3,
26129 : /*68812*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
26130 : /*68815*/ OPC_Scope, 47, /*->68864*/ // 4 children in Scope
26131 : /*68817*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
26132 : /*68819*/ OPC_MoveParent,
26133 : /*68820*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26134 : /*68822*/ OPC_EmitInteger, MVT::i32, 15,
26135 : /*68825*/ OPC_EmitInteger, MVT::i1, 0,
26136 : /*68828*/ OPC_EmitInteger, MVT::i1, 0,
26137 : /*68831*/ OPC_EmitInteger, MVT::i1, 1,
26138 : /*68834*/ OPC_EmitInteger, MVT::i1, 0,
26139 : /*68837*/ OPC_EmitInteger, MVT::i1, 0,
26140 : /*68840*/ OPC_EmitInteger, MVT::i1, 0,
26141 : /*68843*/ OPC_EmitInteger, MVT::i1, 0,
26142 : /*68846*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V4), 0,
26143 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26144 : // Src: (SIsampled:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
26145 : // Dst: (IMAGE_SAMPLE_D_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26146 : /*68864*/ /*Scope*/ 47, /*->68912*/
26147 : /*68865*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
26148 : /*68867*/ OPC_MoveParent,
26149 : /*68868*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26150 : /*68870*/ OPC_EmitInteger, MVT::i32, 15,
26151 : /*68873*/ OPC_EmitInteger, MVT::i1, 0,
26152 : /*68876*/ OPC_EmitInteger, MVT::i1, 0,
26153 : /*68879*/ OPC_EmitInteger, MVT::i1, 0,
26154 : /*68882*/ OPC_EmitInteger, MVT::i1, 0,
26155 : /*68885*/ OPC_EmitInteger, MVT::i1, 0,
26156 : /*68888*/ OPC_EmitInteger, MVT::i1, 0,
26157 : /*68891*/ OPC_EmitInteger, MVT::i1, 0,
26158 : /*68894*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V4), 0,
26159 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26160 : // Src: (SIsampled:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
26161 : // Dst: (IMAGE_SAMPLE_C_D_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26162 : /*68912*/ /*Scope*/ 47, /*->68960*/
26163 : /*68913*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
26164 : /*68915*/ OPC_MoveParent,
26165 : /*68916*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26166 : /*68918*/ OPC_EmitInteger, MVT::i32, 15,
26167 : /*68921*/ OPC_EmitInteger, MVT::i1, 0,
26168 : /*68924*/ OPC_EmitInteger, MVT::i1, 0,
26169 : /*68927*/ OPC_EmitInteger, MVT::i1, 1,
26170 : /*68930*/ OPC_EmitInteger, MVT::i1, 0,
26171 : /*68933*/ OPC_EmitInteger, MVT::i1, 0,
26172 : /*68936*/ OPC_EmitInteger, MVT::i1, 0,
26173 : /*68939*/ OPC_EmitInteger, MVT::i1, 0,
26174 : /*68942*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V4), 0,
26175 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26176 : // Src: (SIsampled:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
26177 : // Dst: (IMAGE_SAMPLE_C_D_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26178 : /*68960*/ /*Scope*/ 45, /*->69006*/
26179 : /*68961*/ OPC_MoveParent,
26180 : /*68962*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26181 : /*68964*/ OPC_EmitInteger, MVT::i32, 15,
26182 : /*68967*/ OPC_EmitInteger, MVT::i1, 0,
26183 : /*68970*/ OPC_EmitInteger, MVT::i1, 0,
26184 : /*68973*/ OPC_EmitInteger, MVT::i1, 0,
26185 : /*68976*/ OPC_EmitInteger, MVT::i1, 0,
26186 : /*68979*/ OPC_EmitInteger, MVT::i1, 0,
26187 : /*68982*/ OPC_EmitInteger, MVT::i1, 0,
26188 : /*68985*/ OPC_EmitInteger, MVT::i1, 0,
26189 : /*68988*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V4), 0,
26190 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26191 : // Src: (SIsampled:v4f32 v4i32:v4i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
26192 : // Dst: (IMAGE_SAMPLE_D_V4_V4:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v4i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26193 : /*69006*/ 0, /*End of Scope*/
26194 : /*69007*/ /*Scope*/ 73|128,1/*201*/, /*->69210*/
26195 : /*69009*/ OPC_CheckChild0Type, MVT::v8i32,
26196 : /*69011*/ OPC_RecordChild1, // #1 = $rsrc
26197 : /*69012*/ OPC_RecordChild2, // #2 = $sampler
26198 : /*69013*/ OPC_MoveChild, 3,
26199 : /*69015*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
26200 : /*69018*/ OPC_Scope, 47, /*->69067*/ // 4 children in Scope
26201 : /*69020*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
26202 : /*69022*/ OPC_MoveParent,
26203 : /*69023*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26204 : /*69025*/ OPC_EmitInteger, MVT::i32, 15,
26205 : /*69028*/ OPC_EmitInteger, MVT::i1, 0,
26206 : /*69031*/ OPC_EmitInteger, MVT::i1, 0,
26207 : /*69034*/ OPC_EmitInteger, MVT::i1, 1,
26208 : /*69037*/ OPC_EmitInteger, MVT::i1, 0,
26209 : /*69040*/ OPC_EmitInteger, MVT::i1, 0,
26210 : /*69043*/ OPC_EmitInteger, MVT::i1, 0,
26211 : /*69046*/ OPC_EmitInteger, MVT::i1, 0,
26212 : /*69049*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V8), 0,
26213 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26214 : // Src: (SIsampled:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
26215 : // Dst: (IMAGE_SAMPLE_D_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26216 : /*69067*/ /*Scope*/ 47, /*->69115*/
26217 : /*69068*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
26218 : /*69070*/ OPC_MoveParent,
26219 : /*69071*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26220 : /*69073*/ OPC_EmitInteger, MVT::i32, 15,
26221 : /*69076*/ OPC_EmitInteger, MVT::i1, 0,
26222 : /*69079*/ OPC_EmitInteger, MVT::i1, 0,
26223 : /*69082*/ OPC_EmitInteger, MVT::i1, 0,
26224 : /*69085*/ OPC_EmitInteger, MVT::i1, 0,
26225 : /*69088*/ OPC_EmitInteger, MVT::i1, 0,
26226 : /*69091*/ OPC_EmitInteger, MVT::i1, 0,
26227 : /*69094*/ OPC_EmitInteger, MVT::i1, 0,
26228 : /*69097*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V8), 0,
26229 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26230 : // Src: (SIsampled:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
26231 : // Dst: (IMAGE_SAMPLE_C_D_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26232 : /*69115*/ /*Scope*/ 47, /*->69163*/
26233 : /*69116*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
26234 : /*69118*/ OPC_MoveParent,
26235 : /*69119*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26236 : /*69121*/ OPC_EmitInteger, MVT::i32, 15,
26237 : /*69124*/ OPC_EmitInteger, MVT::i1, 0,
26238 : /*69127*/ OPC_EmitInteger, MVT::i1, 0,
26239 : /*69130*/ OPC_EmitInteger, MVT::i1, 1,
26240 : /*69133*/ OPC_EmitInteger, MVT::i1, 0,
26241 : /*69136*/ OPC_EmitInteger, MVT::i1, 0,
26242 : /*69139*/ OPC_EmitInteger, MVT::i1, 0,
26243 : /*69142*/ OPC_EmitInteger, MVT::i1, 0,
26244 : /*69145*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V8), 0,
26245 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26246 : // Src: (SIsampled:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
26247 : // Dst: (IMAGE_SAMPLE_C_D_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26248 : /*69163*/ /*Scope*/ 45, /*->69209*/
26249 : /*69164*/ OPC_MoveParent,
26250 : /*69165*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26251 : /*69167*/ OPC_EmitInteger, MVT::i32, 15,
26252 : /*69170*/ OPC_EmitInteger, MVT::i1, 0,
26253 : /*69173*/ OPC_EmitInteger, MVT::i1, 0,
26254 : /*69176*/ OPC_EmitInteger, MVT::i1, 0,
26255 : /*69179*/ OPC_EmitInteger, MVT::i1, 0,
26256 : /*69182*/ OPC_EmitInteger, MVT::i1, 0,
26257 : /*69185*/ OPC_EmitInteger, MVT::i1, 0,
26258 : /*69188*/ OPC_EmitInteger, MVT::i1, 0,
26259 : /*69191*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V8), 0,
26260 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26261 : // Src: (SIsampled:v4f32 v8i32:v8i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
26262 : // Dst: (IMAGE_SAMPLE_D_V4_V8:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v8i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26263 : /*69209*/ 0, /*End of Scope*/
26264 : /*69210*/ /*Scope*/ 73|128,1/*201*/, /*->69413*/
26265 : /*69212*/ OPC_CheckChild0Type, MVT::v16i32,
26266 : /*69214*/ OPC_RecordChild1, // #1 = $rsrc
26267 : /*69215*/ OPC_RecordChild2, // #2 = $sampler
26268 : /*69216*/ OPC_MoveChild, 3,
26269 : /*69218*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
26270 : /*69221*/ OPC_Scope, 47, /*->69270*/ // 4 children in Scope
26271 : /*69223*/ OPC_CheckPredicate, 116, // Predicate_TEX_ARRAY
26272 : /*69225*/ OPC_MoveParent,
26273 : /*69226*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26274 : /*69228*/ OPC_EmitInteger, MVT::i32, 15,
26275 : /*69231*/ OPC_EmitInteger, MVT::i1, 0,
26276 : /*69234*/ OPC_EmitInteger, MVT::i1, 0,
26277 : /*69237*/ OPC_EmitInteger, MVT::i1, 1,
26278 : /*69240*/ OPC_EmitInteger, MVT::i1, 0,
26279 : /*69243*/ OPC_EmitInteger, MVT::i1, 0,
26280 : /*69246*/ OPC_EmitInteger, MVT::i1, 0,
26281 : /*69249*/ OPC_EmitInteger, MVT::i1, 0,
26282 : /*69252*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V16), 0,
26283 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26284 : // Src: (SIsampled:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_ARRAY>>) - Complexity = 7
26285 : // Dst: (IMAGE_SAMPLE_D_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26286 : /*69270*/ /*Scope*/ 47, /*->69318*/
26287 : /*69271*/ OPC_CheckPredicate, 119, // Predicate_TEX_SHADOW
26288 : /*69273*/ OPC_MoveParent,
26289 : /*69274*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26290 : /*69276*/ OPC_EmitInteger, MVT::i32, 15,
26291 : /*69279*/ OPC_EmitInteger, MVT::i1, 0,
26292 : /*69282*/ OPC_EmitInteger, MVT::i1, 0,
26293 : /*69285*/ OPC_EmitInteger, MVT::i1, 0,
26294 : /*69288*/ OPC_EmitInteger, MVT::i1, 0,
26295 : /*69291*/ OPC_EmitInteger, MVT::i1, 0,
26296 : /*69294*/ OPC_EmitInteger, MVT::i1, 0,
26297 : /*69297*/ OPC_EmitInteger, MVT::i1, 0,
26298 : /*69300*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V16), 0,
26299 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26300 : // Src: (SIsampled:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW>>) - Complexity = 7
26301 : // Dst: (IMAGE_SAMPLE_C_D_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26302 : /*69318*/ /*Scope*/ 47, /*->69366*/
26303 : /*69319*/ OPC_CheckPredicate, 144, // Predicate_TEX_SHADOW_ARRAY
26304 : /*69321*/ OPC_MoveParent,
26305 : /*69322*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26306 : /*69324*/ OPC_EmitInteger, MVT::i32, 15,
26307 : /*69327*/ OPC_EmitInteger, MVT::i1, 0,
26308 : /*69330*/ OPC_EmitInteger, MVT::i1, 0,
26309 : /*69333*/ OPC_EmitInteger, MVT::i1, 1,
26310 : /*69336*/ OPC_EmitInteger, MVT::i1, 0,
26311 : /*69339*/ OPC_EmitInteger, MVT::i1, 0,
26312 : /*69342*/ OPC_EmitInteger, MVT::i1, 0,
26313 : /*69345*/ OPC_EmitInteger, MVT::i1, 0,
26314 : /*69348*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_C_D_V4_V16), 0,
26315 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26316 : // Src: (SIsampled:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)<<P:Predicate_TEX_SHADOW_ARRAY>>) - Complexity = 7
26317 : // Dst: (IMAGE_SAMPLE_C_D_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 1:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26318 : /*69366*/ /*Scope*/ 45, /*->69412*/
26319 : /*69367*/ OPC_MoveParent,
26320 : /*69368*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26321 : /*69370*/ OPC_EmitInteger, MVT::i32, 15,
26322 : /*69373*/ OPC_EmitInteger, MVT::i1, 0,
26323 : /*69376*/ OPC_EmitInteger, MVT::i1, 0,
26324 : /*69379*/ OPC_EmitInteger, MVT::i1, 0,
26325 : /*69382*/ OPC_EmitInteger, MVT::i1, 0,
26326 : /*69385*/ OPC_EmitInteger, MVT::i1, 0,
26327 : /*69388*/ OPC_EmitInteger, MVT::i1, 0,
26328 : /*69391*/ OPC_EmitInteger, MVT::i1, 0,
26329 : /*69394*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::IMAGE_SAMPLE_D_V4_V16), 0,
26330 : 1/*#VTs*/, MVT::v4f32, 11/*#Ops*/, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2,
26331 : // Src: (SIsampled:v4f32 v16i32:v16i32:$addr, v32i8:v32i8:$rsrc, v4i32:v4i32:$sampler, (imm:i32)) - Complexity = 6
26332 : // Dst: (IMAGE_SAMPLE_D_V4_V16:v4f32 15:i32, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, 0:i1, ?:v16i32:$addr, ?:v32i8:$rsrc, ?:v4i32:$sampler)
26333 : /*69412*/ 0, /*End of Scope*/
26334 : /*69413*/ 0, /*End of Scope*/
26335 : /*69414*/ /*SwitchOpcode*/ 39, TARGET_VAL(AMDGPUISD::LOAD_INPUT),// ->69456
26336 : /*69417*/ OPC_RecordChild0, // #0 = $tlst
26337 : /*69418*/ OPC_RecordChild1, // #1 = $attr_offset
26338 : /*69419*/ OPC_MoveChild, 1,
26339 : /*69421*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
26340 : /*69424*/ OPC_MoveParent,
26341 : /*69425*/ OPC_RecordChild2, // #2 = $buf_idx_vgpr
26342 : /*69426*/ OPC_CheckPatternPredicate, 0, // (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
26343 : /*69428*/ OPC_EmitInteger, MVT::i32, 0,
26344 : /*69431*/ OPC_EmitConvertToTarget, 1,
26345 : /*69433*/ OPC_EmitInteger, MVT::i1, 0,
26346 : /*69436*/ OPC_EmitInteger, MVT::i1, 0,
26347 : /*69439*/ OPC_EmitInteger, MVT::i1, 0,
26348 : /*69442*/ OPC_MorphNodeTo, TARGET_VAL(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN), 0,
26349 : 1/*#VTs*/, MVT::v4f32, 7/*#Ops*/, 2, 0, 3, 4, 5, 6, 7,
26350 : // Src: (SIload_input:v4f32 v4i32:v4i32:$tlst, (imm:i16):$attr_offset, i32:i32:$buf_idx_vgpr) - Complexity = 6
26351 : // Dst: (BUFFER_LOAD_FORMAT_XYZW_IDXEN:v4f32 ?:i32:$buf_idx_vgpr, ?:v4i32:$tlst, 0:i32, (imm:i16):$attr_offset, 0:i1, 0:i1, 0:i1)
26352 : /*69456*/ 0, // EndSwitchOpcode
26353 : 0
26354 : }; // Total Array size is 69458 bytes
26355 :
26356 : // Opcode Histogram:
26357 : // #OPC_Scope = 417
26358 : // #OPC_RecordNode = 1171
26359 : // #OPC_RecordChild = 2203
26360 : // #OPC_RecordMemRef = 16
26361 : // #OPC_CaptureGlueInput = 23
26362 : // #OPC_MoveChild = 1413
26363 : // #OPC_MoveParent = 1638
26364 : // #OPC_CheckSame = 0
26365 : // #OPC_CheckChildSame = 89
26366 : // #OPC_CheckPatternPredicate = 1140
26367 : // #OPC_CheckPredicate = 458
26368 : // #OPC_CheckOpcode = 419
26369 : // #OPC_SwitchOpcode = 3
26370 : // #OPC_CheckType = 610
26371 : // #OPC_SwitchType = 101
26372 : // #OPC_CheckChildType = 433
26373 : // #OPC_CheckInteger = 16
26374 : // #OPC_CheckChildInteger = 236
26375 : // #OPC_CheckCondCode = 9
26376 : // #OPC_CheckValueType = 4
26377 : // #OPC_CheckComplexPat = 298
26378 : // #OPC_CheckAndImm = 0
26379 : // #OPC_CheckOrImm = 0
26380 : // #OPC_CheckFoldableChainNode = 0
26381 : // #OPC_EmitInteger = 4442
26382 : // #OPC_EmitStringInteger = 221
26383 : // #OPC_EmitRegister = 263
26384 : // #OPC_EmitConvertToTarget = 265
26385 : // #OPC_EmitMergeInputChains = 263
26386 : // #OPC_EmitCopyToReg = 2
26387 : // #OPC_EmitNode = 189
26388 : // #OPC_EmitNodeXForm = 2112
26389 : // #OPC_MarkGlueResults = 0
26390 : // #OPC_CompleteMatch = 33
26391 : // #OPC_MorphNodeTo = 1408
26392 :
26393 : #undef TARGET_VAL
26394 156451 : return SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));
26395 : }
26396 :
26397 187061 : bool CheckPatternPredicate(unsigned PredNo) const override {
26398 187061 : switch (PredNo) {
26399 0 : default: llvm_unreachable("Invalid predicate in table?");
26400 50434 : case 0: return (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS);
26401 47549 : case 1: return (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true);
26402 7877 : case 2: return (Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS);
26403 2454 : case 3: return (Subtarget->hasCaymanISA());
26404 3956 : case 4: return (Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && !Subtarget->hasCaymanISA());
26405 62 : case 5: return (Subtarget->hasFlatAddressSpace());
26406 20621 : case 6: return (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS);
26407 4031 : case 7: return (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS);
26408 7214 : case 8: return (Subtarget->getGeneration() <= AMDGPUSubtarget::R700);
26409 42524 : case 9: return (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS);
26410 23 : case 10: return (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS);
26411 118 : case 11: return (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS);
26412 131 : case 12: return (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true) && (Subtarget->getLDSBankCount() == 32);
26413 5 : case 13: return (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) && (true) && (Subtarget->getLDSBankCount() == 16);
26414 6 : case 14: return (TM.Options.UnsafeFPMath);
26415 56 : case 15: return (Subtarget->getGeneration() == AMDGPUSubtarget::R700);
26416 : }
26417 : }
26418 :
26419 773089 : bool CheckNodePredicate(SDNode *Node,
26420 : unsigned PredNo) const override {
26421 773089 : switch (PredNo) {
26422 0 : default: llvm_unreachable("Invalid predicate in table?");
26423 : case 0: { // Predicate_si_st_local
26424 5267 : SDNode *N = Node;
26425 :
26426 5267 : return isLocalStore(cast<StoreSDNode>(N));
26427 :
26428 : }
26429 : case 1: { // Predicate_si_store_local
26430 380 : SDNode *N = Node;
26431 :
26432 1140 : return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
26433 760 : !cast<StoreSDNode>(N)->isTruncatingStore();
26434 :
26435 : }
26436 : case 2: { // Predicate_si_store_local_align8
26437 98 : SDNode *N = Node;
26438 :
26439 98 : return cast<MemSDNode>(N)->getAlignment() % 8 == 0;
26440 :
26441 : }
26442 : case 3: { // Predicate_unindexedstore
26443 12267 : SDNode *N = Node;
26444 :
26445 24534 : return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
26446 :
26447 : }
26448 : case 4: { // Predicate_truncstore
26449 16863 : SDNode *N = Node;
26450 :
26451 33726 : return cast<StoreSDNode>(N)->isTruncatingStore();
26452 :
26453 : }
26454 : case 5: { // Predicate_truncstorei8
26455 3572 : SDNode *N = Node;
26456 :
26457 3572 : return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
26458 :
26459 : }
26460 : case 6: { // Predicate_truncstorei8_global
26461 2164 : SDNode *N = Node;
26462 :
26463 2164 : return isGlobalStore(dyn_cast<StoreSDNode>(N));
26464 :
26465 : }
26466 : case 7: { // Predicate_truncstorei16
26467 2652 : SDNode *N = Node;
26468 :
26469 2652 : return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
26470 :
26471 : }
26472 : case 8: { // Predicate_truncstorei16_global
26473 1034 : SDNode *N = Node;
26474 :
26475 1034 : return isGlobalStore(dyn_cast<StoreSDNode>(N));
26476 :
26477 : }
26478 : case 9: { // Predicate_store
26479 20818 : SDNode *N = Node;
26480 :
26481 41636 : return !cast<StoreSDNode>(N)->isTruncatingStore();
26482 :
26483 : }
26484 : case 10: { // Predicate_global_store
26485 15613 : SDNode *N = Node;
26486 :
26487 15613 : return isGlobalStore(dyn_cast<StoreSDNode>(N));
26488 :
26489 : }
26490 : case 11: { // Predicate_truncstorei8_private
26491 281 : SDNode *N = Node;
26492 :
26493 562 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
26494 :
26495 : }
26496 : case 12: { // Predicate_truncstorei16_private
26497 72 : SDNode *N = Node;
26498 :
26499 144 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
26500 :
26501 : }
26502 : case 13: { // Predicate_store_private
26503 2003 : SDNode *N = Node;
26504 :
26505 4006 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
26506 :
26507 : }
26508 : case 14: { // Predicate_si_truncstore_local
26509 473 : SDNode *N = Node;
26510 :
26511 946 : return cast<StoreSDNode>(N)->isTruncatingStore();
26512 :
26513 : }
26514 : case 15: { // Predicate_si_truncstore_local_i8
26515 221 : SDNode *N = Node;
26516 :
26517 221 : return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
26518 :
26519 : }
26520 : case 16: { // Predicate_si_truncstore_local_i16
26521 53 : SDNode *N = Node;
26522 :
26523 53 : return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
26524 :
26525 : }
26526 : case 17: { // Predicate_local_store
26527 1367 : SDNode *N = Node;
26528 :
26529 1367 : return isLocalStore(dyn_cast<StoreSDNode>(N));
26530 :
26531 : }
26532 : case 18: { // Predicate_truncstorei8_local
26533 9 : SDNode *N = Node;
26534 :
26535 9 : return isLocalStore(dyn_cast<StoreSDNode>(N));
26536 :
26537 : }
26538 : case 19: { // Predicate_truncstorei16_local
26539 4 : SDNode *N = Node;
26540 :
26541 4 : return isLocalStore(dyn_cast<StoreSDNode>(N));
26542 :
26543 : }
26544 : case 20: { // Predicate_truncstorei8_flat
26545 4 : SDNode *N = Node;
26546 :
26547 4 : return isFlatStore(dyn_cast<StoreSDNode>(N));
26548 :
26549 : }
26550 : case 21: { // Predicate_truncstorei16_flat
26551 4 : SDNode *N = Node;
26552 :
26553 4 : return isFlatStore(dyn_cast<StoreSDNode>(N));
26554 :
26555 : }
26556 : case 22: { // Predicate_flat_store
26557 21 : SDNode *N = Node;
26558 :
26559 21 : return isFlatStore(dyn_cast<StoreSDNode>(N));
26560 :
26561 : }
26562 : case 23: { // Predicate_unindexedload
26563 104640 : SDNode *N = Node;
26564 :
26565 209280 : return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
26566 :
26567 : }
26568 : case 24: { // Predicate_az_extload
26569 80849 : SDNode *N = Node;
26570 :
26571 80849 : LoadSDNode *L = cast<LoadSDNode>(N);
26572 80849 : return L->getExtensionType() == ISD::ZEXTLOAD ||
26573 80849 : L->getExtensionType() == ISD::EXTLOAD;
26574 :
26575 : }
26576 : case 25: { // Predicate_az_extloadi8
26577 11202 : SDNode *N = Node;
26578 :
26579 11202 : return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
26580 :
26581 : }
26582 : case 26: { // Predicate_az_extloadi8_global
26583 3600 : SDNode *N = Node;
26584 :
26585 3600 : return isGlobalLoad(dyn_cast<LoadSDNode>(N));
26586 :
26587 : }
26588 : case 27: { // Predicate_sextload
26589 66184 : SDNode *N = Node;
26590 :
26591 132368 : return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
26592 :
26593 : }
26594 : case 28: { // Predicate_sextloadi8
26595 2403 : SDNode *N = Node;
26596 :
26597 2403 : return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
26598 :
26599 : }
26600 : case 29: { // Predicate_sextloadi8_global
26601 442 : SDNode *N = Node;
26602 :
26603 442 : return isGlobalLoad(dyn_cast<LoadSDNode>(N));
26604 :
26605 : }
26606 : case 30: { // Predicate_az_extloadi16
26607 9940 : SDNode *N = Node;
26608 :
26609 9940 : return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
26610 :
26611 : }
26612 : case 31: { // Predicate_az_extloadi16_global
26613 2903 : SDNode *N = Node;
26614 :
26615 2903 : return isGlobalLoad(dyn_cast<LoadSDNode>(N));
26616 :
26617 : }
26618 : case 32: { // Predicate_sextloadi16
26619 2198 : SDNode *N = Node;
26620 :
26621 2198 : return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
26622 :
26623 : }
26624 : case 33: { // Predicate_sextloadi16_global
26625 1120 : SDNode *N = Node;
26626 :
26627 1120 : return isGlobalLoad(dyn_cast<LoadSDNode>(N));
26628 :
26629 : }
26630 : case 34: { // Predicate_load
26631 123081 : SDNode *N = Node;
26632 :
26633 246162 : return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
26634 :
26635 : }
26636 : case 35: { // Predicate_global_load
26637 26610 : SDNode *N = Node;
26638 :
26639 26610 : return isGlobalLoad(dyn_cast<LoadSDNode>(N));
26640 :
26641 : }
26642 : case 36: { // Predicate_sextloadi8_constant
26643 221 : SDNode *N = Node;
26644 :
26645 221 : return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
26646 :
26647 : }
26648 : case 37: { // Predicate_az_extloadi8_constant
26649 1453 : SDNode *N = Node;
26650 :
26651 1453 : return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
26652 :
26653 : }
26654 : case 38: { // Predicate_sextloadi16_constant
26655 560 : SDNode *N = Node;
26656 :
26657 560 : return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
26658 :
26659 : }
26660 : case 39: { // Predicate_az_extloadi16_constant
26661 1324 : SDNode *N = Node;
26662 :
26663 1324 : return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
26664 :
26665 : }
26666 : case 40: { // Predicate_constant_load
26667 90878 : SDNode *N = Node;
26668 :
26669 90878 : return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
26670 :
26671 : }
26672 : case 41: { // Predicate_sextloadi8_private
26673 28 : SDNode *N = Node;
26674 :
26675 56 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
26676 :
26677 : }
26678 : case 42: { // Predicate_extloadi8_private
26679 561 : SDNode *N = Node;
26680 :
26681 1122 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
26682 :
26683 : }
26684 : case 43: { // Predicate_sextloadi16_private
26685 24 : SDNode *N = Node;
26686 :
26687 48 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
26688 :
26689 : }
26690 : case 44: { // Predicate_extloadi16_private
26691 208 : SDNode *N = Node;
26692 :
26693 416 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
26694 :
26695 : }
26696 : case 45: { // Predicate_load_private
26697 10675 : SDNode *N = Node;
26698 :
26699 21350 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
26700 :
26701 : }
26702 : case 46: { // Predicate_load_param_exti8
26703 767 : SDNode *N = Node;
26704 767 : return isConstantLoad(dyn_cast<LoadSDNode>(N), 0);
26705 : }
26706 : case 47: { // Predicate_load_param_exti16
26707 320 : SDNode *N = Node;
26708 320 : return isConstantLoad(dyn_cast<LoadSDNode>(N), 0);
26709 : }
26710 : case 48: { // Predicate_load_param
26711 1120 : SDNode *N = Node;
26712 1120 : return isConstantLoad(dyn_cast<LoadSDNode>(N), 0);
26713 : }
26714 : case 49: { // Predicate_si_ld_local
26715 28294 : SDNode *N = Node;
26716 :
26717 28294 : return isLocalLoad(cast<LoadSDNode>(N));
26718 :
26719 : }
26720 : case 50: { // Predicate_si_sextload_local
26721 960 : SDNode *N = Node;
26722 :
26723 1920 : return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
26724 :
26725 : }
26726 : case 51: { // Predicate_si_sextload_local_i8
26727 30 : SDNode *N = Node;
26728 30 : return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
26729 : }
26730 : case 52: { // Predicate_si_az_extload_local
26731 930 : SDNode *N = Node;
26732 :
26733 930 : LoadSDNode *L = cast<LoadSDNode>(N);
26734 930 : return L->getExtensionType() == ISD::ZEXTLOAD ||
26735 930 : L->getExtensionType() == ISD::EXTLOAD;
26736 :
26737 : }
26738 : case 53: { // Predicate_si_az_extload_local_i8
26739 304 : SDNode *N = Node;
26740 304 : return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
26741 : }
26742 : case 54: { // Predicate_si_sextload_local_i16
26743 14 : SDNode *N = Node;
26744 14 : return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
26745 : }
26746 : case 55: { // Predicate_si_az_extload_local_i16
26747 108 : SDNode *N = Node;
26748 108 : return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
26749 : }
26750 : case 56: { // Predicate_si_load_local
26751 399 : SDNode *N = Node;
26752 :
26753 1197 : return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
26754 798 : cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
26755 :
26756 : }
26757 : case 57: { // Predicate_IMM8bitDWORD
26758 26262 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
26759 26262 : return (N->getZExtValue() & ~0x3FC) == 0;
26760 : }
26761 : case 58: { // Predicate_IMM20bit
26762 20158 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
26763 40316 : return isUInt<20>(N->getZExtValue());
26764 : }
26765 : case 59: { // Predicate_IMM32bit
26766 16169 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
26767 32338 : return isUInt<32>(N->getZExtValue());
26768 : }
26769 : case 60: { // Predicate_sextloadi8_flat
26770 4 : SDNode *N = Node;
26771 :
26772 4 : return isFlatLoad(dyn_cast<LoadSDNode>(N));
26773 :
26774 : }
26775 : case 61: { // Predicate_az_extloadi8_flat
26776 4 : SDNode *N = Node;
26777 :
26778 4 : return isFlatLoad(dyn_cast<LoadSDNode>(N));
26779 :
26780 : }
26781 : case 62: { // Predicate_sextloadi16_flat
26782 4 : SDNode *N = Node;
26783 :
26784 4 : return isFlatLoad(dyn_cast<LoadSDNode>(N));
26785 :
26786 : }
26787 : case 63: { // Predicate_az_extloadi16_flat
26788 4 : SDNode *N = Node;
26789 :
26790 4 : return isFlatLoad(dyn_cast<LoadSDNode>(N));
26791 :
26792 : }
26793 : case 64: { // Predicate_flat_load
26794 8640 : SDNode *N = Node;
26795 :
26796 8640 : return isFlatLoad(dyn_cast<LoadSDNode>(N));
26797 :
26798 : }
26799 : case 65: { // Predicate_az_extloadi32
26800 0 : SDNode *N = Node;
26801 :
26802 0 : return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
26803 :
26804 : }
26805 : case 66: { // Predicate_az_extloadi32_flat
26806 0 : SDNode *N = Node;
26807 :
26808 0 : return isFlatLoad(dyn_cast<LoadSDNode>(N));
26809 :
26810 : }
26811 : case 67: { // Predicate_local_load
26812 42 : SDNode *N = Node;
26813 :
26814 42 : return isLocalLoad(dyn_cast<LoadSDNode>(N));
26815 :
26816 : }
26817 : case 68: { // Predicate_sextloadi8_local
26818 0 : SDNode *N = Node;
26819 :
26820 0 : return isLocalLoad(dyn_cast<LoadSDNode>(N));
26821 :
26822 : }
26823 : case 69: { // Predicate_az_extloadi8_local
26824 30 : SDNode *N = Node;
26825 :
26826 30 : return isLocalLoad(dyn_cast<LoadSDNode>(N));
26827 :
26828 : }
26829 : case 70: { // Predicate_sextloadi16_local
26830 0 : SDNode *N = Node;
26831 :
26832 0 : return isLocalLoad(dyn_cast<LoadSDNode>(N));
26833 :
26834 : }
26835 : case 71: { // Predicate_az_extloadi16_local
26836 28 : SDNode *N = Node;
26837 :
26838 28 : return isLocalLoad(dyn_cast<LoadSDNode>(N));
26839 :
26840 : }
26841 : case 72: { // Predicate_si_load_local_align8
26842 71 : SDNode *N = Node;
26843 :
26844 71 : return cast<MemSDNode>(N)->getAlignment() % 8 == 0;
26845 :
26846 : }
26847 : case 73: { // Predicate_atomic_swap_global
26848 34 : SDNode *N = Node;
26849 68 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
26850 : }
26851 : case 74: { // Predicate_si_atomic_swap_local
26852 26 : SDNode *N = Node;
26853 :
26854 52 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26855 :
26856 : }
26857 : case 75: { // Predicate_atomic_swap_local
26858 4 : SDNode *N = Node;
26859 :
26860 8 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26861 :
26862 : }
26863 : case 76: { // Predicate_atomic_add_global
26864 89 : SDNode *N = Node;
26865 178 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
26866 : }
26867 : case 77: { // Predicate_si_atomic_load_add_local
26868 86 : SDNode *N = Node;
26869 :
26870 172 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26871 :
26872 : }
26873 : case 78: { // Predicate_atomic_load_add_local
26874 16 : SDNode *N = Node;
26875 :
26876 32 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26877 :
26878 : }
26879 : case 79: { // Predicate_atomic_sub_global
26880 70 : SDNode *N = Node;
26881 140 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
26882 : }
26883 : case 80: { // Predicate_si_atomic_load_sub_local
26884 66 : SDNode *N = Node;
26885 :
26886 132 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26887 :
26888 : }
26889 : case 81: { // Predicate_atomic_load_sub_local
26890 12 : SDNode *N = Node;
26891 :
26892 24 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26893 :
26894 : }
26895 : case 82: { // Predicate_atomic_min_global
26896 34 : SDNode *N = Node;
26897 68 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
26898 : }
26899 : case 83: { // Predicate_si_atomic_load_min_local
26900 26 : SDNode *N = Node;
26901 :
26902 52 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26903 :
26904 : }
26905 : case 84: { // Predicate_atomic_load_min_local
26906 4 : SDNode *N = Node;
26907 :
26908 8 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26909 :
26910 : }
26911 : case 85: { // Predicate_atomic_umin_global
26912 34 : SDNode *N = Node;
26913 68 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
26914 : }
26915 : case 86: { // Predicate_si_atomic_load_umin_local
26916 26 : SDNode *N = Node;
26917 :
26918 52 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26919 :
26920 : }
26921 : case 87: { // Predicate_atomic_load_umin_local
26922 4 : SDNode *N = Node;
26923 :
26924 8 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26925 :
26926 : }
26927 : case 88: { // Predicate_atomic_max_global
26928 34 : SDNode *N = Node;
26929 68 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
26930 : }
26931 : case 89: { // Predicate_si_atomic_load_max_local
26932 26 : SDNode *N = Node;
26933 :
26934 52 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26935 :
26936 : }
26937 : case 90: { // Predicate_atomic_load_max_local
26938 4 : SDNode *N = Node;
26939 :
26940 8 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26941 :
26942 : }
26943 : case 91: { // Predicate_atomic_umax_global
26944 34 : SDNode *N = Node;
26945 68 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
26946 : }
26947 : case 92: { // Predicate_si_atomic_load_umax_local
26948 26 : SDNode *N = Node;
26949 :
26950 52 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26951 :
26952 : }
26953 : case 93: { // Predicate_atomic_load_umax_local
26954 4 : SDNode *N = Node;
26955 :
26956 8 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26957 :
26958 : }
26959 : case 94: { // Predicate_atomic_and_global
26960 34 : SDNode *N = Node;
26961 68 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
26962 : }
26963 : case 95: { // Predicate_si_atomic_load_and_local
26964 26 : SDNode *N = Node;
26965 :
26966 52 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26967 :
26968 : }
26969 : case 96: { // Predicate_atomic_load_and_local
26970 4 : SDNode *N = Node;
26971 :
26972 8 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26973 :
26974 : }
26975 : case 97: { // Predicate_atomic_or_global
26976 34 : SDNode *N = Node;
26977 68 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
26978 : }
26979 : case 98: { // Predicate_si_atomic_load_or_local
26980 26 : SDNode *N = Node;
26981 :
26982 52 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26983 :
26984 : }
26985 : case 99: { // Predicate_atomic_load_or_local
26986 4 : SDNode *N = Node;
26987 :
26988 8 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26989 :
26990 : }
26991 : case 100: { // Predicate_atomic_xor_global
26992 34 : SDNode *N = Node;
26993 68 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
26994 : }
26995 : case 101: { // Predicate_si_atomic_load_xor_local
26996 26 : SDNode *N = Node;
26997 :
26998 52 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
26999 :
27000 : }
27001 : case 102: { // Predicate_atomic_load_xor_local
27002 4 : SDNode *N = Node;
27003 :
27004 8 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
27005 :
27006 : }
27007 : case 103: { // Predicate_COND_OEQ
27008 627 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27009 627 : return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;
27010 : }
27011 : case 104: { // Predicate_COND_OGT
27012 555 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27013 555 : return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;
27014 : }
27015 : case 105: { // Predicate_COND_OGE
27016 380 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27017 380 : return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;
27018 : }
27019 : case 106: { // Predicate_COND_UNE_NE
27020 15 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27021 15 : return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;
27022 : }
27023 : case 107: { // Predicate_FP_ONE
27024 140 : ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
27025 140 : return N->isExactlyValue(1.0);
27026 : }
27027 : case 108: { // Predicate_FP_ZERO
27028 144 : ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
27029 288 : return N->getValueAPF().isZero();
27030 : }
27031 : case 109: { // Predicate_COND_EQ
27032 6355 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27033 6355 : return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;
27034 : }
27035 : case 110: { // Predicate_COND_SGE
27036 1508 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27037 1508 : return N->get() == ISD::SETGE;
27038 : }
27039 : case 111: { // Predicate_COND_SGT
27040 1863 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27041 1863 : return N->get() == ISD::SETGT;
27042 : }
27043 : case 112: { // Predicate_si_atomic_cmp_swap_32_local
27044 13 : SDNode *N = Node;
27045 :
27046 13 : AtomicSDNode *AN = cast<AtomicSDNode>(N);
27047 52 : return AN->getMemoryVT() == MVT::i32 &&
27048 13 : AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
27049 :
27050 : }
27051 : case 113: { // Predicate_si_atomic_cmp_swap_64_local
27052 6 : SDNode *N = Node;
27053 :
27054 6 : AtomicSDNode *AN = cast<AtomicSDNode>(N);
27055 24 : return AN->getMemoryVT() == MVT::i64 &&
27056 6 : AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
27057 :
27058 : }
27059 : case 114: { // Predicate_atomic_cmp_swap_32_local
27060 0 : SDNode *N = Node;
27061 :
27062 0 : AtomicSDNode *AN = cast<AtomicSDNode>(N);
27063 0 : return AN->getMemoryVT() == MVT::i32 &&
27064 0 : AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
27065 :
27066 : }
27067 : case 115: { // Predicate_IMMZeroBasedBitfieldMask
27068 591 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
27069 :
27070 1182 : return isMask_32(N->getZExtValue());
27071 :
27072 : }
27073 : case 116: { // Predicate_TEX_ARRAY
27074 170 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
27075 170 : uint32_t TType = (uint32_t)N->getZExtValue();
27076 170 : return TType == 9 || TType == 10 || TType == 16;
27077 :
27078 : }
27079 : case 117: { // Predicate_TEX_MSAA
27080 18 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
27081 18 : uint32_t TType = (uint32_t)N->getZExtValue();
27082 18 : return TType == 14;
27083 :
27084 : }
27085 : case 118: { // Predicate_TEX_ARRAY_MSAA
27086 44 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
27087 44 : uint32_t TType = (uint32_t)N->getZExtValue();
27088 44 : return TType == 15;
27089 :
27090 : }
27091 : case 119: { // Predicate_TEX_SHADOW
27092 104 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
27093 104 : uint32_t TType = (uint32_t)N->getZExtValue();
27094 104 : return (TType >= 6 && TType <= 8) || TType == 13;
27095 :
27096 : }
27097 : case 120: { // Predicate_mskor_global
27098 137 : SDNode *N = Node;
27099 :
27100 274 : return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
27101 :
27102 : }
27103 : case 121: { // Predicate_anonymous_1454
27104 6790 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
27105 :
27106 6790 : if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
27107 : return false;
27108 : }
27109 : const SIRegisterInfo *SIRI =
27110 3376 : static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
27111 9294 : for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
27112 : U != E; ++U) {
27113 12831 : if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
27114 : return true;
27115 : }
27116 : }
27117 : return false;
27118 :
27119 : }
27120 : case 122: { // Predicate_anonymous_1460
27121 307 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
27122 :
27123 307 : return isInlineImmediate(N);
27124 :
27125 : }
27126 : case 123: { // Predicate_FP_HALF
27127 9 : ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
27128 9 : return N->isExactlyValue(0.5);
27129 : }
27130 : case 124: { // Predicate_cvt_rpi_i32_f32
27131 6 : SDNode *N = Node;
27132 6 : (void) N; return TM.Options.NoNaNsFPMath;
27133 : }
27134 : case 125: { // Predicate_cvt_flr_i32_f32
27135 25 : SDNode *N = Node;
27136 25 : (void)N; return TM.Options.NoNaNsFPMath;
27137 : }
27138 : case 126: { // Predicate_COND_NULL
27139 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27140 : (void)N; return false;
27141 : }
27142 : case 127: { // Predicate_COND_OLT
27143 468 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27144 468 : return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;
27145 : }
27146 : case 128: { // Predicate_COND_OLE
27147 416 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27148 416 : return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;
27149 : }
27150 : case 129: { // Predicate_COND_ONE
27151 303 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27152 303 : return N->get() == ISD::SETONE || N->get() == ISD::SETNE;
27153 : }
27154 : case 130: { // Predicate_COND_O
27155 168 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27156 168 : return N->get() == ISD::SETO;
27157 : }
27158 : case 131: { // Predicate_COND_UO
27159 153 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27160 153 : return N->get() == ISD::SETUO;
27161 : }
27162 : case 132: { // Predicate_COND_ULT
27163 1642 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27164 1642 : return N->get() == ISD::SETULT;
27165 : }
27166 : case 133: { // Predicate_COND_UEQ
27167 136 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27168 136 : return N->get() == ISD::SETUEQ;
27169 : }
27170 : case 134: { // Predicate_COND_ULE
27171 1603 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27172 1603 : return N->get() == ISD::SETULE;
27173 : }
27174 : case 135: { // Predicate_COND_UGT
27175 1578 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27176 1578 : return N->get() == ISD::SETUGT;
27177 : }
27178 : case 136: { // Predicate_COND_UNE
27179 97 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27180 97 : return N->get() == ISD::SETUNE;
27181 : }
27182 : case 137: { // Predicate_COND_UGE
27183 1490 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27184 1490 : return N->get() == ISD::SETUGE;
27185 : }
27186 : case 138: { // Predicate_COND_SLT
27187 2690 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27188 2690 : return N->get() == ISD::SETLT;
27189 : }
27190 : case 139: { // Predicate_COND_SLE
27191 1868 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27192 1868 : return N->get() == ISD::SETLE;
27193 : }
27194 : case 140: { // Predicate_COND_NE
27195 3092 : CondCodeSDNode*N = cast<CondCodeSDNode>(Node);
27196 3092 : return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;
27197 : }
27198 : case 141: { // Predicate_anonymous_1456
27199 824 : ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
27200 :
27201 824 : if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
27202 : return false;
27203 : }
27204 : const SIRegisterInfo *SIRI =
27205 574 : static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
27206 2047 : for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
27207 : U != E; ++U) {
27208 2697 : if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
27209 : return true;
27210 : }
27211 : }
27212 : return false;
27213 :
27214 : }
27215 : case 142: { // Predicate_anonymous_1464
27216 93 : ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
27217 :
27218 93 : return isInlineImmediate(N);
27219 :
27220 : }
27221 : case 143: { // Predicate_TEX_RECT
27222 60 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
27223 60 : uint32_t TType = (uint32_t)N->getZExtValue();
27224 60 : return TType == 5;
27225 :
27226 : }
27227 : case 144: { // Predicate_TEX_SHADOW_ARRAY
27228 88 : ConstantSDNode*N = cast<ConstantSDNode>(Node);
27229 88 : uint32_t TType = (uint32_t)N->getZExtValue();
27230 88 : return TType == 11 || TType == 12 || TType == 17;
27231 :
27232 : }
27233 : }
27234 : }
27235 :
27236 48987 : bool CheckComplexPattern(SDNode *Root, SDNode *Parent,
27237 : SDValue N, unsigned PatternNo,
27238 : SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) override {
27239 97974 : unsigned NextRes = Result.size();
27240 48987 : switch (PatternNo) {
27241 0 : default: llvm_unreachable("Invalid pattern # in table?");
27242 : case 0:
27243 1346 : Result.resize(NextRes+2);
27244 4038 : return SelectDS1Addr1Offset(N, Result[NextRes+0].first, Result[NextRes+1].first);
27245 : case 1:
27246 19696 : Result.resize(NextRes+7);
27247 157568 : return SelectMUBUFAddr64(N, Result[NextRes+0].first, Result[NextRes+1].first, Result[NextRes+2].first, Result[NextRes+3].first, Result[NextRes+4].first, Result[NextRes+5].first, Result[NextRes+6].first);
27248 : case 2:
27249 12343 : Result.resize(NextRes+6);
27250 86401 : return SelectMUBUFOffset(N, Result[NextRes+0].first, Result[NextRes+1].first, Result[NextRes+2].first, Result[NextRes+3].first, Result[NextRes+4].first, Result[NextRes+5].first);
27251 : case 3:
27252 429 : Result.resize(NextRes+4);
27253 2145 : return SelectMUBUFScratch(N, Result[NextRes+0].first, Result[NextRes+1].first, Result[NextRes+2].first, Result[NextRes+3].first);
27254 : case 4:
27255 35 : Result.resize(NextRes+3);
27256 140 : return SelectDS64Bit4ByteAligned(N, Result[NextRes+0].first, Result[NextRes+1].first, Result[NextRes+2].first);
27257 : case 5:
27258 969 : Result.resize(NextRes+2);
27259 2907 : return SelectADDRVTX_READ(N, Result[NextRes+0].first, Result[NextRes+1].first);
27260 : case 6:
27261 81 : Result.resize(NextRes+5);
27262 486 : return SelectMUBUFAddr64(N, Result[NextRes+0].first, Result[NextRes+1].first, Result[NextRes+2].first, Result[NextRes+3].first, Result[NextRes+4].first);
27263 : case 7:
27264 41 : Result.resize(NextRes+4);
27265 205 : return SelectMUBUFOffset(N, Result[NextRes+0].first, Result[NextRes+1].first, Result[NextRes+2].first, Result[NextRes+3].first);
27266 : case 8:
27267 94 : Result.resize(NextRes+2);
27268 282 : return SelectADDRIndirect(N, Result[NextRes+0].first, Result[NextRes+1].first);
27269 : case 9:
27270 3878 : Result.resize(NextRes+1);
27271 7756 : return SelectGlobalValueConstantOffset(N, Result[NextRes+0].first);
27272 : case 10:
27273 0 : Result.resize(NextRes+2);
27274 0 : return SelectGlobalValueVariableOffset(N, Result[NextRes+0].first, Result[NextRes+1].first);
27275 : case 11:
27276 5092 : Result.resize(NextRes+4);
27277 25460 : return SelectVOP3Mods0(N, Result[NextRes+0].first, Result[NextRes+1].first, Result[NextRes+2].first, Result[NextRes+3].first);
27278 : case 12:
27279 4919 : Result.resize(NextRes+2);
27280 14757 : return SelectVOP3Mods(N, Result[NextRes+0].first, Result[NextRes+1].first);
27281 : case 13:
27282 32 : Result.resize(NextRes+4);
27283 160 : return SelectVOP3Mods0Clamp0OMod(N, Result[NextRes+0].first, Result[NextRes+1].first, Result[NextRes+2].first, Result[NextRes+3].first);
27284 : case 14:
27285 32 : Result.resize(NextRes+3);
27286 128 : return SelectVOP3Mods0Clamp(N, Result[NextRes+0].first, Result[NextRes+1].first, Result[NextRes+2].first);
27287 : }
27288 : }
27289 :
27290 14135 : SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) override {
27291 14135 : switch (XFormNo) {
27292 0 : default: llvm_unreachable("Invalid xform # in table?");
27293 : case 0: { // as_i16imm
27294 2740 : ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
27295 :
27296 1370 : return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
27297 :
27298 : }
27299 : case 1: { // as_i1imm
27300 2452 : ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
27301 :
27302 1226 : return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
27303 :
27304 : }
27305 : case 2: { // as_i8imm
27306 40 : ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
27307 :
27308 20 : return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
27309 :
27310 : }
27311 : case 3: { // as_dword_i32imm
27312 12208 : ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
27313 :
27314 6104 : return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
27315 :
27316 : }
27317 : case 4: { // as_i32imm
27318 8308 : ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
27319 :
27320 4154 : return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
27321 :
27322 : }
27323 : case 5: { // IMMPopCount
27324 1098 : ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
27325 :
27326 549 : return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N),
27327 549 : MVT::i32);
27328 :
27329 : }
27330 : case 6: { // as_i64imm
27331 90 : ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
27332 :
27333 45 : return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
27334 :
27335 : }
27336 : case 7: { // bitcast_fpimm_to_i32
27337 1148 : ConstantFPSDNode *N = cast<ConstantFPSDNode>(V.getNode());
27338 :
27339 : return CurDAG->getTargetConstant(
27340 1722 : N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
27341 :
27342 : }
27343 : case 8: { // bitcast_fpimm_to_i64
27344 186 : ConstantFPSDNode *N = cast<ConstantFPSDNode>(V.getNode());
27345 :
27346 : return CurDAG->getTargetConstant(
27347 279 : N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
27348 :
27349 : }
27350 : }
27351 : }
27352 :
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