Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Subtarget Enumeration Source Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_SUBTARGETINFO_ENUM
11 : #undef GET_SUBTARGETINFO_ENUM
12 : namespace llvm {
13 : namespace AMDGPU {
14 : enum : uint64_t {
15 : Feature64BitPtr = 0,
16 : FeatureCFALUBug = 1,
17 : FeatureCIInsts = 2,
18 : FeatureCaymanISA = 3,
19 : FeatureDisable = 4,
20 : FeatureDumpCode = 5,
21 : FeatureDumpCodeLower = 6,
22 : FeatureEnableLoadStoreOpt = 7,
23 : FeatureEvergreen = 8,
24 : FeatureFP32Denormals = 9,
25 : FeatureFP64 = 10,
26 : FeatureFP64Denormals = 11,
27 : FeatureFastFMAF32 = 12,
28 : FeatureFetchLimit8 = 13,
29 : FeatureFetchLimit16 = 14,
30 : FeatureFlatAddressSpace = 15,
31 : FeatureGCN = 16,
32 : FeatureGCN1Encoding = 17,
33 : FeatureGCN3Encoding = 18,
34 : FeatureIRStructurizer = 19,
35 : FeatureIfCvt = 20,
36 : FeatureLDSBankCount16 = 21,
37 : FeatureLDSBankCount32 = 22,
38 : FeatureLocalMemorySize0 = 23,
39 : FeatureLocalMemorySize32768 = 24,
40 : FeatureLocalMemorySize65536 = 25,
41 : FeatureNorthernIslands = 26,
42 : FeaturePromoteAlloca = 27,
43 : FeatureR600 = 28,
44 : FeatureR600ALUInst = 29,
45 : FeatureR700 = 30,
46 : FeatureSGPRInitBug = 31,
47 : FeatureSeaIslands = 32,
48 : FeatureSouthernIslands = 33,
49 : FeatureVGPRSpilling = 34,
50 : FeatureVertexCache = 35,
51 : FeatureVolcanicIslands = 36,
52 : FeatureWavefrontSize16 = 37,
53 : FeatureWavefrontSize32 = 38,
54 : FeatureWavefrontSize64 = 39
55 : };
56 : }
57 : } // End llvm namespace
58 : #endif // GET_SUBTARGETINFO_ENUM
59 :
60 :
61 : #ifdef GET_SUBTARGETINFO_MC_DESC
62 : #undef GET_SUBTARGETINFO_MC_DESC
63 : namespace llvm {
64 : // Sorted (by key) array of values for CPU features.
65 : extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[] = {
66 : { "64BitPtr", "Specify if 64-bit addressing should be used", { AMDGPU::Feature64BitPtr }, { } },
67 : { "DumpCode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCode }, { } },
68 : { "EVERGREEN", "EVERGREEN GPU generation", { AMDGPU::FeatureEvergreen }, { AMDGPU::FeatureFetchLimit16, AMDGPU::FeatureLocalMemorySize32768 } },
69 : { "HasVertexCache", "Specify use of dedicated vertex cache", { AMDGPU::FeatureVertexCache }, { } },
70 : { "NORTHERN_ISLANDS", "NORTHERN_ISLANDS GPU generation", { AMDGPU::FeatureNorthernIslands }, { AMDGPU::FeatureFetchLimit16, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureLocalMemorySize32768 } },
71 : { "R600", "R600 GPU generation", { AMDGPU::FeatureR600 }, { AMDGPU::FeatureR600ALUInst, AMDGPU::FeatureFetchLimit8, AMDGPU::FeatureLocalMemorySize0 } },
72 : { "R600ALUInst", "Older version of ALU instructions encoding", { AMDGPU::FeatureR600ALUInst }, { } },
73 : { "R700", "R700 GPU generation", { AMDGPU::FeatureR700 }, { AMDGPU::FeatureFetchLimit16, AMDGPU::FeatureLocalMemorySize0 } },
74 : { "SEA_ISLANDS", "SEA_ISLANDS GPU generation", { AMDGPU::FeatureSeaIslands }, { AMDGPU::Feature64BitPtr, AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureGCN, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN1Encoding, AMDGPU::FeatureCIInsts } },
75 : { "SOUTHERN_ISLANDS", "SOUTHERN_ISLANDS GPU generation", { AMDGPU::FeatureSouthernIslands }, { AMDGPU::Feature64BitPtr, AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize32768, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureGCN, AMDGPU::FeatureGCN1Encoding, AMDGPU::FeatureLDSBankCount32 } },
76 : { "VOLCANIC_ISLANDS", "VOLCANIC_ISLANDS GPU generation", { AMDGPU::FeatureVolcanicIslands }, { AMDGPU::Feature64BitPtr, AMDGPU::FeatureFP64, AMDGPU::FeatureLocalMemorySize65536, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureFlatAddressSpace, AMDGPU::FeatureGCN, AMDGPU::FeatureGCN3Encoding, AMDGPU::FeatureCIInsts, AMDGPU::FeatureLDSBankCount32 } },
77 : { "caymanISA", "Use Cayman ISA", { AMDGPU::FeatureCaymanISA }, { } },
78 : { "cfalubug", "GPU has CF_ALU bug", { AMDGPU::FeatureCFALUBug }, { } },
79 : { "ci-insts", "Additional intstructions for CI+", { AMDGPU::FeatureCIInsts }, { } },
80 : { "disable-ifcvt", "Disable the if conversion pass", { AMDGPU::FeatureIfCvt }, { } },
81 : { "disable-irstructurizer", "Disable IR Structurizer", { AMDGPU::FeatureIRStructurizer }, { } },
82 : { "dumpcode", "Dump MachineInstrs in the CodeEmitter", { AMDGPU::FeatureDumpCodeLower }, { } },
83 : { "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", { AMDGPU::FeatureFastFMAF32 }, { } },
84 : { "fetch16", "Limit the maximum number of fetches in a clause to 16", { AMDGPU::FeatureFetchLimit16 }, { } },
85 : { "fetch8", "Limit the maximum number of fetches in a clause to 8", { AMDGPU::FeatureFetchLimit8 }, { } },
86 : { "flat-address-space", "Support flat address space", { AMDGPU::FeatureFlatAddressSpace }, { } },
87 : { "fp32-denormals", "Enable single precision denormal handling", { AMDGPU::FeatureFP32Denormals }, { } },
88 : { "fp64", "Enable double precision operations", { AMDGPU::FeatureFP64 }, { } },
89 : { "fp64-denormals", "Enable double precision denormal handling", { AMDGPU::FeatureFP64Denormals }, { AMDGPU::FeatureFP64 } },
90 : { "gcn", "GCN or newer GPU", { AMDGPU::FeatureGCN }, { } },
91 : { "gcn1-encoding", "Encoding format for SI and CI", { AMDGPU::FeatureGCN1Encoding }, { } },
92 : { "gcn3-encoding", "Encoding format for VI", { AMDGPU::FeatureGCN3Encoding }, { } },
93 : { "ldsbankcount16", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount16 }, { } },
94 : { "ldsbankcount32", "The number of LDS banks per compute unit.", { AMDGPU::FeatureLDSBankCount32 }, { } },
95 : { "load-store-opt", "Enable SI load/store optimizer pass", { AMDGPU::FeatureEnableLoadStoreOpt }, { } },
96 : { "localmemorysize0", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize0 }, { } },
97 : { "localmemorysize32768", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize32768 }, { } },
98 : { "localmemorysize65536", "The size of local memory in bytes", { AMDGPU::FeatureLocalMemorySize65536 }, { } },
99 : { "promote-alloca", "Enable promote alloca pass", { AMDGPU::FeaturePromoteAlloca }, { } },
100 : { "sgpr-init-bug", "VI SGPR initilization bug requiring a fixed SGPR allocation size", { AMDGPU::FeatureSGPRInitBug }, { } },
101 : { "vgpr-spilling", "Enable spilling of VGPRs to scratch memory", { AMDGPU::FeatureVGPRSpilling }, { } },
102 : { "wavefrontsize16", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize16 }, { } },
103 : { "wavefrontsize32", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize32 }, { } },
104 : { "wavefrontsize64", "The number of threads per wavefront", { AMDGPU::FeatureWavefrontSize64 }, { } }
105 1166003 : };
106 :
107 : // Sorted (by key) array of values for CPU subtype.
108 : extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[] = {
109 : { "", "Select the processor", { AMDGPU::FeatureR600, AMDGPU::FeatureVertexCache }, { } },
110 : { "SI", "Select the SI processor", { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureFastFMAF32 }, { } },
111 : { "barts", "Select the barts processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureVertexCache, AMDGPU::FeatureCFALUBug }, { } },
112 : { "bonaire", "Select the bonaire processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32 }, { } },
113 : { "caicos", "Select the caicos processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureCFALUBug }, { } },
114 : { "carrizo", "Select the carrizo processor", { AMDGPU::FeatureVolcanicIslands }, { } },
115 : { "cayman", "Select the cayman processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureFP64, AMDGPU::FeatureCaymanISA }, { } },
116 : { "cedar", "Select the cedar processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize32, AMDGPU::FeatureCFALUBug }, { } },
117 : { "cypress", "Select the cypress processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureFP64, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64 }, { } },
118 : { "hainan", "Select the hainan processor", { AMDGPU::FeatureSouthernIslands }, { } },
119 : { "hawaii", "Select the hawaii processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureLDSBankCount32 }, { } },
120 : { "iceland", "Select the iceland processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureSGPRInitBug }, { } },
121 : { "juniper", "Select the juniper processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64 }, { } },
122 : { "kabini", "Select the kabini processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16 }, { } },
123 : { "kaveri", "Select the kaveri processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount32 }, { } },
124 : { "mullins", "Select the mullins processor", { AMDGPU::FeatureSeaIslands, AMDGPU::FeatureLDSBankCount16 }, { } },
125 : { "oland", "Select the oland processor", { AMDGPU::FeatureSouthernIslands }, { } },
126 : { "pitcairn", "Select the pitcairn processor", { AMDGPU::FeatureSouthernIslands }, { } },
127 : { "r600", "Select the r600 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64 }, { } },
128 : { "r630", "Select the r630 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize32 }, { } },
129 : { "redwood", "Select the redwood processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureCFALUBug }, { } },
130 : { "rs880", "Select the rs880 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureWavefrontSize16 }, { } },
131 : { "rv670", "Select the rv670 processor", { AMDGPU::FeatureR600, AMDGPU::FeatureFP64, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64 }, { } },
132 : { "rv710", "Select the rv710 processor", { AMDGPU::FeatureR700, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize32 }, { } },
133 : { "rv730", "Select the rv730 processor", { AMDGPU::FeatureR700, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize32 }, { } },
134 : { "rv770", "Select the rv770 processor", { AMDGPU::FeatureR700, AMDGPU::FeatureFP64, AMDGPU::FeatureVertexCache, AMDGPU::FeatureWavefrontSize64 }, { } },
135 : { "sumo", "Select the sumo processor", { AMDGPU::FeatureEvergreen, AMDGPU::FeatureWavefrontSize64, AMDGPU::FeatureCFALUBug }, { } },
136 : { "tahiti", "Select the tahiti processor", { AMDGPU::FeatureSouthernIslands, AMDGPU::FeatureFastFMAF32 }, { } },
137 : { "tonga", "Select the tonga processor", { AMDGPU::FeatureVolcanicIslands, AMDGPU::FeatureSGPRInitBug }, { } },
138 : { "turks", "Select the turks processor", { AMDGPU::FeatureNorthernIslands, AMDGPU::FeatureVertexCache, AMDGPU::FeatureCFALUBug }, { } },
139 : { "verde", "Select the verde processor", { AMDGPU::FeatureSouthernIslands }, { } }
140 1166003 : };
141 :
142 : #ifdef DBGFIELD
143 : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
144 : #endif
145 : #ifndef NDEBUG
146 : #define DBGFIELD(x) x,
147 : #else
148 : #define DBGFIELD(x)
149 : #endif
150 :
151 : // Functional units for "R600_VLIW5_Itin"
152 : namespace R600_VLIW5_ItinFU {
153 : const unsigned ALU_X = 1 << 0;
154 : const unsigned ALU_Y = 1 << 1;
155 : const unsigned ALU_Z = 1 << 2;
156 : const unsigned ALU_W = 1 << 3;
157 : const unsigned TRANS = 1 << 4;
158 : const unsigned ALU_NULL = 1 << 5;
159 : }
160 :
161 : // Functional units for "R600_VLIW4_Itin"
162 : namespace R600_VLIW4_ItinFU {
163 : const unsigned ALU_X = 1 << 0;
164 : const unsigned ALU_Y = 1 << 1;
165 : const unsigned ALU_Z = 1 << 2;
166 : const unsigned ALU_W = 1 << 3;
167 : const unsigned ALU_NULL = 1 << 4;
168 : }
169 :
170 : extern const llvm::InstrStage AMDGPUStages[] = {
171 : { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
172 : { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
173 : { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
174 : { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
175 : { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
176 : { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
177 : { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
178 : { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
179 : { 0, 0, 0, llvm::InstrStage::Required } // End stages
180 : };
181 : extern const unsigned AMDGPUOperandCycles[] = {
182 : 0, // No itinerary
183 : 0 // End operand cycles
184 : };
185 : extern const unsigned AMDGPUForwardingPaths[] = {
186 : 0, // No itinerary
187 : 0 // End bypass tables
188 : };
189 :
190 : static const llvm::InstrItinerary R600_VLIW5_Itin[] = {
191 : { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
192 : { 1, 1, 2, 0, 0 }, // 1 AnyALU
193 : { 1, 2, 3, 0, 0 }, // 2 NullALU
194 : { 1, 3, 4, 0, 0 }, // 3 VecALU
195 : { 1, 2, 3, 0, 0 }, // 4 NullALU_WriteVMEM
196 : { 1, 4, 5, 0, 0 }, // 5 TransALU
197 : { 1, 2, 3, 0, 0 }, // 6 NullALU_WriteLDS
198 : { 1, 2, 3, 0, 0 }, // 7 NullALU_Write32Bit
199 : { 1, 5, 6, 0, 0 }, // 8 XALU
200 : { 1, 2, 3, 0, 0 }, // 9 NullALU_WriteSALU
201 : { 1, 2, 3, 0, 0 }, // 10 NullALU_WriteSMEM
202 : { 1, 2, 3, 0, 0 }, // 11 NullALU_WriteDouble
203 : { 1, 2, 3, 0, 0 }, // 12 NullALU_WriteQuarterRate32
204 : { 1, 2, 3, 0, 0 }, // 13 NullALU_WriteFloatFMA_WriteSALU
205 : { 1, 2, 3, 0, 0 }, // 14 NullALU_WriteDouble_WriteSALU
206 : { 0, ~0U, ~0U, ~0U, ~0U } // end marker
207 : };
208 :
209 : static const llvm::InstrItinerary R600_VLIW4_Itin[] = {
210 : { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
211 : { 1, 6, 7, 0, 0 }, // 1 AnyALU
212 : { 1, 7, 8, 0, 0 }, // 2 NullALU
213 : { 1, 6, 7, 0, 0 }, // 3 VecALU
214 : { 1, 7, 8, 0, 0 }, // 4 NullALU_WriteVMEM
215 : { 1, 7, 8, 0, 0 }, // 5 TransALU
216 : { 1, 7, 8, 0, 0 }, // 6 NullALU_WriteLDS
217 : { 1, 7, 8, 0, 0 }, // 7 NullALU_Write32Bit
218 : { 0, 0, 0, 0, 0 }, // 8 XALU
219 : { 1, 7, 8, 0, 0 }, // 9 NullALU_WriteSALU
220 : { 1, 7, 8, 0, 0 }, // 10 NullALU_WriteSMEM
221 : { 1, 7, 8, 0, 0 }, // 11 NullALU_WriteDouble
222 : { 1, 7, 8, 0, 0 }, // 12 NullALU_WriteQuarterRate32
223 : { 1, 7, 8, 0, 0 }, // 13 NullALU_WriteFloatFMA_WriteSALU
224 : { 1, 7, 8, 0, 0 }, // 14 NullALU_WriteDouble_WriteSALU
225 : { 0, ~0U, ~0U, ~0U, ~0U } // end marker
226 : };
227 :
228 : // ===============================================================
229 : // Data tables for the new per-operand machine model.
230 :
231 : // {ProcResourceIdx, Cycles}
232 : extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[] = {
233 : { 0, 0}, // Invalid
234 : { 6, 1}, // #1
235 : { 3, 1}, // #2
236 : { 5, 1}, // #3
237 : { 4, 1}, // #4
238 : { 4, 1}, // #5
239 : { 5, 1} // #6
240 : }; // AMDGPUWriteProcResTable
241 :
242 : // {Cycles, WriteResourceID}
243 : extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[] = {
244 : { 0, 0}, // Invalid
245 : {450, 0}, // #1 WriteVMEM
246 : {32, 0}, // #2 WriteLDS
247 : { 1, 0}, // #3 Write32Bit_WriteSALU
248 : {10, 0}, // #4 WriteSMEM
249 : { 4, 0}, // #5 WriteDouble_WriteQuarterRate32
250 : { 1, 0}, // #6 WriteFloatFMA_WriteSALU
251 : { 1, 0}, // #7 WriteSALU
252 : {16, 0}, // #8 WriteDouble
253 : {16, 0}, // #9 WriteFloatFMA_WriteDouble
254 : { 1, 0} // #10 WriteSALU
255 : }; // AMDGPUWriteLatencyTable
256 :
257 : // {UseIdx, WriteResourceID, Cycles}
258 : extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[] = {
259 : {0, 0, 0}, // Invalid
260 : }; // AMDGPUReadAdvanceTable
261 :
262 : // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
263 : static const llvm::MCSchedClassDesc SIFullSpeedModelSchedClasses[] = {
264 : {DBGFIELD("InvalidSchedClass") 65535, 0, 0, 0, 0, 0, 0, 0, 0},
265 : {DBGFIELD("AnyALU") 0, 0, 0, 0, 0, 0, 0, 0, 0}, // #1
266 : {DBGFIELD("NullALU") 0, 0, 0, 0, 0, 0, 0, 0, 0}, // #2
267 : {DBGFIELD("VecALU") 0, 0, 0, 0, 0, 0, 0, 0, 0}, // #3
268 : {DBGFIELD("NullALU_WriteVMEM") 1, 0, 0, 1, 1, 1, 1, 0, 0}, // #4
269 : {DBGFIELD("TransALU") 0, 0, 0, 0, 0, 0, 0, 0, 0}, // #5
270 : {DBGFIELD("NullALU_WriteLDS") 1, 0, 0, 2, 1, 2, 1, 0, 0}, // #6
271 : {DBGFIELD("NullALU_Write32Bit") 1, 0, 0, 3, 1, 3, 1, 0, 0}, // #7
272 : {DBGFIELD("XALU") 0, 0, 0, 0, 0, 0, 0, 0, 0}, // #8
273 : {DBGFIELD("NullALU_WriteSALU") 1, 0, 0, 4, 1, 3, 1, 0, 0}, // #9
274 : {DBGFIELD("NullALU_WriteSMEM") 1, 0, 0, 2, 1, 4, 1, 0, 0}, // #10
275 : {DBGFIELD("NullALU_WriteDouble") 1, 0, 0, 3, 1, 5, 1, 0, 0}, // #11
276 : {DBGFIELD("NullALU_WriteQuarterRate32") 1, 0, 0, 3, 1, 5, 1, 0, 0}, // #12
277 : {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, 0, 0, 5, 2, 6, 2, 0, 0}, // #13
278 : {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, 0, 0, 5, 2, 5, 2, 0, 0} // #14
279 : }; // SIFullSpeedModelSchedClasses
280 :
281 : // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
282 : static const llvm::MCSchedClassDesc SIQuarterSpeedModelSchedClasses[] = {
283 : {DBGFIELD("InvalidSchedClass") 65535, 0, 0, 0, 0, 0, 0, 0, 0},
284 : {DBGFIELD("AnyALU") 0, 0, 0, 0, 0, 0, 0, 0, 0}, // #1
285 : {DBGFIELD("NullALU") 0, 0, 0, 0, 0, 0, 0, 0, 0}, // #2
286 : {DBGFIELD("VecALU") 0, 0, 0, 0, 0, 0, 0, 0, 0}, // #3
287 : {DBGFIELD("NullALU_WriteVMEM") 1, 0, 0, 1, 1, 1, 1, 0, 0}, // #4
288 : {DBGFIELD("TransALU") 0, 0, 0, 0, 0, 0, 0, 0, 0}, // #5
289 : {DBGFIELD("NullALU_WriteLDS") 1, 0, 0, 2, 1, 2, 1, 0, 0}, // #6
290 : {DBGFIELD("NullALU_Write32Bit") 1, 0, 0, 3, 1, 3, 1, 0, 0}, // #7
291 : {DBGFIELD("XALU") 0, 0, 0, 0, 0, 0, 0, 0, 0}, // #8
292 : {DBGFIELD("NullALU_WriteSALU") 1, 0, 0, 4, 1, 3, 1, 0, 0}, // #9
293 : {DBGFIELD("NullALU_WriteSMEM") 1, 0, 0, 2, 1, 4, 1, 0, 0}, // #10
294 : {DBGFIELD("NullALU_WriteDouble") 1, 0, 0, 3, 1, 8, 1, 0, 0}, // #11
295 : {DBGFIELD("NullALU_WriteQuarterRate32") 1, 0, 0, 3, 1, 5, 1, 0, 0}, // #12
296 : {DBGFIELD("NullALU_WriteFloatFMA_WriteSALU") 2, 0, 0, 5, 2, 9, 2, 0, 0}, // #13
297 : {DBGFIELD("NullALU_WriteDouble_WriteSALU") 2, 0, 0, 5, 2, 9, 2, 0, 0} // #14
298 : }; // SIQuarterSpeedModelSchedClasses
299 :
300 : static const llvm::MCSchedModel NoSchedModel = {
301 : MCSchedModel::DefaultIssueWidth,
302 : MCSchedModel::DefaultMicroOpBufferSize,
303 : MCSchedModel::DefaultLoopMicroOpBufferSize,
304 : MCSchedModel::DefaultLoadLatency,
305 : MCSchedModel::DefaultHighLatency,
306 : MCSchedModel::DefaultMispredictPenalty,
307 : 0, // PostRAScheduler
308 : 1, // CompleteModel
309 : 0, // Processor ID
310 : 0, 0, 0, 0, // No instruction-level machine model.
311 : nullptr}; // No Itinerary
312 :
313 : static const llvm::MCSchedModel R600_VLIW5_ItinModel = {
314 : MCSchedModel::DefaultIssueWidth,
315 : MCSchedModel::DefaultMicroOpBufferSize,
316 : MCSchedModel::DefaultLoopMicroOpBufferSize,
317 : MCSchedModel::DefaultLoadLatency,
318 : MCSchedModel::DefaultHighLatency,
319 : MCSchedModel::DefaultMispredictPenalty,
320 : 0, // PostRAScheduler
321 : 1, // CompleteModel
322 : 1, // Processor ID
323 : 0, 0, 0, 0, // No instruction-level machine model.
324 : R600_VLIW5_Itin};
325 :
326 : // {Name, NumUnits, SuperIdx, IsBuffered}
327 : static const llvm::MCProcResourceDesc SIFullSpeedModelProcResources[] = {
328 : {DBGFIELD("InvalidUnit") 0, 0, 0},
329 : {DBGFIELD("HWBranch") 1, 0, 0}, // #1
330 : {DBGFIELD("HWExport") 7, 0, 0}, // #2
331 : {DBGFIELD("HWLGKM") 31, 0, 0}, // #3
332 : {DBGFIELD("HWSALU") 1, 0, 0}, // #4
333 : {DBGFIELD("HWVALU") 1, 0, 0}, // #5
334 : {DBGFIELD("HWVMEM") 15, 0, 0} // #6
335 : };
336 :
337 : static const llvm::MCSchedModel SIFullSpeedModel = {
338 : MCSchedModel::DefaultIssueWidth,
339 : MCSchedModel::DefaultMicroOpBufferSize,
340 : MCSchedModel::DefaultLoopMicroOpBufferSize,
341 : MCSchedModel::DefaultLoadLatency,
342 : MCSchedModel::DefaultHighLatency,
343 : MCSchedModel::DefaultMispredictPenalty,
344 : 0, // PostRAScheduler
345 : 1, // CompleteModel
346 : 2, // Processor ID
347 : SIFullSpeedModelProcResources,
348 : SIFullSpeedModelSchedClasses,
349 : 7,
350 : 15,
351 : nullptr}; // No Itinerary
352 :
353 : // {Name, NumUnits, SuperIdx, IsBuffered}
354 : static const llvm::MCProcResourceDesc SIQuarterSpeedModelProcResources[] = {
355 : {DBGFIELD("InvalidUnit") 0, 0, 0},
356 : {DBGFIELD("HWBranch") 1, 0, 0}, // #1
357 : {DBGFIELD("HWExport") 7, 0, 0}, // #2
358 : {DBGFIELD("HWLGKM") 31, 0, 0}, // #3
359 : {DBGFIELD("HWSALU") 1, 0, 0}, // #4
360 : {DBGFIELD("HWVALU") 1, 0, 0}, // #5
361 : {DBGFIELD("HWVMEM") 15, 0, 0} // #6
362 : };
363 :
364 : static const llvm::MCSchedModel SIQuarterSpeedModel = {
365 : MCSchedModel::DefaultIssueWidth,
366 : MCSchedModel::DefaultMicroOpBufferSize,
367 : MCSchedModel::DefaultLoopMicroOpBufferSize,
368 : MCSchedModel::DefaultLoadLatency,
369 : MCSchedModel::DefaultHighLatency,
370 : MCSchedModel::DefaultMispredictPenalty,
371 : 0, // PostRAScheduler
372 : 1, // CompleteModel
373 : 3, // Processor ID
374 : SIQuarterSpeedModelProcResources,
375 : SIQuarterSpeedModelSchedClasses,
376 : 7,
377 : 15,
378 : nullptr}; // No Itinerary
379 :
380 : static const llvm::MCSchedModel R600_VLIW4_ItinModel = {
381 : MCSchedModel::DefaultIssueWidth,
382 : MCSchedModel::DefaultMicroOpBufferSize,
383 : MCSchedModel::DefaultLoopMicroOpBufferSize,
384 : MCSchedModel::DefaultLoadLatency,
385 : MCSchedModel::DefaultHighLatency,
386 : MCSchedModel::DefaultMispredictPenalty,
387 : 0, // PostRAScheduler
388 : 1, // CompleteModel
389 : 4, // Processor ID
390 : 0, 0, 0, 0, // No instruction-level machine model.
391 : R600_VLIW4_Itin};
392 :
393 : // Sorted (by key) array of itineraries for CPU subtype.
394 : extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[] = {
395 : { "", (const void *)&R600_VLIW5_ItinModel },
396 : { "SI", (const void *)&SIFullSpeedModel },
397 : { "barts", (const void *)&R600_VLIW5_ItinModel },
398 : { "bonaire", (const void *)&SIQuarterSpeedModel },
399 : { "caicos", (const void *)&R600_VLIW5_ItinModel },
400 : { "carrizo", (const void *)&SIQuarterSpeedModel },
401 : { "cayman", (const void *)&R600_VLIW4_ItinModel },
402 : { "cedar", (const void *)&R600_VLIW5_ItinModel },
403 : { "cypress", (const void *)&R600_VLIW5_ItinModel },
404 : { "hainan", (const void *)&SIQuarterSpeedModel },
405 : { "hawaii", (const void *)&SIFullSpeedModel },
406 : { "iceland", (const void *)&SIQuarterSpeedModel },
407 : { "juniper", (const void *)&R600_VLIW5_ItinModel },
408 : { "kabini", (const void *)&SIQuarterSpeedModel },
409 : { "kaveri", (const void *)&SIQuarterSpeedModel },
410 : { "mullins", (const void *)&SIQuarterSpeedModel },
411 : { "oland", (const void *)&SIQuarterSpeedModel },
412 : { "pitcairn", (const void *)&SIQuarterSpeedModel },
413 : { "r600", (const void *)&R600_VLIW5_ItinModel },
414 : { "r630", (const void *)&R600_VLIW5_ItinModel },
415 : { "redwood", (const void *)&R600_VLIW5_ItinModel },
416 : { "rs880", (const void *)&R600_VLIW5_ItinModel },
417 : { "rv670", (const void *)&R600_VLIW5_ItinModel },
418 : { "rv710", (const void *)&R600_VLIW5_ItinModel },
419 : { "rv730", (const void *)&R600_VLIW5_ItinModel },
420 : { "rv770", (const void *)&R600_VLIW5_ItinModel },
421 : { "sumo", (const void *)&R600_VLIW5_ItinModel },
422 : { "tahiti", (const void *)&SIFullSpeedModel },
423 : { "tonga", (const void *)&SIQuarterSpeedModel },
424 : { "turks", (const void *)&R600_VLIW5_ItinModel },
425 : { "verde", (const void *)&SIQuarterSpeedModel }
426 : };
427 : #undef DBGFIELD
428 884 : static inline void InitAMDGPUMCSubtargetInfo(MCSubtargetInfo *II, const Triple &TT, StringRef CPU, StringRef FS) {
429 : II->InitMCSubtargetInfo(TT, CPU, FS, AMDGPUFeatureKV, AMDGPUSubTypeKV,
430 : AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable,
431 884 : AMDGPUStages, AMDGPUOperandCycles, AMDGPUForwardingPaths);
432 884 : }
433 :
434 : } // End llvm namespace
435 : #endif // GET_SUBTARGETINFO_MC_DESC
436 :
437 :
438 : #ifdef GET_SUBTARGETINFO_TARGET_DESC
439 : #undef GET_SUBTARGETINFO_TARGET_DESC
440 : #include "llvm/Support/Debug.h"
441 : #include "llvm/Support/raw_ostream.h"
442 : // ParseSubtargetFeatures - Parses features string setting specified
443 : // subtarget options.
444 840 : void llvm::AMDGPUSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
445 : DEBUG(dbgs() << "\nFeatures:" << FS);
446 : DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
447 840 : InitMCProcessorInfo(CPU, FS);
448 840 : const FeatureBitset& Bits = getFeatureBits();
449 1680 : if (Bits[AMDGPU::Feature64BitPtr]) Is64bit = true;
450 1680 : if (Bits[AMDGPU::FeatureCFALUBug]) CFALUBug = true;
451 1680 : if (Bits[AMDGPU::FeatureCIInsts]) CIInsts = true;
452 1680 : if (Bits[AMDGPU::FeatureCaymanISA]) CaymanISA = true;
453 1680 : if (Bits[AMDGPU::FeatureDisable]) FeatureDisable = true;
454 1680 : if (Bits[AMDGPU::FeatureDumpCode]) DumpCode = true;
455 1680 : if (Bits[AMDGPU::FeatureDumpCodeLower]) DumpCode = true;
456 1680 : if (Bits[AMDGPU::FeatureEnableLoadStoreOpt]) EnableLoadStoreOpt = true;
457 1680 : if (Bits[AMDGPU::FeatureEvergreen] && Gen < AMDGPUSubtarget::EVERGREEN) Gen = AMDGPUSubtarget::EVERGREEN;
458 1680 : if (Bits[AMDGPU::FeatureFP32Denormals]) FP32Denormals = true;
459 1680 : if (Bits[AMDGPU::FeatureFP64]) FP64 = true;
460 1680 : if (Bits[AMDGPU::FeatureFP64Denormals]) FP64Denormals = true;
461 1680 : if (Bits[AMDGPU::FeatureFastFMAF32]) FastFMAF32 = true;
462 1680 : if (Bits[AMDGPU::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
463 1680 : if (Bits[AMDGPU::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
464 1680 : if (Bits[AMDGPU::FeatureFlatAddressSpace]) FlatAddressSpace = true;
465 1680 : if (Bits[AMDGPU::FeatureGCN]) IsGCN = true;
466 1680 : if (Bits[AMDGPU::FeatureGCN1Encoding]) GCN1Encoding = true;
467 1680 : if (Bits[AMDGPU::FeatureGCN3Encoding]) GCN3Encoding = true;
468 1680 : if (Bits[AMDGPU::FeatureIRStructurizer]) EnableIRStructurizer = false;
469 1680 : if (Bits[AMDGPU::FeatureIfCvt]) EnableIfCvt = false;
470 1680 : if (Bits[AMDGPU::FeatureLDSBankCount16] && LDSBankCount < 16) LDSBankCount = 16;
471 1680 : if (Bits[AMDGPU::FeatureLDSBankCount32] && LDSBankCount < 32) LDSBankCount = 32;
472 1680 : if (Bits[AMDGPU::FeatureLocalMemorySize0] && LocalMemorySize < 0) LocalMemorySize = 0;
473 1680 : if (Bits[AMDGPU::FeatureLocalMemorySize32768] && LocalMemorySize < 32768) LocalMemorySize = 32768;
474 1680 : if (Bits[AMDGPU::FeatureLocalMemorySize65536] && LocalMemorySize < 65536) LocalMemorySize = 65536;
475 1680 : if (Bits[AMDGPU::FeatureNorthernIslands] && Gen < AMDGPUSubtarget::NORTHERN_ISLANDS) Gen = AMDGPUSubtarget::NORTHERN_ISLANDS;
476 1680 : if (Bits[AMDGPU::FeaturePromoteAlloca]) EnablePromoteAlloca = true;
477 1680 : if (Bits[AMDGPU::FeatureR600] && Gen < AMDGPUSubtarget::R600) Gen = AMDGPUSubtarget::R600;
478 1680 : if (Bits[AMDGPU::FeatureR600ALUInst]) R600ALUInst = false;
479 1680 : if (Bits[AMDGPU::FeatureR700] && Gen < AMDGPUSubtarget::R700) Gen = AMDGPUSubtarget::R700;
480 1680 : if (Bits[AMDGPU::FeatureSGPRInitBug]) SGPRInitBug = true;
481 1680 : if (Bits[AMDGPU::FeatureSeaIslands] && Gen < AMDGPUSubtarget::SEA_ISLANDS) Gen = AMDGPUSubtarget::SEA_ISLANDS;
482 1680 : if (Bits[AMDGPU::FeatureSouthernIslands] && Gen < AMDGPUSubtarget::SOUTHERN_ISLANDS) Gen = AMDGPUSubtarget::SOUTHERN_ISLANDS;
483 1680 : if (Bits[AMDGPU::FeatureVGPRSpilling]) EnableVGPRSpilling = true;
484 1680 : if (Bits[AMDGPU::FeatureVertexCache]) HasVertexCache = true;
485 1680 : if (Bits[AMDGPU::FeatureVolcanicIslands] && Gen < AMDGPUSubtarget::VOLCANIC_ISLANDS) Gen = AMDGPUSubtarget::VOLCANIC_ISLANDS;
486 1680 : if (Bits[AMDGPU::FeatureWavefrontSize16] && WavefrontSize < 16) WavefrontSize = 16;
487 1680 : if (Bits[AMDGPU::FeatureWavefrontSize32] && WavefrontSize < 32) WavefrontSize = 32;
488 1680 : if (Bits[AMDGPU::FeatureWavefrontSize64] && WavefrontSize < 64) WavefrontSize = 64;
489 840 : }
490 : #endif // GET_SUBTARGETINFO_TARGET_DESC
491 :
492 :
493 : #ifdef GET_SUBTARGETINFO_HEADER
494 : #undef GET_SUBTARGETINFO_HEADER
495 : namespace llvm {
496 : class DFAPacketizer;
497 828 : struct AMDGPUGenSubtargetInfo : public TargetSubtargetInfo {
498 : explicit AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
499 : public:
500 : unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
501 : DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
502 : };
503 : } // End llvm namespace
504 : #endif // GET_SUBTARGETINFO_HEADER
505 :
506 :
507 : #ifdef GET_SUBTARGETINFO_CTOR
508 : #undef GET_SUBTARGETINFO_CTOR
509 : #include "llvm/CodeGen/TargetSchedule.h"
510 : namespace llvm {
511 : extern const llvm::SubtargetFeatureKV AMDGPUFeatureKV[];
512 : extern const llvm::SubtargetFeatureKV AMDGPUSubTypeKV[];
513 : extern const llvm::SubtargetInfoKV AMDGPUProcSchedKV[];
514 : extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[];
515 : extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[];
516 : extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[];
517 : extern const llvm::InstrStage AMDGPUStages[];
518 : extern const unsigned AMDGPUOperandCycles[];
519 : extern const unsigned AMDGPUForwardingPaths[];
520 840 : AMDGPUGenSubtargetInfo::AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
521 840 : : TargetSubtargetInfo() {
522 : InitMCSubtargetInfo(TT, CPU, FS, makeArrayRef(AMDGPUFeatureKV, 39), makeArrayRef(AMDGPUSubTypeKV, 31),
523 : AMDGPUProcSchedKV, AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable,
524 840 : AMDGPUStages, AMDGPUOperandCycles, AMDGPUForwardingPaths);
525 840 : }
526 :
527 0 : unsigned AMDGPUGenSubtargetInfo
528 : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
529 0 : report_fatal_error("Expected a variant SchedClass");
530 : } // AMDGPUGenSubtargetInfo::resolveSchedClass
531 : } // End llvm namespace
532 : #endif // GET_SUBTARGETINFO_CTOR
533 :
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