LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/WebAssembly - WebAssemblyGenFastISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 229 772 29.7 %
Date: 2018-10-20 13:21:21 Functions: 22 64 34.4 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* "Fast" Instruction Selector for the WebAssembly target                     *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : // FastEmit Immediate Predicate functions.
      11             : static bool Predicate_ImmI8(int64_t Imm) {
      12             : return ((uint64_t)Imm & ((1UL << 8) - 1)) == (uint64_t)Imm;
      13             : }
      14             : static bool Predicate_ImmI16(int64_t Imm) {
      15             : return ((uint64_t)Imm & ((1UL << 16) - 1)) == (uint64_t)Imm;
      16             : }
      17             : static bool Predicate_LaneIdx4(int64_t Imm) {
      18             : return 0 <= Imm && Imm < 4;
      19             : }
      20             : static bool Predicate_LaneIdx2(int64_t Imm) {
      21             : return 0 <= Imm && Imm < 2;
      22             : }
      23             : static bool Predicate_LaneIdx16(int64_t Imm) {
      24             : return 0 <= Imm && Imm < 16;
      25             : }
      26             : static bool Predicate_LaneIdx8(int64_t Imm) {
      27             : return 0 <= Imm && Imm < 8;
      28             : }
      29             : static bool Predicate_LaneIdx32(int64_t Imm) {
      30             : return 0 <= Imm && Imm < 32;
      31             : }
      32             : 
      33             : 
      34             : // FastEmit functions for ISD::ANY_EXTEND.
      35             : 
      36             : unsigned fastEmit_ISD_ANY_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      37           0 :   if (RetVT.SimpleTy != MVT::i64)
      38             :     return 0;
      39           0 :   return fastEmitInst_r(WebAssembly::I64_EXTEND_U_I32, &WebAssembly::I64RegClass, Op0, Op0IsKill);
      40             : }
      41             : 
      42             : unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
      43           0 :   switch (VT.SimpleTy) {
      44           0 :   case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
      45             :   default: return 0;
      46             :   }
      47             : }
      48             : 
      49             : // FastEmit functions for ISD::BITCAST.
      50             : 
      51             : unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      52           1 :   if (RetVT.SimpleTy != MVT::f32)
      53             :     return 0;
      54           1 :   return fastEmitInst_r(WebAssembly::F32_REINTERPRET_I32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
      55             : }
      56             : 
      57             : unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      58           1 :   if (RetVT.SimpleTy != MVT::f64)
      59             :     return 0;
      60           1 :   return fastEmitInst_r(WebAssembly::F64_REINTERPRET_I64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
      61             : }
      62             : 
      63             : unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      64           1 :   if (RetVT.SimpleTy != MVT::i32)
      65             :     return 0;
      66           1 :   return fastEmitInst_r(WebAssembly::I32_REINTERPRET_F32, &WebAssembly::I32RegClass, Op0, Op0IsKill);
      67             : }
      68             : 
      69             : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      70           1 :   if (RetVT.SimpleTy != MVT::i64)
      71             :     return 0;
      72           1 :   return fastEmitInst_r(WebAssembly::I64_REINTERPRET_F64, &WebAssembly::I64RegClass, Op0, Op0IsKill);
      73             : }
      74             : 
      75           4 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
      76           4 :   switch (VT.SimpleTy) {
      77           1 :   case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
      78           1 :   case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
      79           1 :   case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
      80           1 :   case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
      81             :   default: return 0;
      82             :   }
      83             : }
      84             : 
      85             : // FastEmit functions for ISD::CTLZ.
      86             : 
      87             : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      88           0 :   if (RetVT.SimpleTy != MVT::i32)
      89             :     return 0;
      90           0 :   return fastEmitInst_r(WebAssembly::CLZ_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill);
      91             : }
      92             : 
      93             : unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
      94           0 :   if (RetVT.SimpleTy != MVT::i64)
      95             :     return 0;
      96           0 :   return fastEmitInst_r(WebAssembly::CLZ_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill);
      97             : }
      98             : 
      99           0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     100           0 :   switch (VT.SimpleTy) {
     101           0 :   case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     102           0 :   case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     103             :   default: return 0;
     104             :   }
     105             : }
     106             : 
     107             : // FastEmit functions for ISD::CTPOP.
     108             : 
     109             : unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     110           0 :   if (RetVT.SimpleTy != MVT::i32)
     111             :     return 0;
     112           0 :   return fastEmitInst_r(WebAssembly::POPCNT_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     113             : }
     114             : 
     115             : unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     116           0 :   if (RetVT.SimpleTy != MVT::i64)
     117             :     return 0;
     118           0 :   return fastEmitInst_r(WebAssembly::POPCNT_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     119             : }
     120             : 
     121           0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     122           0 :   switch (VT.SimpleTy) {
     123           0 :   case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     124           0 :   case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     125             :   default: return 0;
     126             :   }
     127             : }
     128             : 
     129             : // FastEmit functions for ISD::CTTZ.
     130             : 
     131             : unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     132           0 :   if (RetVT.SimpleTy != MVT::i32)
     133             :     return 0;
     134           0 :   return fastEmitInst_r(WebAssembly::CTZ_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     135             : }
     136             : 
     137             : unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     138           0 :   if (RetVT.SimpleTy != MVT::i64)
     139             :     return 0;
     140           0 :   return fastEmitInst_r(WebAssembly::CTZ_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     141             : }
     142             : 
     143           0 : unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     144           0 :   switch (VT.SimpleTy) {
     145           0 :   case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
     146           0 :   case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
     147             :   default: return 0;
     148             :   }
     149             : }
     150             : 
     151             : // FastEmit functions for ISD::FABS.
     152             : 
     153             : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     154           0 :   if (RetVT.SimpleTy != MVT::f32)
     155             :     return 0;
     156           0 :   return fastEmitInst_r(WebAssembly::ABS_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     157             : }
     158             : 
     159             : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     160           0 :   if (RetVT.SimpleTy != MVT::f64)
     161             :     return 0;
     162           0 :   return fastEmitInst_r(WebAssembly::ABS_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     163             : }
     164             : 
     165             : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     166           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     167             :     return 0;
     168           0 :   if ((Subtarget->hasSIMD128())) {
     169           0 :     return fastEmitInst_r(WebAssembly::ABS_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     170             :   }
     171             :   return 0;
     172             : }
     173             : 
     174             : unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     175           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     176             :     return 0;
     177           0 :   if ((Subtarget->hasSIMD128())) {
     178           0 :     return fastEmitInst_r(WebAssembly::ABS_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     179             :   }
     180             :   return 0;
     181             : }
     182             : 
     183           0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     184           0 :   switch (VT.SimpleTy) {
     185           0 :   case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
     186           0 :   case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
     187           0 :   case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     188           0 :   case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     189             :   default: return 0;
     190             :   }
     191             : }
     192             : 
     193             : // FastEmit functions for ISD::FCEIL.
     194             : 
     195             : unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     196           0 :   if (RetVT.SimpleTy != MVT::f32)
     197             :     return 0;
     198           0 :   return fastEmitInst_r(WebAssembly::CEIL_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     199             : }
     200             : 
     201             : unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     202           0 :   if (RetVT.SimpleTy != MVT::f64)
     203             :     return 0;
     204           0 :   return fastEmitInst_r(WebAssembly::CEIL_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     205             : }
     206             : 
     207           0 : unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     208           0 :   switch (VT.SimpleTy) {
     209           0 :   case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
     210           0 :   case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
     211             :   default: return 0;
     212             :   }
     213             : }
     214             : 
     215             : // FastEmit functions for ISD::FFLOOR.
     216             : 
     217             : unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     218           0 :   if (RetVT.SimpleTy != MVT::f32)
     219             :     return 0;
     220           0 :   return fastEmitInst_r(WebAssembly::FLOOR_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     221             : }
     222             : 
     223             : unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     224           0 :   if (RetVT.SimpleTy != MVT::f64)
     225             :     return 0;
     226           0 :   return fastEmitInst_r(WebAssembly::FLOOR_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     227             : }
     228             : 
     229           0 : unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     230           0 :   switch (VT.SimpleTy) {
     231           0 :   case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
     232           0 :   case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
     233             :   default: return 0;
     234             :   }
     235             : }
     236             : 
     237             : // FastEmit functions for ISD::FNEARBYINT.
     238             : 
     239             : unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     240           0 :   if (RetVT.SimpleTy != MVT::f32)
     241             :     return 0;
     242           0 :   return fastEmitInst_r(WebAssembly::NEAREST_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     243             : }
     244             : 
     245             : unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     246           0 :   if (RetVT.SimpleTy != MVT::f64)
     247             :     return 0;
     248           0 :   return fastEmitInst_r(WebAssembly::NEAREST_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     249             : }
     250             : 
     251           0 : unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     252           0 :   switch (VT.SimpleTy) {
     253           0 :   case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     254           0 :   case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     255             :   default: return 0;
     256             :   }
     257             : }
     258             : 
     259             : // FastEmit functions for ISD::FNEG.
     260             : 
     261             : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     262           0 :   if (RetVT.SimpleTy != MVT::f32)
     263             :     return 0;
     264           0 :   return fastEmitInst_r(WebAssembly::NEG_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     265             : }
     266             : 
     267             : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     268           0 :   if (RetVT.SimpleTy != MVT::f64)
     269             :     return 0;
     270           0 :   return fastEmitInst_r(WebAssembly::NEG_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     271             : }
     272             : 
     273             : unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     274           3 :   if (RetVT.SimpleTy != MVT::v4f32)
     275             :     return 0;
     276           3 :   if ((Subtarget->hasSIMD128())) {
     277           3 :     return fastEmitInst_r(WebAssembly::NEG_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     278             :   }
     279             :   return 0;
     280             : }
     281             : 
     282             : unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     283           2 :   if (RetVT.SimpleTy != MVT::v2f64)
     284             :     return 0;
     285           2 :   if ((Subtarget->hasSIMD128())) {
     286           2 :     return fastEmitInst_r(WebAssembly::NEG_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     287             :   }
     288             :   return 0;
     289             : }
     290             : 
     291           5 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     292           5 :   switch (VT.SimpleTy) {
     293           0 :   case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
     294           0 :   case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
     295           3 :   case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     296           2 :   case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     297             :   default: return 0;
     298             :   }
     299             : }
     300             : 
     301             : // FastEmit functions for ISD::FP_EXTEND.
     302             : 
     303             : unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     304           0 :   if (RetVT.SimpleTy != MVT::f64)
     305             :     return 0;
     306           0 :   return fastEmitInst_r(WebAssembly::F64_PROMOTE_F32, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     307             : }
     308             : 
     309             : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     310           0 :   switch (VT.SimpleTy) {
     311           0 :   case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
     312             :   default: return 0;
     313             :   }
     314             : }
     315             : 
     316             : // FastEmit functions for ISD::FP_ROUND.
     317             : 
     318             : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     319           0 :   if (RetVT.SimpleTy != MVT::f32)
     320             :     return 0;
     321           0 :   return fastEmitInst_r(WebAssembly::F32_DEMOTE_F64, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     322             : }
     323             : 
     324             : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     325           0 :   switch (VT.SimpleTy) {
     326           0 :   case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
     327             :   default: return 0;
     328             :   }
     329             : }
     330             : 
     331             : // FastEmit functions for ISD::FP_TO_SINT.
     332             : 
     333           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     334           0 :   if ((!Subtarget->hasNontrappingFPToInt())) {
     335           0 :     return fastEmitInst_r(WebAssembly::FP_TO_SINT_I32_F32, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     336             :   }
     337             :   if ((Subtarget->hasNontrappingFPToInt())) {
     338           0 :     return fastEmitInst_r(WebAssembly::I32_TRUNC_S_SAT_F32, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     339             :   }
     340             :   return 0;
     341             : }
     342             : 
     343           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     344           0 :   if ((!Subtarget->hasNontrappingFPToInt())) {
     345           0 :     return fastEmitInst_r(WebAssembly::FP_TO_SINT_I64_F32, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     346             :   }
     347             :   if ((Subtarget->hasNontrappingFPToInt())) {
     348           0 :     return fastEmitInst_r(WebAssembly::I64_TRUNC_S_SAT_F32, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     349             :   }
     350             :   return 0;
     351             : }
     352             : 
     353           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     354           0 : switch (RetVT.SimpleTy) {
     355           0 :   case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0, Op0IsKill);
     356           0 :   case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0, Op0IsKill);
     357             :   default: return 0;
     358             : }
     359             : }
     360             : 
     361           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     362           0 :   if ((!Subtarget->hasNontrappingFPToInt())) {
     363           0 :     return fastEmitInst_r(WebAssembly::FP_TO_SINT_I32_F64, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     364             :   }
     365             :   if ((Subtarget->hasNontrappingFPToInt())) {
     366           0 :     return fastEmitInst_r(WebAssembly::I32_TRUNC_S_SAT_F64, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     367             :   }
     368             :   return 0;
     369             : }
     370             : 
     371           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     372           0 :   if ((!Subtarget->hasNontrappingFPToInt())) {
     373           0 :     return fastEmitInst_r(WebAssembly::FP_TO_SINT_I64_F64, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     374             :   }
     375             :   if ((Subtarget->hasNontrappingFPToInt())) {
     376           0 :     return fastEmitInst_r(WebAssembly::I64_TRUNC_S_SAT_F64, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     377             :   }
     378             :   return 0;
     379             : }
     380             : 
     381           0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     382           0 : switch (RetVT.SimpleTy) {
     383           0 :   case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0, Op0IsKill);
     384           0 :   case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0, Op0IsKill);
     385             :   default: return 0;
     386             : }
     387             : }
     388             : 
     389             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     390           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     391             :     return 0;
     392           0 :   if ((Subtarget->hasSIMD128())) {
     393           0 :     return fastEmitInst_r(WebAssembly::fp_to_sint_v4i32_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     394             :   }
     395             :   return 0;
     396             : }
     397             : 
     398             : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     399           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     400             :     return 0;
     401           0 :   if ((Subtarget->hasSIMD128())) {
     402           0 :     return fastEmitInst_r(WebAssembly::fp_to_sint_v2i64_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     403             :   }
     404             :   return 0;
     405             : }
     406             : 
     407           0 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     408           0 :   switch (VT.SimpleTy) {
     409           0 :   case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     410           0 :   case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     411           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     412           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     413             :   default: return 0;
     414             :   }
     415             : }
     416             : 
     417             : // FastEmit functions for ISD::FP_TO_UINT.
     418             : 
     419           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     420           0 :   if ((!Subtarget->hasNontrappingFPToInt())) {
     421           0 :     return fastEmitInst_r(WebAssembly::FP_TO_UINT_I32_F32, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     422             :   }
     423             :   if ((Subtarget->hasNontrappingFPToInt())) {
     424           0 :     return fastEmitInst_r(WebAssembly::I32_TRUNC_U_SAT_F32, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     425             :   }
     426             :   return 0;
     427             : }
     428             : 
     429           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     430           0 :   if ((!Subtarget->hasNontrappingFPToInt())) {
     431           0 :     return fastEmitInst_r(WebAssembly::FP_TO_UINT_I64_F32, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     432             :   }
     433             :   if ((Subtarget->hasNontrappingFPToInt())) {
     434           0 :     return fastEmitInst_r(WebAssembly::I64_TRUNC_U_SAT_F32, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     435             :   }
     436             :   return 0;
     437             : }
     438             : 
     439           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     440           0 : switch (RetVT.SimpleTy) {
     441           0 :   case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0, Op0IsKill);
     442           0 :   case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0, Op0IsKill);
     443             :   default: return 0;
     444             : }
     445             : }
     446             : 
     447           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     448           0 :   if ((!Subtarget->hasNontrappingFPToInt())) {
     449           0 :     return fastEmitInst_r(WebAssembly::FP_TO_UINT_I32_F64, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     450             :   }
     451             :   if ((Subtarget->hasNontrappingFPToInt())) {
     452           0 :     return fastEmitInst_r(WebAssembly::I32_TRUNC_U_SAT_F64, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     453             :   }
     454             :   return 0;
     455             : }
     456             : 
     457           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     458           0 :   if ((!Subtarget->hasNontrappingFPToInt())) {
     459           0 :     return fastEmitInst_r(WebAssembly::FP_TO_UINT_I64_F64, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     460             :   }
     461             :   if ((Subtarget->hasNontrappingFPToInt())) {
     462           0 :     return fastEmitInst_r(WebAssembly::I64_TRUNC_U_SAT_F64, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     463             :   }
     464             :   return 0;
     465             : }
     466             : 
     467           0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     468           0 : switch (RetVT.SimpleTy) {
     469           0 :   case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0, Op0IsKill);
     470           0 :   case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0, Op0IsKill);
     471             :   default: return 0;
     472             : }
     473             : }
     474             : 
     475             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     476           0 :   if (RetVT.SimpleTy != MVT::v4i32)
     477             :     return 0;
     478           0 :   if ((Subtarget->hasSIMD128())) {
     479           0 :     return fastEmitInst_r(WebAssembly::fp_to_uint_v4i32_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     480             :   }
     481             :   return 0;
     482             : }
     483             : 
     484             : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     485           0 :   if (RetVT.SimpleTy != MVT::v2i64)
     486             :     return 0;
     487           0 :   if ((Subtarget->hasSIMD128())) {
     488           0 :     return fastEmitInst_r(WebAssembly::fp_to_uint_v2i64_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     489             :   }
     490             :   return 0;
     491             : }
     492             : 
     493           0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     494           0 :   switch (VT.SimpleTy) {
     495           0 :   case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     496           0 :   case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     497           0 :   case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     498           0 :   case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     499             :   default: return 0;
     500             :   }
     501             : }
     502             : 
     503             : // FastEmit functions for ISD::FRINT.
     504             : 
     505             : unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     506           0 :   if (RetVT.SimpleTy != MVT::f32)
     507             :     return 0;
     508           0 :   return fastEmitInst_r(WebAssembly::NEAREST_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     509             : }
     510             : 
     511             : unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     512           0 :   if (RetVT.SimpleTy != MVT::f64)
     513             :     return 0;
     514           0 :   return fastEmitInst_r(WebAssembly::NEAREST_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     515             : }
     516             : 
     517           0 : unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     518           0 :   switch (VT.SimpleTy) {
     519           0 :   case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     520           0 :   case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     521             :   default: return 0;
     522             :   }
     523             : }
     524             : 
     525             : // FastEmit functions for ISD::FSQRT.
     526             : 
     527             : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     528           0 :   if (RetVT.SimpleTy != MVT::f32)
     529             :     return 0;
     530           0 :   return fastEmitInst_r(WebAssembly::SQRT_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     531             : }
     532             : 
     533             : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     534           0 :   if (RetVT.SimpleTy != MVT::f64)
     535             :     return 0;
     536           0 :   return fastEmitInst_r(WebAssembly::SQRT_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     537             : }
     538             : 
     539             : unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     540           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     541             :     return 0;
     542           0 :   if ((Subtarget->hasSIMD128())) {
     543           0 :     return fastEmitInst_r(WebAssembly::SQRT_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     544             :   }
     545             :   return 0;
     546             : }
     547             : 
     548             : unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     549           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     550             :     return 0;
     551           0 :   if ((Subtarget->hasSIMD128())) {
     552           0 :     return fastEmitInst_r(WebAssembly::SQRT_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     553             :   }
     554             :   return 0;
     555             : }
     556             : 
     557           0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     558           0 :   switch (VT.SimpleTy) {
     559           0 :   case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
     560           0 :   case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
     561           0 :   case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     562           0 :   case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     563             :   default: return 0;
     564             :   }
     565             : }
     566             : 
     567             : // FastEmit functions for ISD::FTRUNC.
     568             : 
     569             : unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     570           0 :   if (RetVT.SimpleTy != MVT::f32)
     571             :     return 0;
     572           0 :   return fastEmitInst_r(WebAssembly::TRUNC_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     573             : }
     574             : 
     575             : unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     576           0 :   if (RetVT.SimpleTy != MVT::f64)
     577             :     return 0;
     578           0 :   return fastEmitInst_r(WebAssembly::TRUNC_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     579             : }
     580             : 
     581           0 : unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     582           0 :   switch (VT.SimpleTy) {
     583           0 :   case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
     584           0 :   case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
     585             :   default: return 0;
     586             :   }
     587             : }
     588             : 
     589             : // FastEmit functions for ISD::SIGN_EXTEND.
     590             : 
     591             : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     592           0 :   if (RetVT.SimpleTy != MVT::i64)
     593             :     return 0;
     594           0 :   return fastEmitInst_r(WebAssembly::I64_EXTEND_S_I32, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     595             : }
     596             : 
     597             : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     598           0 :   switch (VT.SimpleTy) {
     599           0 :   case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     600             :   default: return 0;
     601             :   }
     602             : }
     603             : 
     604             : // FastEmit functions for ISD::SINT_TO_FP.
     605             : 
     606             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     607           0 :   return fastEmitInst_r(WebAssembly::F32_CONVERT_S_I32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     608             : }
     609             : 
     610             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     611           0 :   return fastEmitInst_r(WebAssembly::F64_CONVERT_S_I32, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     612             : }
     613             : 
     614           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     615           0 : switch (RetVT.SimpleTy) {
     616           0 :   case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
     617           0 :   case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
     618             :   default: return 0;
     619             : }
     620             : }
     621             : 
     622             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     623           0 :   return fastEmitInst_r(WebAssembly::F32_CONVERT_S_I64, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     624             : }
     625             : 
     626             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     627           0 :   return fastEmitInst_r(WebAssembly::F64_CONVERT_S_I64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     628             : }
     629             : 
     630           0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     631           0 : switch (RetVT.SimpleTy) {
     632           0 :   case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill);
     633           0 :   case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0, Op0IsKill);
     634             :   default: return 0;
     635             : }
     636             : }
     637             : 
     638             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     639           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     640             :     return 0;
     641           0 :   if ((Subtarget->hasSIMD128())) {
     642           0 :     return fastEmitInst_r(WebAssembly::sint_to_fp_v4f32_v4i32, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     643             :   }
     644             :   return 0;
     645             : }
     646             : 
     647             : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     648           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     649             :     return 0;
     650           0 :   if ((Subtarget->hasSIMD128())) {
     651           0 :     return fastEmitInst_r(WebAssembly::sint_to_fp_v2f64_v2i64, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     652             :   }
     653             :   return 0;
     654             : }
     655             : 
     656           0 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     657           0 :   switch (VT.SimpleTy) {
     658           0 :   case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     659           0 :   case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     660           0 :   case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     661           0 :   case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     662             :   default: return 0;
     663             :   }
     664             : }
     665             : 
     666             : // FastEmit functions for ISD::TRUNCATE.
     667             : 
     668             : unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     669           0 :   if (RetVT.SimpleTy != MVT::i32)
     670             :     return 0;
     671           0 :   return fastEmitInst_r(WebAssembly::I32_WRAP_I64, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     672             : }
     673             : 
     674             : unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     675           0 :   switch (VT.SimpleTy) {
     676           0 :   case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0, Op0IsKill);
     677             :   default: return 0;
     678             :   }
     679             : }
     680             : 
     681             : // FastEmit functions for ISD::UINT_TO_FP.
     682             : 
     683             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     684           0 :   return fastEmitInst_r(WebAssembly::F32_CONVERT_U_I32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     685             : }
     686             : 
     687             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     688           0 :   return fastEmitInst_r(WebAssembly::F64_CONVERT_U_I32, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     689             : }
     690             : 
     691           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     692           0 : switch (RetVT.SimpleTy) {
     693           0 :   case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
     694           0 :   case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
     695             :   default: return 0;
     696             : }
     697             : }
     698             : 
     699             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     700           0 :   return fastEmitInst_r(WebAssembly::F32_CONVERT_U_I64, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     701             : }
     702             : 
     703             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     704           0 :   return fastEmitInst_r(WebAssembly::F64_CONVERT_U_I64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     705             : }
     706             : 
     707           0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     708           0 : switch (RetVT.SimpleTy) {
     709           0 :   case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f32_r(Op0, Op0IsKill);
     710           0 :   case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_MVT_f64_r(Op0, Op0IsKill);
     711             :   default: return 0;
     712             : }
     713             : }
     714             : 
     715             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     716           0 :   if (RetVT.SimpleTy != MVT::v4f32)
     717             :     return 0;
     718           0 :   if ((Subtarget->hasSIMD128())) {
     719           0 :     return fastEmitInst_r(WebAssembly::uint_to_fp_v4f32_v4i32, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     720             :   }
     721             :   return 0;
     722             : }
     723             : 
     724             : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     725           0 :   if (RetVT.SimpleTy != MVT::v2f64)
     726             :     return 0;
     727           0 :   if ((Subtarget->hasSIMD128())) {
     728           0 :     return fastEmitInst_r(WebAssembly::uint_to_fp_v2f64_v2i64, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     729             :   }
     730             :   return 0;
     731             : }
     732             : 
     733           0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     734           0 :   switch (VT.SimpleTy) {
     735           0 :   case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
     736           0 :   case MVT::i64: return fastEmit_ISD_UINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill);
     737           0 :   case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     738           0 :   case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     739             :   default: return 0;
     740             :   }
     741             : }
     742             : 
     743             : // FastEmit functions for ISD::ZERO_EXTEND.
     744             : 
     745             : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     746           0 :   if (RetVT.SimpleTy != MVT::i64)
     747             :     return 0;
     748           0 :   return fastEmitInst_r(WebAssembly::I64_EXTEND_U_I32, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     749             : }
     750             : 
     751             : unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     752           0 :   switch (VT.SimpleTy) {
     753           0 :   case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
     754             :   default: return 0;
     755             :   }
     756             : }
     757             : 
     758             : // FastEmit functions for WebAssemblyISD::BR_TABLE.
     759             : 
     760             : unsigned fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     761           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     762             :     return 0;
     763           0 :   return fastEmitInst_r(WebAssembly::BR_TABLE_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     764             : }
     765             : 
     766             : unsigned fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     767           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     768             :     return 0;
     769           0 :   return fastEmitInst_r(WebAssembly::BR_TABLE_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     770             : }
     771             : 
     772           0 : unsigned fastEmit_WebAssemblyISD_BR_TABLE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     773           0 :   switch (VT.SimpleTy) {
     774           0 :   case MVT::i32: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i32_r(RetVT, Op0, Op0IsKill);
     775           0 :   case MVT::i64: return fastEmit_WebAssemblyISD_BR_TABLE_MVT_i64_r(RetVT, Op0, Op0IsKill);
     776             :   default: return 0;
     777             :   }
     778             : }
     779             : 
     780             : // FastEmit functions for WebAssemblyISD::CALL0.
     781             : 
     782             : unsigned fastEmit_WebAssemblyISD_CALL0_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     783           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     784             :     return 0;
     785           0 :   return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_VOID, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     786             : }
     787             : 
     788             : unsigned fastEmit_WebAssemblyISD_CALL0_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     789           0 :   switch (VT.SimpleTy) {
     790           0 :   case MVT::i32: return fastEmit_WebAssemblyISD_CALL0_MVT_i32_r(RetVT, Op0, Op0IsKill);
     791             :   default: return 0;
     792             :   }
     793             : }
     794             : 
     795             : // FastEmit functions for WebAssemblyISD::CALL1.
     796             : 
     797             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
     798           0 :   return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     799             : }
     800             : 
     801             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
     802           0 :   return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     803             : }
     804             : 
     805             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
     806           0 :   return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     807             : }
     808             : 
     809             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
     810           0 :   return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     811             : }
     812             : 
     813             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
     814           0 :   if ((Subtarget->hasSIMD128())) {
     815           0 :     return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_v16i8, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     816             :   }
     817             :   return 0;
     818             : }
     819             : 
     820             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
     821           0 :   if ((Subtarget->hasSIMD128())) {
     822           0 :     return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_v8i16, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     823             :   }
     824             :   return 0;
     825             : }
     826             : 
     827             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
     828           0 :   if ((Subtarget->hasSIMD128())) {
     829           0 :     return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_v4i32, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     830             :   }
     831             :   return 0;
     832             : }
     833             : 
     834             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
     835           0 :   if ((Subtarget->hasSIMD128())) {
     836           0 :     return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_v2i64, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     837             :   }
     838             :   return 0;
     839             : }
     840             : 
     841             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
     842           0 :   if ((Subtarget->hasSIMD128())) {
     843           0 :     return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     844             :   }
     845             :   return 0;
     846             : }
     847             : 
     848             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
     849           0 :   if ((Subtarget->hasSIMD128())) {
     850           0 :     return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     851             :   }
     852             :   return 0;
     853             : }
     854             : 
     855             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_ExceptRef_r(unsigned Op0, bool Op0IsKill) {
     856           0 :   return fastEmitInst_r(WebAssembly::PCALL_INDIRECT_EXCEPT_REF, &WebAssembly::EXCEPT_REFRegClass, Op0, Op0IsKill);
     857             : }
     858             : 
     859           0 : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     860           0 : switch (RetVT.SimpleTy) {
     861           0 :   case MVT::i32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_i32_r(Op0, Op0IsKill);
     862           0 :   case MVT::i64: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_i64_r(Op0, Op0IsKill);
     863           0 :   case MVT::f32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
     864           0 :   case MVT::f64: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
     865           0 :   case MVT::v16i8: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v16i8_r(Op0, Op0IsKill);
     866           0 :   case MVT::v8i16: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v8i16_r(Op0, Op0IsKill);
     867           0 :   case MVT::v4i32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill);
     868           0 :   case MVT::v2i64: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v2i64_r(Op0, Op0IsKill);
     869           0 :   case MVT::v4f32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v4f32_r(Op0, Op0IsKill);
     870           0 :   case MVT::v2f64: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v2f64_r(Op0, Op0IsKill);
     871           0 :   case MVT::ExceptRef: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_ExceptRef_r(Op0, Op0IsKill);
     872             :   default: return 0;
     873             : }
     874             : }
     875             : 
     876             : unsigned fastEmit_WebAssemblyISD_CALL1_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     877           0 :   switch (VT.SimpleTy) {
     878           0 :   case MVT::i32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_r(RetVT, Op0, Op0IsKill);
     879             :   default: return 0;
     880             :   }
     881             : }
     882             : 
     883             : // FastEmit functions for WebAssemblyISD::RETURN.
     884             : 
     885             : unsigned fastEmit_WebAssemblyISD_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     886           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     887             :     return 0;
     888           0 :   return fastEmitInst_r(WebAssembly::RETURN_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill);
     889             : }
     890             : 
     891             : unsigned fastEmit_WebAssemblyISD_RETURN_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     892           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     893             :     return 0;
     894           0 :   return fastEmitInst_r(WebAssembly::RETURN_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill);
     895             : }
     896             : 
     897             : unsigned fastEmit_WebAssemblyISD_RETURN_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     898           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     899             :     return 0;
     900           0 :   return fastEmitInst_r(WebAssembly::RETURN_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill);
     901             : }
     902             : 
     903             : unsigned fastEmit_WebAssemblyISD_RETURN_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     904           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     905             :     return 0;
     906           0 :   return fastEmitInst_r(WebAssembly::RETURN_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill);
     907             : }
     908             : 
     909             : unsigned fastEmit_WebAssemblyISD_RETURN_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     910           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     911             :     return 0;
     912           0 :   if ((Subtarget->hasSIMD128())) {
     913           0 :     return fastEmitInst_r(WebAssembly::RETURN_v16i8, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     914             :   }
     915             :   return 0;
     916             : }
     917             : 
     918             : unsigned fastEmit_WebAssemblyISD_RETURN_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     919           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     920             :     return 0;
     921           0 :   if ((Subtarget->hasSIMD128())) {
     922           0 :     return fastEmitInst_r(WebAssembly::RETURN_v8i16, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     923             :   }
     924             :   return 0;
     925             : }
     926             : 
     927             : unsigned fastEmit_WebAssemblyISD_RETURN_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     928           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     929             :     return 0;
     930           0 :   if ((Subtarget->hasSIMD128())) {
     931           0 :     return fastEmitInst_r(WebAssembly::RETURN_v4i32, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     932             :   }
     933             :   return 0;
     934             : }
     935             : 
     936             : unsigned fastEmit_WebAssemblyISD_RETURN_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     937           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     938             :     return 0;
     939           0 :   if ((Subtarget->hasSIMD128())) {
     940           0 :     return fastEmitInst_r(WebAssembly::RETURN_v2i64, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     941             :   }
     942             :   return 0;
     943             : }
     944             : 
     945             : unsigned fastEmit_WebAssemblyISD_RETURN_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     946           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     947             :     return 0;
     948           0 :   if ((Subtarget->hasSIMD128())) {
     949           0 :     return fastEmitInst_r(WebAssembly::RETURN_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     950             :   }
     951             :   return 0;
     952             : }
     953             : 
     954             : unsigned fastEmit_WebAssemblyISD_RETURN_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     955           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     956             :     return 0;
     957           0 :   if ((Subtarget->hasSIMD128())) {
     958           0 :     return fastEmitInst_r(WebAssembly::RETURN_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill);
     959             :   }
     960             :   return 0;
     961             : }
     962             : 
     963             : unsigned fastEmit_WebAssemblyISD_RETURN_MVT_ExceptRef_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
     964           0 :   if (RetVT.SimpleTy != MVT::isVoid)
     965             :     return 0;
     966           0 :   return fastEmitInst_r(WebAssembly::RETURN_EXCEPT_REF, &WebAssembly::EXCEPT_REFRegClass, Op0, Op0IsKill);
     967             : }
     968             : 
     969           0 : unsigned fastEmit_WebAssemblyISD_RETURN_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
     970           0 :   switch (VT.SimpleTy) {
     971           0 :   case MVT::i32: return fastEmit_WebAssemblyISD_RETURN_MVT_i32_r(RetVT, Op0, Op0IsKill);
     972           0 :   case MVT::i64: return fastEmit_WebAssemblyISD_RETURN_MVT_i64_r(RetVT, Op0, Op0IsKill);
     973           0 :   case MVT::f32: return fastEmit_WebAssemblyISD_RETURN_MVT_f32_r(RetVT, Op0, Op0IsKill);
     974           0 :   case MVT::f64: return fastEmit_WebAssemblyISD_RETURN_MVT_f64_r(RetVT, Op0, Op0IsKill);
     975           0 :   case MVT::v16i8: return fastEmit_WebAssemblyISD_RETURN_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
     976           0 :   case MVT::v8i16: return fastEmit_WebAssemblyISD_RETURN_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
     977           0 :   case MVT::v4i32: return fastEmit_WebAssemblyISD_RETURN_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
     978           0 :   case MVT::v2i64: return fastEmit_WebAssemblyISD_RETURN_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
     979           0 :   case MVT::v4f32: return fastEmit_WebAssemblyISD_RETURN_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
     980           0 :   case MVT::v2f64: return fastEmit_WebAssemblyISD_RETURN_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
     981           0 :   case MVT::ExceptRef: return fastEmit_WebAssemblyISD_RETURN_MVT_ExceptRef_r(RetVT, Op0, Op0IsKill);
     982             :   default: return 0;
     983             :   }
     984             : }
     985             : 
     986             : // Top-level FastEmit function.
     987             : 
     988           5 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
     989           5 :   switch (Opcode) {
     990           0 :   case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
     991           0 :   case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
     992           0 :   case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
     993           0 :   case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
     994           0 :   case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0, Op0IsKill);
     995           0 :   case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
     996           0 :   case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
     997           0 :   case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
     998           0 :   case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
     999           5 :   case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
    1000           0 :   case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1001           0 :   case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
    1002           0 :   case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
    1003           0 :   case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
    1004           0 :   case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
    1005           0 :   case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
    1006           0 :   case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
    1007           0 :   case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1008           0 :   case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1009           0 :   case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill);
    1010           0 :   case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
    1011           0 :   case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
    1012           0 :   case WebAssemblyISD::BR_TABLE: return fastEmit_WebAssemblyISD_BR_TABLE_r(VT, RetVT, Op0, Op0IsKill);
    1013           0 :   case WebAssemblyISD::CALL0: return fastEmit_WebAssemblyISD_CALL0_r(VT, RetVT, Op0, Op0IsKill);
    1014           0 :   case WebAssemblyISD::CALL1: return fastEmit_WebAssemblyISD_CALL1_r(VT, RetVT, Op0, Op0IsKill);
    1015           0 :   case WebAssemblyISD::RETURN: return fastEmit_WebAssemblyISD_RETURN_r(VT, RetVT, Op0, Op0IsKill);
    1016             :   default: return 0;
    1017             :   }
    1018             : }
    1019             : 
    1020             : // FastEmit functions for ISD::ADD.
    1021             : 
    1022             : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1023          10 :   if (RetVT.SimpleTy != MVT::i32)
    1024             :     return 0;
    1025          10 :   return fastEmitInst_rr(WebAssembly::ADD_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1026             : }
    1027             : 
    1028             : unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1029           0 :   if (RetVT.SimpleTy != MVT::i64)
    1030             :     return 0;
    1031           0 :   return fastEmitInst_rr(WebAssembly::ADD_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1032             : }
    1033             : 
    1034             : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1035           3 :   if (RetVT.SimpleTy != MVT::v16i8)
    1036             :     return 0;
    1037           3 :   if ((Subtarget->hasSIMD128())) {
    1038           3 :     return fastEmitInst_rr(WebAssembly::ADD_v16i8, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1039             :   }
    1040             :   return 0;
    1041             : }
    1042             : 
    1043             : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1044           3 :   if (RetVT.SimpleTy != MVT::v8i16)
    1045             :     return 0;
    1046           3 :   if ((Subtarget->hasSIMD128())) {
    1047           3 :     return fastEmitInst_rr(WebAssembly::ADD_v8i16, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1048             :   }
    1049             :   return 0;
    1050             : }
    1051             : 
    1052             : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1053           3 :   if (RetVT.SimpleTy != MVT::v4i32)
    1054             :     return 0;
    1055           3 :   if ((Subtarget->hasSIMD128())) {
    1056           3 :     return fastEmitInst_rr(WebAssembly::ADD_v4i32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1057             :   }
    1058             :   return 0;
    1059             : }
    1060             : 
    1061             : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1062           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    1063             :     return 0;
    1064           2 :   if ((Subtarget->hasSIMD128())) {
    1065           2 :     return fastEmitInst_rr(WebAssembly::ADD_v2i64, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1066             :   }
    1067             :   return 0;
    1068             : }
    1069             : 
    1070          21 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1071          21 :   switch (VT.SimpleTy) {
    1072          10 :   case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1073           0 :   case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1074           3 :   case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1075           3 :   case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1076           3 :   case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1077           2 :   case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1078             :   default: return 0;
    1079             :   }
    1080             : }
    1081             : 
    1082             : // FastEmit functions for ISD::AND.
    1083             : 
    1084             : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1085           0 :   if (RetVT.SimpleTy != MVT::i32)
    1086             :     return 0;
    1087           0 :   return fastEmitInst_rr(WebAssembly::AND_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1088             : }
    1089             : 
    1090             : unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1091           0 :   if (RetVT.SimpleTy != MVT::i64)
    1092             :     return 0;
    1093           0 :   return fastEmitInst_rr(WebAssembly::AND_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1094             : }
    1095             : 
    1096             : unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1097           6 :   if (RetVT.SimpleTy != MVT::v16i8)
    1098             :     return 0;
    1099           6 :   if ((Subtarget->hasSIMD128())) {
    1100           6 :     return fastEmitInst_rr(WebAssembly::AND_v16i8, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1101             :   }
    1102             :   return 0;
    1103             : }
    1104             : 
    1105             : unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1106           6 :   if (RetVT.SimpleTy != MVT::v8i16)
    1107             :     return 0;
    1108           6 :   if ((Subtarget->hasSIMD128())) {
    1109           6 :     return fastEmitInst_rr(WebAssembly::AND_v8i16, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1110             :   }
    1111             :   return 0;
    1112             : }
    1113             : 
    1114             : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1115           6 :   if (RetVT.SimpleTy != MVT::v4i32)
    1116             :     return 0;
    1117           6 :   if ((Subtarget->hasSIMD128())) {
    1118           6 :     return fastEmitInst_rr(WebAssembly::AND_v4i32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1119             :   }
    1120             :   return 0;
    1121             : }
    1122             : 
    1123             : unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1124           4 :   if (RetVT.SimpleTy != MVT::v2i64)
    1125             :     return 0;
    1126           4 :   if ((Subtarget->hasSIMD128())) {
    1127           4 :     return fastEmitInst_rr(WebAssembly::AND_v2i64, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1128             :   }
    1129             :   return 0;
    1130             : }
    1131             : 
    1132          22 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1133          22 :   switch (VT.SimpleTy) {
    1134           0 :   case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1135           0 :   case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1136           6 :   case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1137           6 :   case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1138           6 :   case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1139           4 :   case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1140             :   default: return 0;
    1141             :   }
    1142             : }
    1143             : 
    1144             : // FastEmit functions for ISD::FADD.
    1145             : 
    1146             : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1147           0 :   if (RetVT.SimpleTy != MVT::f32)
    1148             :     return 0;
    1149           0 :   return fastEmitInst_rr(WebAssembly::ADD_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1150             : }
    1151             : 
    1152             : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1153           0 :   if (RetVT.SimpleTy != MVT::f64)
    1154             :     return 0;
    1155           0 :   return fastEmitInst_rr(WebAssembly::ADD_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1156             : }
    1157             : 
    1158             : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1159           3 :   if (RetVT.SimpleTy != MVT::v4f32)
    1160             :     return 0;
    1161           3 :   if ((Subtarget->hasSIMD128())) {
    1162           3 :     return fastEmitInst_rr(WebAssembly::ADD_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1163             :   }
    1164             :   return 0;
    1165             : }
    1166             : 
    1167             : unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1168           2 :   if (RetVT.SimpleTy != MVT::v2f64)
    1169             :     return 0;
    1170           2 :   if ((Subtarget->hasSIMD128())) {
    1171           2 :     return fastEmitInst_rr(WebAssembly::ADD_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1172             :   }
    1173             :   return 0;
    1174             : }
    1175             : 
    1176           5 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1177           5 :   switch (VT.SimpleTy) {
    1178           0 :   case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1179           0 :   case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1180           3 :   case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1181           2 :   case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1182             :   default: return 0;
    1183             :   }
    1184             : }
    1185             : 
    1186             : // FastEmit functions for ISD::FCOPYSIGN.
    1187             : 
    1188             : unsigned fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1189           0 :   if (RetVT.SimpleTy != MVT::f32)
    1190             :     return 0;
    1191           0 :   return fastEmitInst_rr(WebAssembly::COPYSIGN_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1192             : }
    1193             : 
    1194             : unsigned fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1195           0 :   if (RetVT.SimpleTy != MVT::f64)
    1196             :     return 0;
    1197           0 :   return fastEmitInst_rr(WebAssembly::COPYSIGN_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1198             : }
    1199             : 
    1200           0 : unsigned fastEmit_ISD_FCOPYSIGN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1201           0 :   switch (VT.SimpleTy) {
    1202           0 :   case MVT::f32: return fastEmit_ISD_FCOPYSIGN_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1203           0 :   case MVT::f64: return fastEmit_ISD_FCOPYSIGN_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1204             :   default: return 0;
    1205             :   }
    1206             : }
    1207             : 
    1208             : // FastEmit functions for ISD::FDIV.
    1209             : 
    1210             : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1211           0 :   if (RetVT.SimpleTy != MVT::f32)
    1212             :     return 0;
    1213           0 :   return fastEmitInst_rr(WebAssembly::DIV_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1214             : }
    1215             : 
    1216             : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1217           0 :   if (RetVT.SimpleTy != MVT::f64)
    1218             :     return 0;
    1219           0 :   return fastEmitInst_rr(WebAssembly::DIV_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1220             : }
    1221             : 
    1222             : unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1223           3 :   if (RetVT.SimpleTy != MVT::v4f32)
    1224             :     return 0;
    1225           3 :   if ((Subtarget->hasSIMD128())) {
    1226           3 :     return fastEmitInst_rr(WebAssembly::DIV_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1227             :   }
    1228             :   return 0;
    1229             : }
    1230             : 
    1231             : unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1232           2 :   if (RetVT.SimpleTy != MVT::v2f64)
    1233             :     return 0;
    1234           2 :   if ((Subtarget->hasSIMD128())) {
    1235           2 :     return fastEmitInst_rr(WebAssembly::DIV_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1236             :   }
    1237             :   return 0;
    1238             : }
    1239             : 
    1240           5 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1241           5 :   switch (VT.SimpleTy) {
    1242           0 :   case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1243           0 :   case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1244           3 :   case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1245           2 :   case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1246             :   default: return 0;
    1247             :   }
    1248             : }
    1249             : 
    1250             : // FastEmit functions for ISD::FMAXNAN.
    1251             : 
    1252             : unsigned fastEmit_ISD_FMAXNAN_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1253           0 :   if (RetVT.SimpleTy != MVT::f32)
    1254             :     return 0;
    1255           0 :   return fastEmitInst_rr(WebAssembly::MAX_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1256             : }
    1257             : 
    1258             : unsigned fastEmit_ISD_FMAXNAN_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1259           0 :   if (RetVT.SimpleTy != MVT::f64)
    1260             :     return 0;
    1261           0 :   return fastEmitInst_rr(WebAssembly::MAX_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1262             : }
    1263             : 
    1264             : unsigned fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1265           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1266             :     return 0;
    1267           0 :   if ((Subtarget->hasSIMD128())) {
    1268           0 :     return fastEmitInst_rr(WebAssembly::MAX_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1269             :   }
    1270             :   return 0;
    1271             : }
    1272             : 
    1273             : unsigned fastEmit_ISD_FMAXNAN_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1274           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1275             :     return 0;
    1276           0 :   if ((Subtarget->hasSIMD128())) {
    1277           0 :     return fastEmitInst_rr(WebAssembly::MAX_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1278             :   }
    1279             :   return 0;
    1280             : }
    1281             : 
    1282           0 : unsigned fastEmit_ISD_FMAXNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1283           0 :   switch (VT.SimpleTy) {
    1284           0 :   case MVT::f32: return fastEmit_ISD_FMAXNAN_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1285           0 :   case MVT::f64: return fastEmit_ISD_FMAXNAN_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1286           0 :   case MVT::v4f32: return fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1287           0 :   case MVT::v2f64: return fastEmit_ISD_FMAXNAN_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1288             :   default: return 0;
    1289             :   }
    1290             : }
    1291             : 
    1292             : // FastEmit functions for ISD::FMINNAN.
    1293             : 
    1294             : unsigned fastEmit_ISD_FMINNAN_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1295           0 :   if (RetVT.SimpleTy != MVT::f32)
    1296             :     return 0;
    1297           0 :   return fastEmitInst_rr(WebAssembly::MIN_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1298             : }
    1299             : 
    1300             : unsigned fastEmit_ISD_FMINNAN_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1301           0 :   if (RetVT.SimpleTy != MVT::f64)
    1302             :     return 0;
    1303           0 :   return fastEmitInst_rr(WebAssembly::MIN_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1304             : }
    1305             : 
    1306             : unsigned fastEmit_ISD_FMINNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1307           0 :   if (RetVT.SimpleTy != MVT::v4f32)
    1308             :     return 0;
    1309           0 :   if ((Subtarget->hasSIMD128())) {
    1310           0 :     return fastEmitInst_rr(WebAssembly::MIN_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1311             :   }
    1312             :   return 0;
    1313             : }
    1314             : 
    1315             : unsigned fastEmit_ISD_FMINNAN_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1316           0 :   if (RetVT.SimpleTy != MVT::v2f64)
    1317             :     return 0;
    1318           0 :   if ((Subtarget->hasSIMD128())) {
    1319           0 :     return fastEmitInst_rr(WebAssembly::MIN_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1320             :   }
    1321             :   return 0;
    1322             : }
    1323             : 
    1324           0 : unsigned fastEmit_ISD_FMINNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1325           0 :   switch (VT.SimpleTy) {
    1326           0 :   case MVT::f32: return fastEmit_ISD_FMINNAN_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1327           0 :   case MVT::f64: return fastEmit_ISD_FMINNAN_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1328           0 :   case MVT::v4f32: return fastEmit_ISD_FMINNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1329           0 :   case MVT::v2f64: return fastEmit_ISD_FMINNAN_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1330             :   default: return 0;
    1331             :   }
    1332             : }
    1333             : 
    1334             : // FastEmit functions for ISD::FMUL.
    1335             : 
    1336             : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1337           0 :   if (RetVT.SimpleTy != MVT::f32)
    1338             :     return 0;
    1339           0 :   return fastEmitInst_rr(WebAssembly::MUL_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1340             : }
    1341             : 
    1342             : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1343           0 :   if (RetVT.SimpleTy != MVT::f64)
    1344             :     return 0;
    1345           0 :   return fastEmitInst_rr(WebAssembly::MUL_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1346             : }
    1347             : 
    1348             : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1349           3 :   if (RetVT.SimpleTy != MVT::v4f32)
    1350             :     return 0;
    1351           3 :   if ((Subtarget->hasSIMD128())) {
    1352           3 :     return fastEmitInst_rr(WebAssembly::MUL_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1353             :   }
    1354             :   return 0;
    1355             : }
    1356             : 
    1357             : unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1358           2 :   if (RetVT.SimpleTy != MVT::v2f64)
    1359             :     return 0;
    1360           2 :   if ((Subtarget->hasSIMD128())) {
    1361           2 :     return fastEmitInst_rr(WebAssembly::MUL_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1362             :   }
    1363             :   return 0;
    1364             : }
    1365             : 
    1366           5 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1367           5 :   switch (VT.SimpleTy) {
    1368           0 :   case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1369           0 :   case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1370           3 :   case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1371           2 :   case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1372             :   default: return 0;
    1373             :   }
    1374             : }
    1375             : 
    1376             : // FastEmit functions for ISD::FSUB.
    1377             : 
    1378             : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1379           0 :   if (RetVT.SimpleTy != MVT::f32)
    1380             :     return 0;
    1381           0 :   return fastEmitInst_rr(WebAssembly::SUB_F32, &WebAssembly::F32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1382             : }
    1383             : 
    1384             : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1385           0 :   if (RetVT.SimpleTy != MVT::f64)
    1386             :     return 0;
    1387           0 :   return fastEmitInst_rr(WebAssembly::SUB_F64, &WebAssembly::F64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1388             : }
    1389             : 
    1390             : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1391           3 :   if (RetVT.SimpleTy != MVT::v4f32)
    1392             :     return 0;
    1393           3 :   if ((Subtarget->hasSIMD128())) {
    1394           3 :     return fastEmitInst_rr(WebAssembly::SUB_v4f32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1395             :   }
    1396             :   return 0;
    1397             : }
    1398             : 
    1399             : unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1400           2 :   if (RetVT.SimpleTy != MVT::v2f64)
    1401             :     return 0;
    1402           2 :   if ((Subtarget->hasSIMD128())) {
    1403           2 :     return fastEmitInst_rr(WebAssembly::SUB_v2f64, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1404             :   }
    1405             :   return 0;
    1406             : }
    1407             : 
    1408           5 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1409           5 :   switch (VT.SimpleTy) {
    1410           0 :   case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1411           0 :   case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1412           3 :   case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1413           2 :   case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1414             :   default: return 0;
    1415             :   }
    1416             : }
    1417             : 
    1418             : // FastEmit functions for ISD::MUL.
    1419             : 
    1420             : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1421           0 :   if (RetVT.SimpleTy != MVT::i32)
    1422             :     return 0;
    1423           0 :   return fastEmitInst_rr(WebAssembly::MUL_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1424             : }
    1425             : 
    1426             : unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1427           0 :   if (RetVT.SimpleTy != MVT::i64)
    1428             :     return 0;
    1429           0 :   return fastEmitInst_rr(WebAssembly::MUL_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1430             : }
    1431             : 
    1432             : unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1433           3 :   if (RetVT.SimpleTy != MVT::v16i8)
    1434             :     return 0;
    1435           3 :   if ((Subtarget->hasSIMD128())) {
    1436           3 :     return fastEmitInst_rr(WebAssembly::MUL_v16i8, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1437             :   }
    1438             :   return 0;
    1439             : }
    1440             : 
    1441             : unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1442           3 :   if (RetVT.SimpleTy != MVT::v8i16)
    1443             :     return 0;
    1444           3 :   if ((Subtarget->hasSIMD128())) {
    1445           3 :     return fastEmitInst_rr(WebAssembly::MUL_v8i16, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1446             :   }
    1447             :   return 0;
    1448             : }
    1449             : 
    1450             : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1451           3 :   if (RetVT.SimpleTy != MVT::v4i32)
    1452             :     return 0;
    1453           3 :   if ((Subtarget->hasSIMD128())) {
    1454           3 :     return fastEmitInst_rr(WebAssembly::MUL_v4i32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1455             :   }
    1456             :   return 0;
    1457             : }
    1458             : 
    1459          11 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1460          11 :   switch (VT.SimpleTy) {
    1461           0 :   case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1462           0 :   case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1463           3 :   case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1464           3 :   case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1465           3 :   case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1466             :   default: return 0;
    1467             :   }
    1468             : }
    1469             : 
    1470             : // FastEmit functions for ISD::OR.
    1471             : 
    1472             : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1473           0 :   if (RetVT.SimpleTy != MVT::i32)
    1474             :     return 0;
    1475           0 :   return fastEmitInst_rr(WebAssembly::OR_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1476             : }
    1477             : 
    1478             : unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1479           0 :   if (RetVT.SimpleTy != MVT::i64)
    1480             :     return 0;
    1481           0 :   return fastEmitInst_rr(WebAssembly::OR_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1482             : }
    1483             : 
    1484             : unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1485           6 :   if (RetVT.SimpleTy != MVT::v16i8)
    1486             :     return 0;
    1487           6 :   if ((Subtarget->hasSIMD128())) {
    1488           6 :     return fastEmitInst_rr(WebAssembly::OR_v16i8, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1489             :   }
    1490             :   return 0;
    1491             : }
    1492             : 
    1493             : unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1494           6 :   if (RetVT.SimpleTy != MVT::v8i16)
    1495             :     return 0;
    1496           6 :   if ((Subtarget->hasSIMD128())) {
    1497           6 :     return fastEmitInst_rr(WebAssembly::OR_v8i16, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1498             :   }
    1499             :   return 0;
    1500             : }
    1501             : 
    1502             : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1503           6 :   if (RetVT.SimpleTy != MVT::v4i32)
    1504             :     return 0;
    1505           6 :   if ((Subtarget->hasSIMD128())) {
    1506           6 :     return fastEmitInst_rr(WebAssembly::OR_v4i32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1507             :   }
    1508             :   return 0;
    1509             : }
    1510             : 
    1511             : unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1512           4 :   if (RetVT.SimpleTy != MVT::v2i64)
    1513             :     return 0;
    1514           4 :   if ((Subtarget->hasSIMD128())) {
    1515           4 :     return fastEmitInst_rr(WebAssembly::OR_v2i64, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1516             :   }
    1517             :   return 0;
    1518             : }
    1519             : 
    1520          22 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1521          22 :   switch (VT.SimpleTy) {
    1522           0 :   case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1523           0 :   case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1524           6 :   case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1525           6 :   case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1526           6 :   case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1527           4 :   case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1528             :   default: return 0;
    1529             :   }
    1530             : }
    1531             : 
    1532             : // FastEmit functions for ISD::ROTL.
    1533             : 
    1534             : unsigned fastEmit_ISD_ROTL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1535           0 :   if (RetVT.SimpleTy != MVT::i32)
    1536             :     return 0;
    1537           0 :   return fastEmitInst_rr(WebAssembly::ROTL_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1538             : }
    1539             : 
    1540             : unsigned fastEmit_ISD_ROTL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1541           0 :   if (RetVT.SimpleTy != MVT::i64)
    1542             :     return 0;
    1543           0 :   return fastEmitInst_rr(WebAssembly::ROTL_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1544             : }
    1545             : 
    1546           0 : unsigned fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1547           0 :   switch (VT.SimpleTy) {
    1548           0 :   case MVT::i32: return fastEmit_ISD_ROTL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1549           0 :   case MVT::i64: return fastEmit_ISD_ROTL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1550             :   default: return 0;
    1551             :   }
    1552             : }
    1553             : 
    1554             : // FastEmit functions for ISD::ROTR.
    1555             : 
    1556             : unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1557           0 :   if (RetVT.SimpleTy != MVT::i32)
    1558             :     return 0;
    1559           0 :   return fastEmitInst_rr(WebAssembly::ROTR_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1560             : }
    1561             : 
    1562             : unsigned fastEmit_ISD_ROTR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1563           0 :   if (RetVT.SimpleTy != MVT::i64)
    1564             :     return 0;
    1565           0 :   return fastEmitInst_rr(WebAssembly::ROTR_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1566             : }
    1567             : 
    1568           0 : unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1569           0 :   switch (VT.SimpleTy) {
    1570           0 :   case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1571           0 :   case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1572             :   default: return 0;
    1573             :   }
    1574             : }
    1575             : 
    1576             : // FastEmit functions for ISD::SDIV.
    1577             : 
    1578             : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1579           0 :   if (RetVT.SimpleTy != MVT::i32)
    1580             :     return 0;
    1581           0 :   return fastEmitInst_rr(WebAssembly::DIV_S_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1582             : }
    1583             : 
    1584             : unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1585           0 :   if (RetVT.SimpleTy != MVT::i64)
    1586             :     return 0;
    1587           0 :   return fastEmitInst_rr(WebAssembly::DIV_S_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1588             : }
    1589             : 
    1590           0 : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1591           0 :   switch (VT.SimpleTy) {
    1592           0 :   case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1593           0 :   case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1594             :   default: return 0;
    1595             :   }
    1596             : }
    1597             : 
    1598             : // FastEmit functions for ISD::SHL.
    1599             : 
    1600             : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1601           0 :   if (RetVT.SimpleTy != MVT::i32)
    1602             :     return 0;
    1603           0 :   return fastEmitInst_rr(WebAssembly::SHL_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1604             : }
    1605             : 
    1606             : unsigned fastEmit_ISD_SHL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1607           0 :   if (RetVT.SimpleTy != MVT::i64)
    1608             :     return 0;
    1609           0 :   return fastEmitInst_rr(WebAssembly::SHL_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1610             : }
    1611             : 
    1612          13 : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1613          13 :   switch (VT.SimpleTy) {
    1614           0 :   case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1615           0 :   case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1616             :   default: return 0;
    1617             :   }
    1618             : }
    1619             : 
    1620             : // FastEmit functions for ISD::SRA.
    1621             : 
    1622             : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1623           0 :   if (RetVT.SimpleTy != MVT::i32)
    1624             :     return 0;
    1625           0 :   return fastEmitInst_rr(WebAssembly::SHR_S_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1626             : }
    1627             : 
    1628             : unsigned fastEmit_ISD_SRA_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1629           0 :   if (RetVT.SimpleTy != MVT::i64)
    1630             :     return 0;
    1631           0 :   return fastEmitInst_rr(WebAssembly::SHR_S_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1632             : }
    1633             : 
    1634          13 : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1635          13 :   switch (VT.SimpleTy) {
    1636           0 :   case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1637           0 :   case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1638             :   default: return 0;
    1639             :   }
    1640             : }
    1641             : 
    1642             : // FastEmit functions for ISD::SREM.
    1643             : 
    1644             : unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1645           0 :   if (RetVT.SimpleTy != MVT::i32)
    1646             :     return 0;
    1647           0 :   return fastEmitInst_rr(WebAssembly::REM_S_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1648             : }
    1649             : 
    1650             : unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1651           0 :   if (RetVT.SimpleTy != MVT::i64)
    1652             :     return 0;
    1653           0 :   return fastEmitInst_rr(WebAssembly::REM_S_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1654             : }
    1655             : 
    1656           0 : unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1657           0 :   switch (VT.SimpleTy) {
    1658           0 :   case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1659           0 :   case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1660             :   default: return 0;
    1661             :   }
    1662             : }
    1663             : 
    1664             : // FastEmit functions for ISD::SRL.
    1665             : 
    1666             : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1667           0 :   if (RetVT.SimpleTy != MVT::i32)
    1668             :     return 0;
    1669           0 :   return fastEmitInst_rr(WebAssembly::SHR_U_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1670             : }
    1671             : 
    1672             : unsigned fastEmit_ISD_SRL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1673           0 :   if (RetVT.SimpleTy != MVT::i64)
    1674             :     return 0;
    1675           0 :   return fastEmitInst_rr(WebAssembly::SHR_U_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1676             : }
    1677             : 
    1678          13 : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1679          13 :   switch (VT.SimpleTy) {
    1680           0 :   case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1681           0 :   case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1682             :   default: return 0;
    1683             :   }
    1684             : }
    1685             : 
    1686             : // FastEmit functions for ISD::SUB.
    1687             : 
    1688             : unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1689           1 :   if (RetVT.SimpleTy != MVT::i32)
    1690             :     return 0;
    1691           1 :   return fastEmitInst_rr(WebAssembly::SUB_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1692             : }
    1693             : 
    1694             : unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1695           0 :   if (RetVT.SimpleTy != MVT::i64)
    1696             :     return 0;
    1697           0 :   return fastEmitInst_rr(WebAssembly::SUB_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1698             : }
    1699             : 
    1700             : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1701           3 :   if (RetVT.SimpleTy != MVT::v16i8)
    1702             :     return 0;
    1703           3 :   if ((Subtarget->hasSIMD128())) {
    1704           3 :     return fastEmitInst_rr(WebAssembly::SUB_v16i8, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1705             :   }
    1706             :   return 0;
    1707             : }
    1708             : 
    1709             : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1710           3 :   if (RetVT.SimpleTy != MVT::v8i16)
    1711             :     return 0;
    1712           3 :   if ((Subtarget->hasSIMD128())) {
    1713           3 :     return fastEmitInst_rr(WebAssembly::SUB_v8i16, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1714             :   }
    1715             :   return 0;
    1716             : }
    1717             : 
    1718             : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1719           3 :   if (RetVT.SimpleTy != MVT::v4i32)
    1720             :     return 0;
    1721           3 :   if ((Subtarget->hasSIMD128())) {
    1722           3 :     return fastEmitInst_rr(WebAssembly::SUB_v4i32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1723             :   }
    1724             :   return 0;
    1725             : }
    1726             : 
    1727             : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1728           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    1729             :     return 0;
    1730           2 :   if ((Subtarget->hasSIMD128())) {
    1731           2 :     return fastEmitInst_rr(WebAssembly::SUB_v2i64, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1732             :   }
    1733             :   return 0;
    1734             : }
    1735             : 
    1736          12 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1737          12 :   switch (VT.SimpleTy) {
    1738           1 :   case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1739           0 :   case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1740           3 :   case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1741           3 :   case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1742           3 :   case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1743           2 :   case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1744             :   default: return 0;
    1745             :   }
    1746             : }
    1747             : 
    1748             : // FastEmit functions for ISD::UDIV.
    1749             : 
    1750             : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1751           0 :   if (RetVT.SimpleTy != MVT::i32)
    1752             :     return 0;
    1753           0 :   return fastEmitInst_rr(WebAssembly::DIV_U_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1754             : }
    1755             : 
    1756             : unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1757           0 :   if (RetVT.SimpleTy != MVT::i64)
    1758             :     return 0;
    1759           0 :   return fastEmitInst_rr(WebAssembly::DIV_U_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1760             : }
    1761             : 
    1762           0 : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1763           0 :   switch (VT.SimpleTy) {
    1764           0 :   case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1765           0 :   case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1766             :   default: return 0;
    1767             :   }
    1768             : }
    1769             : 
    1770             : // FastEmit functions for ISD::UREM.
    1771             : 
    1772             : unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1773           1 :   if (RetVT.SimpleTy != MVT::i32)
    1774             :     return 0;
    1775           1 :   return fastEmitInst_rr(WebAssembly::REM_U_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1776             : }
    1777             : 
    1778             : unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1779           0 :   if (RetVT.SimpleTy != MVT::i64)
    1780             :     return 0;
    1781           0 :   return fastEmitInst_rr(WebAssembly::REM_U_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1782             : }
    1783             : 
    1784           1 : unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1785           1 :   switch (VT.SimpleTy) {
    1786           1 :   case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1787           0 :   case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1788             :   default: return 0;
    1789             :   }
    1790             : }
    1791             : 
    1792             : // FastEmit functions for ISD::XOR.
    1793             : 
    1794             : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1795           3 :   if (RetVT.SimpleTy != MVT::i32)
    1796             :     return 0;
    1797           3 :   return fastEmitInst_rr(WebAssembly::XOR_I32, &WebAssembly::I32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1798             : }
    1799             : 
    1800             : unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1801           0 :   if (RetVT.SimpleTy != MVT::i64)
    1802             :     return 0;
    1803           0 :   return fastEmitInst_rr(WebAssembly::XOR_I64, &WebAssembly::I64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1804             : }
    1805             : 
    1806             : unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1807           3 :   if (RetVT.SimpleTy != MVT::v16i8)
    1808             :     return 0;
    1809           3 :   if ((Subtarget->hasSIMD128())) {
    1810           3 :     return fastEmitInst_rr(WebAssembly::XOR_v16i8, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1811             :   }
    1812             :   return 0;
    1813             : }
    1814             : 
    1815             : unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1816           3 :   if (RetVT.SimpleTy != MVT::v8i16)
    1817             :     return 0;
    1818           3 :   if ((Subtarget->hasSIMD128())) {
    1819           3 :     return fastEmitInst_rr(WebAssembly::XOR_v8i16, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1820             :   }
    1821             :   return 0;
    1822             : }
    1823             : 
    1824             : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1825           3 :   if (RetVT.SimpleTy != MVT::v4i32)
    1826             :     return 0;
    1827           3 :   if ((Subtarget->hasSIMD128())) {
    1828           3 :     return fastEmitInst_rr(WebAssembly::XOR_v4i32, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1829             :   }
    1830             :   return 0;
    1831             : }
    1832             : 
    1833             : unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1834           2 :   if (RetVT.SimpleTy != MVT::v2i64)
    1835             :     return 0;
    1836           2 :   if ((Subtarget->hasSIMD128())) {
    1837           2 :     return fastEmitInst_rr(WebAssembly::XOR_v2i64, &WebAssembly::V128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
    1838             :   }
    1839             :   return 0;
    1840             : }
    1841             : 
    1842          14 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
    1843          14 :   switch (VT.SimpleTy) {
    1844           3 :   case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1845           0 :   case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1846           3 :   case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1847           3 :   case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1848           3 :   case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1849           2 :   case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1850             :   default: return 0;
    1851             :   }
    1852             : }
    1853             : 
    1854             : // Top-level FastEmit function.
    1855             : 
    1856         162 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
    1857         162 :   switch (Opcode) {
    1858          21 :   case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1859          22 :   case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1860           5 :   case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1861           0 :   case ISD::FCOPYSIGN: return fastEmit_ISD_FCOPYSIGN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1862           5 :   case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1863           0 :   case ISD::FMAXNAN: return fastEmit_ISD_FMAXNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1864           0 :   case ISD::FMINNAN: return fastEmit_ISD_FMINNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1865           5 :   case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1866           5 :   case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1867          11 :   case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1868          22 :   case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1869           0 :   case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1870           0 :   case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1871           0 :   case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1872          13 :   case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1873          13 :   case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1874           0 :   case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1875          13 :   case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1876          12 :   case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1877           0 :   case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1878           1 :   case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1879          14 :   case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
    1880             :   default: return 0;
    1881             :   }
    1882             : }
    1883             : 
    1884             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    1885             : 
    1886             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1887             :   if (RetVT.SimpleTy != MVT::i32)
    1888             :     return 0;
    1889             :   if ((Subtarget->hasSIMD128())) {
    1890             :     return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_v4i32, &WebAssembly::I32RegClass, Op0, Op0IsKill, imm1);
    1891             :   }
    1892             :   return 0;
    1893             : }
    1894             : 
    1895             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1896             :   if (RetVT.SimpleTy != MVT::f32)
    1897             :     return 0;
    1898             :   if ((Subtarget->hasSIMD128())) {
    1899             :     return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_v4f32, &WebAssembly::F32RegClass, Op0, Op0IsKill, imm1);
    1900             :   }
    1901             :   return 0;
    1902             : }
    1903             : 
    1904             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1905             :   switch (VT.SimpleTy) {
    1906             :   case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_LaneIdx4(RetVT, Op0, Op0IsKill, imm1);
    1907             :   case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_LaneIdx4(RetVT, Op0, Op0IsKill, imm1);
    1908             :   default: return 0;
    1909             :   }
    1910             : }
    1911             : 
    1912             : // Top-level FastEmit function.
    1913             : 
    1914             : unsigned fastEmit_ri_Predicate_LaneIdx4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1915             :   switch (Opcode) {
    1916             :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx4(VT, RetVT, Op0, Op0IsKill, imm1);
    1917             :   default: return 0;
    1918             :   }
    1919             : }
    1920             : 
    1921             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    1922             : 
    1923             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1924             :   if (RetVT.SimpleTy != MVT::i64)
    1925             :     return 0;
    1926             :   if ((Subtarget->hasSIMD128())) {
    1927             :     return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_v2i64, &WebAssembly::I64RegClass, Op0, Op0IsKill, imm1);
    1928             :   }
    1929             :   return 0;
    1930             : }
    1931             : 
    1932             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1933             :   if (RetVT.SimpleTy != MVT::f64)
    1934             :     return 0;
    1935             :   if ((Subtarget->hasSIMD128())) {
    1936             :     return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_v2f64, &WebAssembly::F64RegClass, Op0, Op0IsKill, imm1);
    1937             :   }
    1938             :   return 0;
    1939             : }
    1940             : 
    1941             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1942             :   switch (VT.SimpleTy) {
    1943             :   case MVT::v2i64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i64_ri_Predicate_LaneIdx2(RetVT, Op0, Op0IsKill, imm1);
    1944             :   case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_LaneIdx2(RetVT, Op0, Op0IsKill, imm1);
    1945             :   default: return 0;
    1946             :   }
    1947             : }
    1948             : 
    1949             : // Top-level FastEmit function.
    1950             : 
    1951             : unsigned fastEmit_ri_Predicate_LaneIdx2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1952             :   switch (Opcode) {
    1953             :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx2(VT, RetVT, Op0, Op0IsKill, imm1);
    1954             :   default: return 0;
    1955             :   }
    1956             : }
    1957             : 
    1958             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    1959             : 
    1960             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1961             :   if (RetVT.SimpleTy != MVT::i32)
    1962             :     return 0;
    1963             :   return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_v16i8_u, &WebAssembly::I32RegClass, Op0, Op0IsKill, imm1);
    1964             : }
    1965             : 
    1966             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1967             :   switch (VT.SimpleTy) {
    1968             :   case MVT::v16i8: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v16i8_ri_Predicate_LaneIdx16(RetVT, Op0, Op0IsKill, imm1);
    1969             :   default: return 0;
    1970             :   }
    1971             : }
    1972             : 
    1973             : // Top-level FastEmit function.
    1974             : 
    1975             : unsigned fastEmit_ri_Predicate_LaneIdx16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1976             :   switch (Opcode) {
    1977             :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx16(VT, RetVT, Op0, Op0IsKill, imm1);
    1978             :   default: return 0;
    1979             :   }
    1980             : }
    1981             : 
    1982             : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
    1983             : 
    1984             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1985             :   if (RetVT.SimpleTy != MVT::i32)
    1986             :     return 0;
    1987             :   return fastEmitInst_ri(WebAssembly::EXTRACT_LANE_v8i16_u, &WebAssembly::I32RegClass, Op0, Op0IsKill, imm1);
    1988             : }
    1989             : 
    1990             : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    1991             :   switch (VT.SimpleTy) {
    1992             :   case MVT::v8i16: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v8i16_ri_Predicate_LaneIdx8(RetVT, Op0, Op0IsKill, imm1);
    1993             :   default: return 0;
    1994             :   }
    1995             : }
    1996             : 
    1997             : // Top-level FastEmit function.
    1998             : 
    1999             : unsigned fastEmit_ri_Predicate_LaneIdx8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
    2000             :   switch (Opcode) {
    2001             :   case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_LaneIdx8(VT, RetVT, Op0, Op0IsKill, imm1);
    2002             :   default: return 0;
    2003             :   }
    2004             : }
    2005             : 
    2006             : // FastEmit functions for ISD::ConstantFP.
    2007             : 
    2008             : unsigned fastEmit_ISD_ConstantFP_MVT_f32_f(MVT RetVT, const ConstantFP *f0) {
    2009           2 :   if (RetVT.SimpleTy != MVT::f32)
    2010             :     return 0;
    2011           2 :   return fastEmitInst_f(WebAssembly::CONST_F32, &WebAssembly::F32RegClass, f0);
    2012             : }
    2013             : 
    2014             : unsigned fastEmit_ISD_ConstantFP_MVT_f64_f(MVT RetVT, const ConstantFP *f0) {
    2015           2 :   if (RetVT.SimpleTy != MVT::f64)
    2016             :     return 0;
    2017           2 :   return fastEmitInst_f(WebAssembly::CONST_F64, &WebAssembly::F64RegClass, f0);
    2018             : }
    2019             : 
    2020           4 : unsigned fastEmit_ISD_ConstantFP_f(MVT VT, MVT RetVT, const ConstantFP *f0) {
    2021           4 :   switch (VT.SimpleTy) {
    2022           2 :   case MVT::f32: return fastEmit_ISD_ConstantFP_MVT_f32_f(RetVT, f0);
    2023           2 :   case MVT::f64: return fastEmit_ISD_ConstantFP_MVT_f64_f(RetVT, f0);
    2024             :   default: return 0;
    2025             :   }
    2026             : }
    2027             : 
    2028             : // Top-level FastEmit function.
    2029             : 
    2030           4 : unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *f0) override {
    2031           4 :   switch (Opcode) {
    2032           4 :   case ISD::ConstantFP: return fastEmit_ISD_ConstantFP_f(VT, RetVT, f0);
    2033             :   default: return 0;
    2034             :   }
    2035             : }
    2036             : 
    2037             : // FastEmit functions for ISD::Constant.
    2038             : 
    2039             : unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
    2040          38 :   if (RetVT.SimpleTy != MVT::i32)
    2041             :     return 0;
    2042          38 :   return fastEmitInst_i(WebAssembly::CONST_I32, &WebAssembly::I32RegClass, imm0);
    2043             : }
    2044             : 
    2045             : unsigned fastEmit_ISD_Constant_MVT_i64_i(MVT RetVT, uint64_t imm0) {
    2046           2 :   if (RetVT.SimpleTy != MVT::i64)
    2047             :     return 0;
    2048           2 :   return fastEmitInst_i(WebAssembly::CONST_I64, &WebAssembly::I64RegClass, imm0);
    2049             : }
    2050             : 
    2051          40 : unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
    2052          40 :   switch (VT.SimpleTy) {
    2053          38 :   case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
    2054           2 :   case MVT::i64: return fastEmit_ISD_Constant_MVT_i64_i(RetVT, imm0);
    2055             :   default: return 0;
    2056             :   }
    2057             : }
    2058             : 
    2059             : // FastEmit functions for WebAssemblyISD::CALL1.
    2060             : 
    2061             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_i32_i(uint64_t imm0) {
    2062           0 :   return fastEmitInst_i(WebAssembly::CALL_I32, &WebAssembly::I32RegClass, imm0);
    2063             : }
    2064             : 
    2065             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_i64_i(uint64_t imm0) {
    2066           0 :   return fastEmitInst_i(WebAssembly::CALL_I64, &WebAssembly::I64RegClass, imm0);
    2067             : }
    2068             : 
    2069             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_f32_i(uint64_t imm0) {
    2070           0 :   return fastEmitInst_i(WebAssembly::CALL_F32, &WebAssembly::F32RegClass, imm0);
    2071             : }
    2072             : 
    2073             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_f64_i(uint64_t imm0) {
    2074           0 :   return fastEmitInst_i(WebAssembly::CALL_F64, &WebAssembly::F64RegClass, imm0);
    2075             : }
    2076             : 
    2077             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v16i8_i(uint64_t imm0) {
    2078           0 :   if ((Subtarget->hasSIMD128())) {
    2079           0 :     return fastEmitInst_i(WebAssembly::CALL_v16i8, &WebAssembly::V128RegClass, imm0);
    2080             :   }
    2081             :   return 0;
    2082             : }
    2083             : 
    2084             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v8i16_i(uint64_t imm0) {
    2085           0 :   if ((Subtarget->hasSIMD128())) {
    2086           0 :     return fastEmitInst_i(WebAssembly::CALL_v8i16, &WebAssembly::V128RegClass, imm0);
    2087             :   }
    2088             :   return 0;
    2089             : }
    2090             : 
    2091             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v4i32_i(uint64_t imm0) {
    2092           0 :   if ((Subtarget->hasSIMD128())) {
    2093           0 :     return fastEmitInst_i(WebAssembly::CALL_v4i32, &WebAssembly::V128RegClass, imm0);
    2094             :   }
    2095             :   return 0;
    2096             : }
    2097             : 
    2098             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v2i64_i(uint64_t imm0) {
    2099           0 :   if ((Subtarget->hasSIMD128())) {
    2100           0 :     return fastEmitInst_i(WebAssembly::CALL_v2i64, &WebAssembly::V128RegClass, imm0);
    2101             :   }
    2102             :   return 0;
    2103             : }
    2104             : 
    2105             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v4f32_i(uint64_t imm0) {
    2106           0 :   if ((Subtarget->hasSIMD128())) {
    2107           0 :     return fastEmitInst_i(WebAssembly::CALL_v4f32, &WebAssembly::V128RegClass, imm0);
    2108             :   }
    2109             :   return 0;
    2110             : }
    2111             : 
    2112             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v2f64_i(uint64_t imm0) {
    2113           0 :   if ((Subtarget->hasSIMD128())) {
    2114           0 :     return fastEmitInst_i(WebAssembly::CALL_v2f64, &WebAssembly::V128RegClass, imm0);
    2115             :   }
    2116             :   return 0;
    2117             : }
    2118             : 
    2119             : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_ExceptRef_i(uint64_t imm0) {
    2120           0 :   return fastEmitInst_i(WebAssembly::CALL_EXCEPT_REF, &WebAssembly::EXCEPT_REFRegClass, imm0);
    2121             : }
    2122             : 
    2123           0 : unsigned fastEmit_WebAssemblyISD_CALL1_MVT_i32_i(MVT RetVT, uint64_t imm0) {
    2124           0 : switch (RetVT.SimpleTy) {
    2125           0 :   case MVT::i32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_i32_i(imm0);
    2126           0 :   case MVT::i64: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_i64_i(imm0);
    2127           0 :   case MVT::f32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_f32_i(imm0);
    2128           0 :   case MVT::f64: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_f64_i(imm0);
    2129             :   case MVT::v16i8: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v16i8_i(imm0);
    2130             :   case MVT::v8i16: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v8i16_i(imm0);
    2131             :   case MVT::v4i32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v4i32_i(imm0);
    2132             :   case MVT::v2i64: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v2i64_i(imm0);
    2133             :   case MVT::v4f32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v4f32_i(imm0);
    2134             :   case MVT::v2f64: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_v2f64_i(imm0);
    2135           0 :   case MVT::ExceptRef: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_MVT_ExceptRef_i(imm0);
    2136             :   default: return 0;
    2137             : }
    2138             : }
    2139             : 
    2140             : unsigned fastEmit_WebAssemblyISD_CALL1_i(MVT VT, MVT RetVT, uint64_t imm0) {
    2141           0 :   switch (VT.SimpleTy) {
    2142           0 :   case MVT::i32: return fastEmit_WebAssemblyISD_CALL1_MVT_i32_i(RetVT, imm0);
    2143             :   default: return 0;
    2144             :   }
    2145             : }
    2146             : 
    2147             : // Top-level FastEmit function.
    2148             : 
    2149          40 : unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
    2150          40 :   switch (Opcode) {
    2151          40 :   case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
    2152           0 :   case WebAssemblyISD::CALL1: return fastEmit_WebAssemblyISD_CALL1_i(VT, RetVT, imm0);
    2153             :   default: return 0;
    2154             :   }
    2155             : }
    2156             : 

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