LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/X86 - X86GenRegisterBank.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 5 5 100.0 %
Date: 2017-09-14 15:23:50 Functions: 1 1 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Register Bank Source Fragments                                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_REGBANK_DECLARATIONS
      10             : #undef GET_REGBANK_DECLARATIONS
      11             : namespace llvm {
      12             : namespace X86 {
      13             : enum {
      14             :   GPRRegBankID,
      15             :   VECRRegBankID,
      16             :   NumRegisterBanks,
      17             : };
      18             : } // end namespace X86
      19             : } // end namespace llvm
      20             : #endif // GET_REGBANK_DECLARATIONS
      21             : 
      22             : #ifdef GET_TARGET_REGBANK_CLASS
      23             : #undef GET_TARGET_REGBANK_CLASS
      24             : private:
      25             :   static RegisterBank *RegBanks[];
      26             : 
      27             : protected:
      28             :   X86GenRegisterBankInfo();
      29             : 
      30             : #endif // GET_TARGET_REGBANK_CLASS
      31             : 
      32             : #ifdef GET_TARGET_REGBANK_IMPL
      33             : #undef GET_TARGET_REGBANK_IMPL
      34             : namespace llvm {
      35             : namespace X86 {
      36             : const uint32_t GPRRegBankCoverageData[] = {
      37             :     // 0-31
      38             :     (1u << (X86::GR8RegClassID - 0)) |
      39             :     (1u << (X86::GR16RegClassID - 0)) |
      40             :     (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
      41             :     (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 0)) |
      42             :     (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 0)) |
      43             :     (1u << (X86::GR32RegClassID - 0)) |
      44             :     (1u << (X86::GR32_NOSPRegClassID - 0)) |
      45             :     (1u << (X86::GR32_NOAXRegClassID - 0)) |
      46             :     (1u << (X86::GR32_NOAX_and_GR32_NOSPRegClassID - 0)) |
      47             :     (1u << (X86::GR8_NOREXRegClassID - 0)) |
      48             :     (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
      49             :     (1u << (X86::GR8_ABCD_LRegClassID - 0)) |
      50             :     (1u << (X86::GR16_NOREXRegClassID - 0)) |
      51             :     (1u << (X86::GR16_ABCDRegClassID - 0)) |
      52             :     (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID - 0)) |
      53             :     (1u << (X86::GR32_NOREXRegClassID - 0)) |
      54             :     0,
      55             :     // 32-63
      56             :     (1u << (X86::GR64RegClassID - 32)) |
      57             :     (1u << (X86::GR64_with_sub_8bitRegClassID - 32)) |
      58             :     (1u << (X86::GR64_NOSPRegClassID - 32)) |
      59             :     (1u << (X86::GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSPRegClassID - 32)) |
      60             :     (1u << (X86::GR32_NOAX_and_GR32_NOREXRegClassID - 32)) |
      61             :     (1u << (X86::GR32_NOREX_NOSPRegClassID - 32)) |
      62             :     (1u << (X86::GR32_NOAX_and_GR32_NOREX_NOSPRegClassID - 32)) |
      63             :     (1u << (X86::GR32_ABCDRegClassID - 32)) |
      64             :     (1u << (X86::GR32_ABCD_and_GR32_NOAXRegClassID - 32)) |
      65             :     (1u << (X86::GR32_TCRegClassID - 32)) |
      66             :     (1u << (X86::GR32_NOAX_and_GR32_TCRegClassID - 32)) |
      67             :     (1u << (X86::GR32_ADRegClassID - 32)) |
      68             :     (1u << (X86::GR32_AD_and_GR32_NOAXRegClassID - 32)) |
      69             :     (1u << (X86::GR64_NOSP_and_GR64_TCRegClassID - 32)) |
      70             :     (1u << (X86::GR64_NOREX_NOSPRegClassID - 32)) |
      71             :     (1u << (X86::GR64_with_sub_32bit_in_GR32_NOAXRegClassID - 32)) |
      72             :     (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 32)) |
      73             :     (1u << (X86::GR64_NOREXRegClassID - 32)) |
      74             :     (1u << (X86::GR64_TCRegClassID - 32)) |
      75             :     (1u << (X86::GR64_TCW64RegClassID - 32)) |
      76             :     0,
      77             :     // 64-95
      78             :     (1u << (X86::GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAXRegClassID - 64)) |
      79             :     (1u << (X86::GR64_TCW64_and_GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAXRegClassID - 64)) |
      80             :     (1u << (X86::GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TCRegClassID - 64)) |
      81             :     (1u << (X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAXRegClassID - 64)) |
      82             :     (1u << (X86::GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXRegClassID - 64)) |
      83             :     (1u << (X86::GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAXRegClassID - 64)) |
      84             :     (1u << (X86::GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSPRegClassID - 64)) |
      85             :     (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAXRegClassID - 64)) |
      86             :     (1u << (X86::GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPRegClassID - 64)) |
      87             :     (1u << (X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID - 64)) |
      88             :     (1u << (X86::GR64_with_sub_32bit_in_GR32_TCRegClassID - 64)) |
      89             :     (1u << (X86::GR64_ADRegClassID - 64)) |
      90             :     (1u << (X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID - 64)) |
      91             :     (1u << (X86::GR64_ABCDRegClassID - 64)) |
      92             :     (1u << (X86::GR64_NOSP_and_GR64_TCW64RegClassID - 64)) |
      93             :     (1u << (X86::GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXRegClassID - 64)) |
      94             :     (1u << (X86::GR64_NOREX_and_GR64_TCRegClassID - 64)) |
      95             :     (1u << (X86::GR64_NOREX_and_GR64_TCW64RegClassID - 64)) |
      96             :     (1u << (X86::GR64_and_LOW32_ADDR_ACCESSRegClassID - 64)) |
      97             :     (1u << (X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID - 64)) |
      98             :     (1u << (X86::GR64_TC_and_GR64_TCW64RegClassID - 64)) |
      99             :     0,
     100             :     // 96-127
     101             :     0,
     102             : };
     103             : const uint32_t VECRRegBankCoverageData[] = {
     104             :     // 0-31
     105             :     (1u << (X86::FR32XRegClassID - 0)) |
     106             :     (1u << (X86::FR32RegClassID - 0)) |
     107             :     0,
     108             :     // 32-63
     109             :     (1u << (X86::FR64XRegClassID - 32)) |
     110             :     (1u << (X86::FR64RegClassID - 32)) |
     111             :     0,
     112             :     // 64-95
     113             :     (1u << (X86::VR128XRegClassID - 64)) |
     114             :     (1u << (X86::VR256XRegClassID - 64)) |
     115             :     (1u << (X86::FR128RegClassID - 64)) |
     116             :     (1u << (X86::VR128RegClassID - 64)) |
     117             :     (1u << (X86::VR256RegClassID - 64)) |
     118             :     (1u << (X86::VR128HRegClassID - 64)) |
     119             :     (1u << (X86::VR128LRegClassID - 64)) |
     120             :     0,
     121             :     // 96-127
     122             :     (1u << (X86::VR512RegClassID - 96)) |
     123             :     (1u << (X86::VR512_with_sub_xmm_in_FR128RegClassID - 96)) |
     124             :     (1u << (X86::VR512_with_sub_xmm_in_VR128HRegClassID - 96)) |
     125             :     (1u << (X86::VR256HRegClassID - 96)) |
     126             :     (1u << (X86::VR512_with_sub_xmm_in_VR128LRegClassID - 96)) |
     127             :     (1u << (X86::VR256LRegClassID - 96)) |
     128             :     0,
     129             : };
     130             : 
     131       72306 : RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 102);
     132       72306 : RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* Size */ 512, /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 102);
     133             : } // end namespace X86
     134             : 
     135             : RegisterBank *X86GenRegisterBankInfo::RegBanks[] = {
     136             :     &X86::GPRRegBank,
     137             :     &X86::VECRRegBank,
     138             : };
     139             : 
     140        8020 : X86GenRegisterBankInfo::X86GenRegisterBankInfo()
     141        8020 :     : RegisterBankInfo(RegBanks, X86::NumRegisterBanks) {
     142             :   // Assert that RegBank indices match their ID's
     143             : #ifndef NDEBUG
     144             :   unsigned Index = 0;
     145             :   for (const auto &RB : RegBanks)
     146             :     assert(Index++ == RB->getID() && "Index != ID");
     147             : #endif // NDEBUG
     148        8020 : }
     149             : } // end namespace llvm
     150             : #endif // GET_TARGET_REGBANK_IMPL

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