Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Register Bank Source Fragments *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 : #ifdef GET_REGBANK_DECLARATIONS
10 : #undef GET_REGBANK_DECLARATIONS
11 : namespace llvm {
12 : namespace X86 {
13 : enum {
14 : GPRRegBankID,
15 : VECRRegBankID,
16 : NumRegisterBanks,
17 : };
18 : } // end namespace X86
19 : } // end namespace llvm
20 : #endif // GET_REGBANK_DECLARATIONS
21 :
22 : #ifdef GET_TARGET_REGBANK_CLASS
23 : #undef GET_TARGET_REGBANK_CLASS
24 : private:
25 : static RegisterBank *RegBanks[];
26 :
27 : protected:
28 : X86GenRegisterBankInfo();
29 :
30 : #endif // GET_TARGET_REGBANK_CLASS
31 :
32 : #ifdef GET_TARGET_REGBANK_IMPL
33 : #undef GET_TARGET_REGBANK_IMPL
34 : namespace llvm {
35 : namespace X86 {
36 : const uint32_t GPRRegBankCoverageData[] = {
37 : // 0-31
38 : (1u << (X86::GR8RegClassID - 0)) |
39 : (1u << (X86::GR16RegClassID - 0)) |
40 : (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
41 : (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 0)) |
42 : (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 0)) |
43 : (1u << (X86::GR32RegClassID - 0)) |
44 : (1u << (X86::GR32_NOSPRegClassID - 0)) |
45 : (1u << (X86::GR8_NOREXRegClassID - 0)) |
46 : (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
47 : (1u << (X86::GR8_ABCD_LRegClassID - 0)) |
48 : (1u << (X86::GR16_NOREXRegClassID - 0)) |
49 : (1u << (X86::GR16_ABCDRegClassID - 0)) |
50 : (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID - 0)) |
51 : (1u << (X86::GR32_NOREXRegClassID - 0)) |
52 : 0,
53 : // 32-63
54 : (1u << (X86::GR64RegClassID - 32)) |
55 : (1u << (X86::GR64_with_sub_8bitRegClassID - 32)) |
56 : (1u << (X86::GR64_NOSPRegClassID - 32)) |
57 : (1u << (X86::GR32_NOREX_NOSPRegClassID - 32)) |
58 : (1u << (X86::GR32_ABCDRegClassID - 32)) |
59 : (1u << (X86::GR32_TCRegClassID - 32)) |
60 : (1u << (X86::GR32_ADRegClassID - 32)) |
61 : (1u << (X86::GR32_DCRegClassID - 32)) |
62 : (1u << (X86::GR32_AD_and_GR32_DCRegClassID - 32)) |
63 : (1u << (X86::GR32_CBRegClassID - 32)) |
64 : (1u << (X86::GR32_CB_and_GR32_DCRegClassID - 32)) |
65 : (1u << (X86::GR32_SIDIRegClassID - 32)) |
66 : (1u << (X86::GR32_BSIRegClassID - 32)) |
67 : (1u << (X86::GR32_BSI_and_GR32_SIDIRegClassID - 32)) |
68 : (1u << (X86::GR32_DIBPRegClassID - 32)) |
69 : (1u << (X86::GR32_DIBP_and_GR32_SIDIRegClassID - 32)) |
70 : (1u << (X86::GR32_ABCD_and_GR32_BSIRegClassID - 32)) |
71 : (1u << (X86::GR32_BPSPRegClassID - 32)) |
72 : (1u << (X86::GR32_BPSP_and_GR32_DIBPRegClassID - 32)) |
73 : (1u << (X86::GR64_NOREXRegClassID - 32)) |
74 : (1u << (X86::GR64_TCRegClassID - 32)) |
75 : 0,
76 : // 64-95
77 : (1u << (X86::GR64_NOSP_and_GR64_TCRegClassID - 64)) |
78 : (1u << (X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID - 64)) |
79 : (1u << (X86::GR64_with_sub_32bit_in_GR32_TCRegClassID - 64)) |
80 : (1u << (X86::GR64_ADRegClassID - 64)) |
81 : (1u << (X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID - 64)) |
82 : (1u << (X86::GR64_with_sub_32bit_in_GR32_DCRegClassID - 64)) |
83 : (1u << (X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID - 64)) |
84 : (1u << (X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID - 64)) |
85 : (1u << (X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID - 64)) |
86 : (1u << (X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID - 64)) |
87 : (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID - 64)) |
88 : (1u << (X86::GR64_NOREX_NOSPRegClassID - 64)) |
89 : (1u << (X86::GR64_ABCDRegClassID - 64)) |
90 : (1u << (X86::GR64_with_sub_32bit_in_GR32_CBRegClassID - 64)) |
91 : (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID - 64)) |
92 : (1u << (X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID - 64)) |
93 : (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID - 64)) |
94 : (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID - 64)) |
95 : (1u << (X86::GR64_NOSP_and_GR64_TCW64RegClassID - 64)) |
96 : (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 64)) |
97 : (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID - 64)) |
98 : (1u << (X86::GR64_NOREX_and_GR64_TCRegClassID - 64)) |
99 : (1u << (X86::GR64_NOREX_and_GR64_TCW64RegClassID - 64)) |
100 : (1u << (X86::GR64_and_LOW32_ADDR_ACCESSRegClassID - 64)) |
101 : (1u << (X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID - 64)) |
102 : (1u << (X86::GR64_TC_and_GR64_TCW64RegClassID - 64)) |
103 : (1u << (X86::GR64_TCW64RegClassID - 64)) |
104 : 0,
105 : // 96-127
106 : 0,
107 : };
108 : const uint32_t VECRRegBankCoverageData[] = {
109 : // 0-31
110 : (1u << (X86::FR32XRegClassID - 0)) |
111 : (1u << (X86::FR32RegClassID - 0)) |
112 : 0,
113 : // 32-63
114 : (1u << (X86::FR64XRegClassID - 32)) |
115 : (1u << (X86::FR64RegClassID - 32)) |
116 : 0,
117 : // 64-95
118 : 0,
119 : // 96-127
120 : (1u << (X86::VR512RegClassID - 96)) |
121 : (1u << (X86::VR128XRegClassID - 96)) |
122 : (1u << (X86::VR256XRegClassID - 96)) |
123 : (1u << (X86::VR512_with_sub_xmm_in_FR32RegClassID - 96)) |
124 : (1u << (X86::VR128RegClassID - 96)) |
125 : (1u << (X86::VR256RegClassID - 96)) |
126 : (1u << (X86::VR512_with_sub_xmm_in_VR128HRegClassID - 96)) |
127 : (1u << (X86::VR128HRegClassID - 96)) |
128 : (1u << (X86::VR256HRegClassID - 96)) |
129 : (1u << (X86::VR512_with_sub_xmm_in_VR128LRegClassID - 96)) |
130 : (1u << (X86::VR128LRegClassID - 96)) |
131 : (1u << (X86::VR256LRegClassID - 96)) |
132 : 0,
133 : };
134 :
135 : RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 109);
136 : RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* Size */ 512, /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 109);
137 : } // end namespace X86
138 :
139 : RegisterBank *X86GenRegisterBankInfo::RegBanks[] = {
140 : &X86::GPRRegBank,
141 : &X86::VECRRegBank,
142 : };
143 :
144 16283 : X86GenRegisterBankInfo::X86GenRegisterBankInfo()
145 16283 : : RegisterBankInfo(RegBanks, X86::NumRegisterBanks) {
146 : // Assert that RegBank indices match their ID's
147 : #ifndef NDEBUG
148 : unsigned Index = 0;
149 : for (const auto &RB : RegBanks)
150 : assert(Index++ == RB->getID() && "Index != ID");
151 : #endif // NDEBUG
152 16283 : }
153 : } // end namespace llvm
154 : #endif // GET_TARGET_REGBANK_IMPL
|