LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/XCore - XCoreGenCallingConv.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 24 28 85.7 %
Date: 2017-09-14 15:23:50 Functions: 2 2 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Calling Convention Implementation Fragment                                 *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : static bool CC_XCore(unsigned ValNo, MVT ValVT,
      10             :                      MVT LocVT, CCValAssign::LocInfo LocInfo,
      11             :                      ISD::ArgFlagsTy ArgFlags, CCState &State);
      12             : static bool RetCC_XCore(unsigned ValNo, MVT ValVT,
      13             :                         MVT LocVT, CCValAssign::LocInfo LocInfo,
      14             :                         ISD::ArgFlagsTy ArgFlags, CCState &State);
      15             : 
      16             : 
      17         449 : static bool CC_XCore(unsigned ValNo, MVT ValVT,
      18             :                      MVT LocVT, CCValAssign::LocInfo LocInfo,
      19             :                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
      20             : 
      21         898 :   if (LocVT == MVT::i8 ||
      22         449 :       LocVT == MVT::i16) {
      23           0 :     LocVT = MVT::i32;
      24           0 :     if (ArgFlags.isSExt())
      25             :         LocInfo = CCValAssign::SExt;
      26           0 :     else if (ArgFlags.isZExt())
      27             :         LocInfo = CCValAssign::ZExt;
      28             :     else
      29           0 :         LocInfo = CCValAssign::AExt;
      30             :   }
      31             : 
      32         449 :   if (ArgFlags.isNest()) {
      33           1 :     if (unsigned Reg = State.AllocateReg(XCore::R11)) {
      34           2 :       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      35           1 :       return false;
      36             :     }
      37             :   }
      38             : 
      39         448 :   if (LocVT == MVT::i32) {
      40             :     static const MCPhysReg RegList1[] = {
      41             :       XCore::R0, XCore::R1, XCore::R2, XCore::R3
      42             :     };
      43         448 :     if (unsigned Reg = State.AllocateReg(RegList1)) {
      44         868 :       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      45         434 :       return false;
      46             :     }
      47             :   }
      48             : 
      49          14 :   if (LocVT == MVT::i32) {
      50          14 :     unsigned Offset2 = State.AllocateStack(4, 4);
      51          28 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
      52          14 :     return false;
      53             :   }
      54             : 
      55             :   return true;  // CC didn't match.
      56             : }
      57             : 
      58             : 
      59         588 : static bool RetCC_XCore(unsigned ValNo, MVT ValVT,
      60             :                         MVT LocVT, CCValAssign::LocInfo LocInfo,
      61             :                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
      62             : 
      63         588 :   if (LocVT == MVT::i32) {
      64             :     static const MCPhysReg RegList1[] = {
      65             :       XCore::R0, XCore::R1, XCore::R2, XCore::R3
      66             :     };
      67         588 :     if (unsigned Reg = State.AllocateReg(RegList1)) {
      68        1166 :       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      69         583 :       return false;
      70             :     }
      71             :   }
      72             : 
      73           5 :   if (LocVT == MVT::i32) {
      74           5 :     unsigned Offset2 = State.AllocateStack(4, 4);
      75          10 :     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
      76           5 :     return false;
      77             :   }
      78             : 
      79             :   return true;  // CC didn't match.
      80             : }

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