LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/XCore - XCoreGenInstrInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 3 4 75.0 %
Date: 2018-09-23 13:06:45 Functions: 1 3 33.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Instruction Enum Values and Descriptors                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_INSTRINFO_ENUM
      10             : #undef GET_INSTRINFO_ENUM
      11             : namespace llvm {
      12             : 
      13             : namespace XCore {
      14             :   enum {
      15             :     PHI = 0,
      16             :     INLINEASM   = 1,
      17             :     CFI_INSTRUCTION     = 2,
      18             :     EH_LABEL    = 3,
      19             :     GC_LABEL    = 4,
      20             :     ANNOTATION_LABEL    = 5,
      21             :     KILL        = 6,
      22             :     EXTRACT_SUBREG      = 7,
      23             :     INSERT_SUBREG       = 8,
      24             :     IMPLICIT_DEF        = 9,
      25             :     SUBREG_TO_REG       = 10,
      26             :     COPY_TO_REGCLASS    = 11,
      27             :     DBG_VALUE   = 12,
      28             :     DBG_LABEL   = 13,
      29             :     REG_SEQUENCE        = 14,
      30             :     COPY        = 15,
      31             :     BUNDLE      = 16,
      32             :     LIFETIME_START      = 17,
      33             :     LIFETIME_END        = 18,
      34             :     STACKMAP    = 19,
      35             :     FENTRY_CALL = 20,
      36             :     PATCHPOINT  = 21,
      37             :     LOAD_STACK_GUARD    = 22,
      38             :     STATEPOINT  = 23,
      39             :     LOCAL_ESCAPE        = 24,
      40             :     FAULTING_OP = 25,
      41             :     PATCHABLE_OP        = 26,
      42             :     PATCHABLE_FUNCTION_ENTER    = 27,
      43             :     PATCHABLE_RET       = 28,
      44             :     PATCHABLE_FUNCTION_EXIT     = 29,
      45             :     PATCHABLE_TAIL_CALL = 30,
      46             :     PATCHABLE_EVENT_CALL        = 31,
      47             :     PATCHABLE_TYPED_EVENT_CALL  = 32,
      48             :     ICALL_BRANCH_FUNNEL = 33,
      49             :     G_ADD       = 34,
      50             :     G_SUB       = 35,
      51             :     G_MUL       = 36,
      52             :     G_SDIV      = 37,
      53             :     G_UDIV      = 38,
      54             :     G_SREM      = 39,
      55             :     G_UREM      = 40,
      56             :     G_AND       = 41,
      57             :     G_OR        = 42,
      58             :     G_XOR       = 43,
      59             :     G_IMPLICIT_DEF      = 44,
      60             :     G_PHI       = 45,
      61             :     G_FRAME_INDEX       = 46,
      62             :     G_GLOBAL_VALUE      = 47,
      63             :     G_EXTRACT   = 48,
      64             :     G_UNMERGE_VALUES    = 49,
      65             :     G_INSERT    = 50,
      66             :     G_MERGE_VALUES      = 51,
      67             :     G_PTRTOINT  = 52,
      68             :     G_INTTOPTR  = 53,
      69             :     G_BITCAST   = 54,
      70             :     G_INTRINSIC_TRUNC   = 55,
      71             :     G_INTRINSIC_ROUND   = 56,
      72             :     G_LOAD      = 57,
      73             :     G_SEXTLOAD  = 58,
      74             :     G_ZEXTLOAD  = 59,
      75             :     G_STORE     = 60,
      76             :     G_ATOMIC_CMPXCHG_WITH_SUCCESS       = 61,
      77             :     G_ATOMIC_CMPXCHG    = 62,
      78             :     G_ATOMICRMW_XCHG    = 63,
      79             :     G_ATOMICRMW_ADD     = 64,
      80             :     G_ATOMICRMW_SUB     = 65,
      81             :     G_ATOMICRMW_AND     = 66,
      82             :     G_ATOMICRMW_NAND    = 67,
      83             :     G_ATOMICRMW_OR      = 68,
      84             :     G_ATOMICRMW_XOR     = 69,
      85             :     G_ATOMICRMW_MAX     = 70,
      86             :     G_ATOMICRMW_MIN     = 71,
      87             :     G_ATOMICRMW_UMAX    = 72,
      88             :     G_ATOMICRMW_UMIN    = 73,
      89             :     G_BRCOND    = 74,
      90             :     G_BRINDIRECT        = 75,
      91             :     G_INTRINSIC = 76,
      92             :     G_INTRINSIC_W_SIDE_EFFECTS  = 77,
      93             :     G_ANYEXT    = 78,
      94             :     G_TRUNC     = 79,
      95             :     G_CONSTANT  = 80,
      96             :     G_FCONSTANT = 81,
      97             :     G_VASTART   = 82,
      98             :     G_VAARG     = 83,
      99             :     G_SEXT      = 84,
     100             :     G_ZEXT      = 85,
     101             :     G_SHL       = 86,
     102             :     G_LSHR      = 87,
     103             :     G_ASHR      = 88,
     104             :     G_ICMP      = 89,
     105             :     G_FCMP      = 90,
     106             :     G_SELECT    = 91,
     107             :     G_UADDO     = 92,
     108             :     G_UADDE     = 93,
     109             :     G_USUBO     = 94,
     110             :     G_USUBE     = 95,
     111             :     G_SADDO     = 96,
     112             :     G_SADDE     = 97,
     113             :     G_SSUBO     = 98,
     114             :     G_SSUBE     = 99,
     115             :     G_UMULO     = 100,
     116             :     G_SMULO     = 101,
     117             :     G_UMULH     = 102,
     118             :     G_SMULH     = 103,
     119             :     G_FADD      = 104,
     120             :     G_FSUB      = 105,
     121             :     G_FMUL      = 106,
     122             :     G_FMA       = 107,
     123             :     G_FDIV      = 108,
     124             :     G_FREM      = 109,
     125             :     G_FPOW      = 110,
     126             :     G_FEXP      = 111,
     127             :     G_FEXP2     = 112,
     128             :     G_FLOG      = 113,
     129             :     G_FLOG2     = 114,
     130             :     G_FNEG      = 115,
     131             :     G_FPEXT     = 116,
     132             :     G_FPTRUNC   = 117,
     133             :     G_FPTOSI    = 118,
     134             :     G_FPTOUI    = 119,
     135             :     G_SITOFP    = 120,
     136             :     G_UITOFP    = 121,
     137             :     G_FABS      = 122,
     138             :     G_GEP       = 123,
     139             :     G_PTR_MASK  = 124,
     140             :     G_BR        = 125,
     141             :     G_INSERT_VECTOR_ELT = 126,
     142             :     G_EXTRACT_VECTOR_ELT        = 127,
     143             :     G_SHUFFLE_VECTOR    = 128,
     144             :     G_CTTZ      = 129,
     145             :     G_CTTZ_ZERO_UNDEF   = 130,
     146             :     G_CTLZ      = 131,
     147             :     G_CTLZ_ZERO_UNDEF   = 132,
     148             :     G_CTPOP     = 133,
     149             :     G_BSWAP     = 134,
     150             :     G_ADDRSPACE_CAST    = 135,
     151             :     G_BLOCK_ADDR        = 136,
     152             :     ADJCALLSTACKDOWN    = 137,
     153             :     ADJCALLSTACKUP      = 138,
     154             :     BR_JT       = 139,
     155             :     BR_JT32     = 140,
     156             :     EH_RETURN   = 141,
     157             :     FRAME_TO_ARGS_OFFSET        = 142,
     158             :     Int_MemBarrier      = 143,
     159             :     LDAWFI      = 144,
     160             :     LDWFI       = 145,
     161             :     SELECT_CC   = 146,
     162             :     STWFI       = 147,
     163             :     ADD_2rus    = 148,
     164             :     ADD_3r      = 149,
     165             :     ANDNOT_2r   = 150,
     166             :     AND_3r      = 151,
     167             :     ASHR_l2rus  = 152,
     168             :     ASHR_l3r    = 153,
     169             :     BAU_1r      = 154,
     170             :     BITREV_l2r  = 155,
     171             :     BLACP_lu10  = 156,
     172             :     BLACP_u10   = 157,
     173             :     BLAT_lu6    = 158,
     174             :     BLAT_u6     = 159,
     175             :     BLA_1r      = 160,
     176             :     BLRB_lu10   = 161,
     177             :     BLRB_u10    = 162,
     178             :     BLRF_lu10   = 163,
     179             :     BLRF_u10    = 164,
     180             :     BRBF_lru6   = 165,
     181             :     BRBF_ru6    = 166,
     182             :     BRBT_lru6   = 167,
     183             :     BRBT_ru6    = 168,
     184             :     BRBU_lu6    = 169,
     185             :     BRBU_u6     = 170,
     186             :     BRFF_lru6   = 171,
     187             :     BRFF_ru6    = 172,
     188             :     BRFT_lru6   = 173,
     189             :     BRFT_ru6    = 174,
     190             :     BRFU_lu6    = 175,
     191             :     BRFU_u6     = 176,
     192             :     BRU_1r      = 177,
     193             :     BYTEREV_l2r = 178,
     194             :     CHKCT_2r    = 179,
     195             :     CHKCT_rus   = 180,
     196             :     CLRE_0R     = 181,
     197             :     CLRPT_1R    = 182,
     198             :     CLRSR_branch_lu6    = 183,
     199             :     CLRSR_branch_u6     = 184,
     200             :     CLRSR_lu6   = 185,
     201             :     CLRSR_u6    = 186,
     202             :     CLZ_l2r     = 187,
     203             :     CRC8_l4r    = 188,
     204             :     CRC_l3r     = 189,
     205             :     DCALL_0R    = 190,
     206             :     DENTSP_0R   = 191,
     207             :     DGETREG_1r  = 192,
     208             :     DIVS_l3r    = 193,
     209             :     DIVU_l3r    = 194,
     210             :     DRESTSP_0R  = 195,
     211             :     DRET_0R     = 196,
     212             :     ECALLF_1r   = 197,
     213             :     ECALLT_1r   = 198,
     214             :     EDU_1r      = 199,
     215             :     EEF_2r      = 200,
     216             :     EET_2r      = 201,
     217             :     EEU_1r      = 202,
     218             :     ENDIN_2r    = 203,
     219             :     ENTSP_lu6   = 204,
     220             :     ENTSP_u6    = 205,
     221             :     EQ_2rus     = 206,
     222             :     EQ_3r       = 207,
     223             :     EXTDP_lu6   = 208,
     224             :     EXTDP_u6    = 209,
     225             :     EXTSP_lu6   = 210,
     226             :     EXTSP_u6    = 211,
     227             :     FREER_1r    = 212,
     228             :     FREET_0R    = 213,
     229             :     GETD_l2r    = 214,
     230             :     GETED_0R    = 215,
     231             :     GETET_0R    = 216,
     232             :     GETID_0R    = 217,
     233             :     GETKEP_0R   = 218,
     234             :     GETKSP_0R   = 219,
     235             :     GETN_l2r    = 220,
     236             :     GETPS_l2r   = 221,
     237             :     GETR_rus    = 222,
     238             :     GETSR_lu6   = 223,
     239             :     GETSR_u6    = 224,
     240             :     GETST_2r    = 225,
     241             :     GETTS_2r    = 226,
     242             :     INCT_2r     = 227,
     243             :     INITCP_2r   = 228,
     244             :     INITDP_2r   = 229,
     245             :     INITLR_l2r  = 230,
     246             :     INITPC_2r   = 231,
     247             :     INITSP_2r   = 232,
     248             :     INPW_l2rus  = 233,
     249             :     INSHR_2r    = 234,
     250             :     INT_2r      = 235,
     251             :     IN_2r       = 236,
     252             :     KCALL_1r    = 237,
     253             :     KCALL_lu6   = 238,
     254             :     KCALL_u6    = 239,
     255             :     KENTSP_lu6  = 240,
     256             :     KENTSP_u6   = 241,
     257             :     KRESTSP_lu6 = 242,
     258             :     KRESTSP_u6  = 243,
     259             :     KRET_0R     = 244,
     260             :     LADD_l5r    = 245,
     261             :     LD16S_3r    = 246,
     262             :     LD8U_3r     = 247,
     263             :     LDA16B_l3r  = 248,
     264             :     LDA16F_l3r  = 249,
     265             :     LDAPB_lu10  = 250,
     266             :     LDAPB_u10   = 251,
     267             :     LDAPF_lu10  = 252,
     268             :     LDAPF_lu10_ba       = 253,
     269             :     LDAPF_u10   = 254,
     270             :     LDAWB_l2rus = 255,
     271             :     LDAWB_l3r   = 256,
     272             :     LDAWCP_lu6  = 257,
     273             :     LDAWCP_u6   = 258,
     274             :     LDAWDP_lru6 = 259,
     275             :     LDAWDP_ru6  = 260,
     276             :     LDAWF_l2rus = 261,
     277             :     LDAWF_l3r   = 262,
     278             :     LDAWSP_lru6 = 263,
     279             :     LDAWSP_ru6  = 264,
     280             :     LDC_lru6    = 265,
     281             :     LDC_ru6     = 266,
     282             :     LDET_0R     = 267,
     283             :     LDIVU_l5r   = 268,
     284             :     LDSED_0R    = 269,
     285             :     LDSPC_0R    = 270,
     286             :     LDSSR_0R    = 271,
     287             :     LDWCP_lru6  = 272,
     288             :     LDWCP_lu10  = 273,
     289             :     LDWCP_ru6   = 274,
     290             :     LDWCP_u10   = 275,
     291             :     LDWDP_lru6  = 276,
     292             :     LDWDP_ru6   = 277,
     293             :     LDWSP_lru6  = 278,
     294             :     LDWSP_ru6   = 279,
     295             :     LDW_2rus    = 280,
     296             :     LDW_3r      = 281,
     297             :     LMUL_l6r    = 282,
     298             :     LSS_3r      = 283,
     299             :     LSUB_l5r    = 284,
     300             :     LSU_3r      = 285,
     301             :     MACCS_l4r   = 286,
     302             :     MACCU_l4r   = 287,
     303             :     MJOIN_1r    = 288,
     304             :     MKMSK_2r    = 289,
     305             :     MKMSK_rus   = 290,
     306             :     MSYNC_1r    = 291,
     307             :     MUL_l3r     = 292,
     308             :     NEG = 293,
     309             :     NOT = 294,
     310             :     OR_3r       = 295,
     311             :     OUTCT_2r    = 296,
     312             :     OUTCT_rus   = 297,
     313             :     OUTPW_l2rus = 298,
     314             :     OUTSHR_2r   = 299,
     315             :     OUTT_2r     = 300,
     316             :     OUT_2r      = 301,
     317             :     PEEK_2r     = 302,
     318             :     REMS_l3r    = 303,
     319             :     REMU_l3r    = 304,
     320             :     RETSP_lu6   = 305,
     321             :     RETSP_u6    = 306,
     322             :     SETCLK_l2r  = 307,
     323             :     SETCP_1r    = 308,
     324             :     SETC_l2r    = 309,
     325             :     SETC_lru6   = 310,
     326             :     SETC_ru6    = 311,
     327             :     SETDP_1r    = 312,
     328             :     SETD_2r     = 313,
     329             :     SETEV_1r    = 314,
     330             :     SETKEP_0R   = 315,
     331             :     SETN_l2r    = 316,
     332             :     SETPSC_2r   = 317,
     333             :     SETPS_l2r   = 318,
     334             :     SETPT_2r    = 319,
     335             :     SETRDY_l2r  = 320,
     336             :     SETSP_1r    = 321,
     337             :     SETSR_branch_lu6    = 322,
     338             :     SETSR_branch_u6     = 323,
     339             :     SETSR_lu6   = 324,
     340             :     SETSR_u6    = 325,
     341             :     SETTW_l2r   = 326,
     342             :     SETV_1r     = 327,
     343             :     SEXT_2r     = 328,
     344             :     SEXT_rus    = 329,
     345             :     SHL_2rus    = 330,
     346             :     SHL_3r      = 331,
     347             :     SHR_2rus    = 332,
     348             :     SHR_3r      = 333,
     349             :     SSYNC_0r    = 334,
     350             :     ST16_l3r    = 335,
     351             :     ST8_l3r     = 336,
     352             :     STET_0R     = 337,
     353             :     STSED_0R    = 338,
     354             :     STSPC_0R    = 339,
     355             :     STSSR_0R    = 340,
     356             :     STWDP_lru6  = 341,
     357             :     STWDP_ru6   = 342,
     358             :     STWSP_lru6  = 343,
     359             :     STWSP_ru6   = 344,
     360             :     STW_2rus    = 345,
     361             :     STW_l3r     = 346,
     362             :     SUB_2rus    = 347,
     363             :     SUB_3r      = 348,
     364             :     SYNCR_1r    = 349,
     365             :     TESTCT_2r   = 350,
     366             :     TESTLCL_l2r = 351,
     367             :     TESTWCT_2r  = 352,
     368             :     TSETMR_2r   = 353,
     369             :     TSETR_3r    = 354,
     370             :     TSTART_1R   = 355,
     371             :     WAITEF_1R   = 356,
     372             :     WAITET_1R   = 357,
     373             :     WAITEU_0R   = 358,
     374             :     XOR_l3r     = 359,
     375             :     ZEXT_2r     = 360,
     376             :     ZEXT_rus    = 361,
     377             :     INSTRUCTION_LIST_END = 362
     378             :   };
     379             : 
     380             : } // end XCore namespace
     381             : } // end llvm namespace
     382             : #endif // GET_INSTRINFO_ENUM
     383             : 
     384             : #ifdef GET_INSTRINFO_SCHED_ENUM
     385             : #undef GET_INSTRINFO_SCHED_ENUM
     386             : namespace llvm {
     387             : 
     388             : namespace XCore {
     389             : namespace Sched {
     390             :   enum {
     391             :     NoInstrModel        = 0,
     392             :     SCHED_LIST_END = 1
     393             :   };
     394             : } // end Sched namespace
     395             : } // end XCore namespace
     396             : } // end llvm namespace
     397             : #endif // GET_INSTRINFO_SCHED_ENUM
     398             : 
     399             : #ifdef GET_INSTRINFO_MC_DESC
     400             : #undef GET_INSTRINFO_MC_DESC
     401             : namespace llvm {
     402             : 
     403             : static const MCPhysReg ImplicitList1[] = { XCore::SP, 0 };
     404             : static const MCPhysReg ImplicitList2[] = { XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR, 0 };
     405             : static const MCPhysReg ImplicitList3[] = { XCore::R11, 0 };
     406             : 
     407             : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     408             : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     409             : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     410             : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     411             : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     412             : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     413             : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     414             : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     415             : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
     416             : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     417             : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     418             : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     419             : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     420             : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     421             : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     422             : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     423             : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     424             : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     425             : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     426             : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     427             : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     428             : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     429             : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     430             : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     431             : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     432             : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     433             : static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     434             : static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     435             : static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     436             : static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     437             : static const MCOperandInfo OperandInfo32[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     438             : static const MCOperandInfo OperandInfo33[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     439             : static const MCOperandInfo OperandInfo34[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     440             : static const MCOperandInfo OperandInfo35[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     441             : static const MCOperandInfo OperandInfo36[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     442             : static const MCOperandInfo OperandInfo37[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     443             : static const MCOperandInfo OperandInfo38[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     444             : static const MCOperandInfo OperandInfo39[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     445             : static const MCOperandInfo OperandInfo40[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     446             : static const MCOperandInfo OperandInfo41[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     447             : static const MCOperandInfo OperandInfo42[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     448             : static const MCOperandInfo OperandInfo43[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     449             : static const MCOperandInfo OperandInfo44[] = { { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     450             : static const MCOperandInfo OperandInfo45[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     451             : static const MCOperandInfo OperandInfo46[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     452             : static const MCOperandInfo OperandInfo47[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     453             : static const MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     454             : static const MCOperandInfo OperandInfo49[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     455             : 
     456             : extern const MCInstrDesc XCoreInsts[] = {
     457             :   { 0,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
     458             :   { 1,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
     459             :   { 2,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
     460             :   { 3,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
     461             :   { 4,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
     462             :   { 5,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
     463             :   { 6,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
     464             :   { 7,  3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
     465             :   { 8,  4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
     466             :   { 9,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
     467             :   { 10, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
     468             :   { 11, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
     469             :   { 12, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
     470             :   { 13, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
     471             :   { 14, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
     472             :   { 15, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
     473             :   { 16, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
     474             :   { 17, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
     475             :   { 18, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
     476             :   { 19, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
     477             :   { 20, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
     478             :   { 21, 6,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
     479             :   { 22, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
     480             :   { 23, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
     481             :   { 24, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
     482             :   { 25, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
     483             :   { 26, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
     484             :   { 27, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
     485             :   { 28, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
     486             :   { 29, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
     487             :   { 30, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
     488             :   { 31, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
     489             :   { 32, 3,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
     490             :   { 33, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
     491             :   { 34, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
     492             :   { 35, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
     493             :   { 36, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
     494             :   { 37, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
     495             :   { 38, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
     496             :   { 39, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
     497             :   { 40, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
     498             :   { 41, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
     499             :   { 42, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
     500             :   { 43, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
     501             :   { 44, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
     502             :   { 45, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
     503             :   { 46, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
     504             :   { 47, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
     505             :   { 48, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
     506             :   { 49, 2,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
     507             :   { 50, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
     508             :   { 51, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
     509             :   { 52, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
     510             :   { 53, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
     511             :   { 54, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
     512             :   { 55, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #55 = G_INTRINSIC_TRUNC
     513             :   { 56, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #56 = G_INTRINSIC_ROUND
     514             :   { 57, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_LOAD
     515             :   { 58, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_SEXTLOAD
     516             :   { 59, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = G_ZEXTLOAD
     517             :   { 60, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #60 = G_STORE
     518             :   { 61, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #61 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
     519             :   { 62, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMIC_CMPXCHG
     520             :   { 63, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_XCHG
     521             :   { 64, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_ADD
     522             :   { 65, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_SUB
     523             :   { 66, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_AND
     524             :   { 67, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_NAND
     525             :   { 68, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_OR
     526             :   { 69, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_XOR
     527             :   { 70, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_MAX
     528             :   { 71, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_MIN
     529             :   { 72, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_UMAX
     530             :   { 73, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_UMIN
     531             :   { 74, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #74 = G_BRCOND
     532             :   { 75, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #75 = G_BRINDIRECT
     533             :   { 76, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #76 = G_INTRINSIC
     534             :   { 77, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #77 = G_INTRINSIC_W_SIDE_EFFECTS
     535             :   { 78, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #78 = G_ANYEXT
     536             :   { 79, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #79 = G_TRUNC
     537             :   { 80, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #80 = G_CONSTANT
     538             :   { 81, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #81 = G_FCONSTANT
     539             :   { 82, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #82 = G_VASTART
     540             :   { 83, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #83 = G_VAARG
     541             :   { 84, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #84 = G_SEXT
     542             :   { 85, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #85 = G_ZEXT
     543             :   { 86, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_SHL
     544             :   { 87, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #87 = G_LSHR
     545             :   { 88, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #88 = G_ASHR
     546             :   { 89, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #89 = G_ICMP
     547             :   { 90, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_FCMP
     548             :   { 91, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #91 = G_SELECT
     549             :   { 92, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #92 = G_UADDO
     550             :   { 93, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #93 = G_UADDE
     551             :   { 94, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #94 = G_USUBO
     552             :   { 95, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #95 = G_USUBE
     553             :   { 96, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_SADDO
     554             :   { 97, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #97 = G_SADDE
     555             :   { 98, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #98 = G_SSUBO
     556             :   { 99, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #99 = G_SSUBE
     557             :   { 100,        4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #100 = G_UMULO
     558             :   { 101,        4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #101 = G_SMULO
     559             :   { 102,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_UMULH
     560             :   { 103,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_SMULH
     561             :   { 104,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FADD
     562             :   { 105,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #105 = G_FSUB
     563             :   { 106,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_FMUL
     564             :   { 107,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FMA
     565             :   { 108,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FDIV
     566             :   { 109,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FREM
     567             :   { 110,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FPOW
     568             :   { 111,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #111 = G_FEXP
     569             :   { 112,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #112 = G_FEXP2
     570             :   { 113,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #113 = G_FLOG
     571             :   { 114,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #114 = G_FLOG2
     572             :   { 115,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FNEG
     573             :   { 116,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #116 = G_FPEXT
     574             :   { 117,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #117 = G_FPTRUNC
     575             :   { 118,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #118 = G_FPTOSI
     576             :   { 119,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #119 = G_FPTOUI
     577             :   { 120,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #120 = G_SITOFP
     578             :   { 121,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_UITOFP
     579             :   { 122,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #122 = G_FABS
     580             :   { 123,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #123 = G_GEP
     581             :   { 124,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #124 = G_PTR_MASK
     582             :   { 125,        1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #125 = G_BR
     583             :   { 126,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #126 = G_INSERT_VECTOR_ELT
     584             :   { 127,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #127 = G_EXTRACT_VECTOR_ELT
     585             :   { 128,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #128 = G_SHUFFLE_VECTOR
     586             :   { 129,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #129 = G_CTTZ
     587             :   { 130,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #130 = G_CTTZ_ZERO_UNDEF
     588             :   { 131,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #131 = G_CTLZ
     589             :   { 132,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #132 = G_CTLZ_ZERO_UNDEF
     590             :   { 133,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #133 = G_CTPOP
     591             :   { 134,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #134 = G_BSWAP
     592             :   { 135,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_ADDRSPACE_CAST
     593             :   { 136,        2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #136 = G_BLOCK_ADDR
     594             :   { 137,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #137 = ADJCALLSTACKDOWN
     595             :   { 138,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #138 = ADJCALLSTACKUP
     596             :   { 139,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #139 = BR_JT
     597             :   { 140,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #140 = BR_JT32
     598             :   { 141,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #141 = EH_RETURN
     599             :   { 142,        1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #142 = FRAME_TO_ARGS_OFFSET
     600             :   { 143,        0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #143 = Int_MemBarrier
     601             :   { 144,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #144 = LDAWFI
     602             :   { 145,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #145 = LDWFI
     603             :   { 146,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #146 = SELECT_CC
     604             :   { 147,        3,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #147 = STWFI
     605             :   { 148,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #148 = ADD_2rus
     606             :   { 149,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #149 = ADD_3r
     607             :   { 150,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #150 = ANDNOT_2r
     608             :   { 151,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #151 = AND_3r
     609             :   { 152,        3,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #152 = ASHR_l2rus
     610             :   { 153,        3,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #153 = ASHR_l3r
     611             :   { 154,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #154 = BAU_1r
     612             :   { 155,        2,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #155 = BITREV_l2r
     613             :   { 156,        1,      0,      4,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo3, -1 ,nullptr },  // Inst #156 = BLACP_lu10
     614             :   { 157,        1,      0,      2,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo3, -1 ,nullptr },  // Inst #157 = BLACP_u10
     615             :   { 158,        1,      0,      4,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #158 = BLAT_lu6
     616             :   { 159,        1,      0,      2,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #159 = BLAT_u6
     617             :   { 160,        1,      0,      2,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo33, -1 ,nullptr },  // Inst #160 = BLA_1r
     618             :   { 161,        1,      0,      4,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #161 = BLRB_lu10
     619             :   { 162,        1,      0,      2,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #162 = BLRB_u10
     620             :   { 163,        1,      0,      4,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #163 = BLRF_lu10
     621             :   { 164,        1,      0,      2,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #164 = BLRF_u10
     622             :   { 165,        2,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #165 = BRBF_lru6
     623             :   { 166,        2,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #166 = BRBF_ru6
     624             :   { 167,        2,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #167 = BRBT_lru6
     625             :   { 168,        2,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #168 = BRBT_ru6
     626             :   { 169,        1,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #169 = BRBU_lu6
     627             :   { 170,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #170 = BRBU_u6
     628             :   { 171,        2,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #171 = BRFF_lru6
     629             :   { 172,        2,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #172 = BRFF_ru6
     630             :   { 173,        2,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #173 = BRFT_lru6
     631             :   { 174,        2,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #174 = BRFT_ru6
     632             :   { 175,        1,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #175 = BRFU_lu6
     633             :   { 176,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #176 = BRFU_u6
     634             :   { 177,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #177 = BRU_1r
     635             :   { 178,        2,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #178 = BYTEREV_l2r
     636             :   { 179,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #179 = CHKCT_2r
     637             :   { 180,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #180 = CHKCT_rus
     638             :   { 181,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #181 = CLRE_0R
     639             :   { 182,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #182 = CLRPT_1R
     640             :   { 183,        1,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #183 = CLRSR_branch_lu6
     641             :   { 184,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #184 = CLRSR_branch_u6
     642             :   { 185,        1,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #185 = CLRSR_lu6
     643             :   { 186,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #186 = CLRSR_u6
     644             :   { 187,        2,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #187 = CLZ_l2r
     645             :   { 188,        5,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #188 = CRC8_l4r
     646             :   { 189,        4,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #189 = CRC_l3r
     647             :   { 190,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #190 = DCALL_0R
     648             :   { 191,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #191 = DENTSP_0R
     649             :   { 192,        1,      1,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #192 = DGETREG_1r
     650             :   { 193,        3,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #193 = DIVS_l3r
     651             :   { 194,        3,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #194 = DIVU_l3r
     652             :   { 195,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #195 = DRESTSP_0R
     653             :   { 196,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #196 = DRET_0R
     654             :   { 197,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #197 = ECALLF_1r
     655             :   { 198,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #198 = ECALLT_1r
     656             :   { 199,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #199 = EDU_1r
     657             :   { 200,        2,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #200 = EEF_2r
     658             :   { 201,        2,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #201 = EET_2r
     659             :   { 202,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #202 = EEU_1r
     660             :   { 203,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #203 = ENDIN_2r
     661             :   { 204,        1,      0,      4,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #204 = ENTSP_lu6
     662             :   { 205,        1,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #205 = ENTSP_u6
     663             :   { 206,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #206 = EQ_2rus
     664             :   { 207,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #207 = EQ_3r
     665             :   { 208,        1,      0,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #208 = EXTDP_lu6
     666             :   { 209,        1,      0,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #209 = EXTDP_u6
     667             :   { 210,        1,      0,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #210 = EXTSP_lu6
     668             :   { 211,        1,      0,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #211 = EXTSP_u6
     669             :   { 212,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #212 = FREER_1r
     670             :   { 213,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #213 = FREET_0R
     671             :   { 214,        2,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #214 = GETD_l2r
     672             :   { 215,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #215 = GETED_0R
     673             :   { 216,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #216 = GETET_0R
     674             :   { 217,        0,      0,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #217 = GETID_0R
     675             :   { 218,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #218 = GETKEP_0R
     676             :   { 219,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #219 = GETKSP_0R
     677             :   { 220,        2,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #220 = GETN_l2r
     678             :   { 221,        2,      1,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #221 = GETPS_l2r
     679             :   { 222,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #222 = GETR_rus
     680             :   { 223,        1,      0,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #223 = GETSR_lu6
     681             :   { 224,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #224 = GETSR_u6
     682             :   { 225,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #225 = GETST_2r
     683             :   { 226,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #226 = GETTS_2r
     684             :   { 227,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #227 = INCT_2r
     685             :   { 228,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #228 = INITCP_2r
     686             :   { 229,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #229 = INITDP_2r
     687             :   { 230,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #230 = INITLR_l2r
     688             :   { 231,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #231 = INITPC_2r
     689             :   { 232,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #232 = INITSP_2r
     690             :   { 233,        3,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #233 = INPW_l2rus
     691             :   { 234,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #234 = INSHR_2r
     692             :   { 235,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #235 = INT_2r
     693             :   { 236,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #236 = IN_2r
     694             :   { 237,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #237 = KCALL_1r
     695             :   { 238,        1,      0,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #238 = KCALL_lu6
     696             :   { 239,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #239 = KCALL_u6
     697             :   { 240,        1,      0,      4,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #240 = KENTSP_lu6
     698             :   { 241,        1,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #241 = KENTSP_u6
     699             :   { 242,        1,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #242 = KRESTSP_lu6
     700             :   { 243,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #243 = KRESTSP_u6
     701             :   { 244,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #244 = KRET_0R
     702             :   { 245,        5,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #245 = LADD_l5r
     703             :   { 246,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #246 = LD16S_3r
     704             :   { 247,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #247 = LD8U_3r
     705             :   { 248,        3,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #248 = LDA16B_l3r
     706             :   { 249,        3,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #249 = LDA16F_l3r
     707             :   { 250,        1,      0,      4,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #250 = LDAPB_lu10
     708             :   { 251,        1,      0,      2,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #251 = LDAPB_u10
     709             :   { 252,        1,      0,      4,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #252 = LDAPF_lu10
     710             :   { 253,        1,      0,      4,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #253 = LDAPF_lu10_ba
     711             :   { 254,        1,      0,      2,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #254 = LDAPF_u10
     712             :   { 255,        3,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #255 = LDAWB_l2rus
     713             :   { 256,        3,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #256 = LDAWB_l3r
     714             :   { 257,        1,      0,      4,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #257 = LDAWCP_lu6
     715             :   { 258,        1,      0,      2,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #258 = LDAWCP_u6
     716             :   { 259,        2,      1,      4,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #259 = LDAWDP_lru6
     717             :   { 260,        2,      1,      2,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #260 = LDAWDP_ru6
     718             :   { 261,        3,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #261 = LDAWF_l2rus
     719             :   { 262,        3,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #262 = LDAWF_l3r
     720             :   { 263,        2,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #263 = LDAWSP_lru6
     721             :   { 264,        2,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #264 = LDAWSP_ru6
     722             :   { 265,        2,      1,      4,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #265 = LDC_lru6
     723             :   { 266,        2,      1,      2,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #266 = LDC_ru6
     724             :   { 267,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #267 = LDET_0R
     725             :   { 268,        5,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #268 = LDIVU_l5r
     726             :   { 269,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #269 = LDSED_0R
     727             :   { 270,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #270 = LDSPC_0R
     728             :   { 271,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #271 = LDSSR_0R
     729             :   { 272,        2,      1,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #272 = LDWCP_lru6
     730             :   { 273,        1,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #273 = LDWCP_lu10
     731             :   { 274,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #274 = LDWCP_ru6
     732             :   { 275,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #275 = LDWCP_u10
     733             :   { 276,        2,      1,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #276 = LDWDP_lru6
     734             :   { 277,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #277 = LDWDP_ru6
     735             :   { 278,        2,      1,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #278 = LDWSP_lru6
     736             :   { 279,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #279 = LDWSP_ru6
     737             :   { 280,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #280 = LDW_2rus
     738             :   { 281,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #281 = LDW_3r
     739             :   { 282,        6,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #282 = LMUL_l6r
     740             :   { 283,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #283 = LSS_3r
     741             :   { 284,        5,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #284 = LSUB_l5r
     742             :   { 285,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #285 = LSU_3r
     743             :   { 286,        6,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #286 = MACCS_l4r
     744             :   { 287,        6,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #287 = MACCU_l4r
     745             :   { 288,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #288 = MJOIN_1r
     746             :   { 289,        2,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #289 = MKMSK_2r
     747             :   { 290,        2,      1,      2,      0,      0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #290 = MKMSK_rus
     748             :   { 291,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #291 = MSYNC_1r
     749             :   { 292,        3,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #292 = MUL_l3r
     750             :   { 293,        2,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #293 = NEG
     751             :   { 294,        2,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #294 = NOT
     752             :   { 295,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #295 = OR_3r
     753             :   { 296,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #296 = OUTCT_2r
     754             :   { 297,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #297 = OUTCT_rus
     755             :   { 298,        3,      0,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #298 = OUTPW_l2rus
     756             :   { 299,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #299 = OUTSHR_2r
     757             :   { 300,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #300 = OUTT_2r
     758             :   { 301,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #301 = OUT_2r
     759             :   { 302,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #302 = PEEK_2r
     760             :   { 303,        3,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #303 = REMS_l3r
     761             :   { 304,        3,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #304 = REMU_l3r
     762             :   { 305,        1,      0,      4,      0,      0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #305 = RETSP_lu6
     763             :   { 306,        1,      0,      2,      0,      0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #306 = RETSP_u6
     764             :   { 307,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #307 = SETCLK_l2r
     765             :   { 308,        1,      0,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #308 = SETCP_1r
     766             :   { 309,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #309 = SETC_l2r
     767             :   { 310,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #310 = SETC_lru6
     768             :   { 311,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #311 = SETC_ru6
     769             :   { 312,        1,      0,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #312 = SETDP_1r
     770             :   { 313,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #313 = SETD_2r
     771             :   { 314,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #314 = SETEV_1r
     772             :   { 315,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, nullptr, -1 ,nullptr },  // Inst #315 = SETKEP_0R
     773             :   { 316,        2,      0,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #316 = SETN_l2r
     774             :   { 317,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #317 = SETPSC_2r
     775             :   { 318,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #318 = SETPS_l2r
     776             :   { 319,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #319 = SETPT_2r
     777             :   { 320,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #320 = SETRDY_l2r
     778             :   { 321,        1,      0,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #321 = SETSP_1r
     779             :   { 322,        1,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #322 = SETSR_branch_lu6
     780             :   { 323,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #323 = SETSR_branch_u6
     781             :   { 324,        1,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #324 = SETSR_lu6
     782             :   { 325,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #325 = SETSR_u6
     783             :   { 326,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #326 = SETTW_l2r
     784             :   { 327,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #327 = SETV_1r
     785             :   { 328,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #328 = SEXT_2r
     786             :   { 329,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #329 = SEXT_rus
     787             :   { 330,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #330 = SHL_2rus
     788             :   { 331,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #331 = SHL_3r
     789             :   { 332,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #332 = SHR_2rus
     790             :   { 333,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #333 = SHR_3r
     791             :   { 334,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #334 = SSYNC_0r
     792             :   { 335,        3,      0,      4,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #335 = ST16_l3r
     793             :   { 336,        3,      0,      4,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #336 = ST8_l3r
     794             :   { 337,        0,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #337 = STET_0R
     795             :   { 338,        0,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #338 = STSED_0R
     796             :   { 339,        0,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #339 = STSPC_0R
     797             :   { 340,        0,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #340 = STSSR_0R
     798             :   { 341,        2,      0,      4,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #341 = STWDP_lru6
     799             :   { 342,        2,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #342 = STWDP_ru6
     800             :   { 343,        2,      0,      4,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #343 = STWSP_lru6
     801             :   { 344,        2,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #344 = STWSP_ru6
     802             :   { 345,        3,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #345 = STW_2rus
     803             :   { 346,        3,      0,      4,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #346 = STW_l3r
     804             :   { 347,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #347 = SUB_2rus
     805             :   { 348,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #348 = SUB_3r
     806             :   { 349,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #349 = SYNCR_1r
     807             :   { 350,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #350 = TESTCT_2r
     808             :   { 351,        2,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #351 = TESTLCL_l2r
     809             :   { 352,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #352 = TESTWCT_2r
     810             :   { 353,        2,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #353 = TSETMR_2r
     811             :   { 354,        3,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #354 = TSETR_3r
     812             :   { 355,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #355 = TSTART_1R
     813             :   { 356,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #356 = WAITEF_1R
     814             :   { 357,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #357 = WAITET_1R
     815             :   { 358,        0,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #358 = WAITEU_0R
     816             :   { 359,        3,      1,      4,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #359 = XOR_l3r
     817             :   { 360,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #360 = ZEXT_2r
     818             :   { 361,        3,      1,      2,      0,      0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #361 = ZEXT_rus
     819             : };
     820             : 
     821             : extern const char XCoreInstrNameData[] = {
     822             :   /* 0 */ 'L', 'D', 'A', 'P', 'B', '_', 'u', '1', '0', 0,
     823             :   /* 10 */ 'B', 'L', 'R', 'B', '_', 'u', '1', '0', 0,
     824             :   /* 19 */ 'L', 'D', 'A', 'P', 'F', '_', 'u', '1', '0', 0,
     825             :   /* 29 */ 'B', 'L', 'R', 'F', '_', 'u', '1', '0', 0,
     826             :   /* 38 */ 'B', 'L', 'A', 'C', 'P', '_', 'u', '1', '0', 0,
     827             :   /* 48 */ 'L', 'D', 'W', 'C', 'P', '_', 'u', '1', '0', 0,
     828             :   /* 58 */ 'L', 'D', 'A', 'P', 'B', '_', 'l', 'u', '1', '0', 0,
     829             :   /* 69 */ 'B', 'L', 'R', 'B', '_', 'l', 'u', '1', '0', 0,
     830             :   /* 79 */ 'L', 'D', 'A', 'P', 'F', '_', 'l', 'u', '1', '0', 0,
     831             :   /* 90 */ 'B', 'L', 'R', 'F', '_', 'l', 'u', '1', '0', 0,
     832             :   /* 100 */ 'B', 'L', 'A', 'C', 'P', '_', 'l', 'u', '1', '0', 0,
     833             :   /* 111 */ 'L', 'D', 'W', 'C', 'P', '_', 'l', 'u', '1', '0', 0,
     834             :   /* 122 */ 'B', 'R', '_', 'J', 'T', '3', '2', 0,
     835             :   /* 130 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
     836             :   /* 138 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
     837             :   /* 146 */ 'K', 'C', 'A', 'L', 'L', '_', 'u', '6', 0,
     838             :   /* 155 */ 'L', 'D', 'A', 'W', 'C', 'P', '_', 'u', '6', 0,
     839             :   /* 165 */ 'E', 'X', 'T', 'D', 'P', '_', 'u', '6', 0,
     840             :   /* 174 */ 'R', 'E', 'T', 'S', 'P', '_', 'u', '6', 0,
     841             :   /* 183 */ 'K', 'E', 'N', 'T', 'S', 'P', '_', 'u', '6', 0,
     842             :   /* 193 */ 'K', 'R', 'E', 'S', 'T', 'S', 'P', '_', 'u', '6', 0,
     843             :   /* 204 */ 'E', 'X', 'T', 'S', 'P', '_', 'u', '6', 0,
     844             :   /* 213 */ 'C', 'L', 'R', 'S', 'R', '_', 'u', '6', 0,
     845             :   /* 222 */ 'G', 'E', 'T', 'S', 'R', '_', 'u', '6', 0,
     846             :   /* 231 */ 'S', 'E', 'T', 'S', 'R', '_', 'u', '6', 0,
     847             :   /* 240 */ 'B', 'L', 'A', 'T', '_', 'u', '6', 0,
     848             :   /* 248 */ 'B', 'R', 'B', 'U', '_', 'u', '6', 0,
     849             :   /* 256 */ 'B', 'R', 'F', 'U', '_', 'u', '6', 0,
     850             :   /* 264 */ 'C', 'L', 'R', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'u', '6', 0,
     851             :   /* 280 */ 'S', 'E', 'T', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'u', '6', 0,
     852             :   /* 296 */ 'K', 'C', 'A', 'L', 'L', '_', 'l', 'u', '6', 0,
     853             :   /* 306 */ 'L', 'D', 'A', 'W', 'C', 'P', '_', 'l', 'u', '6', 0,
     854             :   /* 317 */ 'E', 'X', 'T', 'D', 'P', '_', 'l', 'u', '6', 0,
     855             :   /* 327 */ 'R', 'E', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
     856             :   /* 337 */ 'K', 'E', 'N', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
     857             :   /* 348 */ 'K', 'R', 'E', 'S', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
     858             :   /* 360 */ 'E', 'X', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
     859             :   /* 370 */ 'C', 'L', 'R', 'S', 'R', '_', 'l', 'u', '6', 0,
     860             :   /* 380 */ 'G', 'E', 'T', 'S', 'R', '_', 'l', 'u', '6', 0,
     861             :   /* 390 */ 'S', 'E', 'T', 'S', 'R', '_', 'l', 'u', '6', 0,
     862             :   /* 400 */ 'B', 'L', 'A', 'T', '_', 'l', 'u', '6', 0,
     863             :   /* 409 */ 'B', 'R', 'B', 'U', '_', 'l', 'u', '6', 0,
     864             :   /* 418 */ 'B', 'R', 'F', 'U', '_', 'l', 'u', '6', 0,
     865             :   /* 427 */ 'C', 'L', 'R', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'l', 'u', '6', 0,
     866             :   /* 444 */ 'S', 'E', 'T', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'l', 'u', '6', 0,
     867             :   /* 461 */ 'L', 'D', 'C', '_', 'r', 'u', '6', 0,
     868             :   /* 469 */ 'S', 'E', 'T', 'C', '_', 'r', 'u', '6', 0,
     869             :   /* 478 */ 'B', 'R', 'B', 'F', '_', 'r', 'u', '6', 0,
     870             :   /* 487 */ 'B', 'R', 'F', 'F', '_', 'r', 'u', '6', 0,
     871             :   /* 496 */ 'L', 'D', 'W', 'C', 'P', '_', 'r', 'u', '6', 0,
     872             :   /* 506 */ 'L', 'D', 'A', 'W', 'D', 'P', '_', 'r', 'u', '6', 0,
     873             :   /* 517 */ 'L', 'D', 'W', 'D', 'P', '_', 'r', 'u', '6', 0,
     874             :   /* 527 */ 'S', 'T', 'W', 'D', 'P', '_', 'r', 'u', '6', 0,
     875             :   /* 537 */ 'L', 'D', 'A', 'W', 'S', 'P', '_', 'r', 'u', '6', 0,
     876             :   /* 548 */ 'L', 'D', 'W', 'S', 'P', '_', 'r', 'u', '6', 0,
     877             :   /* 558 */ 'S', 'T', 'W', 'S', 'P', '_', 'r', 'u', '6', 0,
     878             :   /* 568 */ 'B', 'R', 'B', 'T', '_', 'r', 'u', '6', 0,
     879             :   /* 577 */ 'B', 'R', 'F', 'T', '_', 'r', 'u', '6', 0,
     880             :   /* 586 */ 'L', 'D', 'C', '_', 'l', 'r', 'u', '6', 0,
     881             :   /* 595 */ 'S', 'E', 'T', 'C', '_', 'l', 'r', 'u', '6', 0,
     882             :   /* 605 */ 'B', 'R', 'B', 'F', '_', 'l', 'r', 'u', '6', 0,
     883             :   /* 615 */ 'B', 'R', 'F', 'F', '_', 'l', 'r', 'u', '6', 0,
     884             :   /* 625 */ 'L', 'D', 'W', 'C', 'P', '_', 'l', 'r', 'u', '6', 0,
     885             :   /* 636 */ 'L', 'D', 'A', 'W', 'D', 'P', '_', 'l', 'r', 'u', '6', 0,
     886             :   /* 648 */ 'L', 'D', 'W', 'D', 'P', '_', 'l', 'r', 'u', '6', 0,
     887             :   /* 659 */ 'S', 'T', 'W', 'D', 'P', '_', 'l', 'r', 'u', '6', 0,
     888             :   /* 670 */ 'L', 'D', 'A', 'W', 'S', 'P', '_', 'l', 'r', 'u', '6', 0,
     889             :   /* 682 */ 'L', 'D', 'W', 'S', 'P', '_', 'l', 'r', 'u', '6', 0,
     890             :   /* 693 */ 'S', 'T', 'W', 'S', 'P', '_', 'l', 'r', 'u', '6', 0,
     891             :   /* 704 */ 'B', 'R', 'B', 'T', '_', 'l', 'r', 'u', '6', 0,
     892             :   /* 714 */ 'B', 'R', 'F', 'T', '_', 'l', 'r', 'u', '6', 0,
     893             :   /* 724 */ 'G', '_', 'F', 'M', 'A', 0,
     894             :   /* 730 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
     895             :   /* 737 */ 'G', '_', 'S', 'U', 'B', 0,
     896             :   /* 743 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
     897             :   /* 759 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', 0,
     898             :   /* 769 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
     899             :   /* 781 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
     900             :   /* 791 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
     901             :   /* 809 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
     902             :   /* 817 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
     903             :   /* 828 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
     904             :   /* 839 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
     905             :   /* 846 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
     906             :   /* 853 */ 'G', '_', 'A', 'D', 'D', 0,
     907             :   /* 859 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
     908             :   /* 875 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
     909             :   /* 892 */ 'G', '_', 'A', 'N', 'D', 0,
     910             :   /* 898 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
     911             :   /* 914 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
     912             :   /* 927 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
     913             :   /* 936 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
     914             :   /* 954 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
     915             :   /* 971 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
     916             :   /* 979 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
     917             :   /* 987 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
     918             :   /* 1000 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
     919             :   /* 1008 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
     920             :   /* 1016 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
     921             :   /* 1023 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
     922             :   /* 1036 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
     923             :   /* 1044 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
     924             :   /* 1054 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
     925             :   /* 1069 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
     926             :   /* 1087 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
     927             :   /* 1105 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
     928             :   /* 1120 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
     929             :   /* 1127 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     930             :   /* 1142 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     931             :   /* 1156 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
     932             :   /* 1170 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
     933             :   /* 1187 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
     934             :   /* 1204 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
     935             :   /* 1211 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
     936             :   /* 1219 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
     937             :   /* 1227 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
     938             :   /* 1235 */ 'L', 'D', 'A', 'W', 'F', 'I', 0,
     939             :   /* 1242 */ 'L', 'D', 'W', 'F', 'I', 0,
     940             :   /* 1248 */ 'S', 'T', 'W', 'F', 'I', 0,
     941             :   /* 1254 */ 'G', '_', 'P', 'H', 'I', 0,
     942             :   /* 1260 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
     943             :   /* 1269 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
     944             :   /* 1278 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
     945             :   /* 1289 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
     946             :   /* 1298 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
     947             :   /* 1308 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
     948             :   /* 1317 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
     949             :   /* 1334 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
     950             :   /* 1354 */ 'G', '_', 'S', 'H', 'L', 0,
     951             :   /* 1360 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
     952             :   /* 1380 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
     953             :   /* 1407 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
     954             :   /* 1428 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
     955             :   /* 1440 */ 'K', 'I', 'L', 'L', 0,
     956             :   /* 1445 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
     957             :   /* 1452 */ 'G', '_', 'M', 'U', 'L', 0,
     958             :   /* 1458 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
     959             :   /* 1465 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
     960             :   /* 1472 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
     961             :   /* 1479 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
     962             :   /* 1489 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
     963             :   /* 1506 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
     964             :   /* 1522 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
     965             :   /* 1538 */ 'E', 'H', '_', 'R', 'E', 'T', 'U', 'R', 'N', 0,
     966             :   /* 1548 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
     967             :   /* 1565 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
     968             :   /* 1573 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
     969             :   /* 1581 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
     970             :   /* 1589 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
     971             :   /* 1597 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
     972             :   /* 1605 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
     973             :   /* 1613 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
     974             :   /* 1622 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
     975             :   /* 1630 */ 'G', '_', 'G', 'E', 'P', 0,
     976             :   /* 1636 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
     977             :   /* 1645 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
     978             :   /* 1654 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
     979             :   /* 1661 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
     980             :   /* 1668 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
     981             :   /* 1676 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
     982             :   /* 1689 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
     983             :   /* 1701 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
     984             :   /* 1716 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
     985             :   /* 1723 */ 'L', 'D', 'S', 'P', 'C', '_', '0', 'R', 0,
     986             :   /* 1732 */ 'S', 'T', 'S', 'P', 'C', '_', '0', 'R', 0,
     987             :   /* 1741 */ 'L', 'D', 'S', 'E', 'D', '_', '0', 'R', 0,
     988             :   /* 1750 */ 'S', 'T', 'S', 'E', 'D', '_', '0', 'R', 0,
     989             :   /* 1759 */ 'G', 'E', 'T', 'E', 'D', '_', '0', 'R', 0,
     990             :   /* 1768 */ 'G', 'E', 'T', 'I', 'D', '_', '0', 'R', 0,
     991             :   /* 1777 */ 'C', 'L', 'R', 'E', '_', '0', 'R', 0,
     992             :   /* 1785 */ 'D', 'C', 'A', 'L', 'L', '_', '0', 'R', 0,
     993             :   /* 1794 */ 'G', 'E', 'T', 'K', 'E', 'P', '_', '0', 'R', 0,
     994             :   /* 1804 */ 'S', 'E', 'T', 'K', 'E', 'P', '_', '0', 'R', 0,
     995             :   /* 1814 */ 'G', 'E', 'T', 'K', 'S', 'P', '_', '0', 'R', 0,
     996             :   /* 1824 */ 'D', 'E', 'N', 'T', 'S', 'P', '_', '0', 'R', 0,
     997             :   /* 1834 */ 'D', 'R', 'E', 'S', 'T', 'S', 'P', '_', '0', 'R', 0,
     998             :   /* 1845 */ 'L', 'D', 'S', 'S', 'R', '_', '0', 'R', 0,
     999             :   /* 1854 */ 'S', 'T', 'S', 'S', 'R', '_', '0', 'R', 0,
    1000             :   /* 1863 */ 'L', 'D', 'E', 'T', '_', '0', 'R', 0,
    1001             :   /* 1871 */ 'F', 'R', 'E', 'E', 'T', '_', '0', 'R', 0,
    1002             :   /* 1880 */ 'D', 'R', 'E', 'T', '_', '0', 'R', 0,
    1003             :   /* 1888 */ 'K', 'R', 'E', 'T', '_', '0', 'R', 0,
    1004             :   /* 1896 */ 'G', 'E', 'T', 'E', 'T', '_', '0', 'R', 0,
    1005             :   /* 1905 */ 'S', 'T', 'E', 'T', '_', '0', 'R', 0,
    1006             :   /* 1913 */ 'W', 'A', 'I', 'T', 'E', 'U', '_', '0', 'R', 0,
    1007             :   /* 1923 */ 'W', 'A', 'I', 'T', 'E', 'F', '_', '1', 'R', 0,
    1008             :   /* 1933 */ 'W', 'A', 'I', 'T', 'E', 'T', '_', '1', 'R', 0,
    1009             :   /* 1943 */ 'C', 'L', 'R', 'P', 'T', '_', '1', 'R', 0,
    1010             :   /* 1952 */ 'T', 'S', 'T', 'A', 'R', 'T', '_', '1', 'R', 0,
    1011             :   /* 1962 */ 'G', '_', 'B', 'R', 0,
    1012             :   /* 1967 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
    1013             :   /* 1980 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
    1014             :   /* 2005 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
    1015             :   /* 2012 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
    1016             :   /* 2019 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
    1017             :   /* 2036 */ 'G', '_', 'X', 'O', 'R', 0,
    1018             :   /* 2042 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
    1019             :   /* 2058 */ 'G', '_', 'O', 'R', 0,
    1020             :   /* 2063 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
    1021             :   /* 2078 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
    1022             :   /* 2089 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
    1023             :   /* 2096 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
    1024             :   /* 2113 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
    1025             :   /* 2128 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
    1026             :   /* 2145 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
    1027             :   /* 2175 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
    1028             :   /* 2202 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
    1029             :   /* 2212 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
    1030             :   /* 2221 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
    1031             :   /* 2234 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
    1032             :   /* 2248 */ 'F', 'R', 'A', 'M', 'E', '_', 'T', 'O', '_', 'A', 'R', 'G', 'S', '_', 'O', 'F', 'F', 'S', 'E', 'T', 0,
    1033             :   /* 2269 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
    1034             :   /* 2293 */ 'B', 'R', '_', 'J', 'T', 0,
    1035             :   /* 2299 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
    1036             :   /* 2320 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
    1037             :   /* 2340 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
    1038             :   /* 2352 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
    1039             :   /* 2363 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
    1040             :   /* 2374 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
    1041             :   /* 2385 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
    1042             :   /* 2396 */ 'N', 'O', 'T', 0,
    1043             :   /* 2400 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
    1044             :   /* 2410 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
    1045             :   /* 2425 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
    1046             :   /* 2434 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
    1047             :   /* 2444 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
    1048             :   /* 2461 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
    1049             :   /* 2469 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
    1050             :   /* 2476 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
    1051             :   /* 2485 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
    1052             :   /* 2492 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
    1053             :   /* 2499 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
    1054             :   /* 2506 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
    1055             :   /* 2513 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
    1056             :   /* 2520 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
    1057             :   /* 2537 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
    1058             :   /* 2553 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
    1059             :   /* 2567 */ 'C', 'O', 'P', 'Y', 0,
    1060             :   /* 2572 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
    1061             :   /* 2579 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
    1062             :   /* 2586 */ 'L', 'D', 'A', 'P', 'F', '_', 'l', 'u', '1', '0', '_', 'b', 'a', 0,
    1063             :   /* 2600 */ 'S', 'S', 'Y', 'N', 'C', '_', '0', 'r', 0,
    1064             :   /* 2609 */ 'B', 'L', 'A', '_', '1', 'r', 0,
    1065             :   /* 2616 */ 'M', 'S', 'Y', 'N', 'C', '_', '1', 'r', 0,
    1066             :   /* 2625 */ 'E', 'C', 'A', 'L', 'L', 'F', '_', '1', 'r', 0,
    1067             :   /* 2635 */ 'D', 'G', 'E', 'T', 'R', 'E', 'G', '_', '1', 'r', 0,
    1068             :   /* 2646 */ 'K', 'C', 'A', 'L', 'L', '_', '1', 'r', 0,
    1069             :   /* 2655 */ 'M', 'J', 'O', 'I', 'N', '_', '1', 'r', 0,
    1070             :   /* 2664 */ 'S', 'E', 'T', 'C', 'P', '_', '1', 'r', 0,
    1071             :   /* 2673 */ 'S', 'E', 'T', 'D', 'P', '_', '1', 'r', 0,
    1072             :   /* 2682 */ 'S', 'E', 'T', 'S', 'P', '_', '1', 'r', 0,
    1073             :   /* 2691 */ 'S', 'Y', 'N', 'C', 'R', '_', '1', 'r', 0,
    1074             :   /* 2700 */ 'F', 'R', 'E', 'E', 'R', '_', '1', 'r', 0,
    1075             :   /* 2709 */ 'E', 'C', 'A', 'L', 'L', 'T', '_', '1', 'r', 0,
    1076             :   /* 2719 */ 'B', 'A', 'U', '_', '1', 'r', 0,
    1077             :   /* 2726 */ 'E', 'D', 'U', '_', '1', 'r', 0,
    1078             :   /* 2733 */ 'E', 'E', 'U', '_', '1', 'r', 0,
    1079             :   /* 2740 */ 'B', 'R', 'U', '_', '1', 'r', 0,
    1080             :   /* 2747 */ 'S', 'E', 'T', 'E', 'V', '_', '1', 'r', 0,
    1081             :   /* 2756 */ 'S', 'E', 'T', 'V', '_', '1', 'r', 0,
    1082             :   /* 2764 */ 'I', 'N', 'I', 'T', 'P', 'C', '_', '2', 'r', 0,
    1083             :   /* 2774 */ 'S', 'E', 'T', 'P', 'S', 'C', '_', '2', 'r', 0,
    1084             :   /* 2784 */ 'S', 'E', 'T', 'D', '_', '2', 'r', 0,
    1085             :   /* 2792 */ 'E', 'E', 'F', '_', '2', 'r', 0,
    1086             :   /* 2799 */ 'P', 'E', 'E', 'K', '_', '2', 'r', 0,
    1087             :   /* 2807 */ 'M', 'K', 'M', 'S', 'K', '_', '2', 'r', 0,
    1088             :   /* 2816 */ 'E', 'N', 'D', 'I', 'N', '_', '2', 'r', 0,
    1089             :   /* 2825 */ 'I', 'N', 'I', 'T', 'C', 'P', '_', '2', 'r', 0,
    1090             :   /* 2835 */ 'I', 'N', 'I', 'T', 'D', 'P', '_', '2', 'r', 0,
    1091             :   /* 2845 */ 'I', 'N', 'I', 'T', 'S', 'P', '_', '2', 'r', 0,
    1092             :   /* 2855 */ 'I', 'N', 'S', 'H', 'R', '_', '2', 'r', 0,
    1093             :   /* 2864 */ 'O', 'U', 'T', 'S', 'H', 'R', '_', '2', 'r', 0,
    1094             :   /* 2874 */ 'T', 'S', 'E', 'T', 'M', 'R', '_', '2', 'r', 0,
    1095             :   /* 2884 */ 'G', 'E', 'T', 'T', 'S', '_', '2', 'r', 0,
    1096             :   /* 2893 */ 'C', 'H', 'K', 'C', 'T', '_', '2', 'r', 0,
    1097             :   /* 2902 */ 'I', 'N', 'C', 'T', '_', '2', 'r', 0,
    1098             :   /* 2910 */ 'T', 'E', 'S', 'T', 'C', 'T', '_', '2', 'r', 0,
    1099             :   /* 2920 */ 'O', 'U', 'T', 'C', 'T', '_', '2', 'r', 0,
    1100             :   /* 2929 */ 'T', 'E', 'S', 'T', 'W', 'C', 'T', '_', '2', 'r', 0,
    1101             :   /* 2940 */ 'E', 'E', 'T', '_', '2', 'r', 0,
    1102             :   /* 2947 */ 'I', 'N', 'T', '_', '2', 'r', 0,
    1103             :   /* 2954 */ 'A', 'N', 'D', 'N', 'O', 'T', '_', '2', 'r', 0,
    1104             :   /* 2964 */ 'S', 'E', 'T', 'P', 'T', '_', '2', 'r', 0,
    1105             :   /* 2973 */ 'G', 'E', 'T', 'S', 'T', '_', '2', 'r', 0,
    1106             :   /* 2982 */ 'O', 'U', 'T', 'T', '_', '2', 'r', 0,
    1107             :   /* 2990 */ 'O', 'U', 'T', '_', '2', 'r', 0,
    1108             :   /* 2997 */ 'S', 'E', 'X', 'T', '_', '2', 'r', 0,
    1109             :   /* 3005 */ 'Z', 'E', 'X', 'T', '_', '2', 'r', 0,
    1110             :   /* 3013 */ 'S', 'E', 'T', 'C', '_', 'l', '2', 'r', 0,
    1111             :   /* 3022 */ 'G', 'E', 'T', 'D', '_', 'l', '2', 'r', 0,
    1112             :   /* 3031 */ 'S', 'E', 'T', 'C', 'L', 'K', '_', 'l', '2', 'r', 0,
    1113             :   /* 3042 */ 'T', 'E', 'S', 'T', 'L', 'C', 'L', '_', 'l', '2', 'r', 0,
    1114             :   /* 3054 */ 'G', 'E', 'T', 'N', '_', 'l', '2', 'r', 0,
    1115             :   /* 3063 */ 'S', 'E', 'T', 'N', '_', 'l', '2', 'r', 0,
    1116             :   /* 3072 */ 'I', 'N', 'I', 'T', 'L', 'R', '_', 'l', '2', 'r', 0,
    1117             :   /* 3083 */ 'G', 'E', 'T', 'P', 'S', '_', 'l', '2', 'r', 0,
    1118             :   /* 3093 */ 'S', 'E', 'T', 'P', 'S', '_', 'l', '2', 'r', 0,
    1119             :   /* 3103 */ 'B', 'Y', 'T', 'E', 'R', 'E', 'V', '_', 'l', '2', 'r', 0,
    1120             :   /* 3115 */ 'B', 'I', 'T', 'R', 'E', 'V', '_', 'l', '2', 'r', 0,
    1121             :   /* 3126 */ 'S', 'E', 'T', 'T', 'W', '_', 'l', '2', 'r', 0,
    1122             :   /* 3136 */ 'S', 'E', 'T', 'R', 'D', 'Y', '_', 'l', '2', 'r', 0,
    1123             :   /* 3147 */ 'C', 'L', 'Z', '_', 'l', '2', 'r', 0,
    1124             :   /* 3155 */ 'S', 'U', 'B', '_', '3', 'r', 0,
    1125             :   /* 3162 */ 'A', 'D', 'D', '_', '3', 'r', 0,
    1126             :   /* 3169 */ 'A', 'N', 'D', '_', '3', 'r', 0,
    1127             :   /* 3176 */ 'S', 'H', 'L', '_', '3', 'r', 0,
    1128             :   /* 3183 */ 'E', 'Q', '_', '3', 'r', 0,
    1129             :   /* 3189 */ 'S', 'H', 'R', '_', '3', 'r', 0,
    1130             :   /* 3196 */ 'O', 'R', '_', '3', 'r', 0,
    1131             :   /* 3202 */ 'T', 'S', 'E', 'T', 'R', '_', '3', 'r', 0,
    1132             :   /* 3211 */ 'L', 'D', '1', '6', 'S', '_', '3', 'r', 0,
    1133             :   /* 3220 */ 'L', 'S', 'S', '_', '3', 'r', 0,
    1134             :   /* 3227 */ 'L', 'D', '8', 'U', '_', '3', 'r', 0,
    1135             :   /* 3235 */ 'L', 'S', 'U', '_', '3', 'r', 0,
    1136             :   /* 3242 */ 'L', 'D', 'W', '_', '3', 'r', 0,
    1137             :   /* 3249 */ 'S', 'T', '1', '6', '_', 'l', '3', 'r', 0,
    1138             :   /* 3258 */ 'S', 'T', '8', '_', 'l', '3', 'r', 0,
    1139             :   /* 3266 */ 'L', 'D', 'A', '1', '6', 'B', '_', 'l', '3', 'r', 0,
    1140             :   /* 3277 */ 'L', 'D', 'A', 'W', 'B', '_', 'l', '3', 'r', 0,
    1141             :   /* 3287 */ 'C', 'R', 'C', '_', 'l', '3', 'r', 0,
    1142             :   /* 3295 */ 'L', 'D', 'A', '1', '6', 'F', '_', 'l', '3', 'r', 0,
    1143             :   /* 3306 */ 'L', 'D', 'A', 'W', 'F', '_', 'l', '3', 'r', 0,
    1144             :   /* 3316 */ 'M', 'U', 'L', '_', 'l', '3', 'r', 0,
    1145             :   /* 3324 */ 'A', 'S', 'H', 'R', '_', 'l', '3', 'r', 0,
    1146             :   /* 3333 */ 'X', 'O', 'R', '_', 'l', '3', 'r', 0,
    1147             :   /* 3341 */ 'R', 'E', 'M', 'S', '_', 'l', '3', 'r', 0,
    1148             :   /* 3350 */ 'D', 'I', 'V', 'S', '_', 'l', '3', 'r', 0,
    1149             :   /* 3359 */ 'R', 'E', 'M', 'U', '_', 'l', '3', 'r', 0,
    1150             :   /* 3368 */ 'D', 'I', 'V', 'U', '_', 'l', '3', 'r', 0,
    1151             :   /* 3377 */ 'S', 'T', 'W', '_', 'l', '3', 'r', 0,
    1152             :   /* 3385 */ 'C', 'R', 'C', '8', '_', 'l', '4', 'r', 0,
    1153             :   /* 3394 */ 'M', 'A', 'C', 'C', 'S', '_', 'l', '4', 'r', 0,
    1154             :   /* 3404 */ 'M', 'A', 'C', 'C', 'U', '_', 'l', '4', 'r', 0,
    1155             :   /* 3414 */ 'L', 'S', 'U', 'B', '_', 'l', '5', 'r', 0,
    1156             :   /* 3423 */ 'L', 'A', 'D', 'D', '_', 'l', '5', 'r', 0,
    1157             :   /* 3432 */ 'L', 'D', 'I', 'V', 'U', '_', 'l', '5', 'r', 0,
    1158             :   /* 3442 */ 'L', 'M', 'U', 'L', '_', 'l', '6', 'r', 0,
    1159             :   /* 3451 */ 'I', 'n', 't', '_', 'M', 'e', 'm', 'B', 'a', 'r', 'r', 'i', 'e', 'r', 0,
    1160             :   /* 3466 */ 'S', 'U', 'B', '_', '2', 'r', 'u', 's', 0,
    1161             :   /* 3475 */ 'A', 'D', 'D', '_', '2', 'r', 'u', 's', 0,
    1162             :   /* 3484 */ 'S', 'H', 'L', '_', '2', 'r', 'u', 's', 0,
    1163             :   /* 3493 */ 'E', 'Q', '_', '2', 'r', 'u', 's', 0,
    1164             :   /* 3501 */ 'S', 'H', 'R', '_', '2', 'r', 'u', 's', 0,
    1165             :   /* 3510 */ 'L', 'D', 'W', '_', '2', 'r', 'u', 's', 0,
    1166             :   /* 3519 */ 'S', 'T', 'W', '_', '2', 'r', 'u', 's', 0,
    1167             :   /* 3528 */ 'L', 'D', 'A', 'W', 'B', '_', 'l', '2', 'r', 'u', 's', 0,
    1168             :   /* 3540 */ 'L', 'D', 'A', 'W', 'F', '_', 'l', '2', 'r', 'u', 's', 0,
    1169             :   /* 3552 */ 'A', 'S', 'H', 'R', '_', 'l', '2', 'r', 'u', 's', 0,
    1170             :   /* 3563 */ 'I', 'N', 'P', 'W', '_', 'l', '2', 'r', 'u', 's', 0,
    1171             :   /* 3574 */ 'O', 'U', 'T', 'P', 'W', '_', 'l', '2', 'r', 'u', 's', 0,
    1172             :   /* 3586 */ 'M', 'K', 'M', 'S', 'K', '_', 'r', 'u', 's', 0,
    1173             :   /* 3596 */ 'G', 'E', 'T', 'R', '_', 'r', 'u', 's', 0,
    1174             :   /* 3605 */ 'C', 'H', 'K', 'C', 'T', '_', 'r', 'u', 's', 0,
    1175             :   /* 3615 */ 'O', 'U', 'T', 'C', 'T', '_', 'r', 'u', 's', 0,
    1176             :   /* 3625 */ 'S', 'E', 'X', 'T', '_', 'r', 'u', 's', 0,
    1177             :   /* 3634 */ 'Z', 'E', 'X', 'T', '_', 'r', 'u', 's', 0,
    1178             : };
    1179             : 
    1180             : extern const unsigned XCoreInstrNameIndices[] = {
    1181             :     1256U, 1479U, 1522U, 1308U, 1289U, 1317U, 1440U, 1127U, 
    1182             :     1142U, 1107U, 1156U, 2128U, 1044U, 1298U, 987U, 2567U, 
    1183             :     1016U, 2410U, 914U, 1613U, 1428U, 2374U, 954U, 2363U, 
    1184             :     1023U, 1689U, 1676U, 1980U, 2234U, 2269U, 1360U, 1407U, 
    1185             :     1380U, 1334U, 853U, 737U, 1452U, 2499U, 2506U, 1465U, 
    1186             :     1472U, 892U, 2058U, 2036U, 1105U, 1254U, 2553U, 1054U, 
    1187             :     2202U, 2096U, 2425U, 2113U, 2385U, 2078U, 2434U, 791U, 
    1188             :     936U, 839U, 817U, 828U, 1036U, 2145U, 1170U, 1187U, 
    1189             :     859U, 743U, 898U, 875U, 2063U, 2042U, 2537U, 1506U, 
    1190             :     2520U, 1489U, 927U, 2221U, 769U, 2175U, 2476U, 809U, 
    1191             :     2352U, 2340U, 2400U, 1211U, 2469U, 2485U, 1354U, 2012U, 
    1192             :     2005U, 1661U, 1654U, 2212U, 1589U, 1008U, 1573U, 979U, 
    1193             :     1581U, 1000U, 1565U, 971U, 1605U, 1597U, 1227U, 1219U, 
    1194             :     846U, 730U, 1445U, 724U, 2492U, 1458U, 2513U, 1716U, 
    1195             :     138U, 1204U, 130U, 1120U, 2461U, 781U, 1260U, 1269U, 
    1196             :     1636U, 1645U, 2089U, 1630U, 1278U, 1962U, 2320U, 2299U, 
    1197             :     2019U, 2579U, 1087U, 2572U, 1069U, 1668U, 1622U, 2444U, 
    1198             :     1967U, 1548U, 1701U, 2293U, 122U, 1538U, 2248U, 3451U, 
    1199             :     1235U, 1242U, 759U, 1248U, 3475U, 3162U, 2954U, 3169U, 
    1200             :     3552U, 3324U, 2719U, 3115U, 100U, 38U, 400U, 240U, 
    1201             :     2609U, 69U, 10U, 90U, 29U, 605U, 478U, 704U, 
    1202             :     568U, 409U, 248U, 615U, 487U, 714U, 577U, 418U, 
    1203             :     256U, 2740U, 3103U, 2893U, 3605U, 1777U, 1943U, 427U, 
    1204             :     264U, 370U, 213U, 3147U, 3385U, 3287U, 1785U, 1824U, 
    1205             :     2635U, 3350U, 3368U, 1834U, 1880U, 2625U, 2709U, 2726U, 
    1206             :     2792U, 2940U, 2733U, 2816U, 338U, 184U, 3493U, 3183U, 
    1207             :     317U, 165U, 360U, 204U, 2700U, 1871U, 3022U, 1759U, 
    1208             :     1896U, 1768U, 1794U, 1814U, 3054U, 3083U, 3596U, 380U, 
    1209             :     222U, 2973U, 2884U, 2902U, 2825U, 2835U, 3072U, 2764U, 
    1210             :     2845U, 3563U, 2855U, 2947U, 2819U, 2646U, 296U, 146U, 
    1211             :     337U, 183U, 348U, 193U, 1888U, 3423U, 3211U, 3227U, 
    1212             :     3266U, 3295U, 58U, 0U, 79U, 2586U, 19U, 3528U, 
    1213             :     3277U, 306U, 155U, 636U, 506U, 3540U, 3306U, 670U, 
    1214             :     537U, 586U, 461U, 1863U, 3432U, 1741U, 1723U, 1845U, 
    1215             :     625U, 111U, 496U, 48U, 648U, 517U, 682U, 548U, 
    1216             :     3510U, 3242U, 3442U, 3220U, 3414U, 3235U, 3394U, 3404U, 
    1217             :     2655U, 2807U, 3586U, 2616U, 3316U, 1123U, 2396U, 3196U, 
    1218             :     2920U, 3615U, 3574U, 2864U, 2982U, 2990U, 2799U, 3341U, 
    1219             :     3359U, 327U, 174U, 3031U, 2664U, 3013U, 595U, 469U, 
    1220             :     2673U, 2784U, 2747U, 1804U, 3063U, 2774U, 3093U, 2964U, 
    1221             :     3136U, 2682U, 444U, 280U, 390U, 231U, 3126U, 2756U, 
    1222             :     2997U, 3625U, 3484U, 3176U, 3501U, 3189U, 2600U, 3249U, 
    1223             :     3258U, 1905U, 1750U, 1732U, 1854U, 659U, 527U, 693U, 
    1224             :     558U, 3519U, 3377U, 3466U, 3155U, 2691U, 2910U, 3042U, 
    1225             :     2929U, 2874U, 3202U, 1952U, 1923U, 1933U, 1913U, 3333U, 
    1226             :     3005U, 3634U, 
    1227             : };
    1228             : 
    1229             : static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
    1230             :   II->InitMCInstrInfo(XCoreInsts, XCoreInstrNameIndices, XCoreInstrNameData, 362);
    1231             : }
    1232             : 
    1233             : } // end llvm namespace
    1234             : #endif // GET_INSTRINFO_MC_DESC
    1235             : 
    1236             : #ifdef GET_INSTRINFO_HEADER
    1237             : #undef GET_INSTRINFO_HEADER
    1238             : namespace llvm {
    1239             : struct XCoreGenInstrInfo : public TargetInstrInfo {
    1240             :   explicit XCoreGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
    1241           0 :   ~XCoreGenInstrInfo() override = default;
    1242             : 
    1243             : };
    1244             : } // end llvm namespace
    1245             : #endif // GET_INSTRINFO_HEADER
    1246             : 
    1247             : #ifdef GET_INSTRINFO_CTOR_DTOR
    1248             : #undef GET_INSTRINFO_CTOR_DTOR
    1249             : namespace llvm {
    1250             : extern const MCInstrDesc XCoreInsts[];
    1251             : extern const unsigned XCoreInstrNameIndices[];
    1252             : extern const char XCoreInstrNameData[];
    1253          80 : XCoreGenInstrInfo::XCoreGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
    1254         160 :   : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
    1255             :   InitMCInstrInfo(XCoreInsts, XCoreInstrNameIndices, XCoreInstrNameData, 362);
    1256          80 : }
    1257             : } // end llvm namespace
    1258             : #endif // GET_INSTRINFO_CTOR_DTOR
    1259             : 
    1260             : #ifdef GET_INSTRINFO_OPERAND_ENUM
    1261             : #undef GET_INSTRINFO_OPERAND_ENUM
    1262             : namespace llvm {
    1263             : namespace XCore {
    1264             : namespace OpName {
    1265             : enum {
    1266             : OPERAND_LAST
    1267             : };
    1268             : } // end namespace OpName
    1269             : } // end namespace XCore
    1270             : } // end namespace llvm
    1271             : #endif //GET_INSTRINFO_OPERAND_ENUM
    1272             : 
    1273             : #ifdef GET_INSTRINFO_NAMED_OPS
    1274             : #undef GET_INSTRINFO_NAMED_OPS
    1275             : namespace llvm {
    1276             : namespace XCore {
    1277             : LLVM_READONLY
    1278             : int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
    1279             :   return -1;
    1280             : }
    1281             : } // end namespace XCore
    1282             : } // end namespace llvm
    1283             : #endif //GET_INSTRINFO_NAMED_OPS
    1284             : 
    1285             : #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
    1286             : #undef GET_INSTRINFO_OPERAND_TYPES_ENUM
    1287             : namespace llvm {
    1288             : namespace XCore {
    1289             : namespace OpTypes {
    1290             : enum OperandType {
    1291             :   InlineJT = 0,
    1292             :   InlineJT32 = 1,
    1293             :   MEMii = 2,
    1294             :   brtarget = 3,
    1295             :   brtarget_neg = 4,
    1296             :   f32imm = 5,
    1297             :   f64imm = 6,
    1298             :   i16imm = 7,
    1299             :   i1imm = 8,
    1300             :   i32imm = 9,
    1301             :   i64imm = 10,
    1302             :   i8imm = 11,
    1303             :   pcrel_imm = 12,
    1304             :   pcrel_imm_neg = 13,
    1305             :   ptype0 = 14,
    1306             :   ptype1 = 15,
    1307             :   ptype2 = 16,
    1308             :   ptype3 = 17,
    1309             :   ptype4 = 18,
    1310             :   ptype5 = 19,
    1311             :   type0 = 20,
    1312             :   type1 = 21,
    1313             :   type2 = 22,
    1314             :   type3 = 23,
    1315             :   type4 = 24,
    1316             :   type5 = 25,
    1317             :   OPERAND_TYPE_LIST_END
    1318             : };
    1319             : } // end namespace OpTypes
    1320             : } // end namespace XCore
    1321             : } // end namespace llvm
    1322             : #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
    1323             : 

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