LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/XCore - XCoreGenInstrInfo.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 6 6 100.0 %
Date: 2017-09-14 15:23:50 Functions: 1 3 33.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Target Instruction Enum Values and Descriptors                             *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_INSTRINFO_ENUM
      10             : #undef GET_INSTRINFO_ENUM
      11             : namespace llvm {
      12             : 
      13             : namespace XCore {
      14             :   enum {
      15             :     PHI = 0,
      16             :     INLINEASM   = 1,
      17             :     CFI_INSTRUCTION     = 2,
      18             :     EH_LABEL    = 3,
      19             :     GC_LABEL    = 4,
      20             :     ANNOTATION_LABEL    = 5,
      21             :     KILL        = 6,
      22             :     EXTRACT_SUBREG      = 7,
      23             :     INSERT_SUBREG       = 8,
      24             :     IMPLICIT_DEF        = 9,
      25             :     SUBREG_TO_REG       = 10,
      26             :     COPY_TO_REGCLASS    = 11,
      27             :     DBG_VALUE   = 12,
      28             :     REG_SEQUENCE        = 13,
      29             :     COPY        = 14,
      30             :     BUNDLE      = 15,
      31             :     LIFETIME_START      = 16,
      32             :     LIFETIME_END        = 17,
      33             :     STACKMAP    = 18,
      34             :     FENTRY_CALL = 19,
      35             :     PATCHPOINT  = 20,
      36             :     LOAD_STACK_GUARD    = 21,
      37             :     STATEPOINT  = 22,
      38             :     LOCAL_ESCAPE        = 23,
      39             :     FAULTING_OP = 24,
      40             :     PATCHABLE_OP        = 25,
      41             :     PATCHABLE_FUNCTION_ENTER    = 26,
      42             :     PATCHABLE_RET       = 27,
      43             :     PATCHABLE_FUNCTION_EXIT     = 28,
      44             :     PATCHABLE_TAIL_CALL = 29,
      45             :     PATCHABLE_EVENT_CALL        = 30,
      46             :     G_ADD       = 31,
      47             :     G_SUB       = 32,
      48             :     G_MUL       = 33,
      49             :     G_SDIV      = 34,
      50             :     G_UDIV      = 35,
      51             :     G_SREM      = 36,
      52             :     G_UREM      = 37,
      53             :     G_AND       = 38,
      54             :     G_OR        = 39,
      55             :     G_XOR       = 40,
      56             :     G_IMPLICIT_DEF      = 41,
      57             :     G_PHI       = 42,
      58             :     G_FRAME_INDEX       = 43,
      59             :     G_GLOBAL_VALUE      = 44,
      60             :     G_EXTRACT   = 45,
      61             :     G_UNMERGE_VALUES    = 46,
      62             :     G_INSERT    = 47,
      63             :     G_MERGE_VALUES      = 48,
      64             :     G_PTRTOINT  = 49,
      65             :     G_INTTOPTR  = 50,
      66             :     G_BITCAST   = 51,
      67             :     G_LOAD      = 52,
      68             :     G_STORE     = 53,
      69             :     G_BRCOND    = 54,
      70             :     G_BRINDIRECT        = 55,
      71             :     G_INTRINSIC = 56,
      72             :     G_INTRINSIC_W_SIDE_EFFECTS  = 57,
      73             :     G_ANYEXT    = 58,
      74             :     G_TRUNC     = 59,
      75             :     G_CONSTANT  = 60,
      76             :     G_FCONSTANT = 61,
      77             :     G_VASTART   = 62,
      78             :     G_VAARG     = 63,
      79             :     G_SEXT      = 64,
      80             :     G_ZEXT      = 65,
      81             :     G_SHL       = 66,
      82             :     G_LSHR      = 67,
      83             :     G_ASHR      = 68,
      84             :     G_ICMP      = 69,
      85             :     G_FCMP      = 70,
      86             :     G_SELECT    = 71,
      87             :     G_UADDE     = 72,
      88             :     G_USUBE     = 73,
      89             :     G_SADDO     = 74,
      90             :     G_SSUBO     = 75,
      91             :     G_UMULO     = 76,
      92             :     G_SMULO     = 77,
      93             :     G_UMULH     = 78,
      94             :     G_SMULH     = 79,
      95             :     G_FADD      = 80,
      96             :     G_FSUB      = 81,
      97             :     G_FMUL      = 82,
      98             :     G_FMA       = 83,
      99             :     G_FDIV      = 84,
     100             :     G_FREM      = 85,
     101             :     G_FPOW      = 86,
     102             :     G_FEXP      = 87,
     103             :     G_FEXP2     = 88,
     104             :     G_FLOG      = 89,
     105             :     G_FLOG2     = 90,
     106             :     G_FNEG      = 91,
     107             :     G_FPEXT     = 92,
     108             :     G_FPTRUNC   = 93,
     109             :     G_FPTOSI    = 94,
     110             :     G_FPTOUI    = 95,
     111             :     G_SITOFP    = 96,
     112             :     G_UITOFP    = 97,
     113             :     G_GEP       = 98,
     114             :     G_PTR_MASK  = 99,
     115             :     G_BR        = 100,
     116             :     G_INSERT_VECTOR_ELT = 101,
     117             :     G_EXTRACT_VECTOR_ELT        = 102,
     118             :     G_SHUFFLE_VECTOR    = 103,
     119             :     ADD_2rus    = 104,
     120             :     ADD_3r      = 105,
     121             :     ADJCALLSTACKDOWN    = 106,
     122             :     ADJCALLSTACKUP      = 107,
     123             :     ANDNOT_2r   = 108,
     124             :     AND_3r      = 109,
     125             :     ASHR_l2rus  = 110,
     126             :     ASHR_l3r    = 111,
     127             :     BAU_1r      = 112,
     128             :     BITREV_l2r  = 113,
     129             :     BLACP_lu10  = 114,
     130             :     BLACP_u10   = 115,
     131             :     BLAT_lu6    = 116,
     132             :     BLAT_u6     = 117,
     133             :     BLA_1r      = 118,
     134             :     BLRB_lu10   = 119,
     135             :     BLRB_u10    = 120,
     136             :     BLRF_lu10   = 121,
     137             :     BLRF_u10    = 122,
     138             :     BRBF_lru6   = 123,
     139             :     BRBF_ru6    = 124,
     140             :     BRBT_lru6   = 125,
     141             :     BRBT_ru6    = 126,
     142             :     BRBU_lu6    = 127,
     143             :     BRBU_u6     = 128,
     144             :     BRFF_lru6   = 129,
     145             :     BRFF_ru6    = 130,
     146             :     BRFT_lru6   = 131,
     147             :     BRFT_ru6    = 132,
     148             :     BRFU_lu6    = 133,
     149             :     BRFU_u6     = 134,
     150             :     BRU_1r      = 135,
     151             :     BR_JT       = 136,
     152             :     BR_JT32     = 137,
     153             :     BYTEREV_l2r = 138,
     154             :     CHKCT_2r    = 139,
     155             :     CHKCT_rus   = 140,
     156             :     CLRE_0R     = 141,
     157             :     CLRPT_1R    = 142,
     158             :     CLRSR_branch_lu6    = 143,
     159             :     CLRSR_branch_u6     = 144,
     160             :     CLRSR_lu6   = 145,
     161             :     CLRSR_u6    = 146,
     162             :     CLZ_l2r     = 147,
     163             :     CRC8_l4r    = 148,
     164             :     CRC_l3r     = 149,
     165             :     DCALL_0R    = 150,
     166             :     DENTSP_0R   = 151,
     167             :     DGETREG_1r  = 152,
     168             :     DIVS_l3r    = 153,
     169             :     DIVU_l3r    = 154,
     170             :     DRESTSP_0R  = 155,
     171             :     DRET_0R     = 156,
     172             :     ECALLF_1r   = 157,
     173             :     ECALLT_1r   = 158,
     174             :     EDU_1r      = 159,
     175             :     EEF_2r      = 160,
     176             :     EET_2r      = 161,
     177             :     EEU_1r      = 162,
     178             :     EH_RETURN   = 163,
     179             :     ENDIN_2r    = 164,
     180             :     ENTSP_lu6   = 165,
     181             :     ENTSP_u6    = 166,
     182             :     EQ_2rus     = 167,
     183             :     EQ_3r       = 168,
     184             :     EXTDP_lu6   = 169,
     185             :     EXTDP_u6    = 170,
     186             :     EXTSP_lu6   = 171,
     187             :     EXTSP_u6    = 172,
     188             :     FRAME_TO_ARGS_OFFSET        = 173,
     189             :     FREER_1r    = 174,
     190             :     FREET_0R    = 175,
     191             :     GETD_l2r    = 176,
     192             :     GETED_0R    = 177,
     193             :     GETET_0R    = 178,
     194             :     GETID_0R    = 179,
     195             :     GETKEP_0R   = 180,
     196             :     GETKSP_0R   = 181,
     197             :     GETN_l2r    = 182,
     198             :     GETPS_l2r   = 183,
     199             :     GETR_rus    = 184,
     200             :     GETSR_lu6   = 185,
     201             :     GETSR_u6    = 186,
     202             :     GETST_2r    = 187,
     203             :     GETTS_2r    = 188,
     204             :     INCT_2r     = 189,
     205             :     INITCP_2r   = 190,
     206             :     INITDP_2r   = 191,
     207             :     INITLR_l2r  = 192,
     208             :     INITPC_2r   = 193,
     209             :     INITSP_2r   = 194,
     210             :     INPW_l2rus  = 195,
     211             :     INSHR_2r    = 196,
     212             :     INT_2r      = 197,
     213             :     IN_2r       = 198,
     214             :     Int_MemBarrier      = 199,
     215             :     KCALL_1r    = 200,
     216             :     KCALL_lu6   = 201,
     217             :     KCALL_u6    = 202,
     218             :     KENTSP_lu6  = 203,
     219             :     KENTSP_u6   = 204,
     220             :     KRESTSP_lu6 = 205,
     221             :     KRESTSP_u6  = 206,
     222             :     KRET_0R     = 207,
     223             :     LADD_l5r    = 208,
     224             :     LD16S_3r    = 209,
     225             :     LD8U_3r     = 210,
     226             :     LDA16B_l3r  = 211,
     227             :     LDA16F_l3r  = 212,
     228             :     LDAPB_lu10  = 213,
     229             :     LDAPB_u10   = 214,
     230             :     LDAPF_lu10  = 215,
     231             :     LDAPF_lu10_ba       = 216,
     232             :     LDAPF_u10   = 217,
     233             :     LDAWB_l2rus = 218,
     234             :     LDAWB_l3r   = 219,
     235             :     LDAWCP_lu6  = 220,
     236             :     LDAWCP_u6   = 221,
     237             :     LDAWDP_lru6 = 222,
     238             :     LDAWDP_ru6  = 223,
     239             :     LDAWFI      = 224,
     240             :     LDAWF_l2rus = 225,
     241             :     LDAWF_l3r   = 226,
     242             :     LDAWSP_lru6 = 227,
     243             :     LDAWSP_ru6  = 228,
     244             :     LDC_lru6    = 229,
     245             :     LDC_ru6     = 230,
     246             :     LDET_0R     = 231,
     247             :     LDIVU_l5r   = 232,
     248             :     LDSED_0R    = 233,
     249             :     LDSPC_0R    = 234,
     250             :     LDSSR_0R    = 235,
     251             :     LDWCP_lru6  = 236,
     252             :     LDWCP_lu10  = 237,
     253             :     LDWCP_ru6   = 238,
     254             :     LDWCP_u10   = 239,
     255             :     LDWDP_lru6  = 240,
     256             :     LDWDP_ru6   = 241,
     257             :     LDWFI       = 242,
     258             :     LDWSP_lru6  = 243,
     259             :     LDWSP_ru6   = 244,
     260             :     LDW_2rus    = 245,
     261             :     LDW_3r      = 246,
     262             :     LMUL_l6r    = 247,
     263             :     LSS_3r      = 248,
     264             :     LSUB_l5r    = 249,
     265             :     LSU_3r      = 250,
     266             :     MACCS_l4r   = 251,
     267             :     MACCU_l4r   = 252,
     268             :     MJOIN_1r    = 253,
     269             :     MKMSK_2r    = 254,
     270             :     MKMSK_rus   = 255,
     271             :     MSYNC_1r    = 256,
     272             :     MUL_l3r     = 257,
     273             :     NEG = 258,
     274             :     NOT = 259,
     275             :     OR_3r       = 260,
     276             :     OUTCT_2r    = 261,
     277             :     OUTCT_rus   = 262,
     278             :     OUTPW_l2rus = 263,
     279             :     OUTSHR_2r   = 264,
     280             :     OUTT_2r     = 265,
     281             :     OUT_2r      = 266,
     282             :     PEEK_2r     = 267,
     283             :     REMS_l3r    = 268,
     284             :     REMU_l3r    = 269,
     285             :     RETSP_lu6   = 270,
     286             :     RETSP_u6    = 271,
     287             :     SELECT_CC   = 272,
     288             :     SETCLK_l2r  = 273,
     289             :     SETCP_1r    = 274,
     290             :     SETC_l2r    = 275,
     291             :     SETC_lru6   = 276,
     292             :     SETC_ru6    = 277,
     293             :     SETDP_1r    = 278,
     294             :     SETD_2r     = 279,
     295             :     SETEV_1r    = 280,
     296             :     SETKEP_0R   = 281,
     297             :     SETN_l2r    = 282,
     298             :     SETPSC_2r   = 283,
     299             :     SETPS_l2r   = 284,
     300             :     SETPT_2r    = 285,
     301             :     SETRDY_l2r  = 286,
     302             :     SETSP_1r    = 287,
     303             :     SETSR_branch_lu6    = 288,
     304             :     SETSR_branch_u6     = 289,
     305             :     SETSR_lu6   = 290,
     306             :     SETSR_u6    = 291,
     307             :     SETTW_l2r   = 292,
     308             :     SETV_1r     = 293,
     309             :     SEXT_2r     = 294,
     310             :     SEXT_rus    = 295,
     311             :     SHL_2rus    = 296,
     312             :     SHL_3r      = 297,
     313             :     SHR_2rus    = 298,
     314             :     SHR_3r      = 299,
     315             :     SSYNC_0r    = 300,
     316             :     ST16_l3r    = 301,
     317             :     ST8_l3r     = 302,
     318             :     STET_0R     = 303,
     319             :     STSED_0R    = 304,
     320             :     STSPC_0R    = 305,
     321             :     STSSR_0R    = 306,
     322             :     STWDP_lru6  = 307,
     323             :     STWDP_ru6   = 308,
     324             :     STWFI       = 309,
     325             :     STWSP_lru6  = 310,
     326             :     STWSP_ru6   = 311,
     327             :     STW_2rus    = 312,
     328             :     STW_l3r     = 313,
     329             :     SUB_2rus    = 314,
     330             :     SUB_3r      = 315,
     331             :     SYNCR_1r    = 316,
     332             :     TESTCT_2r   = 317,
     333             :     TESTLCL_l2r = 318,
     334             :     TESTWCT_2r  = 319,
     335             :     TSETMR_2r   = 320,
     336             :     TSETR_3r    = 321,
     337             :     TSTART_1R   = 322,
     338             :     WAITEF_1R   = 323,
     339             :     WAITET_1R   = 324,
     340             :     WAITEU_0R   = 325,
     341             :     XOR_l3r     = 326,
     342             :     ZEXT_2r     = 327,
     343             :     ZEXT_rus    = 328,
     344             :     INSTRUCTION_LIST_END = 329
     345             :   };
     346             : 
     347             : namespace Sched {
     348             :   enum {
     349             :     NoInstrModel        = 0,
     350             :     SCHED_LIST_END = 1
     351             :   };
     352             : } // end Sched namespace
     353             : } // end XCore namespace
     354             : } // end llvm namespace
     355             : #endif // GET_INSTRINFO_ENUM
     356             : 
     357             : #ifdef GET_INSTRINFO_MC_DESC
     358             : #undef GET_INSTRINFO_MC_DESC
     359             : namespace llvm {
     360             : 
     361             : static const MCPhysReg ImplicitList1[] = { XCore::SP, 0 };
     362             : static const MCPhysReg ImplicitList2[] = { XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR, 0 };
     363             : static const MCPhysReg ImplicitList3[] = { XCore::R11, 0 };
     364             : 
     365             : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     366             : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     367             : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     368             : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     369             : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     370             : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     371             : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     372             : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     373             : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
     374             : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     375             : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     376             : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     377             : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     378             : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     379             : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     380             : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     381             : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     382             : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     383             : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     384             : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     385             : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
     386             : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
     387             : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     388             : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     389             : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     390             : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
     391             : static const MCOperandInfo OperandInfo28[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     392             : static const MCOperandInfo OperandInfo29[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     393             : static const MCOperandInfo OperandInfo30[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     394             : static const MCOperandInfo OperandInfo31[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     395             : static const MCOperandInfo OperandInfo32[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     396             : static const MCOperandInfo OperandInfo33[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     397             : static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     398             : static const MCOperandInfo OperandInfo35[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     399             : static const MCOperandInfo OperandInfo36[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     400             : static const MCOperandInfo OperandInfo37[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     401             : static const MCOperandInfo OperandInfo38[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     402             : static const MCOperandInfo OperandInfo39[] = { { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     403             : static const MCOperandInfo OperandInfo40[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
     404             : static const MCOperandInfo OperandInfo41[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     405             : static const MCOperandInfo OperandInfo42[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     406             : static const MCOperandInfo OperandInfo43[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     407             : static const MCOperandInfo OperandInfo44[] = { { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
     408             : static const MCOperandInfo OperandInfo45[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     409             : static const MCOperandInfo OperandInfo46[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
     410             : 
     411             : extern const MCInstrDesc XCoreInsts[] = {
     412             :   { 0,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
     413             :   { 1,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
     414             :   { 2,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
     415             :   { 3,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
     416             :   { 4,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
     417             :   { 5,  1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
     418             :   { 6,  0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
     419             :   { 7,  3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
     420             :   { 8,  4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
     421             :   { 9,  1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
     422             :   { 10, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
     423             :   { 11, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
     424             :   { 12, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
     425             :   { 13, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #13 = REG_SEQUENCE
     426             :   { 14, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = COPY
     427             :   { 15, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #15 = BUNDLE
     428             :   { 16, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #16 = LIFETIME_START
     429             :   { 17, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_END
     430             :   { 18, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #18 = STACKMAP
     431             :   { 19, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #19 = FENTRY_CALL
     432             :   { 20, 6,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #20 = PATCHPOINT
     433             :   { 21, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #21 = LOAD_STACK_GUARD
     434             :   { 22, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #22 = STATEPOINT
     435             :   { 23, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #23 = LOCAL_ESCAPE
     436             :   { 24, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #24 = FAULTING_OP
     437             :   { 25, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = PATCHABLE_OP
     438             :   { 26, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #26 = PATCHABLE_FUNCTION_ENTER
     439             :   { 27, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #27 = PATCHABLE_RET
     440             :   { 28, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_EXIT
     441             :   { 29, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #29 = PATCHABLE_TAIL_CALL
     442             :   { 30, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #30 = PATCHABLE_EVENT_CALL
     443             :   { 31, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #31 = G_ADD
     444             :   { 32, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = G_SUB
     445             :   { 33, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = G_MUL
     446             :   { 34, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #34 = G_SDIV
     447             :   { 35, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #35 = G_UDIV
     448             :   { 36, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #36 = G_SREM
     449             :   { 37, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #37 = G_UREM
     450             :   { 38, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #38 = G_AND
     451             :   { 39, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #39 = G_OR
     452             :   { 40, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #40 = G_XOR
     453             :   { 41, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_IMPLICIT_DEF
     454             :   { 42, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_PHI
     455             :   { 43, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #43 = G_FRAME_INDEX
     456             :   { 44, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_GLOBAL_VALUE
     457             :   { 45, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #45 = G_EXTRACT
     458             :   { 46, 0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #46 = G_UNMERGE_VALUES
     459             :   { 47, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #47 = G_INSERT
     460             :   { 48, 1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #48 = G_MERGE_VALUES
     461             :   { 49, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_PTRTOINT
     462             :   { 50, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_INTTOPTR
     463             :   { 51, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_BITCAST
     464             :   { 52, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_LOAD
     465             :   { 53, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_STORE
     466             :   { 54, 2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #54 = G_BRCOND
     467             :   { 55, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #55 = G_BRINDIRECT
     468             :   { 56, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #56 = G_INTRINSIC
     469             :   { 57, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #57 = G_INTRINSIC_W_SIDE_EFFECTS
     470             :   { 58, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_ANYEXT
     471             :   { 59, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = G_TRUNC
     472             :   { 60, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #60 = G_CONSTANT
     473             :   { 61, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #61 = G_FCONSTANT
     474             :   { 62, 1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #62 = G_VASTART
     475             :   { 63, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #63 = G_VAARG
     476             :   { 64, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #64 = G_SEXT
     477             :   { 65, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #65 = G_ZEXT
     478             :   { 66, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #66 = G_SHL
     479             :   { 67, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #67 = G_LSHR
     480             :   { 68, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #68 = G_ASHR
     481             :   { 69, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #69 = G_ICMP
     482             :   { 70, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #70 = G_FCMP
     483             :   { 71, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #71 = G_SELECT
     484             :   { 72, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #72 = G_UADDE
     485             :   { 73, 5,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #73 = G_USUBE
     486             :   { 74, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #74 = G_SADDO
     487             :   { 75, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #75 = G_SSUBO
     488             :   { 76, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #76 = G_UMULO
     489             :   { 77, 4,      2,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #77 = G_SMULO
     490             :   { 78, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #78 = G_UMULH
     491             :   { 79, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #79 = G_SMULH
     492             :   { 80, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #80 = G_FADD
     493             :   { 81, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #81 = G_FSUB
     494             :   { 82, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #82 = G_FMUL
     495             :   { 83, 4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #83 = G_FMA
     496             :   { 84, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #84 = G_FDIV
     497             :   { 85, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #85 = G_FREM
     498             :   { 86, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #86 = G_FPOW
     499             :   { 87, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = G_FEXP
     500             :   { 88, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = G_FEXP2
     501             :   { 89, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #89 = G_FLOG
     502             :   { 90, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #90 = G_FLOG2
     503             :   { 91, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #91 = G_FNEG
     504             :   { 92, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #92 = G_FPEXT
     505             :   { 93, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #93 = G_FPTRUNC
     506             :   { 94, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #94 = G_FPTOSI
     507             :   { 95, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #95 = G_FPTOUI
     508             :   { 96, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #96 = G_SITOFP
     509             :   { 97, 2,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #97 = G_UITOFP
     510             :   { 98, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #98 = G_GEP
     511             :   { 99, 3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #99 = G_PTR_MASK
     512             :   { 100,        1,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #100 = G_BR
     513             :   { 101,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #101 = G_INSERT_VECTOR_ELT
     514             :   { 102,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #102 = G_EXTRACT_VECTOR_ELT
     515             :   { 103,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #103 = G_SHUFFLE_VECTOR
     516             :   { 104,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #104 = ADD_2rus
     517             :   { 105,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #105 = ADD_3r
     518             :   { 106,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #106 = ADJCALLSTACKDOWN
     519             :   { 107,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #107 = ADJCALLSTACKUP
     520             :   { 108,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #108 = ANDNOT_2r
     521             :   { 109,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #109 = AND_3r
     522             :   { 110,        3,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #110 = ASHR_l2rus
     523             :   { 111,        3,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #111 = ASHR_l3r
     524             :   { 112,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #112 = BAU_1r
     525             :   { 113,        2,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #113 = BITREV_l2r
     526             :   { 114,        1,      0,      4,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo3, -1 ,nullptr },  // Inst #114 = BLACP_lu10
     527             :   { 115,        1,      0,      2,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo3, -1 ,nullptr },  // Inst #115 = BLACP_u10
     528             :   { 116,        1,      0,      4,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #116 = BLAT_lu6
     529             :   { 117,        1,      0,      2,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #117 = BLAT_u6
     530             :   { 118,        1,      0,      2,      0,      0|(1ULL<<MCID::Call), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo31, -1 ,nullptr },  // Inst #118 = BLA_1r
     531             :   { 119,        1,      0,      4,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #119 = BLRB_lu10
     532             :   { 120,        1,      0,      2,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #120 = BLRB_u10
     533             :   { 121,        1,      0,      4,      0,      0|(1ULL<<MCID::Call), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #121 = BLRF_lu10
     534             :   { 122,        1,      0,      2,      0,      0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #122 = BLRF_u10
     535             :   { 123,        2,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #123 = BRBF_lru6
     536             :   { 124,        2,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #124 = BRBF_ru6
     537             :   { 125,        2,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #125 = BRBT_lru6
     538             :   { 126,        2,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #126 = BRBT_ru6
     539             :   { 127,        1,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #127 = BRBU_lu6
     540             :   { 128,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #128 = BRBU_u6
     541             :   { 129,        2,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #129 = BRFF_lru6
     542             :   { 130,        2,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #130 = BRFF_ru6
     543             :   { 131,        2,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #131 = BRFT_lru6
     544             :   { 132,        2,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #132 = BRFT_ru6
     545             :   { 133,        1,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #133 = BRFU_lu6
     546             :   { 134,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #134 = BRFU_u6
     547             :   { 135,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #135 = BRU_1r
     548             :   { 136,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #136 = BR_JT
     549             :   { 137,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #137 = BR_JT32
     550             :   { 138,        2,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #138 = BYTEREV_l2r
     551             :   { 139,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #139 = CHKCT_2r
     552             :   { 140,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #140 = CHKCT_rus
     553             :   { 141,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #141 = CLRE_0R
     554             :   { 142,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #142 = CLRPT_1R
     555             :   { 143,        1,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #143 = CLRSR_branch_lu6
     556             :   { 144,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #144 = CLRSR_branch_u6
     557             :   { 145,        1,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #145 = CLRSR_lu6
     558             :   { 146,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #146 = CLRSR_u6
     559             :   { 147,        2,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #147 = CLZ_l2r
     560             :   { 148,        5,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #148 = CRC8_l4r
     561             :   { 149,        4,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #149 = CRC_l3r
     562             :   { 150,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #150 = DCALL_0R
     563             :   { 151,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #151 = DENTSP_0R
     564             :   { 152,        1,      1,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #152 = DGETREG_1r
     565             :   { 153,        3,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #153 = DIVS_l3r
     566             :   { 154,        3,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #154 = DIVU_l3r
     567             :   { 155,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #155 = DRESTSP_0R
     568             :   { 156,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #156 = DRET_0R
     569             :   { 157,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #157 = ECALLF_1r
     570             :   { 158,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #158 = ECALLT_1r
     571             :   { 159,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #159 = EDU_1r
     572             :   { 160,        2,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #160 = EEF_2r
     573             :   { 161,        2,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #161 = EET_2r
     574             :   { 162,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #162 = EEU_1r
     575             :   { 163,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #163 = EH_RETURN
     576             :   { 164,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #164 = ENDIN_2r
     577             :   { 165,        1,      0,      4,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #165 = ENTSP_lu6
     578             :   { 166,        1,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #166 = ENTSP_u6
     579             :   { 167,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #167 = EQ_2rus
     580             :   { 168,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #168 = EQ_3r
     581             :   { 169,        1,      0,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #169 = EXTDP_lu6
     582             :   { 170,        1,      0,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #170 = EXTDP_u6
     583             :   { 171,        1,      0,      4,      0,      0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #171 = EXTSP_lu6
     584             :   { 172,        1,      0,      2,      0,      0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #172 = EXTSP_u6
     585             :   { 173,        1,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #173 = FRAME_TO_ARGS_OFFSET
     586             :   { 174,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #174 = FREER_1r
     587             :   { 175,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #175 = FREET_0R
     588             :   { 176,        2,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #176 = GETD_l2r
     589             :   { 177,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #177 = GETED_0R
     590             :   { 178,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #178 = GETET_0R
     591             :   { 179,        0,      0,      2,      0,      0, 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #179 = GETID_0R
     592             :   { 180,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #180 = GETKEP_0R
     593             :   { 181,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #181 = GETKSP_0R
     594             :   { 182,        2,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #182 = GETN_l2r
     595             :   { 183,        2,      1,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #183 = GETPS_l2r
     596             :   { 184,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #184 = GETR_rus
     597             :   { 185,        1,      0,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #185 = GETSR_lu6
     598             :   { 186,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #186 = GETSR_u6
     599             :   { 187,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #187 = GETST_2r
     600             :   { 188,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #188 = GETTS_2r
     601             :   { 189,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #189 = INCT_2r
     602             :   { 190,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #190 = INITCP_2r
     603             :   { 191,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #191 = INITDP_2r
     604             :   { 192,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #192 = INITLR_l2r
     605             :   { 193,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #193 = INITPC_2r
     606             :   { 194,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #194 = INITSP_2r
     607             :   { 195,        3,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #195 = INPW_l2rus
     608             :   { 196,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #196 = INSHR_2r
     609             :   { 197,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #197 = INT_2r
     610             :   { 198,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #198 = IN_2r
     611             :   { 199,        0,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #199 = Int_MemBarrier
     612             :   { 200,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #200 = KCALL_1r
     613             :   { 201,        1,      0,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #201 = KCALL_lu6
     614             :   { 202,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #202 = KCALL_u6
     615             :   { 203,        1,      0,      4,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #203 = KENTSP_lu6
     616             :   { 204,        1,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #204 = KENTSP_u6
     617             :   { 205,        1,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #205 = KRESTSP_lu6
     618             :   { 206,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #206 = KRESTSP_u6
     619             :   { 207,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #207 = KRET_0R
     620             :   { 208,        5,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #208 = LADD_l5r
     621             :   { 209,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #209 = LD16S_3r
     622             :   { 210,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #210 = LD8U_3r
     623             :   { 211,        3,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #211 = LDA16B_l3r
     624             :   { 212,        3,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #212 = LDA16F_l3r
     625             :   { 213,        1,      0,      4,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #213 = LDAPB_lu10
     626             :   { 214,        1,      0,      2,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #214 = LDAPB_u10
     627             :   { 215,        1,      0,      4,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #215 = LDAPF_lu10
     628             :   { 216,        1,      0,      4,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #216 = LDAPF_lu10_ba
     629             :   { 217,        1,      0,      2,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #217 = LDAPF_u10
     630             :   { 218,        3,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #218 = LDAWB_l2rus
     631             :   { 219,        3,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #219 = LDAWB_l3r
     632             :   { 220,        1,      0,      4,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #220 = LDAWCP_lu6
     633             :   { 221,        1,      0,      2,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #221 = LDAWCP_u6
     634             :   { 222,        2,      1,      4,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #222 = LDAWDP_lru6
     635             :   { 223,        2,      1,      2,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #223 = LDAWDP_ru6
     636             :   { 224,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #224 = LDAWFI
     637             :   { 225,        3,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #225 = LDAWF_l2rus
     638             :   { 226,        3,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #226 = LDAWF_l3r
     639             :   { 227,        2,      1,      4,      0,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #227 = LDAWSP_lru6
     640             :   { 228,        2,      1,      2,      0,      0, 0x0ULL, ImplicitList1, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #228 = LDAWSP_ru6
     641             :   { 229,        2,      1,      4,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #229 = LDC_lru6
     642             :   { 230,        2,      1,      2,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #230 = LDC_ru6
     643             :   { 231,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #231 = LDET_0R
     644             :   { 232,        5,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #232 = LDIVU_l5r
     645             :   { 233,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #233 = LDSED_0R
     646             :   { 234,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #234 = LDSPC_0R
     647             :   { 235,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #235 = LDSSR_0R
     648             :   { 236,        2,      1,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #236 = LDWCP_lru6
     649             :   { 237,        1,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #237 = LDWCP_lu10
     650             :   { 238,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #238 = LDWCP_ru6
     651             :   { 239,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList3, OperandInfo3, -1 ,nullptr },  // Inst #239 = LDWCP_u10
     652             :   { 240,        2,      1,      4,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #240 = LDWDP_lru6
     653             :   { 241,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #241 = LDWDP_ru6
     654             :   { 242,        3,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #242 = LDWFI
     655             :   { 243,        2,      1,      4,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList1, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #243 = LDWSP_lru6
     656             :   { 244,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList1, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #244 = LDWSP_ru6
     657             :   { 245,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #245 = LDW_2rus
     658             :   { 246,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #246 = LDW_3r
     659             :   { 247,        6,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #247 = LMUL_l6r
     660             :   { 248,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #248 = LSS_3r
     661             :   { 249,        5,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #249 = LSUB_l5r
     662             :   { 250,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #250 = LSU_3r
     663             :   { 251,        6,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #251 = MACCS_l4r
     664             :   { 252,        6,      2,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #252 = MACCU_l4r
     665             :   { 253,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #253 = MJOIN_1r
     666             :   { 254,        2,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #254 = MKMSK_2r
     667             :   { 255,        2,      1,      2,      0,      0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #255 = MKMSK_rus
     668             :   { 256,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #256 = MSYNC_1r
     669             :   { 257,        3,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #257 = MUL_l3r
     670             :   { 258,        2,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #258 = NEG
     671             :   { 259,        2,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #259 = NOT
     672             :   { 260,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #260 = OR_3r
     673             :   { 261,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #261 = OUTCT_2r
     674             :   { 262,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #262 = OUTCT_rus
     675             :   { 263,        3,      0,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #263 = OUTPW_l2rus
     676             :   { 264,        3,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #264 = OUTSHR_2r
     677             :   { 265,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #265 = OUTT_2r
     678             :   { 266,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #266 = OUT_2r
     679             :   { 267,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #267 = PEEK_2r
     680             :   { 268,        3,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #268 = REMS_l3r
     681             :   { 269,        3,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #269 = REMU_l3r
     682             :   { 270,        1,      0,      4,      0,      0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #270 = RETSP_lu6
     683             :   { 271,        1,      0,      2,      0,      0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #271 = RETSP_u6
     684             :   { 272,        4,      1,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #272 = SELECT_CC
     685             :   { 273,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #273 = SETCLK_l2r
     686             :   { 274,        1,      0,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #274 = SETCP_1r
     687             :   { 275,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #275 = SETC_l2r
     688             :   { 276,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #276 = SETC_lru6
     689             :   { 277,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #277 = SETC_ru6
     690             :   { 278,        1,      0,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #278 = SETDP_1r
     691             :   { 279,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #279 = SETD_2r
     692             :   { 280,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #280 = SETEV_1r
     693             :   { 281,        0,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, nullptr, nullptr, -1 ,nullptr },  // Inst #281 = SETKEP_0R
     694             :   { 282,        2,      0,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #282 = SETN_l2r
     695             :   { 283,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #283 = SETPSC_2r
     696             :   { 284,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #284 = SETPS_l2r
     697             :   { 285,        2,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #285 = SETPT_2r
     698             :   { 286,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #286 = SETRDY_l2r
     699             :   { 287,        1,      0,      2,      0,      0, 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #287 = SETSP_1r
     700             :   { 288,        1,      0,      4,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #288 = SETSR_branch_lu6
     701             :   { 289,        1,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #289 = SETSR_branch_u6
     702             :   { 290,        1,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #290 = SETSR_lu6
     703             :   { 291,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #291 = SETSR_u6
     704             :   { 292,        2,      0,      4,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #292 = SETTW_l2r
     705             :   { 293,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #293 = SETV_1r
     706             :   { 294,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #294 = SEXT_2r
     707             :   { 295,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #295 = SEXT_rus
     708             :   { 296,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #296 = SHL_2rus
     709             :   { 297,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #297 = SHL_3r
     710             :   { 298,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #298 = SHR_2rus
     711             :   { 299,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #299 = SHR_3r
     712             :   { 300,        0,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #300 = SSYNC_0r
     713             :   { 301,        3,      0,      4,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #301 = ST16_l3r
     714             :   { 302,        3,      0,      4,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #302 = ST8_l3r
     715             :   { 303,        0,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #303 = STET_0R
     716             :   { 304,        0,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #304 = STSED_0R
     717             :   { 305,        0,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #305 = STSPC_0R
     718             :   { 306,        0,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr },  // Inst #306 = STSSR_0R
     719             :   { 307,        2,      0,      4,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #307 = STWDP_lru6
     720             :   { 308,        2,      0,      2,      0,      0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #308 = STWDP_ru6
     721             :   { 309,        3,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #309 = STWFI
     722             :   { 310,        2,      0,      4,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList1, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #310 = STWSP_lru6
     723             :   { 311,        2,      0,      2,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList1, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #311 = STWSP_ru6
     724             :   { 312,        3,      0,      2,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #312 = STW_2rus
     725             :   { 313,        3,      0,      4,      0,      0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #313 = STW_l3r
     726             :   { 314,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #314 = SUB_2rus
     727             :   { 315,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #315 = SUB_3r
     728             :   { 316,        1,      0,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #316 = SYNCR_1r
     729             :   { 317,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #317 = TESTCT_2r
     730             :   { 318,        2,      1,      4,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #318 = TESTLCL_l2r
     731             :   { 319,        2,      1,      2,      0,      0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #319 = TESTWCT_2r
     732             :   { 320,        2,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #320 = TSETMR_2r
     733             :   { 321,        3,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #321 = TSETR_3r
     734             :   { 322,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #322 = TSTART_1R
     735             :   { 323,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #323 = WAITEF_1R
     736             :   { 324,        1,      0,      2,      0,      0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #324 = WAITET_1R
     737             :   { 325,        0,      0,      2,      0,      0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #325 = WAITEU_0R
     738             :   { 326,        3,      1,      4,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #326 = XOR_l3r
     739             :   { 327,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #327 = ZEXT_2r
     740             :   { 328,        3,      1,      2,      0,      0, 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #328 = ZEXT_rus
     741             : };
     742             : 
     743             : extern const char XCoreInstrNameData[] = {
     744             :   /* 0 */ 'L', 'D', 'A', 'P', 'B', '_', 'u', '1', '0', 0,
     745             :   /* 10 */ 'B', 'L', 'R', 'B', '_', 'u', '1', '0', 0,
     746             :   /* 19 */ 'L', 'D', 'A', 'P', 'F', '_', 'u', '1', '0', 0,
     747             :   /* 29 */ 'B', 'L', 'R', 'F', '_', 'u', '1', '0', 0,
     748             :   /* 38 */ 'B', 'L', 'A', 'C', 'P', '_', 'u', '1', '0', 0,
     749             :   /* 48 */ 'L', 'D', 'W', 'C', 'P', '_', 'u', '1', '0', 0,
     750             :   /* 58 */ 'L', 'D', 'A', 'P', 'B', '_', 'l', 'u', '1', '0', 0,
     751             :   /* 69 */ 'B', 'L', 'R', 'B', '_', 'l', 'u', '1', '0', 0,
     752             :   /* 79 */ 'L', 'D', 'A', 'P', 'F', '_', 'l', 'u', '1', '0', 0,
     753             :   /* 90 */ 'B', 'L', 'R', 'F', '_', 'l', 'u', '1', '0', 0,
     754             :   /* 100 */ 'B', 'L', 'A', 'C', 'P', '_', 'l', 'u', '1', '0', 0,
     755             :   /* 111 */ 'L', 'D', 'W', 'C', 'P', '_', 'l', 'u', '1', '0', 0,
     756             :   /* 122 */ 'B', 'R', '_', 'J', 'T', '3', '2', 0,
     757             :   /* 130 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
     758             :   /* 138 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
     759             :   /* 146 */ 'K', 'C', 'A', 'L', 'L', '_', 'u', '6', 0,
     760             :   /* 155 */ 'L', 'D', 'A', 'W', 'C', 'P', '_', 'u', '6', 0,
     761             :   /* 165 */ 'E', 'X', 'T', 'D', 'P', '_', 'u', '6', 0,
     762             :   /* 174 */ 'R', 'E', 'T', 'S', 'P', '_', 'u', '6', 0,
     763             :   /* 183 */ 'K', 'E', 'N', 'T', 'S', 'P', '_', 'u', '6', 0,
     764             :   /* 193 */ 'K', 'R', 'E', 'S', 'T', 'S', 'P', '_', 'u', '6', 0,
     765             :   /* 204 */ 'E', 'X', 'T', 'S', 'P', '_', 'u', '6', 0,
     766             :   /* 213 */ 'C', 'L', 'R', 'S', 'R', '_', 'u', '6', 0,
     767             :   /* 222 */ 'G', 'E', 'T', 'S', 'R', '_', 'u', '6', 0,
     768             :   /* 231 */ 'S', 'E', 'T', 'S', 'R', '_', 'u', '6', 0,
     769             :   /* 240 */ 'B', 'L', 'A', 'T', '_', 'u', '6', 0,
     770             :   /* 248 */ 'B', 'R', 'B', 'U', '_', 'u', '6', 0,
     771             :   /* 256 */ 'B', 'R', 'F', 'U', '_', 'u', '6', 0,
     772             :   /* 264 */ 'C', 'L', 'R', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'u', '6', 0,
     773             :   /* 280 */ 'S', 'E', 'T', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'u', '6', 0,
     774             :   /* 296 */ 'K', 'C', 'A', 'L', 'L', '_', 'l', 'u', '6', 0,
     775             :   /* 306 */ 'L', 'D', 'A', 'W', 'C', 'P', '_', 'l', 'u', '6', 0,
     776             :   /* 317 */ 'E', 'X', 'T', 'D', 'P', '_', 'l', 'u', '6', 0,
     777             :   /* 327 */ 'R', 'E', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
     778             :   /* 337 */ 'K', 'E', 'N', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
     779             :   /* 348 */ 'K', 'R', 'E', 'S', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
     780             :   /* 360 */ 'E', 'X', 'T', 'S', 'P', '_', 'l', 'u', '6', 0,
     781             :   /* 370 */ 'C', 'L', 'R', 'S', 'R', '_', 'l', 'u', '6', 0,
     782             :   /* 380 */ 'G', 'E', 'T', 'S', 'R', '_', 'l', 'u', '6', 0,
     783             :   /* 390 */ 'S', 'E', 'T', 'S', 'R', '_', 'l', 'u', '6', 0,
     784             :   /* 400 */ 'B', 'L', 'A', 'T', '_', 'l', 'u', '6', 0,
     785             :   /* 409 */ 'B', 'R', 'B', 'U', '_', 'l', 'u', '6', 0,
     786             :   /* 418 */ 'B', 'R', 'F', 'U', '_', 'l', 'u', '6', 0,
     787             :   /* 427 */ 'C', 'L', 'R', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'l', 'u', '6', 0,
     788             :   /* 444 */ 'S', 'E', 'T', 'S', 'R', '_', 'b', 'r', 'a', 'n', 'c', 'h', '_', 'l', 'u', '6', 0,
     789             :   /* 461 */ 'L', 'D', 'C', '_', 'r', 'u', '6', 0,
     790             :   /* 469 */ 'S', 'E', 'T', 'C', '_', 'r', 'u', '6', 0,
     791             :   /* 478 */ 'B', 'R', 'B', 'F', '_', 'r', 'u', '6', 0,
     792             :   /* 487 */ 'B', 'R', 'F', 'F', '_', 'r', 'u', '6', 0,
     793             :   /* 496 */ 'L', 'D', 'W', 'C', 'P', '_', 'r', 'u', '6', 0,
     794             :   /* 506 */ 'L', 'D', 'A', 'W', 'D', 'P', '_', 'r', 'u', '6', 0,
     795             :   /* 517 */ 'L', 'D', 'W', 'D', 'P', '_', 'r', 'u', '6', 0,
     796             :   /* 527 */ 'S', 'T', 'W', 'D', 'P', '_', 'r', 'u', '6', 0,
     797             :   /* 537 */ 'L', 'D', 'A', 'W', 'S', 'P', '_', 'r', 'u', '6', 0,
     798             :   /* 548 */ 'L', 'D', 'W', 'S', 'P', '_', 'r', 'u', '6', 0,
     799             :   /* 558 */ 'S', 'T', 'W', 'S', 'P', '_', 'r', 'u', '6', 0,
     800             :   /* 568 */ 'B', 'R', 'B', 'T', '_', 'r', 'u', '6', 0,
     801             :   /* 577 */ 'B', 'R', 'F', 'T', '_', 'r', 'u', '6', 0,
     802             :   /* 586 */ 'L', 'D', 'C', '_', 'l', 'r', 'u', '6', 0,
     803             :   /* 595 */ 'S', 'E', 'T', 'C', '_', 'l', 'r', 'u', '6', 0,
     804             :   /* 605 */ 'B', 'R', 'B', 'F', '_', 'l', 'r', 'u', '6', 0,
     805             :   /* 615 */ 'B', 'R', 'F', 'F', '_', 'l', 'r', 'u', '6', 0,
     806             :   /* 625 */ 'L', 'D', 'W', 'C', 'P', '_', 'l', 'r', 'u', '6', 0,
     807             :   /* 636 */ 'L', 'D', 'A', 'W', 'D', 'P', '_', 'l', 'r', 'u', '6', 0,
     808             :   /* 648 */ 'L', 'D', 'W', 'D', 'P', '_', 'l', 'r', 'u', '6', 0,
     809             :   /* 659 */ 'S', 'T', 'W', 'D', 'P', '_', 'l', 'r', 'u', '6', 0,
     810             :   /* 670 */ 'L', 'D', 'A', 'W', 'S', 'P', '_', 'l', 'r', 'u', '6', 0,
     811             :   /* 682 */ 'L', 'D', 'W', 'S', 'P', '_', 'l', 'r', 'u', '6', 0,
     812             :   /* 693 */ 'S', 'T', 'W', 'S', 'P', '_', 'l', 'r', 'u', '6', 0,
     813             :   /* 704 */ 'B', 'R', 'B', 'T', '_', 'l', 'r', 'u', '6', 0,
     814             :   /* 714 */ 'B', 'R', 'F', 'T', '_', 'l', 'r', 'u', '6', 0,
     815             :   /* 724 */ 'G', '_', 'F', 'M', 'A', 0,
     816             :   /* 730 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
     817             :   /* 737 */ 'G', '_', 'S', 'U', 'B', 0,
     818             :   /* 743 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', 0,
     819             :   /* 753 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
     820             :   /* 765 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
     821             :   /* 775 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
     822             :   /* 783 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
     823             :   /* 790 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
     824             :   /* 797 */ 'G', '_', 'A', 'D', 'D', 0,
     825             :   /* 803 */ 'G', '_', 'A', 'N', 'D', 0,
     826             :   /* 809 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
     827             :   /* 822 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
     828             :   /* 831 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
     829             :   /* 848 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
     830             :   /* 856 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
     831             :   /* 869 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
     832             :   /* 877 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
     833             :   /* 884 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
     834             :   /* 897 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
     835             :   /* 905 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
     836             :   /* 915 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
     837             :   /* 930 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
     838             :   /* 945 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
     839             :   /* 952 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     840             :   /* 967 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
     841             :   /* 981 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
     842             :   /* 995 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
     843             :   /* 1002 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
     844             :   /* 1010 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
     845             :   /* 1018 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
     846             :   /* 1026 */ 'L', 'D', 'A', 'W', 'F', 'I', 0,
     847             :   /* 1033 */ 'L', 'D', 'W', 'F', 'I', 0,
     848             :   /* 1039 */ 'S', 'T', 'W', 'F', 'I', 0,
     849             :   /* 1045 */ 'G', '_', 'P', 'H', 'I', 0,
     850             :   /* 1051 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
     851             :   /* 1060 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
     852             :   /* 1069 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
     853             :   /* 1080 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
     854             :   /* 1089 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
     855             :   /* 1098 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
     856             :   /* 1115 */ 'G', '_', 'S', 'H', 'L', 0,
     857             :   /* 1121 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
     858             :   /* 1141 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
     859             :   /* 1162 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
     860             :   /* 1174 */ 'K', 'I', 'L', 'L', 0,
     861             :   /* 1179 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
     862             :   /* 1186 */ 'G', '_', 'M', 'U', 'L', 0,
     863             :   /* 1192 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
     864             :   /* 1199 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
     865             :   /* 1206 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
     866             :   /* 1213 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
     867             :   /* 1223 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
     868             :   /* 1239 */ 'E', 'H', '_', 'R', 'E', 'T', 'U', 'R', 'N', 0,
     869             :   /* 1249 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
     870             :   /* 1266 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
     871             :   /* 1274 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
     872             :   /* 1282 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
     873             :   /* 1290 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
     874             :   /* 1298 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
     875             :   /* 1307 */ 'G', '_', 'G', 'E', 'P', 0,
     876             :   /* 1313 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
     877             :   /* 1322 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
     878             :   /* 1331 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
     879             :   /* 1338 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
     880             :   /* 1345 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
     881             :   /* 1358 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
     882             :   /* 1370 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
     883             :   /* 1385 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
     884             :   /* 1392 */ 'L', 'D', 'S', 'P', 'C', '_', '0', 'R', 0,
     885             :   /* 1401 */ 'S', 'T', 'S', 'P', 'C', '_', '0', 'R', 0,
     886             :   /* 1410 */ 'L', 'D', 'S', 'E', 'D', '_', '0', 'R', 0,
     887             :   /* 1419 */ 'S', 'T', 'S', 'E', 'D', '_', '0', 'R', 0,
     888             :   /* 1428 */ 'G', 'E', 'T', 'E', 'D', '_', '0', 'R', 0,
     889             :   /* 1437 */ 'G', 'E', 'T', 'I', 'D', '_', '0', 'R', 0,
     890             :   /* 1446 */ 'C', 'L', 'R', 'E', '_', '0', 'R', 0,
     891             :   /* 1454 */ 'D', 'C', 'A', 'L', 'L', '_', '0', 'R', 0,
     892             :   /* 1463 */ 'G', 'E', 'T', 'K', 'E', 'P', '_', '0', 'R', 0,
     893             :   /* 1473 */ 'S', 'E', 'T', 'K', 'E', 'P', '_', '0', 'R', 0,
     894             :   /* 1483 */ 'G', 'E', 'T', 'K', 'S', 'P', '_', '0', 'R', 0,
     895             :   /* 1493 */ 'D', 'E', 'N', 'T', 'S', 'P', '_', '0', 'R', 0,
     896             :   /* 1503 */ 'D', 'R', 'E', 'S', 'T', 'S', 'P', '_', '0', 'R', 0,
     897             :   /* 1514 */ 'L', 'D', 'S', 'S', 'R', '_', '0', 'R', 0,
     898             :   /* 1523 */ 'S', 'T', 'S', 'S', 'R', '_', '0', 'R', 0,
     899             :   /* 1532 */ 'L', 'D', 'E', 'T', '_', '0', 'R', 0,
     900             :   /* 1540 */ 'F', 'R', 'E', 'E', 'T', '_', '0', 'R', 0,
     901             :   /* 1549 */ 'D', 'R', 'E', 'T', '_', '0', 'R', 0,
     902             :   /* 1557 */ 'K', 'R', 'E', 'T', '_', '0', 'R', 0,
     903             :   /* 1565 */ 'G', 'E', 'T', 'E', 'T', '_', '0', 'R', 0,
     904             :   /* 1574 */ 'S', 'T', 'E', 'T', '_', '0', 'R', 0,
     905             :   /* 1582 */ 'W', 'A', 'I', 'T', 'E', 'U', '_', '0', 'R', 0,
     906             :   /* 1592 */ 'W', 'A', 'I', 'T', 'E', 'F', '_', '1', 'R', 0,
     907             :   /* 1602 */ 'W', 'A', 'I', 'T', 'E', 'T', '_', '1', 'R', 0,
     908             :   /* 1612 */ 'C', 'L', 'R', 'P', 'T', '_', '1', 'R', 0,
     909             :   /* 1621 */ 'T', 'S', 'T', 'A', 'R', 'T', '_', '1', 'R', 0,
     910             :   /* 1631 */ 'G', '_', 'B', 'R', 0,
     911             :   /* 1636 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
     912             :   /* 1661 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
     913             :   /* 1668 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
     914             :   /* 1675 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
     915             :   /* 1692 */ 'G', '_', 'X', 'O', 'R', 0,
     916             :   /* 1698 */ 'G', '_', 'O', 'R', 0,
     917             :   /* 1703 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
     918             :   /* 1714 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
     919             :   /* 1731 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
     920             :   /* 1746 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
     921             :   /* 1763 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
     922             :   /* 1790 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
     923             :   /* 1800 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
     924             :   /* 1809 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
     925             :   /* 1822 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
     926             :   /* 1836 */ 'F', 'R', 'A', 'M', 'E', '_', 'T', 'O', '_', 'A', 'R', 'G', 'S', '_', 'O', 'F', 'F', 'S', 'E', 'T', 0,
     927             :   /* 1857 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
     928             :   /* 1881 */ 'B', 'R', '_', 'J', 'T', 0,
     929             :   /* 1887 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
     930             :   /* 1908 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
     931             :   /* 1928 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
     932             :   /* 1940 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
     933             :   /* 1951 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
     934             :   /* 1962 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
     935             :   /* 1973 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
     936             :   /* 1984 */ 'N', 'O', 'T', 0,
     937             :   /* 1988 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
     938             :   /* 1998 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
     939             :   /* 2013 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
     940             :   /* 2022 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
     941             :   /* 2032 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
     942             :   /* 2040 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
     943             :   /* 2047 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
     944             :   /* 2056 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
     945             :   /* 2063 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
     946             :   /* 2070 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
     947             :   /* 2077 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
     948             :   /* 2084 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
     949             :   /* 2091 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
     950             :   /* 2105 */ 'C', 'O', 'P', 'Y', 0,
     951             :   /* 2110 */ 'L', 'D', 'A', 'P', 'F', '_', 'l', 'u', '1', '0', '_', 'b', 'a', 0,
     952             :   /* 2124 */ 'S', 'S', 'Y', 'N', 'C', '_', '0', 'r', 0,
     953             :   /* 2133 */ 'B', 'L', 'A', '_', '1', 'r', 0,
     954             :   /* 2140 */ 'M', 'S', 'Y', 'N', 'C', '_', '1', 'r', 0,
     955             :   /* 2149 */ 'E', 'C', 'A', 'L', 'L', 'F', '_', '1', 'r', 0,
     956             :   /* 2159 */ 'D', 'G', 'E', 'T', 'R', 'E', 'G', '_', '1', 'r', 0,
     957             :   /* 2170 */ 'K', 'C', 'A', 'L', 'L', '_', '1', 'r', 0,
     958             :   /* 2179 */ 'M', 'J', 'O', 'I', 'N', '_', '1', 'r', 0,
     959             :   /* 2188 */ 'S', 'E', 'T', 'C', 'P', '_', '1', 'r', 0,
     960             :   /* 2197 */ 'S', 'E', 'T', 'D', 'P', '_', '1', 'r', 0,
     961             :   /* 2206 */ 'S', 'E', 'T', 'S', 'P', '_', '1', 'r', 0,
     962             :   /* 2215 */ 'S', 'Y', 'N', 'C', 'R', '_', '1', 'r', 0,
     963             :   /* 2224 */ 'F', 'R', 'E', 'E', 'R', '_', '1', 'r', 0,
     964             :   /* 2233 */ 'E', 'C', 'A', 'L', 'L', 'T', '_', '1', 'r', 0,
     965             :   /* 2243 */ 'B', 'A', 'U', '_', '1', 'r', 0,
     966             :   /* 2250 */ 'E', 'D', 'U', '_', '1', 'r', 0,
     967             :   /* 2257 */ 'E', 'E', 'U', '_', '1', 'r', 0,
     968             :   /* 2264 */ 'B', 'R', 'U', '_', '1', 'r', 0,
     969             :   /* 2271 */ 'S', 'E', 'T', 'E', 'V', '_', '1', 'r', 0,
     970             :   /* 2280 */ 'S', 'E', 'T', 'V', '_', '1', 'r', 0,
     971             :   /* 2288 */ 'I', 'N', 'I', 'T', 'P', 'C', '_', '2', 'r', 0,
     972             :   /* 2298 */ 'S', 'E', 'T', 'P', 'S', 'C', '_', '2', 'r', 0,
     973             :   /* 2308 */ 'S', 'E', 'T', 'D', '_', '2', 'r', 0,
     974             :   /* 2316 */ 'E', 'E', 'F', '_', '2', 'r', 0,
     975             :   /* 2323 */ 'P', 'E', 'E', 'K', '_', '2', 'r', 0,
     976             :   /* 2331 */ 'M', 'K', 'M', 'S', 'K', '_', '2', 'r', 0,
     977             :   /* 2340 */ 'E', 'N', 'D', 'I', 'N', '_', '2', 'r', 0,
     978             :   /* 2349 */ 'I', 'N', 'I', 'T', 'C', 'P', '_', '2', 'r', 0,
     979             :   /* 2359 */ 'I', 'N', 'I', 'T', 'D', 'P', '_', '2', 'r', 0,
     980             :   /* 2369 */ 'I', 'N', 'I', 'T', 'S', 'P', '_', '2', 'r', 0,
     981             :   /* 2379 */ 'I', 'N', 'S', 'H', 'R', '_', '2', 'r', 0,
     982             :   /* 2388 */ 'O', 'U', 'T', 'S', 'H', 'R', '_', '2', 'r', 0,
     983             :   /* 2398 */ 'T', 'S', 'E', 'T', 'M', 'R', '_', '2', 'r', 0,
     984             :   /* 2408 */ 'G', 'E', 'T', 'T', 'S', '_', '2', 'r', 0,
     985             :   /* 2417 */ 'C', 'H', 'K', 'C', 'T', '_', '2', 'r', 0,
     986             :   /* 2426 */ 'I', 'N', 'C', 'T', '_', '2', 'r', 0,
     987             :   /* 2434 */ 'T', 'E', 'S', 'T', 'C', 'T', '_', '2', 'r', 0,
     988             :   /* 2444 */ 'O', 'U', 'T', 'C', 'T', '_', '2', 'r', 0,
     989             :   /* 2453 */ 'T', 'E', 'S', 'T', 'W', 'C', 'T', '_', '2', 'r', 0,
     990             :   /* 2464 */ 'E', 'E', 'T', '_', '2', 'r', 0,
     991             :   /* 2471 */ 'I', 'N', 'T', '_', '2', 'r', 0,
     992             :   /* 2478 */ 'A', 'N', 'D', 'N', 'O', 'T', '_', '2', 'r', 0,
     993             :   /* 2488 */ 'S', 'E', 'T', 'P', 'T', '_', '2', 'r', 0,
     994             :   /* 2497 */ 'G', 'E', 'T', 'S', 'T', '_', '2', 'r', 0,
     995             :   /* 2506 */ 'O', 'U', 'T', 'T', '_', '2', 'r', 0,
     996             :   /* 2514 */ 'O', 'U', 'T', '_', '2', 'r', 0,
     997             :   /* 2521 */ 'S', 'E', 'X', 'T', '_', '2', 'r', 0,
     998             :   /* 2529 */ 'Z', 'E', 'X', 'T', '_', '2', 'r', 0,
     999             :   /* 2537 */ 'S', 'E', 'T', 'C', '_', 'l', '2', 'r', 0,
    1000             :   /* 2546 */ 'G', 'E', 'T', 'D', '_', 'l', '2', 'r', 0,
    1001             :   /* 2555 */ 'S', 'E', 'T', 'C', 'L', 'K', '_', 'l', '2', 'r', 0,
    1002             :   /* 2566 */ 'T', 'E', 'S', 'T', 'L', 'C', 'L', '_', 'l', '2', 'r', 0,
    1003             :   /* 2578 */ 'G', 'E', 'T', 'N', '_', 'l', '2', 'r', 0,
    1004             :   /* 2587 */ 'S', 'E', 'T', 'N', '_', 'l', '2', 'r', 0,
    1005             :   /* 2596 */ 'I', 'N', 'I', 'T', 'L', 'R', '_', 'l', '2', 'r', 0,
    1006             :   /* 2607 */ 'G', 'E', 'T', 'P', 'S', '_', 'l', '2', 'r', 0,
    1007             :   /* 2617 */ 'S', 'E', 'T', 'P', 'S', '_', 'l', '2', 'r', 0,
    1008             :   /* 2627 */ 'B', 'Y', 'T', 'E', 'R', 'E', 'V', '_', 'l', '2', 'r', 0,
    1009             :   /* 2639 */ 'B', 'I', 'T', 'R', 'E', 'V', '_', 'l', '2', 'r', 0,
    1010             :   /* 2650 */ 'S', 'E', 'T', 'T', 'W', '_', 'l', '2', 'r', 0,
    1011             :   /* 2660 */ 'S', 'E', 'T', 'R', 'D', 'Y', '_', 'l', '2', 'r', 0,
    1012             :   /* 2671 */ 'C', 'L', 'Z', '_', 'l', '2', 'r', 0,
    1013             :   /* 2679 */ 'S', 'U', 'B', '_', '3', 'r', 0,
    1014             :   /* 2686 */ 'A', 'D', 'D', '_', '3', 'r', 0,
    1015             :   /* 2693 */ 'A', 'N', 'D', '_', '3', 'r', 0,
    1016             :   /* 2700 */ 'S', 'H', 'L', '_', '3', 'r', 0,
    1017             :   /* 2707 */ 'E', 'Q', '_', '3', 'r', 0,
    1018             :   /* 2713 */ 'S', 'H', 'R', '_', '3', 'r', 0,
    1019             :   /* 2720 */ 'O', 'R', '_', '3', 'r', 0,
    1020             :   /* 2726 */ 'T', 'S', 'E', 'T', 'R', '_', '3', 'r', 0,
    1021             :   /* 2735 */ 'L', 'D', '1', '6', 'S', '_', '3', 'r', 0,
    1022             :   /* 2744 */ 'L', 'S', 'S', '_', '3', 'r', 0,
    1023             :   /* 2751 */ 'L', 'D', '8', 'U', '_', '3', 'r', 0,
    1024             :   /* 2759 */ 'L', 'S', 'U', '_', '3', 'r', 0,
    1025             :   /* 2766 */ 'L', 'D', 'W', '_', '3', 'r', 0,
    1026             :   /* 2773 */ 'S', 'T', '1', '6', '_', 'l', '3', 'r', 0,
    1027             :   /* 2782 */ 'S', 'T', '8', '_', 'l', '3', 'r', 0,
    1028             :   /* 2790 */ 'L', 'D', 'A', '1', '6', 'B', '_', 'l', '3', 'r', 0,
    1029             :   /* 2801 */ 'L', 'D', 'A', 'W', 'B', '_', 'l', '3', 'r', 0,
    1030             :   /* 2811 */ 'C', 'R', 'C', '_', 'l', '3', 'r', 0,
    1031             :   /* 2819 */ 'L', 'D', 'A', '1', '6', 'F', '_', 'l', '3', 'r', 0,
    1032             :   /* 2830 */ 'L', 'D', 'A', 'W', 'F', '_', 'l', '3', 'r', 0,
    1033             :   /* 2840 */ 'M', 'U', 'L', '_', 'l', '3', 'r', 0,
    1034             :   /* 2848 */ 'A', 'S', 'H', 'R', '_', 'l', '3', 'r', 0,
    1035             :   /* 2857 */ 'X', 'O', 'R', '_', 'l', '3', 'r', 0,
    1036             :   /* 2865 */ 'R', 'E', 'M', 'S', '_', 'l', '3', 'r', 0,
    1037             :   /* 2874 */ 'D', 'I', 'V', 'S', '_', 'l', '3', 'r', 0,
    1038             :   /* 2883 */ 'R', 'E', 'M', 'U', '_', 'l', '3', 'r', 0,
    1039             :   /* 2892 */ 'D', 'I', 'V', 'U', '_', 'l', '3', 'r', 0,
    1040             :   /* 2901 */ 'S', 'T', 'W', '_', 'l', '3', 'r', 0,
    1041             :   /* 2909 */ 'C', 'R', 'C', '8', '_', 'l', '4', 'r', 0,
    1042             :   /* 2918 */ 'M', 'A', 'C', 'C', 'S', '_', 'l', '4', 'r', 0,
    1043             :   /* 2928 */ 'M', 'A', 'C', 'C', 'U', '_', 'l', '4', 'r', 0,
    1044             :   /* 2938 */ 'L', 'S', 'U', 'B', '_', 'l', '5', 'r', 0,
    1045             :   /* 2947 */ 'L', 'A', 'D', 'D', '_', 'l', '5', 'r', 0,
    1046             :   /* 2956 */ 'L', 'D', 'I', 'V', 'U', '_', 'l', '5', 'r', 0,
    1047             :   /* 2966 */ 'L', 'M', 'U', 'L', '_', 'l', '6', 'r', 0,
    1048             :   /* 2975 */ 'I', 'n', 't', '_', 'M', 'e', 'm', 'B', 'a', 'r', 'r', 'i', 'e', 'r', 0,
    1049             :   /* 2990 */ 'S', 'U', 'B', '_', '2', 'r', 'u', 's', 0,
    1050             :   /* 2999 */ 'A', 'D', 'D', '_', '2', 'r', 'u', 's', 0,
    1051             :   /* 3008 */ 'S', 'H', 'L', '_', '2', 'r', 'u', 's', 0,
    1052             :   /* 3017 */ 'E', 'Q', '_', '2', 'r', 'u', 's', 0,
    1053             :   /* 3025 */ 'S', 'H', 'R', '_', '2', 'r', 'u', 's', 0,
    1054             :   /* 3034 */ 'L', 'D', 'W', '_', '2', 'r', 'u', 's', 0,
    1055             :   /* 3043 */ 'S', 'T', 'W', '_', '2', 'r', 'u', 's', 0,
    1056             :   /* 3052 */ 'L', 'D', 'A', 'W', 'B', '_', 'l', '2', 'r', 'u', 's', 0,
    1057             :   /* 3064 */ 'L', 'D', 'A', 'W', 'F', '_', 'l', '2', 'r', 'u', 's', 0,
    1058             :   /* 3076 */ 'A', 'S', 'H', 'R', '_', 'l', '2', 'r', 'u', 's', 0,
    1059             :   /* 3087 */ 'I', 'N', 'P', 'W', '_', 'l', '2', 'r', 'u', 's', 0,
    1060             :   /* 3098 */ 'O', 'U', 'T', 'P', 'W', '_', 'l', '2', 'r', 'u', 's', 0,
    1061             :   /* 3110 */ 'M', 'K', 'M', 'S', 'K', '_', 'r', 'u', 's', 0,
    1062             :   /* 3120 */ 'G', 'E', 'T', 'R', '_', 'r', 'u', 's', 0,
    1063             :   /* 3129 */ 'C', 'H', 'K', 'C', 'T', '_', 'r', 'u', 's', 0,
    1064             :   /* 3139 */ 'O', 'U', 'T', 'C', 'T', '_', 'r', 'u', 's', 0,
    1065             :   /* 3149 */ 'S', 'E', 'X', 'T', '_', 'r', 'u', 's', 0,
    1066             :   /* 3158 */ 'Z', 'E', 'X', 'T', '_', 'r', 'u', 's', 0,
    1067             : };
    1068             : 
    1069             : extern const unsigned XCoreInstrNameIndices[] = {
    1070             :     1047U, 1213U, 1223U, 1089U, 1080U, 1098U, 1174U, 952U, 
    1071             :     967U, 932U, 981U, 1746U, 905U, 856U, 2105U, 877U, 
    1072             :     1998U, 809U, 1298U, 1162U, 1962U, 831U, 1951U, 884U, 
    1073             :     1358U, 1345U, 1636U, 1822U, 1857U, 1121U, 1141U, 797U, 
    1074             :     737U, 1186U, 2070U, 2077U, 1199U, 1206U, 803U, 1698U, 
    1075             :     1692U, 930U, 1045U, 2091U, 915U, 1790U, 1714U, 2013U, 
    1076             :     1731U, 1973U, 1703U, 2022U, 783U, 897U, 822U, 1809U, 
    1077             :     753U, 1763U, 2047U, 775U, 1940U, 1928U, 1988U, 1002U, 
    1078             :     2040U, 2056U, 1115U, 1668U, 1661U, 1338U, 1331U, 1800U, 
    1079             :     869U, 848U, 1274U, 1266U, 1290U, 1282U, 1018U, 1010U, 
    1080             :     790U, 730U, 1179U, 724U, 2063U, 1192U, 2084U, 1385U, 
    1081             :     138U, 995U, 130U, 945U, 2032U, 765U, 1051U, 1060U, 
    1082             :     1313U, 1322U, 1307U, 1069U, 1631U, 1908U, 1887U, 1675U, 
    1083             :     2999U, 2686U, 1249U, 1370U, 2478U, 2693U, 3076U, 2848U, 
    1084             :     2243U, 2639U, 100U, 38U, 400U, 240U, 2133U, 69U, 
    1085             :     10U, 90U, 29U, 605U, 478U, 704U, 568U, 409U, 
    1086             :     248U, 615U, 487U, 714U, 577U, 418U, 256U, 2264U, 
    1087             :     1881U, 122U, 2627U, 2417U, 3129U, 1446U, 1612U, 427U, 
    1088             :     264U, 370U, 213U, 2671U, 2909U, 2811U, 1454U, 1493U, 
    1089             :     2159U, 2874U, 2892U, 1503U, 1549U, 2149U, 2233U, 2250U, 
    1090             :     2316U, 2464U, 2257U, 1239U, 2340U, 338U, 184U, 3017U, 
    1091             :     2707U, 317U, 165U, 360U, 204U, 1836U, 2224U, 1540U, 
    1092             :     2546U, 1428U, 1565U, 1437U, 1463U, 1483U, 2578U, 2607U, 
    1093             :     3120U, 380U, 222U, 2497U, 2408U, 2426U, 2349U, 2359U, 
    1094             :     2596U, 2288U, 2369U, 3087U, 2379U, 2471U, 2343U, 2975U, 
    1095             :     2170U, 296U, 146U, 337U, 183U, 348U, 193U, 1557U, 
    1096             :     2947U, 2735U, 2751U, 2790U, 2819U, 58U, 0U, 79U, 
    1097             :     2110U, 19U, 3052U, 2801U, 306U, 155U, 636U, 506U, 
    1098             :     1026U, 3064U, 2830U, 670U, 537U, 586U, 461U, 1532U, 
    1099             :     2956U, 1410U, 1392U, 1514U, 625U, 111U, 496U, 48U, 
    1100             :     648U, 517U, 1033U, 682U, 548U, 3034U, 2766U, 2966U, 
    1101             :     2744U, 2938U, 2759U, 2918U, 2928U, 2179U, 2331U, 3110U, 
    1102             :     2140U, 2840U, 948U, 1984U, 2720U, 2444U, 3139U, 3098U, 
    1103             :     2388U, 2506U, 2514U, 2323U, 2865U, 2883U, 327U, 174U, 
    1104             :     743U, 2555U, 2188U, 2537U, 595U, 469U, 2197U, 2308U, 
    1105             :     2271U, 1473U, 2587U, 2298U, 2617U, 2488U, 2660U, 2206U, 
    1106             :     444U, 280U, 390U, 231U, 2650U, 2280U, 2521U, 3149U, 
    1107             :     3008U, 2700U, 3025U, 2713U, 2124U, 2773U, 2782U, 1574U, 
    1108             :     1419U, 1401U, 1523U, 659U, 527U, 1039U, 693U, 558U, 
    1109             :     3043U, 2901U, 2990U, 2679U, 2215U, 2434U, 2566U, 2453U, 
    1110             :     2398U, 2726U, 1621U, 1592U, 1602U, 1582U, 2857U, 2529U, 
    1111             :     3158U, 
    1112             : };
    1113             : 
    1114             : static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
    1115          81 :   II->InitMCInstrInfo(XCoreInsts, XCoreInstrNameIndices, XCoreInstrNameData, 329);
    1116             : }
    1117             : 
    1118             : } // end llvm namespace
    1119             : #endif // GET_INSTRINFO_MC_DESC
    1120             : 
    1121             : #ifdef GET_INSTRINFO_HEADER
    1122             : #undef GET_INSTRINFO_HEADER
    1123             : namespace llvm {
    1124             : struct XCoreGenInstrInfo : public TargetInstrInfo {
    1125             :   explicit XCoreGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
    1126          78 :   ~XCoreGenInstrInfo() override = default;
    1127             : };
    1128             : } // end llvm namespace
    1129             : #endif // GET_INSTRINFO_HEADER
    1130             : 
    1131             : #ifdef GET_INSTRINFO_CTOR_DTOR
    1132             : #undef GET_INSTRINFO_CTOR_DTOR
    1133             : namespace llvm {
    1134             : extern const MCInstrDesc XCoreInsts[];
    1135             : extern const unsigned XCoreInstrNameIndices[];
    1136             : extern const char XCoreInstrNameData[];
    1137          80 : XCoreGenInstrInfo::XCoreGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
    1138         160 :   : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
    1139         160 :   InitMCInstrInfo(XCoreInsts, XCoreInstrNameIndices, XCoreInstrNameData, 329);
    1140          80 : }
    1141             : } // end llvm namespace
    1142             : #endif // GET_INSTRINFO_CTOR_DTOR
    1143             : 
    1144             : #ifdef GET_INSTRINFO_OPERAND_ENUM
    1145             : #undef GET_INSTRINFO_OPERAND_ENUM
    1146             : namespace llvm {
    1147             : namespace XCore {
    1148             : namespace OpName {
    1149             : enum {
    1150             : OPERAND_LAST
    1151             : };
    1152             : } // end namespace OpName
    1153             : } // end namespace XCore
    1154             : } // end namespace llvm
    1155             : #endif //GET_INSTRINFO_OPERAND_ENUM
    1156             : 
    1157             : #ifdef GET_INSTRINFO_NAMED_OPS
    1158             : #undef GET_INSTRINFO_NAMED_OPS
    1159             : namespace llvm {
    1160             : namespace XCore {
    1161             : LLVM_READONLY
    1162             : int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
    1163             :   return -1;
    1164             : }
    1165             : } // end namespace XCore
    1166             : } // end namespace llvm
    1167             : #endif //GET_INSTRINFO_NAMED_OPS
    1168             : 
    1169             : #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
    1170             : #undef GET_INSTRINFO_OPERAND_TYPES_ENUM
    1171             : namespace llvm {
    1172             : namespace XCore {
    1173             : namespace OpTypes {
    1174             : enum OperandType {
    1175             :   InlineJT = 0,
    1176             :   InlineJT32 = 1,
    1177             :   MEMii = 2,
    1178             :   brtarget = 3,
    1179             :   brtarget_neg = 4,
    1180             :   f32imm = 5,
    1181             :   f64imm = 6,
    1182             :   i16imm = 7,
    1183             :   i1imm = 8,
    1184             :   i32imm = 9,
    1185             :   i64imm = 10,
    1186             :   i8imm = 11,
    1187             :   pcrel_imm = 12,
    1188             :   pcrel_imm_neg = 13,
    1189             :   type0 = 14,
    1190             :   type1 = 15,
    1191             :   type2 = 16,
    1192             :   type3 = 17,
    1193             :   type4 = 18,
    1194             :   type5 = 19,
    1195             :   OPERAND_TYPE_LIST_END
    1196             : };
    1197             : } // end namespace OpTypes
    1198             : } // end namespace XCore
    1199             : } // end namespace llvm
    1200             : #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
    1201             : 

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