LCOV - code coverage report
Current view: top level - include/llvm/CodeGen - FunctionLoweringInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 32 32 100.0 %
Date: 2017-09-14 15:23:50 Functions: 7 8 87.5 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen ---===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This implements routines for translating functions from LLVM IR into
      11             : // Machine IR.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
      16             : #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
      17             : 
      18             : #include "llvm/ADT/APInt.h"
      19             : #include "llvm/ADT/DenseMap.h"
      20             : #include "llvm/ADT/IndexedMap.h"
      21             : #include "llvm/ADT/Optional.h"
      22             : #include "llvm/ADT/SmallPtrSet.h"
      23             : #include "llvm/ADT/SmallVector.h"
      24             : #include "llvm/CodeGen/ISDOpcodes.h"
      25             : #include "llvm/CodeGen/MachineBasicBlock.h"
      26             : #include "llvm/IR/Instructions.h"
      27             : #include "llvm/IR/Type.h"
      28             : #include "llvm/IR/Value.h"
      29             : #include "llvm/Support/KnownBits.h"
      30             : #include "llvm/Target/TargetRegisterInfo.h"
      31             : #include <cassert>
      32             : #include <utility>
      33             : #include <vector>
      34             : 
      35             : namespace llvm {
      36             : 
      37             : class Argument;
      38             : class BasicBlock;
      39             : class BranchProbabilityInfo;
      40             : class Function;
      41             : class Instruction;
      42             : class MachineFunction;
      43             : class MachineInstr;
      44             : class MachineRegisterInfo;
      45             : class MVT;
      46             : class SelectionDAG;
      47             : class TargetLowering;
      48             : 
      49             : //===--------------------------------------------------------------------===//
      50             : /// FunctionLoweringInfo - This contains information that is global to a
      51             : /// function that is used when lowering a region of the function.
      52             : ///
      53      683592 : class FunctionLoweringInfo {
      54             : public:
      55             :   const Function *Fn;
      56             :   MachineFunction *MF;
      57             :   const TargetLowering *TLI;
      58             :   MachineRegisterInfo *RegInfo;
      59             :   BranchProbabilityInfo *BPI;
      60             :   /// CanLowerReturn - true iff the function's return value can be lowered to
      61             :   /// registers.
      62             :   bool CanLowerReturn;
      63             : 
      64             :   /// True if part of the CSRs will be handled via explicit copies.
      65             :   bool SplitCSR;
      66             : 
      67             :   /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
      68             :   /// allocated to hold a pointer to the hidden sret parameter.
      69             :   unsigned DemoteRegister;
      70             : 
      71             :   /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
      72             :   DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
      73             : 
      74             :   /// A map from swifterror value in a basic block to the virtual register it is
      75             :   /// currently represented by.
      76             :   DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
      77             :       SwiftErrorVRegDefMap;
      78             : 
      79             :   /// A list of upward exposed vreg uses that need to be satisfied by either a
      80             :   /// copy def or a phi node at the beginning of the basic block representing
      81             :   /// the predecessor(s) swifterror value.
      82             :   DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
      83             :       SwiftErrorVRegUpwardsUse;
      84             : 
      85             :   /// A map from instructions that define/use a swifterror value to the virtual
      86             :   /// register that represents that def/use.
      87             :   llvm::DenseMap<PointerIntPair<const Instruction *, 1, bool>, unsigned>
      88             :       SwiftErrorVRegDefUses;
      89             : 
      90             :   /// The swifterror argument of the current function.
      91             :   const Value *SwiftErrorArg;
      92             : 
      93             :   using SwiftErrorValues = SmallVector<const Value*, 1>;
      94             :   /// A function can only have a single swifterror argument. And if it does
      95             :   /// have a swifterror argument, it must be the first entry in
      96             :   /// SwiftErrorVals.
      97             :   SwiftErrorValues SwiftErrorVals;
      98             : 
      99             :   /// Get or create the swifterror value virtual register in
     100             :   /// SwiftErrorVRegDefMap for this basic block.
     101             :   unsigned getOrCreateSwiftErrorVReg(const MachineBasicBlock *,
     102             :                                      const Value *);
     103             : 
     104             :   /// Set the swifterror virtual register in the SwiftErrorVRegDefMap for this
     105             :   /// basic block.
     106             :   void setCurrentSwiftErrorVReg(const MachineBasicBlock *MBB, const Value *,
     107             :                                 unsigned);
     108             : 
     109             :   /// Get or create the swifterror value virtual register for a def of a
     110             :   /// swifterror by an instruction.
     111             :   std::pair<unsigned, bool> getOrCreateSwiftErrorVRegDefAt(const Instruction *);
     112             :   std::pair<unsigned, bool>
     113             :   getOrCreateSwiftErrorVRegUseAt(const Instruction *, const MachineBasicBlock *,
     114             :                                  const Value *);
     115             : 
     116             :   /// ValueMap - Since we emit code for the function a basic block at a time,
     117             :   /// we must remember which virtual registers hold the values for
     118             :   /// cross-basic-block values.
     119             :   DenseMap<const Value *, unsigned> ValueMap;
     120             : 
     121             :   /// Track virtual registers created for exception pointers.
     122             :   DenseMap<const Value *, unsigned> CatchPadExceptionPointers;
     123             : 
     124             :   /// Keep track of frame indices allocated for statepoints as they could be
     125             :   /// used across basic block boundaries.  This struct is more complex than a
     126             :   /// simple map because the stateopint lowering code de-duplicates gc pointers
     127             :   /// based on their SDValue (so %p and (bitcast %p to T) will get the same
     128             :   /// slot), and we track that here.
     129             : 
     130         414 :   struct StatepointSpillMap {
     131             :     using SlotMapTy = DenseMap<const Value *, Optional<int>>;
     132             : 
     133             :     /// Maps uniqued llvm IR values to the slots they were spilled in.  If a
     134             :     /// value is mapped to None it means we visited the value but didn't spill
     135             :     /// it (because it was a constant, for instance).
     136             :     SlotMapTy SlotMap;
     137             : 
     138             :     /// Maps llvm IR values to the values they were de-duplicated to.
     139             :     DenseMap<const Value *, const Value *> DuplicateMap;
     140             : 
     141          75 :     SlotMapTy::const_iterator find(const Value *V) const {
     142          75 :       auto DuplIt = DuplicateMap.find(V);
     143         150 :       if (DuplIt != DuplicateMap.end())
     144          15 :         V = DuplIt->second;
     145          75 :       return SlotMap.find(V);
     146             :     }
     147             : 
     148          18 :     SlotMapTy::const_iterator end() const { return SlotMap.end(); }
     149             :   };
     150             : 
     151             :   /// Maps gc.statepoint instructions to their corresponding StatepointSpillMap
     152             :   /// instances.
     153             :   DenseMap<const Instruction *, StatepointSpillMap> StatepointSpillMaps;
     154             : 
     155             :   /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
     156             :   /// the entry block.  This allows the allocas to be efficiently referenced
     157             :   /// anywhere in the function.
     158             :   DenseMap<const AllocaInst*, int> StaticAllocaMap;
     159             : 
     160             :   /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
     161             :   DenseMap<const Argument*, int> ByValArgFrameIndexMap;
     162             : 
     163             :   /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
     164             :   /// function arguments that are inserted after scheduling is completed.
     165             :   SmallVector<MachineInstr*, 8> ArgDbgValues;
     166             : 
     167             :   /// RegFixups - Registers which need to be replaced after isel is done.
     168             :   DenseMap<unsigned, unsigned> RegFixups;
     169             : 
     170             :   /// StatepointStackSlots - A list of temporary stack slots (frame indices)
     171             :   /// used to spill values at a statepoint.  We store them here to enable
     172             :   /// reuse of the same stack slots across different statepoints in different
     173             :   /// basic blocks.
     174             :   SmallVector<unsigned, 50> StatepointStackSlots;
     175             : 
     176             :   /// MBB - The current block.
     177             :   MachineBasicBlock *MBB;
     178             : 
     179             :   /// MBB - The current insert position inside the current block.
     180             :   MachineBasicBlock::iterator InsertPt;
     181             : 
     182      941012 :   struct LiveOutInfo {
     183             :     unsigned NumSignBits : 31;
     184             :     unsigned IsValid : 1;
     185             :     KnownBits Known = 1;
     186             : 
     187       18528 :     LiveOutInfo() : NumSignBits(0), IsValid(true) {}
     188             :   };
     189             : 
     190             :   /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
     191             :   /// for a value.
     192             :   DenseMap<const Value *, ISD::NodeType> PreferredExtendType;
     193             : 
     194             :   /// VisitedBBs - The set of basic blocks visited thus far by instruction
     195             :   /// selection.
     196             :   SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
     197             : 
     198             :   /// PHINodesToUpdate - A list of phi instructions whose operand list will
     199             :   /// be updated after processing the current basic block.
     200             :   /// TODO: This isn't per-function state, it's per-basic-block state. But
     201             :   /// there's no other convenient place for it to live right now.
     202             :   std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
     203             :   unsigned OrigNumPHINodesToUpdate;
     204             : 
     205             :   /// If the current MBB is a landing pad, the exception pointer and exception
     206             :   /// selector registers are copied into these virtual registers by
     207             :   /// SelectionDAGISel::PrepareEHLandingPad().
     208             :   unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
     209             : 
     210             :   /// set - Initialize this FunctionLoweringInfo with the given Function
     211             :   /// and its associated MachineFunction.
     212             :   ///
     213             :   void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
     214             : 
     215             :   /// clear - Clear out all the function-specific state. This returns this
     216             :   /// FunctionLoweringInfo to an empty state, ready to be used for a
     217             :   /// different function.
     218             :   void clear();
     219             : 
     220             :   /// isExportedInst - Return true if the specified value is an instruction
     221             :   /// exported from its block.
     222             :   bool isExportedInst(const Value *V) {
     223       55902 :     return ValueMap.count(V);
     224             :   }
     225             : 
     226             :   unsigned CreateReg(MVT VT);
     227             : 
     228             :   unsigned CreateRegs(Type *Ty);
     229             : 
     230      143659 :   unsigned InitializeRegForValue(const Value *V) {
     231             :     // Tokens never live in vregs.
     232      287318 :     if (V->getType()->isTokenTy())
     233             :       return 0;
     234      287052 :     unsigned &R = ValueMap[V];
     235             :     assert(R == 0 && "Already initialized this value register!");
     236      143526 :     return R = CreateRegs(V->getType());
     237             :   }
     238             : 
     239             :   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
     240             :   /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
     241             :   const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
     242      222756 :     if (!LiveOutRegInfo.inBounds(Reg))
     243             :       return nullptr;
     244             : 
     245      145564 :     const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
     246       72782 :     if (!LOI->IsValid)
     247             :       return nullptr;
     248             : 
     249             :     return LOI;
     250             :   }
     251             : 
     252             :   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
     253             :   /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
     254             :   /// the register's LiveOutInfo is for a smaller bit width, it is extended to
     255             :   /// the larger bit width by zero extension. The bit width must be no smaller
     256             :   /// than the LiveOutInfo's existing bit width.
     257             :   const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
     258             : 
     259             :   /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
     260       94474 :   void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
     261             :                          const KnownBits &Known) {
     262             :     // Only install this information if it tells us something.
     263       94474 :     if (NumSignBits == 1 && Known.isUnknown())
     264             :       return;
     265             : 
     266       17689 :     LiveOutRegInfo.grow(Reg);
     267       35378 :     LiveOutInfo &LOI = LiveOutRegInfo[Reg];
     268       17689 :     LOI.NumSignBits = NumSignBits;
     269       17689 :     LOI.Known.One = Known.One;
     270       17689 :     LOI.Known.Zero = Known.Zero;
     271             :   }
     272             : 
     273             :   /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
     274             :   /// register based on the LiveOutInfo of its operands.
     275             :   void ComputePHILiveOutRegInfo(const PHINode*);
     276             : 
     277             :   /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
     278             :   /// called when a block is visited before all of its predecessors.
     279        8075 :   void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
     280             :     // PHIs with no uses have no ValueMap entry.
     281       16150 :     DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN);
     282       24225 :     if (It == ValueMap.end())
     283             :       return;
     284             : 
     285        8069 :     unsigned Reg = It->second;
     286        8069 :     if (Reg == 0)
     287             :       return;
     288             : 
     289        8068 :     LiveOutRegInfo.grow(Reg);
     290       16136 :     LiveOutRegInfo[Reg].IsValid = false;
     291             :   }
     292             : 
     293             :   /// setArgumentFrameIndex - Record frame index for the byval
     294             :   /// argument.
     295             :   void setArgumentFrameIndex(const Argument *A, int FI);
     296             : 
     297             :   /// getArgumentFrameIndex - Get frame index for the byval argument.
     298             :   int getArgumentFrameIndex(const Argument *A);
     299             : 
     300             :   unsigned getCatchPadExceptionPointerVReg(const Value *CPI,
     301             :                                            const TargetRegisterClass *RC);
     302             : 
     303             : private:
     304             :   void addSEHHandlersForLPads(ArrayRef<const LandingPadInst *> LPads);
     305             : 
     306             :   /// LiveOutRegInfo - Information about live out vregs.
     307             :   IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
     308             : };
     309             : 
     310             : } // end namespace llvm
     311             : 
     312             : #endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H

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