Line data Source code
1 : //=== llvm/CodeGen/ISDOpcodes.h  CodeGen opcodes * C++ *===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //======//
9 : //
10 : // This file declares codegen opcodes and related utilities.
11 : //
12 : //======//
13 :
14 : #ifndef LLVM_CODEGEN_ISDOPCODES_H
15 : #define LLVM_CODEGEN_ISDOPCODES_H
16 :
17 : namespace llvm {
18 :
19 : /// ISD namespace  This namespace contains an enum which represents all of the
20 : /// SelectionDAG node types and value types.
21 : ///
22 : namespace ISD {
23 :
24 : //======//
25 : /// ISD::NodeType enum  This enum defines the targetindependent operators
26 : /// for a SelectionDAG.
27 : ///
28 : /// Targets may also define targetdependent operator codes for SDNodes. For
29 : /// example, on x86, these are the enum values in the X86ISD namespace.
30 : /// Targets should aim to use targetindependent operators to model their
31 : /// instruction sets as much as possible, and only use targetdependent
32 : /// operators when they have special requirements.
33 : ///
34 : /// Finally, during and after selection proper, SNodes may use special
35 : /// operator codes that correspond directly with MachineInstr opcodes. These
36 : /// are used to represent selected instructions. See the isMachineOpcode()
37 : /// and getMachineOpcode() member functions of SDNode.
38 : ///
39 : enum NodeType {
40 : /// DELETED_NODE  This is an illegal value that is used to catch
41 : /// errors. This opcode is not a legal opcode for any node.
42 : DELETED_NODE,
43 :
44 : /// EntryToken  This is the marker used to indicate the start of a region.
45 : EntryToken,
46 :
47 : /// TokenFactor  This node takes multiple tokens as input and produces a
48 : /// single token result. This is used to represent the fact that the operand
49 : /// operators are independent of each other.
50 : TokenFactor,
51 :
52 : /// AssertSext, AssertZext  These nodes record if a register contains a
53 : /// value that has already been zero or sign extended from a narrower type.
54 : /// These nodes take two operands. The first is the node that has already
55 : /// been extended, and the second is a value type node indicating the width
56 : /// of the extension
57 : AssertSext, AssertZext,
58 :
59 : /// Various leaf nodes.
60 : BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
61 : Constant, ConstantFP,
62 : GlobalAddress, GlobalTLSAddress, FrameIndex,
63 : JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
64 :
65 : /// The address of the GOT
66 : GLOBAL_OFFSET_TABLE,
67 :
68 : /// FRAMEADDR, RETURNADDR  These nodes represent llvm.frameaddress and
69 : /// llvm.returnaddress on the DAG. These nodes take one operand, the index
70 : /// of the frame or return address to return. An index of zero corresponds
71 : /// to the current function's frame or return address, an index of one to
72 : /// the parent's frame or return address, and so on.
73 : FRAMEADDR, RETURNADDR, ADDROFRETURNADDR,
74 :
75 : /// LOCAL_RECOVER  Represents the llvm.localrecover intrinsic.
76 : /// Materializes the offset from the local object pointer of another
77 : /// function to a particular local object passed to llvm.localescape. The
78 : /// operand is the MCSymbol label used to represent this offset, since
79 : /// typically the offset is not known until after code generation of the
80 : /// parent.
81 : LOCAL_RECOVER,
82 :
83 : /// READ_REGISTER, WRITE_REGISTER  This node represents llvm.register on
84 : /// the DAG, which implements the named register global variables extension.
85 : READ_REGISTER,
86 : WRITE_REGISTER,
87 :
88 : /// FRAME_TO_ARGS_OFFSET  This node represents offset from frame pointer to
89 : /// first (possible) onstack argument. This is needed for correct stack
90 : /// adjustment during unwind.
91 : FRAME_TO_ARGS_OFFSET,
92 :
93 : /// EH_DWARF_CFA  This node represents the pointer to the DWARF Canonical
94 : /// Frame Address (CFA), generally the value of the stack pointer at the
95 : /// call site in the previous frame.
96 : EH_DWARF_CFA,
97 :
98 : /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER)  This node represents
99 : /// 'eh_return' gcc dwarf builtin, which is used to return from
100 : /// exception. The general meaning is: adjust stack by OFFSET and pass
101 : /// execution to HANDLER. Many platformrelated details also :)
102 : EH_RETURN,
103 :
104 : /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
105 : /// This corresponds to the eh.sjlj.setjmp intrinsic.
106 : /// It takes an input chain and a pointer to the jump buffer as inputs
107 : /// and returns an outchain.
108 : EH_SJLJ_SETJMP,
109 :
110 : /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
111 : /// This corresponds to the eh.sjlj.longjmp intrinsic.
112 : /// It takes an input chain and a pointer to the jump buffer as inputs
113 : /// and returns an outchain.
114 : EH_SJLJ_LONGJMP,
115 :
116 : /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
117 : /// The target initializes the dispatch table here.
118 : EH_SJLJ_SETUP_DISPATCH,
119 :
120 : /// TargetConstant*  Like Constant*, but the DAG does not do any folding,
121 : /// simplification, or lowering of the constant. They are used for constants
122 : /// which are known to fit in the immediate fields of their users, or for
123 : /// carrying magic numbers which are not values which need to be
124 : /// materialized in registers.
125 : TargetConstant,
126 : TargetConstantFP,
127 :
128 : /// TargetGlobalAddress  Like GlobalAddress, but the DAG does no folding or
129 : /// anything else with this node, and this is valid in the targetspecific
130 : /// dag, turning into a GlobalAddress operand.
131 : TargetGlobalAddress,
132 : TargetGlobalTLSAddress,
133 : TargetFrameIndex,
134 : TargetJumpTable,
135 : TargetConstantPool,
136 : TargetExternalSymbol,
137 : TargetBlockAddress,
138 :
139 : MCSymbol,
140 :
141 : /// TargetIndex  Like a constant pool entry, but with completely
142 : /// targetdependent semantics. Holds target flags, a 32bit index, and a
143 : /// 64bit index. Targets can use this however they like.
144 : TargetIndex,
145 :
146 : /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
147 : /// This node represents a target intrinsic function with no side effects.
148 : /// The first operand is the ID number of the intrinsic from the
149 : /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
150 : /// node returns the result of the intrinsic.
151 : INTRINSIC_WO_CHAIN,
152 :
153 : /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
154 : /// This node represents a target intrinsic function with side effects that
155 : /// returns a result. The first operand is a chain pointer. The second is
156 : /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The
157 : /// operands to the intrinsic follow. The node has two results, the result
158 : /// of the intrinsic and an output chain.
159 : INTRINSIC_W_CHAIN,
160 :
161 : /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
162 : /// This node represents a target intrinsic function with side effects that
163 : /// does not return a result. The first operand is a chain pointer. The
164 : /// second is the ID number of the intrinsic from the llvm::Intrinsic
165 : /// namespace. The operands to the intrinsic follow.
166 : INTRINSIC_VOID,
167 :
168 : /// CopyToReg  This node has three operands: a chain, a register number to
169 : /// set to this value, and a value.
170 : CopyToReg,
171 :
172 : /// CopyFromReg  This node indicates that the input value is a virtual or
173 : /// physical register that is defined outside of the scope of this
174 : /// SelectionDAG. The register is available from the RegisterSDNode object.
175 : CopyFromReg,
176 :
177 : /// UNDEF  An undefined node.
178 : UNDEF,
179 :
180 : /// EXTRACT_ELEMENT  This is used to get the lower or upper (determined by
181 : /// a Constant, which is required to be operand #1) half of the integer or
182 : /// float value specified as operand #0. This is only for use before
183 : /// legalization, for values that will be broken into multiple registers.
184 : EXTRACT_ELEMENT,
185 :
186 : /// BUILD_PAIR  This is the opposite of EXTRACT_ELEMENT in some ways.
187 : /// Given two values of the same integer value type, this produces a value
188 : /// twice as big. Like EXTRACT_ELEMENT, this can only be used before
189 : /// legalization.
190 : BUILD_PAIR,
191 :
192 : /// MERGE_VALUES  This node takes multiple discrete operands and returns
193 : /// them all as its individual results. This nodes has exactly the same
194 : /// number of inputs and outputs. This node is useful for some pieces of the
195 : /// code generator that want to think about a single node with multiple
196 : /// results, not multiple nodes.
197 : MERGE_VALUES,
198 :
199 : /// Simple integer binary arithmetic operators.
200 : ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
201 :
202 : /// SMUL_LOHI/UMUL_LOHI  Multiply two integers of type iN, producing
203 : /// a signed/unsigned value of type i[2*N], and return the full value as
204 : /// two results, each of type iN.
205 : SMUL_LOHI, UMUL_LOHI,
206 :
207 : /// SDIVREM/UDIVREM  Divide two integers and produce both a quotient and
208 : /// remainder result.
209 : SDIVREM, UDIVREM,
210 :
211 : /// CARRY_FALSE  This node is used when folding other nodes,
212 : /// like ADDC/SUBC, which indicate the carry result is always false.
213 : CARRY_FALSE,
214 :
215 : /// Carrysetting nodes for multiple precision addition and subtraction.
216 : /// These nodes take two operands of the same value type, and produce two
217 : /// results. The first result is the normal add or sub result, the second
218 : /// result is the carry flag result.
219 : /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY.
220 : /// They are kept around for now to provide a smooth transition path
221 : /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed.
222 : ADDC, SUBC,
223 :
224 : /// Carryusing nodes for multiple precision addition and subtraction. These
225 : /// nodes take three operands: The first two are the normal lhs and rhs to
226 : /// the add or sub, and the third is the input carry flag. These nodes
227 : /// produce two results; the normal result of the add or sub, and the output
228 : /// carry flag. These nodes both read and write a carry flag to allow them
229 : /// to them to be chained together for add and sub of arbitrarily large
230 : /// values.
231 : ADDE, SUBE,
232 :
233 : /// Carryusing nodes for multiple precision addition and subtraction.
234 : /// These nodes take three operands: The first two are the normal lhs and
235 : /// rhs to the add or sub, and the third is a boolean indicating if there
236 : /// is an incoming carry. These nodes produce two results: the normal
237 : /// result of the add or sub, and the output carry so they can be chained
238 : /// together. The use of this opcode is preferable to adde/sube if the
239 : /// target supports it, as the carry is a regular value rather than a
240 : /// glue, which allows further optimisation.
241 : ADDCARRY, SUBCARRY,
242 :
243 : /// RESULT, BOOL = [SU]ADDO(LHS, RHS)  Overflowaware nodes for addition.
244 : /// These nodes take two operands: the normal LHS and RHS to the add. They
245 : /// produce two results: the normal result of the add, and a boolean that
246 : /// indicates if an overflow occurred (*not* a flag, because it may be store
247 : /// to memory, etc.). If the type of the boolean is not i1 then the high
248 : /// bits conform to getBooleanContents.
249 : /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
250 : SADDO, UADDO,
251 :
252 : /// Same for subtraction.
253 : SSUBO, USUBO,
254 :
255 : /// Same for multiplication.
256 : SMULO, UMULO,
257 :
258 : /// Simple binary floating point operators.
259 : FADD, FSUB, FMUL, FDIV, FREM,
260 :
261 : /// Constrained versions of the binary floating point operators.
262 : /// These will be lowered to the simple operators before final selection.
263 : /// They are used to limit optimizations while the DAG is being
264 : /// optimized.
265 : STRICT_FADD, STRICT_FSUB, STRICT_FMUL, STRICT_FDIV, STRICT_FREM,
266 : STRICT_FMA,
267 :
268 : /// Constrained versions of libmequivalent floating point intrinsics.
269 : /// These will be lowered to the equivalent nonconstrained pseudoop
270 : /// (or expanded to the equivalent library call) before final selection.
271 : /// They are used to limit optimizations while the DAG is being optimized.
272 : STRICT_FSQRT, STRICT_FPOW, STRICT_FPOWI, STRICT_FSIN, STRICT_FCOS,
273 : STRICT_FEXP, STRICT_FEXP2, STRICT_FLOG, STRICT_FLOG10, STRICT_FLOG2,
274 : STRICT_FRINT, STRICT_FNEARBYINT,
275 :
276 : /// FMA  Perform a * b + c with no intermediate rounding step.
277 : FMA,
278 :
279 : /// FMAD  Perform a * b + c, while getting the same result as the
280 : /// separately rounded operations.
281 : FMAD,
282 :
283 : /// FCOPYSIGN(X, Y)  Return the value of X with the sign of Y. NOTE: This
284 : /// DAG node does not require that X and Y have the same type, just that
285 : /// they are both floating point. X and the result must have the same type.
286 : /// FCOPYSIGN(f32, f64) is allowed.
287 : FCOPYSIGN,
288 :
289 : /// INT = FGETSIGN(FP)  Return the sign bit of the specified floating point
290 : /// value as an integer 0/1 value.
291 : FGETSIGN,
292 :
293 : /// Returns platform specific canonical encoding of a floating point number.
294 : FCANONICALIZE,
295 :
296 : /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...)  Return a vector with the
297 : /// specified, possibly variable, elements. The number of elements is
298 : /// required to be a power of two. The types of the operands must all be
299 : /// the same and must match the vector element type, except that integer
300 : /// types are allowed to be larger than the element type, in which case
301 : /// the operands are implicitly truncated.
302 : BUILD_VECTOR,
303 :
304 : /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX)  Returns VECTOR with the element
305 : /// at IDX replaced with VAL. If the type of VAL is larger than the vector
306 : /// element type then VAL is truncated before replacement.
307 : INSERT_VECTOR_ELT,
308 :
309 : /// EXTRACT_VECTOR_ELT(VECTOR, IDX)  Returns a single element from VECTOR
310 : /// identified by the (potentially variable) element number IDX. If the
311 : /// return type is an integer type larger than the element type of the
312 : /// vector, the result is extended to the width of the return type. In
313 : /// that case, the high bits are undefined.
314 : EXTRACT_VECTOR_ELT,
315 :
316 : /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...)  Given a number of values of
317 : /// vector type with the same length and element type, this produces a
318 : /// concatenated vector result value, with length equal to the sum of the
319 : /// lengths of the input vectors.
320 : CONCAT_VECTORS,
321 :
322 : /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX)  Returns a vector
323 : /// with VECTOR2 inserted into VECTOR1 at the (potentially
324 : /// variable) element number IDX, which must be a multiple of the
325 : /// VECTOR2 vector length. The elements of VECTOR1 starting at
326 : /// IDX are overwritten with VECTOR2. Elements IDX through
327 : /// vector_length(VECTOR2) must be valid VECTOR1 indices.
328 : INSERT_SUBVECTOR,
329 :
330 : /// EXTRACT_SUBVECTOR(VECTOR, IDX)  Returns a subvector from VECTOR (an
331 : /// vector value) starting with the element number IDX, which must be a
332 : /// constant multiple of the result vector length.
333 : EXTRACT_SUBVECTOR,
334 :
335 : /// VECTOR_SHUFFLE(VEC1, VEC2)  Returns a vector, of the same type as
336 : /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
337 : /// values that indicate which value (or undef) each result element will
338 : /// get. These constant ints are accessible through the
339 : /// ShuffleVectorSDNode class. This is quite similar to the Altivec
340 : /// 'vperm' instruction, except that the indices must be constants and are
341 : /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
342 : VECTOR_SHUFFLE,
343 :
344 : /// SCALAR_TO_VECTOR(VAL)  This represents the operation of loading a
345 : /// scalar value into element 0 of the resultant vector type. The top
346 : /// elements 1 to N1 of the Nelement vector are undefined. The type
347 : /// of the operand must match the vector element type, except when they
348 : /// are integer types. In this case the operand is allowed to be wider
349 : /// than the vector element type, and is implicitly truncated to it.
350 : SCALAR_TO_VECTOR,
351 :
352 : /// MULHU/MULHS  Multiply high  Multiply two integers of type iN,
353 : /// producing an unsigned/signed value of type i[2*N], then return the top
354 : /// part.
355 : MULHU, MULHS,
356 :
357 : /// [US]{MIN/MAX}  Binary minimum or maximum or signed or unsigned
358 : /// integers.
359 : SMIN, SMAX, UMIN, UMAX,
360 :
361 : /// Bitwise operators  logical and, logical or, logical xor.
362 : AND, OR, XOR,
363 :
364 : /// ABS  Determine the unsigned absolute value of a signed integer value of
365 : /// the same bitwidth.
366 : /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow
367 : /// is performed.
368 : ABS,
369 :
370 : /// Shift and rotation operations. After legalization, the type of the
371 : /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization
372 : /// the shift amount can be any type, but care must be taken to ensure it is
373 : /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before
374 : /// legalization, types like i1024 can occur and i8 doesn't have enough bits
375 : /// to represent the shift amount.
376 : /// When the 1st operand is a vector, the shift amount must be in the same
377 : /// type. (TLI.getShiftAmountTy() will return the same type when the input
378 : /// type is a vector.)
379 : SHL, SRA, SRL, ROTL, ROTR,
380 :
381 : /// Byte Swap and Counting operators.
382 : BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE,
383 :
384 : /// Bit counting operators with an undefined result for zero inputs.
385 : CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
386 :
387 : /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
388 : /// i1 then the high bits must conform to getBooleanContents.
389 : SELECT,
390 :
391 : /// Select with a vector condition (op #0) and two vector operands (ops #1
392 : /// and #2), returning a vector result. All vectors have the same length.
393 : /// Much like the scalar select and setcc, each bit in the condition selects
394 : /// whether the corresponding result element is taken from op #1 or op #2.
395 : /// At first, the VSELECT condition is of vXi1 type. Later, targets may
396 : /// change the condition type in order to match the VSELECT node using a
397 : /// pattern. The condition follows the BooleanContent format of the target.
398 : VSELECT,
399 :
400 : /// Select with condition operator  This selects between a true value and
401 : /// a false value (ops #2 and #3) based on the boolean result of comparing
402 : /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
403 : /// condition code in op #4, a CondCodeSDNode.
404 : SELECT_CC,
405 :
406 : /// SetCC operator  This evaluates to a true value iff the condition is
407 : /// true. If the result value type is not i1 then the high bits conform
408 : /// to getBooleanContents. The operands to this are the left and right
409 : /// operands to compare (ops #0, and #1) and the condition code to compare
410 : /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
411 : /// then the result type must also be a vector type.
412 : SETCC,
413 :
414 : /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, and
415 : /// op #2 is a *carry value*. This operator checks the result of
416 : /// "LHS  RHS  Carry", and can be used to compare two wide integers:
417 : /// (setcce lhshi rhshi (subc lhslo rhslo) cc). Only valid for integers.
418 : /// FIXME: This node is deprecated in favor of SETCCCARRY.
419 : /// It is kept around for now to provide a smooth transition path
420 : /// toward the use of SETCCCARRY and will eventually be removed.
421 : SETCCE,
422 :
423 : /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
424 : /// op #2 is a boolean indicating if there is an incoming carry. This
425 : /// operator checks the result of "LHS  RHS  Carry", and can be used to
426 : /// compare two wide integers: (setcce lhshi rhshi (subc lhslo rhslo) cc).
427 : /// Only valid for integers.
428 : SETCCCARRY,
429 :
430 : /// SHL_PARTS/SRA_PARTS/SRL_PARTS  These operators are used for expanded
431 : /// integer shift operations. The operation ordering is:
432 : /// [Lo,Hi] = op [LoLHS,HiLHS], Amt
433 : SHL_PARTS, SRA_PARTS, SRL_PARTS,
434 :
435 : /// Conversion operators. These are all single input single output
436 : /// operations. For all of these, the result type must be strictly
437 : /// wider or narrower (depending on the operation) than the source
438 : /// type.
439 :
440 : /// SIGN_EXTEND  Used for integer types, replicating the sign bit
441 : /// into new bits.
442 : SIGN_EXTEND,
443 :
444 : /// ZERO_EXTEND  Used for integer types, zeroing the new bits.
445 : ZERO_EXTEND,
446 :
447 : /// ANY_EXTEND  Used for integer types. The high bits are undefined.
448 : ANY_EXTEND,
449 :
450 : /// TRUNCATE  Completely drop the high bits.
451 : TRUNCATE,
452 :
453 : /// [SU]INT_TO_FP  These operators convert integers (whose interpreted sign
454 : /// depends on the first letter) to floating point.
455 : SINT_TO_FP,
456 : UINT_TO_FP,
457 :
458 : /// SIGN_EXTEND_INREG  This operator atomically performs a SHL/SRA pair to
459 : /// sign extend a small value in a large integer register (e.g. sign
460 : /// extending the low 8 bits of a 32bit register to fill the top 24 bits
461 : /// with the 7th bit). The size of the smaller type is indicated by the 1th
462 : /// operand, a ValueType node.
463 : SIGN_EXTEND_INREG,
464 :
465 : /// ANY_EXTEND_VECTOR_INREG(Vector)  This operator represents an
466 : /// inregister anyextension of the low lanes of an integer vector. The
467 : /// result type must have fewer elements than the operand type, and those
468 : /// elements must be larger integer types such that the total size of the
469 : /// operand type and the result type match. Each of the low operand
470 : /// elements is anyextended into the corresponding, wider result
471 : /// elements with the high bits becoming undef.
472 : ANY_EXTEND_VECTOR_INREG,
473 :
474 : /// SIGN_EXTEND_VECTOR_INREG(Vector)  This operator represents an
475 : /// inregister signextension of the low lanes of an integer vector. The
476 : /// result type must have fewer elements than the operand type, and those
477 : /// elements must be larger integer types such that the total size of the
478 : /// operand type and the result type match. Each of the low operand
479 : /// elements is signextended into the corresponding, wider result
480 : /// elements.
481 : // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to
482 : // scalars, but it also doesn't handle vectors well. Either it should be
483 : // restricted to scalars or this node (and its handling) should be merged
484 : // into it.
485 : SIGN_EXTEND_VECTOR_INREG,
486 :
487 : /// ZERO_EXTEND_VECTOR_INREG(Vector)  This operator represents an
488 : /// inregister zeroextension of the low lanes of an integer vector. The
489 : /// result type must have fewer elements than the operand type, and those
490 : /// elements must be larger integer types such that the total size of the
491 : /// operand type and the result type match. Each of the low operand
492 : /// elements is zeroextended into the corresponding, wider result
493 : /// elements.
494 : ZERO_EXTEND_VECTOR_INREG,
495 :
496 : /// FP_TO_[US]INT  Convert a floating point value to a signed or unsigned
497 : /// integer.
498 : FP_TO_SINT,
499 : FP_TO_UINT,
500 :
501 : /// X = FP_ROUND(Y, TRUNC)  Rounding 'Y' from a larger floating point type
502 : /// down to the precision of the destination VT. TRUNC is a flag, which is
503 : /// always an integer that is zero or one. If TRUNC is 0, this is a
504 : /// normal rounding, if it is 1, this FP_ROUND is known to not change the
505 : /// value of Y.
506 : ///
507 : /// The TRUNC = 1 case is used in cases where we know that the value will
508 : /// not be modified by the node, because Y is not using any of the extra
509 : /// precision of source type. This allows certain transformations like
510 : /// FP_EXTEND(FP_ROUND(X,1)) > X which are not safe for
511 : /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
512 : FP_ROUND,
513 :
514 : /// FLT_ROUNDS_  Returns current rounding mode:
515 : /// 1 Undefined
516 : /// 0 Round to 0
517 : /// 1 Round to nearest
518 : /// 2 Round to +inf
519 : /// 3 Round to inf
520 : FLT_ROUNDS_,
521 :
522 : /// X = FP_ROUND_INREG(Y, VT)  This operator takes an FP register, and
523 : /// rounds it to a floating point value. It then promotes it and returns it
524 : /// in a register of the same size. This operation effectively just
525 : /// discards excess precision. The type to round down to is specified by
526 : /// the VT operand, a VTSDNode.
527 : FP_ROUND_INREG,
528 :
529 : /// X = FP_EXTEND(Y)  Extend a smaller FP type into a larger FP type.
530 : FP_EXTEND,
531 :
532 : /// BITCAST  This operator converts between integer, vector and FP
533 : /// values, as if the value was stored to memory with one type and loaded
534 : /// from the same address with the other type (or equivalently for vector
535 : /// format conversions, etc). The source and result are required to have
536 : /// the same bit size (e.g. f32 <> i32). This can also be used for
537 : /// inttoint or fptofp conversions, but that is a noop, deleted by
538 : /// getNode().
539 : ///
540 : /// This operator is subtly different from the bitcast instruction from
541 : /// LLVMIR since this node may change the bits in the register. For
542 : /// example, this occurs on bigendian NEON and bigendian MSA where the
543 : /// layout of the bits in the register depends on the vector type and this
544 : /// operator acts as a shuffle operation for some vector type combinations.
545 : BITCAST,
546 :
547 : /// ADDRSPACECAST  This operator converts between pointers of different
548 : /// address spaces.
549 : ADDRSPACECAST,
550 :
551 : /// FP16_TO_FP, FP_TO_FP16  These operators are used to perform promotions
552 : /// and truncation for halfprecision (16 bit) floating numbers. These nodes
553 : /// form a semisoftened interface for dealing with f16 (as an i16), which
554 : /// is often a storageonly type but has native conversions.
555 : FP16_TO_FP, FP_TO_FP16,
556 :
557 : /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
558 : /// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
559 : /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR  Perform various unary
560 : /// floating point operations. These are inspired by libm.
561 : FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
562 : FLOG, FLOG2, FLOG10, FEXP, FEXP2,
563 : FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
564 : /// FMINNUM/FMAXNUM  Perform floatingpoint minimum or maximum on two
565 : /// values.
566 : /// In the case where a single input is NaN, the nonNaN input is returned.
567 : ///
568 : /// The return value of (FMINNUM 0.0, 0.0) could be either 0.0 or 0.0.
569 : FMINNUM, FMAXNUM,
570 : /// FMINNAN/FMAXNAN  Behave identically to FMINNUM/FMAXNUM, except that
571 : /// when a single input is NaN, NaN is returned.
572 : FMINNAN, FMAXNAN,
573 :
574 : /// FSINCOS  Compute both fsin and fcos as a single operation.
575 : FSINCOS,
576 :
577 : /// LOAD and STORE have token chains as their first operand, then the same
578 : /// operands as an LLVM load/store instruction, then an offset node that
579 : /// is added / subtracted from the base pointer to form the address (for
580 : /// indexed memory ops).
581 : LOAD, STORE,
582 :
583 : /// DYNAMIC_STACKALLOC  Allocate some number of bytes on the stack aligned
584 : /// to a specified boundary. This node always has two return values: a new
585 : /// stack pointer value and a chain. The first operand is the token chain,
586 : /// the second is the number of bytes to allocate, and the third is the
587 : /// alignment boundary. The size is guaranteed to be a multiple of the
588 : /// stack alignment, and the alignment is guaranteed to be bigger than the
589 : /// stack alignment (if required) or 0 to get standard stack alignment.
590 : DYNAMIC_STACKALLOC,
591 :
592 : /// Control flow instructions. These all have token chains.
593 :
594 : /// BR  Unconditional branch. The first operand is the chain
595 : /// operand, the second is the MBB to branch to.
596 : BR,
597 :
598 : /// BRIND  Indirect branch. The first operand is the chain, the second
599 : /// is the value to branch to, which must be of the same type as the
600 : /// target's pointer type.
601 : BRIND,
602 :
603 : /// BR_JT  Jumptable branch. The first operand is the chain, the second
604 : /// is the jumptable index, the last one is the jumptable entry index.
605 : BR_JT,
606 :
607 : /// BRCOND  Conditional branch. The first operand is the chain, the
608 : /// second is the condition, the third is the block to branch to if the
609 : /// condition is true. If the type of the condition is not i1, then the
610 : /// high bits must conform to getBooleanContents.
611 : BRCOND,
612 :
613 : /// BR_CC  Conditional branch. The behavior is like that of SELECT_CC, in
614 : /// that the condition is represented as condition code, and two nodes to
615 : /// compare, rather than as a combined SetCC node. The operands in order
616 : /// are chain, cc, lhs, rhs, block to branch to if condition is true.
617 : BR_CC,
618 :
619 : /// INLINEASM  Represents an inline asm block. This node always has two
620 : /// return values: a chain and a flag result. The inputs are as follows:
621 : /// Operand #0 : Input chain.
622 : /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string.
623 : /// Operand #2 : a MDNodeSDNode with the !srcloc metadata.
624 : /// Operand #3 : HasSideEffect, IsAlignStack bits.
625 : /// After this, it is followed by a list of operands with this format:
626 : /// ConstantSDNode: Flags that encode whether it is a mem or not, the
627 : /// of operands that follow, etc. See InlineAsm.h.
628 : /// ... however many operands ...
629 : /// Operand #last: Optional, an incoming flag.
630 : ///
631 : /// The variable width operands are required to represent target addressing
632 : /// modes as a single "operand", even though they may have multiple
633 : /// SDOperands.
634 : INLINEASM,
635 :
636 : /// EH_LABEL  Represents a label in mid basic block used to track
637 : /// locations needed for debug and exception handling tables. These nodes
638 : /// take a chain as input and return a chain.
639 : EH_LABEL,
640 :
641 : /// ANNOTATION_LABEL  Represents a mid basic block label used by
642 : /// annotations. This should remain within the basic block and be ordered
643 : /// with respect to other call instructions, but loads and stores may float
644 : /// past it.
645 : ANNOTATION_LABEL,
646 :
647 : /// CATCHPAD  Represents a catchpad instruction.
648 : CATCHPAD,
649 :
650 : /// CATCHRET  Represents a return from a catch block funclet. Used for
651 : /// MSVC compatible exception handling. Takes a chain operand and a
652 : /// destination basic block operand.
653 : CATCHRET,
654 :
655 : /// CLEANUPRET  Represents a return from a cleanup block funclet. Used for
656 : /// MSVC compatible exception handling. Takes only a chain operand.
657 : CLEANUPRET,
658 :
659 : /// STACKSAVE  STACKSAVE has one operand, an input chain. It produces a
660 : /// value, the same type as the pointer type for the system, and an output
661 : /// chain.
662 : STACKSAVE,
663 :
664 : /// STACKRESTORE has two operands, an input chain and a pointer to restore
665 : /// to it returns an output chain.
666 : STACKRESTORE,
667 :
668 : /// CALLSEQ_START/CALLSEQ_END  These operators mark the beginning and end
669 : /// of a call sequence, and carry arbitrary information that target might
670 : /// want to know. The first operand is a chain, the rest are specified by
671 : /// the target and not touched by the DAG optimizers.
672 : /// Targets that may use stack to pass call arguments define additional
673 : /// operands:
674 : ///  size of the call frame part that must be set up within the
675 : /// CALLSEQ_START..CALLSEQ_END pair,
676 : ///  part of the call frame prepared prior to CALLSEQ_START.
677 : /// Both these parameters must be constants, their sum is the total call
678 : /// frame size.
679 : /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
680 : CALLSEQ_START, // Beginning of a call sequence
681 : CALLSEQ_END, // End of a call sequence
682 :
683 : /// VAARG  VAARG has four operands: an input chain, a pointer, a SRCVALUE,
684 : /// and the alignment. It returns a pair of values: the vaarg value and a
685 : /// new chain.
686 : VAARG,
687 :
688 : /// VACOPY  VACOPY has 5 operands: an input chain, a destination pointer,
689 : /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
690 : /// source.
691 : VACOPY,
692 :
693 : /// VAEND, VASTART  VAEND and VASTART have three operands: an input chain,
694 : /// pointer, and a SRCVALUE.
695 : VAEND, VASTART,
696 :
697 : /// SRCVALUE  This is a node type that holds a Value* that is used to
698 : /// make reference to a value in the LLVM IR.
699 : SRCVALUE,
700 :
701 : /// MDNODE_SDNODE  This is a node that holdes an MDNode*, which is used to
702 : /// reference metadata in the IR.
703 : MDNODE_SDNODE,
704 :
705 : /// PCMARKER  This corresponds to the pcmarker intrinsic.
706 : PCMARKER,
707 :
708 : /// READCYCLECOUNTER  This corresponds to the readcyclecounter intrinsic.
709 : /// It produces a chain and one i64 value. The only operand is a chain.
710 : /// If i64 is not legal, the result will be expanded into smaller values.
711 : /// Still, it returns an i64, so targets should set legality for i64.
712 : /// The result is the content of the architecturespecific cycle
713 : /// counterlike register (or other high accuracy low latency clock source).
714 : READCYCLECOUNTER,
715 :
716 : /// HANDLENODE node  Used as a handle for various purposes.
717 : HANDLENODE,
718 :
719 : /// INIT_TRAMPOLINE  This corresponds to the init_trampoline intrinsic. It
720 : /// takes as input a token chain, the pointer to the trampoline, the pointer
721 : /// to the nested function, the pointer to pass for the 'nest' parameter, a
722 : /// SRCVALUE for the trampoline and another for the nested function
723 : /// (allowing targets to access the original Function*).
724 : /// It produces a token chain as output.
725 : INIT_TRAMPOLINE,
726 :
727 : /// ADJUST_TRAMPOLINE  This corresponds to the adjust_trampoline intrinsic.
728 : /// It takes a pointer to the trampoline and produces a (possibly) new
729 : /// pointer to the same trampoline with platformspecific adjustments
730 : /// applied. The pointer it returns points to an executable block of code.
731 : ADJUST_TRAMPOLINE,
732 :
733 : /// TRAP  Trapping instruction
734 : TRAP,
735 :
736 : /// DEBUGTRAP  Trap intended to get the attention of a debugger.
737 : DEBUGTRAP,
738 :
739 : /// PREFETCH  This corresponds to a prefetch intrinsic. The first operand
740 : /// is the chain. The other operands are the address to prefetch,
741 : /// read / write specifier, locality specifier and instruction / data cache
742 : /// specifier.
743 : PREFETCH,
744 :
745 : /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
746 : /// This corresponds to the fence instruction. It takes an input chain, and
747 : /// two integer constants: an AtomicOrdering and a SynchronizationScope.
748 : ATOMIC_FENCE,
749 :
750 : /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
751 : /// This corresponds to "load atomic" instruction.
752 : ATOMIC_LOAD,
753 :
754 : /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
755 : /// This corresponds to "store atomic" instruction.
756 : ATOMIC_STORE,
757 :
758 : /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
759 : /// For doubleword atomic operations:
760 : /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
761 : /// swapLo, swapHi)
762 : /// This corresponds to the cmpxchg instruction.
763 : ATOMIC_CMP_SWAP,
764 :
765 : /// Val, Success, OUTCHAIN
766 : /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
767 : /// N.b. this is still a strong cmpxchg operation, so
768 : /// Success == "Val == cmp".
769 : ATOMIC_CMP_SWAP_WITH_SUCCESS,
770 :
771 : /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
772 : /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
773 : /// For doubleword atomic operations:
774 : /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
775 : /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
776 : /// These correspond to the atomicrmw instruction.
777 : ATOMIC_SWAP,
778 : ATOMIC_LOAD_ADD,
779 : ATOMIC_LOAD_SUB,
780 : ATOMIC_LOAD_AND,
781 : ATOMIC_LOAD_OR,
782 : ATOMIC_LOAD_XOR,
783 : ATOMIC_LOAD_NAND,
784 : ATOMIC_LOAD_MIN,
785 : ATOMIC_LOAD_MAX,
786 : ATOMIC_LOAD_UMIN,
787 : ATOMIC_LOAD_UMAX,
788 :
789 : // Masked load and store  consecutive vector load and store operations
790 : // with additional mask operand that prevents memory accesses to the
791 : // maskedoff lanes.
792 : MLOAD, MSTORE,
793 :
794 : // Masked gather and scatter  load and store operations for a vector of
795 : // random addresses with additional mask operand that prevents memory
796 : // accesses to the maskedoff lanes.
797 : MGATHER, MSCATTER,
798 :
799 : /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
800 : /// is the chain and the second operand is the alloca pointer.
801 : LIFETIME_START, LIFETIME_END,
802 :
803 : /// GC_TRANSITION_START/GC_TRANSITION_END  These operators mark the
804 : /// beginning and end of GC transition sequence, and carry arbitrary
805 : /// information that target might need for lowering. The first operand is
806 : /// a chain, the rest are specified by the target and not touched by the DAG
807 : /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
808 : /// nested.
809 : GC_TRANSITION_START,
810 : GC_TRANSITION_END,
811 :
812 : /// GET_DYNAMIC_AREA_OFFSET  get offset from native SP to the address of
813 : /// the most recent dynamic alloca. For most targets that would be 0, but
814 : /// for some others (e.g. PowerPC, PowerPC64) that would be compiletime
815 : /// known nonzero constant. The only operand here is the chain.
816 : GET_DYNAMIC_AREA_OFFSET,
817 :
818 : /// Generic reduction nodes. These nodes represent horizontal vector
819 : /// reduction operations, producing a scalar result.
820 : /// The STRICT variants perform reductions in sequential order. The first
821 : /// operand is an initial scalar accumulator value, and the second operand
822 : /// is the vector to reduce.
823 : VECREDUCE_STRICT_FADD, VECREDUCE_STRICT_FMUL,
824 : /// These reductions are nonstrict, and have a single vector operand.
825 : VECREDUCE_FADD, VECREDUCE_FMUL,
826 : VECREDUCE_ADD, VECREDUCE_MUL,
827 : VECREDUCE_AND, VECREDUCE_OR, VECREDUCE_XOR,
828 : VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN,
829 : /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
830 : VECREDUCE_FMAX, VECREDUCE_FMIN,
831 :
832 : /// BUILTIN_OP_END  This must be the last enum value in this list.
833 : /// The targetspecific preisel opcode values start here.
834 : BUILTIN_OP_END
835 : };
836 :
837 : /// FIRST_TARGET_MEMORY_OPCODE  Targetspecific preisel operations
838 : /// which do not reference a specific memory location should be less than
839 : /// this value. Those that do must not be less than this value, and can
840 : /// be used with SelectionDAG::getMemIntrinsicNode.
841 : static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+300;
842 :
843 : //======//
844 : /// MemIndexedMode enum  This enum defines the load / store indexed
845 : /// addressing modes.
846 : ///
847 : /// UNINDEXED "Normal" load / store. The effective address is already
848 : /// computed and is available in the base pointer. The offset
849 : /// operand is always undefined. In addition to producing a
850 : /// chain, an unindexed load produces one value (result of the
851 : /// load); an unindexed store does not produce a value.
852 : ///
853 : /// PRE_INC Similar to the unindexed mode where the effective address is
854 : /// PRE_DEC the value of the base pointer add / subtract the offset.
855 : /// It considers the computation as being folded into the load /
856 : /// store operation (i.e. the load / store does the address
857 : /// computation as well as performing the memory transaction).
858 : /// The base operand is always undefined. In addition to
859 : /// producing a chain, preindexed load produces two values
860 : /// (result of the load and the result of the address
861 : /// computation); a preindexed store produces one value (result
862 : /// of the address computation).
863 : ///
864 : /// POST_INC The effective address is the value of the base pointer. The
865 : /// POST_DEC value of the offset operand is then added to / subtracted
866 : /// from the base after memory transaction. In addition to
867 : /// producing a chain, postindexed load produces two values
868 : /// (the result of the load and the result of the base +/ offset
869 : /// computation); a postindexed store produces one value (the
870 : /// the result of the base +/ offset computation).
871 : enum MemIndexedMode {
872 : UNINDEXED = 0,
873 : PRE_INC,
874 : PRE_DEC,
875 : POST_INC,
876 : POST_DEC
877 : };
878 :
879 : static const int LAST_INDEXED_MODE = POST_DEC + 1;
880 :
881 : //======//
882 : /// LoadExtType enum  This enum defines the three variants of LOADEXT
883 : /// (load with extension).
884 : ///
885 : /// SEXTLOAD loads the integer operand and sign extends it to a larger
886 : /// integer result type.
887 : /// ZEXTLOAD loads the integer operand and zero extends it to a larger
888 : /// integer result type.
889 : /// EXTLOAD is used for two things: floating point extending loads and
890 : /// integer extending loads [the top bits are undefined].
891 : enum LoadExtType {
892 : NON_EXTLOAD = 0,
893 : EXTLOAD,
894 : SEXTLOAD,
895 : ZEXTLOAD
896 : };
897 :
898 : static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
899 :
900 : NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
901 :
902 : //======//
903 : /// ISD::CondCode enum  These are ordered carefully to make the bitfields
904 : /// below work out, when considering SETFALSE (something that never exists
905 : /// dynamically) as 0. "U" > Unsigned (for integer operands) or Unordered
906 : /// (for floating point), "L" > Less than, "G" > Greater than, "E" > Equal
907 : /// to. If the "N" column is 1, the result of the comparison is undefined if
908 : /// the input is a NAN.
909 : ///
910 : /// All of these (except for the 'always folded ops') should be handled for
911 : /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
912 : /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
913 : ///
914 : /// Note that these are laid out in a specific order to allow bittwiddling
915 : /// to transform conditions.
916 : enum CondCode {
917 : // Opcode N U L G E Intuitive operation
918 : SETFALSE, // 0 0 0 0 Always false (always folded)
919 : SETOEQ, // 0 0 0 1 True if ordered and equal
920 : SETOGT, // 0 0 1 0 True if ordered and greater than
921 : SETOGE, // 0 0 1 1 True if ordered and greater than or equal
922 : SETOLT, // 0 1 0 0 True if ordered and less than
923 : SETOLE, // 0 1 0 1 True if ordered and less than or equal
924 : SETONE, // 0 1 1 0 True if ordered and operands are unequal
925 : SETO, // 0 1 1 1 True if ordered (no nans)
926 : SETUO, // 1 0 0 0 True if unordered: isnan(X)  isnan(Y)
927 : SETUEQ, // 1 0 0 1 True if unordered or equal
928 : SETUGT, // 1 0 1 0 True if unordered or greater than
929 : SETUGE, // 1 0 1 1 True if unordered, greater than, or equal
930 : SETULT, // 1 1 0 0 True if unordered or less than
931 : SETULE, // 1 1 0 1 True if unordered, less than, or equal
932 : SETUNE, // 1 1 1 0 True if unordered or not equal
933 : SETTRUE, // 1 1 1 1 Always true (always folded)
934 : // Don't care operations: undefined if the input is a nan.
935 : SETFALSE2, // 1 X 0 0 0 Always false (always folded)
936 : SETEQ, // 1 X 0 0 1 True if equal
937 : SETGT, // 1 X 0 1 0 True if greater than
938 : SETGE, // 1 X 0 1 1 True if greater than or equal
939 : SETLT, // 1 X 1 0 0 True if less than
940 : SETLE, // 1 X 1 0 1 True if less than or equal
941 : SETNE, // 1 X 1 1 0 True if not equal
942 : SETTRUE2, // 1 X 1 1 1 Always true (always folded)
943 :
944 : SETCC_INVALID // Marker value.
945 : };
946 :
947 : /// Return true if this is a setcc instruction that performs a signed
948 : /// comparison when used with integer operands.
949 : inline bool isSignedIntSetCC(CondCode Code) {
950 304782 : return Code == SETGT  Code == SETGE  Code == SETLT  Code == SETLE;
951 : }
952 :
953 : /// Return true if this is a setcc instruction that performs an unsigned
954 : /// comparison when used with integer operands.
955 : inline bool isUnsignedIntSetCC(CondCode Code) {
956 6101 : return Code == SETUGT  Code == SETUGE  Code == SETULT  Code == SETULE;
957 : }
958 :
959 : /// Return true if the specified condition returns true if the two operands to
960 : /// the condition are equal. Note that if one of the two operands is a NaN,
961 : /// this value is meaningless.
962 : inline bool isTrueWhenEqual(CondCode Cond) {
963 3793 : return ((int)Cond & 1) != 0;
964 : }
965 :
966 : /// This function returns 0 if the condition is always false if an operand is
967 : /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
968 : /// the condition is undefined if the operand is a NaN.
969 : inline unsigned getUnorderedFlavor(CondCode Cond) {
970 515 : return ((int)Cond >> 3) & 3;
971 : }
972 :
973 : /// Return the operation corresponding to !(X op Y), where 'op' is a valid
974 : /// SetCC operation.
975 : CondCode getSetCCInverse(CondCode Operation, bool isInteger);
976 :
977 : /// Return the operation corresponding to (Y op X) when given the operation
978 : /// for (X op Y).
979 : CondCode getSetCCSwappedOperands(CondCode Operation);
980 :
981 : /// Return the result of a logical OR between different comparisons of
982 : /// identical values: ((X op1 Y)  (X op2 Y)). This function returns
983 : /// SETCC_INVALID if it is not possible to represent the resultant comparison.
984 : CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
985 :
986 : /// Return the result of a logical AND between different comparisons of
987 : /// identical values: ((X op1 Y) & (X op2 Y)). This function returns
988 : /// SETCC_INVALID if it is not possible to represent the resultant comparison.
989 : CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
990 :
991 : } // end llvm::ISD namespace
992 :
993 : } // end llvm namespace
994 :
995 : #endif
