LCOV - code coverage report
Current view: top level - include/llvm/CodeGen - MachineInstr.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 155 155 100.0 %
Date: 2018-05-20 00:06:23 Functions: 16 16 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains the declaration of the MachineInstr class, which is the
      11             : // basic representation for all target dependent machine instructions used by
      12             : // the back end.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #ifndef LLVM_CODEGEN_MACHINEINSTR_H
      17             : #define LLVM_CODEGEN_MACHINEINSTR_H
      18             : 
      19             : #include "llvm/ADT/DenseMapInfo.h"
      20             : #include "llvm/ADT/ilist.h"
      21             : #include "llvm/ADT/ilist_node.h"
      22             : #include "llvm/ADT/iterator_range.h"
      23             : #include "llvm/Analysis/AliasAnalysis.h"
      24             : #include "llvm/CodeGen/MachineOperand.h"
      25             : #include "llvm/CodeGen/TargetOpcodes.h"
      26             : #include "llvm/IR/DebugLoc.h"
      27             : #include "llvm/IR/InlineAsm.h"
      28             : #include "llvm/MC/MCInstrDesc.h"
      29             : #include "llvm/Support/ArrayRecycler.h"
      30             : #include <algorithm>
      31             : #include <cassert>
      32             : #include <cstdint>
      33             : #include <utility>
      34             : 
      35             : namespace llvm {
      36             : 
      37             : template <typename T> class ArrayRef;
      38             : class DIExpression;
      39             : class DILocalVariable;
      40             : class MachineBasicBlock;
      41             : class MachineFunction;
      42             : class MachineMemOperand;
      43             : class MachineRegisterInfo;
      44             : class ModuleSlotTracker;
      45             : class raw_ostream;
      46             : template <typename T> class SmallVectorImpl;
      47             : class SmallBitVector;
      48             : class StringRef;
      49             : class TargetInstrInfo;
      50             : class TargetRegisterClass;
      51             : class TargetRegisterInfo;
      52             : 
      53             : //===----------------------------------------------------------------------===//
      54             : /// Representation of each machine instruction.
      55             : ///
      56             : /// This class isn't a POD type, but it must have a trivial destructor. When a
      57             : /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
      58             : /// without having their destructor called.
      59             : ///
      60             : class MachineInstr
      61             :     : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
      62             :                                     ilist_sentinel_tracking<true>> {
      63             : public:
      64             :   using mmo_iterator = MachineMemOperand **;
      65             : 
      66             :   /// Flags to specify different kinds of comments to output in
      67             :   /// assembly code.  These flags carry semantic information not
      68             :   /// otherwise easily derivable from the IR text.
      69             :   ///
      70             :   enum CommentFlag {
      71             :     ReloadReuse = 0x1,    // higher bits are reserved for target dep comments.
      72             :     NoSchedComment = 0x2,
      73             :     TAsmComments = 0x4    // Target Asm comments should start from this value.
      74             :   };
      75             : 
      76             :   enum MIFlag {
      77             :     NoFlags      = 0,
      78             :     FrameSetup   = 1 << 0,              // Instruction is used as a part of
      79             :                                         // function frame setup code.
      80             :     FrameDestroy = 1 << 1,              // Instruction is used as a part of
      81             :                                         // function frame destruction code.
      82             :     BundledPred  = 1 << 2,              // Instruction has bundled predecessors.
      83             :     BundledSucc  = 1 << 3,              // Instruction has bundled successors.
      84             :     FmNoNans     = 1 << 4,              // Instruction does not support Fast
      85             :                                         // math nan values.
      86             :     FmNoInfs     = 1 << 5,              // Instruction does not support Fast
      87             :                                         // math infinity values.
      88             :     FmNsz        = 1 << 6,              // Instruction is not required to retain
      89             :                                         // signed zero values.
      90             :     FmArcp       = 1 << 7,              // Instruction supports Fast math
      91             :                                         // reciprocal approximations.
      92             :     FmContract   = 1 << 8,              // Instruction supports Fast math
      93             :                                         // contraction operations like fma.
      94             :     FmAfn        = 1 << 9,              // Instruction may map to Fast math
      95             :                                         // instrinsic approximation.
      96             :     FmReassoc    = 1 << 10              // Instruction supports Fast math
      97             :                                         // reassociation of operand order.
      98             :   };
      99             : 
     100             : private:
     101             :   const MCInstrDesc *MCID;              // Instruction descriptor.
     102             :   MachineBasicBlock *Parent = nullptr;  // Pointer to the owning basic block.
     103             : 
     104             :   // Operands are allocated by an ArrayRecycler.
     105             :   MachineOperand *Operands = nullptr;   // Pointer to the first operand.
     106             :   unsigned NumOperands = 0;             // Number of operands on instruction.
     107             :   using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
     108             :   OperandCapacity CapOperands;          // Capacity of the Operands array.
     109             : 
     110             :   uint16_t Flags = 0;                   // Various bits of additional
     111             :                                         // information about machine
     112             :                                         // instruction.
     113             : 
     114             :   uint8_t AsmPrinterFlags = 0;          // Various bits of information used by
     115             :                                         // the AsmPrinter to emit helpful
     116             :                                         // comments.  This is *not* semantic
     117             :                                         // information.  Do not use this for
     118             :                                         // anything other than to convey comment
     119             :                                         // information to AsmPrinter.
     120             : 
     121             :   uint8_t NumMemRefs = 0;               // Information on memory references.
     122             :   // Note that MemRefs == nullptr,  means 'don't know', not 'no memory access'.
     123             :   // Calling code must treat missing information conservatively.  If the number
     124             :   // of memory operands required to be precise exceeds the maximum value of
     125             :   // NumMemRefs - currently 256 - we remove the operands entirely. Note also
     126             :   // that this is a non-owning reference to a shared copy on write buffer owned
     127             :   // by the MachineFunction and created via MF.allocateMemRefsArray.
     128             :   mmo_iterator MemRefs = nullptr;
     129             : 
     130             :   DebugLoc debugLoc;                    // Source line information.
     131             : 
     132             :   // Intrusive list support
     133             :   friend struct ilist_traits<MachineInstr>;
     134             :   friend struct ilist_callback_traits<MachineBasicBlock>;
     135    12201689 :   void setParent(MachineBasicBlock *P) { Parent = P; }
     136             : 
     137             :   /// This constructor creates a copy of the given
     138             :   /// MachineInstr in the given MachineFunction.
     139             :   MachineInstr(MachineFunction &, const MachineInstr &);
     140             : 
     141             :   /// This constructor create a MachineInstr and add the implicit operands.
     142             :   /// It reserves space for number of operands specified by
     143             :   /// MCInstrDesc.  An explicit DebugLoc is supplied.
     144             :   MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
     145             :                bool NoImp = false);
     146             : 
     147             :   // MachineInstrs are pool-allocated and owned by MachineFunction.
     148             :   friend class MachineFunction;
     149             : 
     150             : public:
     151             :   MachineInstr(const MachineInstr &) = delete;
     152             :   MachineInstr &operator=(const MachineInstr &) = delete;
     153             :   // Use MachineFunction::DeleteMachineInstr() instead.
     154             :   ~MachineInstr() = delete;
     155             : 
     156             :   const MachineBasicBlock* getParent() const { return Parent; }
     157             :   MachineBasicBlock* getParent() { return Parent; }
     158             : 
     159             :   /// Return the function that contains the basic block that this instruction
     160             :   /// belongs to.
     161             :   ///
     162             :   /// Note: this is undefined behaviour if the instruction does not have a
     163             :   /// parent.
     164             :   const MachineFunction *getMF() const;
     165             :   MachineFunction *getMF() {
     166             :     return const_cast<MachineFunction *>(
     167    10654519 :         static_cast<const MachineInstr *>(this)->getMF());
     168             :   }
     169             : 
     170             :   /// Return the asm printer flags bitvector.
     171             :   uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
     172             : 
     173             :   /// Clear the AsmPrinter bitvector.
     174             :   void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
     175             : 
     176             :   /// Return whether an AsmPrinter flag is set.
     177             :   bool getAsmPrinterFlag(CommentFlag Flag) const {
     178             :     return AsmPrinterFlags & Flag;
     179             :   }
     180             : 
     181             :   /// Set a flag for the AsmPrinter.
     182             :   void setAsmPrinterFlag(uint8_t Flag) {
     183       22923 :     AsmPrinterFlags |= Flag;
     184             :   }
     185             : 
     186             :   /// Clear specific AsmPrinter flags.
     187             :   void clearAsmPrinterFlag(CommentFlag Flag) {
     188             :     AsmPrinterFlags &= ~Flag;
     189             :   }
     190             : 
     191             :   /// Return the MI flags bitvector.
     192             :   uint8_t getFlags() const {
     193        2142 :     return Flags;
     194             :   }
     195             : 
     196             :   /// Return whether an MI flag is set.
     197             :   bool getFlag(MIFlag Flag) const {
     198    21828327 :     return Flags & Flag;
     199             :   }
     200             : 
     201             :   /// Set a MI flag.
     202             :   void setFlag(MIFlag Flag) {
     203      420004 :     Flags |= (uint16_t)Flag;
     204             :   }
     205             : 
     206             :   void setFlags(unsigned flags) {
     207             :     // Filter out the automatically maintained flags.
     208             :     unsigned Mask = BundledPred | BundledSucc;
     209      171353 :     Flags = (Flags & Mask) | (flags & ~Mask);
     210             :   }
     211             : 
     212             :   /// clearFlag - Clear a MI flag.
     213             :   void clearFlag(MIFlag Flag) {
     214       79169 :     Flags &= ~((uint16_t)Flag);
     215             :   }
     216             : 
     217             :   /// Return true if MI is in a bundle (but not the first MI in a bundle).
     218             :   ///
     219             :   /// A bundle looks like this before it's finalized:
     220             :   ///   ----------------
     221             :   ///   |      MI      |
     222             :   ///   ----------------
     223             :   ///          |
     224             :   ///   ----------------
     225             :   ///   |      MI    * |
     226             :   ///   ----------------
     227             :   ///          |
     228             :   ///   ----------------
     229             :   ///   |      MI    * |
     230             :   ///   ----------------
     231             :   /// In this case, the first MI starts a bundle but is not inside a bundle, the
     232             :   /// next 2 MIs are considered "inside" the bundle.
     233             :   ///
     234             :   /// After a bundle is finalized, it looks like this:
     235             :   ///   ----------------
     236             :   ///   |    Bundle    |
     237             :   ///   ----------------
     238             :   ///          |
     239             :   ///   ----------------
     240             :   ///   |      MI    * |
     241             :   ///   ----------------
     242             :   ///          |
     243             :   ///   ----------------
     244             :   ///   |      MI    * |
     245             :   ///   ----------------
     246             :   ///          |
     247             :   ///   ----------------
     248             :   ///   |      MI    * |
     249             :   ///   ----------------
     250             :   /// The first instruction has the special opcode "BUNDLE". It's not "inside"
     251             :   /// a bundle, but the next three MIs are.
     252             :   bool isInsideBundle() const {
     253    43365283 :     return getFlag(BundledPred);
     254             :   }
     255             : 
     256             :   /// Return true if this instruction part of a bundle. This is true
     257             :   /// if either itself or its following instruction is marked "InsideBundle".
     258             :   bool isBundled() const {
     259   269118533 :     return isBundledWithPred() || isBundledWithSucc();
     260             :   }
     261             : 
     262             :   /// Return true if this instruction is part of a bundle, and it is not the
     263             :   /// first instruction in the bundle.
     264   417098872 :   bool isBundledWithPred() const { return getFlag(BundledPred); }
     265             : 
     266             :   /// Return true if this instruction is part of a bundle, and it is not the
     267             :   /// last instruction in the bundle.
     268   250837714 :   bool isBundledWithSucc() const { return getFlag(BundledSucc); }
     269             : 
     270             :   /// Bundle this instruction with its predecessor. This can be an unbundled
     271             :   /// instruction, or it can be the first instruction in a bundle.
     272             :   void bundleWithPred();
     273             : 
     274             :   /// Bundle this instruction with its successor. This can be an unbundled
     275             :   /// instruction, or it can be the last instruction in a bundle.
     276             :   void bundleWithSucc();
     277             : 
     278             :   /// Break bundle above this instruction.
     279             :   void unbundleFromPred();
     280             : 
     281             :   /// Break bundle below this instruction.
     282             :   void unbundleFromSucc();
     283             : 
     284             :   /// Returns the debug location id of this MachineInstr.
     285    10085907 :   const DebugLoc &getDebugLoc() const { return debugLoc; }
     286             : 
     287             :   /// Return the debug variable referenced by
     288             :   /// this DBG_VALUE instruction.
     289             :   const DILocalVariable *getDebugVariable() const;
     290             : 
     291             :   /// Return the complex address expression referenced by
     292             :   /// this DBG_VALUE instruction.
     293             :   const DIExpression *getDebugExpression() const;
     294             : 
     295             :   /// Return the debug label referenced by
     296             :   /// this DBG_LABEL instruction.
     297             :   const DILabel *getDebugLabel() const;
     298             : 
     299             :   /// Emit an error referring to the source location of this instruction.
     300             :   /// This should only be used for inline assembly that is somehow
     301             :   /// impossible to compile. Other errors should have been handled much
     302             :   /// earlier.
     303             :   ///
     304             :   /// If this method returns, the caller should try to recover from the error.
     305             :   void emitError(StringRef Msg) const;
     306             : 
     307             :   /// Returns the target instruction descriptor of this MachineInstr.
     308             :   const MCInstrDesc &getDesc() const { return *MCID; }
     309             : 
     310             :   /// Returns the opcode of this MachineInstr.
     311   841280600 :   unsigned getOpcode() const { return MCID->Opcode; }
     312             : 
     313             :   /// Access to explicit operands of the instruction.
     314             :   unsigned getNumOperands() const { return NumOperands; }
     315             : 
     316             :   const MachineOperand& getOperand(unsigned i) const {
     317             :     assert(i < getNumOperands() && "getOperand() out of range!");
     318   400017539 :     return Operands[i];
     319             :   }
     320             :   MachineOperand& getOperand(unsigned i) {
     321             :     assert(i < getNumOperands() && "getOperand() out of range!");
     322   288788128 :     return Operands[i];
     323             :   }
     324             : 
     325             :   /// Return true if operand \p OpIdx is a subregister index.
     326       63390 :   bool isOperandSubregIdx(unsigned OpIdx) const {
     327             :     assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&
     328             :            "Expected MO_Immediate operand type.");
     329       63390 :     if (isExtractSubreg() && OpIdx == 2)
     330             :       return true;
     331       63380 :     if (isInsertSubreg() && OpIdx == 3)
     332             :       return true;
     333       63293 :     if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
     334             :       return true;
     335       62953 :     if (isSubregToReg() && OpIdx == 3)
     336             :       return true;
     337             :     return false;
     338             :   }
     339             : 
     340             :   /// Returns the number of non-implicit operands.
     341             :   unsigned getNumExplicitOperands() const;
     342             : 
     343             :   /// iterator/begin/end - Iterate over all operands of a machine instruction.
     344             :   using mop_iterator = MachineOperand *;
     345             :   using const_mop_iterator = const MachineOperand *;
     346             : 
     347             :   mop_iterator operands_begin() { return Operands; }
     348    66955040 :   mop_iterator operands_end() { return Operands + NumOperands; }
     349             : 
     350             :   const_mop_iterator operands_begin() const { return Operands; }
     351    36342562 :   const_mop_iterator operands_end() const { return Operands + NumOperands; }
     352             : 
     353             :   iterator_range<mop_iterator> operands() {
     354    44348915 :     return make_range(operands_begin(), operands_end());
     355             :   }
     356             :   iterator_range<const_mop_iterator> operands() const {
     357    31959947 :     return make_range(operands_begin(), operands_end());
     358             :   }
     359             :   iterator_range<mop_iterator> explicit_operands() {
     360             :     return make_range(operands_begin(),
     361      815897 :                       operands_begin() + getNumExplicitOperands());
     362             :   }
     363             :   iterator_range<const_mop_iterator> explicit_operands() const {
     364             :     return make_range(operands_begin(),
     365     4258705 :                       operands_begin() + getNumExplicitOperands());
     366             :   }
     367             :   iterator_range<mop_iterator> implicit_operands() {
     368      815025 :     return make_range(explicit_operands().end(), operands_end());
     369             :   }
     370             :   iterator_range<const_mop_iterator> implicit_operands() const {
     371     3825145 :     return make_range(explicit_operands().end(), operands_end());
     372             :   }
     373             :   /// Returns a range over all explicit operands that are register definitions.
     374             :   /// Implicit definition are not included!
     375             :   iterator_range<mop_iterator> defs() {
     376             :     return make_range(operands_begin(),
     377      442861 :                       operands_begin() + getDesc().getNumDefs());
     378             :   }
     379             :   /// \copydoc defs()
     380             :   iterator_range<const_mop_iterator> defs() const {
     381             :     return make_range(operands_begin(),
     382     1002138 :                       operands_begin() + getDesc().getNumDefs());
     383             :   }
     384             :   /// Returns a range that includes all operands that are register uses.
     385             :   /// This may include unrelated operands which are not register uses.
     386             :   iterator_range<mop_iterator> uses() {
     387      303373 :     return make_range(operands_begin() + getDesc().getNumDefs(),
     388      606746 :                       operands_end());
     389             :   }
     390             :   /// \copydoc uses()
     391             :   iterator_range<const_mop_iterator> uses() const {
     392      487767 :     return make_range(operands_begin() + getDesc().getNumDefs(),
     393      975534 :                       operands_end());
     394             :   }
     395        1509 :   iterator_range<mop_iterator> explicit_uses() {
     396        1509 :     return make_range(operands_begin() + getDesc().getNumDefs(),
     397        3018 :                       operands_begin() + getNumExplicitOperands() );
     398             :   }
     399             :   iterator_range<const_mop_iterator> explicit_uses() const {
     400             :     return make_range(operands_begin() + getDesc().getNumDefs(),
     401             :                       operands_begin() + getNumExplicitOperands() );
     402             :   }
     403             : 
     404             :   /// Returns the number of the operand iterator \p I points to.
     405             :   unsigned getOperandNo(const_mop_iterator I) const {
     406     1145261 :     return I - operands_begin();
     407             :   }
     408             : 
     409             :   /// Access to memory operands of the instruction
     410             :   mmo_iterator memoperands_begin() const { return MemRefs; }
     411    38231626 :   mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
     412             :   /// Return true if we don't have any memory operands which described the
     413             :   /// memory access done by this instruction.  If this is true, calling code
     414             :   /// must be conservative.
     415             :   bool memoperands_empty() const { return NumMemRefs == 0; }
     416             : 
     417             :   iterator_range<mmo_iterator>  memoperands() {
     418     3563846 :     return make_range(memoperands_begin(), memoperands_end());
     419             :   }
     420             :   iterator_range<mmo_iterator> memoperands() const {
     421     7952445 :     return make_range(memoperands_begin(), memoperands_end());
     422             :   }
     423             : 
     424             :   /// Return true if this instruction has exactly one MachineMemOperand.
     425             :   bool hasOneMemOperand() const {
     426          15 :     return NumMemRefs == 1;
     427             :   }
     428             : 
     429             :   /// Return the number of memory operands.
     430             :   unsigned getNumMemOperands() const { return NumMemRefs; }
     431             : 
     432             :   /// API for querying MachineInstr properties. They are the same as MCInstrDesc
     433             :   /// queries but they are bundle aware.
     434             : 
     435             :   enum QueryType {
     436             :     IgnoreBundle,    // Ignore bundles
     437             :     AnyInBundle,     // Return true if any instruction in bundle has property
     438             :     AllInBundle      // Return true if all instructions in bundle have property
     439             :   };
     440             : 
     441             :   /// Return true if the instruction (or in the case of a bundle,
     442             :   /// the instructions inside the bundle) has the specified property.
     443             :   /// The first argument is the property being queried.
     444             :   /// The second argument indicates whether the query should look inside
     445             :   /// instruction bundles.
     446   367817052 :   bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
     447             :     // Inline the fast path for unbundled or bundle-internal instructions.
     448   368055936 :     if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
     449   367584835 :       return getDesc().getFlags() & (1ULL << MCFlag);
     450             : 
     451             :     // If this is the first instruction in a bundle, take the slow path.
     452      232217 :     return hasPropertyInBundle(1ULL << MCFlag, Type);
     453             :   }
     454             : 
     455             :   /// Return true if this instruction can have a variable number of operands.
     456             :   /// In this case, the variable operands will be after the normal
     457             :   /// operands but before the implicit definitions and uses (if any are
     458             :   /// present).
     459             :   bool isVariadic(QueryType Type = IgnoreBundle) const {
     460    35960354 :     return hasProperty(MCID::Variadic, Type);
     461             :   }
     462             : 
     463             :   /// Set if this instruction has an optional definition, e.g.
     464             :   /// ARM instructions which can set condition code if 's' bit is set.
     465             :   bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
     466        6989 :     return hasProperty(MCID::HasOptionalDef, Type);
     467             :   }
     468             : 
     469             :   /// Return true if this is a pseudo instruction that doesn't
     470             :   /// correspond to a real machine instruction.
     471             :   bool isPseudo(QueryType Type = IgnoreBundle) const {
     472     4064855 :     return hasProperty(MCID::Pseudo, Type);
     473             :   }
     474             : 
     475             :   bool isReturn(QueryType Type = AnyInBundle) const {
     476     4802844 :     return hasProperty(MCID::Return, Type);
     477             :   }
     478             : 
     479             :   bool isCall(QueryType Type = AnyInBundle) const {
     480    47779808 :     return hasProperty(MCID::Call, Type);
     481             :   }
     482             : 
     483             :   /// Returns true if the specified instruction stops control flow
     484             :   /// from executing the instruction immediately following it.  Examples include
     485             :   /// unconditional branches and return instructions.
     486             :   bool isBarrier(QueryType Type = AnyInBundle) const {
     487     7735010 :     return hasProperty(MCID::Barrier, Type);
     488             :   }
     489             : 
     490             :   /// Returns true if this instruction part of the terminator for a basic block.
     491             :   /// Typically this is things like return and branch instructions.
     492             :   ///
     493             :   /// Various passes use this to insert code into the bottom of a basic block,
     494             :   /// but before control flow occurs.
     495             :   bool isTerminator(QueryType Type = AnyInBundle) const {
     496    62331786 :     return hasProperty(MCID::Terminator, Type);
     497             :   }
     498             : 
     499             :   /// Returns true if this is a conditional, unconditional, or indirect branch.
     500             :   /// Predicates below can be used to discriminate between
     501             :   /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
     502             :   /// get more information.
     503             :   bool isBranch(QueryType Type = AnyInBundle) const {
     504    12683963 :     return hasProperty(MCID::Branch, Type);
     505             :   }
     506             : 
     507             :   /// Return true if this is an indirect branch, such as a
     508             :   /// branch through a register.
     509             :   bool isIndirectBranch(QueryType Type = AnyInBundle) const {
     510     4807188 :     return hasProperty(MCID::IndirectBranch, Type);
     511             :   }
     512             : 
     513             :   /// Return true if this is a branch which may fall
     514             :   /// through to the next instruction or may transfer control flow to some other
     515             :   /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
     516             :   /// information about this branch.
     517     3824277 :   bool isConditionalBranch(QueryType Type = AnyInBundle) const {
     518     7648554 :     return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
     519             :   }
     520             : 
     521             :   /// Return true if this is a branch which always
     522             :   /// transfers control flow to some other block.  The
     523             :   /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
     524             :   /// about this branch.
     525      366021 :   bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
     526      366021 :     return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
     527             :   }
     528             : 
     529             :   /// Return true if this instruction has a predicate operand that
     530             :   /// controls execution.  It may be set to 'always', or may be set to other
     531             :   /// values.   There are various methods in TargetInstrInfo that can be used to
     532             :   /// control and modify the predicate in this instruction.
     533             :   bool isPredicable(QueryType Type = AllInBundle) const {
     534             :     // If it's a bundle than all bundled instructions must be predicable for this
     535             :     // to return true.
     536     2069389 :     return hasProperty(MCID::Predicable, Type);
     537             :   }
     538             : 
     539             :   /// Return true if this instruction is a comparison.
     540             :   bool isCompare(QueryType Type = IgnoreBundle) const {
     541     4521076 :     return hasProperty(MCID::Compare, Type);
     542             :   }
     543             : 
     544             :   /// Return true if this instruction is a move immediate
     545             :   /// (including conditional moves) instruction.
     546             :   bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
     547     3840475 :     return hasProperty(MCID::MoveImm, Type);
     548             :   }
     549             : 
     550             :   /// Return true if this instruction is a bitcast instruction.
     551             :   bool isBitcast(QueryType Type = IgnoreBundle) const {
     552     4851829 :     return hasProperty(MCID::Bitcast, Type);
     553             :   }
     554             : 
     555             :   /// Return true if this instruction is a select instruction.
     556             :   bool isSelect(QueryType Type = IgnoreBundle) const {
     557     3720054 :     return hasProperty(MCID::Select, Type);
     558             :   }
     559             : 
     560             :   /// Return true if this instruction cannot be safely duplicated.
     561             :   /// For example, if the instruction has a unique labels attached
     562             :   /// to it, duplicating it would cause multiple definition errors.
     563             :   bool isNotDuplicable(QueryType Type = AnyInBundle) const {
     564     1124221 :     return hasProperty(MCID::NotDuplicable, Type);
     565             :   }
     566             : 
     567             :   /// Return true if this instruction is convergent.
     568             :   /// Convergent instructions can not be made control-dependent on any
     569             :   /// additional values.
     570     2258926 :   bool isConvergent(QueryType Type = AnyInBundle) const {
     571     2258926 :     if (isInlineAsm()) {
     572         610 :       unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
     573         610 :       if (ExtraInfo & InlineAsm::Extra_IsConvergent)
     574             :         return true;
     575             :     }
     576     2258924 :     return hasProperty(MCID::Convergent, Type);
     577             :   }
     578             : 
     579             :   /// Returns true if the specified instruction has a delay slot
     580             :   /// which must be filled by the code generator.
     581             :   bool hasDelaySlot(QueryType Type = AnyInBundle) const {
     582      132746 :     return hasProperty(MCID::DelaySlot, Type);
     583             :   }
     584             : 
     585             :   /// Return true for instructions that can be folded as
     586             :   /// memory operands in other instructions. The most common use for this
     587             :   /// is instructions that are simple loads from memory that don't modify
     588             :   /// the loaded value in any way, but it can also be used for instructions
     589             :   /// that can be expressed as constant-pool loads, such as V_SETALLONES
     590             :   /// on x86, to allow them to be folded when it is beneficial.
     591             :   /// This should only be set on instructions that return a value in their
     592             :   /// only virtual register definition.
     593             :   bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
     594     4072470 :     return hasProperty(MCID::FoldableAsLoad, Type);
     595             :   }
     596             : 
     597             :   /// Return true if this instruction behaves
     598             :   /// the same way as the generic REG_SEQUENCE instructions.
     599             :   /// E.g., on ARM,
     600             :   /// dX VMOVDRR rY, rZ
     601             :   /// is equivalent to
     602             :   /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
     603             :   ///
     604             :   /// Note that for the optimizers to be able to take advantage of
     605             :   /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
     606             :   /// override accordingly.
     607             :   bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
     608     4661123 :     return hasProperty(MCID::RegSequence, Type);
     609             :   }
     610             : 
     611             :   /// Return true if this instruction behaves
     612             :   /// the same way as the generic EXTRACT_SUBREG instructions.
     613             :   /// E.g., on ARM,
     614             :   /// rX, rY VMOVRRD dZ
     615             :   /// is equivalent to two EXTRACT_SUBREG:
     616             :   /// rX = EXTRACT_SUBREG dZ, ssub_0
     617             :   /// rY = EXTRACT_SUBREG dZ, ssub_1
     618             :   ///
     619             :   /// Note that for the optimizers to be able to take advantage of
     620             :   /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
     621             :   /// override accordingly.
     622             :   bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
     623     4633657 :     return hasProperty(MCID::ExtractSubreg, Type);
     624             :   }
     625             : 
     626             :   /// Return true if this instruction behaves
     627             :   /// the same way as the generic INSERT_SUBREG instructions.
     628             :   /// E.g., on ARM,
     629             :   /// dX = VSETLNi32 dY, rZ, Imm
     630             :   /// is equivalent to a INSERT_SUBREG:
     631             :   /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
     632             :   ///
     633             :   /// Note that for the optimizers to be able to take advantage of
     634             :   /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
     635             :   /// override accordingly.
     636             :   bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
     637     4634024 :     return hasProperty(MCID::InsertSubreg, Type);
     638             :   }
     639             : 
     640             :   //===--------------------------------------------------------------------===//
     641             :   // Side Effect Analysis
     642             :   //===--------------------------------------------------------------------===//
     643             : 
     644             :   /// Return true if this instruction could possibly read memory.
     645             :   /// Instructions with this flag set are not necessarily simple load
     646             :   /// instructions, they may load a value and modify it, for example.
     647    43992396 :   bool mayLoad(QueryType Type = AnyInBundle) const {
     648    43992396 :     if (isInlineAsm()) {
     649       41513 :       unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
     650       41513 :       if (ExtraInfo & InlineAsm::Extra_MayLoad)
     651             :         return true;
     652             :     }
     653    43973126 :     return hasProperty(MCID::MayLoad, Type);
     654             :   }
     655             : 
     656             :   /// Return true if this instruction could possibly modify memory.
     657             :   /// Instructions with this flag set are not necessarily simple store
     658             :   /// instructions, they may store a modified value based on their operands, or
     659             :   /// may not actually modify anything, for example.
     660    47465106 :   bool mayStore(QueryType Type = AnyInBundle) const {
     661    47465106 :     if (isInlineAsm()) {
     662       43864 :       unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
     663       43864 :       if (ExtraInfo & InlineAsm::Extra_MayStore)
     664             :         return true;
     665             :     }
     666    47460054 :     return hasProperty(MCID::MayStore, Type);
     667             :   }
     668             : 
     669             :   /// Return true if this instruction could possibly read or modify memory.
     670      315924 :   bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
     671      315924 :     return mayLoad(Type) || mayStore(Type);
     672             :   }
     673             : 
     674             :   //===--------------------------------------------------------------------===//
     675             :   // Flags that indicate whether an instruction can be modified by a method.
     676             :   //===--------------------------------------------------------------------===//
     677             : 
     678             :   /// Return true if this may be a 2- or 3-address
     679             :   /// instruction (of the form "X = op Y, Z, ..."), which produces the same
     680             :   /// result if Y and Z are exchanged.  If this flag is set, then the
     681             :   /// TargetInstrInfo::commuteInstruction method may be used to hack on the
     682             :   /// instruction.
     683             :   ///
     684             :   /// Note that this flag may be set on instructions that are only commutable
     685             :   /// sometimes.  In these cases, the call to commuteInstruction will fail.
     686             :   /// Also note that some instructions require non-trivial modification to
     687             :   /// commute them.
     688             :   bool isCommutable(QueryType Type = IgnoreBundle) const {
     689     5359748 :     return hasProperty(MCID::Commutable, Type);
     690             :   }
     691             : 
     692             :   /// Return true if this is a 2-address instruction
     693             :   /// which can be changed into a 3-address instruction if needed.  Doing this
     694             :   /// transformation can be profitable in the register allocator, because it
     695             :   /// means that the instruction can use a 2-address form if possible, but
     696             :   /// degrade into a less efficient form if the source and dest register cannot
     697             :   /// be assigned to the same register.  For example, this allows the x86
     698             :   /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
     699             :   /// is the same speed as the shift but has bigger code size.
     700             :   ///
     701             :   /// If this returns true, then the target must implement the
     702             :   /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
     703             :   /// is allowed to fail if the transformation isn't valid for this specific
     704             :   /// instruction (e.g. shl reg, 4 on x86).
     705             :   ///
     706             :   bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
     707      244252 :     return hasProperty(MCID::ConvertibleTo3Addr, Type);
     708             :   }
     709             : 
     710             :   /// Return true if this instruction requires
     711             :   /// custom insertion support when the DAG scheduler is inserting it into a
     712             :   /// machine basic block.  If this is true for the instruction, it basically
     713             :   /// means that it is a pseudo instruction used at SelectionDAG time that is
     714             :   /// expanded out into magic code by the target when MachineInstrs are formed.
     715             :   ///
     716             :   /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
     717             :   /// is used to insert this into the MachineBasicBlock.
     718             :   bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
     719     5230900 :     return hasProperty(MCID::UsesCustomInserter, Type);
     720             :   }
     721             : 
     722             :   /// Return true if this instruction requires *adjustment*
     723             :   /// after instruction selection by calling a target hook. For example, this
     724             :   /// can be used to fill in ARM 's' optional operand depending on whether
     725             :   /// the conditional flag register is used.
     726             :   bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
     727             :     return hasProperty(MCID::HasPostISelHook, Type);
     728             :   }
     729             : 
     730             :   /// Returns true if this instruction is a candidate for remat.
     731             :   /// This flag is deprecated, please don't use it anymore.  If this
     732             :   /// flag is set, the isReallyTriviallyReMaterializable() method is called to
     733             :   /// verify the instruction is really rematable.
     734             :   bool isRematerializable(QueryType Type = AllInBundle) const {
     735             :     // It's only possible to re-mat a bundle if all bundled instructions are
     736             :     // re-materializable.
     737             :     return hasProperty(MCID::Rematerializable, Type);
     738             :   }
     739             : 
     740             :   /// Returns true if this instruction has the same cost (or less) than a move
     741             :   /// instruction. This is useful during certain types of optimizations
     742             :   /// (e.g., remat during two-address conversion or machine licm)
     743             :   /// where we would like to remat or hoist the instruction, but not if it costs
     744             :   /// more than moving the instruction into the appropriate register. Note, we
     745             :   /// are not marking copies from and to the same register class with this flag.
     746             :   bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
     747             :     // Only returns true for a bundle if all bundled instructions are cheap.
     748      627552 :     return hasProperty(MCID::CheapAsAMove, Type);
     749             :   }
     750             : 
     751             :   /// Returns true if this instruction source operands
     752             :   /// have special register allocation requirements that are not captured by the
     753             :   /// operand register classes. e.g. ARM::STRD's two source registers must be an
     754             :   /// even / odd pair, ARM::STM registers have to be in ascending order.
     755             :   /// Post-register allocation passes should not attempt to change allocations
     756             :   /// for sources of instructions with this flag.
     757             :   bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
     758     9207948 :     return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
     759             :   }
     760             : 
     761             :   /// Returns true if this instruction def operands
     762             :   /// have special register allocation requirements that are not captured by the
     763             :   /// operand register classes. e.g. ARM::LDRD's two def registers must be an
     764             :   /// even / odd pair, ARM::LDM registers have to be in ascending order.
     765             :   /// Post-register allocation passes should not attempt to change allocations
     766             :   /// for definitions of instructions with this flag.
     767             :   bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
     768     6464758 :     return hasProperty(MCID::ExtraDefRegAllocReq, Type);
     769             :   }
     770             : 
     771             :   enum MICheckType {
     772             :     CheckDefs,      // Check all operands for equality
     773             :     CheckKillDead,  // Check all operands including kill / dead markers
     774             :     IgnoreDefs,     // Ignore all definitions
     775             :     IgnoreVRegDefs  // Ignore virtual register definitions
     776             :   };
     777             : 
     778             :   /// Return true if this instruction is identical to \p Other.
     779             :   /// Two instructions are identical if they have the same opcode and all their
     780             :   /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
     781             :   /// Note that this means liveness related flags (dead, undef, kill) do not
     782             :   /// affect the notion of identical.
     783             :   bool isIdenticalTo(const MachineInstr &Other,
     784             :                      MICheckType Check = CheckDefs) const;
     785             : 
     786             :   /// Unlink 'this' from the containing basic block, and return it without
     787             :   /// deleting it.
     788             :   ///
     789             :   /// This function can not be used on bundled instructions, use
     790             :   /// removeFromBundle() to remove individual instructions from a bundle.
     791             :   MachineInstr *removeFromParent();
     792             : 
     793             :   /// Unlink this instruction from its basic block and return it without
     794             :   /// deleting it.
     795             :   ///
     796             :   /// If the instruction is part of a bundle, the other instructions in the
     797             :   /// bundle remain bundled.
     798             :   MachineInstr *removeFromBundle();
     799             : 
     800             :   /// Unlink 'this' from the containing basic block and delete it.
     801             :   ///
     802             :   /// If this instruction is the header of a bundle, the whole bundle is erased.
     803             :   /// This function can not be used for instructions inside a bundle, use
     804             :   /// eraseFromBundle() to erase individual bundled instructions.
     805             :   void eraseFromParent();
     806             : 
     807             :   /// Unlink 'this' from the containing basic block and delete it.
     808             :   ///
     809             :   /// For all definitions mark their uses in DBG_VALUE nodes
     810             :   /// as undefined. Otherwise like eraseFromParent().
     811             :   void eraseFromParentAndMarkDBGValuesForRemoval();
     812             : 
     813             :   /// Unlink 'this' form its basic block and delete it.
     814             :   ///
     815             :   /// If the instruction is part of a bundle, the other instructions in the
     816             :   /// bundle remain bundled.
     817             :   void eraseFromBundle();
     818             : 
     819    26499010 :   bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
     820             :   bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
     821             :   bool isAnnotationLabel() const {
     822             :     return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
     823             :   }
     824             : 
     825             :   /// Returns true if the MachineInstr represents a label.
     826             :   bool isLabel() const {
     827    32353645 :     return isEHLabel() || isGCLabel() || isAnnotationLabel();
     828             :   }
     829             : 
     830             :   bool isCFIInstruction() const {
     831     3826614 :     return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
     832             :   }
     833             : 
     834             :   // True if the instruction represents a position in the function.
     835    27771123 :   bool isPosition() const { return isLabel() || isCFIInstruction(); }
     836             : 
     837   149564055 :   bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
     838             :   bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
     839   109849263 :   bool isDebugInstr() const { return isDebugValue() || isDebugLabel(); }
     840             : 
     841             :   /// A DBG_VALUE is indirect iff the first operand is a register and
     842             :   /// the second operand is an immediate.
     843             :   bool isIndirectDebugValue() const {
     844             :     return isDebugValue()
     845      121757 :       && getOperand(0).isReg()
     846      159418 :       && getOperand(1).isImm();
     847             :   }
     848             : 
     849             :   bool isPHI() const {
     850   121791048 :     return getOpcode() == TargetOpcode::PHI ||
     851             :            getOpcode() == TargetOpcode::G_PHI;
     852             :   }
     853      814629 :   bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
     854    12922981 :   bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
     855   200291709 :   bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
     856             : 
     857             :   bool isMSInlineAsm() const {
     858             :     return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
     859             :   }
     860             : 
     861             :   bool isStackAligningInlineAsm() const;
     862             :   InlineAsm::AsmDialect getInlineAsmDialect() const;
     863             : 
     864             :   bool isInsertSubreg() const {
     865      562873 :     return getOpcode() == TargetOpcode::INSERT_SUBREG;
     866             :   }
     867             : 
     868             :   bool isSubregToReg() const {
     869      237498 :     return getOpcode() == TargetOpcode::SUBREG_TO_REG;
     870             :   }
     871             : 
     872             :   bool isRegSequence() const {
     873     5556813 :     return getOpcode() == TargetOpcode::REG_SEQUENCE;
     874             :   }
     875             : 
     876             :   bool isBundle() const {
     877     6503998 :     return getOpcode() == TargetOpcode::BUNDLE;
     878             :   }
     879             : 
     880             :   bool isCopy() const {
     881    83659227 :     return getOpcode() == TargetOpcode::COPY;
     882             :   }
     883             : 
     884             :   bool isFullCopy() const {
     885     2944021 :     return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
     886             :   }
     887             : 
     888             :   bool isExtractSubreg() const {
     889      302213 :     return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
     890             :   }
     891             : 
     892             :   /// Return true if the instruction behaves like a copy.
     893             :   /// This does not include native copy instructions.
     894             :   bool isCopyLike() const {
     895     9685373 :     return isCopy() || isSubregToReg();
     896             :   }
     897             : 
     898             :   /// Return true is the instruction is an identity copy.
     899             :   bool isIdentityCopy() const {
     900     8500535 :     return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
     901             :       getOperand(0).getSubReg() == getOperand(1).getSubReg();
     902             :   }
     903             : 
     904             :   /// Return true if this instruction doesn't produce any output in the form of
     905             :   /// executable instructions.
     906             :   bool isMetaInstruction() const {
     907     7156303 :     switch (getOpcode()) {
     908             :     default:
     909             :       return false;
     910             :     case TargetOpcode::IMPLICIT_DEF:
     911             :     case TargetOpcode::KILL:
     912             :     case TargetOpcode::CFI_INSTRUCTION:
     913             :     case TargetOpcode::EH_LABEL:
     914             :     case TargetOpcode::GC_LABEL:
     915             :     case TargetOpcode::DBG_VALUE:
     916             :     case TargetOpcode::DBG_LABEL:
     917             :     case TargetOpcode::LIFETIME_START:
     918             :     case TargetOpcode::LIFETIME_END:
     919             :       return true;
     920             :     }
     921             :   }
     922             : 
     923             :   /// Return true if this is a transient instruction that is either very likely
     924             :   /// to be eliminated during register allocation (such as copy-like
     925             :   /// instructions), or if this instruction doesn't have an execution-time cost.
     926             :   bool isTransient() const {
     927    12782020 :     switch (getOpcode()) {
     928             :     default:
     929             :       return isMetaInstruction();
     930             :     // Copy-like instructions are usually eliminated during register allocation.
     931             :     case TargetOpcode::PHI:
     932             :     case TargetOpcode::G_PHI:
     933             :     case TargetOpcode::COPY:
     934             :     case TargetOpcode::INSERT_SUBREG:
     935             :     case TargetOpcode::SUBREG_TO_REG:
     936             :     case TargetOpcode::REG_SEQUENCE:
     937             :       return true;
     938             :     }
     939             :   }
     940             : 
     941             :   /// Return the number of instructions inside the MI bundle, excluding the
     942             :   /// bundle header.
     943             :   ///
     944             :   /// This is the number of instructions that MachineBasicBlock::iterator
     945             :   /// skips, 0 for unbundled instructions.
     946             :   unsigned getBundleSize() const;
     947             : 
     948             :   /// Return true if the MachineInstr reads the specified register.
     949             :   /// If TargetRegisterInfo is passed, then it also checks if there
     950             :   /// is a read of a super-register.
     951             :   /// This does not count partial redefines of virtual registers as reads:
     952             :   ///   %reg1024:6 = OP.
     953             :   bool readsRegister(unsigned Reg,
     954             :                      const TargetRegisterInfo *TRI = nullptr) const {
     955     1167055 :     return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
     956             :   }
     957             : 
     958             :   /// Return true if the MachineInstr reads the specified virtual register.
     959             :   /// Take into account that a partial define is a
     960             :   /// read-modify-write operation.
     961             :   bool readsVirtualRegister(unsigned Reg) const {
     962      323729 :     return readsWritesVirtualRegister(Reg).first;
     963             :   }
     964             : 
     965             :   /// Return a pair of bools (reads, writes) indicating if this instruction
     966             :   /// reads or writes Reg. This also considers partial defines.
     967             :   /// If Ops is not null, all operand indices for Reg are added.
     968             :   std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
     969             :                                 SmallVectorImpl<unsigned> *Ops = nullptr) const;
     970             : 
     971             :   /// Return true if the MachineInstr kills the specified register.
     972             :   /// If TargetRegisterInfo is passed, then it also checks if there is
     973             :   /// a kill of a super-register.
     974             :   bool killsRegister(unsigned Reg,
     975             :                      const TargetRegisterInfo *TRI = nullptr) const {
     976      373489 :     return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
     977             :   }
     978             : 
     979             :   /// Return true if the MachineInstr fully defines the specified register.
     980             :   /// If TargetRegisterInfo is passed, then it also checks
     981             :   /// if there is a def of a super-register.
     982             :   /// NOTE: It's ignoring subreg indices on virtual registers.
     983             :   bool definesRegister(unsigned Reg,
     984             :                        const TargetRegisterInfo *TRI = nullptr) const {
     985      571970 :     return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
     986             :   }
     987             : 
     988             :   /// Return true if the MachineInstr modifies (fully define or partially
     989             :   /// define) the specified register.
     990             :   /// NOTE: It's ignoring subreg indices on virtual registers.
     991             :   bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
     992     4703984 :     return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
     993             :   }
     994             : 
     995             :   /// Returns true if the register is dead in this machine instruction.
     996             :   /// If TargetRegisterInfo is passed, then it also checks
     997             :   /// if there is a dead def of a super-register.
     998             :   bool registerDefIsDead(unsigned Reg,
     999             :                          const TargetRegisterInfo *TRI = nullptr) const {
    1000     1184983 :     return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
    1001             :   }
    1002             : 
    1003             :   /// Returns true if the MachineInstr has an implicit-use operand of exactly
    1004             :   /// the given register (not considering sub/super-registers).
    1005             :   bool hasRegisterImplicitUseOperand(unsigned Reg) const;
    1006             : 
    1007             :   /// Returns the operand index that is a use of the specific register or -1
    1008             :   /// if it is not found. It further tightens the search criteria to a use
    1009             :   /// that kills the register if isKill is true.
    1010             :   int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
    1011             :                                 const TargetRegisterInfo *TRI = nullptr) const;
    1012             : 
    1013             :   /// Wrapper for findRegisterUseOperandIdx, it returns
    1014             :   /// a pointer to the MachineOperand rather than an index.
    1015             :   MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
    1016             :                                       const TargetRegisterInfo *TRI = nullptr) {
    1017       27785 :     int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
    1018       27785 :     return (Idx == -1) ? nullptr : &getOperand(Idx);
    1019             :   }
    1020             : 
    1021             :   const MachineOperand *findRegisterUseOperand(
    1022             :     unsigned Reg, bool isKill = false,
    1023             :     const TargetRegisterInfo *TRI = nullptr) const {
    1024             :     return const_cast<MachineInstr *>(this)->
    1025             :       findRegisterUseOperand(Reg, isKill, TRI);
    1026             :   }
    1027             : 
    1028             :   /// Returns the operand index that is a def of the specified register or
    1029             :   /// -1 if it is not found. If isDead is true, defs that are not dead are
    1030             :   /// skipped. If Overlap is true, then it also looks for defs that merely
    1031             :   /// overlap the specified register. If TargetRegisterInfo is non-null,
    1032             :   /// then it also checks if there is a def of a super-register.
    1033             :   /// This may also return a register mask operand when Overlap is true.
    1034             :   int findRegisterDefOperandIdx(unsigned Reg,
    1035             :                                 bool isDead = false, bool Overlap = false,
    1036             :                                 const TargetRegisterInfo *TRI = nullptr) const;
    1037             : 
    1038             :   /// Wrapper for findRegisterDefOperandIdx, it returns
    1039             :   /// a pointer to the MachineOperand rather than an index.
    1040             :   MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
    1041             :                                       const TargetRegisterInfo *TRI = nullptr) {
    1042     1159354 :     int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
    1043     1159354 :     return (Idx == -1) ? nullptr : &getOperand(Idx);
    1044             :   }
    1045             : 
    1046             :   /// Find the index of the first operand in the
    1047             :   /// operand list that is used to represent the predicate. It returns -1 if
    1048             :   /// none is found.
    1049             :   int findFirstPredOperandIdx() const;
    1050             : 
    1051             :   /// Find the index of the flag word operand that
    1052             :   /// corresponds to operand OpIdx on an inline asm instruction.  Returns -1 if
    1053             :   /// getOperand(OpIdx) does not belong to an inline asm operand group.
    1054             :   ///
    1055             :   /// If GroupNo is not NULL, it will receive the number of the operand group
    1056             :   /// containing OpIdx.
    1057             :   ///
    1058             :   /// The flag operand is an immediate that can be decoded with methods like
    1059             :   /// InlineAsm::hasRegClassConstraint().
    1060             :   int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
    1061             : 
    1062             :   /// Compute the static register class constraint for operand OpIdx.
    1063             :   /// For normal instructions, this is derived from the MCInstrDesc.
    1064             :   /// For inline assembly it is derived from the flag words.
    1065             :   ///
    1066             :   /// Returns NULL if the static register class constraint cannot be
    1067             :   /// determined.
    1068             :   const TargetRegisterClass*
    1069             :   getRegClassConstraint(unsigned OpIdx,
    1070             :                         const TargetInstrInfo *TII,
    1071             :                         const TargetRegisterInfo *TRI) const;
    1072             : 
    1073             :   /// Applies the constraints (def/use) implied by this MI on \p Reg to
    1074             :   /// the given \p CurRC.
    1075             :   /// If \p ExploreBundle is set and MI is part of a bundle, all the
    1076             :   /// instructions inside the bundle will be taken into account. In other words,
    1077             :   /// this method accumulates all the constraints of the operand of this MI and
    1078             :   /// the related bundle if MI is a bundle or inside a bundle.
    1079             :   ///
    1080             :   /// Returns the register class that satisfies both \p CurRC and the
    1081             :   /// constraints set by MI. Returns NULL if such a register class does not
    1082             :   /// exist.
    1083             :   ///
    1084             :   /// \pre CurRC must not be NULL.
    1085             :   const TargetRegisterClass *getRegClassConstraintEffectForVReg(
    1086             :       unsigned Reg, const TargetRegisterClass *CurRC,
    1087             :       const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
    1088             :       bool ExploreBundle = false) const;
    1089             : 
    1090             :   /// Applies the constraints (def/use) implied by the \p OpIdx operand
    1091             :   /// to the given \p CurRC.
    1092             :   ///
    1093             :   /// Returns the register class that satisfies both \p CurRC and the
    1094             :   /// constraints set by \p OpIdx MI. Returns NULL if such a register class
    1095             :   /// does not exist.
    1096             :   ///
    1097             :   /// \pre CurRC must not be NULL.
    1098             :   /// \pre The operand at \p OpIdx must be a register.
    1099             :   const TargetRegisterClass *
    1100             :   getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
    1101             :                               const TargetInstrInfo *TII,
    1102             :                               const TargetRegisterInfo *TRI) const;
    1103             : 
    1104             :   /// Add a tie between the register operands at DefIdx and UseIdx.
    1105             :   /// The tie will cause the register allocator to ensure that the two
    1106             :   /// operands are assigned the same physical register.
    1107             :   ///
    1108             :   /// Tied operands are managed automatically for explicit operands in the
    1109             :   /// MCInstrDesc. This method is for exceptional cases like inline asm.
    1110             :   void tieOperands(unsigned DefIdx, unsigned UseIdx);
    1111             : 
    1112             :   /// Given the index of a tied register operand, find the
    1113             :   /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
    1114             :   /// index of the tied operand which must exist.
    1115             :   unsigned findTiedOperandIdx(unsigned OpIdx) const;
    1116             : 
    1117             :   /// Given the index of a register def operand,
    1118             :   /// check if the register def is tied to a source operand, due to either
    1119             :   /// two-address elimination or inline assembly constraints. Returns the
    1120             :   /// first tied use operand index by reference if UseOpIdx is not null.
    1121     2496376 :   bool isRegTiedToUseOperand(unsigned DefOpIdx,
    1122             :                              unsigned *UseOpIdx = nullptr) const {
    1123     2496376 :     const MachineOperand &MO = getOperand(DefOpIdx);
    1124     6343937 :     if (!MO.isReg() || !MO.isDef() || !MO.isTied())
    1125             :       return false;
    1126      198711 :     if (UseOpIdx)
    1127        8422 :       *UseOpIdx = findTiedOperandIdx(DefOpIdx);
    1128             :     return true;
    1129             :   }
    1130             : 
    1131             :   /// Return true if the use operand of the specified index is tied to a def
    1132             :   /// operand. It also returns the def operand index by reference if DefOpIdx
    1133             :   /// is not null.
    1134    47098481 :   bool isRegTiedToDefOperand(unsigned UseOpIdx,
    1135             :                              unsigned *DefOpIdx = nullptr) const {
    1136    47098481 :     const MachineOperand &MO = getOperand(UseOpIdx);
    1137   123133889 :     if (!MO.isReg() || !MO.isUse() || !MO.isTied())
    1138             :       return false;
    1139     1109436 :     if (DefOpIdx)
    1140     1089267 :       *DefOpIdx = findTiedOperandIdx(UseOpIdx);
    1141             :     return true;
    1142             :   }
    1143             : 
    1144             :   /// Clears kill flags on all operands.
    1145             :   void clearKillInfo();
    1146             : 
    1147             :   /// Replace all occurrences of FromReg with ToReg:SubIdx,
    1148             :   /// properly composing subreg indices where necessary.
    1149             :   void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
    1150             :                           const TargetRegisterInfo &RegInfo);
    1151             : 
    1152             :   /// We have determined MI kills a register. Look for the
    1153             :   /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
    1154             :   /// add a implicit operand if it's not found. Returns true if the operand
    1155             :   /// exists / is added.
    1156             :   bool addRegisterKilled(unsigned IncomingReg,
    1157             :                          const TargetRegisterInfo *RegInfo,
    1158             :                          bool AddIfNotFound = false);
    1159             : 
    1160             :   /// Clear all kill flags affecting Reg.  If RegInfo is provided, this includes
    1161             :   /// all aliasing registers.
    1162             :   void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
    1163             : 
    1164             :   /// We have determined MI defined a register without a use.
    1165             :   /// Look for the operand that defines it and mark it as IsDead. If
    1166             :   /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
    1167             :   /// true if the operand exists / is added.
    1168             :   bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
    1169             :                        bool AddIfNotFound = false);
    1170             : 
    1171             :   /// Clear all dead flags on operands defining register @p Reg.
    1172             :   void clearRegisterDeads(unsigned Reg);
    1173             : 
    1174             :   /// Mark all subregister defs of register @p Reg with the undef flag.
    1175             :   /// This function is used when we determined to have a subregister def in an
    1176             :   /// otherwise undefined super register.
    1177             :   void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
    1178             : 
    1179             :   /// We have determined MI defines a register. Make sure there is an operand
    1180             :   /// defining Reg.
    1181             :   void addRegisterDefined(unsigned Reg,
    1182             :                           const TargetRegisterInfo *RegInfo = nullptr);
    1183             : 
    1184             :   /// Mark every physreg used by this instruction as
    1185             :   /// dead except those in the UsedRegs list.
    1186             :   ///
    1187             :   /// On instructions with register mask operands, also add implicit-def
    1188             :   /// operands for all registers in UsedRegs.
    1189             :   void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
    1190             :                              const TargetRegisterInfo &TRI);
    1191             : 
    1192             :   /// Return true if it is safe to move this instruction. If
    1193             :   /// SawStore is set to true, it means that there is a store (or call) between
    1194             :   /// the instruction's location and its intended destination.
    1195             :   bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
    1196             : 
    1197             :   /// Returns true if this instruction's memory access aliases the memory
    1198             :   /// access of Other.
    1199             :   //
    1200             :   /// Assumes any physical registers used to compute addresses
    1201             :   /// have the same value for both instructions.  Returns false if neither
    1202             :   /// instruction writes to memory.
    1203             :   ///
    1204             :   /// @param AA Optional alias analysis, used to compare memory operands.
    1205             :   /// @param Other MachineInstr to check aliasing against.
    1206             :   /// @param UseTBAA Whether to pass TBAA information to alias analysis.
    1207             :   bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA);
    1208             : 
    1209             :   /// Return true if this instruction may have an ordered
    1210             :   /// or volatile memory reference, or if the information describing the memory
    1211             :   /// reference is not available. Return false if it is known to have no
    1212             :   /// ordered or volatile memory references.
    1213             :   bool hasOrderedMemoryRef() const;
    1214             : 
    1215             :   /// Return true if this load instruction never traps and points to a memory
    1216             :   /// location whose value doesn't change during the execution of this function.
    1217             :   ///
    1218             :   /// Examples include loading a value from the constant pool or from the
    1219             :   /// argument area of a function (if it does not change).  If the instruction
    1220             :   /// does multiple loads, this returns true only if all of the loads are
    1221             :   /// dereferenceable and invariant.
    1222             :   bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const;
    1223             : 
    1224             :   /// If the specified instruction is a PHI that always merges together the
    1225             :   /// same virtual register, return the register, otherwise return 0.
    1226             :   unsigned isConstantValuePHI() const;
    1227             : 
    1228             :   /// Return true if this instruction has side effects that are not modeled
    1229             :   /// by mayLoad / mayStore, etc.
    1230             :   /// For all instructions, the property is encoded in MCInstrDesc::Flags
    1231             :   /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
    1232             :   /// INLINEASM instruction, in which case the side effect property is encoded
    1233             :   /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
    1234             :   ///
    1235             :   bool hasUnmodeledSideEffects() const;
    1236             : 
    1237             :   /// Returns true if it is illegal to fold a load across this instruction.
    1238             :   bool isLoadFoldBarrier() const;
    1239             : 
    1240             :   /// Return true if all the defs of this instruction are dead.
    1241             :   bool allDefsAreDead() const;
    1242             : 
    1243             :   /// Copy implicit register operands from specified
    1244             :   /// instruction to this instruction.
    1245             :   void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
    1246             : 
    1247             :   /// Debugging support
    1248             :   /// @{
    1249             :   /// Determine the generic type to be printed (if needed) on uses and defs.
    1250             :   LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
    1251             :                      const MachineRegisterInfo &MRI) const;
    1252             : 
    1253             :   /// Return true when an instruction has tied register that can't be determined
    1254             :   /// by the instruction's descriptor. This is useful for MIR printing, to
    1255             :   /// determine whether we need to print the ties or not.
    1256             :   bool hasComplexRegisterTies() const;
    1257             : 
    1258             :   /// Print this MI to \p OS.
    1259             :   /// Don't print information that can be inferred from other instructions if
    1260             :   /// \p IsStandalone is false. It is usually true when only a fragment of the
    1261             :   /// function is printed.
    1262             :   /// Only print the defs and the opcode if \p SkipOpers is true.
    1263             :   /// Otherwise, also print operands if \p SkipDebugLoc is true.
    1264             :   /// Otherwise, also print the debug loc, with a terminating newline.
    1265             :   /// \p TII is used to print the opcode name.  If it's not present, but the
    1266             :   /// MI is in a function, the opcode will be printed using the function's TII.
    1267             :   void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
    1268             :              bool SkipDebugLoc = false, bool AddNewLine = true,
    1269             :              const TargetInstrInfo *TII = nullptr) const;
    1270             :   void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
    1271             :              bool SkipOpers = false, bool SkipDebugLoc = false,
    1272             :              bool AddNewLine = true,
    1273             :              const TargetInstrInfo *TII = nullptr) const;
    1274             :   void dump() const;
    1275             :   /// @}
    1276             : 
    1277             :   //===--------------------------------------------------------------------===//
    1278             :   // Accessors used to build up machine instructions.
    1279             : 
    1280             :   /// Add the specified operand to the instruction.  If it is an implicit
    1281             :   /// operand, it is added to the end of the operand list.  If it is an
    1282             :   /// explicit operand it is added at the end of the explicit operand list
    1283             :   /// (before the first implicit operand).
    1284             :   ///
    1285             :   /// MF must be the machine function that was used to allocate this
    1286             :   /// instruction.
    1287             :   ///
    1288             :   /// MachineInstrBuilder provides a more convenient interface for creating
    1289             :   /// instructions and adding operands.
    1290             :   void addOperand(MachineFunction &MF, const MachineOperand &Op);
    1291             : 
    1292             :   /// Add an operand without providing an MF reference. This only works for
    1293             :   /// instructions that are inserted in a basic block.
    1294             :   ///
    1295             :   /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
    1296             :   /// preferred.
    1297             :   void addOperand(const MachineOperand &Op);
    1298             : 
    1299             :   /// Replace the instruction descriptor (thus opcode) of
    1300             :   /// the current instruction with a new one.
    1301      872260 :   void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
    1302             : 
    1303             :   /// Replace current source information with new such.
    1304             :   /// Avoid using this, the constructor argument is preferable.
    1305             :   void setDebugLoc(DebugLoc dl) {
    1306             :     debugLoc = std::move(dl);
    1307             :     assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
    1308             :   }
    1309             : 
    1310             :   /// Erase an operand from an instruction, leaving it with one
    1311             :   /// fewer operand than it started with.
    1312             :   void RemoveOperand(unsigned i);
    1313             : 
    1314             :   /// Add a MachineMemOperand to the machine instruction.
    1315             :   /// This function should be used only occasionally. The setMemRefs function
    1316             :   /// is the primary method for setting up a MachineInstr's MemRefs list.
    1317             :   void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
    1318             : 
    1319             :   /// Assign this MachineInstr's memory reference descriptor list.
    1320             :   /// This does not transfer ownership.
    1321             :   void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
    1322     3172967 :     setMemRefs(std::make_pair(NewMemRefs, NewMemRefsEnd-NewMemRefs));
    1323             :   }
    1324             : 
    1325             :   /// Assign this MachineInstr's memory reference descriptor list.  First
    1326             :   /// element in the pair is the begin iterator/pointer to the array; the
    1327             :   /// second is the number of MemoryOperands.  This does not transfer ownership
    1328             :   /// of the underlying memory.
    1329             :   void setMemRefs(std::pair<mmo_iterator, unsigned> NewMemRefs) {
    1330     3223645 :     MemRefs = NewMemRefs.first;
    1331     3195159 :     NumMemRefs = uint8_t(NewMemRefs.second);
    1332             :     assert(NumMemRefs == NewMemRefs.second &&
    1333             :            "Too many memrefs - must drop memory operands");
    1334             :   }
    1335             : 
    1336             :   /// Return a set of memrefs (begin iterator, size) which conservatively
    1337             :   /// describe the memory behavior of both MachineInstrs.  This is appropriate
    1338             :   /// for use when merging two MachineInstrs into one. This routine does not
    1339             :   /// modify the memrefs of the this MachineInstr.
    1340             :   std::pair<mmo_iterator, unsigned> mergeMemRefsWith(const MachineInstr& Other);
    1341             : 
    1342             :   /// Return the MIFlags which represent both MachineInstrs. This
    1343             :   /// should be used when merging two MachineInstrs into one. This routine does
    1344             :   /// not modify the MIFlags of this MachineInstr.
    1345             :   uint8_t mergeFlagsWith(const MachineInstr& Other) const;
    1346             : 
    1347             :   /// Clear this MachineInstr's memory reference descriptor list.  This resets
    1348             :   /// the memrefs to their most conservative state.  This should be used only
    1349             :   /// as a last resort since it greatly pessimizes our knowledge of the memory
    1350             :   /// access performed by the instruction.
    1351             :   void dropMemRefs() {
    1352         401 :     MemRefs = nullptr;
    1353         401 :     NumMemRefs = 0;
    1354             :   }
    1355             : 
    1356             :   /// Break any tie involving OpIdx.
    1357      669527 :   void untieRegOperand(unsigned OpIdx) {
    1358      669527 :     MachineOperand &MO = getOperand(OpIdx);
    1359     1282089 :     if (MO.isReg() && MO.isTied()) {
    1360      134296 :       getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
    1361       67148 :       MO.TiedTo = 0;
    1362             :     }
    1363      669527 :   }
    1364             : 
    1365             :   /// Add all implicit def and use operands to this instruction.
    1366             :   void addImplicitDefUseOperands(MachineFunction &MF);
    1367             : 
    1368             : private:
    1369             :   /// If this instruction is embedded into a MachineFunction, return the
    1370             :   /// MachineRegisterInfo object for the current function, otherwise
    1371             :   /// return null.
    1372             :   MachineRegisterInfo *getRegInfo();
    1373             : 
    1374             :   /// Unlink all of the register operands in this instruction from their
    1375             :   /// respective use lists.  This requires that the operands already be on their
    1376             :   /// use lists.
    1377             :   void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
    1378             : 
    1379             :   /// Add all of the register operands in this instruction from their
    1380             :   /// respective use lists.  This requires that the operands not be on their
    1381             :   /// use lists yet.
    1382             :   void AddRegOperandsToUseLists(MachineRegisterInfo&);
    1383             : 
    1384             :   /// Slow path for hasProperty when we're dealing with a bundle.
    1385             :   bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
    1386             : 
    1387             :   /// Implements the logic of getRegClassConstraintEffectForVReg for the
    1388             :   /// this MI and the given operand index \p OpIdx.
    1389             :   /// If the related operand does not constrained Reg, this returns CurRC.
    1390             :   const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
    1391             :       unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
    1392             :       const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
    1393             : };
    1394             : 
    1395             : /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
    1396             : /// instruction rather than by pointer value.
    1397             : /// The hashing and equality testing functions ignore definitions so this is
    1398             : /// useful for CSE, etc.
    1399             : struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
    1400             :   static inline MachineInstr *getEmptyKey() {
    1401             :     return nullptr;
    1402             :   }
    1403             : 
    1404             :   static inline MachineInstr *getTombstoneKey() {
    1405             :     return reinterpret_cast<MachineInstr*>(-1);
    1406             :   }
    1407             : 
    1408             :   static unsigned getHashValue(const MachineInstr* const &MI);
    1409             : 
    1410    32344169 :   static bool isEqual(const MachineInstr* const &LHS,
    1411             :                       const MachineInstr* const &RHS) {
    1412    52684120 :     if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
    1413    41104005 :         LHS == getEmptyKey() || LHS == getTombstoneKey())
    1414    27964251 :       return LHS == RHS;
    1415     4379918 :     return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
    1416             :   }
    1417             : };
    1418             : 
    1419             : //===----------------------------------------------------------------------===//
    1420             : // Debugging Support
    1421             : 
    1422             : inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
    1423           1 :   MI.print(OS);
    1424             :   return OS;
    1425             : }
    1426             : 
    1427             : } // end namespace llvm
    1428             : 
    1429             : #endif // LLVM_CODEGEN_MACHINEINSTR_H

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