LCOV - code coverage report
Current view: top level - include/llvm/CodeGen - MachineOperand.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 115 118 97.5 %
Date: 2017-09-14 15:23:50 Functions: 0 0 -
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains the declaration of the MachineOperand class.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
      15             : #define LLVM_CODEGEN_MACHINEOPERAND_H
      16             : 
      17             : #include "llvm/IR/Intrinsics.h"
      18             : #include "llvm/Support/DataTypes.h"
      19             : #include <cassert>
      20             : 
      21             : namespace llvm {
      22             : 
      23             : class BlockAddress;
      24             : class ConstantFP;
      25             : class ConstantInt;
      26             : class GlobalValue;
      27             : class MachineBasicBlock;
      28             : class MachineInstr;
      29             : class MachineRegisterInfo;
      30             : class MDNode;
      31             : class ModuleSlotTracker;
      32             : class TargetMachine;
      33             : class TargetIntrinsicInfo;
      34             : class TargetRegisterInfo;
      35             : class hash_code;
      36             : class raw_ostream;
      37             : class MCSymbol;
      38             : 
      39             : /// MachineOperand class - Representation of each machine instruction operand.
      40             : ///
      41             : /// This class isn't a POD type because it has a private constructor, but its
      42             : /// destructor must be trivial. Functions like MachineInstr::addOperand(),
      43             : /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
      44             : /// not having to call the MachineOperand destructor.
      45             : ///
      46             : class MachineOperand {
      47             : public:
      48             :   enum MachineOperandType : unsigned char {
      49             :     MO_Register,          ///< Register operand.
      50             :     MO_Immediate,         ///< Immediate operand
      51             :     MO_CImmediate,        ///< Immediate >64bit operand
      52             :     MO_FPImmediate,       ///< Floating-point immediate operand
      53             :     MO_MachineBasicBlock, ///< MachineBasicBlock reference
      54             :     MO_FrameIndex,        ///< Abstract Stack Frame Index
      55             :     MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
      56             :     MO_TargetIndex,       ///< Target-dependent index+offset operand.
      57             :     MO_JumpTableIndex,    ///< Address of indexed Jump Table for switch
      58             :     MO_ExternalSymbol,    ///< Name of external global symbol
      59             :     MO_GlobalAddress,     ///< Address of a global value
      60             :     MO_BlockAddress,      ///< Address of a basic block
      61             :     MO_RegisterMask,      ///< Mask of preserved registers.
      62             :     MO_RegisterLiveOut,   ///< Mask of live-out registers.
      63             :     MO_Metadata,          ///< Metadata reference (for debug info)
      64             :     MO_MCSymbol,          ///< MCSymbol reference (for debug/eh info)
      65             :     MO_CFIIndex,          ///< MCCFIInstruction index.
      66             :     MO_IntrinsicID,       ///< Intrinsic ID for ISel
      67             :     MO_Predicate,         ///< Generic predicate for ISel
      68             :   };
      69             : 
      70             : private:
      71             :   /// OpKind - Specify what kind of operand this is.  This discriminates the
      72             :   /// union.
      73             :   MachineOperandType OpKind : 8;
      74             : 
      75             :   /// Subregister number for MO_Register.  A value of 0 indicates the
      76             :   /// MO_Register has no subReg.
      77             :   ///
      78             :   /// For all other kinds of operands, this field holds target-specific flags.
      79             :   unsigned SubReg_TargetFlags : 12;
      80             : 
      81             :   /// TiedTo - Non-zero when this register operand is tied to another register
      82             :   /// operand. The encoding of this field is described in the block comment
      83             :   /// before MachineInstr::tieOperands().
      84             :   unsigned char TiedTo : 4;
      85             : 
      86             :   /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
      87             :   /// operands.
      88             : 
      89             :   /// IsDef - True if this is a def, false if this is a use of the register.
      90             :   ///
      91             :   bool IsDef : 1;
      92             : 
      93             :   /// IsImp - True if this is an implicit def or use, false if it is explicit.
      94             :   ///
      95             :   bool IsImp : 1;
      96             : 
      97             :   /// IsKill - True if this instruction is the last use of the register on this
      98             :   /// path through the function.  This is only valid on uses of registers.
      99             :   bool IsKill : 1;
     100             : 
     101             :   /// IsDead - True if this register is never used by a subsequent instruction.
     102             :   /// This is only valid on definitions of registers.
     103             :   bool IsDead : 1;
     104             : 
     105             :   /// IsUndef - True if this register operand reads an "undef" value, i.e. the
     106             :   /// read value doesn't matter.  This flag can be set on both use and def
     107             :   /// operands.  On a sub-register def operand, it refers to the part of the
     108             :   /// register that isn't written.  On a full-register def operand, it is a
     109             :   /// noop.  See readsReg().
     110             :   ///
     111             :   /// This is only valid on registers.
     112             :   ///
     113             :   /// Note that an instruction may have multiple <undef> operands referring to
     114             :   /// the same register.  In that case, the instruction may depend on those
     115             :   /// operands reading the same dont-care value.  For example:
     116             :   ///
     117             :   ///   %vreg1<def> = XOR %vreg2<undef>, %vreg2<undef>
     118             :   ///
     119             :   /// Any register can be used for %vreg2, and its value doesn't matter, but
     120             :   /// the two operands must be the same register.
     121             :   ///
     122             :   bool IsUndef : 1;
     123             : 
     124             :   /// IsInternalRead - True if this operand reads a value that was defined
     125             :   /// inside the same instruction or bundle.  This flag can be set on both use
     126             :   /// and def operands.  On a sub-register def operand, it refers to the part
     127             :   /// of the register that isn't written.  On a full-register def operand, it
     128             :   /// is a noop.
     129             :   ///
     130             :   /// When this flag is set, the instruction bundle must contain at least one
     131             :   /// other def of the register.  If multiple instructions in the bundle define
     132             :   /// the register, the meaning is target-defined.
     133             :   bool IsInternalRead : 1;
     134             : 
     135             :   /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
     136             :   /// by the MachineInstr before all input registers are read.  This is used to
     137             :   /// model the GCC inline asm '&' constraint modifier.
     138             :   bool IsEarlyClobber : 1;
     139             : 
     140             :   /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
     141             :   /// not a real instruction.  Such uses should be ignored during codegen.
     142             :   bool IsDebug : 1;
     143             : 
     144             :   /// SmallContents - This really should be part of the Contents union, but
     145             :   /// lives out here so we can get a better packed struct.
     146             :   /// MO_Register: Register number.
     147             :   /// OffsetedInfo: Low bits of offset.
     148             :   union {
     149             :     unsigned RegNo;           // For MO_Register.
     150             :     unsigned OffsetLo;        // Matches Contents.OffsetedInfo.OffsetHi.
     151             :   } SmallContents;
     152             : 
     153             :   /// ParentMI - This is the instruction that this operand is embedded into.
     154             :   /// This is valid for all operand types, when the operand is in an instr.
     155             :   MachineInstr *ParentMI;
     156             : 
     157             :   /// Contents union - This contains the payload for the various operand types.
     158             :   union {
     159             :     MachineBasicBlock *MBB;  // For MO_MachineBasicBlock.
     160             :     const ConstantFP *CFP;   // For MO_FPImmediate.
     161             :     const ConstantInt *CI;   // For MO_CImmediate. Integers > 64bit.
     162             :     int64_t ImmVal;          // For MO_Immediate.
     163             :     const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
     164             :     const MDNode *MD;        // For MO_Metadata.
     165             :     MCSymbol *Sym;           // For MO_MCSymbol.
     166             :     unsigned CFIIndex;       // For MO_CFI.
     167             :     Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
     168             :     unsigned Pred;           // For MO_Predicate
     169             : 
     170             :     struct {                  // For MO_Register.
     171             :       // Register number is in SmallContents.RegNo.
     172             :       MachineOperand *Prev;   // Access list for register. See MRI.
     173             :       MachineOperand *Next;
     174             :     } Reg;
     175             : 
     176             :     /// OffsetedInfo - This struct contains the offset and an object identifier.
     177             :     /// this represent the object as with an optional offset from it.
     178             :     struct {
     179             :       union {
     180             :         int Index;                // For MO_*Index - The index itself.
     181             :         const char *SymbolName;   // For MO_ExternalSymbol.
     182             :         const GlobalValue *GV;    // For MO_GlobalAddress.
     183             :         const BlockAddress *BA;   // For MO_BlockAddress.
     184             :       } Val;
     185             :       // Low bits of offset are in SmallContents.OffsetLo.
     186             :       int OffsetHi;               // An offset from the object, high 32 bits.
     187             :     } OffsetedInfo;
     188             :   } Contents;
     189             : 
     190             :   explicit MachineOperand(MachineOperandType K)
     191    23501607 :     : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {}
     192             : public:
     193             :   /// getType - Returns the MachineOperandType for this operand.
     194             :   ///
     195   143838861 :   MachineOperandType getType() const { return (MachineOperandType)OpKind; }
     196             : 
     197             :   unsigned getTargetFlags() const {
     198    43577437 :     return isReg() ? 0 : SubReg_TargetFlags;
     199             :   }
     200             :   void setTargetFlags(unsigned F) {
     201             :     assert(!isReg() && "Register operands can't have target flags");
     202     1538730 :     SubReg_TargetFlags = F;
     203             :     assert(SubReg_TargetFlags == F && "Target flags out of range");
     204             :   }
     205             :   void addTargetFlag(unsigned F) {
     206             :     assert(!isReg() && "Register operands can't have target flags");
     207           0 :     SubReg_TargetFlags |= F;
     208             :     assert((SubReg_TargetFlags & F) && "Target flags out of range");
     209             :   }
     210             : 
     211             : 
     212             :   /// getParent - Return the instruction that this operand belongs to.
     213             :   ///
     214             :   MachineInstr *getParent() { return ParentMI; }
     215             :   const MachineInstr *getParent() const { return ParentMI; }
     216             : 
     217             :   /// clearParent - Reset the parent pointer.
     218             :   ///
     219             :   /// The MachineOperand copy constructor also copies ParentMI, expecting the
     220             :   /// original to be deleted. If a MachineOperand is ever stored outside a
     221             :   /// MachineInstr, the parent pointer must be cleared.
     222             :   ///
     223             :   /// Never call clearParent() on an operand in a MachineInstr.
     224             :   ///
     225       13012 :   void clearParent() { ParentMI = nullptr; }
     226             : 
     227             :   void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
     228             :              const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
     229             :   void print(raw_ostream &os, ModuleSlotTracker &MST,
     230             :              const TargetRegisterInfo *TRI = nullptr,
     231             :              const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
     232             :   void dump() const;
     233             : 
     234             :   //===--------------------------------------------------------------------===//
     235             :   // Accessors that tell you what kind of MachineOperand you're looking at.
     236             :   //===--------------------------------------------------------------------===//
     237             : 
     238             :   /// isReg - Tests if this is a MO_Register operand.
     239   858440321 :   bool isReg() const { return OpKind == MO_Register; }
     240             :   /// isImm - Tests if this is a MO_Immediate operand.
     241    15558846 :   bool isImm() const { return OpKind == MO_Immediate; }
     242             :   /// isCImm - Test if this is a MO_CImmediate operand.
     243         151 :   bool isCImm() const { return OpKind == MO_CImmediate; }
     244             :   /// isFPImm - Tests if this is a MO_FPImmediate operand.
     245    31781643 :   bool isFPImm() const { return OpKind == MO_FPImmediate; }
     246             :   /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
     247      273748 :   bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
     248             :   /// isFI - Tests if this is a MO_FrameIndex operand.
     249    56175612 :   bool isFI() const { return OpKind == MO_FrameIndex; }
     250             :   /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
     251      747093 :   bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
     252             :   /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
     253           2 :   bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
     254             :   /// isJTI - Tests if this is a MO_JumpTableIndex operand.
     255     1112559 :   bool isJTI() const { return OpKind == MO_JumpTableIndex; }
     256             :   /// isGlobal - Tests if this is a MO_GlobalAddress operand.
     257     1585461 :   bool isGlobal() const { return OpKind == MO_GlobalAddress; }
     258             :   /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
     259      160466 :   bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
     260             :   /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
     261           0 :   bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
     262             :   /// isRegMask - Tests if this is a MO_RegisterMask operand.
     263    96456453 :   bool isRegMask() const { return OpKind == MO_RegisterMask; }
     264             :   /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
     265             :   bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
     266             :   /// isMetadata - Tests if this is a MO_Metadata operand.
     267      121857 :   bool isMetadata() const { return OpKind == MO_Metadata; }
     268           0 :   bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
     269             :   bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
     270           8 :   bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
     271             :   bool isPredicate() const { return OpKind == MO_Predicate; }
     272             :   //===--------------------------------------------------------------------===//
     273             :   // Accessors for Register Operands
     274             :   //===--------------------------------------------------------------------===//
     275             : 
     276             :   /// getReg - Returns the register number.
     277             :   unsigned getReg() const {
     278             :     assert(isReg() && "This is not a register operand!");
     279             :     return SmallContents.RegNo;
     280             :   }
     281             : 
     282             :   unsigned getSubReg() const {
     283             :     assert(isReg() && "Wrong MachineOperand accessor");
     284   151070898 :     return SubReg_TargetFlags;
     285             :   }
     286             : 
     287             :   bool isUse() const {
     288             :     assert(isReg() && "Wrong MachineOperand accessor");
     289   348853151 :     return !IsDef;
     290             :   }
     291             : 
     292             :   bool isDef() const {
     293             :     assert(isReg() && "Wrong MachineOperand accessor");
     294   368818025 :     return IsDef;
     295             :   }
     296             : 
     297             :   bool isImplicit() const {
     298             :     assert(isReg() && "Wrong MachineOperand accessor");
     299   139114557 :     return IsImp;
     300             :   }
     301             : 
     302             :   bool isDead() const {
     303             :     assert(isReg() && "Wrong MachineOperand accessor");
     304    43963975 :     return IsDead;
     305             :   }
     306             : 
     307             :   bool isKill() const {
     308             :     assert(isReg() && "Wrong MachineOperand accessor");
     309    53482963 :     return IsKill;
     310             :   }
     311             : 
     312             :   bool isUndef() const {
     313             :     assert(isReg() && "Wrong MachineOperand accessor");
     314   151505074 :     return IsUndef;
     315             :   }
     316             : 
     317             :   bool isInternalRead() const {
     318             :     assert(isReg() && "Wrong MachineOperand accessor");
     319   102132518 :     return IsInternalRead;
     320             :   }
     321             : 
     322             :   bool isEarlyClobber() const {
     323             :     assert(isReg() && "Wrong MachineOperand accessor");
     324     8801785 :     return IsEarlyClobber;
     325             :   }
     326             : 
     327             :   bool isTied() const {
     328             :     assert(isReg() && "Wrong MachineOperand accessor");
     329    98928879 :     return TiedTo;
     330             :   }
     331             : 
     332             :   bool isDebug() const {
     333             :     assert(isReg() && "Wrong MachineOperand accessor");
     334    74721761 :     return IsDebug;
     335             :   }
     336             : 
     337             :   /// readsReg - Returns true if this operand reads the previous value of its
     338             :   /// register.  A use operand with the <undef> flag set doesn't read its
     339             :   /// register.  A sub-register def implicitly reads the other parts of the
     340             :   /// register being redefined unless the <undef> flag is set.
     341             :   ///
     342             :   /// This refers to reading the register value from before the current
     343             :   /// instruction or bundle. Internal bundle reads are not included.
     344             :   bool readsReg() const {
     345             :     assert(isReg() && "Wrong MachineOperand accessor");
     346   285797813 :     return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
     347             :   }
     348             : 
     349             :   //===--------------------------------------------------------------------===//
     350             :   // Mutators for Register Operands
     351             :   //===--------------------------------------------------------------------===//
     352             : 
     353             :   /// Change the register this operand corresponds to.
     354             :   ///
     355             :   void setReg(unsigned Reg);
     356             : 
     357             :   void setSubReg(unsigned subReg) {
     358             :     assert(isReg() && "Wrong MachineOperand mutator");
     359    16974921 :     SubReg_TargetFlags = subReg;
     360             :     assert(SubReg_TargetFlags == subReg && "SubReg out of range");
     361             :   }
     362             : 
     363             :   /// substVirtReg - Substitute the current register with the virtual
     364             :   /// subregister Reg:SubReg. Take any existing SubReg index into account,
     365             :   /// using TargetRegisterInfo to compose the subreg indices if necessary.
     366             :   /// Reg must be a virtual register, SubIdx can be 0.
     367             :   ///
     368             :   void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
     369             : 
     370             :   /// substPhysReg - Substitute the current register with the physical register
     371             :   /// Reg, taking any existing SubReg into account. For instance,
     372             :   /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL.
     373             :   ///
     374             :   void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
     375             : 
     376       11204 :   void setIsUse(bool Val = true) { setIsDef(!Val); }
     377             : 
     378             :   void setIsDef(bool Val = true);
     379             : 
     380             :   void setImplicit(bool Val = true) {
     381             :     assert(isReg() && "Wrong MachineOperand mutator");
     382        1311 :     IsImp = Val;
     383             :   }
     384             : 
     385             :   void setIsKill(bool Val = true) {
     386             :     assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
     387             :     assert((!Val || !isDebug()) && "Marking a debug operation as kill");
     388    22729353 :     IsKill = Val;
     389             :   }
     390             : 
     391             :   void setIsDead(bool Val = true) {
     392             :     assert(isReg() && IsDef && "Wrong MachineOperand mutator");
     393     3475163 :     IsDead = Val;
     394             :   }
     395             : 
     396             :   void setIsUndef(bool Val = true) {
     397             :     assert(isReg() && "Wrong MachineOperand mutator");
     398     1572644 :     IsUndef = Val;
     399             :   }
     400             : 
     401             :   void setIsInternalRead(bool Val = true) {
     402             :     assert(isReg() && "Wrong MachineOperand mutator");
     403      835743 :     IsInternalRead = Val;
     404             :   }
     405             : 
     406             :   void setIsEarlyClobber(bool Val = true) {
     407             :     assert(isReg() && IsDef && "Wrong MachineOperand mutator");
     408        5079 :     IsEarlyClobber = Val;
     409             :   }
     410             : 
     411             :   void setIsDebug(bool Val = true) {
     412             :     assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
     413          37 :     IsDebug = Val;
     414             :   }
     415             : 
     416             :   //===--------------------------------------------------------------------===//
     417             :   // Accessors for various operand types.
     418             :   //===--------------------------------------------------------------------===//
     419             : 
     420             :   int64_t getImm() const {
     421             :     assert(isImm() && "Wrong MachineOperand accessor");
     422             :     return Contents.ImmVal;
     423             :   }
     424             : 
     425             :   const ConstantInt *getCImm() const {
     426             :     assert(isCImm() && "Wrong MachineOperand accessor");
     427             :     return Contents.CI;
     428             :   }
     429             : 
     430             :   const ConstantFP *getFPImm() const {
     431             :     assert(isFPImm() && "Wrong MachineOperand accessor");
     432             :     return Contents.CFP;
     433             :   }
     434             : 
     435             :   MachineBasicBlock *getMBB() const {
     436             :     assert(isMBB() && "Wrong MachineOperand accessor");
     437             :     return Contents.MBB;
     438             :   }
     439             : 
     440             :   int getIndex() const {
     441             :     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
     442             :            "Wrong MachineOperand accessor");
     443             :     return Contents.OffsetedInfo.Val.Index;
     444             :   }
     445             : 
     446             :   const GlobalValue *getGlobal() const {
     447             :     assert(isGlobal() && "Wrong MachineOperand accessor");
     448             :     return Contents.OffsetedInfo.Val.GV;
     449             :   }
     450             : 
     451             :   const BlockAddress *getBlockAddress() const {
     452             :     assert(isBlockAddress() && "Wrong MachineOperand accessor");
     453             :     return Contents.OffsetedInfo.Val.BA;
     454             :   }
     455             : 
     456             :   MCSymbol *getMCSymbol() const {
     457             :     assert(isMCSymbol() && "Wrong MachineOperand accessor");
     458             :     return Contents.Sym;
     459             :   }
     460             : 
     461             :   unsigned getCFIIndex() const {
     462             :     assert(isCFIIndex() && "Wrong MachineOperand accessor");
     463             :     return Contents.CFIIndex;
     464             :   }
     465             : 
     466             :   Intrinsic::ID getIntrinsicID() const {
     467             :     assert(isIntrinsicID() && "Wrong MachineOperand accessor");
     468             :     return Contents.IntrinsicID;
     469             :   }
     470             : 
     471             :   unsigned getPredicate() const {
     472             :     assert(isPredicate() && "Wrong MachineOperand accessor");
     473             :     return Contents.Pred;
     474             :   }
     475             : 
     476             :   /// Return the offset from the symbol in this operand. This always returns 0
     477             :   /// for ExternalSymbol operands.
     478             :   int64_t getOffset() const {
     479             :     assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
     480             :             isTargetIndex() || isBlockAddress()) &&
     481             :            "Wrong MachineOperand accessor");
     482     3048234 :     return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
     483     3048234 :            SmallContents.OffsetLo;
     484             :   }
     485             : 
     486             :   const char *getSymbolName() const {
     487             :     assert(isSymbol() && "Wrong MachineOperand accessor");
     488             :     return Contents.OffsetedInfo.Val.SymbolName;
     489             :   }
     490             : 
     491             :   /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
     492             :   /// It is sometimes necessary to detach the register mask pointer from its
     493             :   /// machine operand. This static method can be used for such detached bit
     494             :   /// mask pointers.
     495             :   static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
     496             :     // See TargetRegisterInfo.h.
     497             :     assert(PhysReg < (1u << 30) && "Not a physical register");
     498    59180994 :     return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
     499             :   }
     500             : 
     501             :   /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
     502             :   bool clobbersPhysReg(unsigned PhysReg) const {
     503   108314592 :      return clobbersPhysReg(getRegMask(), PhysReg);
     504             :   }
     505             : 
     506             :   /// getRegMask - Returns a bit mask of registers preserved by this RegMask
     507             :   /// operand.
     508             :   const uint32_t *getRegMask() const {
     509             :     assert(isRegMask() && "Wrong MachineOperand accessor");
     510             :     return Contents.RegMask;
     511             :   }
     512             : 
     513             :   /// getRegLiveOut - Returns a bit mask of live-out registers.
     514             :   const uint32_t *getRegLiveOut() const {
     515             :     assert(isRegLiveOut() && "Wrong MachineOperand accessor");
     516             :     return Contents.RegMask;
     517             :   }
     518             : 
     519             :   const MDNode *getMetadata() const {
     520             :     assert(isMetadata() && "Wrong MachineOperand accessor");
     521             :     return Contents.MD;
     522             :   }
     523             : 
     524             :   //===--------------------------------------------------------------------===//
     525             :   // Mutators for various operand types.
     526             :   //===--------------------------------------------------------------------===//
     527             : 
     528             :   void setImm(int64_t immVal) {
     529             :     assert(isImm() && "Wrong MachineOperand mutator");
     530     6609507 :     Contents.ImmVal = immVal;
     531             :   }
     532             : 
     533             :   void setFPImm(const ConstantFP *CFP) {
     534             :     assert(isFPImm() && "Wrong MachineOperand mutator");
     535             :     Contents.CFP = CFP;
     536             :   }
     537             : 
     538             :   void setOffset(int64_t Offset) {
     539             :     assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
     540             :             isTargetIndex() || isBlockAddress()) &&
     541             :            "Wrong MachineOperand mutator");
     542      905854 :     SmallContents.OffsetLo = unsigned(Offset);
     543      905854 :     Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
     544             :   }
     545             : 
     546             :   void setIndex(int Idx) {
     547             :     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
     548             :            "Wrong MachineOperand mutator");
     549      403780 :     Contents.OffsetedInfo.Val.Index = Idx;
     550             :   }
     551             : 
     552             :   void setMetadata(const MDNode *MD) {
     553             :     assert(isMetadata() && "Wrong MachineOperand mutator");
     554         833 :     Contents.MD = MD;
     555             :   }
     556             : 
     557             :   void setMBB(MachineBasicBlock *MBB) {
     558             :     assert(isMBB() && "Wrong MachineOperand mutator");
     559      652442 :     Contents.MBB = MBB;
     560             :   }
     561             : 
     562             :   /// Sets value of register mask operand referencing Mask.  The
     563             :   /// operand does not take ownership of the memory referenced by Mask, it must
     564             :   /// remain valid for the lifetime of the operand. See CreateRegMask().
     565             :   /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
     566             :   void setRegMask(const uint32_t *RegMaskPtr) {
     567             :     assert(isRegMask() && "Wrong MachineOperand mutator");
     568           8 :     Contents.RegMask = RegMaskPtr;
     569             :   }
     570             : 
     571             :   //===--------------------------------------------------------------------===//
     572             :   // Other methods.
     573             :   //===--------------------------------------------------------------------===//
     574             : 
     575             :   /// Returns true if this operand is identical to the specified operand except
     576             :   /// for liveness related flags (isKill, isUndef and isDead).
     577             :   bool isIdenticalTo(const MachineOperand &Other) const;
     578             : 
     579             :   /// \brief MachineOperand hash_value overload.
     580             :   ///
     581             :   /// Note that this includes the same information in the hash that
     582             :   /// isIdenticalTo uses for comparison. It is thus suited for use in hash
     583             :   /// tables which use that function for equality comparisons only.
     584             :   friend hash_code hash_value(const MachineOperand &MO);
     585             : 
     586             :   /// ChangeToImmediate - Replace this operand with a new immediate operand of
     587             :   /// the specified value.  If an operand is known to be an immediate already,
     588             :   /// the setImm method should be used.
     589             :   void ChangeToImmediate(int64_t ImmVal);
     590             : 
     591             :   /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
     592             :   /// of the specified value.  If an operand is known to be an FP immediate
     593             :   /// already, the setFPImm method should be used.
     594             :   void ChangeToFPImmediate(const ConstantFP *FPImm);
     595             : 
     596             :   /// ChangeToES - Replace this operand with a new external symbol operand.
     597             :   void ChangeToES(const char *SymName, unsigned char TargetFlags = 0);
     598             : 
     599             :   /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
     600             :   void ChangeToMCSymbol(MCSymbol *Sym);
     601             : 
     602             :   /// Replace this operand with a frame index.
     603             :   void ChangeToFrameIndex(int Idx);
     604             : 
     605             :   /// Replace this operand with a target index.
     606             :   void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
     607             :                            unsigned char TargetFlags = 0);
     608             : 
     609             :   /// ChangeToRegister - Replace this operand with a new register operand of
     610             :   /// the specified value.  If an operand is known to be an register already,
     611             :   /// the setReg method should be used.
     612             :   void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
     613             :                         bool isKill = false, bool isDead = false,
     614             :                         bool isUndef = false, bool isDebug = false);
     615             : 
     616             :   //===--------------------------------------------------------------------===//
     617             :   // Construction methods.
     618             :   //===--------------------------------------------------------------------===//
     619             : 
     620             :   static MachineOperand CreateImm(int64_t Val) {
     621     6161577 :     MachineOperand Op(MachineOperand::MO_Immediate);
     622    12314112 :     Op.setImm(Val);
     623             :     return Op;
     624             :   }
     625             : 
     626             :   static MachineOperand CreateCImm(const ConstantInt *CI) {
     627         759 :     MachineOperand Op(MachineOperand::MO_CImmediate);
     628         577 :     Op.Contents.CI = CI;
     629             :     return Op;
     630             :   }
     631             : 
     632             :   static MachineOperand CreateFPImm(const ConstantFP *CFP) {
     633         171 :     MachineOperand Op(MachineOperand::MO_FPImmediate);
     634         152 :     Op.Contents.CFP = CFP;
     635             :     return Op;
     636             :   }
     637             : 
     638             :   static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
     639             :                                   bool isKill = false, bool isDead = false,
     640             :                                   bool isUndef = false,
     641             :                                   bool isEarlyClobber = false,
     642             :                                   unsigned SubReg = 0,
     643             :                                   bool isDebug = false,
     644             :                                   bool isInternalRead = false) {
     645             :     assert(!(isDead && !isDef) && "Dead flag on non-def");
     646             :     assert(!(isKill && isDef) && "Kill flag on def");
     647    15006892 :     MachineOperand Op(MachineOperand::MO_Register);
     648    14966305 :     Op.IsDef = isDef;
     649    14966305 :     Op.IsImp = isImp;
     650    14966305 :     Op.IsKill = isKill;
     651    14966305 :     Op.IsDead = isDead;
     652    14966305 :     Op.IsUndef = isUndef;
     653    14966305 :     Op.IsInternalRead = isInternalRead;
     654    14966305 :     Op.IsEarlyClobber = isEarlyClobber;
     655    14966305 :     Op.TiedTo = 0;
     656    14966305 :     Op.IsDebug = isDebug;
     657    14966305 :     Op.SmallContents.RegNo = Reg;
     658    14966305 :     Op.Contents.Reg.Prev = nullptr;
     659    15006892 :     Op.Contents.Reg.Next = nullptr;
     660    15006892 :     Op.setSubReg(SubReg);
     661             :     return Op;
     662             :   }
     663             :   static MachineOperand CreateMBB(MachineBasicBlock *MBB,
     664             :                                   unsigned char TargetFlags = 0) {
     665      633472 :     MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
     666     1266142 :     Op.setMBB(MBB);
     667     1266142 :     Op.setTargetFlags(TargetFlags);
     668             :     return Op;
     669             :   }
     670             :   static MachineOperand CreateFI(int Idx) {
     671      310437 :     MachineOperand Op(MachineOperand::MO_FrameIndex);
     672      620613 :     Op.setIndex(Idx);
     673             :     return Op;
     674             :   }
     675             :   static MachineOperand CreateCPI(unsigned Idx, int Offset,
     676             :                                   unsigned char TargetFlags = 0) {
     677       24953 :     MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
     678       49891 :     Op.setIndex(Idx);
     679       49891 :     Op.setOffset(Offset);
     680       49891 :     Op.setTargetFlags(TargetFlags);
     681             :     return Op;
     682             :   }
     683             :   static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
     684             :                                           unsigned char TargetFlags = 0) {
     685           2 :     MachineOperand Op(MachineOperand::MO_TargetIndex);
     686           2 :     Op.setIndex(Idx);
     687           2 :     Op.setOffset(Offset);
     688           2 :     Op.setTargetFlags(TargetFlags);
     689             :     return Op;
     690             :   }
     691             :   static MachineOperand CreateJTI(unsigned Idx,
     692             :                                   unsigned char TargetFlags = 0) {
     693         454 :     MachineOperand Op(MachineOperand::MO_JumpTableIndex);
     694         897 :     Op.setIndex(Idx);
     695         897 :     Op.setTargetFlags(TargetFlags);
     696             :     return Op;
     697             :   }
     698             :   static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
     699             :                                  unsigned char TargetFlags = 0) {
     700      779084 :     MachineOperand Op(MachineOperand::MO_GlobalAddress);
     701      778697 :     Op.Contents.OffsetedInfo.Val.GV = GV;
     702     1557781 :     Op.setOffset(Offset);
     703     1557781 :     Op.setTargetFlags(TargetFlags);
     704             :     return Op;
     705             :   }
     706             :   static MachineOperand CreateES(const char *SymName,
     707             :                                  unsigned char TargetFlags = 0) {
     708       26763 :     MachineOperand Op(MachineOperand::MO_ExternalSymbol);
     709       26713 :     Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
     710       53476 :     Op.setOffset(0); // Offset is always 0.
     711       53476 :     Op.setTargetFlags(TargetFlags);
     712             :     return Op;
     713             :   }
     714             :   static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
     715             :                                  unsigned char TargetFlags = 0) {
     716         133 :     MachineOperand Op(MachineOperand::MO_BlockAddress);
     717         128 :     Op.Contents.OffsetedInfo.Val.BA = BA;
     718         261 :     Op.setOffset(Offset);
     719         261 :     Op.setTargetFlags(TargetFlags);
     720             :     return Op;
     721             :   }
     722             :   /// CreateRegMask - Creates a register mask operand referencing Mask.  The
     723             :   /// operand does not take ownership of the memory referenced by Mask, it must
     724             :   /// remain valid for the lifetime of the operand.
     725             :   ///
     726             :   /// A RegMask operand represents a set of non-clobbered physical registers on
     727             :   /// an instruction that clobbers many registers, typically a call.  The bit
     728             :   /// mask has a bit set for each physreg that is preserved by this
     729             :   /// instruction, as described in the documentation for
     730             :   /// TargetRegisterInfo::getCallPreservedMask().
     731             :   ///
     732             :   /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
     733             :   ///
     734             :   static MachineOperand CreateRegMask(const uint32_t *Mask) {
     735             :     assert(Mask && "Missing register mask");
     736      189966 :     MachineOperand Op(MachineOperand::MO_RegisterMask);
     737      189858 :     Op.Contents.RegMask = Mask;
     738             :     return Op;
     739             :   }
     740             :   static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
     741             :     assert(Mask && "Missing live-out register mask");
     742         149 :     MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
     743         148 :     Op.Contents.RegMask = Mask;
     744             :     return Op;
     745             :   }
     746             :   static MachineOperand CreateMetadata(const MDNode *Meta) {
     747      113039 :     MachineOperand Op(MachineOperand::MO_Metadata);
     748      112666 :     Op.Contents.MD = Meta;
     749             :     return Op;
     750             :   }
     751             : 
     752             :   static MachineOperand CreateMCSymbol(MCSymbol *Sym,
     753             :                                        unsigned char TargetFlags = 0) {
     754       75026 :     MachineOperand Op(MachineOperand::MO_MCSymbol);
     755       75026 :     Op.Contents.Sym = Sym;
     756      150052 :     Op.setOffset(0);
     757      150052 :     Op.setTargetFlags(TargetFlags);
     758             :     return Op;
     759             :   }
     760             : 
     761             :   static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
     762      230572 :     MachineOperand Op(MachineOperand::MO_CFIIndex);
     763      230461 :     Op.Contents.CFIIndex = CFIIndex;
     764             :     return Op;
     765             :   }
     766             : 
     767             :   static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
     768          14 :     MachineOperand Op(MachineOperand::MO_IntrinsicID);
     769           9 :     Op.Contents.IntrinsicID = ID;
     770             :     return Op;
     771             :   }
     772             : 
     773             :   static MachineOperand CreatePredicate(unsigned Pred) {
     774         331 :     MachineOperand Op(MachineOperand::MO_Predicate);
     775         105 :     Op.Contents.Pred = Pred;
     776             :     return Op;
     777             :   }
     778             : 
     779             :   friend class MachineInstr;
     780             :   friend class MachineRegisterInfo;
     781             : private:
     782             :   void removeRegFromUses();
     783             : 
     784             :   //===--------------------------------------------------------------------===//
     785             :   // Methods for handling register use/def lists.
     786             :   //===--------------------------------------------------------------------===//
     787             : 
     788             :   /// isOnRegUseList - Return true if this operand is on a register use/def list
     789             :   /// or false if not.  This can only be called for register operands that are
     790             :   /// part of a machine instruction.
     791             :   bool isOnRegUseList() const {
     792             :     assert(isReg() && "Can only add reg operand to use lists");
     793             :     return Contents.Reg.Prev != nullptr;
     794             :   }
     795             : };
     796             : 
     797             : inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) {
     798             :   MO.print(OS, nullptr);
     799             :   return OS;
     800             : }
     801             : 
     802             :   // See friend declaration above. This additional declaration is required in
     803             :   // order to compile LLVM with IBM xlC compiler.
     804             :   hash_code hash_value(const MachineOperand &MO);
     805             : } // End llvm namespace
     806             : 
     807             : #endif

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