LCOV - code coverage report
Current view: top level - include/llvm/CodeGen - MachineOperand.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 82 86 95.3 %
Date: 2018-02-23 15:42:53 Functions: 0 0 -
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains the declaration of the MachineOperand class.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
      15             : #define LLVM_CODEGEN_MACHINEOPERAND_H
      16             : 
      17             : #include "llvm/ADT/DenseMap.h"
      18             : #include "llvm/IR/Intrinsics.h"
      19             : #include "llvm/Support/DataTypes.h"
      20             : #include "llvm/Support/LowLevelTypeImpl.h"
      21             : #include <cassert>
      22             : 
      23             : namespace llvm {
      24             : 
      25             : class BlockAddress;
      26             : class ConstantFP;
      27             : class ConstantInt;
      28             : class GlobalValue;
      29             : class MachineBasicBlock;
      30             : class MachineInstr;
      31             : class MachineRegisterInfo;
      32             : class MCCFIInstruction;
      33             : class MDNode;
      34             : class ModuleSlotTracker;
      35             : class TargetMachine;
      36             : class TargetIntrinsicInfo;
      37             : class TargetRegisterInfo;
      38             : class hash_code;
      39             : class raw_ostream;
      40             : class MCSymbol;
      41             : 
      42             : /// MachineOperand class - Representation of each machine instruction operand.
      43             : ///
      44             : /// This class isn't a POD type because it has a private constructor, but its
      45             : /// destructor must be trivial. Functions like MachineInstr::addOperand(),
      46             : /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
      47             : /// not having to call the MachineOperand destructor.
      48             : ///
      49             : class MachineOperand {
      50             : public:
      51             :   enum MachineOperandType : unsigned char {
      52             :     MO_Register,          ///< Register operand.
      53             :     MO_Immediate,         ///< Immediate operand
      54             :     MO_CImmediate,        ///< Immediate >64bit operand
      55             :     MO_FPImmediate,       ///< Floating-point immediate operand
      56             :     MO_MachineBasicBlock, ///< MachineBasicBlock reference
      57             :     MO_FrameIndex,        ///< Abstract Stack Frame Index
      58             :     MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
      59             :     MO_TargetIndex,       ///< Target-dependent index+offset operand.
      60             :     MO_JumpTableIndex,    ///< Address of indexed Jump Table for switch
      61             :     MO_ExternalSymbol,    ///< Name of external global symbol
      62             :     MO_GlobalAddress,     ///< Address of a global value
      63             :     MO_BlockAddress,      ///< Address of a basic block
      64             :     MO_RegisterMask,      ///< Mask of preserved registers.
      65             :     MO_RegisterLiveOut,   ///< Mask of live-out registers.
      66             :     MO_Metadata,          ///< Metadata reference (for debug info)
      67             :     MO_MCSymbol,          ///< MCSymbol reference (for debug/eh info)
      68             :     MO_CFIIndex,          ///< MCCFIInstruction index.
      69             :     MO_IntrinsicID,       ///< Intrinsic ID for ISel
      70             :     MO_Predicate,         ///< Generic predicate for ISel
      71             :     MO_Last = MO_Predicate,
      72             :   };
      73             : 
      74             : private:
      75             :   /// OpKind - Specify what kind of operand this is.  This discriminates the
      76             :   /// union.
      77             :   unsigned OpKind : 8;
      78             : 
      79             :   /// Subregister number for MO_Register.  A value of 0 indicates the
      80             :   /// MO_Register has no subReg.
      81             :   ///
      82             :   /// For all other kinds of operands, this field holds target-specific flags.
      83             :   unsigned SubReg_TargetFlags : 12;
      84             : 
      85             :   /// TiedTo - Non-zero when this register operand is tied to another register
      86             :   /// operand. The encoding of this field is described in the block comment
      87             :   /// before MachineInstr::tieOperands().
      88             :   unsigned TiedTo : 4;
      89             : 
      90             :   /// IsDef - True if this is a def, false if this is a use of the register.
      91             :   /// This is only valid on register operands.
      92             :   ///
      93             :   unsigned IsDef : 1;
      94             : 
      95             :   /// IsImp - True if this is an implicit def or use, false if it is explicit.
      96             :   /// This is only valid on register opderands.
      97             :   ///
      98             :   unsigned IsImp : 1;
      99             : 
     100             :   /// IsDeadOrKill
     101             :   /// For uses: IsKill - True if this instruction is the last use of the
     102             :   /// register on this path through the function.
     103             :   /// For defs: IsDead - True if this register is never used by a subsequent
     104             :   /// instruction.
     105             :   /// This is only valid on register operands.
     106             :   unsigned IsDeadOrKill : 1;
     107             : 
     108             :   /// IsRenamable - True if this register may be renamed, i.e. it does not
     109             :   /// generate a value that is somehow read in a way that is not represented by
     110             :   /// the Machine IR (e.g. to meet an ABI or ISA requirement).  This is only
     111             :   /// valid on physical register operands.  Virtual registers are assumed to
     112             :   /// always be renamable regardless of the value of this field.
     113             :   unsigned IsRenamable : 1;
     114             : 
     115             :   /// IsUndef - True if this register operand reads an "undef" value, i.e. the
     116             :   /// read value doesn't matter.  This flag can be set on both use and def
     117             :   /// operands.  On a sub-register def operand, it refers to the part of the
     118             :   /// register that isn't written.  On a full-register def operand, it is a
     119             :   /// noop.  See readsReg().
     120             :   ///
     121             :   /// This is only valid on registers.
     122             :   ///
     123             :   /// Note that an instruction may have multiple <undef> operands referring to
     124             :   /// the same register.  In that case, the instruction may depend on those
     125             :   /// operands reading the same dont-care value.  For example:
     126             :   ///
     127             :   ///   %1 = XOR undef %2, undef %2
     128             :   ///
     129             :   /// Any register can be used for %2, and its value doesn't matter, but
     130             :   /// the two operands must be the same register.
     131             :   ///
     132             :   unsigned IsUndef : 1;
     133             : 
     134             :   /// IsInternalRead - True if this operand reads a value that was defined
     135             :   /// inside the same instruction or bundle.  This flag can be set on both use
     136             :   /// and def operands.  On a sub-register def operand, it refers to the part
     137             :   /// of the register that isn't written.  On a full-register def operand, it
     138             :   /// is a noop.
     139             :   ///
     140             :   /// When this flag is set, the instruction bundle must contain at least one
     141             :   /// other def of the register.  If multiple instructions in the bundle define
     142             :   /// the register, the meaning is target-defined.
     143             :   unsigned IsInternalRead : 1;
     144             : 
     145             :   /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
     146             :   /// by the MachineInstr before all input registers are read.  This is used to
     147             :   /// model the GCC inline asm '&' constraint modifier.
     148             :   unsigned IsEarlyClobber : 1;
     149             : 
     150             :   /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
     151             :   /// not a real instruction.  Such uses should be ignored during codegen.
     152             :   unsigned IsDebug : 1;
     153             : 
     154             :   /// SmallContents - This really should be part of the Contents union, but
     155             :   /// lives out here so we can get a better packed struct.
     156             :   /// MO_Register: Register number.
     157             :   /// OffsetedInfo: Low bits of offset.
     158             :   union {
     159             :     unsigned RegNo;           // For MO_Register.
     160             :     unsigned OffsetLo;        // Matches Contents.OffsetedInfo.OffsetHi.
     161             :   } SmallContents;
     162             : 
     163             :   /// ParentMI - This is the instruction that this operand is embedded into.
     164             :   /// This is valid for all operand types, when the operand is in an instr.
     165             :   MachineInstr *ParentMI;
     166             : 
     167             :   /// Contents union - This contains the payload for the various operand types.
     168             :   union {
     169             :     MachineBasicBlock *MBB;  // For MO_MachineBasicBlock.
     170             :     const ConstantFP *CFP;   // For MO_FPImmediate.
     171             :     const ConstantInt *CI;   // For MO_CImmediate. Integers > 64bit.
     172             :     int64_t ImmVal;          // For MO_Immediate.
     173             :     const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
     174             :     const MDNode *MD;        // For MO_Metadata.
     175             :     MCSymbol *Sym;           // For MO_MCSymbol.
     176             :     unsigned CFIIndex;       // For MO_CFI.
     177             :     Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
     178             :     unsigned Pred;           // For MO_Predicate
     179             : 
     180             :     struct {                  // For MO_Register.
     181             :       // Register number is in SmallContents.RegNo.
     182             :       MachineOperand *Prev;   // Access list for register. See MRI.
     183             :       MachineOperand *Next;
     184             :     } Reg;
     185             : 
     186             :     /// OffsetedInfo - This struct contains the offset and an object identifier.
     187             :     /// this represent the object as with an optional offset from it.
     188             :     struct {
     189             :       union {
     190             :         int Index;                // For MO_*Index - The index itself.
     191             :         const char *SymbolName;   // For MO_ExternalSymbol.
     192             :         const GlobalValue *GV;    // For MO_GlobalAddress.
     193             :         const BlockAddress *BA;   // For MO_BlockAddress.
     194             :       } Val;
     195             :       // Low bits of offset are in SmallContents.OffsetLo.
     196             :       int OffsetHi;               // An offset from the object, high 32 bits.
     197             :     } OffsetedInfo;
     198             :   } Contents;
     199             : 
     200             :   explicit MachineOperand(MachineOperandType K)
     201    26055452 :     : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
     202             :     // Assert that the layout is what we expect. It's easy to grow this object.
     203             :     static_assert(alignof(MachineOperand) <= alignof(int64_t),
     204             :                   "MachineOperand shouldn't be more than 8 byte aligned");
     205             :     static_assert(sizeof(Contents) <= 2 * sizeof(void *),
     206             :                   "Contents should be at most two pointers");
     207             :     static_assert(sizeof(MachineOperand) <=
     208             :                       alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
     209             :                                                 3 * sizeof(void *)),
     210             :                   "MachineOperand too big. Should be Kind, SmallContents, "
     211             :                   "ParentMI, and Contents");
     212             :   }
     213             : 
     214             : public:
     215             :   /// getType - Returns the MachineOperandType for this operand.
     216             :   ///
     217   148020057 :   MachineOperandType getType() const { return (MachineOperandType)OpKind; }
     218             : 
     219             :   unsigned getTargetFlags() const {
     220    34377990 :     return isReg() ? 0 : SubReg_TargetFlags;
     221             :   }
     222             :   void setTargetFlags(unsigned F) {
     223             :     assert(!isReg() && "Register operands can't have target flags");
     224     1604962 :     SubReg_TargetFlags = F;
     225             :     assert(SubReg_TargetFlags == F && "Target flags out of range");
     226             :   }
     227             :   void addTargetFlag(unsigned F) {
     228             :     assert(!isReg() && "Register operands can't have target flags");
     229           0 :     SubReg_TargetFlags |= F;
     230             :     assert((SubReg_TargetFlags & F) && "Target flags out of range");
     231             :   }
     232             : 
     233             : 
     234             :   /// getParent - Return the instruction that this operand belongs to.
     235             :   ///
     236             :   MachineInstr *getParent() { return ParentMI; }
     237             :   const MachineInstr *getParent() const { return ParentMI; }
     238             : 
     239             :   /// clearParent - Reset the parent pointer.
     240             :   ///
     241             :   /// The MachineOperand copy constructor also copies ParentMI, expecting the
     242             :   /// original to be deleted. If a MachineOperand is ever stored outside a
     243             :   /// MachineInstr, the parent pointer must be cleared.
     244             :   ///
     245             :   /// Never call clearParent() on an operand in a MachineInstr.
     246             :   ///
     247       18815 :   void clearParent() { ParentMI = nullptr; }
     248             : 
     249             :   /// Print a subreg index operand.
     250             :   /// MO_Immediate operands can also be subreg idices. If it's the case, the
     251             :   /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
     252             :   /// called to check this.
     253             :   static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
     254             :                              const TargetRegisterInfo *TRI);
     255             : 
     256             :   /// Print operand target flags.
     257             :   static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
     258             : 
     259             :   /// Print a MCSymbol as an operand.
     260             :   static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
     261             : 
     262             :   /// Print a stack object reference.
     263             :   static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
     264             :                                         bool IsFixed, StringRef Name);
     265             : 
     266             :   /// Print the offset with explicit +/- signs.
     267             :   static void printOperandOffset(raw_ostream &OS, int64_t Offset);
     268             : 
     269             :   /// Print an IRSlotNumber.
     270             :   static void printIRSlotNumber(raw_ostream &OS, int Slot);
     271             : 
     272             :   /// Print the MachineOperand to \p os.
     273             :   /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
     274             :   /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
     275             :   /// function will try to pick it up from the parent.
     276             :   void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
     277             :              const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
     278             : 
     279             :   /// More complex way of printing a MachineOperand.
     280             :   /// \param TypeToPrint specifies the generic type to be printed on uses and
     281             :   /// defs. It can be determined using MachineInstr::getTypeToPrint.
     282             :   /// \param PrintDef - whether we want to print `def` on an operand which
     283             :   /// isDef. Sometimes, if the operand is printed before '=', we don't print
     284             :   /// `def`.
     285             :   /// \param IsStandalone - whether we want a verbose output of the MO. This
     286             :   /// prints extra information that can be easily inferred when printing the
     287             :   /// whole function, but not when printing only a fragment of it.
     288             :   /// \param ShouldPrintRegisterTies - whether we want to print register ties.
     289             :   /// Sometimes they are easily determined by the instruction's descriptor
     290             :   /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
     291             :   /// \param TiedOperandIdx - if we need to print register ties this needs to
     292             :   /// provide the index of the tied register. If not, it will be ignored.
     293             :   /// \param TRI - provide more target-specific information to the printer.
     294             :   /// Unlike the previous function, this one will not try and get the
     295             :   /// information from it's parent.
     296             :   /// \param IntrinsicInfo - same as \p TRI.
     297             :   void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
     298             :              bool PrintDef, bool IsStandalone, bool ShouldPrintRegisterTies,
     299             :              unsigned TiedOperandIdx, const TargetRegisterInfo *TRI,
     300             :              const TargetIntrinsicInfo *IntrinsicInfo) const;
     301             : 
     302             :   void dump() const;
     303             : 
     304             :   //===--------------------------------------------------------------------===//
     305             :   // Accessors that tell you what kind of MachineOperand you're looking at.
     306             :   //===--------------------------------------------------------------------===//
     307             : 
     308             :   /// isReg - Tests if this is a MO_Register operand.
     309   946338407 :   bool isReg() const { return OpKind == MO_Register; }
     310             :   /// isImm - Tests if this is a MO_Immediate operand.
     311    15321079 :   bool isImm() const { return OpKind == MO_Immediate; }
     312             :   /// isCImm - Test if this is a MO_CImmediate operand.
     313         371 :   bool isCImm() const { return OpKind == MO_CImmediate; }
     314             :   /// isFPImm - Tests if this is a MO_FPImmediate operand.
     315    35614653 :   bool isFPImm() const { return OpKind == MO_FPImmediate; }
     316             :   /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
     317      535151 :   bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
     318             :   /// isFI - Tests if this is a MO_FrameIndex operand.
     319    61708861 :   bool isFI() const { return OpKind == MO_FrameIndex; }
     320             :   /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
     321      798668 :   bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
     322             :   /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
     323           2 :   bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
     324             :   /// isJTI - Tests if this is a MO_JumpTableIndex operand.
     325     1349751 :   bool isJTI() const { return OpKind == MO_JumpTableIndex; }
     326             :   /// isGlobal - Tests if this is a MO_GlobalAddress operand.
     327     2042718 :   bool isGlobal() const { return OpKind == MO_GlobalAddress; }
     328             :   /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
     329      168260 :   bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
     330             :   /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
     331           0 :   bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
     332             :   /// isRegMask - Tests if this is a MO_RegisterMask operand.
     333   107420966 :   bool isRegMask() const { return OpKind == MO_RegisterMask; }
     334             :   /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
     335             :   bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
     336             :   /// isMetadata - Tests if this is a MO_Metadata operand.
     337      193205 :   bool isMetadata() const { return OpKind == MO_Metadata; }
     338           0 :   bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
     339             :   bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
     340          17 :   bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
     341             :   bool isPredicate() const { return OpKind == MO_Predicate; }
     342             :   //===--------------------------------------------------------------------===//
     343             :   // Accessors for Register Operands
     344             :   //===--------------------------------------------------------------------===//
     345             : 
     346             :   /// getReg - Returns the register number.
     347             :   unsigned getReg() const {
     348             :     assert(isReg() && "This is not a register operand!");
     349             :     return SmallContents.RegNo;
     350             :   }
     351             : 
     352             :   unsigned getSubReg() const {
     353             :     assert(isReg() && "Wrong MachineOperand accessor");
     354   172078681 :     return SubReg_TargetFlags;
     355             :   }
     356             : 
     357             :   bool isUse() const {
     358             :     assert(isReg() && "Wrong MachineOperand accessor");
     359   418837739 :     return !IsDef;
     360             :   }
     361             : 
     362             :   bool isDef() const {
     363             :     assert(isReg() && "Wrong MachineOperand accessor");
     364   426819741 :     return IsDef;
     365             :   }
     366             : 
     367             :   bool isImplicit() const {
     368             :     assert(isReg() && "Wrong MachineOperand accessor");
     369   118692404 :     return IsImp;
     370             :   }
     371             : 
     372             :   bool isDead() const {
     373             :     assert(isReg() && "Wrong MachineOperand accessor");
     374    48996585 :     return IsDeadOrKill & IsDef;
     375             :   }
     376             : 
     377             :   bool isKill() const {
     378             :     assert(isReg() && "Wrong MachineOperand accessor");
     379    61611615 :     return IsDeadOrKill & !IsDef;
     380             :   }
     381             : 
     382             :   bool isUndef() const {
     383             :     assert(isReg() && "Wrong MachineOperand accessor");
     384   171599653 :     return IsUndef;
     385             :   }
     386             : 
     387             :   bool isRenamable() const;
     388             : 
     389             :   bool isInternalRead() const {
     390             :     assert(isReg() && "Wrong MachineOperand accessor");
     391   112430207 :     return IsInternalRead;
     392             :   }
     393             : 
     394             :   bool isEarlyClobber() const {
     395             :     assert(isReg() && "Wrong MachineOperand accessor");
     396     9727982 :     return IsEarlyClobber;
     397             :   }
     398             : 
     399             :   bool isTied() const {
     400             :     assert(isReg() && "Wrong MachineOperand accessor");
     401   110296701 :     return TiedTo;
     402             :   }
     403             : 
     404             :   bool isDebug() const {
     405             :     assert(isReg() && "Wrong MachineOperand accessor");
     406    39715255 :     return IsDebug;
     407             :   }
     408             : 
     409             :   /// readsReg - Returns true if this operand reads the previous value of its
     410             :   /// register.  A use operand with the <undef> flag set doesn't read its
     411             :   /// register.  A sub-register def implicitly reads the other parts of the
     412             :   /// register being redefined unless the <undef> flag is set.
     413             :   ///
     414             :   /// This refers to reading the register value from before the current
     415             :   /// instruction or bundle. Internal bundle reads are not included.
     416             :   bool readsReg() const {
     417             :     assert(isReg() && "Wrong MachineOperand accessor");
     418   325184189 :     return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
     419             :   }
     420             : 
     421             :   //===--------------------------------------------------------------------===//
     422             :   // Mutators for Register Operands
     423             :   //===--------------------------------------------------------------------===//
     424             : 
     425             :   /// Change the register this operand corresponds to.
     426             :   ///
     427             :   void setReg(unsigned Reg);
     428             : 
     429             :   void setSubReg(unsigned subReg) {
     430             :     assert(isReg() && "Wrong MachineOperand mutator");
     431    19272834 :     SubReg_TargetFlags = subReg;
     432             :     assert(SubReg_TargetFlags == subReg && "SubReg out of range");
     433             :   }
     434             : 
     435             :   /// substVirtReg - Substitute the current register with the virtual
     436             :   /// subregister Reg:SubReg. Take any existing SubReg index into account,
     437             :   /// using TargetRegisterInfo to compose the subreg indices if necessary.
     438             :   /// Reg must be a virtual register, SubIdx can be 0.
     439             :   ///
     440             :   void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
     441             : 
     442             :   /// substPhysReg - Substitute the current register with the physical register
     443             :   /// Reg, taking any existing SubReg into account. For instance,
     444             :   /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
     445             :   ///
     446             :   void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
     447             : 
     448       16551 :   void setIsUse(bool Val = true) { setIsDef(!Val); }
     449             : 
     450             :   /// Change a def to a use, or a use to a def.
     451             :   void setIsDef(bool Val = true);
     452             : 
     453             :   void setImplicit(bool Val = true) {
     454             :     assert(isReg() && "Wrong MachineOperand mutator");
     455        1414 :     IsImp = Val;
     456             :   }
     457             : 
     458             :   void setIsKill(bool Val = true) {
     459             :     assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
     460             :     assert((!Val || !isDebug()) && "Marking a debug operation as kill");
     461    24780803 :     IsDeadOrKill = Val;
     462             :   }
     463             : 
     464             :   void setIsDead(bool Val = true) {
     465             :     assert(isReg() && IsDef && "Wrong MachineOperand mutator");
     466     3994031 :     IsDeadOrKill = Val;
     467             :   }
     468             : 
     469             :   void setIsUndef(bool Val = true) {
     470             :     assert(isReg() && "Wrong MachineOperand mutator");
     471     1703804 :     IsUndef = Val;
     472             :   }
     473             : 
     474             :   void setIsRenamable(bool Val = true);
     475             : 
     476             :   /// Set IsRenamable to true if there are no extra register allocation
     477             :   /// requirements placed on this operand by the parent instruction's opcode.
     478             :   void setIsRenamableIfNoExtraRegAllocReq();
     479             : 
     480             :   void setIsInternalRead(bool Val = true) {
     481             :     assert(isReg() && "Wrong MachineOperand mutator");
     482      953623 :     IsInternalRead = Val;
     483             :   }
     484             : 
     485             :   void setIsEarlyClobber(bool Val = true) {
     486             :     assert(isReg() && IsDef && "Wrong MachineOperand mutator");
     487        5481 :     IsEarlyClobber = Val;
     488             :   }
     489             : 
     490             :   void setIsDebug(bool Val = true) {
     491             :     assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
     492          37 :     IsDebug = Val;
     493             :   }
     494             : 
     495             :   //===--------------------------------------------------------------------===//
     496             :   // Accessors for various operand types.
     497             :   //===--------------------------------------------------------------------===//
     498             : 
     499             :   int64_t getImm() const {
     500             :     assert(isImm() && "Wrong MachineOperand accessor");
     501             :     return Contents.ImmVal;
     502             :   }
     503             : 
     504             :   const ConstantInt *getCImm() const {
     505             :     assert(isCImm() && "Wrong MachineOperand accessor");
     506             :     return Contents.CI;
     507             :   }
     508             : 
     509             :   const ConstantFP *getFPImm() const {
     510             :     assert(isFPImm() && "Wrong MachineOperand accessor");
     511             :     return Contents.CFP;
     512             :   }
     513             : 
     514             :   MachineBasicBlock *getMBB() const {
     515             :     assert(isMBB() && "Wrong MachineOperand accessor");
     516             :     return Contents.MBB;
     517             :   }
     518             : 
     519             :   int getIndex() const {
     520             :     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
     521             :            "Wrong MachineOperand accessor");
     522             :     return Contents.OffsetedInfo.Val.Index;
     523             :   }
     524             : 
     525             :   const GlobalValue *getGlobal() const {
     526             :     assert(isGlobal() && "Wrong MachineOperand accessor");
     527             :     return Contents.OffsetedInfo.Val.GV;
     528             :   }
     529             : 
     530             :   const BlockAddress *getBlockAddress() const {
     531             :     assert(isBlockAddress() && "Wrong MachineOperand accessor");
     532             :     return Contents.OffsetedInfo.Val.BA;
     533             :   }
     534             : 
     535             :   MCSymbol *getMCSymbol() const {
     536             :     assert(isMCSymbol() && "Wrong MachineOperand accessor");
     537             :     return Contents.Sym;
     538             :   }
     539             : 
     540             :   unsigned getCFIIndex() const {
     541             :     assert(isCFIIndex() && "Wrong MachineOperand accessor");
     542             :     return Contents.CFIIndex;
     543             :   }
     544             : 
     545             :   Intrinsic::ID getIntrinsicID() const {
     546             :     assert(isIntrinsicID() && "Wrong MachineOperand accessor");
     547             :     return Contents.IntrinsicID;
     548             :   }
     549             : 
     550             :   unsigned getPredicate() const {
     551             :     assert(isPredicate() && "Wrong MachineOperand accessor");
     552             :     return Contents.Pred;
     553             :   }
     554             : 
     555             :   /// Return the offset from the symbol in this operand. This always returns 0
     556             :   /// for ExternalSymbol operands.
     557             :   int64_t getOffset() const {
     558             :     assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
     559             :             isTargetIndex() || isBlockAddress()) &&
     560             :            "Wrong MachineOperand accessor");
     561     3167360 :     return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
     562     3167360 :            SmallContents.OffsetLo;
     563             :   }
     564             : 
     565             :   const char *getSymbolName() const {
     566             :     assert(isSymbol() && "Wrong MachineOperand accessor");
     567             :     return Contents.OffsetedInfo.Val.SymbolName;
     568             :   }
     569             : 
     570             :   /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
     571             :   /// It is sometimes necessary to detach the register mask pointer from its
     572             :   /// machine operand. This static method can be used for such detached bit
     573             :   /// mask pointers.
     574             :   static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
     575             :     // See TargetRegisterInfo.h.
     576             :     assert(PhysReg < (1u << 30) && "Not a physical register");
     577    61498382 :     return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
     578             :   }
     579             : 
     580             :   /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
     581             :   bool clobbersPhysReg(unsigned PhysReg) const {
     582    53700152 :      return clobbersPhysReg(getRegMask(), PhysReg);
     583             :   }
     584             : 
     585             :   /// getRegMask - Returns a bit mask of registers preserved by this RegMask
     586             :   /// operand.
     587             :   const uint32_t *getRegMask() const {
     588             :     assert(isRegMask() && "Wrong MachineOperand accessor");
     589             :     return Contents.RegMask;
     590             :   }
     591             : 
     592             :   /// getRegLiveOut - Returns a bit mask of live-out registers.
     593             :   const uint32_t *getRegLiveOut() const {
     594             :     assert(isRegLiveOut() && "Wrong MachineOperand accessor");
     595             :     return Contents.RegMask;
     596             :   }
     597             : 
     598             :   const MDNode *getMetadata() const {
     599             :     assert(isMetadata() && "Wrong MachineOperand accessor");
     600             :     return Contents.MD;
     601             :   }
     602             : 
     603             :   //===--------------------------------------------------------------------===//
     604             :   // Mutators for various operand types.
     605             :   //===--------------------------------------------------------------------===//
     606             : 
     607             :   void setImm(int64_t immVal) {
     608             :     assert(isImm() && "Wrong MachineOperand mutator");
     609     6935361 :     Contents.ImmVal = immVal;
     610             :   }
     611             : 
     612             :   void setFPImm(const ConstantFP *CFP) {
     613             :     assert(isFPImm() && "Wrong MachineOperand mutator");
     614             :     Contents.CFP = CFP;
     615             :   }
     616             : 
     617             :   void setOffset(int64_t Offset) {
     618             :     assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
     619             :             isTargetIndex() || isBlockAddress()) &&
     620             :            "Wrong MachineOperand mutator");
     621      940492 :     SmallContents.OffsetLo = unsigned(Offset);
     622      940492 :     Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
     623             :   }
     624             : 
     625             :   void setIndex(int Idx) {
     626             :     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
     627             :            "Wrong MachineOperand mutator");
     628      417626 :     Contents.OffsetedInfo.Val.Index = Idx;
     629             :   }
     630             : 
     631             :   void setMetadata(const MDNode *MD) {
     632             :     assert(isMetadata() && "Wrong MachineOperand mutator");
     633        1221 :     Contents.MD = MD;
     634             :   }
     635             : 
     636             :   void setMBB(MachineBasicBlock *MBB) {
     637             :     assert(isMBB() && "Wrong MachineOperand mutator");
     638      686680 :     Contents.MBB = MBB;
     639             :   }
     640             : 
     641             :   /// Sets value of register mask operand referencing Mask.  The
     642             :   /// operand does not take ownership of the memory referenced by Mask, it must
     643             :   /// remain valid for the lifetime of the operand. See CreateRegMask().
     644             :   /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
     645             :   void setRegMask(const uint32_t *RegMaskPtr) {
     646             :     assert(isRegMask() && "Wrong MachineOperand mutator");
     647          42 :     Contents.RegMask = RegMaskPtr;
     648             :   }
     649             : 
     650             :   //===--------------------------------------------------------------------===//
     651             :   // Other methods.
     652             :   //===--------------------------------------------------------------------===//
     653             : 
     654             :   /// Returns true if this operand is identical to the specified operand except
     655             :   /// for liveness related flags (isKill, isUndef and isDead). Note that this
     656             :   /// should stay in sync with the hash_value overload below.
     657             :   bool isIdenticalTo(const MachineOperand &Other) const;
     658             : 
     659             :   /// \brief MachineOperand hash_value overload.
     660             :   ///
     661             :   /// Note that this includes the same information in the hash that
     662             :   /// isIdenticalTo uses for comparison. It is thus suited for use in hash
     663             :   /// tables which use that function for equality comparisons only. This must
     664             :   /// stay exactly in sync with isIdenticalTo above.
     665             :   friend hash_code hash_value(const MachineOperand &MO);
     666             : 
     667             :   /// ChangeToImmediate - Replace this operand with a new immediate operand of
     668             :   /// the specified value.  If an operand is known to be an immediate already,
     669             :   /// the setImm method should be used.
     670             :   void ChangeToImmediate(int64_t ImmVal);
     671             : 
     672             :   /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
     673             :   /// of the specified value.  If an operand is known to be an FP immediate
     674             :   /// already, the setFPImm method should be used.
     675             :   void ChangeToFPImmediate(const ConstantFP *FPImm);
     676             : 
     677             :   /// ChangeToES - Replace this operand with a new external symbol operand.
     678             :   void ChangeToES(const char *SymName, unsigned char TargetFlags = 0);
     679             : 
     680             :   /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
     681             :   void ChangeToMCSymbol(MCSymbol *Sym);
     682             : 
     683             :   /// Replace this operand with a frame index.
     684             :   void ChangeToFrameIndex(int Idx);
     685             : 
     686             :   /// Replace this operand with a target index.
     687             :   void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
     688             :                            unsigned char TargetFlags = 0);
     689             : 
     690             :   /// ChangeToRegister - Replace this operand with a new register operand of
     691             :   /// the specified value.  If an operand is known to be an register already,
     692             :   /// the setReg method should be used.
     693             :   void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
     694             :                         bool isKill = false, bool isDead = false,
     695             :                         bool isUndef = false, bool isDebug = false);
     696             : 
     697             :   //===--------------------------------------------------------------------===//
     698             :   // Construction methods.
     699             :   //===--------------------------------------------------------------------===//
     700             : 
     701             :   static MachineOperand CreateImm(int64_t Val) {
     702             :     MachineOperand Op(MachineOperand::MO_Immediate);
     703             :     Op.setImm(Val);
     704             :     return Op;
     705             :   }
     706             : 
     707             :   static MachineOperand CreateCImm(const ConstantInt *CI) {
     708             :     MachineOperand Op(MachineOperand::MO_CImmediate);
     709         918 :     Op.Contents.CI = CI;
     710             :     return Op;
     711             :   }
     712             : 
     713             :   static MachineOperand CreateFPImm(const ConstantFP *CFP) {
     714             :     MachineOperand Op(MachineOperand::MO_FPImmediate);
     715         191 :     Op.Contents.CFP = CFP;
     716             :     return Op;
     717             :   }
     718             : 
     719             :   static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
     720             :                                   bool isKill = false, bool isDead = false,
     721             :                                   bool isUndef = false,
     722             :                                   bool isEarlyClobber = false,
     723             :                                   unsigned SubReg = 0, bool isDebug = false,
     724             :                                   bool isInternalRead = false,
     725             :                                   bool isRenamable = false) {
     726             :     assert(!(isDead && !isDef) && "Dead flag on non-def");
     727             :     assert(!(isKill && isDef) && "Kill flag on def");
     728             :     MachineOperand Op(MachineOperand::MO_Register);
     729    17034188 :     Op.IsDef = isDef;
     730    17034188 :     Op.IsImp = isImp;
     731    17088864 :     Op.IsDeadOrKill = isKill | isDead;
     732    17034188 :     Op.IsRenamable = isRenamable;
     733    17034188 :     Op.IsUndef = isUndef;
     734    17034188 :     Op.IsInternalRead = isInternalRead;
     735    17034188 :     Op.IsEarlyClobber = isEarlyClobber;
     736    17034188 :     Op.TiedTo = 0;
     737    17034188 :     Op.IsDebug = isDebug;
     738    17034188 :     Op.SmallContents.RegNo = Reg;
     739    17034188 :     Op.Contents.Reg.Prev = nullptr;
     740    17034188 :     Op.Contents.Reg.Next = nullptr;
     741             :     Op.setSubReg(SubReg);
     742             :     return Op;
     743             :   }
     744             :   static MachineOperand CreateMBB(MachineBasicBlock *MBB,
     745             :                                   unsigned char TargetFlags = 0) {
     746             :     MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
     747             :     Op.setMBB(MBB);
     748             :     Op.setTargetFlags(TargetFlags);
     749             :     return Op;
     750             :   }
     751             :   static MachineOperand CreateFI(int Idx) {
     752             :     MachineOperand Op(MachineOperand::MO_FrameIndex);
     753             :     Op.setIndex(Idx);
     754             :     return Op;
     755             :   }
     756             :   static MachineOperand CreateCPI(unsigned Idx, int Offset,
     757             :                                   unsigned char TargetFlags = 0) {
     758             :     MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
     759       28639 :     Op.setIndex(Idx);
     760           6 :     Op.setOffset(Offset);
     761             :     Op.setTargetFlags(TargetFlags);
     762             :     return Op;
     763             :   }
     764             :   static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
     765             :                                           unsigned char TargetFlags = 0) {
     766             :     MachineOperand Op(MachineOperand::MO_TargetIndex);
     767           0 :     Op.setIndex(Idx);
     768             :     Op.setOffset(Offset);
     769             :     Op.setTargetFlags(TargetFlags);
     770             :     return Op;
     771             :   }
     772             :   static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags = 0) {
     773             :     MachineOperand Op(MachineOperand::MO_JumpTableIndex);
     774          46 :     Op.setIndex(Idx);
     775             :     Op.setTargetFlags(TargetFlags);
     776             :     return Op;
     777             :   }
     778             :   static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
     779             :                                  unsigned char TargetFlags = 0) {
     780             :     MachineOperand Op(MachineOperand::MO_GlobalAddress);
     781      803742 :     Op.Contents.OffsetedInfo.Val.GV = GV;
     782             :     Op.setOffset(Offset);
     783             :     Op.setTargetFlags(TargetFlags);
     784             :     return Op;
     785             :   }
     786             :   static MachineOperand CreateES(const char *SymName,
     787             :                                  unsigned char TargetFlags = 0) {
     788             :     MachineOperand Op(MachineOperand::MO_ExternalSymbol);
     789       30666 :     Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
     790             :     Op.setOffset(0); // Offset is always 0.
     791             :     Op.setTargetFlags(TargetFlags);
     792             :     return Op;
     793             :   }
     794             :   static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
     795             :                                  unsigned char TargetFlags = 0) {
     796             :     MachineOperand Op(MachineOperand::MO_BlockAddress);
     797         130 :     Op.Contents.OffsetedInfo.Val.BA = BA;
     798             :     Op.setOffset(Offset);
     799             :     Op.setTargetFlags(TargetFlags);
     800             :     return Op;
     801             :   }
     802             :   /// CreateRegMask - Creates a register mask operand referencing Mask.  The
     803             :   /// operand does not take ownership of the memory referenced by Mask, it
     804             :   /// must remain valid for the lifetime of the operand.
     805             :   ///
     806             :   /// A RegMask operand represents a set of non-clobbered physical registers
     807             :   /// on an instruction that clobbers many registers, typically a call.  The
     808             :   /// bit mask has a bit set for each physreg that is preserved by this
     809             :   /// instruction, as described in the documentation for
     810             :   /// TargetRegisterInfo::getCallPreservedMask().
     811             :   ///
     812             :   /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
     813             :   ///
     814             :   static MachineOperand CreateRegMask(const uint32_t *Mask) {
     815             :     assert(Mask && "Missing register mask");
     816             :     MachineOperand Op(MachineOperand::MO_RegisterMask);
     817      196672 :     Op.Contents.RegMask = Mask;
     818             :     return Op;
     819             :   }
     820             :   static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
     821             :     assert(Mask && "Missing live-out register mask");
     822             :     MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
     823         149 :     Op.Contents.RegMask = Mask;
     824             :     return Op;
     825             :   }
     826             :   static MachineOperand CreateMetadata(const MDNode *Meta) {
     827             :     MachineOperand Op(MachineOperand::MO_Metadata);
     828      161161 :     Op.Contents.MD = Meta;
     829             :     return Op;
     830             :   }
     831             : 
     832             :   static MachineOperand CreateMCSymbol(MCSymbol *Sym,
     833             :                                        unsigned char TargetFlags = 0) {
     834             :     MachineOperand Op(MachineOperand::MO_MCSymbol);
     835       76744 :     Op.Contents.Sym = Sym;
     836             :     Op.setOffset(0);
     837             :     Op.setTargetFlags(TargetFlags);
     838             :     return Op;
     839             :   }
     840             : 
     841             :   static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
     842             :     MachineOperand Op(MachineOperand::MO_CFIIndex);
     843      241398 :     Op.Contents.CFIIndex = CFIIndex;
     844             :     return Op;
     845             :   }
     846             : 
     847             :   static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
     848             :     MachineOperand Op(MachineOperand::MO_IntrinsicID);
     849          10 :     Op.Contents.IntrinsicID = ID;
     850             :     return Op;
     851             :   }
     852             : 
     853             :   static MachineOperand CreatePredicate(unsigned Pred) {
     854             :     MachineOperand Op(MachineOperand::MO_Predicate);
     855         125 :     Op.Contents.Pred = Pred;
     856             :     return Op;
     857             :   }
     858             : 
     859             :   friend class MachineInstr;
     860             :   friend class MachineRegisterInfo;
     861             : 
     862             : private:
     863             :   // If this operand is currently a register operand, and if this is in a
     864             :   // function, deregister the operand from the register's use/def list.
     865             :   void removeRegFromUses();
     866             : 
     867             :   /// Artificial kinds for DenseMap usage.
     868             :   enum : unsigned char {
     869             :     MO_Empty = MO_Last + 1,
     870             :     MO_Tombstone,
     871             :   };
     872             : 
     873             :   friend struct DenseMapInfo<MachineOperand>;
     874             : 
     875             :   //===--------------------------------------------------------------------===//
     876             :   // Methods for handling register use/def lists.
     877             :   //===--------------------------------------------------------------------===//
     878             : 
     879             :   /// isOnRegUseList - Return true if this operand is on a register use/def
     880             :   /// list or false if not.  This can only be called for register operands
     881             :   /// that are part of a machine instruction.
     882             :   bool isOnRegUseList() const {
     883             :     assert(isReg() && "Can only add reg operand to use lists");
     884             :     return Contents.Reg.Prev != nullptr;
     885             :   }
     886             : };
     887             : 
     888             : template <> struct DenseMapInfo<MachineOperand> {
     889             :   static MachineOperand getEmptyKey() {
     890             :     return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
     891             :         MachineOperand::MO_Empty));
     892             :   }
     893             :   static MachineOperand getTombstoneKey() {
     894             :     return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
     895             :         MachineOperand::MO_Tombstone));
     896             :   }
     897             :   static unsigned getHashValue(const MachineOperand &MO) {
     898       35228 :     return hash_value(MO);
     899             :   }
     900             :   static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
     901             :     if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
     902      967793 :                              MachineOperand::MO_Empty) ||
     903             :         LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
     904             :                              MachineOperand::MO_Tombstone))
     905      916419 :       return LHS.getType() == RHS.getType();
     906       51374 :     return LHS.isIdenticalTo(RHS);
     907             :   }
     908             : };
     909             : 
     910             : inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
     911             :   MO.print(OS);
     912             :   return OS;
     913             : }
     914             : 
     915             : // See friend declaration above. This additional declaration is required in
     916             : // order to compile LLVM with IBM xlC compiler.
     917             : hash_code hash_value(const MachineOperand &MO);
     918             : } // namespace llvm
     919             : 
     920             : #endif

Generated by: LCOV version 1.13