LCOV - code coverage report
Current view: top level - include/llvm/CodeGen - MachineRegisterInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 122 122 100.0 %
Date: 2018-06-17 00:07:59 Functions: 20 20 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines the MachineRegisterInfo class.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
      15             : #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
      16             : 
      17             : #include "llvm/ADT/ArrayRef.h"
      18             : #include "llvm/ADT/BitVector.h"
      19             : #include "llvm/ADT/DenseMap.h"
      20             : #include "llvm/ADT/IndexedMap.h"
      21             : #include "llvm/ADT/PointerUnion.h"
      22             : #include "llvm/ADT/SmallVector.h"
      23             : #include "llvm/ADT/StringSet.h"
      24             : #include "llvm/ADT/iterator_range.h"
      25             : #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
      26             : #include "llvm/CodeGen/LowLevelType.h"
      27             : #include "llvm/CodeGen/MachineBasicBlock.h"
      28             : #include "llvm/CodeGen/MachineFunction.h"
      29             : #include "llvm/CodeGen/MachineInstrBundle.h"
      30             : #include "llvm/CodeGen/MachineOperand.h"
      31             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      32             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      33             : #include "llvm/MC/LaneBitmask.h"
      34             : #include <cassert>
      35             : #include <cstddef>
      36             : #include <cstdint>
      37             : #include <iterator>
      38             : #include <memory>
      39             : #include <utility>
      40             : #include <vector>
      41             : 
      42             : namespace llvm {
      43             : 
      44             : class PSetIterator;
      45             : 
      46             : /// Convenient type to represent either a register class or a register bank.
      47             : using RegClassOrRegBank =
      48             :     PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
      49             : 
      50             : /// MachineRegisterInfo - Keep track of information for virtual and physical
      51             : /// registers, including vreg register classes, use/def chains for registers,
      52             : /// etc.
      53      925744 : class MachineRegisterInfo {
      54             : public:
      55             :   class Delegate {
      56             :     virtual void anchor();
      57             : 
      58             :   public:
      59             :     virtual ~Delegate() = default;
      60             : 
      61             :     virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
      62             :   };
      63             : 
      64             : private:
      65             :   MachineFunction *MF;
      66             :   Delegate *TheDelegate = nullptr;
      67             : 
      68             :   /// True if subregister liveness is tracked.
      69             :   const bool TracksSubRegLiveness;
      70             : 
      71             :   /// VRegInfo - Information we keep for each virtual register.
      72             :   ///
      73             :   /// Each element in this list contains the register class of the vreg and the
      74             :   /// start of the use/def list for the register.
      75             :   IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
      76             :              VirtReg2IndexFunctor>
      77             :       VRegInfo;
      78             : 
      79             :   /// Map for recovering vreg name from vreg number.
      80             :   /// This map is used by the MIR Printer.
      81             :   IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
      82             : 
      83             :   /// StringSet that is used to unique vreg names.
      84             :   StringSet<> VRegNames;
      85             : 
      86             :   /// The flag is true upon \p UpdatedCSRs initialization
      87             :   /// and false otherwise.
      88             :   bool IsUpdatedCSRsInitialized;
      89             : 
      90             :   /// Contains the updated callee saved register list.
      91             :   /// As opposed to the static list defined in register info,
      92             :   /// all registers that were disabled are removed from the list.
      93             :   SmallVector<MCPhysReg, 16> UpdatedCSRs;
      94             : 
      95             :   /// RegAllocHints - This vector records register allocation hints for
      96             :   /// virtual registers. For each virtual register, it keeps a pair of hint
      97             :   /// type and hints vector making up the allocation hints. Only the first
      98             :   /// hint may be target specific, and in that case this is reflected by the
      99             :   /// first member of the pair being non-zero. If the hinted register is
     100             :   /// virtual, it means the allocator should prefer the physical register
     101             :   /// allocated to it if any.
     102             :   IndexedMap<std::pair<unsigned, SmallVector<unsigned, 4>>,
     103             :              VirtReg2IndexFunctor> RegAllocHints;
     104             : 
     105             :   /// PhysRegUseDefLists - This is an array of the head of the use/def list for
     106             :   /// physical registers.
     107             :   std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
     108             : 
     109             :   /// getRegUseDefListHead - Return the head pointer for the register use/def
     110             :   /// list for the specified virtual or physical register.
     111             :   MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
     112    55306302 :     if (TargetRegisterInfo::isVirtualRegister(RegNo))
     113    24180561 :       return VRegInfo[RegNo].second;
     114    31125741 :     return PhysRegUseDefLists[RegNo];
     115             :   }
     116             : 
     117             :   MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
     118   358920987 :     if (TargetRegisterInfo::isVirtualRegister(RegNo))
     119    72640441 :       return VRegInfo[RegNo].second;
     120   596540659 :     return PhysRegUseDefLists[RegNo];
     121             :   }
     122             : 
     123             :   /// Get the next element in the use-def chain.
     124             :   static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
     125             :     assert(MO && MO->isReg() && "This is not a register operand!");
     126             :     return MO->Contents.Reg.Next;
     127             :   }
     128             : 
     129             :   /// UsedPhysRegMask - Additional used physregs including aliases.
     130             :   /// This bit vector represents all the registers clobbered by function calls.
     131             :   BitVector UsedPhysRegMask;
     132             : 
     133             :   /// ReservedRegs - This is a bit vector of reserved registers.  The target
     134             :   /// may change its mind about which registers should be reserved.  This
     135             :   /// vector is the frozen set of reserved registers when register allocation
     136             :   /// started.
     137             :   BitVector ReservedRegs;
     138             : 
     139             :   using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
     140             :   /// Map generic virtual registers to their low-level type.
     141             :   VRegToTypeMap VRegToType;
     142             : 
     143             :   /// Keep track of the physical registers that are live in to the function.
     144             :   /// Live in values are typically arguments in registers.  LiveIn values are
     145             :   /// allowed to have virtual registers associated with them, stored in the
     146             :   /// second element.
     147             :   std::vector<std::pair<unsigned, unsigned>> LiveIns;
     148             : 
     149             : public:
     150             :   explicit MachineRegisterInfo(MachineFunction *MF);
     151             :   MachineRegisterInfo(const MachineRegisterInfo &) = delete;
     152             :   MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
     153             : 
     154             :   const TargetRegisterInfo *getTargetRegisterInfo() const {
     155    66996021 :     return MF->getSubtarget().getRegisterInfo();
     156             :   }
     157             : 
     158             :   void resetDelegate(Delegate *delegate) {
     159             :     // Ensure another delegate does not take over unless the current
     160             :     // delegate first unattaches itself. If we ever need to multicast
     161             :     // notifications, we will need to change to using a list.
     162             :     assert(TheDelegate == delegate &&
     163             :            "Only the current delegate can perform reset!");
     164      281723 :     TheDelegate = nullptr;
     165             :   }
     166             : 
     167             :   void setDelegate(Delegate *delegate) {
     168             :     assert(delegate && !TheDelegate &&
     169             :            "Attempted to set delegate to null, or to change it without "
     170             :            "first resetting it!");
     171             : 
     172      281723 :     TheDelegate = delegate;
     173             :   }
     174             : 
     175             :   //===--------------------------------------------------------------------===//
     176             :   // Function State
     177             :   //===--------------------------------------------------------------------===//
     178             : 
     179             :   // isSSA - Returns true when the machine function is in SSA form. Early
     180             :   // passes require the machine function to be in SSA form where every virtual
     181             :   // register has a single defining instruction.
     182             :   //
     183             :   // The TwoAddressInstructionPass and PHIElimination passes take the machine
     184             :   // function out of SSA form when they introduce multiple defs per virtual
     185             :   // register.
     186             :   bool isSSA() const {
     187             :     return MF->getProperties().hasProperty(
     188             :         MachineFunctionProperties::Property::IsSSA);
     189             :   }
     190             : 
     191             :   // leaveSSA - Indicates that the machine function is no longer in SSA form.
     192             :   void leaveSSA() {
     193             :     MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA);
     194             :   }
     195             : 
     196             :   /// tracksLiveness - Returns true when tracking register liveness accurately.
     197             :   /// (see MachineFUnctionProperties::Property description for details)
     198             :   bool tracksLiveness() const {
     199             :     return MF->getProperties().hasProperty(
     200             :         MachineFunctionProperties::Property::TracksLiveness);
     201             :   }
     202             : 
     203             :   /// invalidateLiveness - Indicates that register liveness is no longer being
     204             :   /// tracked accurately.
     205             :   ///
     206             :   /// This should be called by late passes that invalidate the liveness
     207             :   /// information.
     208             :   void invalidateLiveness() {
     209             :     MF->getProperties().reset(
     210             :         MachineFunctionProperties::Property::TracksLiveness);
     211             :   }
     212             : 
     213             :   /// Returns true if liveness for register class @p RC should be tracked at
     214             :   /// the subregister level.
     215             :   bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
     216     6201715 :     return subRegLivenessEnabled() && RC.HasDisjunctSubRegs;
     217             :   }
     218             :   bool shouldTrackSubRegLiveness(unsigned VReg) const {
     219             :     assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
     220             :     return shouldTrackSubRegLiveness(*getRegClass(VReg));
     221             :   }
     222             :   bool subRegLivenessEnabled() const {
     223             :     return TracksSubRegLiveness;
     224             :   }
     225             : 
     226             :   //===--------------------------------------------------------------------===//
     227             :   // Register Info
     228             :   //===--------------------------------------------------------------------===//
     229             : 
     230             :   /// Returns true if the updated CSR list was initialized and false otherwise.
     231             :   bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
     232             : 
     233             :   /// Disables the register from the list of CSRs.
     234             :   /// I.e. the register will not appear as part of the CSR mask.
     235             :   /// \see UpdatedCalleeSavedRegs.
     236             :   void disableCalleeSavedRegister(unsigned Reg);
     237             : 
     238             :   /// Returns list of callee saved registers.
     239             :   /// The function returns the updated CSR list (after taking into account
     240             :   /// registers that are disabled from the CSR list).
     241             :   const MCPhysReg *getCalleeSavedRegs() const;
     242             : 
     243             :   /// Sets the updated Callee Saved Registers list.
     244             :   /// Notice that it will override ant previously disabled/saved CSRs.
     245             :   void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
     246             : 
     247             :   // Strictly for use by MachineInstr.cpp.
     248             :   void addRegOperandToUseList(MachineOperand *MO);
     249             : 
     250             :   // Strictly for use by MachineInstr.cpp.
     251             :   void removeRegOperandFromUseList(MachineOperand *MO);
     252             : 
     253             :   // Strictly for use by MachineInstr.cpp.
     254             :   void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
     255             : 
     256             :   /// Verify the sanity of the use list for Reg.
     257             :   void verifyUseList(unsigned Reg) const;
     258             : 
     259             :   /// Verify the use list of all registers.
     260             :   void verifyUseLists() const;
     261             : 
     262             :   /// reg_begin/reg_end - Provide iteration support to walk over all definitions
     263             :   /// and uses of a register within the MachineFunction that corresponds to this
     264             :   /// MachineRegisterInfo object.
     265             :   template<bool Uses, bool Defs, bool SkipDebug,
     266             :            bool ByOperand, bool ByInstr, bool ByBundle>
     267             :   class defusechain_iterator;
     268             :   template<bool Uses, bool Defs, bool SkipDebug,
     269             :            bool ByOperand, bool ByInstr, bool ByBundle>
     270             :   class defusechain_instr_iterator;
     271             : 
     272             :   // Make it a friend so it can access getNextOperandForReg().
     273             :   template<bool, bool, bool, bool, bool, bool>
     274             :     friend class defusechain_iterator;
     275             :   template<bool, bool, bool, bool, bool, bool>
     276             :     friend class defusechain_instr_iterator;
     277             : 
     278             :   /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
     279             :   /// register.
     280             :   using reg_iterator =
     281             :       defusechain_iterator<true, true, false, true, false, false>;
     282             :   reg_iterator reg_begin(unsigned RegNo) const {
     283             :     return reg_iterator(getRegUseDefListHead(RegNo));
     284             :   }
     285             :   static reg_iterator reg_end() { return reg_iterator(nullptr); }
     286             : 
     287             :   inline iterator_range<reg_iterator>  reg_operands(unsigned Reg) const {
     288             :     return make_range(reg_begin(Reg), reg_end());
     289             :   }
     290             : 
     291             :   /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
     292             :   /// of the specified register, stepping by MachineInstr.
     293             :   using reg_instr_iterator =
     294             :       defusechain_instr_iterator<true, true, false, false, true, false>;
     295             :   reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
     296             :     return reg_instr_iterator(getRegUseDefListHead(RegNo));
     297             :   }
     298             :   static reg_instr_iterator reg_instr_end() {
     299             :     return reg_instr_iterator(nullptr);
     300             :   }
     301             : 
     302             :   inline iterator_range<reg_instr_iterator>
     303             :   reg_instructions(unsigned Reg) const {
     304             :     return make_range(reg_instr_begin(Reg), reg_instr_end());
     305             :   }
     306             : 
     307             :   /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
     308             :   /// of the specified register, stepping by bundle.
     309             :   using reg_bundle_iterator =
     310             :       defusechain_instr_iterator<true, true, false, false, false, true>;
     311             :   reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
     312             :     return reg_bundle_iterator(getRegUseDefListHead(RegNo));
     313             :   }
     314             :   static reg_bundle_iterator reg_bundle_end() {
     315             :     return reg_bundle_iterator(nullptr);
     316             :   }
     317             : 
     318             :   inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
     319             :     return make_range(reg_bundle_begin(Reg), reg_bundle_end());
     320             :   }
     321             : 
     322             :   /// reg_empty - Return true if there are no instructions using or defining the
     323             :   /// specified register (it may be live-in).
     324             :   bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
     325             : 
     326             :   /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
     327             :   /// of the specified register, skipping those marked as Debug.
     328             :   using reg_nodbg_iterator =
     329             :       defusechain_iterator<true, true, true, true, false, false>;
     330   196517378 :   reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
     331   196517378 :     return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
     332             :   }
     333             :   static reg_nodbg_iterator reg_nodbg_end() {
     334             :     return reg_nodbg_iterator(nullptr);
     335             :   }
     336             : 
     337             :   inline iterator_range<reg_nodbg_iterator>
     338             :   reg_nodbg_operands(unsigned Reg) const {
     339     5915652 :     return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
     340             :   }
     341             : 
     342             :   /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
     343             :   /// all defs and uses of the specified register, stepping by MachineInstr,
     344             :   /// skipping those marked as Debug.
     345             :   using reg_instr_nodbg_iterator =
     346             :       defusechain_instr_iterator<true, true, true, false, true, false>;
     347       62789 :   reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
     348       62789 :     return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
     349             :   }
     350             :   static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
     351             :     return reg_instr_nodbg_iterator(nullptr);
     352             :   }
     353             : 
     354             :   inline iterator_range<reg_instr_nodbg_iterator>
     355             :   reg_nodbg_instructions(unsigned Reg) const {
     356       49332 :     return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
     357             :   }
     358             : 
     359             :   /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
     360             :   /// all defs and uses of the specified register, stepping by bundle,
     361             :   /// skipping those marked as Debug.
     362             :   using reg_bundle_nodbg_iterator =
     363             :       defusechain_instr_iterator<true, true, true, false, false, true>;
     364             :   reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
     365             :     return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
     366             :   }
     367             :   static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
     368             :     return reg_bundle_nodbg_iterator(nullptr);
     369             :   }
     370             : 
     371             :   inline iterator_range<reg_bundle_nodbg_iterator>
     372             :   reg_nodbg_bundles(unsigned Reg) const {
     373             :     return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
     374             :   }
     375             : 
     376             :   /// reg_nodbg_empty - Return true if the only instructions using or defining
     377             :   /// Reg are Debug instructions.
     378             :   bool reg_nodbg_empty(unsigned RegNo) const {
     379   380344640 :     return reg_nodbg_begin(RegNo) == reg_nodbg_end();
     380             :   }
     381             : 
     382             :   /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
     383             :   using def_iterator =
     384             :       defusechain_iterator<false, true, false, true, false, false>;
     385   132910190 :   def_iterator def_begin(unsigned RegNo) const {
     386   132910190 :     return def_iterator(getRegUseDefListHead(RegNo));
     387             :   }
     388             :   static def_iterator def_end() { return def_iterator(nullptr); }
     389             : 
     390             :   inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
     391     1038158 :     return make_range(def_begin(Reg), def_end());
     392             :   }
     393             : 
     394             :   /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
     395             :   /// specified register, stepping by MachineInst.
     396             :   using def_instr_iterator =
     397             :       defusechain_instr_iterator<false, true, false, false, true, false>;
     398     7603230 :   def_instr_iterator def_instr_begin(unsigned RegNo) const {
     399     7603230 :     return def_instr_iterator(getRegUseDefListHead(RegNo));
     400             :   }
     401             :   static def_instr_iterator def_instr_end() {
     402             :     return def_instr_iterator(nullptr);
     403             :   }
     404             : 
     405             :   inline iterator_range<def_instr_iterator>
     406             :   def_instructions(unsigned Reg) const {
     407      199731 :     return make_range(def_instr_begin(Reg), def_instr_end());
     408             :   }
     409             : 
     410             :   /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
     411             :   /// specified register, stepping by bundle.
     412             :   using def_bundle_iterator =
     413             :       defusechain_instr_iterator<false, true, false, false, false, true>;
     414             :   def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
     415             :     return def_bundle_iterator(getRegUseDefListHead(RegNo));
     416             :   }
     417             :   static def_bundle_iterator def_bundle_end() {
     418             :     return def_bundle_iterator(nullptr);
     419             :   }
     420             : 
     421             :   inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
     422             :     return make_range(def_bundle_begin(Reg), def_bundle_end());
     423             :   }
     424             : 
     425             :   /// def_empty - Return true if there are no instructions defining the
     426             :   /// specified register (it may be live-in).
     427   157780622 :   bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
     428             : 
     429             :   StringRef getVRegName(unsigned Reg) const {
     430       71721 :     return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
     431             :   }
     432             : 
     433     3347704 :   void insertVRegByName(StringRef Name, unsigned Reg) {
     434             :     assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
     435             :            "Named VRegs Must be Unique.");
     436     3347704 :     if (!Name.empty()) {
     437             :       VRegNames.insert(Name);
     438          94 :       VReg2Name.grow(Reg);
     439         188 :       VReg2Name[Reg] = Name.str();
     440             :     }
     441     3347704 :   }
     442             : 
     443             :   /// Return true if there is exactly one operand defining the specified
     444             :   /// register.
     445     3316464 :   bool hasOneDef(unsigned RegNo) const {
     446     3316464 :     def_iterator DI = def_begin(RegNo);
     447     3316464 :     if (DI == def_end())
     448             :       return false;
     449             :     return ++DI == def_end();
     450             :   }
     451             : 
     452             :   /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
     453             :   using use_iterator =
     454             :       defusechain_iterator<true, false, false, true, false, false>;
     455     2694919 :   use_iterator use_begin(unsigned RegNo) const {
     456     2694919 :     return use_iterator(getRegUseDefListHead(RegNo));
     457             :   }
     458             :   static use_iterator use_end() { return use_iterator(nullptr); }
     459             : 
     460             :   inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
     461     1651176 :     return make_range(use_begin(Reg), use_end());
     462             :   }
     463             : 
     464             :   /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
     465             :   /// specified register, stepping by MachineInstr.
     466             :   using use_instr_iterator =
     467             :       defusechain_instr_iterator<true, false, false, false, true, false>;
     468      328951 :   use_instr_iterator use_instr_begin(unsigned RegNo) const {
     469      328951 :     return use_instr_iterator(getRegUseDefListHead(RegNo));
     470             :   }
     471             :   static use_instr_iterator use_instr_end() {
     472             :     return use_instr_iterator(nullptr);
     473             :   }
     474             : 
     475             :   inline iterator_range<use_instr_iterator>
     476             :   use_instructions(unsigned Reg) const {
     477      105903 :     return make_range(use_instr_begin(Reg), use_instr_end());
     478             :   }
     479             : 
     480             :   /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
     481             :   /// specified register, stepping by bundle.
     482             :   using use_bundle_iterator =
     483             :       defusechain_instr_iterator<true, false, false, false, false, true>;
     484             :   use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
     485             :     return use_bundle_iterator(getRegUseDefListHead(RegNo));
     486             :   }
     487             :   static use_bundle_iterator use_bundle_end() {
     488             :     return use_bundle_iterator(nullptr);
     489             :   }
     490             : 
     491             :   inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
     492             :     return make_range(use_bundle_begin(Reg), use_bundle_end());
     493             :   }
     494             : 
     495             :   /// use_empty - Return true if there are no instructions using the specified
     496             :   /// register.
     497      512268 :   bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
     498             : 
     499             :   /// hasOneUse - Return true if there is exactly one instruction using the
     500             :   /// specified register.
     501      169753 :   bool hasOneUse(unsigned RegNo) const {
     502      169753 :     use_iterator UI = use_begin(RegNo);
     503      169753 :     if (UI == use_end())
     504             :       return false;
     505             :     return ++UI == use_end();
     506             :   }
     507             : 
     508             :   /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
     509             :   /// specified register, skipping those marked as Debug.
     510             :   using use_nodbg_iterator =
     511             :       defusechain_iterator<true, false, true, true, false, false>;
     512    13928301 :   use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
     513    13928301 :     return use_nodbg_iterator(getRegUseDefListHead(RegNo));
     514             :   }
     515             :   static use_nodbg_iterator use_nodbg_end() {
     516             :     return use_nodbg_iterator(nullptr);
     517             :   }
     518             : 
     519             :   inline iterator_range<use_nodbg_iterator>
     520             :   use_nodbg_operands(unsigned Reg) const {
     521     3025908 :     return make_range(use_nodbg_begin(Reg), use_nodbg_end());
     522             :   }
     523             : 
     524             :   /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
     525             :   /// all uses of the specified register, stepping by MachineInstr, skipping
     526             :   /// those marked as Debug.
     527             :   using use_instr_nodbg_iterator =
     528             :       defusechain_instr_iterator<true, false, true, false, true, false>;
     529     1978680 :   use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
     530     1978680 :     return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
     531             :   }
     532             :   static use_instr_nodbg_iterator use_instr_nodbg_end() {
     533             :     return use_instr_nodbg_iterator(nullptr);
     534             :   }
     535             : 
     536             :   inline iterator_range<use_instr_nodbg_iterator>
     537             :   use_nodbg_instructions(unsigned Reg) const {
     538      849590 :     return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
     539             :   }
     540             : 
     541             :   /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
     542             :   /// all uses of the specified register, stepping by bundle, skipping
     543             :   /// those marked as Debug.
     544             :   using use_bundle_nodbg_iterator =
     545             :       defusechain_instr_iterator<true, false, true, false, false, true>;
     546             :   use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
     547             :     return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
     548             :   }
     549             :   static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
     550             :     return use_bundle_nodbg_iterator(nullptr);
     551             :   }
     552             : 
     553             :   inline iterator_range<use_bundle_nodbg_iterator>
     554             :   use_nodbg_bundles(unsigned Reg) const {
     555             :     return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
     556             :   }
     557             : 
     558             :   /// use_nodbg_empty - Return true if there are no non-Debug instructions
     559             :   /// using the specified register.
     560             :   bool use_nodbg_empty(unsigned RegNo) const {
     561    13019514 :     return use_nodbg_begin(RegNo) == use_nodbg_end();
     562             :   }
     563             : 
     564             :   /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
     565             :   /// instruction using the specified register.
     566             :   bool hasOneNonDBGUse(unsigned RegNo) const;
     567             : 
     568             :   /// replaceRegWith - Replace all instances of FromReg with ToReg in the
     569             :   /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
     570             :   /// except that it also changes any definitions of the register as well.
     571             :   ///
     572             :   /// Note that it is usually necessary to first constrain ToReg's register
     573             :   /// class and register bank to match the FromReg constraints using one of the
     574             :   /// methods:
     575             :   ///
     576             :   ///   constrainRegClass(ToReg, getRegClass(FromReg))
     577             :   ///   constrainRegAttrs(ToReg, FromReg)
     578             :   ///   RegisterBankInfo::constrainGenericRegister(ToReg,
     579             :   ///       *MRI.getRegClass(FromReg), MRI)
     580             :   ///
     581             :   /// These functions will return a falsy result if the virtual registers have
     582             :   /// incompatible constraints.
     583             :   ///
     584             :   /// Note that if ToReg is a physical register the function will replace and
     585             :   /// apply sub registers to ToReg in order to obtain a final/proper physical
     586             :   /// register.
     587             :   void replaceRegWith(unsigned FromReg, unsigned ToReg);
     588             : 
     589             :   /// getVRegDef - Return the machine instr that defines the specified virtual
     590             :   /// register or null if none is found.  This assumes that the code is in SSA
     591             :   /// form, so there should only be one definition.
     592             :   MachineInstr *getVRegDef(unsigned Reg) const;
     593             : 
     594             :   /// getUniqueVRegDef - Return the unique machine instr that defines the
     595             :   /// specified virtual register or null if none is found.  If there are
     596             :   /// multiple definitions or no definition, return null.
     597             :   MachineInstr *getUniqueVRegDef(unsigned Reg) const;
     598             : 
     599             :   /// clearKillFlags - Iterate over all the uses of the given register and
     600             :   /// clear the kill flag from the MachineOperand. This function is used by
     601             :   /// optimization passes which extend register lifetimes and need only
     602             :   /// preserve conservative kill flag information.
     603             :   void clearKillFlags(unsigned Reg) const;
     604             : 
     605             :   void dumpUses(unsigned RegNo) const;
     606             : 
     607             :   /// Returns true if PhysReg is unallocatable and constant throughout the
     608             :   /// function. Writing to a constant register has no effect.
     609             :   bool isConstantPhysReg(unsigned PhysReg) const;
     610             : 
     611             :   /// Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg
     612             :   /// returns true. This is a utility member function.
     613             :   bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const;
     614             : 
     615             :   /// Get an iterator over the pressure sets affected by the given physical or
     616             :   /// virtual register. If RegUnit is physical, it must be a register unit (from
     617             :   /// MCRegUnitIterator).
     618             :   PSetIterator getPressureSets(unsigned RegUnit) const;
     619             : 
     620             :   //===--------------------------------------------------------------------===//
     621             :   // Virtual Register Info
     622             :   //===--------------------------------------------------------------------===//
     623             : 
     624             :   /// Return the register class of the specified virtual register.
     625             :   /// This shouldn't be used directly unless \p Reg has a register class.
     626             :   /// \see getRegClassOrNull when this might happen.
     627             :   const TargetRegisterClass *getRegClass(unsigned Reg) const {
     628             :     assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() &&
     629             :            "Register class not set, wrong accessor");
     630             :     return VRegInfo[Reg].first.get<const TargetRegisterClass *>();
     631             :   }
     632             : 
     633             :   /// Return the register class of \p Reg, or null if Reg has not been assigned
     634             :   /// a register class yet.
     635             :   ///
     636             :   /// \note A null register class can only happen when these two
     637             :   /// conditions are met:
     638             :   /// 1. Generic virtual registers are created.
     639             :   /// 2. The machine function has not completely been through the
     640             :   ///    instruction selection process.
     641             :   /// None of this condition is possible without GlobalISel for now.
     642             :   /// In other words, if GlobalISel is not used or if the query happens after
     643             :   /// the select pass, using getRegClass is safe.
     644             :   const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
     645             :     const RegClassOrRegBank &Val = VRegInfo[Reg].first;
     646             :     return Val.dyn_cast<const TargetRegisterClass *>();
     647             :   }
     648             : 
     649             :   /// Return the register bank of \p Reg, or null if Reg has not been assigned
     650             :   /// a register bank or has been assigned a register class.
     651             :   /// \note It is possible to get the register bank from the register class via
     652             :   /// RegisterBankInfo::getRegBankFromRegClass.
     653             :   const RegisterBank *getRegBankOrNull(unsigned Reg) const {
     654             :     const RegClassOrRegBank &Val = VRegInfo[Reg].first;
     655             :     return Val.dyn_cast<const RegisterBank *>();
     656             :   }
     657             : 
     658             :   /// Return the register bank or register class of \p Reg.
     659             :   /// \note Before the register bank gets assigned (i.e., before the
     660             :   /// RegBankSelect pass) \p Reg may not have either.
     661             :   const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
     662             :     return VRegInfo[Reg].first;
     663             :   }
     664             : 
     665             :   /// setRegClass - Set the register class of the specified virtual register.
     666             :   void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
     667             : 
     668             :   /// Set the register bank to \p RegBank for \p Reg.
     669             :   void setRegBank(unsigned Reg, const RegisterBank &RegBank);
     670             : 
     671             :   void setRegClassOrRegBank(unsigned Reg,
     672             :                             const RegClassOrRegBank &RCOrRB){
     673          31 :     VRegInfo[Reg].first = RCOrRB;
     674             :   }
     675             : 
     676             :   /// constrainRegClass - Constrain the register class of the specified virtual
     677             :   /// register to be a common subclass of RC and the current register class,
     678             :   /// but only if the new class has at least MinNumRegs registers.  Return the
     679             :   /// new register class, or NULL if no such class exists.
     680             :   /// This should only be used when the constraint is known to be trivial, like
     681             :   /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
     682             :   ///
     683             :   /// \note Assumes that the register has a register class assigned.
     684             :   /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
     685             :   /// InstructionSelect pass and constrainRegAttrs in every other pass,
     686             :   /// including non-select passes of GlobalISel, instead.
     687             :   const TargetRegisterClass *constrainRegClass(unsigned Reg,
     688             :                                                const TargetRegisterClass *RC,
     689             :                                                unsigned MinNumRegs = 0);
     690             : 
     691             :   /// Constrain the register class or the register bank of the virtual register
     692             :   /// \p Reg to be a common subclass and a common bank of both registers
     693             :   /// provided respectively. Do nothing if any of the attributes (classes,
     694             :   /// banks, or low-level types) of the registers are deemed incompatible, or if
     695             :   /// the resulting register will have a class smaller than before and of size
     696             :   /// less than \p MinNumRegs. Return true if such register attributes exist,
     697             :   /// false otherwise.
     698             :   ///
     699             :   /// \note Assumes that each register has either a low-level type or a class
     700             :   /// assigned, but not both. Use this method instead of constrainRegClass and
     701             :   /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
     702             :   /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
     703             :   bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg,
     704             :                          unsigned MinNumRegs = 0);
     705             : 
     706             :   /// recomputeRegClass - Try to find a legal super-class of Reg's register
     707             :   /// class that still satisfies the constraints from the instructions using
     708             :   /// Reg.  Returns true if Reg was upgraded.
     709             :   ///
     710             :   /// This method can be used after constraints have been removed from a
     711             :   /// virtual register, for example after removing instructions or splitting
     712             :   /// the live range.
     713             :   bool recomputeRegClass(unsigned Reg);
     714             : 
     715             :   /// createVirtualRegister - Create and return a new virtual register in the
     716             :   /// function with the specified register class.
     717             :   unsigned createVirtualRegister(const TargetRegisterClass *RegClass,
     718             :                                  StringRef Name = "");
     719             : 
     720             :   /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
     721             :   /// (target independent) virtual register.
     722             :   LLT getType(unsigned Reg) const {
     723    15821654 :     if (TargetRegisterInfo::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
     724      143741 :       return VRegToType[Reg];
     725             :     return LLT{};
     726             :   }
     727             : 
     728             :   /// Set the low-level type of \p VReg to \p Ty.
     729             :   void setType(unsigned VReg, LLT Ty);
     730             : 
     731             :   /// Create and return a new generic virtual register with low-level
     732             :   /// type \p Ty.
     733             :   unsigned createGenericVirtualRegister(LLT Ty, StringRef Name = "");
     734             : 
     735             :   /// Remove all types associated to virtual registers (after instruction
     736             :   /// selection and constraining of all generic virtual registers).
     737             :   void clearVirtRegTypes();
     738             : 
     739             :   /// Creates a new virtual register that has no register class, register bank
     740             :   /// or size assigned yet. This is only allowed to be used
     741             :   /// temporarily while constructing machine instructions. Most operations are
     742             :   /// undefined on an incomplete register until one of setRegClass(),
     743             :   /// setRegBank() or setSize() has been called on it.
     744             :   unsigned createIncompleteVirtualRegister(StringRef Name = "");
     745             : 
     746             :   /// getNumVirtRegs - Return the number of virtual registers created.
     747     7242621 :   unsigned getNumVirtRegs() const { return VRegInfo.size(); }
     748             : 
     749             :   /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
     750             :   void clearVirtRegs();
     751             : 
     752             :   /// setRegAllocationHint - Specify a register allocation hint for the
     753             :   /// specified virtual register. This is typically used by target, and in case
     754             :   /// of an earlier hint it will be overwritten.
     755             :   void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
     756             :     assert(TargetRegisterInfo::isVirtualRegister(VReg));
     757       18279 :     RegAllocHints[VReg].first  = Type;
     758             :     RegAllocHints[VReg].second.clear();
     759       18279 :     RegAllocHints[VReg].second.push_back(PrefReg);
     760             :   }
     761             : 
     762             :   /// addRegAllocationHint - Add a register allocation hint to the hints
     763             :   /// vector for VReg.
     764             :   void addRegAllocationHint(unsigned VReg, unsigned PrefReg) {
     765             :     assert(TargetRegisterInfo::isVirtualRegister(VReg));
     766      764100 :     RegAllocHints[VReg].second.push_back(PrefReg);
     767             :   }
     768             : 
     769             :   /// Specify the preferred (target independent) register allocation hint for
     770             :   /// the specified virtual register.
     771          41 :   void setSimpleHint(unsigned VReg, unsigned PrefReg) {
     772             :     setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
     773          41 :   }
     774             : 
     775             :   void clearSimpleHint(unsigned VReg) {
     776             :     assert (RegAllocHints[VReg].first == 0 &&
     777             :             "Expected to clear a non-target hint!");
     778             :     RegAllocHints[VReg].second.clear();
     779             :   }
     780             : 
     781             :   /// getRegAllocationHint - Return the register allocation hint for the
     782             :   /// specified virtual register. If there are many hints, this returns the
     783             :   /// one with the greatest weight.
     784             :   std::pair<unsigned, unsigned>
     785             :   getRegAllocationHint(unsigned VReg) const {
     786             :     assert(TargetRegisterInfo::isVirtualRegister(VReg));
     787     4484594 :     unsigned BestHint = (RegAllocHints[VReg].second.size() ?
     788             :                          RegAllocHints[VReg].second[0] : 0);
     789             :     return std::pair<unsigned, unsigned>(RegAllocHints[VReg].first, BestHint);
     790             :   }
     791             : 
     792             :   /// getSimpleHint - same as getRegAllocationHint except it will only return
     793             :   /// a target independent hint.
     794             :   unsigned getSimpleHint(unsigned VReg) const {
     795             :     assert(TargetRegisterInfo::isVirtualRegister(VReg));
     796             :     std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
     797     1541136 :     return Hint.first ? 0 : Hint.second;
     798             :   }
     799             : 
     800             :   /// getRegAllocationHints - Return a reference to the vector of all
     801             :   /// register allocation hints for VReg.
     802             :   const std::pair<unsigned, SmallVector<unsigned, 4>>
     803             :   &getRegAllocationHints(unsigned VReg) const {
     804             :     assert(TargetRegisterInfo::isVirtualRegister(VReg));
     805             :     return RegAllocHints[VReg];
     806             :   }
     807             : 
     808             :   /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
     809             :   /// specified register as undefined which causes the DBG_VALUE to be
     810             :   /// deleted during LiveDebugVariables analysis.
     811             :   void markUsesInDebugValueAsUndef(unsigned Reg) const;
     812             : 
     813             :   /// Return true if the specified register is modified in this function.
     814             :   /// This checks that no defining machine operands exist for the register or
     815             :   /// any of its aliases. Definitions found on functions marked noreturn are
     816             :   /// ignored, to consider them pass 'true' for optional parameter
     817             :   /// SkipNoReturnDef. The register is also considered modified when it is set
     818             :   /// in the UsedPhysRegMask.
     819             :   bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
     820             : 
     821             :   /// Return true if the specified register is modified or read in this
     822             :   /// function. This checks that no machine operands exist for the register or
     823             :   /// any of its aliases. The register is also considered used when it is set
     824             :   /// in the UsedPhysRegMask.
     825             :   bool isPhysRegUsed(unsigned PhysReg) const;
     826             : 
     827             :   /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
     828             :   /// This corresponds to the bit mask attached to register mask operands.
     829             :   void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
     830      240817 :     UsedPhysRegMask.setBitsNotInMask(RegMask);
     831             :   }
     832             : 
     833             :   const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
     834             : 
     835             :   //===--------------------------------------------------------------------===//
     836             :   // Reserved Register Info
     837             :   //===--------------------------------------------------------------------===//
     838             :   //
     839             :   // The set of reserved registers must be invariant during register
     840             :   // allocation.  For example, the target cannot suddenly decide it needs a
     841             :   // frame pointer when the register allocator has already used the frame
     842             :   // pointer register for something else.
     843             :   //
     844             :   // These methods can be used by target hooks like hasFP() to avoid changing
     845             :   // the reserved register set during register allocation.
     846             : 
     847             :   /// freezeReservedRegs - Called by the register allocator to freeze the set
     848             :   /// of reserved registers before allocation begins.
     849             :   void freezeReservedRegs(const MachineFunction&);
     850             : 
     851             :   /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
     852             :   /// to ensure the set of reserved registers stays constant.
     853             :   bool reservedRegsFrozen() const {
     854     1654859 :     return !ReservedRegs.empty();
     855             :   }
     856             : 
     857             :   /// canReserveReg - Returns true if PhysReg can be used as a reserved
     858             :   /// register.  Any register can be reserved before freezeReservedRegs() is
     859             :   /// called.
     860             :   bool canReserveReg(unsigned PhysReg) const {
     861      310355 :     return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
     862             :   }
     863             : 
     864             :   /// getReservedRegs - Returns a reference to the frozen set of reserved
     865             :   /// registers. This method should always be preferred to calling
     866             :   /// TRI::getReservedRegs() when possible.
     867             :   const BitVector &getReservedRegs() const {
     868             :     assert(reservedRegsFrozen() &&
     869             :            "Reserved registers haven't been frozen yet. "
     870             :            "Use TRI::getReservedRegs().");
     871     3300329 :     return ReservedRegs;
     872             :   }
     873             : 
     874             :   /// isReserved - Returns true when PhysReg is a reserved register.
     875             :   ///
     876             :   /// Reserved registers may belong to an allocatable register class, but the
     877             :   /// target has explicitly requested that they are not used.
     878             :   bool isReserved(unsigned PhysReg) const {
     879             :     return getReservedRegs().test(PhysReg);
     880             :   }
     881             : 
     882             :   /// Returns true when the given register unit is considered reserved.
     883             :   ///
     884             :   /// Register units are considered reserved when for at least one of their
     885             :   /// root registers, the root register and all super registers are reserved.
     886             :   /// This currently iterates the register hierarchy and may be slower than
     887             :   /// expected.
     888             :   bool isReservedRegUnit(unsigned Unit) const;
     889             : 
     890             :   /// isAllocatable - Returns true when PhysReg belongs to an allocatable
     891             :   /// register class and it hasn't been reserved.
     892             :   ///
     893             :   /// Allocatable registers may show up in the allocation order of some virtual
     894             :   /// register, so a register allocator needs to track its liveness and
     895             :   /// availability.
     896    20786840 :   bool isAllocatable(unsigned PhysReg) const {
     897    78329819 :     return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
     898    20786840 :       !isReserved(PhysReg);
     899             :   }
     900             : 
     901             :   //===--------------------------------------------------------------------===//
     902             :   // LiveIn Management
     903             :   //===--------------------------------------------------------------------===//
     904             : 
     905             :   /// addLiveIn - Add the specified register as a live-in.  Note that it
     906             :   /// is an error to add the same register to the same set more than once.
     907             :   void addLiveIn(unsigned Reg, unsigned vreg = 0) {
     908      858932 :     LiveIns.push_back(std::make_pair(Reg, vreg));
     909             :   }
     910             : 
     911             :   // Iteration support for the live-ins set.  It's kept in sorted order
     912             :   // by register number.
     913             :   using livein_iterator =
     914             :       std::vector<std::pair<unsigned,unsigned>>::const_iterator;
     915      968149 :   livein_iterator livein_begin() const { return LiveIns.begin(); }
     916      968149 :   livein_iterator livein_end()   const { return LiveIns.end(); }
     917             :   bool            livein_empty() const { return LiveIns.empty(); }
     918             : 
     919             :   ArrayRef<std::pair<unsigned, unsigned>> liveins() const {
     920             :     return LiveIns;
     921             :   }
     922             : 
     923             :   bool isLiveIn(unsigned Reg) const;
     924             : 
     925             :   /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
     926             :   /// corresponding live-in physical register.
     927             :   unsigned getLiveInPhysReg(unsigned VReg) const;
     928             : 
     929             :   /// getLiveInVirtReg - If PReg is a live-in physical register, return the
     930             :   /// corresponding live-in physical register.
     931             :   unsigned getLiveInVirtReg(unsigned PReg) const;
     932             : 
     933             :   /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
     934             :   /// into the given entry block.
     935             :   void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
     936             :                         const TargetRegisterInfo &TRI,
     937             :                         const TargetInstrInfo &TII);
     938             : 
     939             :   /// Returns a mask covering all bits that can appear in lane masks of
     940             :   /// subregisters of the virtual register @p Reg.
     941             :   LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
     942             : 
     943             :   /// defusechain_iterator - This class provides iterator support for machine
     944             :   /// operands in the function that use or define a specific register.  If
     945             :   /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
     946             :   /// returns defs.  If neither are true then you are silly and it always
     947             :   /// returns end().  If SkipDebug is true it skips uses marked Debug
     948             :   /// when incrementing.
     949             :   template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
     950             :            bool ByOperand, bool ByInstr, bool ByBundle>
     951             :   class defusechain_iterator
     952             :     : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
     953             :     friend class MachineRegisterInfo;
     954             : 
     955             :     MachineOperand *Op = nullptr;
     956             : 
     957    13928301 :     explicit defusechain_iterator(MachineOperand *op) : Op(op) {
     958             :       // If the first node isn't one we're interested in, advance to one that
     959             :       // we are interested in.
     960   346050788 :       if (op) {
     961    42725898 :         if ((!ReturnUses && op->isUse()) ||
     962    13404393 :             (!ReturnDefs && op->isDef()) ||
     963             :             (SkipDebug && op->isDebug()))
     964             :           advance();
     965             :       }
     966    13928301 :     }
     967             : 
     968             :     void advance() {
     969             :       assert(Op && "Cannot increment end iterator!");
     970    65447928 :       Op = getNextOperandForReg(Op);
     971             : 
     972             :       // All defs come before the uses, so stop def_iterator early.
     973             :       if (!ReturnUses) {
     974    16247522 :         if (Op) {
     975    15252964 :           if (Op->isUse())
     976             :             Op = nullptr;
     977             :           else
     978             :             assert(!Op->isDebug() && "Can't have debug defs");
     979             :         }
     980             :       } else {
     981             :         // If this is an operand we don't care about, skip it.
     982    85680714 :         while (Op && ((!ReturnDefs && Op->isDef()) ||
     983             :                       (SkipDebug && Op->isDebug())))
     984     1832257 :           Op = getNextOperandForReg(Op);
     985             :       }
     986             :     }
     987             : 
     988             :   public:
     989             :     using reference = std::iterator<std::forward_iterator_tag,
     990             :                                     MachineInstr, ptrdiff_t>::reference;
     991             :     using pointer = std::iterator<std::forward_iterator_tag,
     992             :                                   MachineInstr, ptrdiff_t>::pointer;
     993             : 
     994             :     defusechain_iterator() = default;
     995             : 
     996             :     bool operator==(const defusechain_iterator &x) const {
     997   283760494 :       return Op == x.Op;
     998             :     }
     999             :     bool operator!=(const defusechain_iterator &x) const {
    1000        8759 :       return !operator==(x);
    1001             :     }
    1002             : 
    1003             :     /// atEnd - return true if this iterator is equal to reg_end() on the value.
    1004             :     bool atEnd() const { return Op == nullptr; }
    1005             : 
    1006             :     // Iterator traversal: forward iteration only
    1007             :     defusechain_iterator &operator++() {          // Preincrement
    1008             :       assert(Op && "Cannot increment end iterator!");
    1009             :       if (ByOperand)
    1010             :         advance();
    1011             :       else if (ByInstr) {
    1012             :         MachineInstr *P = Op->getParent();
    1013             :         do {
    1014             :           advance();
    1015             :         } while (Op && Op->getParent() == P);
    1016             :       } else if (ByBundle) {
    1017             :         MachineBasicBlock::instr_iterator P =
    1018             :             getBundleStart(Op->getParent()->getIterator());
    1019             :         do {
    1020             :           advance();
    1021             :         } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
    1022             :       }
    1023             : 
    1024             :       return *this;
    1025             :     }
    1026             :     defusechain_iterator operator++(int) {        // Postincrement
    1027             :       defusechain_iterator tmp = *this; ++*this; return tmp;
    1028             :     }
    1029             : 
    1030             :     /// getOperandNo - Return the operand # of this MachineOperand in its
    1031             :     /// MachineInstr.
    1032             :     unsigned getOperandNo() const {
    1033             :       assert(Op && "Cannot dereference end iterator!");
    1034     1945898 :       return Op - &Op->getParent()->getOperand(0);
    1035             :     }
    1036             : 
    1037             :     // Retrieve a reference to the current operand.
    1038             :     MachineOperand &operator*() const {
    1039             :       assert(Op && "Cannot dereference end iterator!");
    1040      789504 :       return *Op;
    1041             :     }
    1042             : 
    1043             :     MachineOperand *operator->() const {
    1044             :       assert(Op && "Cannot dereference end iterator!");
    1045         116 :       return Op;
    1046             :     }
    1047             :   };
    1048             : 
    1049             :   /// defusechain_iterator - This class provides iterator support for machine
    1050             :   /// operands in the function that use or define a specific register.  If
    1051             :   /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
    1052             :   /// returns defs.  If neither are true then you are silly and it always
    1053             :   /// returns end().  If SkipDebug is true it skips uses marked Debug
    1054             :   /// when incrementing.
    1055             :   template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
    1056             :            bool ByOperand, bool ByInstr, bool ByBundle>
    1057             :   class defusechain_instr_iterator
    1058             :     : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
    1059             :     friend class MachineRegisterInfo;
    1060             : 
    1061             :     MachineOperand *Op = nullptr;
    1062             : 
    1063     1978680 :     explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
    1064             :       // If the first node isn't one we're interested in, advance to one that
    1065             :       // we are interested in.
    1066     9973650 :       if (op) {
    1067     7966308 :         if ((!ReturnUses && op->isUse()) ||
    1068     1978680 :             (!ReturnDefs && op->isDef()) ||
    1069             :             (SkipDebug && op->isDebug()))
    1070             :           advance();
    1071             :       }
    1072     1978680 :     }
    1073             : 
    1074             :     void advance() {
    1075             :       assert(Op && "Cannot increment end iterator!");
    1076    12485136 :       Op = getNextOperandForReg(Op);
    1077             : 
    1078             :       // All defs come before the uses, so stop def_iterator early.
    1079             :       if (!ReturnUses) {
    1080      570482 :         if (Op) {
    1081      561560 :           if (Op->isUse())
    1082      438894 :             Op = nullptr;
    1083             :           else
    1084             :             assert(!Op->isDebug() && "Can't have debug defs");
    1085             :         }
    1086             :       } else {
    1087             :         // If this is an operand we don't care about, skip it.
    1088    10992352 :         while (Op && ((!ReturnDefs && Op->isDef()) ||
    1089             :                       (SkipDebug && Op->isDebug())))
    1090       84249 :           Op = getNextOperandForReg(Op);
    1091             :       }
    1092             :     }
    1093             : 
    1094             :   public:
    1095             :     using reference = std::iterator<std::forward_iterator_tag,
    1096             :                                     MachineInstr, ptrdiff_t>::reference;
    1097             :     using pointer = std::iterator<std::forward_iterator_tag,
    1098             :                                   MachineInstr, ptrdiff_t>::pointer;
    1099             : 
    1100             :     defusechain_instr_iterator() = default;
    1101             : 
    1102             :     bool operator==(const defusechain_instr_iterator &x) const {
    1103     4467201 :       return Op == x.Op;
    1104             :     }
    1105             :     bool operator!=(const defusechain_instr_iterator &x) const {
    1106             :       return !operator==(x);
    1107             :     }
    1108             : 
    1109             :     /// atEnd - return true if this iterator is equal to reg_end() on the value.
    1110             :     bool atEnd() const { return Op == nullptr; }
    1111             : 
    1112             :     // Iterator traversal: forward iteration only
    1113     3462128 :     defusechain_instr_iterator &operator++() {          // Preincrement
    1114             :       assert(Op && "Cannot increment end iterator!");
    1115             :       if (ByOperand)
    1116             :         advance();
    1117             :       else if (ByInstr) {
    1118     9829680 :         MachineInstr *P = Op->getParent();
    1119             :         do {
    1120             :           advance();
    1121    10067673 :         } while (Op && Op->getParent() == P);
    1122             :       } else if (ByBundle) {
    1123             :         MachineBasicBlock::instr_iterator P =
    1124      105695 :             getBundleStart(Op->getParent()->getIterator());
    1125             :         do {
    1126             :           advance();
    1127      177688 :         } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
    1128             :       }
    1129             : 
    1130     3462128 :       return *this;
    1131             :     }
    1132             :     defusechain_instr_iterator operator++(int) {        // Postincrement
    1133      202140 :       defusechain_instr_iterator tmp = *this; ++*this; return tmp;
    1134             :     }
    1135             : 
    1136             :     // Retrieve a reference to the current operand.
    1137             :     MachineInstr &operator*() const {
    1138             :       assert(Op && "Cannot dereference end iterator!");
    1139             :       if (ByBundle)
    1140      105695 :         return *getBundleStart(Op->getParent()->getIterator());
    1141    12776783 :       return *Op->getParent();
    1142             :     }
    1143             : 
    1144             :     MachineInstr *operator->() const { return &operator*(); }
    1145             :   };
    1146             : };
    1147             : 
    1148             : /// Iterate over the pressure sets affected by the given physical or virtual
    1149             : /// register. If Reg is physical, it must be a register unit (from
    1150             : /// MCRegUnitIterator).
    1151             : class PSetIterator {
    1152             :   const int *PSet = nullptr;
    1153             :   unsigned Weight = 0;
    1154             : 
    1155             : public:
    1156             :   PSetIterator() = default;
    1157             : 
    1158    14014497 :   PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
    1159    14014497 :     const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
    1160    14014497 :     if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
    1161             :       const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
    1162    12212486 :       PSet = TRI->getRegClassPressureSets(RC);
    1163    12212486 :       Weight = TRI->getRegClassWeight(RC).RegWeight;
    1164             :     }
    1165             :     else {
    1166     1802011 :       PSet = TRI->getRegUnitPressureSets(RegUnit);
    1167     1802011 :       Weight = TRI->getRegUnitWeight(RegUnit);
    1168             :     }
    1169    14014497 :     if (*PSet == -1)
    1170      270038 :       PSet = nullptr;
    1171    14014497 :   }
    1172             : 
    1173             :   bool isValid() const { return PSet; }
    1174             : 
    1175             :   unsigned getWeight() const { return Weight; }
    1176             : 
    1177    74873275 :   unsigned operator*() const { return *PSet; }
    1178             : 
    1179             :   void operator++() {
    1180             :     assert(isValid() && "Invalid PSetIterator.");
    1181    32413151 :     ++PSet;
    1182    32413151 :     if (*PSet == -1)
    1183             :       PSet = nullptr;
    1184             :   }
    1185             : };
    1186             : 
    1187             : inline PSetIterator MachineRegisterInfo::
    1188             : getPressureSets(unsigned RegUnit) const {
    1189    14014497 :   return PSetIterator(RegUnit, this);
    1190             : }
    1191             : 
    1192             : } // end namespace llvm
    1193             : 
    1194             : #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H

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