LCOV - code coverage report
Current view: top level - include/llvm/CodeGen - TargetInstrInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 99 201 49.3 %
Date: 2018-02-23 05:02:05 Functions: 42 95 44.2 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file describes the target machine instruction set to the code generator.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_TARGET_TARGETINSTRINFO_H
      15             : #define LLVM_TARGET_TARGETINSTRINFO_H
      16             : 
      17             : #include "llvm/ADT/ArrayRef.h"
      18             : #include "llvm/ADT/DenseMap.h"
      19             : #include "llvm/ADT/DenseMapInfo.h"
      20             : #include "llvm/ADT/None.h"
      21             : #include "llvm/CodeGen/MachineBasicBlock.h"
      22             : #include "llvm/CodeGen/MachineCombinerPattern.h"
      23             : #include "llvm/CodeGen/MachineFunction.h"
      24             : #include "llvm/CodeGen/MachineInstr.h"
      25             : #include "llvm/CodeGen/MachineLoopInfo.h"
      26             : #include "llvm/CodeGen/MachineOperand.h"
      27             : #include "llvm/CodeGen/PseudoSourceValue.h"
      28             : #include "llvm/MC/MCInstrInfo.h"
      29             : #include "llvm/Support/BranchProbability.h"
      30             : #include "llvm/Support/ErrorHandling.h"
      31             : #include <cassert>
      32             : #include <cstddef>
      33             : #include <cstdint>
      34             : #include <utility>
      35             : #include <vector>
      36             : 
      37             : namespace llvm {
      38             : 
      39             : class DFAPacketizer;
      40             : class InstrItineraryData;
      41             : class LiveIntervals;
      42             : class LiveVariables;
      43             : class MachineMemOperand;
      44             : class MachineRegisterInfo;
      45             : class MCAsmInfo;
      46             : class MCInst;
      47             : struct MCSchedModel;
      48             : class Module;
      49             : class ScheduleDAG;
      50             : class ScheduleHazardRecognizer;
      51             : class SDNode;
      52             : class SelectionDAG;
      53             : class RegScavenger;
      54             : class TargetRegisterClass;
      55             : class TargetRegisterInfo;
      56             : class TargetSchedModel;
      57             : class TargetSubtargetInfo;
      58             : 
      59             : template <class T> class SmallVectorImpl;
      60             : 
      61             : //---------------------------------------------------------------------------
      62             : ///
      63             : /// TargetInstrInfo - Interface to description of machine instruction set
      64             : ///
      65             : class TargetInstrInfo : public MCInstrInfo {
      66             : public:
      67             :   TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
      68             :                   unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
      69       31127 :       : CallFrameSetupOpcode(CFSetupOpcode),
      70             :         CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
      71       31127 :         ReturnOpcode(ReturnOpcode) {}
      72             :   TargetInstrInfo(const TargetInstrInfo &) = delete;
      73             :   TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
      74             :   virtual ~TargetInstrInfo();
      75             : 
      76             :   static bool isGenericOpcode(unsigned Opc) {
      77             :     return Opc <= TargetOpcode::GENERIC_OP_END;
      78             :   }
      79             : 
      80             :   /// Given a machine instruction descriptor, returns the register
      81             :   /// class constraint for OpNum, or NULL.
      82             :   const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
      83             :                                          const TargetRegisterInfo *TRI,
      84             :                                          const MachineFunction &MF) const;
      85             : 
      86             :   /// Return true if the instruction is trivially rematerializable, meaning it
      87             :   /// has no side effects and requires no operands that aren't always available.
      88             :   /// This means the only allowed uses are constants and unallocatable physical
      89             :   /// registers so that the instructions result is independent of the place
      90             :   /// in the function.
      91      916822 :   bool isTriviallyReMaterializable(const MachineInstr &MI,
      92             :                                    AliasAnalysis *AA = nullptr) const {
      93     2750219 :     return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
      94     1496843 :            (MI.getDesc().isRematerializable() &&
      95      915233 :             (isReallyTriviallyReMaterializable(MI, AA) ||
      96     1251787 :              isReallyTriviallyReMaterializableGeneric(MI, AA)));
      97             :   }
      98             : 
      99             : protected:
     100             :   /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
     101             :   /// set, this hook lets the target specify whether the instruction is actually
     102             :   /// trivially rematerializable, taking into consideration its operands. This
     103             :   /// predicate must return false if the instruction has any side effects other
     104             :   /// than producing a value, or if it requres any address registers that are
     105             :   /// not always available.
     106             :   /// Requirements must be check as stated in isTriviallyReMaterializable() .
     107       33989 :   virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
     108             :                                                  AliasAnalysis *AA) const {
     109       33989 :     return false;
     110             :   }
     111             : 
     112             :   /// This method commutes the operands of the given machine instruction MI.
     113             :   /// The operands to be commuted are specified by their indices OpIdx1 and
     114             :   /// OpIdx2.
     115             :   ///
     116             :   /// If a target has any instructions that are commutable but require
     117             :   /// converting to different instructions or making non-trivial changes
     118             :   /// to commute them, this method can be overloaded to do that.
     119             :   /// The default implementation simply swaps the commutable operands.
     120             :   ///
     121             :   /// If NewMI is false, MI is modified in place and returned; otherwise, a
     122             :   /// new machine instruction is created and returned.
     123             :   ///
     124             :   /// Do not call this method for a non-commutable instruction.
     125             :   /// Even though the instruction is commutable, the method may still
     126             :   /// fail to commute the operands, null pointer is returned in such cases.
     127             :   virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
     128             :                                                unsigned OpIdx1,
     129             :                                                unsigned OpIdx2) const;
     130             : 
     131             :   /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
     132             :   /// operand indices to (ResultIdx1, ResultIdx2).
     133             :   /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
     134             :   /// predefined to some indices or be undefined (designated by the special
     135             :   /// value 'CommuteAnyOperandIndex').
     136             :   /// The predefined result indices cannot be re-defined.
     137             :   /// The function returns true iff after the result pair redefinition
     138             :   /// the fixed result pair is equal to or equivalent to the source pair of
     139             :   /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
     140             :   /// the pairs (x,y) and (y,x) are equivalent.
     141             :   static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
     142             :                                    unsigned CommutableOpIdx1,
     143             :                                    unsigned CommutableOpIdx2);
     144             : 
     145             : private:
     146             :   /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
     147             :   /// set and the target hook isReallyTriviallyReMaterializable returns false,
     148             :   /// this function does target-independent tests to determine if the
     149             :   /// instruction is really trivially rematerializable.
     150             :   bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
     151             :                                                 AliasAnalysis *AA) const;
     152             : 
     153             : public:
     154             :   /// These methods return the opcode of the frame setup/destroy instructions
     155             :   /// if they exist (-1 otherwise).  Some targets use pseudo instructions in
     156             :   /// order to abstract away the difference between operating with a frame
     157             :   /// pointer and operating without, through the use of these two instructions.
     158             :   ///
     159             :   unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
     160             :   unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
     161             : 
     162             :   /// Returns true if the argument is a frame pseudo instruction.
     163             :   bool isFrameInstr(const MachineInstr &I) const {
     164    17976955 :     return I.getOpcode() == getCallFrameSetupOpcode() ||
     165     5817345 :            I.getOpcode() == getCallFrameDestroyOpcode();
     166             :   }
     167             : 
     168             :   /// Returns true if the argument is a frame setup pseudo instruction.
     169             :   bool isFrameSetup(const MachineInstr &I) const {
     170      840217 :     return I.getOpcode() == getCallFrameSetupOpcode();
     171             :   }
     172             : 
     173             :   /// Returns size of the frame associated with the given frame instruction.
     174             :   /// For frame setup instruction this is frame that is set up space set up
     175             :   /// after the instruction. For frame destroy instruction this is the frame
     176             :   /// freed by the caller.
     177             :   /// Note, in some cases a call frame (or a part of it) may be prepared prior
     178             :   /// to the frame setup instruction. It occurs in the calls that involve
     179             :   /// inalloca arguments. This function reports only the size of the frame part
     180             :   /// that is set up between the frame setup and destroy pseudo instructions.
     181             :   int64_t getFrameSize(const MachineInstr &I) const {
     182             :     assert(isFrameInstr(I) && "Not a frame instruction");
     183             :     assert(I.getOperand(0).getImm() >= 0);
     184      923322 :     return I.getOperand(0).getImm();
     185             :   }
     186             : 
     187             :   /// Returns the total frame size, which is made up of the space set up inside
     188             :   /// the pair of frame start-stop instructions and the space that is set up
     189             :   /// prior to the pair.
     190             :   int64_t getFrameTotalSize(const MachineInstr &I) const {
     191      205186 :     if (isFrameSetup(I)) {
     192             :       assert(I.getOperand(1).getImm() >= 0 &&
     193             :              "Frame size must not be negative");
     194      102593 :       return getFrameSize(I) + I.getOperand(1).getImm();
     195             :     }
     196             :     return getFrameSize(I);
     197             :   }
     198             : 
     199             :   unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
     200             :   unsigned getReturnOpcode() const { return ReturnOpcode; }
     201             : 
     202             :   /// Returns the actual stack pointer adjustment made by an instruction
     203             :   /// as part of a call sequence. By default, only call frame setup/destroy
     204             :   /// instructions adjust the stack, but targets may want to override this
     205             :   /// to enable more fine-grained adjustment, or adjust by a different value.
     206             :   virtual int getSPAdjust(const MachineInstr &MI) const;
     207             : 
     208             :   /// Return true if the instruction is a "coalescable" extension instruction.
     209             :   /// That is, it's like a copy where it's legal for the source to overlap the
     210             :   /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
     211             :   /// expected the pre-extension value is available as a subreg of the result
     212             :   /// register. This also returns the sub-register index in SubIdx.
     213      875524 :   virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
     214             :                                      unsigned &DstReg, unsigned &SubIdx) const {
     215      875524 :     return false;
     216             :   }
     217             : 
     218             :   /// If the specified machine instruction is a direct
     219             :   /// load from a stack slot, return the virtual or physical register number of
     220             :   /// the destination along with the FrameIndex of the loaded stack slot.  If
     221             :   /// not, return 0.  This predicate must return 0 if the instruction has
     222             :   /// any side effects other than loading from the stack slot.
     223        1710 :   virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
     224             :                                        int &FrameIndex) const {
     225        1710 :     return 0;
     226             :   }
     227             : 
     228             :   /// Check for post-frame ptr elimination stack locations as well.
     229             :   /// This uses a heuristic so it isn't reliable for correctness.
     230      739099 :   virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
     231             :                                              int &FrameIndex) const {
     232      739099 :     return 0;
     233             :   }
     234             : 
     235             :   /// If the specified machine instruction has a load from a stack slot,
     236             :   /// return true along with the FrameIndex of the loaded stack slot and the
     237             :   /// machine mem operand containing the reference.
     238             :   /// If not, return false.  Unlike isLoadFromStackSlot, this returns true for
     239             :   /// any instructions that loads from the stack.  This is just a hint, as some
     240             :   /// cases may be missed.
     241             :   virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
     242             :                                     const MachineMemOperand *&MMO,
     243             :                                     int &FrameIndex) const;
     244             : 
     245             :   /// If the specified machine instruction is a direct
     246             :   /// store to a stack slot, return the virtual or physical register number of
     247             :   /// the source reg along with the FrameIndex of the loaded stack slot.  If
     248             :   /// not, return 0.  This predicate must return 0 if the instruction has
     249             :   /// any side effects other than storing to the stack slot.
     250        1036 :   virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
     251             :                                       int &FrameIndex) const {
     252        1036 :     return 0;
     253             :   }
     254             : 
     255             :   /// Check for post-frame ptr elimination stack locations as well.
     256             :   /// This uses a heuristic, so it isn't reliable for correctness.
     257      720112 :   virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
     258             :                                             int &FrameIndex) const {
     259      720112 :     return 0;
     260             :   }
     261             : 
     262             :   /// If the specified machine instruction has a store to a stack slot,
     263             :   /// return true along with the FrameIndex of the loaded stack slot and the
     264             :   /// machine mem operand containing the reference.
     265             :   /// If not, return false.  Unlike isStoreToStackSlot,
     266             :   /// this returns true for any instructions that stores to the
     267             :   /// stack.  This is just a hint, as some cases may be missed.
     268             :   virtual bool hasStoreToStackSlot(const MachineInstr &MI,
     269             :                                    const MachineMemOperand *&MMO,
     270             :                                    int &FrameIndex) const;
     271             : 
     272             :   /// Return true if the specified machine instruction
     273             :   /// is a copy of one stack slot to another and has no other effect.
     274             :   /// Provide the identity of the two frame indices.
     275      810102 :   virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
     276             :                                int &SrcFrameIndex) const {
     277      810102 :     return false;
     278             :   }
     279             : 
     280             :   /// Compute the size in bytes and offset within a stack slot of a spilled
     281             :   /// register or subregister.
     282             :   ///
     283             :   /// \param [out] Size in bytes of the spilled value.
     284             :   /// \param [out] Offset in bytes within the stack slot.
     285             :   /// \returns true if both Size and Offset are successfully computed.
     286             :   ///
     287             :   /// Not all subregisters have computable spill slots. For example,
     288             :   /// subregisters registers may not be byte-sized, and a pair of discontiguous
     289             :   /// subregisters has no single offset.
     290             :   ///
     291             :   /// Targets with nontrivial bigendian implementations may need to override
     292             :   /// this, particularly to support spilled vector registers.
     293             :   virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
     294             :                                  unsigned &Size, unsigned &Offset,
     295             :                                  const MachineFunction &MF) const;
     296             : 
     297             :   /// Returns the size in bytes of the specified MachineInstr, or ~0U
     298             :   /// when this function is not implemented by a target.
     299           0 :   virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
     300           0 :     return ~0U;
     301             :   }
     302             : 
     303             :   /// Return true if the instruction is as cheap as a move instruction.
     304             :   ///
     305             :   /// Targets for different archs need to override this, and different
     306             :   /// micro-architectures can also be finely tuned inside.
     307      702358 :   virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
     308      702358 :     return MI.isAsCheapAsAMove();
     309             :   }
     310             : 
     311             :   /// Return true if the instruction should be sunk by MachineSink.
     312             :   ///
     313             :   /// MachineSink determines on its own whether the instruction is safe to sink;
     314             :   /// this gives the target a hook to override the default behavior with regards
     315             :   /// to which instructions should be sunk.
     316     2765303 :   virtual bool shouldSink(const MachineInstr &MI) const { return true; }
     317             : 
     318             :   /// Re-issue the specified 'original' instruction at the
     319             :   /// specific location targeting a new destination register.
     320             :   /// The register in Orig->getOperand(0).getReg() will be substituted by
     321             :   /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
     322             :   /// SubIdx.
     323             :   virtual void reMaterialize(MachineBasicBlock &MBB,
     324             :                              MachineBasicBlock::iterator MI, unsigned DestReg,
     325             :                              unsigned SubIdx, const MachineInstr &Orig,
     326             :                              const TargetRegisterInfo &TRI) const;
     327             : 
     328             :   /// \brief Clones instruction or the whole instruction bundle \p Orig and
     329             :   /// insert into \p MBB before \p InsertBefore. The target may update operands
     330             :   /// that are required to be unique.
     331             :   ///
     332             :   /// \p Orig must not return true for MachineInstr::isNotDuplicable().
     333             :   virtual MachineInstr &duplicate(MachineBasicBlock &MBB,
     334             :                                   MachineBasicBlock::iterator InsertBefore,
     335             :                                   const MachineInstr &Orig) const;
     336             : 
     337             :   /// This method must be implemented by targets that
     338             :   /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
     339             :   /// may be able to convert a two-address instruction into one or more true
     340             :   /// three-address instructions on demand.  This allows the X86 target (for
     341             :   /// example) to convert ADD and SHL instructions into LEA instructions if they
     342             :   /// would require register copies due to two-addressness.
     343             :   ///
     344             :   /// This method returns a null pointer if the transformation cannot be
     345             :   /// performed, otherwise it returns the last new instruction.
     346             :   ///
     347           0 :   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
     348             :                                               MachineInstr &MI,
     349             :                                               LiveVariables *LV) const {
     350           0 :     return nullptr;
     351             :   }
     352             : 
     353             :   // This constant can be used as an input value of operand index passed to
     354             :   // the method findCommutedOpIndices() to tell the method that the
     355             :   // corresponding operand index is not pre-defined and that the method
     356             :   // can pick any commutable operand.
     357             :   static const unsigned CommuteAnyOperandIndex = ~0U;
     358             : 
     359             :   /// This method commutes the operands of the given machine instruction MI.
     360             :   ///
     361             :   /// The operands to be commuted are specified by their indices OpIdx1 and
     362             :   /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
     363             :   /// 'CommuteAnyOperandIndex', which means that the method is free to choose
     364             :   /// any arbitrarily chosen commutable operand. If both arguments are set to
     365             :   /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
     366             :   /// operands; then commutes them if such operands could be found.
     367             :   ///
     368             :   /// If NewMI is false, MI is modified in place and returned; otherwise, a
     369             :   /// new machine instruction is created and returned.
     370             :   ///
     371             :   /// Do not call this method for a non-commutable instruction or
     372             :   /// for non-commuable operands.
     373             :   /// Even though the instruction is commutable, the method may still
     374             :   /// fail to commute the operands, null pointer is returned in such cases.
     375             :   MachineInstr *
     376             :   commuteInstruction(MachineInstr &MI, bool NewMI = false,
     377             :                      unsigned OpIdx1 = CommuteAnyOperandIndex,
     378             :                      unsigned OpIdx2 = CommuteAnyOperandIndex) const;
     379             : 
     380             :   /// Returns true iff the routine could find two commutable operands in the
     381             :   /// given machine instruction.
     382             :   /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
     383             :   /// If any of the INPUT values is set to the special value
     384             :   /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
     385             :   /// operand, then returns its index in the corresponding argument.
     386             :   /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
     387             :   /// looks for 2 commutable operands.
     388             :   /// If INPUT values refer to some operands of MI, then the method simply
     389             :   /// returns true if the corresponding operands are commutable and returns
     390             :   /// false otherwise.
     391             :   ///
     392             :   /// For example, calling this method this way:
     393             :   ///     unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
     394             :   ///     findCommutedOpIndices(MI, Op1, Op2);
     395             :   /// can be interpreted as a query asking to find an operand that would be
     396             :   /// commutable with the operand#1.
     397             :   virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
     398             :                                      unsigned &SrcOpIdx2) const;
     399             : 
     400             :   /// A pair composed of a register and a sub-register index.
     401             :   /// Used to give some type checking when modeling Reg:SubReg.
     402             :   struct RegSubRegPair {
     403             :     unsigned Reg;
     404             :     unsigned SubReg;
     405             : 
     406             :     RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
     407     2264681 :         : Reg(Reg), SubReg(SubReg) {}
     408             :   };
     409             : 
     410             :   /// A pair composed of a pair of a register and a sub-register index,
     411             :   /// and another sub-register index.
     412             :   /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
     413             :   struct RegSubRegPairAndIdx : RegSubRegPair {
     414             :     unsigned SubIdx;
     415             : 
     416             :     RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
     417             :                         unsigned SubIdx = 0)
     418     1114658 :         : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
     419             :   };
     420             : 
     421             :   /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
     422             :   /// and \p DefIdx.
     423             :   /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
     424             :   /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
     425             :   /// flag are not added to this list.
     426             :   /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
     427             :   /// two elements:
     428             :   /// - %1:sub1, sub0
     429             :   /// - %2<:0>, sub1
     430             :   ///
     431             :   /// \returns true if it is possible to build such an input sequence
     432             :   /// with the pair \p MI, \p DefIdx. False otherwise.
     433             :   ///
     434             :   /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
     435             :   ///
     436             :   /// \note The generic implementation does not provide any support for
     437             :   /// MI.isRegSequenceLike(). In other words, one has to override
     438             :   /// getRegSequenceLikeInputs for target specific instructions.
     439             :   bool
     440             :   getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
     441             :                        SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
     442             : 
     443             :   /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
     444             :   /// and \p DefIdx.
     445             :   /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
     446             :   /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
     447             :   /// - %1:sub1, sub0
     448             :   ///
     449             :   /// \returns true if it is possible to build such an input sequence
     450             :   /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
     451             :   /// False otherwise.
     452             :   ///
     453             :   /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
     454             :   ///
     455             :   /// \note The generic implementation does not provide any support for
     456             :   /// MI.isExtractSubregLike(). In other words, one has to override
     457             :   /// getExtractSubregLikeInputs for target specific instructions.
     458             :   bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
     459             :                               RegSubRegPairAndIdx &InputReg) const;
     460             : 
     461             :   /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
     462             :   /// and \p DefIdx.
     463             :   /// \p [out] BaseReg and \p [out] InsertedReg contain
     464             :   /// the equivalent inputs of INSERT_SUBREG.
     465             :   /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
     466             :   /// - BaseReg: %0:sub0
     467             :   /// - InsertedReg: %1:sub1, sub3
     468             :   ///
     469             :   /// \returns true if it is possible to build such an input sequence
     470             :   /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
     471             :   /// False otherwise.
     472             :   ///
     473             :   /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
     474             :   ///
     475             :   /// \note The generic implementation does not provide any support for
     476             :   /// MI.isInsertSubregLike(). In other words, one has to override
     477             :   /// getInsertSubregLikeInputs for target specific instructions.
     478             :   bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
     479             :                              RegSubRegPair &BaseReg,
     480             :                              RegSubRegPairAndIdx &InsertedReg) const;
     481             : 
     482             :   /// Return true if two machine instructions would produce identical values.
     483             :   /// By default, this is only true when the two instructions
     484             :   /// are deemed identical except for defs. If this function is called when the
     485             :   /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
     486             :   /// aggressive checks.
     487             :   virtual bool produceSameValue(const MachineInstr &MI0,
     488             :                                 const MachineInstr &MI1,
     489             :                                 const MachineRegisterInfo *MRI = nullptr) const;
     490             : 
     491             :   /// \returns true if a branch from an instruction with opcode \p BranchOpc
     492             :   ///  bytes is capable of jumping to a position \p BrOffset bytes away.
     493           0 :   virtual bool isBranchOffsetInRange(unsigned BranchOpc,
     494             :                                      int64_t BrOffset) const {
     495           0 :     llvm_unreachable("target did not implement");
     496             :   }
     497             : 
     498             :   /// \returns The block that branch instruction \p MI jumps to.
     499           0 :   virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
     500           0 :     llvm_unreachable("target did not implement");
     501             :   }
     502             : 
     503             :   /// Insert an unconditional indirect branch at the end of \p MBB to \p
     504             :   /// NewDestBB.  \p BrOffset indicates the offset of \p NewDestBB relative to
     505             :   /// the offset of the position to insert the new branch.
     506             :   ///
     507             :   /// \returns The number of bytes added to the block.
     508           0 :   virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB,
     509             :                                         MachineBasicBlock &NewDestBB,
     510             :                                         const DebugLoc &DL,
     511             :                                         int64_t BrOffset = 0,
     512             :                                         RegScavenger *RS = nullptr) const {
     513           0 :     llvm_unreachable("target did not implement");
     514             :   }
     515             : 
     516             :   /// Analyze the branching code at the end of MBB, returning
     517             :   /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
     518             :   /// implemented for a target).  Upon success, this returns false and returns
     519             :   /// with the following information in various cases:
     520             :   ///
     521             :   /// 1. If this block ends with no branches (it just falls through to its succ)
     522             :   ///    just return false, leaving TBB/FBB null.
     523             :   /// 2. If this block ends with only an unconditional branch, it sets TBB to be
     524             :   ///    the destination block.
     525             :   /// 3. If this block ends with a conditional branch and it falls through to a
     526             :   ///    successor block, it sets TBB to be the branch destination block and a
     527             :   ///    list of operands that evaluate the condition. These operands can be
     528             :   ///    passed to other TargetInstrInfo methods to create new branches.
     529             :   /// 4. If this block ends with a conditional branch followed by an
     530             :   ///    unconditional branch, it returns the 'true' destination in TBB, the
     531             :   ///    'false' destination in FBB, and a list of operands that evaluate the
     532             :   ///    condition.  These operands can be passed to other TargetInstrInfo
     533             :   ///    methods to create new branches.
     534             :   ///
     535             :   /// Note that removeBranch and insertBranch must be implemented to support
     536             :   /// cases where this method returns success.
     537             :   ///
     538             :   /// If AllowModify is true, then this routine is allowed to modify the basic
     539             :   /// block (e.g. delete instructions after the unconditional branch).
     540             :   ///
     541             :   /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
     542             :   /// before calling this function.
     543           0 :   virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
     544             :                              MachineBasicBlock *&FBB,
     545             :                              SmallVectorImpl<MachineOperand> &Cond,
     546             :                              bool AllowModify = false) const {
     547           0 :     return true;
     548             :   }
     549             : 
     550             :   /// Represents a predicate at the MachineFunction level.  The control flow a
     551             :   /// MachineBranchPredicate represents is:
     552             :   ///
     553             :   ///  Reg = LHS `Predicate` RHS         == ConditionDef
     554             :   ///  if Reg then goto TrueDest else goto FalseDest
     555             :   ///
     556             :   struct MachineBranchPredicate {
     557             :     enum ComparePredicate {
     558             :       PRED_EQ,     // True if two values are equal
     559             :       PRED_NE,     // True if two values are not equal
     560             :       PRED_INVALID // Sentinel value
     561             :     };
     562             : 
     563             :     ComparePredicate Predicate = PRED_INVALID;
     564             :     MachineOperand LHS = MachineOperand::CreateImm(0);
     565             :     MachineOperand RHS = MachineOperand::CreateImm(0);
     566             :     MachineBasicBlock *TrueDest = nullptr;
     567             :     MachineBasicBlock *FalseDest = nullptr;
     568             :     MachineInstr *ConditionDef = nullptr;
     569             : 
     570             :     /// SingleUseCondition is true if ConditionDef is dead except for the
     571             :     /// branch(es) at the end of the basic block.
     572             :     ///
     573             :     bool SingleUseCondition = false;
     574             : 
     575         120 :     explicit MachineBranchPredicate() = default;
     576             :   };
     577             : 
     578             :   /// Analyze the branching code at the end of MBB and parse it into the
     579             :   /// MachineBranchPredicate structure if possible.  Returns false on success
     580             :   /// and true on failure.
     581             :   ///
     582             :   /// If AllowModify is true, then this routine is allowed to modify the basic
     583             :   /// block (e.g. delete instructions after the unconditional branch).
     584             :   ///
     585           0 :   virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
     586             :                                       MachineBranchPredicate &MBP,
     587             :                                       bool AllowModify = false) const {
     588           0 :     return true;
     589             :   }
     590             : 
     591             :   /// Remove the branching code at the end of the specific MBB.
     592             :   /// This is only invoked in cases where AnalyzeBranch returns success. It
     593             :   /// returns the number of instructions that were removed.
     594             :   /// If \p BytesRemoved is non-null, report the change in code size from the
     595             :   /// removed instructions.
     596           0 :   virtual unsigned removeBranch(MachineBasicBlock &MBB,
     597             :                                 int *BytesRemoved = nullptr) const {
     598           0 :     llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
     599             :   }
     600             : 
     601             :   /// Insert branch code into the end of the specified MachineBasicBlock. The
     602             :   /// operands to this method are the same as those returned by AnalyzeBranch.
     603             :   /// This is only invoked in cases where AnalyzeBranch returns success. It
     604             :   /// returns the number of instructions inserted. If \p BytesAdded is non-null,
     605             :   /// report the change in code size from the added instructions.
     606             :   ///
     607             :   /// It is also invoked by tail merging to add unconditional branches in
     608             :   /// cases where AnalyzeBranch doesn't apply because there was no original
     609             :   /// branch to analyze.  At least this much must be implemented, else tail
     610             :   /// merging needs to be disabled.
     611             :   ///
     612             :   /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
     613             :   /// before calling this function.
     614           0 :   virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
     615             :                                 MachineBasicBlock *FBB,
     616             :                                 ArrayRef<MachineOperand> Cond,
     617             :                                 const DebugLoc &DL,
     618             :                                 int *BytesAdded = nullptr) const {
     619           0 :     llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
     620             :   }
     621             : 
     622             :   unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
     623             :                                      MachineBasicBlock *DestBB,
     624             :                                      const DebugLoc &DL,
     625             :                                      int *BytesAdded = nullptr) const {
     626           3 :     return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
     627           3 :                         BytesAdded);
     628             :   }
     629             : 
     630             :   /// Analyze the loop code, return true if it cannot be understoo. Upon
     631             :   /// success, this function returns false and returns information about the
     632             :   /// induction variable and compare instruction used at the end.
     633           0 :   virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
     634             :                            MachineInstr *&CmpInst) const {
     635           0 :     return true;
     636             :   }
     637             : 
     638             :   /// Generate code to reduce the loop iteration by one and check if the loop
     639             :   /// is finished.  Return the value/register of the new loop count.  We need
     640             :   /// this function when peeling off one or more iterations of a loop. This
     641             :   /// function assumes the nth iteration is peeled first.
     642           0 :   virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar,
     643             :                                    MachineInstr &Cmp,
     644             :                                    SmallVectorImpl<MachineOperand> &Cond,
     645             :                                    SmallVectorImpl<MachineInstr *> &PrevInsts,
     646             :                                    unsigned Iter, unsigned MaxIter) const {
     647           0 :     llvm_unreachable("Target didn't implement ReduceLoopCount");
     648             :   }
     649             : 
     650             :   /// Delete the instruction OldInst and everything after it, replacing it with
     651             :   /// an unconditional branch to NewDest. This is used by the tail merging pass.
     652             :   virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
     653             :                                        MachineBasicBlock *NewDest) const;
     654             : 
     655             :   /// Return true if it's legal to split the given basic
     656             :   /// block at the specified instruction (i.e. instruction would be the start
     657             :   /// of a new basic block).
     658        3436 :   virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
     659             :                                    MachineBasicBlock::iterator MBBI) const {
     660        3436 :     return true;
     661             :   }
     662             : 
     663             :   /// Return true if it's profitable to predicate
     664             :   /// instructions with accumulated instruction latency of "NumCycles"
     665             :   /// of the specified basic block, where the probability of the instructions
     666             :   /// being executed is given by Probability, and Confidence is a measure
     667             :   /// of our confidence that it will be properly predicted.
     668           0 :   virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
     669             :                                    unsigned ExtraPredCycles,
     670             :                                    BranchProbability Probability) const {
     671           0 :     return false;
     672             :   }
     673             : 
     674             :   /// Second variant of isProfitableToIfCvt. This one
     675             :   /// checks for the case where two basic blocks from true and false path
     676             :   /// of a if-then-else (diamond) are predicated on mutally exclusive
     677             :   /// predicates, where the probability of the true path being taken is given
     678             :   /// by Probability, and Confidence is a measure of our confidence that it
     679             :   /// will be properly predicted.
     680           0 :   virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
     681             :                                    unsigned ExtraTCycles,
     682             :                                    MachineBasicBlock &FMBB, unsigned NumFCycles,
     683             :                                    unsigned ExtraFCycles,
     684             :                                    BranchProbability Probability) const {
     685           0 :     return false;
     686             :   }
     687             : 
     688             :   /// Return true if it's profitable for if-converter to duplicate instructions
     689             :   /// of specified accumulated instruction latencies in the specified MBB to
     690             :   /// enable if-conversion.
     691             :   /// The probability of the instructions being executed is given by
     692             :   /// Probability, and Confidence is a measure of our confidence that it
     693             :   /// will be properly predicted.
     694           0 :   virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
     695             :                                          unsigned NumCycles,
     696             :                                          BranchProbability Probability) const {
     697           0 :     return false;
     698             :   }
     699             : 
     700             :   /// Return true if it's profitable to unpredicate
     701             :   /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
     702             :   /// exclusive predicates.
     703             :   /// e.g.
     704             :   ///   subeq  r0, r1, #1
     705             :   ///   addne  r0, r1, #1
     706             :   /// =>
     707             :   ///   sub    r0, r1, #1
     708             :   ///   addne  r0, r1, #1
     709             :   ///
     710             :   /// This may be profitable is conditional instructions are always executed.
     711          17 :   virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
     712             :                                          MachineBasicBlock &FMBB) const {
     713          17 :     return false;
     714             :   }
     715             : 
     716             :   /// Return true if it is possible to insert a select
     717             :   /// instruction that chooses between TrueReg and FalseReg based on the
     718             :   /// condition code in Cond.
     719             :   ///
     720             :   /// When successful, also return the latency in cycles from TrueReg,
     721             :   /// FalseReg, and Cond to the destination register. In most cases, a select
     722             :   /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
     723             :   ///
     724             :   /// Some x86 implementations have 2-cycle cmov instructions.
     725             :   ///
     726             :   /// @param MBB         Block where select instruction would be inserted.
     727             :   /// @param Cond        Condition returned by AnalyzeBranch.
     728             :   /// @param TrueReg     Virtual register to select when Cond is true.
     729             :   /// @param FalseReg    Virtual register to select when Cond is false.
     730             :   /// @param CondCycles  Latency from Cond+Branch to select output.
     731             :   /// @param TrueCycles  Latency from TrueReg to select output.
     732             :   /// @param FalseCycles Latency from FalseReg to select output.
     733           0 :   virtual bool canInsertSelect(const MachineBasicBlock &MBB,
     734             :                                ArrayRef<MachineOperand> Cond, unsigned TrueReg,
     735             :                                unsigned FalseReg, int &CondCycles,
     736             :                                int &TrueCycles, int &FalseCycles) const {
     737           0 :     return false;
     738             :   }
     739             : 
     740             :   /// Insert a select instruction into MBB before I that will copy TrueReg to
     741             :   /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
     742             :   ///
     743             :   /// This function can only be called after canInsertSelect() returned true.
     744             :   /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
     745             :   /// that the same flags or registers required by Cond are available at the
     746             :   /// insertion point.
     747             :   ///
     748             :   /// @param MBB      Block where select instruction should be inserted.
     749             :   /// @param I        Insertion point.
     750             :   /// @param DL       Source location for debugging.
     751             :   /// @param DstReg   Virtual register to be defined by select instruction.
     752             :   /// @param Cond     Condition as computed by AnalyzeBranch.
     753             :   /// @param TrueReg  Virtual register to copy when Cond is true.
     754             :   /// @param FalseReg Virtual register to copy when Cons is false.
     755           0 :   virtual void insertSelect(MachineBasicBlock &MBB,
     756             :                             MachineBasicBlock::iterator I, const DebugLoc &DL,
     757             :                             unsigned DstReg, ArrayRef<MachineOperand> Cond,
     758             :                             unsigned TrueReg, unsigned FalseReg) const {
     759           0 :     llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
     760             :   }
     761             : 
     762             :   /// Analyze the given select instruction, returning true if
     763             :   /// it cannot be understood. It is assumed that MI->isSelect() is true.
     764             :   ///
     765             :   /// When successful, return the controlling condition and the operands that
     766             :   /// determine the true and false result values.
     767             :   ///
     768             :   ///   Result = SELECT Cond, TrueOp, FalseOp
     769             :   ///
     770             :   /// Some targets can optimize select instructions, for example by predicating
     771             :   /// the instruction defining one of the operands. Such targets should set
     772             :   /// Optimizable.
     773             :   ///
     774             :   /// @param         MI Select instruction to analyze.
     775             :   /// @param Cond    Condition controlling the select.
     776             :   /// @param TrueOp  Operand number of the value selected when Cond is true.
     777             :   /// @param FalseOp Operand number of the value selected when Cond is false.
     778             :   /// @param Optimizable Returned as true if MI is optimizable.
     779             :   /// @returns False on success.
     780         337 :   virtual bool analyzeSelect(const MachineInstr &MI,
     781             :                              SmallVectorImpl<MachineOperand> &Cond,
     782             :                              unsigned &TrueOp, unsigned &FalseOp,
     783             :                              bool &Optimizable) const {
     784             :     assert(MI.getDesc().isSelect() && "MI must be a select instruction");
     785         337 :     return true;
     786             :   }
     787             : 
     788             :   /// Given a select instruction that was understood by
     789             :   /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
     790             :   /// merging it with one of its operands. Returns NULL on failure.
     791             :   ///
     792             :   /// When successful, returns the new select instruction. The client is
     793             :   /// responsible for deleting MI.
     794             :   ///
     795             :   /// If both sides of the select can be optimized, PreferFalse is used to pick
     796             :   /// a side.
     797             :   ///
     798             :   /// @param MI          Optimizable select instruction.
     799             :   /// @param NewMIs     Set that record all MIs in the basic block up to \p
     800             :   /// MI. Has to be updated with any newly created MI or deleted ones.
     801             :   /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
     802             :   /// @returns Optimized instruction or NULL.
     803           0 :   virtual MachineInstr *optimizeSelect(MachineInstr &MI,
     804             :                                        SmallPtrSetImpl<MachineInstr *> &NewMIs,
     805             :                                        bool PreferFalse = false) const {
     806             :     // This function must be implemented if Optimizable is ever set.
     807           0 :     llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
     808             :   }
     809             : 
     810             :   /// Emit instructions to copy a pair of physical registers.
     811             :   ///
     812             :   /// This function should support copies within any legal register class as
     813             :   /// well as any cross-class copies created during instruction selection.
     814             :   ///
     815             :   /// The source and destination registers may overlap, which may require a
     816             :   /// careful implementation when multiple copy instructions are required for
     817             :   /// large registers. See for example the ARM target.
     818           0 :   virtual void copyPhysReg(MachineBasicBlock &MBB,
     819             :                            MachineBasicBlock::iterator MI, const DebugLoc &DL,
     820             :                            unsigned DestReg, unsigned SrcReg,
     821             :                            bool KillSrc) const {
     822           0 :     llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
     823             :   }
     824             : 
     825             :   /// Store the specified register of the given register class to the specified
     826             :   /// stack frame index. The store instruction is to be added to the given
     827             :   /// machine basic block before the specified machine instruction. If isKill
     828             :   /// is true, the register operand is the last use and must be marked kill.
     829           0 :   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
     830             :                                    MachineBasicBlock::iterator MI,
     831             :                                    unsigned SrcReg, bool isKill, int FrameIndex,
     832             :                                    const TargetRegisterClass *RC,
     833             :                                    const TargetRegisterInfo *TRI) const {
     834           0 :     llvm_unreachable("Target didn't implement "
     835             :                      "TargetInstrInfo::storeRegToStackSlot!");
     836             :   }
     837             : 
     838             :   /// Load the specified register of the given register class from the specified
     839             :   /// stack frame index. The load instruction is to be added to the given
     840             :   /// machine basic block before the specified machine instruction.
     841           0 :   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
     842             :                                     MachineBasicBlock::iterator MI,
     843             :                                     unsigned DestReg, int FrameIndex,
     844             :                                     const TargetRegisterClass *RC,
     845             :                                     const TargetRegisterInfo *TRI) const {
     846           0 :     llvm_unreachable("Target didn't implement "
     847             :                      "TargetInstrInfo::loadRegFromStackSlot!");
     848             :   }
     849             : 
     850             :   /// This function is called for all pseudo instructions
     851             :   /// that remain after register allocation. Many pseudo instructions are
     852             :   /// created to help register allocation. This is the place to convert them
     853             :   /// into real instructions. The target can edit MI in place, or it can insert
     854             :   /// new instructions and erase MI. The function should return true if
     855             :   /// anything was changed.
     856         871 :   virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
     857             : 
     858             :   /// Check whether the target can fold a load that feeds a subreg operand
     859             :   /// (or a subreg operand that feeds a store).
     860             :   /// For example, X86 may want to return true if it can fold
     861             :   /// movl (%esp), %eax
     862             :   /// subb, %al, ...
     863             :   /// Into:
     864             :   /// subb (%esp), ...
     865             :   ///
     866             :   /// Ideally, we'd like the target implementation of foldMemoryOperand() to
     867             :   /// reject subregs - but since this behavior used to be enforced in the
     868             :   /// target-independent code, moving this responsibility to the targets
     869             :   /// has the potential of causing nasty silent breakage in out-of-tree targets.
     870        6588 :   virtual bool isSubregFoldable() const { return false; }
     871             : 
     872             :   /// Attempt to fold a load or store of the specified stack
     873             :   /// slot into the specified machine instruction for the specified operand(s).
     874             :   /// If this is possible, a new instruction is returned with the specified
     875             :   /// operand folded, otherwise NULL is returned.
     876             :   /// The new instruction is inserted before MI, and the client is responsible
     877             :   /// for removing the old instruction.
     878             :   MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
     879             :                                   int FrameIndex,
     880             :                                   LiveIntervals *LIS = nullptr) const;
     881             : 
     882             :   /// Same as the previous version except it allows folding of any load and
     883             :   /// store from / to any address, not just from a specific stack slot.
     884             :   MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
     885             :                                   MachineInstr &LoadMI,
     886             :                                   LiveIntervals *LIS = nullptr) const;
     887             : 
     888             :   /// Return true when there is potentially a faster code sequence
     889             :   /// for an instruction chain ending in \p Root. All potential patterns are
     890             :   /// returned in the \p Pattern vector. Pattern should be sorted in priority
     891             :   /// order since the pattern evaluator stops checking as soon as it finds a
     892             :   /// faster sequence.
     893             :   /// \param Root - Instruction that could be combined with one of its operands
     894             :   /// \param Patterns - Vector of possible combination patterns
     895             :   virtual bool getMachineCombinerPatterns(
     896             :       MachineInstr &Root,
     897             :       SmallVectorImpl<MachineCombinerPattern> &Patterns) const;
     898             : 
     899             :   /// Return true when a code sequence can improve throughput. It
     900             :   /// should be called only for instructions in loops.
     901             :   /// \param Pattern - combiner pattern
     902             :   virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
     903             : 
     904             :   /// Return true if the input \P Inst is part of a chain of dependent ops
     905             :   /// that are suitable for reassociation, otherwise return false.
     906             :   /// If the instruction's operands must be commuted to have a previous
     907             :   /// instruction of the same type define the first source operand, \P Commuted
     908             :   /// will be set to true.
     909             :   bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
     910             : 
     911             :   /// Return true when \P Inst is both associative and commutative.
     912           0 :   virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
     913           0 :     return false;
     914             :   }
     915             : 
     916             :   /// Return true when \P Inst has reassociable operands in the same \P MBB.
     917             :   virtual bool hasReassociableOperands(const MachineInstr &Inst,
     918             :                                        const MachineBasicBlock *MBB) const;
     919             : 
     920             :   /// Return true when \P Inst has reassociable sibling.
     921             :   bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
     922             : 
     923             :   /// When getMachineCombinerPatterns() finds patterns, this function generates
     924             :   /// the instructions that could replace the original code sequence. The client
     925             :   /// has to decide whether the actual replacement is beneficial or not.
     926             :   /// \param Root - Instruction that could be combined with one of its operands
     927             :   /// \param Pattern - Combination pattern for Root
     928             :   /// \param InsInstrs - Vector of new instructions that implement P
     929             :   /// \param DelInstrs - Old instructions, including Root, that could be
     930             :   /// replaced by InsInstr
     931             :   /// \param InstrIdxForVirtReg - map of virtual register to instruction in
     932             :   /// InsInstr that defines it
     933             :   virtual void genAlternativeCodeSequence(
     934             :       MachineInstr &Root, MachineCombinerPattern Pattern,
     935             :       SmallVectorImpl<MachineInstr *> &InsInstrs,
     936             :       SmallVectorImpl<MachineInstr *> &DelInstrs,
     937             :       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
     938             : 
     939             :   /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
     940             :   /// reduce critical path length.
     941             :   void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
     942             :                       MachineCombinerPattern Pattern,
     943             :                       SmallVectorImpl<MachineInstr *> &InsInstrs,
     944             :                       SmallVectorImpl<MachineInstr *> &DelInstrs,
     945             :                       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
     946             : 
     947             :   /// This is an architecture-specific helper function of reassociateOps.
     948             :   /// Set special operand attributes for new instructions after reassociation.
     949         269 :   virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
     950             :                                      MachineInstr &NewMI1,
     951         269 :                                      MachineInstr &NewMI2) const {}
     952             : 
     953             :   /// Return true when a target supports MachineCombiner.
     954           0 :   virtual bool useMachineCombiner() const { return false; }
     955             : 
     956             :   /// Return true if the given SDNode can be copied during scheduling
     957             :   /// even if it has glue.
     958          88 :   virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
     959             : 
     960             : protected:
     961             :   /// Target-dependent implementation for foldMemoryOperand.
     962             :   /// Target-independent code in foldMemoryOperand will
     963             :   /// take care of adding a MachineMemOperand to the newly created instruction.
     964             :   /// The instruction and any auxiliary instructions necessary will be inserted
     965             :   /// at InsertPt.
     966             :   virtual MachineInstr *
     967        5629 :   foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
     968             :                         ArrayRef<unsigned> Ops,
     969             :                         MachineBasicBlock::iterator InsertPt, int FrameIndex,
     970             :                         LiveIntervals *LIS = nullptr) const {
     971        5629 :     return nullptr;
     972             :   }
     973             : 
     974             :   /// Target-dependent implementation for foldMemoryOperand.
     975             :   /// Target-independent code in foldMemoryOperand will
     976             :   /// take care of adding a MachineMemOperand to the newly created instruction.
     977             :   /// The instruction and any auxiliary instructions necessary will be inserted
     978             :   /// at InsertPt.
     979          24 :   virtual MachineInstr *foldMemoryOperandImpl(
     980             :       MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
     981             :       MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
     982             :       LiveIntervals *LIS = nullptr) const {
     983          24 :     return nullptr;
     984             :   }
     985             : 
     986             :   /// \brief Target-dependent implementation of getRegSequenceInputs.
     987             :   ///
     988             :   /// \returns true if it is possible to build the equivalent
     989             :   /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
     990             :   ///
     991             :   /// \pre MI.isRegSequenceLike().
     992             :   ///
     993             :   /// \see TargetInstrInfo::getRegSequenceInputs.
     994           0 :   virtual bool getRegSequenceLikeInputs(
     995             :       const MachineInstr &MI, unsigned DefIdx,
     996             :       SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
     997           0 :     return false;
     998             :   }
     999             : 
    1000             :   /// \brief Target-dependent implementation of getExtractSubregInputs.
    1001             :   ///
    1002             :   /// \returns true if it is possible to build the equivalent
    1003             :   /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
    1004             :   ///
    1005             :   /// \pre MI.isExtractSubregLike().
    1006             :   ///
    1007             :   /// \see TargetInstrInfo::getExtractSubregInputs.
    1008           0 :   virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
    1009             :                                           unsigned DefIdx,
    1010             :                                           RegSubRegPairAndIdx &InputReg) const {
    1011           0 :     return false;
    1012             :   }
    1013             : 
    1014             :   /// \brief Target-dependent implementation of getInsertSubregInputs.
    1015             :   ///
    1016             :   /// \returns true if it is possible to build the equivalent
    1017             :   /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
    1018             :   ///
    1019             :   /// \pre MI.isInsertSubregLike().
    1020             :   ///
    1021             :   /// \see TargetInstrInfo::getInsertSubregInputs.
    1022             :   virtual bool
    1023           0 :   getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
    1024             :                             RegSubRegPair &BaseReg,
    1025             :                             RegSubRegPairAndIdx &InsertedReg) const {
    1026           0 :     return false;
    1027             :   }
    1028             : 
    1029             : public:
    1030             :   /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
    1031             :   /// (e.g. stack) the target returns the corresponding address space.
    1032             :   virtual unsigned
    1033      676571 :   getAddressSpaceForPseudoSourceKind(PseudoSourceValue::PSVKind Kind) const {
    1034      676571 :     return 0;
    1035             :   }
    1036             : 
    1037             :   /// unfoldMemoryOperand - Separate a single instruction which folded a load or
    1038             :   /// a store or a load and a store into two or more instruction. If this is
    1039             :   /// possible, returns true as well as the new instructions by reference.
    1040             :   virtual bool
    1041           0 :   unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
    1042             :                       bool UnfoldLoad, bool UnfoldStore,
    1043             :                       SmallVectorImpl<MachineInstr *> &NewMIs) const {
    1044           0 :     return false;
    1045             :   }
    1046             : 
    1047           0 :   virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
    1048             :                                    SmallVectorImpl<SDNode *> &NewNodes) const {
    1049           0 :     return false;
    1050             :   }
    1051             : 
    1052             :   /// Returns the opcode of the would be new
    1053             :   /// instruction after load / store are unfolded from an instruction of the
    1054             :   /// specified opcode. It returns zero if the specified unfolding is not
    1055             :   /// possible. If LoadRegIndex is non-null, it is filled in with the operand
    1056             :   /// index of the operand which will hold the register holding the loaded
    1057             :   /// value.
    1058             :   virtual unsigned
    1059         509 :   getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
    1060             :                              unsigned *LoadRegIndex = nullptr) const {
    1061         509 :     return 0;
    1062             :   }
    1063             : 
    1064             :   /// This is used by the pre-regalloc scheduler to determine if two loads are
    1065             :   /// loading from the same base address. It should only return true if the base
    1066             :   /// pointers are the same and the only differences between the two addresses
    1067             :   /// are the offset. It also returns the offsets by reference.
    1068      255687 :   virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
    1069             :                                        int64_t &Offset1,
    1070             :                                        int64_t &Offset2) const {
    1071      255687 :     return false;
    1072             :   }
    1073             : 
    1074             :   /// This is a used by the pre-regalloc scheduler to determine (in conjunction
    1075             :   /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
    1076             :   /// On some targets if two loads are loading from
    1077             :   /// addresses in the same cache line, it's better if they are scheduled
    1078             :   /// together. This function takes two integers that represent the load offsets
    1079             :   /// from the common base address. It returns true if it decides it's desirable
    1080             :   /// to schedule the two loads together. "NumLoads" is the number of loads that
    1081             :   /// have already been scheduled after Load1.
    1082           0 :   virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
    1083             :                                        int64_t Offset1, int64_t Offset2,
    1084             :                                        unsigned NumLoads) const {
    1085           0 :     return false;
    1086             :   }
    1087             : 
    1088             :   /// Get the base register and byte offset of an instruction that reads/writes
    1089             :   /// memory.
    1090           0 :   virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
    1091             :                                      int64_t &Offset,
    1092             :                                      const TargetRegisterInfo *TRI) const {
    1093           0 :     return false;
    1094             :   }
    1095             : 
    1096             :   /// Return true if the instruction contains a base register and offset. If
    1097             :   /// true, the function also sets the operand position in the instruction
    1098             :   /// for the base register and offset.
    1099           0 :   virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
    1100             :                                         unsigned &BasePos,
    1101             :                                         unsigned &OffsetPos) const {
    1102           0 :     return false;
    1103             :   }
    1104             : 
    1105             :   /// If the instruction is an increment of a constant value, return the amount.
    1106           0 :   virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
    1107           0 :     return false;
    1108             :   }
    1109             : 
    1110             :   /// Returns true if the two given memory operations should be scheduled
    1111             :   /// adjacent. Note that you have to add:
    1112             :   ///   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
    1113             :   /// or
    1114             :   ///   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
    1115             :   /// to TargetPassConfig::createMachineScheduler() to have an effect.
    1116           0 :   virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
    1117             :                                    MachineInstr &SecondLdSt, unsigned BaseReg2,
    1118             :                                    unsigned NumLoads) const {
    1119           0 :     llvm_unreachable("target did not implement shouldClusterMemOps()");
    1120             :   }
    1121             : 
    1122             :   /// Reverses the branch condition of the specified condition list,
    1123             :   /// returning false on success and true if it cannot be reversed.
    1124             :   virtual bool
    1125          96 :   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
    1126          96 :     return true;
    1127             :   }
    1128             : 
    1129             :   /// Insert a noop into the instruction stream at the specified point.
    1130             :   virtual void insertNoop(MachineBasicBlock &MBB,
    1131             :                           MachineBasicBlock::iterator MI) const;
    1132             : 
    1133             :   /// Return the noop instruction to use for a noop.
    1134             :   virtual void getNoop(MCInst &NopInst) const;
    1135             : 
    1136             :   /// Return true for post-incremented instructions.
    1137           0 :   virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
    1138             : 
    1139             :   /// Returns true if the instruction is already predicated.
    1140     4164176 :   virtual bool isPredicated(const MachineInstr &MI) const { return false; }
    1141             : 
    1142             :   /// Returns true if the instruction is a
    1143             :   /// terminator instruction that has not been predicated.
    1144             :   virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
    1145             : 
    1146             :   /// Returns true if MI is an unconditional tail call.
    1147         715 :   virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
    1148         715 :     return false;
    1149             :   }
    1150             : 
    1151             :   /// Returns true if the tail call can be made conditional on BranchCond.
    1152           0 :   virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
    1153             :                                           const MachineInstr &TailCall) const {
    1154           0 :     return false;
    1155             :   }
    1156             : 
    1157             :   /// Replace the conditional branch in MBB with a conditional tail call.
    1158           0 :   virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
    1159             :                                          SmallVectorImpl<MachineOperand> &Cond,
    1160             :                                          const MachineInstr &TailCall) const {
    1161           0 :     llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
    1162             :   }
    1163             : 
    1164             :   /// Convert the instruction into a predicated instruction.
    1165             :   /// It returns true if the operation was successful.
    1166             :   virtual bool PredicateInstruction(MachineInstr &MI,
    1167             :                                     ArrayRef<MachineOperand> Pred) const;
    1168             : 
    1169             :   /// Returns true if the first specified predicate
    1170             :   /// subsumes the second, e.g. GE subsumes GT.
    1171           0 :   virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
    1172             :                                  ArrayRef<MachineOperand> Pred2) const {
    1173           0 :     return false;
    1174             :   }
    1175             : 
    1176             :   /// If the specified instruction defines any predicate
    1177             :   /// or condition code register(s) used for predication, returns true as well
    1178             :   /// as the definition predicate(s) by reference.
    1179       10065 :   virtual bool DefinesPredicate(MachineInstr &MI,
    1180             :                                 std::vector<MachineOperand> &Pred) const {
    1181       10065 :     return false;
    1182             :   }
    1183             : 
    1184             :   /// Return true if the specified instruction can be predicated.
    1185             :   /// By default, this returns true for every instruction with a
    1186             :   /// PredicateOperand.
    1187           0 :   virtual bool isPredicable(const MachineInstr &MI) const {
    1188         888 :     return MI.getDesc().isPredicable();
    1189             :   }
    1190             : 
    1191             :   /// Return true if it's safe to move a machine
    1192             :   /// instruction that defines the specified register class.
    1193       58555 :   virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
    1194       58555 :     return true;
    1195             :   }
    1196             : 
    1197             :   /// Test if the given instruction should be considered a scheduling boundary.
    1198             :   /// This primarily includes labels and terminators.
    1199             :   virtual bool isSchedulingBoundary(const MachineInstr &MI,
    1200             :                                     const MachineBasicBlock *MBB,
    1201             :                                     const MachineFunction &MF) const;
    1202             : 
    1203             :   /// Measure the specified inline asm to determine an approximation of its
    1204             :   /// length.
    1205             :   virtual unsigned getInlineAsmLength(const char *Str,
    1206             :                                       const MCAsmInfo &MAI) const;
    1207             : 
    1208             :   /// Allocate and return a hazard recognizer to use for this target when
    1209             :   /// scheduling the machine instructions before register allocation.
    1210             :   virtual ScheduleHazardRecognizer *
    1211             :   CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
    1212             :                                const ScheduleDAG *DAG) const;
    1213             : 
    1214             :   /// Allocate and return a hazard recognizer to use for this target when
    1215             :   /// scheduling the machine instructions before register allocation.
    1216             :   virtual ScheduleHazardRecognizer *
    1217             :   CreateTargetMIHazardRecognizer(const InstrItineraryData *,
    1218             :                                  const ScheduleDAG *DAG) const;
    1219             : 
    1220             :   /// Allocate and return a hazard recognizer to use for this target when
    1221             :   /// scheduling the machine instructions after register allocation.
    1222             :   virtual ScheduleHazardRecognizer *
    1223             :   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *,
    1224             :                                      const ScheduleDAG *DAG) const;
    1225             : 
    1226             :   /// Allocate and return a hazard recognizer to use for by non-scheduling
    1227             :   /// passes.
    1228             :   virtual ScheduleHazardRecognizer *
    1229           0 :   CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
    1230           0 :     return nullptr;
    1231             :   }
    1232             : 
    1233             :   /// Provide a global flag for disabling the PreRA hazard recognizer that
    1234             :   /// targets may choose to honor.
    1235             :   bool usePreRAHazardRecognizer() const;
    1236             : 
    1237             :   /// For a comparison instruction, return the source registers
    1238             :   /// in SrcReg and SrcReg2 if having two register operands, and the value it
    1239             :   /// compares against in CmpValue. Return true if the comparison instruction
    1240             :   /// can be analyzed.
    1241        4443 :   virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
    1242             :                               unsigned &SrcReg2, int &Mask, int &Value) const {
    1243        4443 :     return false;
    1244             :   }
    1245             : 
    1246             :   /// See if the comparison instruction can be converted
    1247             :   /// into something more efficient. E.g., on ARM most instructions can set the
    1248             :   /// flags register, obviating the need for a separate CMP.
    1249         540 :   virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
    1250             :                                     unsigned SrcReg2, int Mask, int Value,
    1251             :                                     const MachineRegisterInfo *MRI) const {
    1252         540 :     return false;
    1253             :   }
    1254       43871 :   virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
    1255             : 
    1256             :   /// Try to remove the load by folding it to a register operand at the use.
    1257             :   /// We fold the load instructions if and only if the
    1258             :   /// def and use are in the same BB. We only look at one load and see
    1259             :   /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
    1260             :   /// defined by the load we are trying to fold. DefMI returns the machine
    1261             :   /// instruction that defines FoldAsLoadDefReg, and the function returns
    1262             :   /// the machine instruction generated due to folding.
    1263       12950 :   virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
    1264             :                                           const MachineRegisterInfo *MRI,
    1265             :                                           unsigned &FoldAsLoadDefReg,
    1266             :                                           MachineInstr *&DefMI) const {
    1267       12950 :     return nullptr;
    1268             :   }
    1269             : 
    1270             :   /// 'Reg' is known to be defined by a move immediate instruction,
    1271             :   /// try to fold the immediate into the use instruction.
    1272             :   /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
    1273             :   /// then the caller may assume that DefMI has been erased from its parent
    1274             :   /// block. The caller may assume that it will not be erased by this
    1275             :   /// function otherwise.
    1276        3920 :   virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
    1277             :                              unsigned Reg, MachineRegisterInfo *MRI) const {
    1278        3920 :     return false;
    1279             :   }
    1280             : 
    1281             :   /// Return the number of u-operations the given machine
    1282             :   /// instruction will be decoded to on the target cpu. The itinerary's
    1283             :   /// IssueWidth is the number of microops that can be dispatched each
    1284             :   /// cycle. An instruction with zero microops takes no dispatch resources.
    1285             :   virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
    1286             :                                   const MachineInstr &MI) const;
    1287             : 
    1288             :   /// Return true for pseudo instructions that don't consume any
    1289             :   /// machine resources in their current form. These are common cases that the
    1290             :   /// scheduler should consider free, rather than conservatively handling them
    1291             :   /// as instructions with no itinerary.
    1292             :   bool isZeroCost(unsigned Opcode) const {
    1293             :     return Opcode <= TargetOpcode::COPY;
    1294             :   }
    1295             : 
    1296             :   virtual int getOperandLatency(const InstrItineraryData *ItinData,
    1297             :                                 SDNode *DefNode, unsigned DefIdx,
    1298             :                                 SDNode *UseNode, unsigned UseIdx) const;
    1299             : 
    1300             :   /// Compute and return the use operand latency of a given pair of def and use.
    1301             :   /// In most cases, the static scheduling itinerary was enough to determine the
    1302             :   /// operand latency. But it may not be possible for instructions with variable
    1303             :   /// number of defs / uses.
    1304             :   ///
    1305             :   /// This is a raw interface to the itinerary that may be directly overridden
    1306             :   /// by a target. Use computeOperandLatency to get the best estimate of
    1307             :   /// latency.
    1308             :   virtual int getOperandLatency(const InstrItineraryData *ItinData,
    1309             :                                 const MachineInstr &DefMI, unsigned DefIdx,
    1310             :                                 const MachineInstr &UseMI,
    1311             :                                 unsigned UseIdx) const;
    1312             : 
    1313             :   /// Compute the instruction latency of a given instruction.
    1314             :   /// If the instruction has higher cost when predicated, it's returned via
    1315             :   /// PredCost.
    1316             :   virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
    1317             :                                    const MachineInstr &MI,
    1318             :                                    unsigned *PredCost = nullptr) const;
    1319             : 
    1320             :   virtual unsigned getPredicationCost(const MachineInstr &MI) const;
    1321             : 
    1322             :   virtual int getInstrLatency(const InstrItineraryData *ItinData,
    1323             :                               SDNode *Node) const;
    1324             : 
    1325             :   /// Return the default expected latency for a def based on its opcode.
    1326             :   unsigned defaultDefLatency(const MCSchedModel &SchedModel,
    1327             :                              const MachineInstr &DefMI) const;
    1328             : 
    1329             :   int computeDefOperandLatency(const InstrItineraryData *ItinData,
    1330             :                                const MachineInstr &DefMI) const;
    1331             : 
    1332             :   /// Return true if this opcode has high latency to its result.
    1333      513956 :   virtual bool isHighLatencyDef(int opc) const { return false; }
    1334             : 
    1335             :   /// Compute operand latency between a def of 'Reg'
    1336             :   /// and a use in the current loop. Return true if the target considered
    1337             :   /// it 'high'. This is used by optimization passes such as machine LICM to
    1338             :   /// determine whether it makes sense to hoist an instruction out even in a
    1339             :   /// high register pressure situation.
    1340        1159 :   virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
    1341             :                                      const MachineRegisterInfo *MRI,
    1342             :                                      const MachineInstr &DefMI, unsigned DefIdx,
    1343             :                                      const MachineInstr &UseMI,
    1344             :                                      unsigned UseIdx) const {
    1345        1159 :     return false;
    1346             :   }
    1347             : 
    1348             :   /// Compute operand latency of a def of 'Reg'. Return true
    1349             :   /// if the target considered it 'low'.
    1350             :   virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
    1351             :                                 const MachineInstr &DefMI,
    1352             :                                 unsigned DefIdx) const;
    1353             : 
    1354             :   /// Perform target-specific instruction verification.
    1355     5269389 :   virtual bool verifyInstruction(const MachineInstr &MI,
    1356             :                                  StringRef &ErrInfo) const {
    1357     5269389 :     return true;
    1358             :   }
    1359             : 
    1360             :   /// Return the current execution domain and bit mask of
    1361             :   /// possible domains for instruction.
    1362             :   ///
    1363             :   /// Some micro-architectures have multiple execution domains, and multiple
    1364             :   /// opcodes that perform the same operation in different domains.  For
    1365             :   /// example, the x86 architecture provides the por, orps, and orpd
    1366             :   /// instructions that all do the same thing.  There is a latency penalty if a
    1367             :   /// register is written in one domain and read in another.
    1368             :   ///
    1369             :   /// This function returns a pair (domain, mask) containing the execution
    1370             :   /// domain of MI, and a bit mask of possible domains.  The setExecutionDomain
    1371             :   /// function can be used to change the opcode to one of the domains in the
    1372             :   /// bit mask.  Instructions whose execution domain can't be changed should
    1373             :   /// return a 0 mask.
    1374             :   ///
    1375             :   /// The execution domain numbers don't have any special meaning except domain
    1376             :   /// 0 is used for instructions that are not associated with any interesting
    1377             :   /// execution domain.
    1378             :   ///
    1379             :   virtual std::pair<uint16_t, uint16_t>
    1380           0 :   getExecutionDomain(const MachineInstr &MI) const {
    1381           0 :     return std::make_pair(0, 0);
    1382             :   }
    1383             : 
    1384             :   /// Change the opcode of MI to execute in Domain.
    1385             :   ///
    1386             :   /// The bit (1 << Domain) must be set in the mask returned from
    1387             :   /// getExecutionDomain(MI).
    1388           0 :   virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
    1389             : 
    1390             :   /// Returns the preferred minimum clearance
    1391             :   /// before an instruction with an unwanted partial register update.
    1392             :   ///
    1393             :   /// Some instructions only write part of a register, and implicitly need to
    1394             :   /// read the other parts of the register.  This may cause unwanted stalls
    1395             :   /// preventing otherwise unrelated instructions from executing in parallel in
    1396             :   /// an out-of-order CPU.
    1397             :   ///
    1398             :   /// For example, the x86 instruction cvtsi2ss writes its result to bits
    1399             :   /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
    1400             :   /// the instruction needs to wait for the old value of the register to become
    1401             :   /// available:
    1402             :   ///
    1403             :   ///   addps %xmm1, %xmm0
    1404             :   ///   movaps %xmm0, (%rax)
    1405             :   ///   cvtsi2ss %rbx, %xmm0
    1406             :   ///
    1407             :   /// In the code above, the cvtsi2ss instruction needs to wait for the addps
    1408             :   /// instruction before it can issue, even though the high bits of %xmm0
    1409             :   /// probably aren't needed.
    1410             :   ///
    1411             :   /// This hook returns the preferred clearance before MI, measured in
    1412             :   /// instructions.  Other defs of MI's operand OpNum are avoided in the last N
    1413             :   /// instructions before MI.  It should only return a positive value for
    1414             :   /// unwanted dependencies.  If the old bits of the defined register have
    1415             :   /// useful values, or if MI is determined to otherwise read the dependency,
    1416             :   /// the hook should return 0.
    1417             :   ///
    1418             :   /// The unwanted dependency may be handled by:
    1419             :   ///
    1420             :   /// 1. Allocating the same register for an MI def and use.  That makes the
    1421             :   ///    unwanted dependency identical to a required dependency.
    1422             :   ///
    1423             :   /// 2. Allocating a register for the def that has no defs in the previous N
    1424             :   ///    instructions.
    1425             :   ///
    1426             :   /// 3. Calling breakPartialRegDependency() with the same arguments.  This
    1427             :   ///    allows the target to insert a dependency breaking instruction.
    1428             :   ///
    1429             :   virtual unsigned
    1430           0 :   getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
    1431             :                                const TargetRegisterInfo *TRI) const {
    1432             :     // The default implementation returns 0 for no partial register dependency.
    1433           0 :     return 0;
    1434             :   }
    1435             : 
    1436             :   /// \brief Return the minimum clearance before an instruction that reads an
    1437             :   /// unused register.
    1438             :   ///
    1439             :   /// For example, AVX instructions may copy part of a register operand into
    1440             :   /// the unused high bits of the destination register.
    1441             :   ///
    1442             :   /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
    1443             :   ///
    1444             :   /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
    1445             :   /// false dependence on any previous write to %xmm0.
    1446             :   ///
    1447             :   /// This hook works similarly to getPartialRegUpdateClearance, except that it
    1448             :   /// does not take an operand index. Instead sets \p OpNum to the index of the
    1449             :   /// unused register.
    1450      119744 :   virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
    1451             :                                         const TargetRegisterInfo *TRI) const {
    1452             :     // The default implementation returns 0 for no undef register dependency.
    1453      119744 :     return 0;
    1454             :   }
    1455             : 
    1456             :   /// Insert a dependency-breaking instruction
    1457             :   /// before MI to eliminate an unwanted dependency on OpNum.
    1458             :   ///
    1459             :   /// If it wasn't possible to avoid a def in the last N instructions before MI
    1460             :   /// (see getPartialRegUpdateClearance), this hook will be called to break the
    1461             :   /// unwanted dependency.
    1462             :   ///
    1463             :   /// On x86, an xorps instruction can be used as a dependency breaker:
    1464             :   ///
    1465             :   ///   addps %xmm1, %xmm0
    1466             :   ///   movaps %xmm0, (%rax)
    1467             :   ///   xorps %xmm0, %xmm0
    1468             :   ///   cvtsi2ss %rbx, %xmm0
    1469             :   ///
    1470             :   /// An <imp-kill> operand should be added to MI if an instruction was
    1471             :   /// inserted.  This ties the instructions together in the post-ra scheduler.
    1472             :   ///
    1473           0 :   virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
    1474           0 :                                          const TargetRegisterInfo *TRI) const {}
    1475             : 
    1476             :   /// Create machine specific model for scheduling.
    1477             :   virtual DFAPacketizer *
    1478           0 :   CreateTargetScheduleState(const TargetSubtargetInfo &) const {
    1479           0 :     return nullptr;
    1480             :   }
    1481             : 
    1482             :   /// Sometimes, it is possible for the target
    1483             :   /// to tell, even without aliasing information, that two MIs access different
    1484             :   /// memory addresses. This function returns true if two MIs access different
    1485             :   /// memory addresses and false otherwise.
    1486             :   ///
    1487             :   /// Assumes any physical registers used to compute addresses have the same
    1488             :   /// value for both instructions. (This is the most useful assumption for
    1489             :   /// post-RA scheduling.)
    1490             :   ///
    1491             :   /// See also MachineInstr::mayAlias, which is implemented on top of this
    1492             :   /// function.
    1493             :   virtual bool
    1494     2208048 :   areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
    1495             :                                   AliasAnalysis *AA = nullptr) const {
    1496             :     assert((MIa.mayLoad() || MIa.mayStore()) &&
    1497             :            "MIa must load from or modify a memory location");
    1498             :     assert((MIb.mayLoad() || MIb.mayStore()) &&
    1499             :            "MIb must load from or modify a memory location");
    1500     2208048 :     return false;
    1501             :   }
    1502             : 
    1503             :   /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
    1504             :   /// which is a heuristic used for CSE'ing phys reg defs.
    1505      143235 :   virtual unsigned getMachineCSELookAheadLimit() const {
    1506             :     // The default lookahead is small to prevent unprofitable quadratic
    1507             :     // behavior.
    1508      143235 :     return 5;
    1509             :   }
    1510             : 
    1511             :   /// Return an array that contains the ids of the target indices (used for the
    1512             :   /// TargetIndex machine operand) and their names.
    1513             :   ///
    1514             :   /// MIR Serialization is able to serialize only the target indices that are
    1515             :   /// defined by this method.
    1516             :   virtual ArrayRef<std::pair<int, const char *>>
    1517           0 :   getSerializableTargetIndices() const {
    1518           0 :     return None;
    1519             :   }
    1520             : 
    1521             :   /// Decompose the machine operand's target flags into two values - the direct
    1522             :   /// target flag value and any of bit flags that are applied.
    1523             :   virtual std::pair<unsigned, unsigned>
    1524           0 :   decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
    1525           0 :     return std::make_pair(0u, 0u);
    1526             :   }
    1527             : 
    1528             :   /// Return an array that contains the direct target flag values and their
    1529             :   /// names.
    1530             :   ///
    1531             :   /// MIR Serialization is able to serialize only the target flags that are
    1532             :   /// defined by this method.
    1533             :   virtual ArrayRef<std::pair<unsigned, const char *>>
    1534           0 :   getSerializableDirectMachineOperandTargetFlags() const {
    1535           0 :     return None;
    1536             :   }
    1537             : 
    1538             :   /// Return an array that contains the bitmask target flag values and their
    1539             :   /// names.
    1540             :   ///
    1541             :   /// MIR Serialization is able to serialize only the target flags that are
    1542             :   /// defined by this method.
    1543             :   virtual ArrayRef<std::pair<unsigned, const char *>>
    1544           1 :   getSerializableBitmaskMachineOperandTargetFlags() const {
    1545           1 :     return None;
    1546             :   }
    1547             : 
    1548             :   /// Return an array that contains the MMO target flag values and their
    1549             :   /// names.
    1550             :   ///
    1551             :   /// MIR Serialization is able to serialize only the MMO target flags that are
    1552             :   /// defined by this method.
    1553             :   virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
    1554           0 :   getSerializableMachineMemOperandTargetFlags() const {
    1555           0 :     return None;
    1556             :   }
    1557             : 
    1558             :   /// Determines whether \p Inst is a tail call instruction. Override this
    1559             :   /// method on targets that do not properly set MCID::Return and MCID::Call on
    1560             :   /// tail call instructions."
    1561         302 :   virtual bool isTailCall(const MachineInstr &Inst) const {
    1562         398 :     return Inst.isReturn() && Inst.isCall();
    1563             :   }
    1564             : 
    1565             :   /// True if the instruction is bound to the top of its basic block and no
    1566             :   /// other instructions shall be inserted before it. This can be implemented
    1567             :   /// to prevent register allocator to insert spills before such instructions.
    1568       72274 :   virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
    1569       72274 :     return false;
    1570             :   }
    1571             : 
    1572             :   /// \brief Describes the number of instructions that it will take to call and
    1573             :   /// construct a frame for a given outlining candidate.
    1574             :   struct MachineOutlinerInfo {
    1575             :     /// Number of instructions to call an outlined function for this candidate.
    1576             :     unsigned CallOverhead;
    1577             : 
    1578             :     /// \brief Number of instructions to construct an outlined function frame
    1579             :     /// for this candidate.
    1580             :     unsigned FrameOverhead;
    1581             : 
    1582             :     /// \brief Represents the specific instructions that must be emitted to
    1583             :     /// construct a call to this candidate.
    1584             :     unsigned CallConstructionID;
    1585             : 
    1586             :     /// \brief Represents the specific instructions that must be emitted to
    1587             :     /// construct a frame for this candidate's outlined function.
    1588             :     unsigned FrameConstructionID;
    1589             : 
    1590         137 :     MachineOutlinerInfo() {}
    1591             :     MachineOutlinerInfo(unsigned CallOverhead, unsigned FrameOverhead,
    1592             :                         unsigned CallConstructionID,
    1593             :                         unsigned FrameConstructionID)
    1594             :         : CallOverhead(CallOverhead), FrameOverhead(FrameOverhead),
    1595             :           CallConstructionID(CallConstructionID),
    1596             :           FrameConstructionID(FrameConstructionID) {}
    1597             :   };
    1598             : 
    1599             :   /// \brief Returns a \p MachineOutlinerInfo struct containing target-specific
    1600             :   /// information for a set of outlining candidates.
    1601           0 :   virtual MachineOutlinerInfo getOutlininingCandidateInfo(
    1602             :       std::vector<
    1603             :           std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
    1604             :           &RepeatedSequenceLocs) const {
    1605           0 :     llvm_unreachable(
    1606             :         "Target didn't implement TargetInstrInfo::getOutliningOverhead!");
    1607             :   }
    1608             : 
    1609             :   /// Represents how an instruction should be mapped by the outliner.
    1610             :   /// \p Legal instructions are those which are safe to outline.
    1611             :   /// \p Illegal instructions are those which cannot be outlined.
    1612             :   /// \p Invisible instructions are instructions which can be outlined, but
    1613             :   /// shouldn't actually impact the outlining result.
    1614             :   enum MachineOutlinerInstrType { Legal, Illegal, Invisible };
    1615             : 
    1616             :   /// Returns how or if \p MI should be outlined.
    1617             :   virtual MachineOutlinerInstrType
    1618           0 :   getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
    1619           0 :     llvm_unreachable(
    1620             :         "Target didn't implement TargetInstrInfo::getOutliningType!");
    1621             :   }
    1622             : 
    1623             :   /// \brief Returns target-defined flags defining properties of the MBB for
    1624             :   /// the outliner.
    1625          20 :   virtual unsigned getMachineOutlinerMBBFlags(MachineBasicBlock &MBB) const {
    1626          20 :     return 0x0;
    1627             :   }
    1628             : 
    1629             :   /// Insert a custom epilogue for outlined functions.
    1630             :   /// This may be empty, in which case no epilogue or return statement will be
    1631             :   /// emitted.
    1632           0 :   virtual void insertOutlinerEpilogue(MachineBasicBlock &MBB,
    1633             :                                       MachineFunction &MF,
    1634             :                                       const MachineOutlinerInfo &MInfo) const {
    1635           0 :     llvm_unreachable(
    1636             :         "Target didn't implement TargetInstrInfo::insertOutlinerEpilogue!");
    1637             :   }
    1638             : 
    1639             :   /// Insert a call to an outlined function into the program.
    1640             :   /// Returns an iterator to the spot where we inserted the call. This must be
    1641             :   /// implemented by the target.
    1642             :   virtual MachineBasicBlock::iterator
    1643           0 :   insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
    1644             :                      MachineBasicBlock::iterator &It, MachineFunction &MF,
    1645             :                      const MachineOutlinerInfo &MInfo) const {
    1646           0 :     llvm_unreachable(
    1647             :         "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
    1648             :   }
    1649             : 
    1650             :   /// Insert a custom prologue for outlined functions.
    1651             :   /// This may be empty, in which case no prologue will be emitted.
    1652           0 :   virtual void insertOutlinerPrologue(MachineBasicBlock &MBB,
    1653             :                                       MachineFunction &MF,
    1654             :                                       const MachineOutlinerInfo &MInfo) const {
    1655           0 :     llvm_unreachable(
    1656             :         "Target didn't implement TargetInstrInfo::insertOutlinerPrologue!");
    1657             :   }
    1658             : 
    1659             :   /// Return true if the function can safely be outlined from.
    1660             :   /// A function \p MF is considered safe for outlining if an outlined function
    1661             :   /// produced from instructions in F will produce a program which produces the
    1662             :   /// same output for any set of given inputs.
    1663           0 :   virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
    1664             :                                            bool OutlineFromLinkOnceODRs) const {
    1665           0 :     llvm_unreachable("Target didn't implement "
    1666             :                      "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
    1667             :   }
    1668             : 
    1669             : private:
    1670             :   unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
    1671             :   unsigned CatchRetOpcode;
    1672             :   unsigned ReturnOpcode;
    1673             : };
    1674             : 
    1675             : /// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
    1676             : template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
    1677             :   using RegInfo = DenseMapInfo<unsigned>;
    1678             : 
    1679             :   static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
    1680             :     return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
    1681             :                                           RegInfo::getEmptyKey());
    1682             :   }
    1683             : 
    1684             :   static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
    1685             :     return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
    1686             :                                           RegInfo::getTombstoneKey());
    1687             :   }
    1688             : 
    1689             :   /// \brief Reuse getHashValue implementation from
    1690             :   /// std::pair<unsigned, unsigned>.
    1691             :   static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
    1692     2075776 :     std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
    1693     2075776 :     return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
    1694             :   }
    1695             : 
    1696             :   static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
    1697             :                       const TargetInstrInfo::RegSubRegPair &RHS) {
    1698    13868229 :     return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
    1699     5393116 :            RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
    1700             :   }
    1701             : };
    1702             : 
    1703             : } // end namespace llvm
    1704             : 
    1705             : #endif // LLVM_TARGET_TARGETINSTRINFO_H

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