LCOV - code coverage report
Current view: top level - include/llvm/CodeGen - TargetInstrInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 104 208 50.0 %
Date: 2018-07-13 00:08:38 Functions: 44 98 44.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file describes the target machine instruction set to the code generator.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_TARGET_TARGETINSTRINFO_H
      15             : #define LLVM_TARGET_TARGETINSTRINFO_H
      16             : 
      17             : #include "llvm/ADT/ArrayRef.h"
      18             : #include "llvm/ADT/DenseMap.h"
      19             : #include "llvm/ADT/DenseMapInfo.h"
      20             : #include "llvm/ADT/None.h"
      21             : #include "llvm/CodeGen/LiveRegUnits.h"
      22             : #include "llvm/CodeGen/MachineBasicBlock.h"
      23             : #include "llvm/CodeGen/MachineCombinerPattern.h"
      24             : #include "llvm/CodeGen/MachineFunction.h"
      25             : #include "llvm/CodeGen/MachineInstr.h"
      26             : #include "llvm/CodeGen/MachineLoopInfo.h"
      27             : #include "llvm/CodeGen/MachineOperand.h"
      28             : #include "llvm/CodeGen/MachineOutliner.h"
      29             : #include "llvm/CodeGen/PseudoSourceValue.h"
      30             : #include "llvm/MC/MCInstrInfo.h"
      31             : #include "llvm/Support/BranchProbability.h"
      32             : #include "llvm/Support/ErrorHandling.h"
      33             : #include <cassert>
      34             : #include <cstddef>
      35             : #include <cstdint>
      36             : #include <utility>
      37             : #include <vector>
      38             : 
      39             : namespace llvm {
      40             : 
      41             : class DFAPacketizer;
      42             : class InstrItineraryData;
      43             : class LiveIntervals;
      44             : class LiveVariables;
      45             : class MachineMemOperand;
      46             : class MachineRegisterInfo;
      47             : class MCAsmInfo;
      48             : class MCInst;
      49             : struct MCSchedModel;
      50             : class Module;
      51             : class ScheduleDAG;
      52             : class ScheduleHazardRecognizer;
      53             : class SDNode;
      54             : class SelectionDAG;
      55             : class RegScavenger;
      56             : class TargetRegisterClass;
      57             : class TargetRegisterInfo;
      58             : class TargetSchedModel;
      59             : class TargetSubtargetInfo;
      60             : 
      61             : template <class T> class SmallVectorImpl;
      62             : 
      63             : //---------------------------------------------------------------------------
      64             : ///
      65             : /// TargetInstrInfo - Interface to description of machine instruction set
      66             : ///
      67             : class TargetInstrInfo : public MCInstrInfo {
      68             : public:
      69             :   TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
      70             :                   unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
      71       35315 :       : CallFrameSetupOpcode(CFSetupOpcode),
      72             :         CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
      73       35315 :         ReturnOpcode(ReturnOpcode) {}
      74             :   TargetInstrInfo(const TargetInstrInfo &) = delete;
      75             :   TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
      76             :   virtual ~TargetInstrInfo();
      77             : 
      78             :   static bool isGenericOpcode(unsigned Opc) {
      79             :     return Opc <= TargetOpcode::GENERIC_OP_END;
      80             :   }
      81             : 
      82             :   /// Given a machine instruction descriptor, returns the register
      83             :   /// class constraint for OpNum, or NULL.
      84             :   const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
      85             :                                          const TargetRegisterInfo *TRI,
      86             :                                          const MachineFunction &MF) const;
      87             : 
      88             :   /// Return true if the instruction is trivially rematerializable, meaning it
      89             :   /// has no side effects and requires no operands that aren't always available.
      90             :   /// This means the only allowed uses are constants and unallocatable physical
      91             :   /// registers so that the instructions result is independent of the place
      92             :   /// in the function.
      93      842334 :   bool isTriviallyReMaterializable(const MachineInstr &MI,
      94             :                                    AliasAnalysis *AA = nullptr) const {
      95     2526708 :     return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
      96     1324114 :            (MI.getDesc().isRematerializable() &&
      97      772754 :             (isReallyTriviallyReMaterializable(MI, AA) ||
      98     1133012 :              isReallyTriviallyReMaterializableGeneric(MI, AA)));
      99             :   }
     100             : 
     101             : protected:
     102             :   /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
     103             :   /// set, this hook lets the target specify whether the instruction is actually
     104             :   /// trivially rematerializable, taking into consideration its operands. This
     105             :   /// predicate must return false if the instruction has any side effects other
     106             :   /// than producing a value, or if it requres any address registers that are
     107             :   /// not always available.
     108             :   /// Requirements must be check as stated in isTriviallyReMaterializable() .
     109       37582 :   virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
     110             :                                                  AliasAnalysis *AA) const {
     111       37582 :     return false;
     112             :   }
     113             : 
     114             :   /// This method commutes the operands of the given machine instruction MI.
     115             :   /// The operands to be commuted are specified by their indices OpIdx1 and
     116             :   /// OpIdx2.
     117             :   ///
     118             :   /// If a target has any instructions that are commutable but require
     119             :   /// converting to different instructions or making non-trivial changes
     120             :   /// to commute them, this method can be overloaded to do that.
     121             :   /// The default implementation simply swaps the commutable operands.
     122             :   ///
     123             :   /// If NewMI is false, MI is modified in place and returned; otherwise, a
     124             :   /// new machine instruction is created and returned.
     125             :   ///
     126             :   /// Do not call this method for a non-commutable instruction.
     127             :   /// Even though the instruction is commutable, the method may still
     128             :   /// fail to commute the operands, null pointer is returned in such cases.
     129             :   virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
     130             :                                                unsigned OpIdx1,
     131             :                                                unsigned OpIdx2) const;
     132             : 
     133             :   /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
     134             :   /// operand indices to (ResultIdx1, ResultIdx2).
     135             :   /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
     136             :   /// predefined to some indices or be undefined (designated by the special
     137             :   /// value 'CommuteAnyOperandIndex').
     138             :   /// The predefined result indices cannot be re-defined.
     139             :   /// The function returns true iff after the result pair redefinition
     140             :   /// the fixed result pair is equal to or equivalent to the source pair of
     141             :   /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
     142             :   /// the pairs (x,y) and (y,x) are equivalent.
     143             :   static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
     144             :                                    unsigned CommutableOpIdx1,
     145             :                                    unsigned CommutableOpIdx2);
     146             : 
     147             : private:
     148             :   /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
     149             :   /// set and the target hook isReallyTriviallyReMaterializable returns false,
     150             :   /// this function does target-independent tests to determine if the
     151             :   /// instruction is really trivially rematerializable.
     152             :   bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
     153             :                                                 AliasAnalysis *AA) const;
     154             : 
     155             : public:
     156             :   /// These methods return the opcode of the frame setup/destroy instructions
     157             :   /// if they exist (-1 otherwise).  Some targets use pseudo instructions in
     158             :   /// order to abstract away the difference between operating with a frame
     159             :   /// pointer and operating without, through the use of these two instructions.
     160             :   ///
     161             :   unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
     162             :   unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
     163             : 
     164             :   /// Returns true if the argument is a frame pseudo instruction.
     165             :   bool isFrameInstr(const MachineInstr &I) const {
     166    21144813 :     return I.getOpcode() == getCallFrameSetupOpcode() ||
     167     6881241 :            I.getOpcode() == getCallFrameDestroyOpcode();
     168             :   }
     169             : 
     170             :   /// Returns true if the argument is a frame setup pseudo instruction.
     171             :   bool isFrameSetup(const MachineInstr &I) const {
     172      811364 :     return I.getOpcode() == getCallFrameSetupOpcode();
     173             :   }
     174             : 
     175             :   /// Returns size of the frame associated with the given frame instruction.
     176             :   /// For frame setup instruction this is frame that is set up space set up
     177             :   /// after the instruction. For frame destroy instruction this is the frame
     178             :   /// freed by the caller.
     179             :   /// Note, in some cases a call frame (or a part of it) may be prepared prior
     180             :   /// to the frame setup instruction. It occurs in the calls that involve
     181             :   /// inalloca arguments. This function reports only the size of the frame part
     182             :   /// that is set up between the frame setup and destroy pseudo instructions.
     183             :   int64_t getFrameSize(const MachineInstr &I) const {
     184             :     assert(isFrameInstr(I) && "Not a frame instruction");
     185             :     assert(I.getOperand(0).getImm() >= 0);
     186      886685 :     return I.getOperand(0).getImm();
     187             :   }
     188             : 
     189             :   /// Returns the total frame size, which is made up of the space set up inside
     190             :   /// the pair of frame start-stop instructions and the space that is set up
     191             :   /// prior to the pair.
     192             :   int64_t getFrameTotalSize(const MachineInstr &I) const {
     193      231268 :     if (isFrameSetup(I)) {
     194             :       assert(I.getOperand(1).getImm() >= 0 &&
     195             :              "Frame size must not be negative");
     196      115634 :       return getFrameSize(I) + I.getOperand(1).getImm();
     197             :     }
     198             :     return getFrameSize(I);
     199             :   }
     200             : 
     201             :   unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
     202             :   unsigned getReturnOpcode() const { return ReturnOpcode; }
     203             : 
     204             :   /// Returns the actual stack pointer adjustment made by an instruction
     205             :   /// as part of a call sequence. By default, only call frame setup/destroy
     206             :   /// instructions adjust the stack, but targets may want to override this
     207             :   /// to enable more fine-grained adjustment, or adjust by a different value.
     208             :   virtual int getSPAdjust(const MachineInstr &MI) const;
     209             : 
     210             :   /// Return true if the instruction is a "coalescable" extension instruction.
     211             :   /// That is, it's like a copy where it's legal for the source to overlap the
     212             :   /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
     213             :   /// expected the pre-extension value is available as a subreg of the result
     214             :   /// register. This also returns the sub-register index in SubIdx.
     215     1010830 :   virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
     216             :                                      unsigned &DstReg, unsigned &SubIdx) const {
     217     1010830 :     return false;
     218             :   }
     219             : 
     220             :   /// If the specified machine instruction is a direct
     221             :   /// load from a stack slot, return the virtual or physical register number of
     222             :   /// the destination along with the FrameIndex of the loaded stack slot.  If
     223             :   /// not, return 0.  This predicate must return 0 if the instruction has
     224             :   /// any side effects other than loading from the stack slot.
     225        1707 :   virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
     226             :                                        int &FrameIndex) const {
     227        1707 :     return 0;
     228             :   }
     229             : 
     230             :   /// Optional extension of isLoadFromStackSlot that returns the number of
     231             :   /// bytes loaded from the stack. This must be implemented if a backend
     232             :   /// supports partial stack slot spills/loads to further disambiguate
     233             :   /// what the load does.
     234       15077 :   virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
     235             :                                        int &FrameIndex,
     236             :                                        unsigned &MemBytes) const {
     237       15077 :     MemBytes = 0;
     238       15077 :     return isLoadFromStackSlot(MI, FrameIndex);
     239             :   }
     240             : 
     241             :   /// Check for post-frame ptr elimination stack locations as well.
     242             :   /// This uses a heuristic so it isn't reliable for correctness.
     243      785231 :   virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
     244             :                                              int &FrameIndex) const {
     245      785231 :     return 0;
     246             :   }
     247             : 
     248             :   /// If the specified machine instruction has a load from a stack slot,
     249             :   /// return true along with the FrameIndex of the loaded stack slot and the
     250             :   /// machine mem operand containing the reference.
     251             :   /// If not, return false.  Unlike isLoadFromStackSlot, this returns true for
     252             :   /// any instructions that loads from the stack.  This is just a hint, as some
     253             :   /// cases may be missed.
     254             :   virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
     255             :                                     const MachineMemOperand *&MMO,
     256             :                                     int &FrameIndex) const;
     257             : 
     258             :   /// If the specified machine instruction is a direct
     259             :   /// store to a stack slot, return the virtual or physical register number of
     260             :   /// the source reg along with the FrameIndex of the loaded stack slot.  If
     261             :   /// not, return 0.  This predicate must return 0 if the instruction has
     262             :   /// any side effects other than storing to the stack slot.
     263        1030 :   virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
     264             :                                       int &FrameIndex) const {
     265        1030 :     return 0;
     266             :   }
     267             : 
     268             :   /// Optional extension of isStoreToStackSlot that returns the number of
     269             :   /// bytes stored to the stack. This must be implemented if a backend
     270             :   /// supports partial stack slot spills/loads to further disambiguate
     271             :   /// what the store does.
     272        1261 :   virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
     273             :                                       int &FrameIndex,
     274             :                                       unsigned &MemBytes) const {
     275        1261 :     MemBytes = 0;
     276        1261 :     return isStoreToStackSlot(MI, FrameIndex);
     277             :   }
     278             : 
     279             :   /// Check for post-frame ptr elimination stack locations as well.
     280             :   /// This uses a heuristic, so it isn't reliable for correctness.
     281      765721 :   virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
     282             :                                             int &FrameIndex) const {
     283      765721 :     return 0;
     284             :   }
     285             : 
     286             :   /// If the specified machine instruction has a store to a stack slot,
     287             :   /// return true along with the FrameIndex of the loaded stack slot and the
     288             :   /// machine mem operand containing the reference.
     289             :   /// If not, return false.  Unlike isStoreToStackSlot,
     290             :   /// this returns true for any instructions that stores to the
     291             :   /// stack.  This is just a hint, as some cases may be missed.
     292             :   virtual bool hasStoreToStackSlot(const MachineInstr &MI,
     293             :                                    const MachineMemOperand *&MMO,
     294             :                                    int &FrameIndex) const;
     295             : 
     296             :   /// Return true if the specified machine instruction
     297             :   /// is a copy of one stack slot to another and has no other effect.
     298             :   /// Provide the identity of the two frame indices.
     299      806049 :   virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
     300             :                                int &SrcFrameIndex) const {
     301      806049 :     return false;
     302             :   }
     303             : 
     304             :   /// Compute the size in bytes and offset within a stack slot of a spilled
     305             :   /// register or subregister.
     306             :   ///
     307             :   /// \param [out] Size in bytes of the spilled value.
     308             :   /// \param [out] Offset in bytes within the stack slot.
     309             :   /// \returns true if both Size and Offset are successfully computed.
     310             :   ///
     311             :   /// Not all subregisters have computable spill slots. For example,
     312             :   /// subregisters registers may not be byte-sized, and a pair of discontiguous
     313             :   /// subregisters has no single offset.
     314             :   ///
     315             :   /// Targets with nontrivial bigendian implementations may need to override
     316             :   /// this, particularly to support spilled vector registers.
     317             :   virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
     318             :                                  unsigned &Size, unsigned &Offset,
     319             :                                  const MachineFunction &MF) const;
     320             : 
     321             :   /// Returns the size in bytes of the specified MachineInstr, or ~0U
     322             :   /// when this function is not implemented by a target.
     323           0 :   virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
     324           0 :     return ~0U;
     325             :   }
     326             : 
     327             :   /// Return true if the instruction is as cheap as a move instruction.
     328             :   ///
     329             :   /// Targets for different archs need to override this, and different
     330             :   /// micro-architectures can also be finely tuned inside.
     331      634883 :   virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
     332      634883 :     return MI.isAsCheapAsAMove();
     333             :   }
     334             : 
     335             :   /// Return true if the instruction should be sunk by MachineSink.
     336             :   ///
     337             :   /// MachineSink determines on its own whether the instruction is safe to sink;
     338             :   /// this gives the target a hook to override the default behavior with regards
     339             :   /// to which instructions should be sunk.
     340     2859735 :   virtual bool shouldSink(const MachineInstr &MI) const { return true; }
     341             : 
     342             :   /// Re-issue the specified 'original' instruction at the
     343             :   /// specific location targeting a new destination register.
     344             :   /// The register in Orig->getOperand(0).getReg() will be substituted by
     345             :   /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
     346             :   /// SubIdx.
     347             :   virtual void reMaterialize(MachineBasicBlock &MBB,
     348             :                              MachineBasicBlock::iterator MI, unsigned DestReg,
     349             :                              unsigned SubIdx, const MachineInstr &Orig,
     350             :                              const TargetRegisterInfo &TRI) const;
     351             : 
     352             :   /// Clones instruction or the whole instruction bundle \p Orig and
     353             :   /// insert into \p MBB before \p InsertBefore. The target may update operands
     354             :   /// that are required to be unique.
     355             :   ///
     356             :   /// \p Orig must not return true for MachineInstr::isNotDuplicable().
     357             :   virtual MachineInstr &duplicate(MachineBasicBlock &MBB,
     358             :                                   MachineBasicBlock::iterator InsertBefore,
     359             :                                   const MachineInstr &Orig) const;
     360             : 
     361             :   /// This method must be implemented by targets that
     362             :   /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
     363             :   /// may be able to convert a two-address instruction into one or more true
     364             :   /// three-address instructions on demand.  This allows the X86 target (for
     365             :   /// example) to convert ADD and SHL instructions into LEA instructions if they
     366             :   /// would require register copies due to two-addressness.
     367             :   ///
     368             :   /// This method returns a null pointer if the transformation cannot be
     369             :   /// performed, otherwise it returns the last new instruction.
     370             :   ///
     371           0 :   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
     372             :                                               MachineInstr &MI,
     373             :                                               LiveVariables *LV) const {
     374           0 :     return nullptr;
     375             :   }
     376             : 
     377             :   // This constant can be used as an input value of operand index passed to
     378             :   // the method findCommutedOpIndices() to tell the method that the
     379             :   // corresponding operand index is not pre-defined and that the method
     380             :   // can pick any commutable operand.
     381             :   static const unsigned CommuteAnyOperandIndex = ~0U;
     382             : 
     383             :   /// This method commutes the operands of the given machine instruction MI.
     384             :   ///
     385             :   /// The operands to be commuted are specified by their indices OpIdx1 and
     386             :   /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
     387             :   /// 'CommuteAnyOperandIndex', which means that the method is free to choose
     388             :   /// any arbitrarily chosen commutable operand. If both arguments are set to
     389             :   /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
     390             :   /// operands; then commutes them if such operands could be found.
     391             :   ///
     392             :   /// If NewMI is false, MI is modified in place and returned; otherwise, a
     393             :   /// new machine instruction is created and returned.
     394             :   ///
     395             :   /// Do not call this method for a non-commutable instruction or
     396             :   /// for non-commuable operands.
     397             :   /// Even though the instruction is commutable, the method may still
     398             :   /// fail to commute the operands, null pointer is returned in such cases.
     399             :   MachineInstr *
     400             :   commuteInstruction(MachineInstr &MI, bool NewMI = false,
     401             :                      unsigned OpIdx1 = CommuteAnyOperandIndex,
     402             :                      unsigned OpIdx2 = CommuteAnyOperandIndex) const;
     403             : 
     404             :   /// Returns true iff the routine could find two commutable operands in the
     405             :   /// given machine instruction.
     406             :   /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
     407             :   /// If any of the INPUT values is set to the special value
     408             :   /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
     409             :   /// operand, then returns its index in the corresponding argument.
     410             :   /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
     411             :   /// looks for 2 commutable operands.
     412             :   /// If INPUT values refer to some operands of MI, then the method simply
     413             :   /// returns true if the corresponding operands are commutable and returns
     414             :   /// false otherwise.
     415             :   ///
     416             :   /// For example, calling this method this way:
     417             :   ///     unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
     418             :   ///     findCommutedOpIndices(MI, Op1, Op2);
     419             :   /// can be interpreted as a query asking to find an operand that would be
     420             :   /// commutable with the operand#1.
     421             :   virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
     422             :                                      unsigned &SrcOpIdx2) const;
     423             : 
     424             :   /// A pair composed of a register and a sub-register index.
     425             :   /// Used to give some type checking when modeling Reg:SubReg.
     426             :   struct RegSubRegPair {
     427             :     unsigned Reg;
     428             :     unsigned SubReg;
     429             : 
     430             :     RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
     431     2819068 :         : Reg(Reg), SubReg(SubReg) {}
     432             :   };
     433             : 
     434             :   /// A pair composed of a pair of a register and a sub-register index,
     435             :   /// and another sub-register index.
     436             :   /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
     437             :   struct RegSubRegPairAndIdx : RegSubRegPair {
     438             :     unsigned SubIdx;
     439             : 
     440             :     RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
     441             :                         unsigned SubIdx = 0)
     442     1432672 :         : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
     443             :   };
     444             : 
     445             :   /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
     446             :   /// and \p DefIdx.
     447             :   /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
     448             :   /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
     449             :   /// flag are not added to this list.
     450             :   /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
     451             :   /// two elements:
     452             :   /// - %1:sub1, sub0
     453             :   /// - %2<:0>, sub1
     454             :   ///
     455             :   /// \returns true if it is possible to build such an input sequence
     456             :   /// with the pair \p MI, \p DefIdx. False otherwise.
     457             :   ///
     458             :   /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
     459             :   ///
     460             :   /// \note The generic implementation does not provide any support for
     461             :   /// MI.isRegSequenceLike(). In other words, one has to override
     462             :   /// getRegSequenceLikeInputs for target specific instructions.
     463             :   bool
     464             :   getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
     465             :                        SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
     466             : 
     467             :   /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
     468             :   /// and \p DefIdx.
     469             :   /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
     470             :   /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
     471             :   /// - %1:sub1, sub0
     472             :   ///
     473             :   /// \returns true if it is possible to build such an input sequence
     474             :   /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
     475             :   /// False otherwise.
     476             :   ///
     477             :   /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
     478             :   ///
     479             :   /// \note The generic implementation does not provide any support for
     480             :   /// MI.isExtractSubregLike(). In other words, one has to override
     481             :   /// getExtractSubregLikeInputs for target specific instructions.
     482             :   bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
     483             :                               RegSubRegPairAndIdx &InputReg) const;
     484             : 
     485             :   /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
     486             :   /// and \p DefIdx.
     487             :   /// \p [out] BaseReg and \p [out] InsertedReg contain
     488             :   /// the equivalent inputs of INSERT_SUBREG.
     489             :   /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
     490             :   /// - BaseReg: %0:sub0
     491             :   /// - InsertedReg: %1:sub1, sub3
     492             :   ///
     493             :   /// \returns true if it is possible to build such an input sequence
     494             :   /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
     495             :   /// False otherwise.
     496             :   ///
     497             :   /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
     498             :   ///
     499             :   /// \note The generic implementation does not provide any support for
     500             :   /// MI.isInsertSubregLike(). In other words, one has to override
     501             :   /// getInsertSubregLikeInputs for target specific instructions.
     502             :   bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
     503             :                              RegSubRegPair &BaseReg,
     504             :                              RegSubRegPairAndIdx &InsertedReg) const;
     505             : 
     506             :   /// Return true if two machine instructions would produce identical values.
     507             :   /// By default, this is only true when the two instructions
     508             :   /// are deemed identical except for defs. If this function is called when the
     509             :   /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
     510             :   /// aggressive checks.
     511             :   virtual bool produceSameValue(const MachineInstr &MI0,
     512             :                                 const MachineInstr &MI1,
     513             :                                 const MachineRegisterInfo *MRI = nullptr) const;
     514             : 
     515             :   /// \returns true if a branch from an instruction with opcode \p BranchOpc
     516             :   ///  bytes is capable of jumping to a position \p BrOffset bytes away.
     517           0 :   virtual bool isBranchOffsetInRange(unsigned BranchOpc,
     518             :                                      int64_t BrOffset) const {
     519           0 :     llvm_unreachable("target did not implement");
     520             :   }
     521             : 
     522             :   /// \returns The block that branch instruction \p MI jumps to.
     523           0 :   virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
     524           0 :     llvm_unreachable("target did not implement");
     525             :   }
     526             : 
     527             :   /// Insert an unconditional indirect branch at the end of \p MBB to \p
     528             :   /// NewDestBB.  \p BrOffset indicates the offset of \p NewDestBB relative to
     529             :   /// the offset of the position to insert the new branch.
     530             :   ///
     531             :   /// \returns The number of bytes added to the block.
     532           0 :   virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB,
     533             :                                         MachineBasicBlock &NewDestBB,
     534             :                                         const DebugLoc &DL,
     535             :                                         int64_t BrOffset = 0,
     536             :                                         RegScavenger *RS = nullptr) const {
     537           0 :     llvm_unreachable("target did not implement");
     538             :   }
     539             : 
     540             :   /// Analyze the branching code at the end of MBB, returning
     541             :   /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
     542             :   /// implemented for a target).  Upon success, this returns false and returns
     543             :   /// with the following information in various cases:
     544             :   ///
     545             :   /// 1. If this block ends with no branches (it just falls through to its succ)
     546             :   ///    just return false, leaving TBB/FBB null.
     547             :   /// 2. If this block ends with only an unconditional branch, it sets TBB to be
     548             :   ///    the destination block.
     549             :   /// 3. If this block ends with a conditional branch and it falls through to a
     550             :   ///    successor block, it sets TBB to be the branch destination block and a
     551             :   ///    list of operands that evaluate the condition. These operands can be
     552             :   ///    passed to other TargetInstrInfo methods to create new branches.
     553             :   /// 4. If this block ends with a conditional branch followed by an
     554             :   ///    unconditional branch, it returns the 'true' destination in TBB, the
     555             :   ///    'false' destination in FBB, and a list of operands that evaluate the
     556             :   ///    condition.  These operands can be passed to other TargetInstrInfo
     557             :   ///    methods to create new branches.
     558             :   ///
     559             :   /// Note that removeBranch and insertBranch must be implemented to support
     560             :   /// cases where this method returns success.
     561             :   ///
     562             :   /// If AllowModify is true, then this routine is allowed to modify the basic
     563             :   /// block (e.g. delete instructions after the unconditional branch).
     564             :   ///
     565             :   /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
     566             :   /// before calling this function.
     567           0 :   virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
     568             :                              MachineBasicBlock *&FBB,
     569             :                              SmallVectorImpl<MachineOperand> &Cond,
     570             :                              bool AllowModify = false) const {
     571           0 :     return true;
     572             :   }
     573             : 
     574             :   /// Represents a predicate at the MachineFunction level.  The control flow a
     575             :   /// MachineBranchPredicate represents is:
     576             :   ///
     577             :   ///  Reg = LHS `Predicate` RHS         == ConditionDef
     578             :   ///  if Reg then goto TrueDest else goto FalseDest
     579             :   ///
     580             :   struct MachineBranchPredicate {
     581             :     enum ComparePredicate {
     582             :       PRED_EQ,     // True if two values are equal
     583             :       PRED_NE,     // True if two values are not equal
     584             :       PRED_INVALID // Sentinel value
     585             :     };
     586             : 
     587             :     ComparePredicate Predicate = PRED_INVALID;
     588             :     MachineOperand LHS = MachineOperand::CreateImm(0);
     589             :     MachineOperand RHS = MachineOperand::CreateImm(0);
     590             :     MachineBasicBlock *TrueDest = nullptr;
     591             :     MachineBasicBlock *FalseDest = nullptr;
     592             :     MachineInstr *ConditionDef = nullptr;
     593             : 
     594             :     /// SingleUseCondition is true if ConditionDef is dead except for the
     595             :     /// branch(es) at the end of the basic block.
     596             :     ///
     597             :     bool SingleUseCondition = false;
     598             : 
     599         122 :     explicit MachineBranchPredicate() = default;
     600             :   };
     601             : 
     602             :   /// Analyze the branching code at the end of MBB and parse it into the
     603             :   /// MachineBranchPredicate structure if possible.  Returns false on success
     604             :   /// and true on failure.
     605             :   ///
     606             :   /// If AllowModify is true, then this routine is allowed to modify the basic
     607             :   /// block (e.g. delete instructions after the unconditional branch).
     608             :   ///
     609           0 :   virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
     610             :                                       MachineBranchPredicate &MBP,
     611             :                                       bool AllowModify = false) const {
     612           0 :     return true;
     613             :   }
     614             : 
     615             :   /// Remove the branching code at the end of the specific MBB.
     616             :   /// This is only invoked in cases where AnalyzeBranch returns success. It
     617             :   /// returns the number of instructions that were removed.
     618             :   /// If \p BytesRemoved is non-null, report the change in code size from the
     619             :   /// removed instructions.
     620           0 :   virtual unsigned removeBranch(MachineBasicBlock &MBB,
     621             :                                 int *BytesRemoved = nullptr) const {
     622           0 :     llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
     623             :   }
     624             : 
     625             :   /// Insert branch code into the end of the specified MachineBasicBlock. The
     626             :   /// operands to this method are the same as those returned by AnalyzeBranch.
     627             :   /// This is only invoked in cases where AnalyzeBranch returns success. It
     628             :   /// returns the number of instructions inserted. If \p BytesAdded is non-null,
     629             :   /// report the change in code size from the added instructions.
     630             :   ///
     631             :   /// It is also invoked by tail merging to add unconditional branches in
     632             :   /// cases where AnalyzeBranch doesn't apply because there was no original
     633             :   /// branch to analyze.  At least this much must be implemented, else tail
     634             :   /// merging needs to be disabled.
     635             :   ///
     636             :   /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
     637             :   /// before calling this function.
     638           0 :   virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
     639             :                                 MachineBasicBlock *FBB,
     640             :                                 ArrayRef<MachineOperand> Cond,
     641             :                                 const DebugLoc &DL,
     642             :                                 int *BytesAdded = nullptr) const {
     643           0 :     llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
     644             :   }
     645             : 
     646             :   unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
     647             :                                      MachineBasicBlock *DestBB,
     648             :                                      const DebugLoc &DL,
     649             :                                      int *BytesAdded = nullptr) const {
     650           5 :     return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
     651           5 :                         BytesAdded);
     652             :   }
     653             : 
     654             :   /// Analyze the loop code, return true if it cannot be understoo. Upon
     655             :   /// success, this function returns false and returns information about the
     656             :   /// induction variable and compare instruction used at the end.
     657           0 :   virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
     658             :                            MachineInstr *&CmpInst) const {
     659           0 :     return true;
     660             :   }
     661             : 
     662             :   /// Generate code to reduce the loop iteration by one and check if the loop
     663             :   /// is finished.  Return the value/register of the new loop count.  We need
     664             :   /// this function when peeling off one or more iterations of a loop. This
     665             :   /// function assumes the nth iteration is peeled first.
     666           0 :   virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar,
     667             :                                    MachineInstr &Cmp,
     668             :                                    SmallVectorImpl<MachineOperand> &Cond,
     669             :                                    SmallVectorImpl<MachineInstr *> &PrevInsts,
     670             :                                    unsigned Iter, unsigned MaxIter) const {
     671           0 :     llvm_unreachable("Target didn't implement ReduceLoopCount");
     672             :   }
     673             : 
     674             :   /// Delete the instruction OldInst and everything after it, replacing it with
     675             :   /// an unconditional branch to NewDest. This is used by the tail merging pass.
     676             :   virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
     677             :                                        MachineBasicBlock *NewDest) const;
     678             : 
     679             :   /// Return true if it's legal to split the given basic
     680             :   /// block at the specified instruction (i.e. instruction would be the start
     681             :   /// of a new basic block).
     682        3445 :   virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
     683             :                                    MachineBasicBlock::iterator MBBI) const {
     684        3445 :     return true;
     685             :   }
     686             : 
     687             :   /// Return true if it's profitable to predicate
     688             :   /// instructions with accumulated instruction latency of "NumCycles"
     689             :   /// of the specified basic block, where the probability of the instructions
     690             :   /// being executed is given by Probability, and Confidence is a measure
     691             :   /// of our confidence that it will be properly predicted.
     692           0 :   virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
     693             :                                    unsigned ExtraPredCycles,
     694             :                                    BranchProbability Probability) const {
     695           0 :     return false;
     696             :   }
     697             : 
     698             :   /// Second variant of isProfitableToIfCvt. This one
     699             :   /// checks for the case where two basic blocks from true and false path
     700             :   /// of a if-then-else (diamond) are predicated on mutally exclusive
     701             :   /// predicates, where the probability of the true path being taken is given
     702             :   /// by Probability, and Confidence is a measure of our confidence that it
     703             :   /// will be properly predicted.
     704           0 :   virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
     705             :                                    unsigned ExtraTCycles,
     706             :                                    MachineBasicBlock &FMBB, unsigned NumFCycles,
     707             :                                    unsigned ExtraFCycles,
     708             :                                    BranchProbability Probability) const {
     709           0 :     return false;
     710             :   }
     711             : 
     712             :   /// Return true if it's profitable for if-converter to duplicate instructions
     713             :   /// of specified accumulated instruction latencies in the specified MBB to
     714             :   /// enable if-conversion.
     715             :   /// The probability of the instructions being executed is given by
     716             :   /// Probability, and Confidence is a measure of our confidence that it
     717             :   /// will be properly predicted.
     718           0 :   virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
     719             :                                          unsigned NumCycles,
     720             :                                          BranchProbability Probability) const {
     721           0 :     return false;
     722             :   }
     723             : 
     724             :   /// Return true if it's profitable to unpredicate
     725             :   /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
     726             :   /// exclusive predicates.
     727             :   /// e.g.
     728             :   ///   subeq  r0, r1, #1
     729             :   ///   addne  r0, r1, #1
     730             :   /// =>
     731             :   ///   sub    r0, r1, #1
     732             :   ///   addne  r0, r1, #1
     733             :   ///
     734             :   /// This may be profitable is conditional instructions are always executed.
     735          18 :   virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
     736             :                                          MachineBasicBlock &FMBB) const {
     737          18 :     return false;
     738             :   }
     739             : 
     740             :   /// Return true if it is possible to insert a select
     741             :   /// instruction that chooses between TrueReg and FalseReg based on the
     742             :   /// condition code in Cond.
     743             :   ///
     744             :   /// When successful, also return the latency in cycles from TrueReg,
     745             :   /// FalseReg, and Cond to the destination register. In most cases, a select
     746             :   /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
     747             :   ///
     748             :   /// Some x86 implementations have 2-cycle cmov instructions.
     749             :   ///
     750             :   /// @param MBB         Block where select instruction would be inserted.
     751             :   /// @param Cond        Condition returned by AnalyzeBranch.
     752             :   /// @param TrueReg     Virtual register to select when Cond is true.
     753             :   /// @param FalseReg    Virtual register to select when Cond is false.
     754             :   /// @param CondCycles  Latency from Cond+Branch to select output.
     755             :   /// @param TrueCycles  Latency from TrueReg to select output.
     756             :   /// @param FalseCycles Latency from FalseReg to select output.
     757           0 :   virtual bool canInsertSelect(const MachineBasicBlock &MBB,
     758             :                                ArrayRef<MachineOperand> Cond, unsigned TrueReg,
     759             :                                unsigned FalseReg, int &CondCycles,
     760             :                                int &TrueCycles, int &FalseCycles) const {
     761           0 :     return false;
     762             :   }
     763             : 
     764             :   /// Insert a select instruction into MBB before I that will copy TrueReg to
     765             :   /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
     766             :   ///
     767             :   /// This function can only be called after canInsertSelect() returned true.
     768             :   /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
     769             :   /// that the same flags or registers required by Cond are available at the
     770             :   /// insertion point.
     771             :   ///
     772             :   /// @param MBB      Block where select instruction should be inserted.
     773             :   /// @param I        Insertion point.
     774             :   /// @param DL       Source location for debugging.
     775             :   /// @param DstReg   Virtual register to be defined by select instruction.
     776             :   /// @param Cond     Condition as computed by AnalyzeBranch.
     777             :   /// @param TrueReg  Virtual register to copy when Cond is true.
     778             :   /// @param FalseReg Virtual register to copy when Cons is false.
     779           0 :   virtual void insertSelect(MachineBasicBlock &MBB,
     780             :                             MachineBasicBlock::iterator I, const DebugLoc &DL,
     781             :                             unsigned DstReg, ArrayRef<MachineOperand> Cond,
     782             :                             unsigned TrueReg, unsigned FalseReg) const {
     783           0 :     llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
     784             :   }
     785             : 
     786             :   /// Analyze the given select instruction, returning true if
     787             :   /// it cannot be understood. It is assumed that MI->isSelect() is true.
     788             :   ///
     789             :   /// When successful, return the controlling condition and the operands that
     790             :   /// determine the true and false result values.
     791             :   ///
     792             :   ///   Result = SELECT Cond, TrueOp, FalseOp
     793             :   ///
     794             :   /// Some targets can optimize select instructions, for example by predicating
     795             :   /// the instruction defining one of the operands. Such targets should set
     796             :   /// Optimizable.
     797             :   ///
     798             :   /// @param         MI Select instruction to analyze.
     799             :   /// @param Cond    Condition controlling the select.
     800             :   /// @param TrueOp  Operand number of the value selected when Cond is true.
     801             :   /// @param FalseOp Operand number of the value selected when Cond is false.
     802             :   /// @param Optimizable Returned as true if MI is optimizable.
     803             :   /// @returns False on success.
     804         368 :   virtual bool analyzeSelect(const MachineInstr &MI,
     805             :                              SmallVectorImpl<MachineOperand> &Cond,
     806             :                              unsigned &TrueOp, unsigned &FalseOp,
     807             :                              bool &Optimizable) const {
     808             :     assert(MI.getDesc().isSelect() && "MI must be a select instruction");
     809         368 :     return true;
     810             :   }
     811             : 
     812             :   /// Given a select instruction that was understood by
     813             :   /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
     814             :   /// merging it with one of its operands. Returns NULL on failure.
     815             :   ///
     816             :   /// When successful, returns the new select instruction. The client is
     817             :   /// responsible for deleting MI.
     818             :   ///
     819             :   /// If both sides of the select can be optimized, PreferFalse is used to pick
     820             :   /// a side.
     821             :   ///
     822             :   /// @param MI          Optimizable select instruction.
     823             :   /// @param NewMIs     Set that record all MIs in the basic block up to \p
     824             :   /// MI. Has to be updated with any newly created MI or deleted ones.
     825             :   /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
     826             :   /// @returns Optimized instruction or NULL.
     827           0 :   virtual MachineInstr *optimizeSelect(MachineInstr &MI,
     828             :                                        SmallPtrSetImpl<MachineInstr *> &NewMIs,
     829             :                                        bool PreferFalse = false) const {
     830             :     // This function must be implemented if Optimizable is ever set.
     831           0 :     llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
     832             :   }
     833             : 
     834             :   /// Emit instructions to copy a pair of physical registers.
     835             :   ///
     836             :   /// This function should support copies within any legal register class as
     837             :   /// well as any cross-class copies created during instruction selection.
     838             :   ///
     839             :   /// The source and destination registers may overlap, which may require a
     840             :   /// careful implementation when multiple copy instructions are required for
     841             :   /// large registers. See for example the ARM target.
     842           0 :   virtual void copyPhysReg(MachineBasicBlock &MBB,
     843             :                            MachineBasicBlock::iterator MI, const DebugLoc &DL,
     844             :                            unsigned DestReg, unsigned SrcReg,
     845             :                            bool KillSrc) const {
     846           0 :     llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
     847             :   }
     848             : 
     849             :   /// If the specific machine instruction is a instruction that moves/copies
     850             :   /// value from one register to another register return true along with
     851             :   /// @Source machine operand and @Destination machine operand.
     852           0 :   virtual bool isCopyInstr(const MachineInstr &MI,
     853             :                            const MachineOperand *&SourceOpNum,
     854             :                            const MachineOperand *&Destination) const {
     855           0 :     return false;
     856             :   }
     857             : 
     858             :   /// Store the specified register of the given register class to the specified
     859             :   /// stack frame index. The store instruction is to be added to the given
     860             :   /// machine basic block before the specified machine instruction. If isKill
     861             :   /// is true, the register operand is the last use and must be marked kill.
     862           0 :   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
     863             :                                    MachineBasicBlock::iterator MI,
     864             :                                    unsigned SrcReg, bool isKill, int FrameIndex,
     865             :                                    const TargetRegisterClass *RC,
     866             :                                    const TargetRegisterInfo *TRI) const {
     867           0 :     llvm_unreachable("Target didn't implement "
     868             :                      "TargetInstrInfo::storeRegToStackSlot!");
     869             :   }
     870             : 
     871             :   /// Load the specified register of the given register class from the specified
     872             :   /// stack frame index. The load instruction is to be added to the given
     873             :   /// machine basic block before the specified machine instruction.
     874           0 :   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
     875             :                                     MachineBasicBlock::iterator MI,
     876             :                                     unsigned DestReg, int FrameIndex,
     877             :                                     const TargetRegisterClass *RC,
     878             :                                     const TargetRegisterInfo *TRI) const {
     879           0 :     llvm_unreachable("Target didn't implement "
     880             :                      "TargetInstrInfo::loadRegFromStackSlot!");
     881             :   }
     882             : 
     883             :   /// This function is called for all pseudo instructions
     884             :   /// that remain after register allocation. Many pseudo instructions are
     885             :   /// created to help register allocation. This is the place to convert them
     886             :   /// into real instructions. The target can edit MI in place, or it can insert
     887             :   /// new instructions and erase MI. The function should return true if
     888             :   /// anything was changed.
     889        7161 :   virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
     890             : 
     891             :   /// Check whether the target can fold a load that feeds a subreg operand
     892             :   /// (or a subreg operand that feeds a store).
     893             :   /// For example, X86 may want to return true if it can fold
     894             :   /// movl (%esp), %eax
     895             :   /// subb, %al, ...
     896             :   /// Into:
     897             :   /// subb (%esp), ...
     898             :   ///
     899             :   /// Ideally, we'd like the target implementation of foldMemoryOperand() to
     900             :   /// reject subregs - but since this behavior used to be enforced in the
     901             :   /// target-independent code, moving this responsibility to the targets
     902             :   /// has the potential of causing nasty silent breakage in out-of-tree targets.
     903        6880 :   virtual bool isSubregFoldable() const { return false; }
     904             : 
     905             :   /// Attempt to fold a load or store of the specified stack
     906             :   /// slot into the specified machine instruction for the specified operand(s).
     907             :   /// If this is possible, a new instruction is returned with the specified
     908             :   /// operand folded, otherwise NULL is returned.
     909             :   /// The new instruction is inserted before MI, and the client is responsible
     910             :   /// for removing the old instruction.
     911             :   MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
     912             :                                   int FrameIndex,
     913             :                                   LiveIntervals *LIS = nullptr) const;
     914             : 
     915             :   /// Same as the previous version except it allows folding of any load and
     916             :   /// store from / to any address, not just from a specific stack slot.
     917             :   MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
     918             :                                   MachineInstr &LoadMI,
     919             :                                   LiveIntervals *LIS = nullptr) const;
     920             : 
     921             :   /// Return true when there is potentially a faster code sequence
     922             :   /// for an instruction chain ending in \p Root. All potential patterns are
     923             :   /// returned in the \p Pattern vector. Pattern should be sorted in priority
     924             :   /// order since the pattern evaluator stops checking as soon as it finds a
     925             :   /// faster sequence.
     926             :   /// \param Root - Instruction that could be combined with one of its operands
     927             :   /// \param Patterns - Vector of possible combination patterns
     928             :   virtual bool getMachineCombinerPatterns(
     929             :       MachineInstr &Root,
     930             :       SmallVectorImpl<MachineCombinerPattern> &Patterns) const;
     931             : 
     932             :   /// Return true when a code sequence can improve throughput. It
     933             :   /// should be called only for instructions in loops.
     934             :   /// \param Pattern - combiner pattern
     935             :   virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
     936             : 
     937             :   /// Return true if the input \P Inst is part of a chain of dependent ops
     938             :   /// that are suitable for reassociation, otherwise return false.
     939             :   /// If the instruction's operands must be commuted to have a previous
     940             :   /// instruction of the same type define the first source operand, \P Commuted
     941             :   /// will be set to true.
     942             :   bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
     943             : 
     944             :   /// Return true when \P Inst is both associative and commutative.
     945           0 :   virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
     946           0 :     return false;
     947             :   }
     948             : 
     949             :   /// Return true when \P Inst has reassociable operands in the same \P MBB.
     950             :   virtual bool hasReassociableOperands(const MachineInstr &Inst,
     951             :                                        const MachineBasicBlock *MBB) const;
     952             : 
     953             :   /// Return true when \P Inst has reassociable sibling.
     954             :   bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
     955             : 
     956             :   /// When getMachineCombinerPatterns() finds patterns, this function generates
     957             :   /// the instructions that could replace the original code sequence. The client
     958             :   /// has to decide whether the actual replacement is beneficial or not.
     959             :   /// \param Root - Instruction that could be combined with one of its operands
     960             :   /// \param Pattern - Combination pattern for Root
     961             :   /// \param InsInstrs - Vector of new instructions that implement P
     962             :   /// \param DelInstrs - Old instructions, including Root, that could be
     963             :   /// replaced by InsInstr
     964             :   /// \param InstrIdxForVirtReg - map of virtual register to instruction in
     965             :   /// InsInstr that defines it
     966             :   virtual void genAlternativeCodeSequence(
     967             :       MachineInstr &Root, MachineCombinerPattern Pattern,
     968             :       SmallVectorImpl<MachineInstr *> &InsInstrs,
     969             :       SmallVectorImpl<MachineInstr *> &DelInstrs,
     970             :       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
     971             : 
     972             :   /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
     973             :   /// reduce critical path length.
     974             :   void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
     975             :                       MachineCombinerPattern Pattern,
     976             :                       SmallVectorImpl<MachineInstr *> &InsInstrs,
     977             :                       SmallVectorImpl<MachineInstr *> &DelInstrs,
     978             :                       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
     979             : 
     980             :   /// This is an architecture-specific helper function of reassociateOps.
     981             :   /// Set special operand attributes for new instructions after reassociation.
     982         270 :   virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
     983             :                                      MachineInstr &NewMI1,
     984         270 :                                      MachineInstr &NewMI2) const {}
     985             : 
     986             :   /// Return true when a target supports MachineCombiner.
     987           0 :   virtual bool useMachineCombiner() const { return false; }
     988             : 
     989             :   /// Return true if the given SDNode can be copied during scheduling
     990             :   /// even if it has glue.
     991         104 :   virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
     992             : 
     993             : protected:
     994             :   /// Target-dependent implementation for foldMemoryOperand.
     995             :   /// Target-independent code in foldMemoryOperand will
     996             :   /// take care of adding a MachineMemOperand to the newly created instruction.
     997             :   /// The instruction and any auxiliary instructions necessary will be inserted
     998             :   /// at InsertPt.
     999             :   virtual MachineInstr *
    1000        5679 :   foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
    1001             :                         ArrayRef<unsigned> Ops,
    1002             :                         MachineBasicBlock::iterator InsertPt, int FrameIndex,
    1003             :                         LiveIntervals *LIS = nullptr) const {
    1004        5679 :     return nullptr;
    1005             :   }
    1006             : 
    1007             :   /// Target-dependent implementation for foldMemoryOperand.
    1008             :   /// Target-independent code in foldMemoryOperand will
    1009             :   /// take care of adding a MachineMemOperand to the newly created instruction.
    1010             :   /// The instruction and any auxiliary instructions necessary will be inserted
    1011             :   /// at InsertPt.
    1012          27 :   virtual MachineInstr *foldMemoryOperandImpl(
    1013             :       MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
    1014             :       MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
    1015             :       LiveIntervals *LIS = nullptr) const {
    1016          27 :     return nullptr;
    1017             :   }
    1018             : 
    1019             :   /// Target-dependent implementation of getRegSequenceInputs.
    1020             :   ///
    1021             :   /// \returns true if it is possible to build the equivalent
    1022             :   /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
    1023             :   ///
    1024             :   /// \pre MI.isRegSequenceLike().
    1025             :   ///
    1026             :   /// \see TargetInstrInfo::getRegSequenceInputs.
    1027           0 :   virtual bool getRegSequenceLikeInputs(
    1028             :       const MachineInstr &MI, unsigned DefIdx,
    1029             :       SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
    1030           0 :     return false;
    1031             :   }
    1032             : 
    1033             :   /// Target-dependent implementation of getExtractSubregInputs.
    1034             :   ///
    1035             :   /// \returns true if it is possible to build the equivalent
    1036             :   /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
    1037             :   ///
    1038             :   /// \pre MI.isExtractSubregLike().
    1039             :   ///
    1040             :   /// \see TargetInstrInfo::getExtractSubregInputs.
    1041           0 :   virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
    1042             :                                           unsigned DefIdx,
    1043             :                                           RegSubRegPairAndIdx &InputReg) const {
    1044           0 :     return false;
    1045             :   }
    1046             : 
    1047             :   /// Target-dependent implementation of getInsertSubregInputs.
    1048             :   ///
    1049             :   /// \returns true if it is possible to build the equivalent
    1050             :   /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
    1051             :   ///
    1052             :   /// \pre MI.isInsertSubregLike().
    1053             :   ///
    1054             :   /// \see TargetInstrInfo::getInsertSubregInputs.
    1055             :   virtual bool
    1056           0 :   getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
    1057             :                             RegSubRegPair &BaseReg,
    1058             :                             RegSubRegPairAndIdx &InsertedReg) const {
    1059           0 :     return false;
    1060             :   }
    1061             : 
    1062             : public:
    1063             :   /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
    1064             :   /// (e.g. stack) the target returns the corresponding address space.
    1065             :   virtual unsigned
    1066      935540 :   getAddressSpaceForPseudoSourceKind(PseudoSourceValue::PSVKind Kind) const {
    1067      935540 :     return 0;
    1068             :   }
    1069             : 
    1070             :   /// unfoldMemoryOperand - Separate a single instruction which folded a load or
    1071             :   /// a store or a load and a store into two or more instruction. If this is
    1072             :   /// possible, returns true as well as the new instructions by reference.
    1073             :   virtual bool
    1074           0 :   unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
    1075             :                       bool UnfoldLoad, bool UnfoldStore,
    1076             :                       SmallVectorImpl<MachineInstr *> &NewMIs) const {
    1077           0 :     return false;
    1078             :   }
    1079             : 
    1080           0 :   virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
    1081             :                                    SmallVectorImpl<SDNode *> &NewNodes) const {
    1082           0 :     return false;
    1083             :   }
    1084             : 
    1085             :   /// Returns the opcode of the would be new
    1086             :   /// instruction after load / store are unfolded from an instruction of the
    1087             :   /// specified opcode. It returns zero if the specified unfolding is not
    1088             :   /// possible. If LoadRegIndex is non-null, it is filled in with the operand
    1089             :   /// index of the operand which will hold the register holding the loaded
    1090             :   /// value.
    1091             :   virtual unsigned
    1092         609 :   getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
    1093             :                              unsigned *LoadRegIndex = nullptr) const {
    1094         609 :     return 0;
    1095             :   }
    1096             : 
    1097             :   /// This is used by the pre-regalloc scheduler to determine if two loads are
    1098             :   /// loading from the same base address. It should only return true if the base
    1099             :   /// pointers are the same and the only differences between the two addresses
    1100             :   /// are the offset. It also returns the offsets by reference.
    1101      281039 :   virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
    1102             :                                        int64_t &Offset1,
    1103             :                                        int64_t &Offset2) const {
    1104      281039 :     return false;
    1105             :   }
    1106             : 
    1107             :   /// This is a used by the pre-regalloc scheduler to determine (in conjunction
    1108             :   /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
    1109             :   /// On some targets if two loads are loading from
    1110             :   /// addresses in the same cache line, it's better if they are scheduled
    1111             :   /// together. This function takes two integers that represent the load offsets
    1112             :   /// from the common base address. It returns true if it decides it's desirable
    1113             :   /// to schedule the two loads together. "NumLoads" is the number of loads that
    1114             :   /// have already been scheduled after Load1.
    1115           0 :   virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
    1116             :                                        int64_t Offset1, int64_t Offset2,
    1117             :                                        unsigned NumLoads) const {
    1118           0 :     return false;
    1119             :   }
    1120             : 
    1121             :   /// Get the base register and byte offset of an instruction that reads/writes
    1122             :   /// memory.
    1123           0 :   virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
    1124             :                                      int64_t &Offset,
    1125             :                                      const TargetRegisterInfo *TRI) const {
    1126           0 :     return false;
    1127             :   }
    1128             : 
    1129             :   /// Return true if the instruction contains a base register and offset. If
    1130             :   /// true, the function also sets the operand position in the instruction
    1131             :   /// for the base register and offset.
    1132           0 :   virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
    1133             :                                         unsigned &BasePos,
    1134             :                                         unsigned &OffsetPos) const {
    1135           0 :     return false;
    1136             :   }
    1137             : 
    1138             :   /// If the instruction is an increment of a constant value, return the amount.
    1139           0 :   virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
    1140           0 :     return false;
    1141             :   }
    1142             : 
    1143             :   /// Returns true if the two given memory operations should be scheduled
    1144             :   /// adjacent. Note that you have to add:
    1145             :   ///   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
    1146             :   /// or
    1147             :   ///   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
    1148             :   /// to TargetPassConfig::createMachineScheduler() to have an effect.
    1149           0 :   virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
    1150             :                                    MachineInstr &SecondLdSt, unsigned BaseReg2,
    1151             :                                    unsigned NumLoads) const {
    1152           0 :     llvm_unreachable("target did not implement shouldClusterMemOps()");
    1153             :   }
    1154             : 
    1155             :   /// Reverses the branch condition of the specified condition list,
    1156             :   /// returning false on success and true if it cannot be reversed.
    1157             :   virtual bool
    1158          19 :   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
    1159          19 :     return true;
    1160             :   }
    1161             : 
    1162             :   /// Insert a noop into the instruction stream at the specified point.
    1163             :   virtual void insertNoop(MachineBasicBlock &MBB,
    1164             :                           MachineBasicBlock::iterator MI) const;
    1165             : 
    1166             :   /// Return the noop instruction to use for a noop.
    1167             :   virtual void getNoop(MCInst &NopInst) const;
    1168             : 
    1169             :   /// Return true for post-incremented instructions.
    1170           0 :   virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
    1171             : 
    1172             :   /// Returns true if the instruction is already predicated.
    1173     3921940 :   virtual bool isPredicated(const MachineInstr &MI) const { return false; }
    1174             : 
    1175             :   /// Returns true if the instruction is a
    1176             :   /// terminator instruction that has not been predicated.
    1177             :   virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
    1178             : 
    1179             :   /// Returns true if MI is an unconditional tail call.
    1180         778 :   virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
    1181         778 :     return false;
    1182             :   }
    1183             : 
    1184             :   /// Returns true if the tail call can be made conditional on BranchCond.
    1185           0 :   virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
    1186             :                                           const MachineInstr &TailCall) const {
    1187           0 :     return false;
    1188             :   }
    1189             : 
    1190             :   /// Replace the conditional branch in MBB with a conditional tail call.
    1191           0 :   virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
    1192             :                                          SmallVectorImpl<MachineOperand> &Cond,
    1193             :                                          const MachineInstr &TailCall) const {
    1194           0 :     llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
    1195             :   }
    1196             : 
    1197             :   /// Convert the instruction into a predicated instruction.
    1198             :   /// It returns true if the operation was successful.
    1199             :   virtual bool PredicateInstruction(MachineInstr &MI,
    1200             :                                     ArrayRef<MachineOperand> Pred) const;
    1201             : 
    1202             :   /// Returns true if the first specified predicate
    1203             :   /// subsumes the second, e.g. GE subsumes GT.
    1204           0 :   virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
    1205             :                                  ArrayRef<MachineOperand> Pred2) const {
    1206           0 :     return false;
    1207             :   }
    1208             : 
    1209             :   /// If the specified instruction defines any predicate
    1210             :   /// or condition code register(s) used for predication, returns true as well
    1211             :   /// as the definition predicate(s) by reference.
    1212       11112 :   virtual bool DefinesPredicate(MachineInstr &MI,
    1213             :                                 std::vector<MachineOperand> &Pred) const {
    1214       11112 :     return false;
    1215             :   }
    1216             : 
    1217             :   /// Return true if the specified instruction can be predicated.
    1218             :   /// By default, this returns true for every instruction with a
    1219             :   /// PredicateOperand.
    1220           0 :   virtual bool isPredicable(const MachineInstr &MI) const {
    1221         914 :     return MI.getDesc().isPredicable();
    1222             :   }
    1223             : 
    1224             :   /// Return true if it's safe to move a machine
    1225             :   /// instruction that defines the specified register class.
    1226       67398 :   virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
    1227       67398 :     return true;
    1228             :   }
    1229             : 
    1230             :   /// Test if the given instruction should be considered a scheduling boundary.
    1231             :   /// This primarily includes labels and terminators.
    1232             :   virtual bool isSchedulingBoundary(const MachineInstr &MI,
    1233             :                                     const MachineBasicBlock *MBB,
    1234             :                                     const MachineFunction &MF) const;
    1235             : 
    1236             :   /// Measure the specified inline asm to determine an approximation of its
    1237             :   /// length.
    1238             :   virtual unsigned getInlineAsmLength(const char *Str,
    1239             :                                       const MCAsmInfo &MAI) const;
    1240             : 
    1241             :   /// Allocate and return a hazard recognizer to use for this target when
    1242             :   /// scheduling the machine instructions before register allocation.
    1243             :   virtual ScheduleHazardRecognizer *
    1244             :   CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
    1245             :                                const ScheduleDAG *DAG) const;
    1246             : 
    1247             :   /// Allocate and return a hazard recognizer to use for this target when
    1248             :   /// scheduling the machine instructions before register allocation.
    1249             :   virtual ScheduleHazardRecognizer *
    1250             :   CreateTargetMIHazardRecognizer(const InstrItineraryData *,
    1251             :                                  const ScheduleDAG *DAG) const;
    1252             : 
    1253             :   /// Allocate and return a hazard recognizer to use for this target when
    1254             :   /// scheduling the machine instructions after register allocation.
    1255             :   virtual ScheduleHazardRecognizer *
    1256             :   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *,
    1257             :                                      const ScheduleDAG *DAG) const;
    1258             : 
    1259             :   /// Allocate and return a hazard recognizer to use for by non-scheduling
    1260             :   /// passes.
    1261             :   virtual ScheduleHazardRecognizer *
    1262           0 :   CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
    1263           0 :     return nullptr;
    1264             :   }
    1265             : 
    1266             :   /// Provide a global flag for disabling the PreRA hazard recognizer that
    1267             :   /// targets may choose to honor.
    1268             :   bool usePreRAHazardRecognizer() const;
    1269             : 
    1270             :   /// For a comparison instruction, return the source registers
    1271             :   /// in SrcReg and SrcReg2 if having two register operands, and the value it
    1272             :   /// compares against in CmpValue. Return true if the comparison instruction
    1273             :   /// can be analyzed.
    1274        4282 :   virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
    1275             :                               unsigned &SrcReg2, int &Mask, int &Value) const {
    1276        4282 :     return false;
    1277             :   }
    1278             : 
    1279             :   /// See if the comparison instruction can be converted
    1280             :   /// into something more efficient. E.g., on ARM most instructions can set the
    1281             :   /// flags register, obviating the need for a separate CMP.
    1282         905 :   virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
    1283             :                                     unsigned SrcReg2, int Mask, int Value,
    1284             :                                     const MachineRegisterInfo *MRI) const {
    1285         905 :     return false;
    1286             :   }
    1287       46134 :   virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
    1288             : 
    1289             :   /// Try to remove the load by folding it to a register operand at the use.
    1290             :   /// We fold the load instructions if and only if the
    1291             :   /// def and use are in the same BB. We only look at one load and see
    1292             :   /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
    1293             :   /// defined by the load we are trying to fold. DefMI returns the machine
    1294             :   /// instruction that defines FoldAsLoadDefReg, and the function returns
    1295             :   /// the machine instruction generated due to folding.
    1296       13803 :   virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
    1297             :                                           const MachineRegisterInfo *MRI,
    1298             :                                           unsigned &FoldAsLoadDefReg,
    1299             :                                           MachineInstr *&DefMI) const {
    1300       13803 :     return nullptr;
    1301             :   }
    1302             : 
    1303             :   /// 'Reg' is known to be defined by a move immediate instruction,
    1304             :   /// try to fold the immediate into the use instruction.
    1305             :   /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
    1306             :   /// then the caller may assume that DefMI has been erased from its parent
    1307             :   /// block. The caller may assume that it will not be erased by this
    1308             :   /// function otherwise.
    1309        6911 :   virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
    1310             :                              unsigned Reg, MachineRegisterInfo *MRI) const {
    1311        6911 :     return false;
    1312             :   }
    1313             : 
    1314             :   /// Return the number of u-operations the given machine
    1315             :   /// instruction will be decoded to on the target cpu. The itinerary's
    1316             :   /// IssueWidth is the number of microops that can be dispatched each
    1317             :   /// cycle. An instruction with zero microops takes no dispatch resources.
    1318             :   virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
    1319             :                                   const MachineInstr &MI) const;
    1320             : 
    1321             :   /// Return true for pseudo instructions that don't consume any
    1322             :   /// machine resources in their current form. These are common cases that the
    1323             :   /// scheduler should consider free, rather than conservatively handling them
    1324             :   /// as instructions with no itinerary.
    1325             :   bool isZeroCost(unsigned Opcode) const {
    1326             :     return Opcode <= TargetOpcode::COPY;
    1327             :   }
    1328             : 
    1329             :   virtual int getOperandLatency(const InstrItineraryData *ItinData,
    1330             :                                 SDNode *DefNode, unsigned DefIdx,
    1331             :                                 SDNode *UseNode, unsigned UseIdx) const;
    1332             : 
    1333             :   /// Compute and return the use operand latency of a given pair of def and use.
    1334             :   /// In most cases, the static scheduling itinerary was enough to determine the
    1335             :   /// operand latency. But it may not be possible for instructions with variable
    1336             :   /// number of defs / uses.
    1337             :   ///
    1338             :   /// This is a raw interface to the itinerary that may be directly overridden
    1339             :   /// by a target. Use computeOperandLatency to get the best estimate of
    1340             :   /// latency.
    1341             :   virtual int getOperandLatency(const InstrItineraryData *ItinData,
    1342             :                                 const MachineInstr &DefMI, unsigned DefIdx,
    1343             :                                 const MachineInstr &UseMI,
    1344             :                                 unsigned UseIdx) const;
    1345             : 
    1346             :   /// Compute the instruction latency of a given instruction.
    1347             :   /// If the instruction has higher cost when predicated, it's returned via
    1348             :   /// PredCost.
    1349             :   virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
    1350             :                                    const MachineInstr &MI,
    1351             :                                    unsigned *PredCost = nullptr) const;
    1352             : 
    1353             :   virtual unsigned getPredicationCost(const MachineInstr &MI) const;
    1354             : 
    1355             :   virtual int getInstrLatency(const InstrItineraryData *ItinData,
    1356             :                               SDNode *Node) const;
    1357             : 
    1358             :   /// Return the default expected latency for a def based on its opcode.
    1359             :   unsigned defaultDefLatency(const MCSchedModel &SchedModel,
    1360             :                              const MachineInstr &DefMI) const;
    1361             : 
    1362             :   int computeDefOperandLatency(const InstrItineraryData *ItinData,
    1363             :                                const MachineInstr &DefMI) const;
    1364             : 
    1365             :   /// Return true if this opcode has high latency to its result.
    1366      518797 :   virtual bool isHighLatencyDef(int opc) const { return false; }
    1367             : 
    1368             :   /// Compute operand latency between a def of 'Reg'
    1369             :   /// and a use in the current loop. Return true if the target considered
    1370             :   /// it 'high'. This is used by optimization passes such as machine LICM to
    1371             :   /// determine whether it makes sense to hoist an instruction out even in a
    1372             :   /// high register pressure situation.
    1373        1329 :   virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
    1374             :                                      const MachineRegisterInfo *MRI,
    1375             :                                      const MachineInstr &DefMI, unsigned DefIdx,
    1376             :                                      const MachineInstr &UseMI,
    1377             :                                      unsigned UseIdx) const {
    1378        1329 :     return false;
    1379             :   }
    1380             : 
    1381             :   /// Compute operand latency of a def of 'Reg'. Return true
    1382             :   /// if the target considered it 'low'.
    1383             :   virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
    1384             :                                 const MachineInstr &DefMI,
    1385             :                                 unsigned DefIdx) const;
    1386             : 
    1387             :   /// Perform target-specific instruction verification.
    1388     5930284 :   virtual bool verifyInstruction(const MachineInstr &MI,
    1389             :                                  StringRef &ErrInfo) const {
    1390     5930284 :     return true;
    1391             :   }
    1392             : 
    1393             :   /// Return the current execution domain and bit mask of
    1394             :   /// possible domains for instruction.
    1395             :   ///
    1396             :   /// Some micro-architectures have multiple execution domains, and multiple
    1397             :   /// opcodes that perform the same operation in different domains.  For
    1398             :   /// example, the x86 architecture provides the por, orps, and orpd
    1399             :   /// instructions that all do the same thing.  There is a latency penalty if a
    1400             :   /// register is written in one domain and read in another.
    1401             :   ///
    1402             :   /// This function returns a pair (domain, mask) containing the execution
    1403             :   /// domain of MI, and a bit mask of possible domains.  The setExecutionDomain
    1404             :   /// function can be used to change the opcode to one of the domains in the
    1405             :   /// bit mask.  Instructions whose execution domain can't be changed should
    1406             :   /// return a 0 mask.
    1407             :   ///
    1408             :   /// The execution domain numbers don't have any special meaning except domain
    1409             :   /// 0 is used for instructions that are not associated with any interesting
    1410             :   /// execution domain.
    1411             :   ///
    1412             :   virtual std::pair<uint16_t, uint16_t>
    1413           0 :   getExecutionDomain(const MachineInstr &MI) const {
    1414           0 :     return std::make_pair(0, 0);
    1415             :   }
    1416             : 
    1417             :   /// Change the opcode of MI to execute in Domain.
    1418             :   ///
    1419             :   /// The bit (1 << Domain) must be set in the mask returned from
    1420             :   /// getExecutionDomain(MI).
    1421           0 :   virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
    1422             : 
    1423             :   /// Returns the preferred minimum clearance
    1424             :   /// before an instruction with an unwanted partial register update.
    1425             :   ///
    1426             :   /// Some instructions only write part of a register, and implicitly need to
    1427             :   /// read the other parts of the register.  This may cause unwanted stalls
    1428             :   /// preventing otherwise unrelated instructions from executing in parallel in
    1429             :   /// an out-of-order CPU.
    1430             :   ///
    1431             :   /// For example, the x86 instruction cvtsi2ss writes its result to bits
    1432             :   /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
    1433             :   /// the instruction needs to wait for the old value of the register to become
    1434             :   /// available:
    1435             :   ///
    1436             :   ///   addps %xmm1, %xmm0
    1437             :   ///   movaps %xmm0, (%rax)
    1438             :   ///   cvtsi2ss %rbx, %xmm0
    1439             :   ///
    1440             :   /// In the code above, the cvtsi2ss instruction needs to wait for the addps
    1441             :   /// instruction before it can issue, even though the high bits of %xmm0
    1442             :   /// probably aren't needed.
    1443             :   ///
    1444             :   /// This hook returns the preferred clearance before MI, measured in
    1445             :   /// instructions.  Other defs of MI's operand OpNum are avoided in the last N
    1446             :   /// instructions before MI.  It should only return a positive value for
    1447             :   /// unwanted dependencies.  If the old bits of the defined register have
    1448             :   /// useful values, or if MI is determined to otherwise read the dependency,
    1449             :   /// the hook should return 0.
    1450             :   ///
    1451             :   /// The unwanted dependency may be handled by:
    1452             :   ///
    1453             :   /// 1. Allocating the same register for an MI def and use.  That makes the
    1454             :   ///    unwanted dependency identical to a required dependency.
    1455             :   ///
    1456             :   /// 2. Allocating a register for the def that has no defs in the previous N
    1457             :   ///    instructions.
    1458             :   ///
    1459             :   /// 3. Calling breakPartialRegDependency() with the same arguments.  This
    1460             :   ///    allows the target to insert a dependency breaking instruction.
    1461             :   ///
    1462             :   virtual unsigned
    1463           0 :   getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
    1464             :                                const TargetRegisterInfo *TRI) const {
    1465             :     // The default implementation returns 0 for no partial register dependency.
    1466           0 :     return 0;
    1467             :   }
    1468             : 
    1469             :   /// Return the minimum clearance before an instruction that reads an
    1470             :   /// unused register.
    1471             :   ///
    1472             :   /// For example, AVX instructions may copy part of a register operand into
    1473             :   /// the unused high bits of the destination register.
    1474             :   ///
    1475             :   /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
    1476             :   ///
    1477             :   /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
    1478             :   /// false dependence on any previous write to %xmm0.
    1479             :   ///
    1480             :   /// This hook works similarly to getPartialRegUpdateClearance, except that it
    1481             :   /// does not take an operand index. Instead sets \p OpNum to the index of the
    1482             :   /// unused register.
    1483      124210 :   virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
    1484             :                                         const TargetRegisterInfo *TRI) const {
    1485             :     // The default implementation returns 0 for no undef register dependency.
    1486      124210 :     return 0;
    1487             :   }
    1488             : 
    1489             :   /// Insert a dependency-breaking instruction
    1490             :   /// before MI to eliminate an unwanted dependency on OpNum.
    1491             :   ///
    1492             :   /// If it wasn't possible to avoid a def in the last N instructions before MI
    1493             :   /// (see getPartialRegUpdateClearance), this hook will be called to break the
    1494             :   /// unwanted dependency.
    1495             :   ///
    1496             :   /// On x86, an xorps instruction can be used as a dependency breaker:
    1497             :   ///
    1498             :   ///   addps %xmm1, %xmm0
    1499             :   ///   movaps %xmm0, (%rax)
    1500             :   ///   xorps %xmm0, %xmm0
    1501             :   ///   cvtsi2ss %rbx, %xmm0
    1502             :   ///
    1503             :   /// An <imp-kill> operand should be added to MI if an instruction was
    1504             :   /// inserted.  This ties the instructions together in the post-ra scheduler.
    1505             :   ///
    1506           0 :   virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
    1507           0 :                                          const TargetRegisterInfo *TRI) const {}
    1508             : 
    1509             :   /// Create machine specific model for scheduling.
    1510             :   virtual DFAPacketizer *
    1511           0 :   CreateTargetScheduleState(const TargetSubtargetInfo &) const {
    1512           0 :     return nullptr;
    1513             :   }
    1514             : 
    1515             :   /// Sometimes, it is possible for the target
    1516             :   /// to tell, even without aliasing information, that two MIs access different
    1517             :   /// memory addresses. This function returns true if two MIs access different
    1518             :   /// memory addresses and false otherwise.
    1519             :   ///
    1520             :   /// Assumes any physical registers used to compute addresses have the same
    1521             :   /// value for both instructions. (This is the most useful assumption for
    1522             :   /// post-RA scheduling.)
    1523             :   ///
    1524             :   /// See also MachineInstr::mayAlias, which is implemented on top of this
    1525             :   /// function.
    1526             :   virtual bool
    1527     2274064 :   areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
    1528             :                                   AliasAnalysis *AA = nullptr) const {
    1529             :     assert((MIa.mayLoad() || MIa.mayStore()) &&
    1530             :            "MIa must load from or modify a memory location");
    1531             :     assert((MIb.mayLoad() || MIb.mayStore()) &&
    1532             :            "MIb must load from or modify a memory location");
    1533     2274064 :     return false;
    1534             :   }
    1535             : 
    1536             :   /// Return the value to use for the MachineCSE's LookAheadLimit,
    1537             :   /// which is a heuristic used for CSE'ing phys reg defs.
    1538      166248 :   virtual unsigned getMachineCSELookAheadLimit() const {
    1539             :     // The default lookahead is small to prevent unprofitable quadratic
    1540             :     // behavior.
    1541      166248 :     return 5;
    1542             :   }
    1543             : 
    1544             :   /// Return an array that contains the ids of the target indices (used for the
    1545             :   /// TargetIndex machine operand) and their names.
    1546             :   ///
    1547             :   /// MIR Serialization is able to serialize only the target indices that are
    1548             :   /// defined by this method.
    1549             :   virtual ArrayRef<std::pair<int, const char *>>
    1550           0 :   getSerializableTargetIndices() const {
    1551           0 :     return None;
    1552             :   }
    1553             : 
    1554             :   /// Decompose the machine operand's target flags into two values - the direct
    1555             :   /// target flag value and any of bit flags that are applied.
    1556             :   virtual std::pair<unsigned, unsigned>
    1557           0 :   decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
    1558           0 :     return std::make_pair(0u, 0u);
    1559             :   }
    1560             : 
    1561             :   /// Return an array that contains the direct target flag values and their
    1562             :   /// names.
    1563             :   ///
    1564             :   /// MIR Serialization is able to serialize only the target flags that are
    1565             :   /// defined by this method.
    1566             :   virtual ArrayRef<std::pair<unsigned, const char *>>
    1567           0 :   getSerializableDirectMachineOperandTargetFlags() const {
    1568           0 :     return None;
    1569             :   }
    1570             : 
    1571             :   /// Return an array that contains the bitmask target flag values and their
    1572             :   /// names.
    1573             :   ///
    1574             :   /// MIR Serialization is able to serialize only the target flags that are
    1575             :   /// defined by this method.
    1576             :   virtual ArrayRef<std::pair<unsigned, const char *>>
    1577           1 :   getSerializableBitmaskMachineOperandTargetFlags() const {
    1578           1 :     return None;
    1579             :   }
    1580             : 
    1581             :   /// Return an array that contains the MMO target flag values and their
    1582             :   /// names.
    1583             :   ///
    1584             :   /// MIR Serialization is able to serialize only the MMO target flags that are
    1585             :   /// defined by this method.
    1586             :   virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
    1587           0 :   getSerializableMachineMemOperandTargetFlags() const {
    1588           0 :     return None;
    1589             :   }
    1590             : 
    1591             :   /// Determines whether \p Inst is a tail call instruction. Override this
    1592             :   /// method on targets that do not properly set MCID::Return and MCID::Call on
    1593             :   /// tail call instructions."
    1594         354 :   virtual bool isTailCall(const MachineInstr &Inst) const {
    1595         454 :     return Inst.isReturn() && Inst.isCall();
    1596             :   }
    1597             : 
    1598             :   /// True if the instruction is bound to the top of its basic block and no
    1599             :   /// other instructions shall be inserted before it. This can be implemented
    1600             :   /// to prevent register allocator to insert spills before such instructions.
    1601       86133 :   virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
    1602       86133 :     return false;
    1603             :   }
    1604             : 
    1605             :   /// Returns a \p outliner::TargetCostInfo struct containing target-specific
    1606             :   /// information for a set of outlining candidates.
    1607           0 :   virtual outliner::TargetCostInfo getOutliningCandidateInfo(
    1608             :       std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
    1609           0 :     llvm_unreachable(
    1610             :         "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
    1611             :   }
    1612             : 
    1613             :   /// Returns how or if \p MI should be outlined.
    1614             :   virtual outliner::InstrType
    1615           0 :   getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
    1616           0 :     llvm_unreachable(
    1617             :         "Target didn't implement TargetInstrInfo::getOutliningType!");
    1618             :   }
    1619             : 
    1620             :   /// Returns target-defined flags defining properties of the MBB for
    1621             :   /// the outliner.
    1622          26 :   virtual unsigned getMachineOutlinerMBBFlags(MachineBasicBlock &MBB) const {
    1623          26 :     return 0x0;
    1624             :   }
    1625             : 
    1626             :   /// Insert a custom frame for outlined functions.
    1627           0 :   virtual void buildOutlinedFrame(MachineBasicBlock &MBB,
    1628             :                                       MachineFunction &MF,
    1629             :                                     const outliner::TargetCostInfo &TCI) const {
    1630           0 :     llvm_unreachable(
    1631             :         "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
    1632             :   }
    1633             : 
    1634             :   /// Insert a call to an outlined function into the program.
    1635             :   /// Returns an iterator to the spot where we inserted the call. This must be
    1636             :   /// implemented by the target.
    1637             :   virtual MachineBasicBlock::iterator
    1638           0 :   insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
    1639             :                      MachineBasicBlock::iterator &It, MachineFunction &MF,
    1640             :                      const outliner::TargetCostInfo &TCI) const {
    1641           0 :     llvm_unreachable(
    1642             :         "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
    1643             :   }
    1644             : 
    1645             :   /// Return true if the function can safely be outlined from.
    1646             :   /// A function \p MF is considered safe for outlining if an outlined function
    1647             :   /// produced from instructions in F will produce a program which produces the
    1648             :   /// same output for any set of given inputs.
    1649           0 :   virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
    1650             :                                            bool OutlineFromLinkOnceODRs) const {
    1651           0 :     llvm_unreachable("Target didn't implement "
    1652             :                      "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
    1653             :   }
    1654             : 
    1655             :   /// Return true if the function should be outlined from by default.
    1656           0 :   virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const {
    1657           0 :     return false;
    1658             :   }
    1659             : 
    1660             : private:
    1661             :   unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
    1662             :   unsigned CatchRetOpcode;
    1663             :   unsigned ReturnOpcode;
    1664             : };
    1665             : 
    1666             : /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
    1667             : template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
    1668             :   using RegInfo = DenseMapInfo<unsigned>;
    1669             : 
    1670             :   static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
    1671             :     return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
    1672             :                                           RegInfo::getEmptyKey());
    1673             :   }
    1674             : 
    1675             :   static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
    1676             :     return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
    1677             :                                           RegInfo::getTombstoneKey());
    1678             :   }
    1679             : 
    1680             :   /// Reuse getHashValue implementation from
    1681             :   /// std::pair<unsigned, unsigned>.
    1682             :   static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
    1683     2731849 :     std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
    1684     2731849 :     return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
    1685             :   }
    1686             : 
    1687             :   static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
    1688             :                       const TargetInstrInfo::RegSubRegPair &RHS) {
    1689    19893105 :     return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
    1690     7834439 :            RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
    1691             :   }
    1692             : };
    1693             : 
    1694             : } // end namespace llvm
    1695             : 
    1696             : #endif // LLVM_TARGET_TARGETINSTRINFO_H

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