LCOV - code coverage report
Current view: top level - include/llvm/CodeGen - TargetLowering.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 454 518 87.6 %
Date: 2018-02-18 03:11:45 Functions: 149 190 78.4 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : ///
      10             : /// \file
      11             : /// This file describes how to lower LLVM code to machine code.  This has two
      12             : /// main components:
      13             : ///
      14             : ///  1. Which ValueTypes are natively supported by the target.
      15             : ///  2. Which operations are supported for supported ValueTypes.
      16             : ///  3. Cost thresholds for alternative implementations of certain operations.
      17             : ///
      18             : /// In addition it has a few other components, like information about FP
      19             : /// immediates.
      20             : ///
      21             : //===----------------------------------------------------------------------===//
      22             : 
      23             : #ifndef LLVM_CODEGEN_TARGETLOWERING_H
      24             : #define LLVM_CODEGEN_TARGETLOWERING_H
      25             : 
      26             : #include "llvm/ADT/APInt.h"
      27             : #include "llvm/ADT/ArrayRef.h"
      28             : #include "llvm/ADT/DenseMap.h"
      29             : #include "llvm/ADT/STLExtras.h"
      30             : #include "llvm/ADT/SmallVector.h"
      31             : #include "llvm/ADT/StringRef.h"
      32             : #include "llvm/CodeGen/DAGCombine.h"
      33             : #include "llvm/CodeGen/ISDOpcodes.h"
      34             : #include "llvm/CodeGen/MachineValueType.h"
      35             : #include "llvm/CodeGen/RuntimeLibcalls.h"
      36             : #include "llvm/CodeGen/SelectionDAG.h"
      37             : #include "llvm/CodeGen/SelectionDAGNodes.h"
      38             : #include "llvm/CodeGen/TargetCallingConv.h"
      39             : #include "llvm/CodeGen/ValueTypes.h"
      40             : #include "llvm/IR/Attributes.h"
      41             : #include "llvm/IR/CallSite.h"
      42             : #include "llvm/IR/CallingConv.h"
      43             : #include "llvm/IR/DataLayout.h"
      44             : #include "llvm/IR/DerivedTypes.h"
      45             : #include "llvm/IR/Function.h"
      46             : #include "llvm/IR/IRBuilder.h"
      47             : #include "llvm/IR/InlineAsm.h"
      48             : #include "llvm/IR/Instruction.h"
      49             : #include "llvm/IR/Instructions.h"
      50             : #include "llvm/IR/Type.h"
      51             : #include "llvm/MC/MCRegisterInfo.h"
      52             : #include "llvm/Support/AtomicOrdering.h"
      53             : #include "llvm/Support/Casting.h"
      54             : #include "llvm/Support/ErrorHandling.h"
      55             : #include "llvm/Target/TargetMachine.h"
      56             : #include <algorithm>
      57             : #include <cassert>
      58             : #include <climits>
      59             : #include <cstdint>
      60             : #include <iterator>
      61             : #include <map>
      62             : #include <string>
      63             : #include <utility>
      64             : #include <vector>
      65             : 
      66             : namespace llvm {
      67             : 
      68             : class BranchProbability;
      69             : class CCState;
      70             : class CCValAssign;
      71             : class Constant;
      72             : class FastISel;
      73             : class FunctionLoweringInfo;
      74             : class GlobalValue;
      75             : class IntrinsicInst;
      76             : struct KnownBits;
      77             : class LLVMContext;
      78             : class MachineBasicBlock;
      79             : class MachineFunction;
      80             : class MachineInstr;
      81             : class MachineJumpTableInfo;
      82             : class MachineLoop;
      83             : class MachineRegisterInfo;
      84             : class MCContext;
      85             : class MCExpr;
      86             : class Module;
      87             : class TargetRegisterClass;
      88             : class TargetLibraryInfo;
      89             : class TargetRegisterInfo;
      90             : class Value;
      91             : 
      92             : namespace Sched {
      93             : 
      94             :   enum Preference {
      95             :     None,             // No preference
      96             :     Source,           // Follow source order.
      97             :     RegPressure,      // Scheduling for lowest register pressure.
      98             :     Hybrid,           // Scheduling for both latency and register pressure.
      99             :     ILP,              // Scheduling for ILP in low register pressure mode.
     100             :     VLIW              // Scheduling for VLIW targets.
     101             :   };
     102             : 
     103             : } // end namespace Sched
     104             : 
     105             : /// This base class for TargetLowering contains the SelectionDAG-independent
     106             : /// parts that can be used from the rest of CodeGen.
     107             : class TargetLoweringBase {
     108             : public:
     109             :   /// This enum indicates whether operations are valid for a target, and if not,
     110             :   /// what action should be used to make them valid.
     111             :   enum LegalizeAction : uint8_t {
     112             :     Legal,      // The target natively supports this operation.
     113             :     Promote,    // This operation should be executed in a larger type.
     114             :     Expand,     // Try to expand this to other ops, otherwise use a libcall.
     115             :     LibCall,    // Don't try to expand this to other ops, always use a libcall.
     116             :     Custom      // Use the LowerOperation hook to implement custom lowering.
     117             :   };
     118             : 
     119             :   /// This enum indicates whether a types are legal for a target, and if not,
     120             :   /// what action should be used to make them valid.
     121             :   enum LegalizeTypeAction : uint8_t {
     122             :     TypeLegal,           // The target natively supports this type.
     123             :     TypePromoteInteger,  // Replace this integer with a larger one.
     124             :     TypeExpandInteger,   // Split this integer into two of half the size.
     125             :     TypeSoftenFloat,     // Convert this float to a same size integer type,
     126             :                          // if an operation is not supported in target HW.
     127             :     TypeExpandFloat,     // Split this float into two of half the size.
     128             :     TypeScalarizeVector, // Replace this one-element vector with its element.
     129             :     TypeSplitVector,     // Split this vector into two of half the size.
     130             :     TypeWidenVector,     // This vector should be widened into a larger vector.
     131             :     TypePromoteFloat     // Replace this float with a larger one.
     132             :   };
     133             : 
     134             :   /// LegalizeKind holds the legalization kind that needs to happen to EVT
     135             :   /// in order to type-legalize it.
     136             :   using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
     137             : 
     138             :   /// Enum that describes how the target represents true/false values.
     139             :   enum BooleanContent {
     140             :     UndefinedBooleanContent,    // Only bit 0 counts, the rest can hold garbage.
     141             :     ZeroOrOneBooleanContent,        // All bits zero except for bit 0.
     142             :     ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
     143             :   };
     144             : 
     145             :   /// Enum that describes what type of support for selects the target has.
     146             :   enum SelectSupportKind {
     147             :     ScalarValSelect,      // The target supports scalar selects (ex: cmov).
     148             :     ScalarCondVectorVal,  // The target supports selects with a scalar condition
     149             :                           // and vector values (ex: cmov).
     150             :     VectorMaskSelect      // The target supports vector selects with a vector
     151             :                           // mask (ex: x86 blends).
     152             :   };
     153             : 
     154             :   /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
     155             :   /// to, if at all. Exists because different targets have different levels of
     156             :   /// support for these atomic instructions, and also have different options
     157             :   /// w.r.t. what they should expand to.
     158             :   enum class AtomicExpansionKind {
     159             :     None,    // Don't expand the instruction.
     160             :     LLSC,    // Expand the instruction into loadlinked/storeconditional; used
     161             :              // by ARM/AArch64.
     162             :     LLOnly,  // Expand the (load) instruction into just a load-linked, which has
     163             :              // greater atomic guarantees than a normal load.
     164             :     CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
     165             :   };
     166             : 
     167             :   /// Enum that specifies when a multiplication should be expanded.
     168             :   enum class MulExpansionKind {
     169             :     Always,            // Always expand the instruction.
     170             :     OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
     171             :                        // or custom.
     172             :   };
     173             : 
     174             :   class ArgListEntry {
     175             :   public:
     176             :     Value *Val = nullptr;
     177             :     SDValue Node = SDValue();
     178             :     Type *Ty = nullptr;
     179             :     bool IsSExt : 1;
     180             :     bool IsZExt : 1;
     181             :     bool IsInReg : 1;
     182             :     bool IsSRet : 1;
     183             :     bool IsNest : 1;
     184             :     bool IsByVal : 1;
     185             :     bool IsInAlloca : 1;
     186             :     bool IsReturned : 1;
     187             :     bool IsSwiftSelf : 1;
     188             :     bool IsSwiftError : 1;
     189             :     uint16_t Alignment = 0;
     190             : 
     191             :     ArgListEntry()
     192      522896 :         : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
     193             :           IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
     194      522896 :           IsSwiftSelf(false), IsSwiftError(false) {}
     195             : 
     196             :     void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
     197             :   };
     198             :   using ArgListTy = std::vector<ArgListEntry>;
     199             : 
     200        4835 :   virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
     201        4835 :                                      ArgListTy &Args) const {};
     202             : 
     203             :   static ISD::NodeType getExtendForContent(BooleanContent Content) {
     204       41342 :     switch (Content) {
     205             :     case UndefinedBooleanContent:
     206             :       // Extend by adding rubbish bits.
     207             :       return ISD::ANY_EXTEND;
     208       40001 :     case ZeroOrOneBooleanContent:
     209             :       // Extend by adding zero bits.
     210             :       return ISD::ZERO_EXTEND;
     211        1239 :     case ZeroOrNegativeOneBooleanContent:
     212             :       // Extend by copying the sign bit.
     213             :       return ISD::SIGN_EXTEND;
     214             :     }
     215           0 :     llvm_unreachable("Invalid content kind");
     216             :   }
     217             : 
     218             :   /// NOTE: The TargetMachine owns TLOF.
     219             :   explicit TargetLoweringBase(const TargetMachine &TM);
     220             :   TargetLoweringBase(const TargetLoweringBase &) = delete;
     221             :   TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
     222       60490 :   virtual ~TargetLoweringBase() = default;
     223             : 
     224             : protected:
     225             :   /// \brief Initialize all of the actions to default values.
     226             :   void initActions();
     227             : 
     228             : public:
     229             :   const TargetMachine &getTargetMachine() const { return TM; }
     230             : 
     231        6044 :   virtual bool useSoftFloat() const { return false; }
     232             : 
     233             :   /// Return the pointer type for the given address space, defaults to
     234             :   /// the pointer type from the data layout.
     235             :   /// FIXME: The default needs to be removed once all the code is updated.
     236             :   MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
     237     6238490 :     return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
     238             :   }
     239             : 
     240             :   /// Return the type for frame index, which is determined by
     241             :   /// the alloca address space specified through the data layout.
     242      179418 :   MVT getFrameIndexTy(const DataLayout &DL) const {
     243      179418 :     return getPointerTy(DL, DL.getAllocaAddrSpace());
     244             :   }
     245             : 
     246             :   /// Return the type for operands of fence.
     247             :   /// TODO: Let fence operands be of i32 type and remove this.
     248         500 :   virtual MVT getFenceOperandTy(const DataLayout &DL) const {
     249         500 :     return getPointerTy(DL);
     250             :   }
     251             : 
     252             :   /// EVT is not used in-tree, but is used by out-of-tree target.
     253             :   /// A documentation for this function would be nice...
     254             :   virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
     255             : 
     256             :   EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
     257             : 
     258             :   /// Returns the type to be used for the index operand of:
     259             :   /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
     260             :   /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
     261      115684 :   virtual MVT getVectorIdxTy(const DataLayout &DL) const {
     262      115684 :     return getPointerTy(DL);
     263             :   }
     264             : 
     265       53957 :   virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
     266       53957 :     return true;
     267             :   }
     268             : 
     269             :   /// Return true if multiple condition registers are available.
     270             :   bool hasMultipleConditionRegisters() const {
     271             :     return HasMultipleConditionRegisters;
     272             :   }
     273             : 
     274             :   /// Return true if the target has BitExtract instructions.
     275             :   bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
     276             : 
     277             :   /// Return the preferred vector type legalization action.
     278             :   virtual TargetLoweringBase::LegalizeTypeAction
     279     1380368 :   getPreferredVectorAction(EVT VT) const {
     280             :     // The default action for one element vectors is to scalarize
     281     2643346 :     if (VT.getVectorNumElements() == 1)
     282             :       return TypeScalarizeVector;
     283             :     // The default action for other vectors is to promote
     284     1159554 :     return TypePromoteInteger;
     285             :   }
     286             : 
     287             :   // There are two general methods for expanding a BUILD_VECTOR node:
     288             :   //  1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
     289             :   //     them together.
     290             :   //  2. Build the vector on the stack and then load it.
     291             :   // If this function returns true, then method (1) will be used, subject to
     292             :   // the constraint that all of the necessary shuffles are legal (as determined
     293             :   // by isShuffleMaskLegal). If this function returns false, then method (2) is
     294             :   // always used. The vector type, and the number of defined values, are
     295             :   // provided.
     296             :   virtual bool
     297        1530 :   shouldExpandBuildVectorWithShuffles(EVT /* VT */,
     298             :                                       unsigned DefinedValues) const {
     299        1552 :     return DefinedValues < 3;
     300             :   }
     301             : 
     302             :   /// Return true if integer divide is usually cheaper than a sequence of
     303             :   /// several shifts, adds, and multiplies for this target.
     304             :   /// The definition of "cheaper" may depend on whether we're optimizing
     305             :   /// for speed or for size.
     306         564 :   virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
     307             : 
     308             :   /// Return true if the target can handle a standalone remainder operation.
     309           0 :   virtual bool hasStandaloneRem(EVT VT) const {
     310           0 :     return true;
     311             :   }
     312             : 
     313             :   /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
     314          76 :   virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
     315             :     // Default behavior is to replace SQRT(X) with X*RSQRT(X).
     316          76 :     return false;
     317             :   }
     318             : 
     319             :   /// Reciprocal estimate status values used by the functions below.
     320             :   enum ReciprocalEstimate : int {
     321             :     Unspecified = -1,
     322             :     Disabled = 0,
     323             :     Enabled = 1
     324             :   };
     325             : 
     326             :   /// Return a ReciprocalEstimate enum value for a square root of the given type
     327             :   /// based on the function's attributes. If the operation is not overridden by
     328             :   /// the function's attributes, "Unspecified" is returned and target defaults
     329             :   /// are expected to be used for instruction selection.
     330             :   int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
     331             : 
     332             :   /// Return a ReciprocalEstimate enum value for a division of the given type
     333             :   /// based on the function's attributes. If the operation is not overridden by
     334             :   /// the function's attributes, "Unspecified" is returned and target defaults
     335             :   /// are expected to be used for instruction selection.
     336             :   int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
     337             : 
     338             :   /// Return the refinement step count for a square root of the given type based
     339             :   /// on the function's attributes. If the operation is not overridden by
     340             :   /// the function's attributes, "Unspecified" is returned and target defaults
     341             :   /// are expected to be used for instruction selection.
     342             :   int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
     343             : 
     344             :   /// Return the refinement step count for a division of the given type based
     345             :   /// on the function's attributes. If the operation is not overridden by
     346             :   /// the function's attributes, "Unspecified" is returned and target defaults
     347             :   /// are expected to be used for instruction selection.
     348             :   int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
     349             : 
     350             :   /// Returns true if target has indicated at least one type should be bypassed.
     351             :   bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
     352             : 
     353             :   /// Returns map of slow types for division or remainder with corresponding
     354             :   /// fast types
     355             :   const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
     356       11843 :     return BypassSlowDivWidths;
     357             :   }
     358             : 
     359             :   /// Return true if Flow Control is an expensive operation that should be
     360             :   /// avoided.
     361             :   bool isJumpExpensive() const { return JumpIsExpensive; }
     362             : 
     363             :   /// Return true if selects are only cheaper than branches if the branch is
     364             :   /// unlikely to be predicted right.
     365             :   bool isPredictableSelectExpensive() const {
     366             :     return PredictableSelectIsExpensive;
     367             :   }
     368             : 
     369             :   /// If a branch or a select condition is skewed in one direction by more than
     370             :   /// this factor, it is very likely to be predicted correctly.
     371             :   virtual BranchProbability getPredictableBranchThreshold() const;
     372             : 
     373             :   /// Return true if the following transform is beneficial:
     374             :   /// fold (conv (load x)) -> (load (conv*)x)
     375             :   /// On architectures that don't natively support some vector loads
     376             :   /// efficiently, casting the load to a smaller vector of larger types and
     377             :   /// loading is more efficient, however, this can be undone by optimizations in
     378             :   /// dag combiner.
     379       46302 :   virtual bool isLoadBitCastBeneficial(EVT LoadVT,
     380             :                                        EVT BitcastVT) const {
     381             :     // Don't do if we could do an indexed load on the original type, but not on
     382             :     // the new one.
     383       46302 :     if (!LoadVT.isSimple() || !BitcastVT.isSimple())
     384             :       return true;
     385             : 
     386             :     MVT LoadMVT = LoadVT.getSimpleVT();
     387             : 
     388             :     // Don't bother doing this if it's just going to be promoted again later, as
     389             :     // doing so might interfere with other combines.
     390       87809 :     if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
     391       85182 :         getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
     392             :       return false;
     393             : 
     394             :     return true;
     395             :   }
     396             : 
     397             :   /// Return true if the following transform is beneficial:
     398             :   /// (store (y (conv x)), y*)) -> (store x, (x*))
     399       50658 :   virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
     400             :     // Default to the same logic as loads.
     401       50658 :     return isLoadBitCastBeneficial(StoreVT, BitcastVT);
     402             :   }
     403             : 
     404             :   /// Return true if it is expected to be cheaper to do a store of a non-zero
     405             :   /// vector constant with the given size and type for the address space than to
     406             :   /// store the individual scalar element constants.
     407       12750 :   virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
     408             :                                             unsigned NumElem,
     409             :                                             unsigned AddrSpace) const {
     410       12750 :     return false;
     411             :   }
     412             : 
     413             :   /// Allow store merging after legalization in addition to before legalization.
     414             :   /// This may catch stores that do not exist earlier (eg, stores created from
     415             :   /// intrinsics).
     416       54909 :   virtual bool mergeStoresAfterLegalization() const { return true; }
     417             : 
     418             :   /// Returns if it's reasonable to merge stores to MemVT size.
     419        7688 :   virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
     420             :                                 const SelectionDAG &DAG) const {
     421        7688 :     return true;
     422             :   }
     423             : 
     424             :   /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
     425           8 :   virtual bool isCheapToSpeculateCttz() const {
     426           8 :     return false;
     427             :   }
     428             : 
     429             :   /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
     430           5 :   virtual bool isCheapToSpeculateCtlz() const {
     431           5 :     return false;
     432             :   }
     433             : 
     434             :   /// \brief Return true if ctlz instruction is fast.
     435           0 :   virtual bool isCtlzFast() const {
     436           0 :     return false;
     437             :   }
     438             : 
     439             :   /// Return true if it is safe to transform an integer-domain bitwise operation
     440             :   /// into the equivalent floating-point operation. This should be set to true
     441             :   /// if the target has IEEE-754-compliant fabs/fneg operations for the input
     442             :   /// type.
     443       16739 :   virtual bool hasBitPreservingFPLogic(EVT VT) const {
     444       16739 :     return false;
     445             :   }
     446             : 
     447             :   /// \brief Return true if it is cheaper to split the store of a merged int val
     448             :   /// from a pair of smaller values into multiple stores.
     449          56 :   virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
     450          56 :     return false;
     451             :   }
     452             : 
     453             :   /// \brief Return if the target supports combining a
     454             :   /// chain like:
     455             :   /// \code
     456             :   ///   %andResult = and %val1, #mask
     457             :   ///   %icmpResult = icmp %andResult, 0
     458             :   /// \endcode
     459             :   /// into a single machine instruction of a form like:
     460             :   /// \code
     461             :   ///   cc = test %register, #mask
     462             :   /// \endcode
     463          41 :   virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
     464          41 :     return false;
     465             :   }
     466             : 
     467             :   /// Use bitwise logic to make pairs of compares more efficient. For example:
     468             :   /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
     469             :   /// This should be true when it takes more than one instruction to lower
     470             :   /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
     471             :   /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
     472         356 :   virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
     473         356 :     return false;
     474             :   }
     475             : 
     476             :   /// Return the preferred operand type if the target has a quick way to compare
     477             :   /// integer values of the given size. Assume that any legal integer type can
     478             :   /// be compared efficiently. Targets may override this to allow illegal wide
     479             :   /// types to return a vector type if there is support to compare that type.
     480           0 :   virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
     481           0 :     MVT VT = MVT::getIntegerVT(NumBits);
     482           0 :     return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
     483             :   }
     484             : 
     485             :   /// Return true if the target should transform:
     486             :   /// (X & Y) == Y ---> (~X & Y) == 0
     487             :   /// (X & Y) != Y ---> (~X & Y) != 0
     488             :   ///
     489             :   /// This may be profitable if the target has a bitwise and-not operation that
     490             :   /// sets comparison flags. A target may want to limit the transformation based
     491             :   /// on the type of Y or if Y is a constant.
     492             :   ///
     493             :   /// Note that the transform will not occur if Y is known to be a power-of-2
     494             :   /// because a mask and compare of a single bit can be handled by inverting the
     495             :   /// predicate, for example:
     496             :   /// (X & 8) == 8 ---> (X & 8) != 0
     497         514 :   virtual bool hasAndNotCompare(SDValue Y) const {
     498         514 :     return false;
     499             :   }
     500             : 
     501             :   /// Return true if the target has a bitwise and-not operation:
     502             :   /// X = ~A & B
     503             :   /// This can be used to simplify select or other instructions.
     504         813 :   virtual bool hasAndNot(SDValue X) const {
     505             :     // If the target has the more complex version of this operation, assume that
     506             :     // it has this operation too.
     507         813 :     return hasAndNotCompare(X);
     508             :   }
     509             : 
     510             :   /// \brief Return true if the target wants to use the optimization that
     511             :   /// turns ext(promotableInst1(...(promotableInstN(load)))) into
     512             :   /// promotedInst1(...(promotedInstN(ext(load)))).
     513             :   bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
     514             : 
     515             :   /// Return true if the target can combine store(extractelement VectorTy,
     516             :   /// Idx).
     517             :   /// \p Cost[out] gives the cost of that transformation when this is true.
     518       18070 :   virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
     519             :                                          unsigned &Cost) const {
     520       18070 :     return false;
     521             :   }
     522             : 
     523             :   /// Return true if target supports floating point exceptions.
     524             :   bool hasFloatingPointExceptions() const {
     525             :     return HasFloatingPointExceptions;
     526             :   }
     527             : 
     528             :   /// Return true if target always beneficiates from combining into FMA for a
     529             :   /// given value type. This must typically return false on targets where FMA
     530             :   /// takes more cycles to execute than FADD.
     531        4082 :   virtual bool enableAggressiveFMAFusion(EVT VT) const {
     532        4082 :     return false;
     533             :   }
     534             : 
     535             :   /// Return the ValueType of the result of SETCC operations.
     536             :   virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
     537             :                                  EVT VT) const;
     538             : 
     539             :   /// Return the ValueType for comparison libcalls. Comparions libcalls include
     540             :   /// floating point comparion calls, and Ordered/Unordered check calls on
     541             :   /// floating point numbers.
     542             :   virtual
     543             :   MVT::SimpleValueType getCmpLibcallReturnType() const;
     544             : 
     545             :   /// For targets without i1 registers, this gives the nature of the high-bits
     546             :   /// of boolean values held in types wider than i1.
     547             :   ///
     548             :   /// "Boolean values" are special true/false values produced by nodes like
     549             :   /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
     550             :   /// Not to be confused with general values promoted from i1.  Some cpus
     551             :   /// distinguish between vectors of boolean and scalars; the isVec parameter
     552             :   /// selects between the two kinds.  For example on X86 a scalar boolean should
     553             :   /// be zero extended from i1, while the elements of a vector of booleans
     554             :   /// should be sign extended from i1.
     555             :   ///
     556             :   /// Some cpus also treat floating point types the same way as they treat
     557             :   /// vectors instead of the way they treat scalars.
     558             :   BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
     559      824097 :     if (isVec)
     560      125855 :       return BooleanVectorContents;
     561      702876 :     return isFloat ? BooleanFloatContents : BooleanContents;
     562             :   }
     563             : 
     564      822179 :   BooleanContent getBooleanContents(EVT Type) const {
     565     1644358 :     return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
     566             :   }
     567             : 
     568             :   /// Return target scheduling preference.
     569             :   Sched::Preference getSchedulingPreference() const {
     570             :     return SchedPreferenceInfo;
     571             :   }
     572             : 
     573             :   /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
     574             :   /// for different nodes. This function returns the preference (or none) for
     575             :   /// the given node.
     576     3750859 :   virtual Sched::Preference getSchedulingPreference(SDNode *) const {
     577     3750859 :     return Sched::None;
     578             :   }
     579             : 
     580             :   /// Return the register class that should be used for the specified value
     581             :   /// type.
     582     8573584 :   virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
     583     8775099 :     const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
     584             :     assert(RC && "This value type is not natively supported!");
     585     8573584 :     return RC;
     586             :   }
     587             : 
     588             :   /// Return the 'representative' register class for the specified value
     589             :   /// type.
     590             :   ///
     591             :   /// The 'representative' register class is the largest legal super-reg
     592             :   /// register class for the register class of the value type.  For example, on
     593             :   /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
     594             :   /// register class is GR64 on x86_64.
     595      446634 :   virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
     596      856512 :     const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
     597      446634 :     return RC;
     598             :   }
     599             : 
     600             :   /// Return the cost of the 'representative' register class for the specified
     601             :   /// value type.
     602      518623 :   virtual uint8_t getRepRegClassCostFor(MVT VT) const {
     603      518623 :     return RepRegClassCostForVT[VT.SimpleTy];
     604             :   }
     605             : 
     606             :   /// Return true if the target has native support for the specified value type.
     607             :   /// This means that it has a register that directly holds it without
     608             :   /// promotions or expansions.
     609             :   bool isTypeLegal(EVT VT) const {
     610             :     assert(!VT.isSimple() ||
     611             :            (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
     612   144267269 :     return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
     613             :   }
     614             : 
     615             :   class ValueTypeActionImpl {
     616             :     /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
     617             :     /// that indicates how instruction selection should deal with the type.
     618             :     LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
     619             : 
     620             :   public:
     621       33219 :     ValueTypeActionImpl() {
     622       33219 :       std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
     623             :                 TypeLegal);
     624             :     }
     625             : 
     626             :     LegalizeTypeAction getTypeAction(MVT VT) const {
     627    29752433 :       return ValueTypeActions[VT.SimpleTy];
     628             :     }
     629             : 
     630             :     void setTypeAction(MVT VT, LegalizeTypeAction Action) {
     631     3205553 :       ValueTypeActions[VT.SimpleTy] = Action;
     632             :     }
     633             :   };
     634             : 
     635             :   const ValueTypeActionImpl &getValueTypeActions() const {
     636             :     return ValueTypeActions;
     637             :   }
     638             : 
     639             :   /// Return how we should legalize values of this type, either it is already
     640             :   /// legal (return 'Legal') or we need to promote it to a larger type (return
     641             :   /// 'Promote'), or we need to expand it into multiple registers of smaller
     642             :   /// integer type (return 'Expand').  'Custom' is not an option.
     643             :   LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
     644    28286183 :     return getTypeConversion(Context, VT).first;
     645             :   }
     646             :   LegalizeTypeAction getTypeAction(MVT VT) const {
     647             :     return ValueTypeActions.getTypeAction(VT);
     648             :   }
     649             : 
     650             :   /// For types supported by the target, this is an identity function.  For
     651             :   /// types that must be promoted to larger types, this returns the larger type
     652             :   /// to promote to.  For integer types that are larger than the largest integer
     653             :   /// register, this contains one step in the expansion to get to the smaller
     654             :   /// register. For illegal floating point types, this returns the integer type
     655             :   /// to transform to.
     656             :   EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
     657      738258 :     return getTypeConversion(Context, VT).second;
     658             :   }
     659             : 
     660             :   /// For types supported by the target, this is an identity function.  For
     661             :   /// types that must be expanded (i.e. integer types that are larger than the
     662             :   /// largest integer register or illegal floating point types), this returns
     663             :   /// the largest legal type it will be expanded to.
     664       71956 :   EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
     665             :     assert(!VT.isVector());
     666             :     while (true) {
     667       74690 :       switch (getTypeAction(Context, VT)) {
     668       71956 :       case TypeLegal:
     669       71956 :         return VT;
     670        1367 :       case TypeExpandInteger:
     671        1367 :         VT = getTypeToTransformTo(Context, VT);
     672             :         break;
     673           0 :       default:
     674           0 :         llvm_unreachable("Type is not legal nor is it to be expanded!");
     675             :       }
     676             :     }
     677             :   }
     678             : 
     679             :   /// Vector types are broken down into some number of legal first class types.
     680             :   /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
     681             :   /// promoted EVT::f64 values with the X86 FP stack.  Similarly, EVT::v2i64
     682             :   /// turns into 4 EVT::i32 values with both PPC and X86.
     683             :   ///
     684             :   /// This method returns the number of registers needed, and the VT for each
     685             :   /// register.  It also returns the VT and quantity of the intermediate values
     686             :   /// before they are promoted/expanded.
     687             :   unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
     688             :                                   EVT &IntermediateVT,
     689             :                                   unsigned &NumIntermediates,
     690             :                                   MVT &RegisterVT) const;
     691             : 
     692             :   /// Certain targets such as MIPS require that some types such as vectors are
     693             :   /// always broken down into scalars in some contexts. This occurs even if the
     694             :   /// vector type is legal.
     695       10643 :   virtual unsigned getVectorTypeBreakdownForCallingConv(
     696             :       LLVMContext &Context, EVT VT, EVT &IntermediateVT,
     697             :       unsigned &NumIntermediates, MVT &RegisterVT) const {
     698             :     return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
     699       10643 :                                   RegisterVT);
     700             :   }
     701             : 
     702             :   struct IntrinsicInfo {
     703             :     unsigned     opc = 0;          // target opcode
     704             :     EVT          memVT;            // memory VT
     705             : 
     706             :     // value representing memory location
     707             :     PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
     708             : 
     709             :     int          offset = 0;       // offset off of ptrVal
     710             :     unsigned     size = 0;         // the size of the memory location
     711             :                                    // (taken from memVT if zero)
     712             :     unsigned     align = 1;        // alignment
     713             : 
     714             :     MachineMemOperand::Flags flags = MachineMemOperand::MONone;
     715             :     IntrinsicInfo() = default;
     716             :   };
     717             : 
     718             :   /// Given an intrinsic, checks if on the target the intrinsic will need to map
     719             :   /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
     720             :   /// true and store the intrinsic information into the IntrinsicInfo that was
     721             :   /// passed to the function.
     722        3803 :   virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
     723             :                                   MachineFunction &,
     724             :                                   unsigned /*Intrinsic*/) const {
     725        3803 :     return false;
     726             :   }
     727             : 
     728             :   /// Returns true if the target can instruction select the specified FP
     729             :   /// immediate natively. If false, the legalizer will materialize the FP
     730             :   /// immediate as a load from a constant pool.
     731          65 :   virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
     732          65 :     return false;
     733             :   }
     734             : 
     735             :   /// Targets can use this to indicate that they only support *some*
     736             :   /// VECTOR_SHUFFLE operations, those with specific masks.  By default, if a
     737             :   /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
     738             :   /// legal.
     739         584 :   virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
     740         584 :     return true;
     741             :   }
     742             : 
     743             :   /// Returns true if the operation can trap for the value type.
     744             :   ///
     745             :   /// VT must be a legal type. By default, we optimistically assume most
     746             :   /// operations don't trap except for integer divide and remainder.
     747             :   virtual bool canOpTrap(unsigned Op, EVT VT) const;
     748             : 
     749             :   /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
     750             :   /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
     751             :   /// a VAND with a constant pool entry.
     752        1106 :   virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
     753             :                                       EVT /*VT*/) const {
     754        1106 :     return false;
     755             :   }
     756             : 
     757             :   /// Return how this operation should be treated: either it is legal, needs to
     758             :   /// be promoted to a larger size, needs to be expanded to some other code
     759             :   /// sequence, or the target has a custom expander for it.
     760             :   LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
     761    27954632 :     if (VT.isExtended()) return Expand;
     762             :     // If a target-specific SDNode requires legalization, require the target
     763             :     // to provide custom legalization for it.
     764     3108492 :     if (Op >= array_lengthof(OpActions[0])) return Custom;
     765    49856060 :     return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
     766             :   }
     767             : 
     768             :   /// Return true if the specified operation is legal on this target or can be
     769             :   /// made legal with custom lowering. This is used to help guide high-level
     770             :   /// lowering decisions.
     771       88821 :   bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
     772     4964300 :     return (VT == MVT::Other || isTypeLegal(VT)) &&
     773     4381706 :       (getOperationAction(Op, VT) == Legal ||
     774       88821 :        getOperationAction(Op, VT) == Custom);
     775             :   }
     776             : 
     777             :   /// Return true if the specified operation is legal on this target or can be
     778             :   /// made legal using promotion. This is used to help guide high-level lowering
     779             :   /// decisions.
     780      150212 :   bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
     781      150202 :     return (VT == MVT::Other || isTypeLegal(VT)) &&
     782        4092 :       (getOperationAction(Op, VT) == Legal ||
     783      150212 :        getOperationAction(Op, VT) == Promote);
     784             :   }
     785             : 
     786             :   /// Return true if the specified operation is legal on this target or can be
     787             :   /// made legal with custom lowering or using promotion. This is used to help
     788             :   /// guide high-level lowering decisions.
     789       52606 :   bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
     790       49949 :     return (VT == MVT::Other || isTypeLegal(VT)) &&
     791       27073 :       (getOperationAction(Op, VT) == Legal ||
     792       23174 :        getOperationAction(Op, VT) == Custom ||
     793       52606 :        getOperationAction(Op, VT) == Promote);
     794             :   }
     795             : 
     796             :   /// Return true if the operation uses custom lowering, regardless of whether
     797             :   /// the type is legal or not.
     798             :   bool isOperationCustom(unsigned Op, EVT VT) const {
     799             :     return getOperationAction(Op, VT) == Custom;
     800             :   }
     801             : 
     802             :   /// Return true if lowering to a jump table is allowed.
     803        2616 :   virtual bool areJTsAllowed(const Function *Fn) const {
     804        5230 :     if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
     805             :       return false;
     806             : 
     807             :     return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
     808             :            isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
     809             :   }
     810             : 
     811             :   /// Check whether the range [Low,High] fits in a machine word.
     812        3100 :   bool rangeFitsInWord(const APInt &Low, const APInt &High,
     813             :                        const DataLayout &DL) const {
     814             :     // FIXME: Using the pointer type doesn't seem ideal.
     815        3100 :     uint64_t BW = DL.getIndexSizeInBits(0u);
     816        9300 :     uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
     817        3100 :     return Range <= BW;
     818             :   }
     819             : 
     820             :   /// Return true if lowering to a jump table is suitable for a set of case
     821             :   /// clusters which may contain \p NumCases cases, \p Range range of values.
     822             :   /// FIXME: This function check the maximum table size and density, but the
     823             :   /// minimum size is not checked. It would be nice if the minimum size is
     824             :   /// also combined within this function. Currently, the minimum size check is
     825             :   /// performed in findJumpTable() in SelectionDAGBuiler and
     826             :   /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
     827        2102 :   virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
     828             :                                       uint64_t Range) const {
     829        2102 :     const bool OptForSize = SI->getParent()->getParent()->optForSize();
     830        2102 :     const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
     831             :     const unsigned MaxJumpTableSize =
     832        2050 :         OptForSize || getMaximumJumpTableSize() == 0
     833        2563 :             ? UINT_MAX
     834             :             : getMaximumJumpTableSize();
     835             :     // Check whether a range of clusters is dense enough for a jump table.
     836        3993 :     if (Range <= MaxJumpTableSize &&
     837        1891 :         (NumCases * 100 >= Range * MinDensity)) {
     838             :       return true;
     839             :     }
     840        1001 :     return false;
     841             :   }
     842             : 
     843             :   /// Return true if lowering to a bit test is suitable for a set of case
     844             :   /// clusters which contains \p NumDests unique destinations, \p Low and
     845             :   /// \p High as its lowest and highest case values, and expects \p NumCmps
     846             :   /// case value comparisons. Check if the number of destinations, comparison
     847             :   /// metric, and range are all suitable.
     848        2097 :   bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
     849             :                              const APInt &Low, const APInt &High,
     850             :                              const DataLayout &DL) const {
     851             :     // FIXME: I don't think NumCmps is the correct metric: a single case and a
     852             :     // range of cases both require only one branch to lower. Just looking at the
     853             :     // number of clusters and destinations should be enough to decide whether to
     854             :     // build bit tests.
     855             : 
     856             :     // To lower a range with bit tests, the range must fit the bitwidth of a
     857             :     // machine word.
     858        2097 :     if (!rangeFitsInWord(Low, High, DL))
     859             :       return false;
     860             : 
     861             :     // Decide whether it's profitable to lower this range with bit tests. Each
     862             :     // destination requires a bit test and branch, and there is an overall range
     863             :     // check branch. For a small number of clusters, separate comparisons might
     864             :     // be cheaper, and for many destinations, splitting the range might be
     865             :     // better.
     866        3699 :     return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
     867        1821 :            (NumDests == 3 && NumCmps >= 6);
     868             :   }
     869             : 
     870             :   /// Return true if the specified operation is illegal on this target or
     871             :   /// unlikely to be made legal with custom lowering. This is used to help guide
     872             :   /// high-level lowering decisions.
     873             :   bool isOperationExpand(unsigned Op, EVT VT) const {
     874       13796 :     return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
     875             :   }
     876             : 
     877             :   /// Return true if the specified operation is legal on this target.
     878             :   bool isOperationLegal(unsigned Op, EVT VT) const {
     879     1161676 :     return (VT == MVT::Other || isTypeLegal(VT)) &&
     880             :            getOperationAction(Op, VT) == Legal;
     881             :   }
     882             : 
     883             :   /// Return how this load with extension should be treated: either it is legal,
     884             :   /// needs to be promoted to a larger size, needs to be expanded to some other
     885             :   /// code sequence, or the target has a custom expander for it.
     886             :   LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
     887             :                                   EVT MemVT) const {
     888      128450 :     if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
     889      122260 :     unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
     890      121812 :     unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
     891             :     assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
     892             :            MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
     893       80570 :     unsigned Shift = 4 * ExtType;
     894      125200 :     return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
     895             :   }
     896             : 
     897             :   /// Return true if the specified load with extension is legal on this target.
     898             :   bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
     899       31321 :     return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
     900             :   }
     901             : 
     902             :   /// Return true if the specified load with extension is legal or custom
     903             :   /// on this target.
     904             :   bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
     905        2190 :     return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
     906             :            getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
     907             :   }
     908             : 
     909             :   /// Return how this store with truncation should be treated: either it is
     910             :   /// legal, needs to be promoted to a larger size, needs to be expanded to some
     911             :   /// other code sequence, or the target has a custom expander for it.
     912             :   LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
     913      260389 :     if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
     914       41104 :     unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
     915       41104 :     unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
     916             :     assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
     917             :            "Table isn't big enough!");
     918       41104 :     return TruncStoreActions[ValI][MemI];
     919             :   }
     920             : 
     921             :   /// Return true if the specified store with truncation is legal on this
     922             :   /// target.
     923             :   bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
     924       12264 :     return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
     925             :   }
     926             : 
     927             :   /// Return true if the specified store with truncation has solution on this
     928             :   /// target.
     929             :   bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
     930        1933 :     return isTypeLegal(ValVT) &&
     931        1049 :       (getTruncStoreAction(ValVT, MemVT) == Legal ||
     932             :        getTruncStoreAction(ValVT, MemVT) == Custom);
     933             :   }
     934             : 
     935             :   /// Return how the indexed load should be treated: either it is legal, needs
     936             :   /// to be promoted to a larger size, needs to be expanded to some other code
     937             :   /// sequence, or the target has a custom expander for it.
     938             :   LegalizeAction
     939             :   getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
     940             :     assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
     941             :            "Table isn't big enough!");
     942     2255160 :     unsigned Ty = (unsigned)VT.SimpleTy;
     943     2255160 :     return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
     944             :   }
     945             : 
     946             :   /// Return true if the specified indexed load is legal on this target.
     947             :   bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
     948     4510320 :     return VT.isSimple() &&
     949     2221998 :       (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
     950             :        getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
     951             :   }
     952             : 
     953             :   /// Return how the indexed store should be treated: either it is legal, needs
     954             :   /// to be promoted to a larger size, needs to be expanded to some other code
     955             :   /// sequence, or the target has a custom expander for it.
     956             :   LegalizeAction
     957             :   getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
     958             :     assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
     959             :            "Table isn't big enough!");
     960     3248790 :     unsigned Ty = (unsigned)VT.SimpleTy;
     961     3248790 :     return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
     962             :   }
     963             : 
     964             :   /// Return true if the specified indexed load is legal on this target.
     965             :   bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
     966     6497580 :     return VT.isSimple() &&
     967     3221370 :       (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
     968             :        getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
     969             :   }
     970             : 
     971             :   /// Return how the condition code should be treated: either it is legal, needs
     972             :   /// to be expanded to some other code sequence, or the target has a custom
     973             :   /// expander for it.
     974             :   LegalizeAction
     975             :   getCondCodeAction(ISD::CondCode CC, MVT VT) const {
     976             :     assert((unsigned)CC < array_lengthof(CondCodeActions) &&
     977             :            ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
     978             :            "Table isn't big enough!");
     979             :     // See setCondCodeAction for how this is encoded.
     980       83971 :     uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
     981       84692 :     uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
     982       84692 :     LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
     983             :     assert(Action != Promote && "Can't promote condition code!");
     984             :     return Action;
     985             :   }
     986             : 
     987             :   /// Return true if the specified condition code is legal on this target.
     988             :   bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
     989             :     return
     990        9444 :       getCondCodeAction(CC, VT) == Legal ||
     991             :       getCondCodeAction(CC, VT) == Custom;
     992             :   }
     993             : 
     994             :   /// If the action for this operation is to promote, this method returns the
     995             :   /// ValueType to promote to.
     996      129925 :   MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
     997             :     assert(getOperationAction(Op, VT) == Promote &&
     998             :            "This operation isn't promoted!");
     999             : 
    1000             :     // See if this has an explicit type specified.
    1001             :     std::map<std::pair<unsigned, MVT::SimpleValueType>,
    1002             :              MVT::SimpleValueType>::const_iterator PTTI =
    1003      259850 :       PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
    1004      129925 :     if (PTTI != PromoteToType.end()) return PTTI->second;
    1005             : 
    1006             :     assert((VT.isInteger() || VT.isFloatingPoint()) &&
    1007             :            "Cannot autopromote this type, add it with AddPromotedToType.");
    1008             : 
    1009             :     MVT NVT = VT;
    1010             :     do {
    1011         748 :       NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
    1012             :       assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
    1013             :              "Didn't find type to promote to!");
    1014         742 :     } while (!isTypeLegal(NVT) ||
    1015             :               getOperationAction(Op, NVT) == Promote);
    1016         707 :     return NVT;
    1017             :   }
    1018             : 
    1019             :   /// Return the EVT corresponding to this LLVM type.  This is fixed by the LLVM
    1020             :   /// operations except for the pointer size.  If AllowUnknown is true, this
    1021             :   /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
    1022             :   /// otherwise it will assert.
    1023     8536652 :   EVT getValueType(const DataLayout &DL, Type *Ty,
    1024             :                    bool AllowUnknown = false) const {
    1025             :     // Lower scalar pointers to native pointer types.
    1026             :     if (PointerType *PTy = dyn_cast<PointerType>(Ty))
    1027     3186950 :       return getPointerTy(DL, PTy->getAddressSpace());
    1028             : 
    1029     5349702 :     if (Ty->isVectorTy()) {
    1030             :       VectorType *VTy = cast<VectorType>(Ty);
    1031             :       Type *Elm = VTy->getElementType();
    1032             :       // Lower vectors of pointers to native pointer types.
    1033             :       if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
    1034             :         EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
    1035        7898 :         Elm = PointerTy.getTypeForEVT(Ty->getContext());
    1036             :       }
    1037             : 
    1038             :       return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
    1039     1361465 :                        VTy->getNumElements());
    1040             :     }
    1041     3988237 :     return EVT::getEVT(Ty, AllowUnknown);
    1042             :   }
    1043             : 
    1044             :   /// Return the MVT corresponding to this LLVM type. See getValueType.
    1045             :   MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
    1046             :                          bool AllowUnknown = false) const {
    1047       68225 :     return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
    1048             :   }
    1049             : 
    1050             :   /// Return the desired alignment for ByVal or InAlloca aggregate function
    1051             :   /// arguments in the caller parameter area.  This is the actual alignment, not
    1052             :   /// its logarithm.
    1053             :   virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
    1054             : 
    1055             :   /// Return the type of registers that this ValueType will eventually require.
    1056             :   MVT getRegisterType(MVT VT) const {
    1057             :     assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
    1058     2817662 :     return RegisterTypeForVT[VT.SimpleTy];
    1059             :   }
    1060             : 
    1061             :   /// Return the type of registers that this ValueType will eventually require.
    1062     2221636 :   MVT getRegisterType(LLVMContext &Context, EVT VT) const {
    1063     2221636 :     if (VT.isSimple()) {
    1064             :       assert((unsigned)VT.getSimpleVT().SimpleTy <
    1065             :                 array_lengthof(RegisterTypeForVT));
    1066     2210615 :       return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
    1067             :     }
    1068       11021 :     if (VT.isVector()) {
    1069        2825 :       EVT VT1;
    1070        2825 :       MVT RegisterVT;
    1071             :       unsigned NumIntermediates;
    1072        2825 :       (void)getVectorTypeBreakdown(Context, VT, VT1,
    1073             :                                    NumIntermediates, RegisterVT);
    1074        2825 :       return RegisterVT;
    1075             :     }
    1076        8196 :     if (VT.isInteger()) {
    1077        8196 :       return getRegisterType(Context, getTypeToTransformTo(Context, VT));
    1078             :     }
    1079           0 :     llvm_unreachable("Unsupported extended type!");
    1080             :   }
    1081             : 
    1082             :   /// Return the number of registers that this ValueType will eventually
    1083             :   /// require.
    1084             :   ///
    1085             :   /// This is one for any types promoted to live in larger registers, but may be
    1086             :   /// more than one for types (like i64) that are split into pieces.  For types
    1087             :   /// like i140, which are first promoted then expanded, it is the number of
    1088             :   /// registers needed to hold all the bits of the original type.  For an i140
    1089             :   /// on a 32 bit machine this means 5 registers.
    1090     2374591 :   unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
    1091     2374591 :     if (VT.isSimple()) {
    1092             :       assert((unsigned)VT.getSimpleVT().SimpleTy <
    1093             :                 array_lengthof(NumRegistersForVT));
    1094     2368208 :       return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
    1095             :     }
    1096        6383 :     if (VT.isVector()) {
    1097        3479 :       EVT VT1;
    1098        3479 :       MVT VT2;
    1099             :       unsigned NumIntermediates;
    1100        3479 :       return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
    1101             :     }
    1102        2904 :     if (VT.isInteger()) {
    1103        2904 :       unsigned BitWidth = VT.getSizeInBits();
    1104        2904 :       unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
    1105        2904 :       return (BitWidth + RegWidth - 1) / RegWidth;
    1106             :     }
    1107           0 :     llvm_unreachable("Unsupported extended type!");
    1108             :   }
    1109             : 
    1110             :   /// Certain combinations of ABIs, Targets and features require that types
    1111             :   /// are legal for some operations and not for other operations.
    1112             :   /// For MIPS all vector types must be passed through the integer register set.
    1113        1457 :   virtual MVT getRegisterTypeForCallingConv(MVT VT) const {
    1114        1457 :     return getRegisterType(VT);
    1115             :   }
    1116             : 
    1117      375624 :   virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
    1118             :                                             EVT VT) const {
    1119     1454289 :     return getRegisterType(Context, VT);
    1120             :   }
    1121             : 
    1122             :   /// Certain targets require unusual breakdowns of certain types. For MIPS,
    1123             :   /// this occurs when a vector type is used, as vector are passed through the
    1124             :   /// integer register set.
    1125      375624 :   virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
    1126             :                                                  EVT VT) const {
    1127     1454289 :     return getNumRegisters(Context, VT);
    1128             :   }
    1129             : 
    1130             :   /// Certain targets have context senstive alignment requirements, where one
    1131             :   /// type has the alignment requirement of another type.
    1132      749867 :   virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
    1133             :                                                  DataLayout DL) const {
    1134      749867 :     return DL.getABITypeAlignment(ArgTy);
    1135             :   }
    1136             : 
    1137             :   /// If true, then instruction selection should seek to shrink the FP constant
    1138             :   /// of the specified type to a smaller type in order to save space and / or
    1139             :   /// reduce runtime.
    1140         283 :   virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
    1141             : 
    1142             :   // Return true if it is profitable to reduce the given load node to a smaller
    1143             :   // type.
    1144             :   //
    1145             :   // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
    1146         932 :   virtual bool shouldReduceLoadWidth(SDNode *Load,
    1147             :                                      ISD::LoadExtType ExtTy,
    1148             :                                      EVT NewVT) const {
    1149         932 :     return true;
    1150             :   }
    1151             : 
    1152             :   /// When splitting a value of the specified type into parts, does the Lo
    1153             :   /// or Hi part come first?  This usually follows the endianness, except
    1154             :   /// for ppcf128, where the Hi part always comes first.
    1155             :   bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
    1156      276517 :     return DL.isBigEndian() || VT == MVT::ppcf128;
    1157             :   }
    1158             : 
    1159             :   /// If true, the target has custom DAG combine transformations that it can
    1160             :   /// perform for the specified node.
    1161             :   bool hasTargetDAGCombine(ISD::NodeType NT) const {
    1162             :     assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
    1163    24932212 :     return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
    1164             :   }
    1165             : 
    1166             :   unsigned getGatherAllAliasesMaxDepth() const {
    1167             :     return GatherAllAliasesMaxDepth;
    1168             :   }
    1169             : 
    1170             :   /// Returns the size of the platform's va_list object.
    1171           0 :   virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
    1172           0 :     return getPointerTy(DL).getSizeInBits();
    1173             :   }
    1174             : 
    1175             :   /// \brief Get maximum # of store operations permitted for llvm.memset
    1176             :   ///
    1177             :   /// This function returns the maximum number of store operations permitted
    1178             :   /// to replace a call to llvm.memset. The value is set by the target at the
    1179             :   /// performance threshold for such a replacement. If OptSize is true,
    1180             :   /// return the limit for functions that have OptSize attribute.
    1181             :   unsigned getMaxStoresPerMemset(bool OptSize) const {
    1182       22995 :     return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
    1183             :   }
    1184             : 
    1185             :   /// \brief Get maximum # of store operations permitted for llvm.memcpy
    1186             :   ///
    1187             :   /// This function returns the maximum number of store operations permitted
    1188             :   /// to replace a call to llvm.memcpy. The value is set by the target at the
    1189             :   /// performance threshold for such a replacement. If OptSize is true,
    1190             :   /// return the limit for functions that have OptSize attribute.
    1191             :   unsigned getMaxStoresPerMemcpy(bool OptSize) const {
    1192        2556 :     return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
    1193             :   }
    1194             : 
    1195             :   /// Get maximum # of load operations permitted for memcmp
    1196             :   ///
    1197             :   /// This function returns the maximum number of load operations permitted
    1198             :   /// to replace a call to memcmp. The value is set by the target at the
    1199             :   /// performance threshold for such a replacement. If OptSize is true,
    1200             :   /// return the limit for functions that have OptSize attribute.
    1201             :   unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
    1202         393 :     return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
    1203             :   }
    1204             : 
    1205             :   /// For memcmp expansion when the memcmp result is only compared equal or
    1206             :   /// not-equal to 0, allow up to this number of load pairs per block. As an
    1207             :   /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
    1208             :   ///   a0 = load2bytes &a[0]
    1209             :   ///   b0 = load2bytes &b[0]
    1210             :   ///   a2 = load1byte  &a[2]
    1211             :   ///   b2 = load1byte  &b[2]
    1212             :   ///   r  = cmp eq (a0 ^ b0 | a2 ^ b2), 0
    1213          22 :   virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
    1214          22 :     return 1;
    1215             :   }
    1216             : 
    1217             :   /// \brief Get maximum # of store operations permitted for llvm.memmove
    1218             :   ///
    1219             :   /// This function returns the maximum number of store operations permitted
    1220             :   /// to replace a call to llvm.memmove. The value is set by the target at the
    1221             :   /// performance threshold for such a replacement. If OptSize is true,
    1222             :   /// return the limit for functions that have OptSize attribute.
    1223             :   unsigned getMaxStoresPerMemmove(bool OptSize) const {
    1224          83 :     return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
    1225             :   }
    1226             : 
    1227             :   /// \brief Determine if the target supports unaligned memory accesses.
    1228             :   ///
    1229             :   /// This function returns true if the target allows unaligned memory accesses
    1230             :   /// of the specified type in the given address space. If true, it also returns
    1231             :   /// whether the unaligned memory access is "fast" in the last argument by
    1232             :   /// reference. This is used, for example, in situations where an array
    1233             :   /// copy/move/set is converted to a sequence of store operations. Its use
    1234             :   /// helps to ensure that such replacements don't generate code that causes an
    1235             :   /// alignment error (trap) on the target machine.
    1236        1207 :   virtual bool allowsMisalignedMemoryAccesses(EVT,
    1237             :                                               unsigned AddrSpace = 0,
    1238             :                                               unsigned Align = 1,
    1239             :                                               bool * /*Fast*/ = nullptr) const {
    1240        1207 :     return false;
    1241             :   }
    1242             : 
    1243             :   /// Return true if the target supports a memory access of this type for the
    1244             :   /// given address space and alignment. If the access is allowed, the optional
    1245             :   /// final parameter returns if the access is also fast (as defined by the
    1246             :   /// target).
    1247             :   bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
    1248             :                           unsigned AddrSpace = 0, unsigned Alignment = 1,
    1249             :                           bool *Fast = nullptr) const;
    1250             : 
    1251             :   /// Returns the target specific optimal type for load and store operations as
    1252             :   /// a result of memset, memcpy, and memmove lowering.
    1253             :   ///
    1254             :   /// If DstAlign is zero that means it's safe to destination alignment can
    1255             :   /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
    1256             :   /// a need to check it against alignment requirement, probably because the
    1257             :   /// source does not need to be loaded. If 'IsMemset' is true, that means it's
    1258             :   /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
    1259             :   /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
    1260             :   /// does not need to be loaded.  It returns EVT::Other if the type should be
    1261             :   /// determined using generic target-independent logic.
    1262         132 :   virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
    1263             :                                   unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
    1264             :                                   bool /*IsMemset*/,
    1265             :                                   bool /*ZeroMemset*/,
    1266             :                                   bool /*MemcpyStrSrc*/,
    1267             :                                   MachineFunction &/*MF*/) const {
    1268         132 :     return MVT::Other;
    1269             :   }
    1270             : 
    1271             :   /// Returns true if it's safe to use load / store of the specified type to
    1272             :   /// expand memcpy / memset inline.
    1273             :   ///
    1274             :   /// This is mostly true for all types except for some special cases. For
    1275             :   /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
    1276             :   /// fstpl which also does type conversion. Note the specified type doesn't
    1277             :   /// have to be legal as the hook is used before type legalization.
    1278         399 :   virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
    1279             : 
    1280             :   /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
    1281             :   bool usesUnderscoreSetJmp() const {
    1282             :     return UseUnderscoreSetJmp;
    1283             :   }
    1284             : 
    1285             :   /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
    1286             :   bool usesUnderscoreLongJmp() const {
    1287             :     return UseUnderscoreLongJmp;
    1288             :   }
    1289             : 
    1290             :   /// Return lower limit for number of blocks in a jump table.
    1291             :   virtual unsigned getMinimumJumpTableEntries() const;
    1292             : 
    1293             :   /// Return lower limit of the density in a jump table.
    1294             :   unsigned getMinimumJumpTableDensity(bool OptForSize) const;
    1295             : 
    1296             :   /// Return upper limit for number of entries in a jump table.
    1297             :   /// Zero if no limit.
    1298             :   unsigned getMaximumJumpTableSize() const;
    1299             : 
    1300         136 :   virtual bool isJumpTableRelative() const {
    1301         142 :     return TM.isPositionIndependent();
    1302             :   }
    1303             : 
    1304             :   /// If a physical register, this specifies the register that
    1305             :   /// llvm.savestack/llvm.restorestack should save and restore.
    1306             :   unsigned getStackPointerRegisterToSaveRestore() const {
    1307             :     return StackPointerRegisterToSaveRestore;
    1308             :   }
    1309             : 
    1310             :   /// If a physical register, this returns the register that receives the
    1311             :   /// exception address on entry to an EH pad.
    1312             :   virtual unsigned
    1313           0 :   getExceptionPointerRegister(const Constant *PersonalityFn) const {
    1314             :     // 0 is guaranteed to be the NoRegister value on all targets
    1315           0 :     return 0;
    1316             :   }
    1317             : 
    1318             :   /// If a physical register, this returns the register that receives the
    1319             :   /// exception typeid on entry to a landing pad.
    1320             :   virtual unsigned
    1321           0 :   getExceptionSelectorRegister(const Constant *PersonalityFn) const {
    1322             :     // 0 is guaranteed to be the NoRegister value on all targets
    1323           0 :     return 0;
    1324             :   }
    1325             : 
    1326           0 :   virtual bool needsFixedCatchObjects() const {
    1327           0 :     report_fatal_error("Funclet EH is not implemented for this target");
    1328             :   }
    1329             : 
    1330             :   /// Returns the target's jmp_buf size in bytes (if never set, the default is
    1331             :   /// 200)
    1332             :   unsigned getJumpBufSize() const {
    1333             :     return JumpBufSize;
    1334             :   }
    1335             : 
    1336             :   /// Returns the target's jmp_buf alignment in bytes (if never set, the default
    1337             :   /// is 0)
    1338             :   unsigned getJumpBufAlignment() const {
    1339             :     return JumpBufAlignment;
    1340             :   }
    1341             : 
    1342             :   /// Return the minimum stack alignment of an argument.
    1343             :   unsigned getMinStackArgumentAlignment() const {
    1344             :     return MinStackArgumentAlignment;
    1345             :   }
    1346             : 
    1347             :   /// Return the minimum function alignment.
    1348             :   unsigned getMinFunctionAlignment() const {
    1349             :     return MinFunctionAlignment;
    1350             :   }
    1351             : 
    1352             :   /// Return the preferred function alignment.
    1353             :   unsigned getPrefFunctionAlignment() const {
    1354             :     return PrefFunctionAlignment;
    1355             :   }
    1356             : 
    1357             :   /// Return the preferred loop alignment.
    1358       25089 :   virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
    1359       25934 :     return PrefLoopAlignment;
    1360             :   }
    1361             : 
    1362             :   /// If the target has a standard location for the stack protector guard,
    1363             :   /// returns the address of that location. Otherwise, returns nullptr.
    1364             :   /// DEPRECATED: please override useLoadStackGuardNode and customize
    1365             :   ///             LOAD_STACK_GUARD, or customize @llvm.stackguard().
    1366             :   virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
    1367             : 
    1368             :   /// Inserts necessary declarations for SSP (stack protection) purpose.
    1369             :   /// Should be used only when getIRStackGuard returns nullptr.
    1370             :   virtual void insertSSPDeclarations(Module &M) const;
    1371             : 
    1372             :   /// Return the variable that's previously inserted by insertSSPDeclarations,
    1373             :   /// if any, otherwise return nullptr. Should be used only when
    1374             :   /// getIRStackGuard returns nullptr.
    1375             :   virtual Value *getSDagStackGuard(const Module &M) const;
    1376             : 
    1377             :   /// If this function returns true, stack protection checks should XOR the
    1378             :   /// frame pointer (or whichever pointer is used to address locals) into the
    1379             :   /// stack guard value before checking it. getIRStackGuard must return nullptr
    1380             :   /// if this returns true.
    1381         188 :   virtual bool useStackGuardXorFP() const { return false; }
    1382             : 
    1383             :   /// If the target has a standard stack protection check function that
    1384             :   /// performs validation and error handling, returns the function. Otherwise,
    1385             :   /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
    1386             :   /// Should be used only when getIRStackGuard returns nullptr.
    1387             :   virtual Value *getSSPStackGuardCheck(const Module &M) const;
    1388             : 
    1389             : protected:
    1390             :   Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
    1391             :                                             bool UseTLS) const;
    1392             : 
    1393             : public:
    1394             :   /// Returns the target-specific address of the unsafe stack pointer.
    1395             :   virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
    1396             : 
    1397             :   /// Returns the name of the symbol used to emit stack probes or the empty
    1398             :   /// string if not applicable.
    1399           0 :   virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
    1400           0 :     return "";
    1401             :   }
    1402             : 
    1403             :   /// Returns true if a cast between SrcAS and DestAS is a noop.
    1404         458 :   virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
    1405         458 :     return false;
    1406             :   }
    1407             : 
    1408             :   /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
    1409             :   /// are happy to sink it into basic blocks.
    1410         200 :   virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
    1411         200 :     return isNoopAddrSpaceCast(SrcAS, DestAS);
    1412             :   }
    1413             : 
    1414             :   /// Return true if the pointer arguments to CI should be aligned by aligning
    1415             :   /// the object whose address is being passed. If so then MinSize is set to the
    1416             :   /// minimum size the object must be to be aligned and PrefAlign is set to the
    1417             :   /// preferred alignment.
    1418      496146 :   virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
    1419             :                                       unsigned & /*PrefAlign*/) const {
    1420      496146 :     return false;
    1421             :   }
    1422             : 
    1423             :   //===--------------------------------------------------------------------===//
    1424             :   /// \name Helpers for TargetTransformInfo implementations
    1425             :   /// @{
    1426             : 
    1427             :   /// Get the ISD node that corresponds to the Instruction class opcode.
    1428             :   int InstructionOpcodeToISD(unsigned Opcode) const;
    1429             : 
    1430             :   /// Estimate the cost of type-legalization and the legalized type.
    1431             :   std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
    1432             :                                               Type *Ty) const;
    1433             : 
    1434             :   /// @}
    1435             : 
    1436             :   //===--------------------------------------------------------------------===//
    1437             :   /// \name Helpers for atomic expansion.
    1438             :   /// @{
    1439             : 
    1440             :   /// Returns the maximum atomic operation size (in bits) supported by
    1441             :   /// the backend. Atomic operations greater than this size (as well
    1442             :   /// as ones that are not naturally aligned), will be expanded by
    1443             :   /// AtomicExpandPass into an __atomic_* library call.
    1444             :   unsigned getMaxAtomicSizeInBitsSupported() const {
    1445             :     return MaxAtomicSizeInBitsSupported;
    1446             :   }
    1447             : 
    1448             :   /// Returns the size of the smallest cmpxchg or ll/sc instruction
    1449             :   /// the backend supports.  Any smaller operations are widened in
    1450             :   /// AtomicExpandPass.
    1451             :   ///
    1452             :   /// Note that *unlike* operations above the maximum size, atomic ops
    1453             :   /// are still natively supported below the minimum; they just
    1454             :   /// require a more complex expansion.
    1455             :   unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
    1456             : 
    1457             :   /// Whether the target supports unaligned atomic operations.
    1458             :   bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
    1459             : 
    1460             :   /// Whether AtomicExpandPass should automatically insert fences and reduce
    1461             :   /// ordering for this atomic. This should be true for most architectures with
    1462             :   /// weak memory ordering. Defaults to false.
    1463        4362 :   virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
    1464        4362 :     return false;
    1465             :   }
    1466             : 
    1467             :   /// Perform a load-linked operation on Addr, returning a "Value *" with the
    1468             :   /// corresponding pointee type. This may entail some non-trivial operations to
    1469             :   /// truncate or reconstruct types that will be illegal in the backend. See
    1470             :   /// ARMISelLowering for an example implementation.
    1471           0 :   virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
    1472             :                                 AtomicOrdering Ord) const {
    1473           0 :     llvm_unreachable("Load linked unimplemented on this target");
    1474             :   }
    1475             : 
    1476             :   /// Perform a store-conditional operation to Addr. Return the status of the
    1477             :   /// store. This should be 0 if the store succeeded, non-zero otherwise.
    1478           0 :   virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
    1479             :                                       Value *Addr, AtomicOrdering Ord) const {
    1480           0 :     llvm_unreachable("Store conditional unimplemented on this target");
    1481             :   }
    1482             : 
    1483             :   /// Inserts in the IR a target-specific intrinsic specifying a fence.
    1484             :   /// It is called by AtomicExpandPass before expanding an
    1485             :   ///   AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
    1486             :   ///   if shouldInsertFencesForAtomic returns true.
    1487             :   ///
    1488             :   /// Inst is the original atomic instruction, prior to other expansions that
    1489             :   /// may be performed.
    1490             :   ///
    1491             :   /// This function should either return a nullptr, or a pointer to an IR-level
    1492             :   ///   Instruction*. Even complex fence sequences can be represented by a
    1493             :   ///   single Instruction* through an intrinsic to be lowered later.
    1494             :   /// Backends should override this method to produce target-specific intrinsic
    1495             :   ///   for their fences.
    1496             :   /// FIXME: Please note that the default implementation here in terms of
    1497             :   ///   IR-level fences exists for historical/compatibility reasons and is
    1498             :   ///   *unsound* ! Fences cannot, in general, be used to restore sequential
    1499             :   ///   consistency. For example, consider the following example:
    1500             :   /// atomic<int> x = y = 0;
    1501             :   /// int r1, r2, r3, r4;
    1502             :   /// Thread 0:
    1503             :   ///   x.store(1);
    1504             :   /// Thread 1:
    1505             :   ///   y.store(1);
    1506             :   /// Thread 2:
    1507             :   ///   r1 = x.load();
    1508             :   ///   r2 = y.load();
    1509             :   /// Thread 3:
    1510             :   ///   r3 = y.load();
    1511             :   ///   r4 = x.load();
    1512             :   ///  r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
    1513             :   ///  seq_cst. But if they are lowered to monotonic accesses, no amount of
    1514             :   ///  IR-level fences can prevent it.
    1515             :   /// @{
    1516         110 :   virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
    1517             :                                         AtomicOrdering Ord) const {
    1518         110 :     if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
    1519          77 :       return Builder.CreateFence(Ord);
    1520             :     else
    1521             :       return nullptr;
    1522             :   }
    1523             : 
    1524         110 :   virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
    1525             :                                          Instruction *Inst,
    1526             :                                          AtomicOrdering Ord) const {
    1527         110 :     if (isAcquireOrStronger(Ord))
    1528          87 :       return Builder.CreateFence(Ord);
    1529             :     else
    1530             :       return nullptr;
    1531             :   }
    1532             :   /// @}
    1533             : 
    1534             :   // Emits code that executes when the comparison result in the ll/sc
    1535             :   // expansion of a cmpxchg instruction is such that the store-conditional will
    1536             :   // not execute.  This makes it possible to balance out the load-linked with
    1537             :   // a dedicated instruction, if desired.
    1538             :   // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
    1539             :   // be unnecessarily held, except if clrex, inserted by this hook, is executed.
    1540           3 :   virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
    1541             : 
    1542             :   /// Returns true if the given (atomic) store should be expanded by the
    1543             :   /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
    1544          66 :   virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
    1545          66 :     return false;
    1546             :   }
    1547             : 
    1548             :   /// Returns true if arguments should be sign-extended in lib calls.
    1549       16247 :   virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
    1550       16247 :     return IsSigned;
    1551             :   }
    1552             : 
    1553             :   /// Returns how the given (atomic) load should be expanded by the
    1554             :   /// IR-level AtomicExpand pass.
    1555          79 :   virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
    1556          79 :     return AtomicExpansionKind::None;
    1557             :   }
    1558             : 
    1559             :   /// Returns true if the given atomic cmpxchg should be expanded by the
    1560             :   /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
    1561             :   /// (through emitLoadLinked() and emitStoreConditional()).
    1562         513 :   virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
    1563         513 :     return false;
    1564             :   }
    1565             : 
    1566             :   /// Returns how the IR-level AtomicExpand pass should expand the given
    1567             :   /// AtomicRMW, if at all. Default is to never expand.
    1568         613 :   virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
    1569         613 :     return AtomicExpansionKind::None;
    1570             :   }
    1571             : 
    1572             :   /// On some platforms, an AtomicRMW that never actually modifies the value
    1573             :   /// (such as fetch_add of 0) can be turned into a fence followed by an
    1574             :   /// atomic load. This may sound useless, but it makes it possible for the
    1575             :   /// processor to keep the cacheline shared, dramatically improving
    1576             :   /// performance. And such idempotent RMWs are useful for implementing some
    1577             :   /// kinds of locks, see for example (justification + benchmarks):
    1578             :   /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
    1579             :   /// This method tries doing that transformation, returning the atomic load if
    1580             :   /// it succeeds, and nullptr otherwise.
    1581             :   /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
    1582             :   /// another round of expansion.
    1583             :   virtual LoadInst *
    1584           0 :   lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
    1585           0 :     return nullptr;
    1586             :   }
    1587             : 
    1588             :   /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
    1589             :   /// SIGN_EXTEND, or ANY_EXTEND).
    1590         817 :   virtual ISD::NodeType getExtendForAtomicOps() const {
    1591         817 :     return ISD::ZERO_EXTEND;
    1592             :   }
    1593             : 
    1594             :   /// @}
    1595             : 
    1596             :   /// Returns true if we should normalize
    1597             :   /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
    1598             :   /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
    1599             :   /// that it saves us from materializing N0 and N1 in an integer register.
    1600             :   /// Targets that are able to perform and/or on flags should return false here.
    1601       39953 :   virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
    1602             :                                                EVT VT) const {
    1603             :     // If a target has multiple condition registers, then it likely has logical
    1604             :     // operations on those registers.
    1605       39953 :     if (hasMultipleConditionRegisters())
    1606             :       return false;
    1607             :     // Only do the transform if the value won't be split into multiple
    1608             :     // registers.
    1609             :     LegalizeTypeAction Action = getTypeAction(Context, VT);
    1610       29410 :     return Action != TypeExpandInteger && Action != TypeExpandFloat &&
    1611             :       Action != TypeSplitVector;
    1612             :   }
    1613             : 
    1614             :   /// Return true if a select of constants (select Cond, C1, C2) should be
    1615             :   /// transformed into simple math ops with the condition value. For example:
    1616             :   /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
    1617        1986 :   virtual bool convertSelectOfConstantsToMath(EVT VT) const {
    1618        1986 :     return false;
    1619             :   }
    1620             : 
    1621             :   //===--------------------------------------------------------------------===//
    1622             :   // TargetLowering Configuration Methods - These methods should be invoked by
    1623             :   // the derived class constructor to configure this object for the target.
    1624             :   //
    1625             : protected:
    1626             :   /// Specify how the target extends the result of integer and floating point
    1627             :   /// boolean values from i1 to a wider type.  See getBooleanContents.
    1628             :   void setBooleanContents(BooleanContent Ty) {
    1629       33216 :     BooleanContents = Ty;
    1630       33216 :     BooleanFloatContents = Ty;
    1631             :   }
    1632             : 
    1633             :   /// Specify how the target extends the result of integer and floating point
    1634             :   /// boolean values from i1 to a wider type.  See getBooleanContents.
    1635             :   void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
    1636             :     BooleanContents = IntTy;
    1637        1053 :     BooleanFloatContents = FloatTy;
    1638             :   }
    1639             : 
    1640             :   /// Specify how the target extends the result of a vector boolean value from a
    1641             :   /// vector of i1 to a wider type.  See getBooleanContents.
    1642             :   void setBooleanVectorContents(BooleanContent Ty) {
    1643       32533 :     BooleanVectorContents = Ty;
    1644             :   }
    1645             : 
    1646             :   /// Specify the target scheduling preference.
    1647             :   void setSchedulingPreference(Sched::Preference Pref) {
    1648       19841 :     SchedPreferenceInfo = Pref;
    1649             :   }
    1650             : 
    1651             :   /// Indicate whether this target prefers to use _setjmp to implement
    1652             :   /// llvm.setjmp or the version without _.  Defaults to false.
    1653             :   void setUseUnderscoreSetJmp(bool Val) {
    1654       12919 :     UseUnderscoreSetJmp = Val;
    1655             :   }
    1656             : 
    1657             :   /// Indicate whether this target prefers to use _longjmp to implement
    1658             :   /// llvm.longjmp or the version without _.  Defaults to false.
    1659             :   void setUseUnderscoreLongJmp(bool Val) {
    1660       12919 :     UseUnderscoreLongJmp = Val;
    1661             :   }
    1662             : 
    1663             :   /// Indicate the minimum number of blocks to generate jump tables.
    1664             :   void setMinimumJumpTableEntries(unsigned Val);
    1665             : 
    1666             :   /// Indicate the maximum number of entries in jump tables.
    1667             :   /// Set to zero to generate unlimited jump tables.
    1668             :   void setMaximumJumpTableSize(unsigned);
    1669             : 
    1670             :   /// If set to a physical register, this specifies the register that
    1671             :   /// llvm.savestack/llvm.restorestack should save and restore.
    1672             :   void setStackPointerRegisterToSaveRestore(unsigned R) {
    1673       30292 :     StackPointerRegisterToSaveRestore = R;
    1674             :   }
    1675             : 
    1676             :   /// Tells the code generator that the target has multiple (allocatable)
    1677             :   /// condition registers that can be used to store the results of comparisons
    1678             :   /// for use by selects and conditional branches. With multiple condition
    1679             :   /// registers, the code generator will not aggressively sink comparisons into
    1680             :   /// the blocks of their users.
    1681             :   void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
    1682        3676 :     HasMultipleConditionRegisters = hasManyRegs;
    1683             :   }
    1684             : 
    1685             :   /// Tells the code generator that the target has BitExtract instructions.
    1686             :   /// The code generator will aggressively sink "shift"s into the blocks of
    1687             :   /// their users if the users will generate "and" instructions which can be
    1688             :   /// combined with "shift" to BitExtract instructions.
    1689             :   void setHasExtractBitsInsn(bool hasExtractInsn = true) {
    1690        3603 :     HasExtractBitsInsn = hasExtractInsn;
    1691             :   }
    1692             : 
    1693             :   /// Tells the code generator not to expand logic operations on comparison
    1694             :   /// predicates into separate sequences that increase the amount of flow
    1695             :   /// control.
    1696             :   void setJumpIsExpensive(bool isExpensive = true);
    1697             : 
    1698             :   /// Tells the code generator that this target supports floating point
    1699             :   /// exceptions and cares about preserving floating point exception behavior.
    1700             :   void setHasFloatingPointExceptions(bool FPExceptions = true) {
    1701        2328 :     HasFloatingPointExceptions = FPExceptions;
    1702             :   }
    1703             : 
    1704             :   /// Tells the code generator which bitwidths to bypass.
    1705             :   void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
    1706        2138 :     BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
    1707             :   }
    1708             : 
    1709             :   /// Add the specified register class as an available regclass for the
    1710             :   /// specified value type. This indicates the selector can handle values of
    1711             :   /// that class natively.
    1712             :   void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
    1713             :     assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
    1714      239697 :     RegClassForVT[VT.SimpleTy] = RC;
    1715             :   }
    1716             : 
    1717             :   /// Return the largest legal super-reg register class of the register class
    1718             :   /// for the specified type and its associated "cost".
    1719             :   virtual std::pair<const TargetRegisterClass *, uint8_t>
    1720             :   findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
    1721             : 
    1722             :   /// Once all of the register classes are added, this allows us to compute
    1723             :   /// derived properties we expose.
    1724             :   void computeRegisterProperties(const TargetRegisterInfo *TRI);
    1725             : 
    1726             :   /// Indicate that the specified operation does not work with the specified
    1727             :   /// type and indicate what to do about it. Note that VT may refer to either
    1728             :   /// the type of a result or that of an operand of Op.
    1729             :   void setOperationAction(unsigned Op, MVT VT,
    1730             :                           LegalizeAction Action) {
    1731             :     assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
    1732    39645034 :     OpActions[(unsigned)VT.SimpleTy][Op] = Action;
    1733             :   }
    1734             : 
    1735             :   /// Indicate that the specified load with extension does not work with the
    1736             :   /// specified type and indicate what to do about it.
    1737             :   void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
    1738             :                         LegalizeAction Action) {
    1739             :     assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
    1740             :            MemVT.isValid() && "Table isn't big enough!");
    1741             :     assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
    1742       12012 :     unsigned Shift = 4 * ExtType;
    1743   491924011 :     LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
    1744   491924011 :     LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
    1745             :   }
    1746             : 
    1747             :   /// Indicate that the specified truncating store does not work with the
    1748             :   /// specified type and indicate what to do about it.
    1749             :   void setTruncStoreAction(MVT ValVT, MVT MemVT,
    1750             :                            LegalizeAction Action) {
    1751             :     assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
    1752   185766093 :     TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
    1753             :   }
    1754             : 
    1755             :   /// Indicate that the specified indexed load does or does not work with the
    1756             :   /// specified type and indicate what to do abort it.
    1757             :   ///
    1758             :   /// NOTE: All indexed mode loads are initialized to Expand in
    1759             :   /// TargetLowering.cpp
    1760             :   void setIndexedLoadAction(unsigned IdxMode, MVT VT,
    1761             :                             LegalizeAction Action) {
    1762             :     assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
    1763             :            (unsigned)Action < 0xf && "Table isn't big enough!");
    1764             :     // Load action are kept in the upper half.
    1765    15060904 :     IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
    1766      104976 :     IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
    1767             :   }
    1768             : 
    1769             :   /// Indicate that the specified indexed store does or does not work with the
    1770             :   /// specified type and indicate what to do about it.
    1771             :   ///
    1772             :   /// NOTE: All indexed mode stores are initialized to Expand in
    1773             :   /// TargetLowering.cpp
    1774             :   void setIndexedStoreAction(unsigned IdxMode, MVT VT,
    1775             :                              LegalizeAction Action) {
    1776             :     assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
    1777             :            (unsigned)Action < 0xf && "Table isn't big enough!");
    1778             :     // Store action are kept in the lower half.
    1779      104848 :     IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
    1780    15062878 :     IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
    1781             :   }
    1782             : 
    1783             :   /// Indicate that the specified condition code is or isn't supported on the
    1784             :   /// target and indicate what to do about it.
    1785             :   void setCondCodeAction(ISD::CondCode CC, MVT VT,
    1786             :                          LegalizeAction Action) {
    1787             :     assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
    1788             :            "Table isn't big enough!");
    1789             :     assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
    1790             :     /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
    1791             :     /// value and the upper 29 bits index into the second dimension of the array
    1792             :     /// to select what 32-bit value to use.
    1793        4746 :     uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
    1794      131448 :     CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
    1795      131448 :     CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
    1796             :   }
    1797             : 
    1798             :   /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
    1799             :   /// to trying a larger integer/fp until it can find one that works. If that
    1800             :   /// default is insufficient, this method can be used by the target to override
    1801             :   /// the default.
    1802             :   void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
    1803     1237202 :     PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
    1804             :   }
    1805             : 
    1806             :   /// Convenience method to set an operation to Promote and specify the type
    1807             :   /// in a single call.
    1808             :   void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
    1809             :     setOperationAction(Opc, OrigVT, Promote);
    1810             :     AddPromotedToType(Opc, OrigVT, DestVT);
    1811             :   }
    1812             : 
    1813             :   /// Targets should invoke this method for each target independent node that
    1814             :   /// they want to provide a custom DAG combiner for by implementing the
    1815             :   /// PerformDAGCombine virtual method.
    1816             :   void setTargetDAGCombine(ISD::NodeType NT) {
    1817             :     assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
    1818       51562 :     TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
    1819             :   }
    1820             : 
    1821             :   /// Set the target's required jmp_buf buffer size (in bytes); default is 200
    1822             :   void setJumpBufSize(unsigned Size) {
    1823             :     JumpBufSize = Size;
    1824             :   }
    1825             : 
    1826             :   /// Set the target's required jmp_buf buffer alignment (in bytes); default is
    1827             :   /// 0
    1828             :   void setJumpBufAlignment(unsigned Align) {
    1829             :     JumpBufAlignment = Align;
    1830             :   }
    1831             : 
    1832             :   /// Set the target's minimum function alignment (in log2(bytes))
    1833             :   void setMinFunctionAlignment(unsigned Align) {
    1834       18936 :     MinFunctionAlignment = Align;
    1835             :   }
    1836             : 
    1837             :   /// Set the target's preferred function alignment.  This should be set if
    1838             :   /// there is a performance benefit to higher-than-minimum alignment (in
    1839             :   /// log2(bytes))
    1840             :   void setPrefFunctionAlignment(unsigned Align) {
    1841       14635 :     PrefFunctionAlignment = Align;
    1842             :   }
    1843             : 
    1844             :   /// Set the target's preferred loop alignment. Default alignment is zero, it
    1845             :   /// means the target does not care about loop alignment.  The alignment is
    1846             :   /// specified in log2(bytes). The target may also override
    1847             :   /// getPrefLoopAlignment to provide per-loop values.
    1848             :   void setPrefLoopAlignment(unsigned Align) {
    1849       14246 :     PrefLoopAlignment = Align;
    1850             :   }
    1851             : 
    1852             :   /// Set the minimum stack alignment of an argument (in log2(bytes)).
    1853             :   void setMinStackArgumentAlignment(unsigned Align) {
    1854       15529 :     MinStackArgumentAlignment = Align;
    1855             :   }
    1856             : 
    1857             :   /// Set the maximum atomic operation size supported by the
    1858             :   /// backend. Atomic operations greater than this size (as well as
    1859             :   /// ones that are not naturally aligned), will be expanded by
    1860             :   /// AtomicExpandPass into an __atomic_* library call.
    1861             :   void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
    1862         765 :     MaxAtomicSizeInBitsSupported = SizeInBits;
    1863             :   }
    1864             : 
    1865             :   /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
    1866             :   void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
    1867         982 :     MinCmpXchgSizeInBits = SizeInBits;
    1868             :   }
    1869             : 
    1870             :   /// Sets whether unaligned atomic operations are supported.
    1871             :   void setSupportsUnalignedAtomics(bool UnalignedSupported) {
    1872             :     SupportsUnalignedAtomics = UnalignedSupported;
    1873             :   }
    1874             : 
    1875             : public:
    1876             :   //===--------------------------------------------------------------------===//
    1877             :   // Addressing mode description hooks (used by LSR etc).
    1878             :   //
    1879             : 
    1880             :   /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
    1881             :   /// instructions reading the address. This allows as much computation as
    1882             :   /// possible to be done in the address mode for that operand. This hook lets
    1883             :   /// targets also pass back when this should be done on intrinsics which
    1884             :   /// load/store.
    1885      227679 :   virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
    1886             :                                     SmallVectorImpl<Value*> &/*Ops*/,
    1887             :                                     Type *&/*AccessTy*/) const {
    1888      227679 :     return false;
    1889             :   }
    1890             : 
    1891             :   /// This represents an addressing mode of:
    1892             :   ///    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
    1893             :   /// If BaseGV is null,  there is no BaseGV.
    1894             :   /// If BaseOffs is zero, there is no base offset.
    1895             :   /// If HasBaseReg is false, there is no base register.
    1896             :   /// If Scale is zero, there is no ScaleReg.  Scale of 1 indicates a reg with
    1897             :   /// no scale.
    1898             :   struct AddrMode {
    1899             :     GlobalValue *BaseGV = nullptr;
    1900             :     int64_t      BaseOffs = 0;
    1901             :     bool         HasBaseReg = false;
    1902             :     int64_t      Scale = 0;
    1903             :     AddrMode() = default;
    1904             :   };
    1905             : 
    1906             :   /// Return true if the addressing mode represented by AM is legal for this
    1907             :   /// target, for a load/store of the specified type.
    1908             :   ///
    1909             :   /// The type may be VoidTy, in which case only return true if the addressing
    1910             :   /// mode is legal for a load/store of any legal type.  TODO: Handle
    1911             :   /// pre/postinc as well.
    1912             :   ///
    1913             :   /// If the address space cannot be determined, it will be -1.
    1914             :   ///
    1915             :   /// TODO: Remove default argument
    1916             :   virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
    1917             :                                      Type *Ty, unsigned AddrSpace,
    1918             :                                      Instruction *I = nullptr) const;
    1919             : 
    1920             :   /// \brief Return the cost of the scaling factor used in the addressing mode
    1921             :   /// represented by AM for this target, for a load/store of the specified type.
    1922             :   ///
    1923             :   /// If the AM is supported, the return value must be >= 0.
    1924             :   /// If the AM is not supported, it returns a negative value.
    1925             :   /// TODO: Handle pre/postinc as well.
    1926             :   /// TODO: Remove default argument
    1927        6354 :   virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
    1928             :                                    Type *Ty, unsigned AS = 0) const {
    1929             :     // Default: assume that any scaling factor used in a legal AM is free.
    1930        6354 :     if (isLegalAddressingMode(DL, AM, Ty, AS))
    1931             :       return 0;
    1932           0 :     return -1;
    1933             :   }
    1934             : 
    1935             :   /// Return true if the specified immediate is legal icmp immediate, that is
    1936             :   /// the target has icmp instructions which can compare a register against the
    1937             :   /// immediate without having to materialize the immediate into a register.
    1938       33364 :   virtual bool isLegalICmpImmediate(int64_t) const {
    1939       33364 :     return true;
    1940             :   }
    1941             : 
    1942             :   /// Return true if the specified immediate is legal add immediate, that is the
    1943             :   /// target has add instructions which can add a register with the immediate
    1944             :   /// without having to materialize the immediate into a register.
    1945        1117 :   virtual bool isLegalAddImmediate(int64_t) const {
    1946        1117 :     return true;
    1947             :   }
    1948             : 
    1949             :   /// Return true if it's significantly cheaper to shift a vector by a uniform
    1950             :   /// scalar than by an amount which will vary across each lane. On x86, for
    1951             :   /// example, there is a "psllw" instruction for the former case, but no simple
    1952             :   /// instruction for a general "a << b" operation on vectors.
    1953        6209 :   virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
    1954        6209 :     return false;
    1955             :   }
    1956             : 
    1957             :   /// Returns true if the opcode is a commutative binary operation.
    1958    35952989 :   virtual bool isCommutativeBinOp(unsigned Opcode) const {
    1959             :     // FIXME: This should get its info from the td file.
    1960    35952989 :     switch (Opcode) {
    1961             :     case ISD::ADD:
    1962             :     case ISD::SMIN:
    1963             :     case ISD::SMAX:
    1964             :     case ISD::UMIN:
    1965             :     case ISD::UMAX:
    1966             :     case ISD::MUL:
    1967             :     case ISD::MULHU:
    1968             :     case ISD::MULHS:
    1969             :     case ISD::SMUL_LOHI:
    1970             :     case ISD::UMUL_LOHI:
    1971             :     case ISD::FADD:
    1972             :     case ISD::FMUL:
    1973             :     case ISD::AND:
    1974             :     case ISD::OR:
    1975             :     case ISD::XOR:
    1976             :     case ISD::SADDO:
    1977             :     case ISD::UADDO:
    1978             :     case ISD::ADDC:
    1979             :     case ISD::ADDE:
    1980             :     case ISD::FMINNUM:
    1981             :     case ISD::FMAXNUM:
    1982             :     case ISD::FMINNAN:
    1983             :     case ISD::FMAXNAN:
    1984             :       return true;
    1985    29872208 :     default: return false;
    1986             :     }
    1987             :   }
    1988             : 
    1989             :   /// Return true if it's free to truncate a value of type FromTy to type
    1990             :   /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
    1991             :   /// by referencing its sub-register AX.
    1992             :   /// Targets must return false when FromTy <= ToTy.
    1993          86 :   virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
    1994          86 :     return false;
    1995             :   }
    1996             : 
    1997             :   /// Return true if a truncation from FromTy to ToTy is permitted when deciding
    1998             :   /// whether a call is in tail position. Typically this means that both results
    1999             :   /// would be assigned to the same register or stack slot, but it could mean
    2000             :   /// the target performs adequate checks of its own before proceeding with the
    2001             :   /// tail call.  Targets must return false when FromTy <= ToTy.
    2002           2 :   virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
    2003           2 :     return false;
    2004             :   }
    2005             : 
    2006        5690 :   virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
    2007        5690 :     return false;
    2008             :   }
    2009             : 
    2010        3330 :   virtual bool isProfitableToHoist(Instruction *I) const { return true; }
    2011             : 
    2012             :   /// Return true if the extension represented by \p I is free.
    2013             :   /// Unlikely the is[Z|FP]ExtFree family which is based on types,
    2014             :   /// this method can use the context provided by \p I to decide
    2015             :   /// whether or not \p I is free.
    2016             :   /// This method extends the behavior of the is[Z|FP]ExtFree family.
    2017             :   /// In other words, if is[Z|FP]Free returns true, then this method
    2018             :   /// returns true as well. The converse is not true.
    2019             :   /// The target can perform the adequate checks by overriding isExtFreeImpl.
    2020             :   /// \pre \p I must be a sign, zero, or fp extension.
    2021       19525 :   bool isExtFree(const Instruction *I) const {
    2022       19525 :     switch (I->getOpcode()) {
    2023         120 :     case Instruction::FPExt:
    2024         240 :       if (isFPExtFree(EVT::getEVT(I->getType()),
    2025         120 :                       EVT::getEVT(I->getOperand(0)->getType())))
    2026             :         return true;
    2027             :       break;
    2028       17049 :     case Instruction::ZExt:
    2029       34098 :       if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
    2030             :         return true;
    2031             :       break;
    2032             :     case Instruction::SExt:
    2033             :       break;
    2034           0 :     default:
    2035           0 :       llvm_unreachable("Instruction is not an extension");
    2036             :     }
    2037       14844 :     return isExtFreeImpl(I);
    2038             :   }
    2039             : 
    2040             :   /// Return true if \p Load and \p Ext can form an ExtLoad.
    2041             :   /// For example, in AArch64
    2042             :   ///   %L = load i8, i8* %ptr
    2043             :   ///   %E = zext i8 %L to i32
    2044             :   /// can be lowered into one load instruction
    2045             :   ///   ldrb w0, [x0]
    2046        5224 :   bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
    2047             :                  const DataLayout &DL) const {
    2048        5224 :     EVT VT = getValueType(DL, Ext->getType());
    2049        5224 :     EVT LoadVT = getValueType(DL, Load->getType());
    2050             : 
    2051             :     // If the load has other users and the truncate is not free, the ext
    2052             :     // probably isn't free.
    2053        7661 :     if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
    2054        2437 :         !isTruncateFree(Ext->getType(), Load->getType()))
    2055             :       return false;
    2056             : 
    2057             :     // Check whether the target supports casts folded into loads.
    2058             :     unsigned LType;
    2059        5224 :     if (isa<ZExtInst>(Ext))
    2060             :       LType = ISD::ZEXTLOAD;
    2061             :     else {
    2062             :       assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
    2063             :       LType = ISD::SEXTLOAD;
    2064             :     }
    2065             : 
    2066        5224 :     return isLoadExtLegal(LType, VT, LoadVT);
    2067             :   }
    2068             : 
    2069             :   /// Return true if any actual instruction that defines a value of type FromTy
    2070             :   /// implicitly zero-extends the value to ToTy in the result register.
    2071             :   ///
    2072             :   /// The function should return true when it is likely that the truncate can
    2073             :   /// be freely folded with an instruction defining a value of FromTy. If
    2074             :   /// the defining instruction is unknown (because you're looking at a
    2075             :   /// function argument, PHI, etc.) then the target may require an
    2076             :   /// explicit truncate, which is not necessarily free, but this function
    2077             :   /// does not deal with those cases.
    2078             :   /// Targets must return false when FromTy >= ToTy.
    2079         300 :   virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
    2080         300 :     return false;
    2081             :   }
    2082             : 
    2083       13158 :   virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
    2084       13158 :     return false;
    2085             :   }
    2086             : 
    2087             :   /// Return true if the target supplies and combines to a paired load
    2088             :   /// two loaded values of type LoadedType next to each other in memory.
    2089             :   /// RequiredAlignment gives the minimal alignment constraints that must be met
    2090             :   /// to be able to select this paired load.
    2091             :   ///
    2092             :   /// This information is *not* used to generate actual paired loads, but it is
    2093             :   /// used to generate a sequence of loads that is easier to combine into a
    2094             :   /// paired load.
    2095             :   /// For instance, something like this:
    2096             :   /// a = load i64* addr
    2097             :   /// b = trunc i64 a to i32
    2098             :   /// c = lshr i64 a, 32
    2099             :   /// d = trunc i64 c to i32
    2100             :   /// will be optimized into:
    2101             :   /// b = load i32* addr1
    2102             :   /// d = load i32* addr2
    2103             :   /// Where addr1 = addr2 +/- sizeof(i32).
    2104             :   ///
    2105             :   /// In other words, unless the target performs a post-isel load combining,
    2106             :   /// this information should not be provided because it will generate more
    2107             :   /// loads.
    2108        7052 :   virtual bool hasPairedLoad(EVT /*LoadedType*/,
    2109             :                              unsigned & /*RequiredAlignment*/) const {
    2110        7052 :     return false;
    2111             :   }
    2112             : 
    2113             :   /// \brief Get the maximum supported factor for interleaved memory accesses.
    2114             :   /// Default to be the minimum interleave factor: 2.
    2115           0 :   virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
    2116             : 
    2117             :   /// \brief Lower an interleaved load to target specific intrinsics. Return
    2118             :   /// true on success.
    2119             :   ///
    2120             :   /// \p LI is the vector load instruction.
    2121             :   /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
    2122             :   /// \p Indices is the corresponding indices for each shufflevector.
    2123             :   /// \p Factor is the interleave factor.
    2124           0 :   virtual bool lowerInterleavedLoad(LoadInst *LI,
    2125             :                                     ArrayRef<ShuffleVectorInst *> Shuffles,
    2126             :                                     ArrayRef<unsigned> Indices,
    2127             :                                     unsigned Factor) const {
    2128           0 :     return false;
    2129             :   }
    2130             : 
    2131             :   /// \brief Lower an interleaved store to target specific intrinsics. Return
    2132             :   /// true on success.
    2133             :   ///
    2134             :   /// \p SI is the vector store instruction.
    2135             :   /// \p SVI is the shufflevector to RE-interleave the stored vector.
    2136             :   /// \p Factor is the interleave factor.
    2137           0 :   virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
    2138             :                                      unsigned Factor) const {
    2139           0 :     return false;
    2140             :   }
    2141             : 
    2142             :   /// Return true if zero-extending the specific node Val to type VT2 is free
    2143             :   /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
    2144             :   /// because it's folded such as X86 zero-extending loads).
    2145        8438 :   virtual bool isZExtFree(SDValue Val, EVT VT2) const {
    2146       23326 :     return isZExtFree(Val.getValueType(), VT2);
    2147             :   }
    2148             : 
    2149             :   /// Return true if an fpext operation is free (for instance, because
    2150             :   /// single-precision floating-point numbers are implicitly extended to
    2151             :   /// double-precision).
    2152         113 :   virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
    2153             :     assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
    2154             :            "invalid fpext types");
    2155         113 :     return false;
    2156             :   }
    2157             : 
    2158             :   /// Return true if an fpext operation input to an \p Opcode operation is free
    2159             :   /// (for instance, because half-precision floating-point numbers are
    2160             :   /// implicitly extended to float-precision) for an FMA instruction.
    2161          44 :   virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
    2162             :     assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
    2163             :            "invalid fpext types");
    2164          44 :     return isFPExtFree(DestVT, SrcVT);
    2165             :   }
    2166             : 
    2167             :   /// Return true if folding a vector load into ExtVal (a sign, zero, or any
    2168             :   /// extend node) is profitable.
    2169        3054 :   virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
    2170             : 
    2171             :   /// Return true if an fneg operation is free to the point where it is never
    2172             :   /// worthwhile to replace it with a bitwise operation.
    2173        1499 :   virtual bool isFNegFree(EVT VT) const {
    2174             :     assert(VT.isFloatingPoint());
    2175        1499 :     return false;
    2176             :   }
    2177             : 
    2178             :   /// Return true if an fabs operation is free to the point where it is never
    2179             :   /// worthwhile to replace it with a bitwise operation.
    2180         595 :   virtual bool isFAbsFree(EVT VT) const {
    2181             :     assert(VT.isFloatingPoint());
    2182         595 :     return false;
    2183             :   }
    2184             : 
    2185             :   /// Return true if an FMA operation is faster than a pair of fmul and fadd
    2186             :   /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
    2187             :   /// returns true, otherwise fmuladd is expanded to fmul + fadd.
    2188             :   ///
    2189             :   /// NOTE: This may be called before legalization on types for which FMAs are
    2190             :   /// not legal, but should return true if those types will eventually legalize
    2191             :   /// to types that support FMAs. After legalization, it will only be called on
    2192             :   /// types that support FMAs (via Legal or Custom actions)
    2193        4687 :   virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
    2194        4687 :     return false;
    2195             :   }
    2196             : 
    2197             :   /// Return true if it's profitable to narrow operations of type VT1 to
    2198             :   /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
    2199             :   /// i32 to i16.
    2200         236 :   virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
    2201         236 :     return false;
    2202             :   }
    2203             : 
    2204             :   /// \brief Return true if it is beneficial to convert a load of a constant to
    2205             :   /// just the constant itself.
    2206             :   /// On some targets it might be more efficient to use a combination of
    2207             :   /// arithmetic instructions to materialize the constant instead of loading it
    2208             :   /// from a constant pool.
    2209          12 :   virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
    2210             :                                                  Type *Ty) const {
    2211          12 :     return false;
    2212             :   }
    2213             : 
    2214             :   /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
    2215             :   /// from this source type with this index. This is needed because
    2216             :   /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
    2217             :   /// the first element, and only the target knows which lowering is cheap.
    2218          48 :   virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
    2219             :                                        unsigned Index) const {
    2220          48 :     return false;
    2221             :   }
    2222             : 
    2223             :   // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
    2224             :   // even if the vector itself has multiple uses.
    2225         609 :   virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
    2226         609 :     return false;
    2227             :   }
    2228             : 
    2229             :   //===--------------------------------------------------------------------===//
    2230             :   // Runtime Library hooks
    2231             :   //
    2232             : 
    2233             :   /// Rename the default libcall routine name for the specified libcall.
    2234             :   void setLibcallName(RTLIB::Libcall Call, const char *Name) {
    2235     1444494 :     LibcallRoutineNames[Call] = Name;
    2236             :   }
    2237             : 
    2238             :   /// Get the libcall routine name for the specified libcall.
    2239             :   const char *getLibcallName(RTLIB::Libcall Call) const {
    2240       45197 :     return LibcallRoutineNames[Call];
    2241             :   }
    2242             : 
    2243             :   /// Override the default CondCode to be used to test the result of the
    2244             :   /// comparison libcall against zero.
    2245             :   void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
    2246       56464 :     CmpLibcallCCs[Call] = CC;
    2247             :   }
    2248             : 
    2249             :   /// Get the CondCode that's to be used to test the result of the comparison
    2250             :   /// libcall against zero.
    2251             :   ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
    2252         311 :     return CmpLibcallCCs[Call];
    2253             :   }
    2254             : 
    2255             :   /// Set the CallingConv that should be used for the specified libcall.
    2256             :   void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
    2257    17398286 :     LibcallCallingConvs[Call] = CC;
    2258             :   }
    2259             : 
    2260             :   /// Get the CallingConv that should be used for the specified libcall.
    2261             :   CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
    2262       11106 :     return LibcallCallingConvs[Call];
    2263             :   }
    2264             : 
    2265             :   /// Execute target specific actions to finalize target lowering.
    2266             :   /// This is used to set extra flags in MachineFrameInformation and freezing
    2267             :   /// the set of reserved registers.
    2268             :   /// The default implementation just freezes the set of reserved registers.
    2269             :   virtual void finalizeLowering(MachineFunction &MF) const;
    2270             : 
    2271             : private:
    2272             :   const TargetMachine &TM;
    2273             : 
    2274             :   /// Tells the code generator that the target has multiple (allocatable)
    2275             :   /// condition registers that can be used to store the results of comparisons
    2276             :   /// for use by selects and conditional branches. With multiple condition
    2277             :   /// registers, the code generator will not aggressively sink comparisons into
    2278             :   /// the blocks of their users.
    2279             :   bool HasMultipleConditionRegisters;
    2280             : 
    2281             :   /// Tells the code generator that the target has BitExtract instructions.
    2282             :   /// The code generator will aggressively sink "shift"s into the blocks of
    2283             :   /// their users if the users will generate "and" instructions which can be
    2284             :   /// combined with "shift" to BitExtract instructions.
    2285             :   bool HasExtractBitsInsn;
    2286             : 
    2287             :   /// Tells the code generator to bypass slow divide or remainder
    2288             :   /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
    2289             :   /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
    2290             :   /// div/rem when the operands are positive and less than 256.
    2291             :   DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
    2292             : 
    2293             :   /// Tells the code generator that it shouldn't generate extra flow control
    2294             :   /// instructions and should attempt to combine flow control instructions via
    2295             :   /// predication.
    2296             :   bool JumpIsExpensive;
    2297             : 
    2298             :   /// Whether the target supports or cares about preserving floating point
    2299             :   /// exception behavior.
    2300             :   bool HasFloatingPointExceptions;
    2301             : 
    2302             :   /// This target prefers to use _setjmp to implement llvm.setjmp.
    2303             :   ///
    2304             :   /// Defaults to false.
    2305             :   bool UseUnderscoreSetJmp;
    2306             : 
    2307             :   /// This target prefers to use _longjmp to implement llvm.longjmp.
    2308             :   ///
    2309             :   /// Defaults to false.
    2310             :   bool UseUnderscoreLongJmp;
    2311             : 
    2312             :   /// Information about the contents of the high-bits in boolean values held in
    2313             :   /// a type wider than i1. See getBooleanContents.
    2314             :   BooleanContent BooleanContents;
    2315             : 
    2316             :   /// Information about the contents of the high-bits in boolean values held in
    2317             :   /// a type wider than i1. See getBooleanContents.
    2318             :   BooleanContent BooleanFloatContents;
    2319             : 
    2320             :   /// Information about the contents of the high-bits in boolean vector values
    2321             :   /// when the element type is wider than i1. See getBooleanContents.
    2322             :   BooleanContent BooleanVectorContents;
    2323             : 
    2324             :   /// The target scheduling preference: shortest possible total cycles or lowest
    2325             :   /// register usage.
    2326             :   Sched::Preference SchedPreferenceInfo;
    2327             : 
    2328             :   /// The size, in bytes, of the target's jmp_buf buffers
    2329             :   unsigned JumpBufSize;
    2330             : 
    2331             :   /// The alignment, in bytes, of the target's jmp_buf buffers
    2332             :   unsigned JumpBufAlignment;
    2333             : 
    2334             :   /// The minimum alignment that any argument on the stack needs to have.
    2335             :   unsigned MinStackArgumentAlignment;
    2336             : 
    2337             :   /// The minimum function alignment (used when optimizing for size, and to
    2338             :   /// prevent explicitly provided alignment from leading to incorrect code).
    2339             :   unsigned MinFunctionAlignment;
    2340             : 
    2341             :   /// The preferred function alignment (used when alignment unspecified and
    2342             :   /// optimizing for speed).
    2343             :   unsigned PrefFunctionAlignment;
    2344             : 
    2345             :   /// The preferred loop alignment.
    2346             :   unsigned PrefLoopAlignment;
    2347             : 
    2348             :   /// Size in bits of the maximum atomics size the backend supports.
    2349             :   /// Accesses larger than this will be expanded by AtomicExpandPass.
    2350             :   unsigned MaxAtomicSizeInBitsSupported;
    2351             : 
    2352             :   /// Size in bits of the minimum cmpxchg or ll/sc operation the
    2353             :   /// backend supports.
    2354             :   unsigned MinCmpXchgSizeInBits;
    2355             : 
    2356             :   /// This indicates if the target supports unaligned atomic operations.
    2357             :   bool SupportsUnalignedAtomics;
    2358             : 
    2359             :   /// If set to a physical register, this specifies the register that
    2360             :   /// llvm.savestack/llvm.restorestack should save and restore.
    2361             :   unsigned StackPointerRegisterToSaveRestore;
    2362             : 
    2363             :   /// This indicates the default register class to use for each ValueType the
    2364             :   /// target supports natively.
    2365             :   const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
    2366             :   unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
    2367             :   MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
    2368             : 
    2369             :   /// This indicates the "representative" register class to use for each
    2370             :   /// ValueType the target supports natively. This information is used by the
    2371             :   /// scheduler to track register pressure. By default, the representative
    2372             :   /// register class is the largest legal super-reg register class of the
    2373             :   /// register class of the specified type. e.g. On x86, i8, i16, and i32's
    2374             :   /// representative class would be GR32.
    2375             :   const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
    2376             : 
    2377             :   /// This indicates the "cost" of the "representative" register class for each
    2378             :   /// ValueType. The cost is used by the scheduler to approximate register
    2379             :   /// pressure.
    2380             :   uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
    2381             : 
    2382             :   /// For any value types we are promoting or expanding, this contains the value
    2383             :   /// type that we are changing to.  For Expanded types, this contains one step
    2384             :   /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
    2385             :   /// (e.g. i64 -> i16).  For types natively supported by the system, this holds
    2386             :   /// the same type (e.g. i32 -> i32).
    2387             :   MVT TransformToType[MVT::LAST_VALUETYPE];
    2388             : 
    2389             :   /// For each operation and each value type, keep a LegalizeAction that
    2390             :   /// indicates how instruction selection should deal with the operation.  Most
    2391             :   /// operations are Legal (aka, supported natively by the target), but
    2392             :   /// operations that are not should be described.  Note that operations on
    2393             :   /// non-legal value types are not described here.
    2394             :   LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
    2395             : 
    2396             :   /// For each load extension type and each value type, keep a LegalizeAction
    2397             :   /// that indicates how instruction selection should deal with a load of a
    2398             :   /// specific value type and extension type. Uses 4-bits to store the action
    2399             :   /// for each of the 4 load ext types.
    2400             :   uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
    2401             : 
    2402             :   /// For each value type pair keep a LegalizeAction that indicates whether a
    2403             :   /// truncating store of a specific value type and truncating type is legal.
    2404             :   LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
    2405             : 
    2406             :   /// For each indexed mode and each value type, keep a pair of LegalizeAction
    2407             :   /// that indicates how instruction selection should deal with the load /
    2408             :   /// store.
    2409             :   ///
    2410             :   /// The first dimension is the value_type for the reference. The second
    2411             :   /// dimension represents the various modes for load store.
    2412             :   uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
    2413             : 
    2414             :   /// For each condition code (ISD::CondCode) keep a LegalizeAction that
    2415             :   /// indicates how instruction selection should deal with the condition code.
    2416             :   ///
    2417             :   /// Because each CC action takes up 4 bits, we need to have the array size be
    2418             :   /// large enough to fit all of the value types. This can be done by rounding
    2419             :   /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
    2420             :   uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
    2421             : 
    2422             : protected:
    2423             :   ValueTypeActionImpl ValueTypeActions;
    2424             : 
    2425             : private:
    2426             :   LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
    2427             : 
    2428             :   /// Targets can specify ISD nodes that they would like PerformDAGCombine
    2429             :   /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
    2430             :   /// array.
    2431             :   unsigned char
    2432             :   TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
    2433             : 
    2434             :   /// For operations that must be promoted to a specific type, this holds the
    2435             :   /// destination type.  This map should be sparse, so don't hold it as an
    2436             :   /// array.
    2437             :   ///
    2438             :   /// Targets add entries to this map with AddPromotedToType(..), clients access
    2439             :   /// this with getTypeToPromoteTo(..).
    2440             :   std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
    2441             :     PromoteToType;
    2442             : 
    2443             :   /// Stores the name each libcall.
    2444             :   const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
    2445             : 
    2446             :   /// The ISD::CondCode that should be used to test the result of each of the
    2447             :   /// comparison libcall against zero.
    2448             :   ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
    2449             : 
    2450             :   /// Stores the CallingConv that should be used for each libcall.
    2451             :   CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
    2452             : 
    2453             :   /// Set default libcall names and calling conventions.
    2454             :   void InitLibcalls(const Triple &TT);
    2455             : 
    2456             : protected:
    2457             :   /// Return true if the extension represented by \p I is free.
    2458             :   /// \pre \p I is a sign, zero, or fp extension and
    2459             :   ///      is[Z|FP]ExtFree of the related types is not true.
    2460       14432 :   virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
    2461             : 
    2462             :   /// Depth that GatherAllAliases should should continue looking for chain
    2463             :   /// dependencies when trying to find a more preferable chain. As an
    2464             :   /// approximation, this should be more than the number of consecutive stores
    2465             :   /// expected to be merged.
    2466             :   unsigned GatherAllAliasesMaxDepth;
    2467             : 
    2468             :   /// \brief Specify maximum number of store instructions per memset call.
    2469             :   ///
    2470             :   /// When lowering \@llvm.memset this field specifies the maximum number of
    2471             :   /// store operations that may be substituted for the call to memset. Targets
    2472             :   /// must set this value based on the cost threshold for that target. Targets
    2473             :   /// should assume that the memset will be done using as many of the largest
    2474             :   /// store operations first, followed by smaller ones, if necessary, per
    2475             :   /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
    2476             :   /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
    2477             :   /// store.  This only applies to setting a constant array of a constant size.
    2478             :   unsigned MaxStoresPerMemset;
    2479             : 
    2480             :   /// Maximum number of stores operations that may be substituted for the call
    2481             :   /// to memset, used for functions with OptSize attribute.
    2482             :   unsigned MaxStoresPerMemsetOptSize;
    2483             : 
    2484             :   /// \brief Specify maximum bytes of store instructions per memcpy call.
    2485             :   ///
    2486             :   /// When lowering \@llvm.memcpy this field specifies the maximum number of
    2487             :   /// store operations that may be substituted for a call to memcpy. Targets
    2488             :   /// must set this value based on the cost threshold for that target. Targets
    2489             :   /// should assume that the memcpy will be done using as many of the largest
    2490             :   /// store operations first, followed by smaller ones, if necessary, per
    2491             :   /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
    2492             :   /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
    2493             :   /// and one 1-byte store. This only applies to copying a constant array of
    2494             :   /// constant size.
    2495             :   unsigned MaxStoresPerMemcpy;
    2496             : 
    2497             :   /// Maximum number of store operations that may be substituted for a call to
    2498             :   /// memcpy, used for functions with OptSize attribute.
    2499             :   unsigned MaxStoresPerMemcpyOptSize;
    2500             :   unsigned MaxLoadsPerMemcmp;
    2501             :   unsigned MaxLoadsPerMemcmpOptSize;
    2502             : 
    2503             :   /// \brief Specify maximum bytes of store instructions per memmove call.
    2504             :   ///
    2505             :   /// When lowering \@llvm.memmove this field specifies the maximum number of
    2506             :   /// store instructions that may be substituted for a call to memmove. Targets
    2507             :   /// must set this value based on the cost threshold for that target. Targets
    2508             :   /// should assume that the memmove will be done using as many of the largest
    2509             :   /// store operations first, followed by smaller ones, if necessary, per
    2510             :   /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
    2511             :   /// with 8-bit alignment would result in nine 1-byte stores.  This only
    2512             :   /// applies to copying a constant array of constant size.
    2513             :   unsigned MaxStoresPerMemmove;
    2514             : 
    2515             :   /// Maximum number of store instructions that may be substituted for a call to
    2516             :   /// memmove, used for functions with OptSize attribute.
    2517             :   unsigned MaxStoresPerMemmoveOptSize;
    2518             : 
    2519             :   /// Tells the code generator that select is more expensive than a branch if
    2520             :   /// the branch is usually predicted right.
    2521             :   bool PredictableSelectIsExpensive;
    2522             : 
    2523             :   /// \see enableExtLdPromotion.
    2524             :   bool EnableExtLdPromotion;
    2525             : 
    2526             :   /// Return true if the value types that can be represented by the specified
    2527             :   /// register class are all legal.
    2528             :   bool isLegalRC(const TargetRegisterInfo &TRI,
    2529             :                  const TargetRegisterClass &RC) const;
    2530             : 
    2531             :   /// Replace/modify any TargetFrameIndex operands with a targte-dependent
    2532             :   /// sequence of memory operands that is recognized by PrologEpilogInserter.
    2533             :   MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
    2534             :                                     MachineBasicBlock *MBB) const;
    2535             : 
    2536             :   /// Replace/modify the XRay custom event operands with target-dependent
    2537             :   /// details.
    2538             :   MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
    2539             :                                          MachineBasicBlock *MBB) const;
    2540             : };
    2541             : 
    2542             : /// This class defines information used to lower LLVM code to legal SelectionDAG
    2543             : /// operators that the target instruction selector can accept natively.
    2544             : ///
    2545             : /// This class also defines callbacks that targets must implement to lower
    2546             : /// target-specific constructs to SelectionDAG operators.
    2547       30245 : class TargetLowering : public TargetLoweringBase {
    2548             : public:
    2549             :   struct DAGCombinerInfo;
    2550             : 
    2551             :   TargetLowering(const TargetLowering &) = delete;
    2552             :   TargetLowering &operator=(const TargetLowering &) = delete;
    2553             : 
    2554             :   /// NOTE: The TargetMachine owns TLOF.
    2555             :   explicit TargetLowering(const TargetMachine &TM);
    2556             : 
    2557             :   bool isPositionIndependent() const;
    2558             : 
    2559             :   /// Returns true by value, base pointer and offset pointer and addressing mode
    2560             :   /// by reference if the node's address can be legally represented as
    2561             :   /// pre-indexed load / store address.
    2562           0 :   virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
    2563             :                                          SDValue &/*Offset*/,
    2564             :                                          ISD::MemIndexedMode &/*AM*/,
    2565             :                                          SelectionDAG &/*DAG*/) const {
    2566           0 :     return false;
    2567             :   }
    2568             : 
    2569             :   /// Returns true by value, base pointer and offset pointer and addressing mode
    2570             :   /// by reference if this node can be combined with a load / store to form a
    2571             :   /// post-indexed load / store.
    2572           0 :   virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
    2573             :                                           SDValue &/*Base*/,
    2574             :                                           SDValue &/*Offset*/,
    2575             :                                           ISD::MemIndexedMode &/*AM*/,
    2576             :                                           SelectionDAG &/*DAG*/) const {
    2577           0 :     return false;
    2578             :   }
    2579             : 
    2580             :   /// Return the entry encoding for a jump table in the current function.  The
    2581             :   /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
    2582             :   virtual unsigned getJumpTableEncoding() const;
    2583             : 
    2584             :   virtual const MCExpr *
    2585           0 :   LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
    2586             :                             const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
    2587             :                             MCContext &/*Ctx*/) const {
    2588           0 :     llvm_unreachable("Need to implement this hook if target has custom JTIs");
    2589             :   }
    2590             : 
    2591             :   /// Returns relocation base for the given PIC jumptable.
    2592             :   virtual SDValue getPICJumpTableRelocBase(SDValue Table,
    2593             :                                            SelectionDAG &DAG) const;
    2594             : 
    2595             :   /// This returns the relocation base for the given PIC jumptable, the same as
    2596             :   /// getPICJumpTableRelocBase, but as an MCExpr.
    2597             :   virtual const MCExpr *
    2598             :   getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
    2599             :                                unsigned JTI, MCContext &Ctx) const;
    2600             : 
    2601             :   /// Return true if folding a constant offset with the given GlobalAddress is
    2602             :   /// legal.  It is frequently not legal in PIC relocation models.
    2603             :   virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
    2604             : 
    2605             :   bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
    2606             :                             SDValue &Chain) const;
    2607             : 
    2608             :   void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
    2609             :                            SDValue &NewRHS, ISD::CondCode &CCCode,
    2610             :                            const SDLoc &DL) const;
    2611             : 
    2612             :   /// Returns a pair of (return value, chain).
    2613             :   /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
    2614             :   std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
    2615             :                                           EVT RetVT, ArrayRef<SDValue> Ops,
    2616             :                                           bool isSigned, const SDLoc &dl,
    2617             :                                           bool doesNotReturn = false,
    2618             :                                           bool isReturnValueUsed = true) const;
    2619             : 
    2620             :   /// Check whether parameters to a call that are passed in callee saved
    2621             :   /// registers are the same as from the calling function.  This needs to be
    2622             :   /// checked for tail call eligibility.
    2623             :   bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
    2624             :       const uint32_t *CallerPreservedMask,
    2625             :       const SmallVectorImpl<CCValAssign> &ArgLocs,
    2626             :       const SmallVectorImpl<SDValue> &OutVals) const;
    2627             : 
    2628             :   //===--------------------------------------------------------------------===//
    2629             :   // TargetLowering Optimization Methods
    2630             :   //
    2631             : 
    2632             :   /// A convenience struct that encapsulates a DAG, and two SDValues for
    2633             :   /// returning information from TargetLowering to its clients that want to
    2634             :   /// combine.
    2635             :   struct TargetLoweringOpt {
    2636             :     SelectionDAG &DAG;
    2637             :     bool LegalTys;
    2638             :     bool LegalOps;
    2639             :     SDValue Old;
    2640             :     SDValue New;
    2641             : 
    2642             :     explicit TargetLoweringOpt(SelectionDAG &InDAG,
    2643     2681071 :                                bool LT, bool LO) :
    2644     2681071 :       DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
    2645             : 
    2646             :     bool LegalTypes() const { return LegalTys; }
    2647             :     bool LegalOperations() const { return LegalOps; }
    2648             : 
    2649             :     bool CombineTo(SDValue O, SDValue N) {
    2650       91115 :       Old = O;
    2651       91115 :       New = N;
    2652             :       return true;
    2653             :     }
    2654             :   };
    2655             : 
    2656             :   /// Check to see if the specified operand of the specified instruction is a
    2657             :   /// constant integer.  If so, check to see if there are any bits set in the
    2658             :   /// constant that are not demanded.  If so, shrink the constant and return
    2659             :   /// true.
    2660             :   bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
    2661             :                               TargetLoweringOpt &TLO) const;
    2662             : 
    2663             :   // Target hook to do target-specific const optimization, which is called by
    2664             :   // ShrinkDemandedConstant. This function should return true if the target
    2665             :   // doesn't want ShrinkDemandedConstant to further optimize the constant.
    2666      252990 :   virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
    2667             :                                             TargetLoweringOpt &TLO) const {
    2668      252990 :     return false;
    2669             :   }
    2670             : 
    2671             :   /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.  This
    2672             :   /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
    2673             :   /// generalized for targets with other types of implicit widening casts.
    2674             :   bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
    2675             :                         TargetLoweringOpt &TLO) const;
    2676             : 
    2677             :   /// Helper for SimplifyDemandedBits that can simplify an operation with
    2678             :   /// multiple uses.  This function simplifies operand \p OpIdx of \p User and
    2679             :   /// then updates \p User with the simplified version. No other uses of
    2680             :   /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
    2681             :   /// function behaves exactly like function SimplifyDemandedBits declared
    2682             :   /// below except that it also updates the DAG by calling
    2683             :   /// DCI.CommitTargetLoweringOpt.
    2684             :   bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
    2685             :                             DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
    2686             : 
    2687             :   /// Look at Op.  At this point, we know that only the DemandedMask bits of the
    2688             :   /// result of Op are ever used downstream.  If we can use this information to
    2689             :   /// simplify Op, create a new simplified DAG node and return true, returning
    2690             :   /// the original and new nodes in Old and New.  Otherwise, analyze the
    2691             :   /// expression and return a mask of KnownOne and KnownZero bits for the
    2692             :   /// expression (used to simplify the caller).  The KnownZero/One bits may only
    2693             :   /// be accurate for those bits in the DemandedMask.
    2694             :   /// \p AssumeSingleUse When this parameter is true, this function will
    2695             :   ///    attempt to simplify \p Op even if there are multiple uses.
    2696             :   ///    Callers are responsible for correctly updating the DAG based on the
    2697             :   ///    results of this function, because simply replacing replacing TLO.Old
    2698             :   ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
    2699             :   ///    has multiple uses.
    2700             :   bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
    2701             :                             KnownBits &Known,
    2702             :                             TargetLoweringOpt &TLO,
    2703             :                             unsigned Depth = 0,
    2704             :                             bool AssumeSingleUse = false) const;
    2705             : 
    2706             :   /// Helper wrapper around SimplifyDemandedBits
    2707             :   bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
    2708             :                             DAGCombinerInfo &DCI) const;
    2709             : 
    2710             :   /// Look at Vector Op. At this point, we know that only the DemandedElts
    2711             :   /// elements of the result of Op are ever used downstream.  If we can use
    2712             :   /// this information to simplify Op, create a new simplified DAG node and
    2713             :   /// return true, storing the original and new nodes in TLO.
    2714             :   /// Otherwise, analyze the expression and return a mask of KnownUndef and
    2715             :   /// KnownZero elements for the expression (used to simplify the caller).
    2716             :   /// The KnownUndef/Zero elements may only be accurate for those bits
    2717             :   /// in the DemandedMask.
    2718             :   /// \p AssumeSingleUse When this parameter is true, this function will
    2719             :   ///    attempt to simplify \p Op even if there are multiple uses.
    2720             :   ///    Callers are responsible for correctly updating the DAG based on the
    2721             :   ///    results of this function, because simply replacing replacing TLO.Old
    2722             :   ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
    2723             :   ///    has multiple uses.
    2724             :   bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
    2725             :                                   APInt &KnownUndef, APInt &KnownZero,
    2726             :                                   TargetLoweringOpt &TLO, unsigned Depth = 0,
    2727             :                                   bool AssumeSingleUse = false) const;
    2728             : 
    2729             :   /// Helper wrapper around SimplifyDemandedVectorElts
    2730             :   bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
    2731             :                                   APInt &KnownUndef, APInt &KnownZero,
    2732             :                                   DAGCombinerInfo &DCI) const;
    2733             : 
    2734             :   /// Determine which of the bits specified in Mask are known to be either zero
    2735             :   /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
    2736             :   /// argument allows us to only collect the known bits that are shared by the
    2737             :   /// requested vector elements.
    2738             :   virtual void computeKnownBitsForTargetNode(const SDValue Op,
    2739             :                                              KnownBits &Known,
    2740             :                                              const APInt &DemandedElts,
    2741             :                                              const SelectionDAG &DAG,
    2742             :                                              unsigned Depth = 0) const;
    2743             : 
    2744             :   /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
    2745             :   /// Default implementation computes low bits based on alignment
    2746             :   /// information. This should preserve known bits passed into it.
    2747             :   virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
    2748             :                                              KnownBits &Known,
    2749             :                                              const APInt &DemandedElts,
    2750             :                                              const SelectionDAG &DAG,
    2751             :                                              unsigned Depth = 0) const;
    2752             : 
    2753             :   /// This method can be implemented by targets that want to expose additional
    2754             :   /// information about sign bits to the DAG Combiner. The DemandedElts
    2755             :   /// argument allows us to only collect the minimum sign bits that are shared
    2756             :   /// by the requested vector elements.
    2757             :   virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
    2758             :                                                    const APInt &DemandedElts,
    2759             :                                                    const SelectionDAG &DAG,
    2760             :                                                    unsigned Depth = 0) const;
    2761             : 
    2762             :   /// Attempt to simplify any target nodes based on the demanded vector
    2763             :   /// elements, returning true on success. Otherwise, analyze the expression and
    2764             :   /// return a mask of KnownUndef and KnownZero elements for the expression
    2765             :   /// (used to simplify the caller). The KnownUndef/Zero elements may only be
    2766             :   /// accurate for those bits in the DemandedMask
    2767             :   virtual bool SimplifyDemandedVectorEltsForTargetNode(
    2768             :       SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
    2769             :       APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
    2770             : 
    2771             :   struct DAGCombinerInfo {
    2772             :     void *DC;  // The DAG Combiner object.
    2773             :     CombineLevel Level;
    2774             :     bool CalledByLegalizer;
    2775             : 
    2776             :   public:
    2777             :     SelectionDAG &DAG;
    2778             : 
    2779             :     DAGCombinerInfo(SelectionDAG &dag, CombineLevel level,  bool cl, void *dc)
    2780    10632402 :       : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
    2781             : 
    2782             :     bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
    2783     1179995 :     bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
    2784             :     bool isAfterLegalizeVectorOps() const {
    2785             :       return Level == AfterLegalizeDAG;
    2786             :     }
    2787             :     CombineLevel getDAGCombineLevel() { return Level; }
    2788             :     bool isCalledByLegalizer() const { return CalledByLegalizer; }
    2789             : 
    2790             :     void AddToWorklist(SDNode *N);
    2791             :     SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
    2792             :     SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
    2793             :     SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
    2794             : 
    2795             :     void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
    2796             :   };
    2797             : 
    2798             :   /// Return if the N is a constant or constant vector equal to the true value
    2799             :   /// from getBooleanContents().
    2800             :   bool isConstTrueVal(const SDNode *N) const;
    2801             : 
    2802             :   /// Return if the N is a constant or constant vector equal to the false value
    2803             :   /// from getBooleanContents().
    2804             :   bool isConstFalseVal(const SDNode *N) const;
    2805             : 
    2806             :   /// Return if \p N is a True value when extended to \p VT.
    2807             :   bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
    2808             : 
    2809             :   /// Try to simplify a setcc built with the specified operands and cc. If it is
    2810             :   /// unable to simplify it, return a null SDValue.
    2811             :   SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
    2812             :                         bool foldBooleans, DAGCombinerInfo &DCI,
    2813             :                         const SDLoc &dl) const;
    2814             : 
    2815             :   // For targets which wrap address, unwrap for analysis.
    2816     2531385 :   virtual SDValue unwrapAddress(SDValue N) const { return N; }
    2817             : 
    2818             :   /// Returns true (and the GlobalValue and the offset) if the node is a
    2819             :   /// GlobalAddress + offset.
    2820             :   virtual bool
    2821             :   isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
    2822             : 
    2823             :   /// This method will be invoked for all target nodes and for any
    2824             :   /// target-independent nodes that the target has registered with invoke it
    2825             :   /// for.
    2826             :   ///
    2827             :   /// The semantics are as follows:
    2828             :   /// Return Value:
    2829             :   ///   SDValue.Val == 0   - No change was made
    2830             :   ///   SDValue.Val == N   - N was replaced, is dead, and is already handled.
    2831             :   ///   otherwise          - N should be replaced by the returned Operand.
    2832             :   ///
    2833             :   /// In addition, methods provided by DAGCombinerInfo may be used to perform
    2834             :   /// more complex transformations.
    2835             :   ///
    2836             :   virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
    2837             : 
    2838             :   /// Return true if it is profitable to move a following shift through this
    2839             :   //  node, adjusting any immediate operands as necessary to preserve semantics.
    2840             :   //  This transformation may not be desirable if it disrupts a particularly
    2841             :   //  auspicious target-specific tree (e.g. bitfield extraction in AArch64).
    2842             :   //  By default, it returns true.
    2843         784 :   virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
    2844         784 :     return true;
    2845             :   }
    2846             : 
    2847             :   // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
    2848             :   // to a shuffle and a truncate.
    2849             :   // Example of such a combine:
    2850             :   // v4i32 build_vector((extract_elt V, 1),
    2851             :   //                    (extract_elt V, 3),
    2852             :   //                    (extract_elt V, 5),
    2853             :   //                    (extract_elt V, 7))
    2854             :   //  -->
    2855             :   // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
    2856           0 :   virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
    2857             :       ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
    2858           0 :     return false;
    2859             :   }
    2860             : 
    2861             :   /// Return true if the target has native support for the specified value type
    2862             :   /// and it is 'desirable' to use the type for the given node type. e.g. On x86
    2863             :   /// i16 is legal, but undesirable since i16 instruction encodings are longer
    2864             :   /// and some i16 instructions are slow.
    2865      230283 :   virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
    2866             :     // By default, assume all legal types are desirable.
    2867      230283 :     return isTypeLegal(VT);
    2868             :   }
    2869             : 
    2870             :   /// Return true if it is profitable for dag combiner to transform a floating
    2871             :   /// point op of specified opcode to a equivalent op of an integer
    2872             :   /// type. e.g. f32 load -> i32 load can be profitable on ARM.
    2873         287 :   virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
    2874             :                                                  EVT /*VT*/) const {
    2875         287 :     return false;
    2876             :   }
    2877             : 
    2878             :   /// This method query the target whether it is beneficial for dag combiner to
    2879             :   /// promote the specified node. If true, it should return the desired
    2880             :   /// promotion type by reference.
    2881        2978 :   virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
    2882        2978 :     return false;
    2883             :   }
    2884             : 
    2885             :   /// Return true if the target supports swifterror attribute. It optimizes
    2886             :   /// loads and stores to reading and writing a specific register.
    2887      342998 :   virtual bool supportSwiftError() const {
    2888      342998 :     return false;
    2889             :   }
    2890             : 
    2891             :   /// Return true if the target supports that a subset of CSRs for the given
    2892             :   /// machine function is handled explicitly via copies.
    2893       24687 :   virtual bool supportSplitCSR(MachineFunction *MF) const {
    2894       24687 :     return false;
    2895             :   }
    2896             : 
    2897             :   /// Perform necessary initialization to handle a subset of CSRs explicitly
    2898             :   /// via copies. This function is called at the beginning of instruction
    2899             :   /// selection.
    2900           0 :   virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
    2901           0 :     llvm_unreachable("Not Implemented");
    2902             :   }
    2903             : 
    2904             :   /// Insert explicit copies in entry and exit blocks. We copy a subset of
    2905             :   /// CSRs to virtual registers in the entry block, and copy them back to
    2906             :   /// physical registers in the exit blocks. This function is called at the end
    2907             :   /// of instruction selection.
    2908           0 :   virtual void insertCopiesSplitCSR(
    2909             :       MachineBasicBlock *Entry,
    2910             :       const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
    2911           0 :     llvm_unreachable("Not Implemented");
    2912             :   }
    2913             : 
    2914             :   //===--------------------------------------------------------------------===//
    2915             :   // Lowering methods - These methods must be implemented by targets so that
    2916             :   // the SelectionDAGBuilder code knows how to lower these.
    2917             :   //
    2918             : 
    2919             :   /// This hook must be implemented to lower the incoming (formal) arguments,
    2920             :   /// described by the Ins array, into the specified DAG. The implementation
    2921             :   /// should fill in the InVals array with legal-type argument values, and
    2922             :   /// return the resulting token chain value.
    2923           0 :   virtual SDValue LowerFormalArguments(
    2924             :       SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
    2925             :       const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
    2926             :       SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
    2927           0 :     llvm_unreachable("Not Implemented");
    2928             :   }
    2929             : 
    2930             :   /// This structure contains all information that is necessary for lowering
    2931             :   /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
    2932             :   /// needs to lower a call, and targets will see this struct in their LowerCall
    2933             :   /// implementation.
    2934      435758 :   struct CallLoweringInfo {
    2935             :     SDValue Chain;
    2936             :     Type *RetTy = nullptr;
    2937             :     bool RetSExt           : 1;
    2938             :     bool RetZExt           : 1;
    2939             :     bool IsVarArg          : 1;
    2940             :     bool IsInReg           : 1;
    2941             :     bool DoesNotReturn     : 1;
    2942             :     bool IsReturnValueUsed : 1;
    2943             :     bool IsConvergent      : 1;
    2944             :     bool IsPatchPoint      : 1;
    2945             : 
    2946             :     // IsTailCall should be modified by implementations of
    2947             :     // TargetLowering::LowerCall that perform tail call conversions.
    2948             :     bool IsTailCall = false;
    2949             : 
    2950             :     // Is Call lowering done post SelectionDAG type legalization.
    2951             :     bool IsPostTypeLegalization = false;
    2952             : 
    2953             :     unsigned NumFixedArgs = -1;
    2954             :     CallingConv::ID CallConv = CallingConv::C;
    2955             :     SDValue Callee;
    2956             :     ArgListTy Args;
    2957             :     SelectionDAG &DAG;
    2958             :     SDLoc DL;
    2959             :     ImmutableCallSite CS;
    2960             :     SmallVector<ISD::OutputArg, 32> Outs;
    2961             :     SmallVector<SDValue, 32> OutVals;
    2962             :     SmallVector<ISD::InputArg, 32> Ins;
    2963             :     SmallVector<SDValue, 4> InVals;
    2964             : 
    2965      217885 :     CallLoweringInfo(SelectionDAG &DAG)
    2966      217885 :         : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
    2967             :           DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
    2968      653655 :           IsPatchPoint(false), DAG(DAG) {}
    2969             : 
    2970             :     CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
    2971             :       DL = dl;
    2972             :       return *this;
    2973             :     }
    2974             : 
    2975             :     CallLoweringInfo &setChain(SDValue InChain) {
    2976      259107 :       Chain = InChain;
    2977             :       return *this;
    2978             :     }
    2979             : 
    2980             :     // setCallee with target/module-specific attributes
    2981        7583 :     CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
    2982             :                                    SDValue Target, ArgListTy &&ArgsList) {
    2983        7583 :       RetTy = ResultType;
    2984        7583 :       Callee = Target;
    2985        7583 :       CallConv = CC;
    2986        7583 :       NumFixedArgs = ArgsList.size();
    2987        7583 :       Args = std::move(ArgsList);
    2988             : 
    2989       15166 :       DAG.getTargetLoweringInfo().markLibCallAttributes(
    2990        7583 :           &(DAG.getMachineFunction()), CC, Args);
    2991        7583 :       return *this;
    2992             :     }
    2993             : 
    2994             :     CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
    2995             :                                 SDValue Target, ArgListTy &&ArgsList) {
    2996         559 :       RetTy = ResultType;
    2997         559 :       Callee = Target;
    2998         559 :       CallConv = CC;
    2999         559 :       NumFixedArgs = ArgsList.size();
    3000         185 :       Args = std::move(ArgsList);
    3001             :       return *this;
    3002             :     }
    3003             : 
    3004      209743 :     CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
    3005             :                                 SDValue Target, ArgListTy &&ArgsList,
    3006             :                                 ImmutableCallSite Call) {
    3007      209743 :       RetTy = ResultType;
    3008             : 
    3009      209743 :       IsInReg = Call.hasRetAttr(Attribute::InReg);
    3010      209743 :       DoesNotReturn =
    3011      209743 :           Call.doesNotReturn() ||
    3012      160412 :           (!Call.isInvoke() &&
    3013             :            isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
    3014      209743 :       IsVarArg = FTy->isVarArg();
    3015      209743 :       IsReturnValueUsed = !Call.getInstruction()->use_empty();
    3016      209743 :       RetSExt = Call.hasRetAttr(Attribute::SExt);
    3017      209743 :       RetZExt = Call.hasRetAttr(Attribute::ZExt);
    3018             : 
    3019      209743 :       Callee = Target;
    3020             : 
    3021      209743 :       CallConv = Call.getCallingConv();
    3022      209743 :       NumFixedArgs = FTy->getNumParams();
    3023      209743 :       Args = std::move(ArgsList);
    3024             : 
    3025      209743 :       CS = Call;
    3026             : 
    3027      209743 :       return *this;
    3028             :     }
    3029             : 
    3030             :     CallLoweringInfo &setInRegister(bool Value = true) {
    3031         197 :       IsInReg = Value;
    3032             :       return *this;
    3033             :     }
    3034             : 
    3035             :     CallLoweringInfo &setNoReturn(bool Value = true) {
    3036        2795 :       DoesNotReturn = Value;
    3037             :       return *this;
    3038             :     }
    3039             : 
    3040             :     CallLoweringInfo &setVarArg(bool Value = true) {
    3041             :       IsVarArg = Value;
    3042             :       return *this;
    3043             :     }
    3044             : 
    3045             :     CallLoweringInfo &setTailCall(bool Value = true) {
    3046      213689 :       IsTailCall = Value;
    3047             :       return *this;
    3048             :     }
    3049             : 
    3050             :     CallLoweringInfo &setDiscardResult(bool Value = true) {
    3051        4721 :       IsReturnValueUsed = !Value;
    3052             :       return *this;
    3053             :     }
    3054             : 
    3055             :     CallLoweringInfo &setConvergent(bool Value = true) {
    3056      209743 :       IsConvergent = Value;
    3057             :       return *this;
    3058             :     }
    3059             : 
    3060             :     CallLoweringInfo &setSExtResult(bool Value = true) {
    3061        5730 :       RetSExt = Value;
    3062             :       return *this;
    3063             :     }
    3064             : 
    3065             :     CallLoweringInfo &setZExtResult(bool Value = true) {
    3066        5721 :       RetZExt = Value;
    3067             :       return *this;
    3068             :     }
    3069             : 
    3070             :     CallLoweringInfo &setIsPatchPoint(bool Value = true) {
    3071         185 :       IsPatchPoint = Value;
    3072             :       return *this;
    3073             :     }
    3074             : 
    3075             :     CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
    3076        2361 :       IsPostTypeLegalization = Value;
    3077             :       return *this;
    3078             :     }
    3079             : 
    3080             :     ArgListTy &getArgs() {
    3081        3970 :       return Args;
    3082             :     }
    3083             :   };
    3084             : 
    3085             :   /// This function lowers an abstract call to a function into an actual call.
    3086             :   /// This returns a pair of operands.  The first element is the return value
    3087             :   /// for the function (if RetTy is not VoidTy).  The second element is the
    3088             :   /// outgoing token chain. It calls LowerCall to do the actual lowering.
    3089             :   std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
    3090             : 
    3091             :   /// This hook must be implemented to lower calls into the specified
    3092             :   /// DAG. The outgoing arguments to the call are described by the Outs array,
    3093             :   /// and the values to be returned by the call are described by the Ins
    3094             :   /// array. The implementation should fill in the InVals array with legal-type
    3095             :   /// return values from the call, and return the resulting token chain value.
    3096             :   virtual SDValue
    3097           0 :     LowerCall(CallLoweringInfo &/*CLI*/,
    3098             :               SmallVectorImpl<SDValue> &/*InVals*/) const {
    3099           0 :     llvm_unreachable("Not Implemented");
    3100             :   }
    3101             : 
    3102             :   /// Target-specific cleanup for formal ByVal parameters.
    3103        1101 :   virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
    3104             : 
    3105             :   /// This hook should be implemented to check whether the return values
    3106             :   /// described by the Outs array can fit into the return registers.  If false
    3107             :   /// is returned, an sret-demotion is performed.
    3108        5239 :   virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
    3109             :                               MachineFunction &/*MF*/, bool /*isVarArg*/,
    3110             :                const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
    3111             :                LLVMContext &/*Context*/) const
    3112             :   {
    3113             :     // Return true by default to get preexisting behavior.
    3114        5239 :     return true;
    3115             :   }
    3116             : 
    3117             :   /// This hook must be implemented to lower outgoing return values, described
    3118             :   /// by the Outs array, into the specified DAG. The implementation should
    3119             :   /// return the resulting token chain value.
    3120           0 :   virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
    3121             :                               bool /*isVarArg*/,
    3122             :                               const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
    3123             :                               const SmallVectorImpl<SDValue> & /*OutVals*/,
    3124             :                               const SDLoc & /*dl*/,
    3125             :                               SelectionDAG & /*DAG*/) const {
    3126           0 :     llvm_unreachable("Not Implemented");
    3127             :   }
    3128             : 
    3129             :   /// Return true if result of the specified node is used by a return node
    3130             :   /// only. It also compute and return the input chain for the tail call.
    3131             :   ///
    3132             :   /// This is used to determine whether it is possible to codegen a libcall as
    3133             :   /// tail call at legalization time.
    3134         402 :   virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
    3135         402 :     return false;
    3136             :   }
    3137             : 
    3138             :   /// Return true if the target may be able emit the call instruction as a tail
    3139             :   /// call. This is used by optimization passes to determine if it's profitable
    3140             :   /// to duplicate return instructions to enable tailcall optimization.
    3141         147 :   virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
    3142         147 :     return false;
    3143             :   }
    3144             : 
    3145             :   /// Return the builtin name for the __builtin___clear_cache intrinsic
    3146             :   /// Default is to invoke the clear cache library call
    3147           2 :   virtual const char * getClearCacheBuiltinName() const {
    3148           2 :     return "__clear_cache";
    3149             :   }
    3150             : 
    3151             :   /// Return the register ID of the name passed in. Used by named register
    3152             :   /// global variables extension. There is no target-independent behaviour
    3153             :   /// so the default action is to bail.
    3154           0 :   virtual unsigned getRegisterByName(const char* RegName, EVT VT,
    3155             :                                      SelectionDAG &DAG) const {
    3156           0 :     report_fatal_error("Named registers not implemented for this target");
    3157             :   }
    3158             : 
    3159             :   /// Return the type that should be used to zero or sign extend a
    3160             :   /// zeroext/signext integer return value.  FIXME: Some C calling conventions
    3161             :   /// require the return type to be promoted, but this is not true all the time,
    3162             :   /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
    3163             :   /// conventions. The frontend should handle this and include all of the
    3164             :   /// necessary information.
    3165        4275 :   virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
    3166             :                                        ISD::NodeType /*ExtendKind*/) const {
    3167       12825 :     EVT MinVT = getRegisterType(Context, MVT::i32);
    3168        4275 :     return VT.bitsLT(MinVT) ? MinVT : VT;
    3169             :   }
    3170             : 
    3171             :   /// For some targets, an LLVM struct type must be broken down into multiple
    3172             :   /// simple types, but the calling convention specifies that the entire struct
    3173             :   /// must be passed in a block of consecutive registers.
    3174             :   virtual bool
    3175      763801 :   functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
    3176             :                                             bool isVarArg) const {
    3177      763801 :     return false;
    3178             :   }
    3179             : 
    3180             :   /// Returns a 0 terminated array of registers that can be safely used as
    3181             :   /// scratch registers.
    3182           0 :   virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
    3183           0 :     return nullptr;
    3184             :   }
    3185             : 
    3186             :   /// This callback is used to prepare for a volatile or atomic load.
    3187             :   /// It takes a chain node as input and returns the chain for the load itself.
    3188             :   ///
    3189             :   /// Having a callback like this is necessary for targets like SystemZ,
    3190             :   /// which allows a CPU to reuse the result of a previous load indefinitely,
    3191             :   /// even if a cache-coherent store is performed by another CPU.  The default
    3192             :   /// implementation does nothing.
    3193       10463 :   virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
    3194             :                                               SelectionDAG &DAG) const {
    3195       10463 :     return Chain;
    3196             :   }
    3197             : 
    3198             :   /// This callback is used to inspect load/store instructions and add
    3199             :   /// target-specific MachineMemOperand flags to them.  The default
    3200             :   /// implementation does nothing.
    3201      612644 :   virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
    3202      612644 :     return MachineMemOperand::MONone;
    3203             :   }
    3204             : 
    3205             :   /// This callback is invoked by the type legalizer to legalize nodes with an
    3206             :   /// illegal operand type but legal result types.  It replaces the
    3207             :   /// LowerOperation callback in the type Legalizer.  The reason we can not do
    3208             :   /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
    3209             :   /// use this callback.
    3210             :   ///
    3211             :   /// TODO: Consider merging with ReplaceNodeResults.
    3212             :   ///
    3213             :   /// The target places new result values for the node in Results (their number
    3214             :   /// and types must exactly match those of the original return values of
    3215             :   /// the node), or leaves Results empty, which indicates that the node is not
    3216             :   /// to be custom lowered after all.
    3217             :   /// The default implementation calls LowerOperation.
    3218             :   virtual void LowerOperationWrapper(SDNode *N,
    3219             :                                      SmallVectorImpl<SDValue> &Results,
    3220             :                                      SelectionDAG &DAG) const;
    3221             : 
    3222             :   /// This callback is invoked for operations that are unsupported by the
    3223             :   /// target, which are registered to use 'custom' lowering, and whose defined
    3224             :   /// values are all legal.  If the target has no operations that require custom
    3225             :   /// lowering, it need not implement this.  The default implementation of this
    3226             :   /// aborts.
    3227             :   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
    3228             : 
    3229             :   /// This callback is invoked when a node result type is illegal for the
    3230             :   /// target, and the operation was registered to use 'custom' lowering for that
    3231             :   /// result type.  The target places new result values for the node in Results
    3232             :   /// (their number and types must exactly match those of the original return
    3233             :   /// values of the node), or leaves Results empty, which indicates that the
    3234             :   /// node is not to be custom lowered after all.
    3235             :   ///
    3236             :   /// If the target has no operations that require custom lowering, it need not
    3237             :   /// implement this.  The default implementation aborts.
    3238           0 :   virtual void ReplaceNodeResults(SDNode * /*N*/,
    3239             :                                   SmallVectorImpl<SDValue> &/*Results*/,
    3240             :                                   SelectionDAG &/*DAG*/) const {
    3241           0 :     llvm_unreachable("ReplaceNodeResults not implemented for this target!");
    3242             :   }
    3243             : 
    3244             :   /// This method returns the name of a target specific DAG node.
    3245             :   virtual const char *getTargetNodeName(unsigned Opcode) const;
    3246             : 
    3247             :   /// This method returns a target specific FastISel object, or null if the
    3248             :   /// target does not support "fast" ISel.
    3249        2524 :   virtual FastISel *createFastISel(FunctionLoweringInfo &,
    3250             :                                    const TargetLibraryInfo *) const {
    3251        2524 :     return nullptr;
    3252             :   }
    3253             : 
    3254             :   bool verifyReturnAddressArgumentIsConstant(SDValue Op,
    3255             :                                              SelectionDAG &DAG) const;
    3256             : 
    3257             :   //===--------------------------------------------------------------------===//
    3258             :   // Inline Asm Support hooks
    3259             :   //
    3260             : 
    3261             :   /// This hook allows the target to expand an inline asm call to be explicit
    3262             :   /// llvm code if it wants to.  This is useful for turning simple inline asms
    3263             :   /// into LLVM intrinsics, which gives the compiler more information about the
    3264             :   /// behavior of the code.
    3265        2427 :   virtual bool ExpandInlineAsm(CallInst *) const {
    3266        2427 :     return false;
    3267             :   }
    3268             : 
    3269             :   enum ConstraintType {
    3270             :     C_Register,            // Constraint represents specific register(s).
    3271             :     C_RegisterClass,       // Constraint represents any of register(s) in class.
    3272             :     C_Memory,              // Memory constraint.
    3273             :     C_Other,               // Something else.
    3274             :     C_Unknown              // Unsupported constraint.
    3275             :   };
    3276             : 
    3277             :   enum ConstraintWeight {
    3278             :     // Generic weights.
    3279             :     CW_Invalid  = -1,     // No match.
    3280             :     CW_Okay     = 0,      // Acceptable.
    3281             :     CW_Good     = 1,      // Good weight.
    3282             :     CW_Better   = 2,      // Better weight.
    3283             :     CW_Best     = 3,      // Best weight.
    3284             : 
    3285             :     // Well-known weights.
    3286             :     CW_SpecificReg  = CW_Okay,    // Specific register operands.
    3287             :     CW_Register     = CW_Good,    // Register operands.
    3288             :     CW_Memory       = CW_Better,  // Memory operands.
    3289             :     CW_Constant     = CW_Best,    // Constant operand.
    3290             :     CW_Default      = CW_Okay     // Default or don't know type.
    3291             :   };
    3292             : 
    3293             :   /// This contains information for each constraint that we are lowering.
    3294     2146704 :   struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
    3295             :     /// This contains the actual string for the code, like "m".  TargetLowering
    3296             :     /// picks the 'best' code from ConstraintInfo::Codes that most closely
    3297             :     /// matches the operand.
    3298             :     std::string ConstraintCode;
    3299             : 
    3300             :     /// Information about the constraint code, e.g. Register, RegisterClass,
    3301             :     /// Memory, Other, Unknown.
    3302             :     TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
    3303             : 
    3304             :     /// If this is the result output operand or a clobber, this is null,
    3305             :     /// otherwise it is the incoming operand to the CallInst.  This gets
    3306             :     /// modified as the asm is processed.
    3307             :     Value *CallOperandVal = nullptr;
    3308             : 
    3309             :     /// The ValueType for the operand value.
    3310             :     MVT ConstraintVT = MVT::Other;
    3311             : 
    3312             :     /// Copy constructor for copying from a ConstraintInfo.
    3313             :     AsmOperandInfo(InlineAsm::ConstraintInfo Info)
    3314      389916 :         : InlineAsm::ConstraintInfo(std::move(Info)) {}
    3315             : 
    3316             :     /// Return true of this is an input operand that is a matching constraint
    3317             :     /// like "4".
    3318             :     bool isMatchingInputConstraint() const;
    3319             : 
    3320             :     /// If this is an input matching constraint, this method returns the output
    3321             :     /// operand it matches.
    3322             :     unsigned getMatchedOperand() const;
    3323             :   };
    3324             : 
    3325             :   using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
    3326             : 
    3327             :   /// Split up the constraint string from the inline assembly value into the
    3328             :   /// specific constraints and their prefixes, and also tie in the associated
    3329             :   /// operand values.  If this returns an empty vector, and if the constraint
    3330             :   /// string itself isn't empty, there was an error parsing.
    3331             :   virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
    3332             :                                                 const TargetRegisterInfo *TRI,
    3333             :                                                 ImmutableCallSite CS) const;
    3334             : 
    3335             :   /// Examine constraint type and operand type and determine a weight value.
    3336             :   /// The operand object must already have been set up with the operand type.
    3337             :   virtual ConstraintWeight getMultipleConstraintMatchWeight(
    3338             :       AsmOperandInfo &info, int maIndex) const;
    3339             : 
    3340             :   /// Examine constraint string and operand type and determine a weight value.
    3341             :   /// The operand object must already have been set up with the operand type.
    3342             :   virtual ConstraintWeight getSingleConstraintMatchWeight(
    3343             :       AsmOperandInfo &info, const char *constraint) const;
    3344             : 
    3345             :   /// Determines the constraint code and constraint type to use for the specific
    3346             :   /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
    3347             :   /// If the actual operand being passed in is available, it can be passed in as
    3348             :   /// Op, otherwise an empty SDValue can be passed.
    3349             :   virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
    3350             :                                       SDValue Op,
    3351             :                                       SelectionDAG *DAG = nullptr) const;
    3352             : 
    3353             :   /// Given a constraint, return the type of constraint it is for this target.
    3354             :   virtual ConstraintType getConstraintType(StringRef Constraint) const;
    3355             : 
    3356             :   /// Given a physical register constraint (e.g.  {edx}), return the register
    3357             :   /// number and the register class for the register.
    3358             :   ///
    3359             :   /// Given a register class constraint, like 'r', if this corresponds directly
    3360             :   /// to an LLVM register class, return a register of 0 and the register class
    3361             :   /// pointer.
    3362             :   ///
    3363             :   /// This should only be used for C_Register constraints.  On error, this
    3364             :   /// returns a register number of 0 and a null register class pointer.
    3365             :   virtual std::pair<unsigned, const TargetRegisterClass *>
    3366             :   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
    3367             :                                StringRef Constraint, MVT VT) const;
    3368             : 
    3369          16 :   virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
    3370             :     if (ConstraintCode == "i")
    3371             :       return InlineAsm::Constraint_i;
    3372             :     else if (ConstraintCode == "m")
    3373             :       return InlineAsm::Constraint_m;
    3374             :     return InlineAsm::Constraint_Unknown;
    3375             :   }
    3376             : 
    3377             :   /// Try to replace an X constraint, which matches anything, with another that
    3378             :   /// has more specific requirements based on the type of the corresponding
    3379             :   /// operand.  This returns null if there is no replacement to make.
    3380             :   virtual const char *LowerXConstraint(EVT ConstraintVT) const;
    3381             : 
    3382             :   /// Lower the specified operand into the Ops vector.  If it is invalid, don't
    3383             :   /// add anything to Ops.
    3384             :   virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
    3385             :                                             std::vector<SDValue> &Ops,
    3386             :                                             SelectionDAG &DAG) const;
    3387             : 
    3388             :   //===--------------------------------------------------------------------===//
    3389             :   // Div utility functions
    3390             :   //
    3391             :   SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
    3392             :                     bool IsAfterLegalization,
    3393             :                     std::vector<SDNode *> *Created) const;
    3394             :   SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
    3395             :                     bool IsAfterLegalization,
    3396             :                     std::vector<SDNode *> *Created) const;
    3397             : 
    3398             :   /// Targets may override this function to provide custom SDIV lowering for
    3399             :   /// power-of-2 denominators.  If the target returns an empty SDValue, LLVM
    3400             :   /// assumes SDIV is expensive and replaces it with a series of other integer
    3401             :   /// operations.
    3402             :   virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
    3403             :                                 SelectionDAG &DAG,
    3404             :                                 std::vector<SDNode *> *Created) const;
    3405             : 
    3406             :   /// Indicate whether this target prefers to combine FDIVs with the same
    3407             :   /// divisor. If the transform should never be done, return zero. If the
    3408             :   /// transform should be done, return the minimum number of divisor uses
    3409             :   /// that must exist.
    3410         240 :   virtual unsigned combineRepeatedFPDivisors() const {
    3411         240 :     return 0;
    3412             :   }
    3413             : 
    3414             :   /// Hooks for building estimates in place of slower divisions and square
    3415             :   /// roots.
    3416             : 
    3417             :   /// Return either a square root or its reciprocal estimate value for the input
    3418             :   /// operand.
    3419             :   /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
    3420             :   /// 'Enabled' as set by a potential default override attribute.
    3421             :   /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
    3422             :   /// refinement iterations required to generate a sufficient (though not
    3423             :   /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
    3424             :   /// The boolean UseOneConstNR output is used to select a Newton-Raphson
    3425             :   /// algorithm implementation that uses either one or two constants.
    3426             :   /// The boolean Reciprocal is used to select whether the estimate is for the
    3427             :   /// square root of the input operand or the reciprocal of its square root.
    3428             :   /// A target may choose to implement its own refinement within this function.
    3429             :   /// If that's true, then return '0' as the number of RefinementSteps to avoid
    3430             :   /// any further refinement of the estimate.
    3431             :   /// An empty SDValue return means no estimate sequence can be created.
    3432           0 :   virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
    3433             :                                   int Enabled, int &RefinementSteps,
    3434             :                                   bool &UseOneConstNR, bool Reciprocal) const {
    3435           0 :     return SDValue();
    3436             :   }
    3437             : 
    3438             :   /// Return a reciprocal estimate value for the input operand.
    3439             :   /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
    3440             :   /// 'Enabled' as set by a potential default override attribute.
    3441             :   /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
    3442             :   /// refinement iterations required to generate a sufficient (though not
    3443             :   /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
    3444             :   /// A target may choose to implement its own refinement within this function.
    3445             :   /// If that's true, then return '0' as the number of RefinementSteps to avoid
    3446             :   /// any further refinement of the estimate.
    3447             :   /// An empty SDValue return means no estimate sequence can be created.
    3448          35 :   virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
    3449             :                                    int Enabled, int &RefinementSteps) const {
    3450          35 :     return SDValue();
    3451             :   }
    3452             : 
    3453             :   //===--------------------------------------------------------------------===//
    3454             :   // Legalization utility functions
    3455             :   //
    3456             : 
    3457             :   /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
    3458             :   /// respectively, each computing an n/2-bit part of the result.
    3459             :   /// \param Result A vector that will be filled with the parts of the result
    3460             :   ///        in little-endian order.
    3461             :   /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
    3462             :   ///        if you want to control how low bits are extracted from the LHS.
    3463             :   /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
    3464             :   /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
    3465             :   /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
    3466             :   /// \returns true if the node has been expanded, false if it has not
    3467             :   bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
    3468             :                       SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
    3469             :                       SelectionDAG &DAG, MulExpansionKind Kind,
    3470             :                       SDValue LL = SDValue(), SDValue LH = SDValue(),
    3471             :                       SDValue RL = SDValue(), SDValue RH = SDValue()) const;
    3472             : 
    3473             :   /// Expand a MUL into two nodes.  One that computes the high bits of
    3474             :   /// the result and one that computes the low bits.
    3475             :   /// \param HiLoVT The value type to use for the Lo and Hi nodes.
    3476             :   /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
    3477             :   ///        if you want to control how low bits are extracted from the LHS.
    3478             :   /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
    3479             :   /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
    3480             :   /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
    3481             :   /// \returns true if the node has been expanded. false if it has not
    3482             :   bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
    3483             :                  SelectionDAG &DAG, MulExpansionKind Kind,
    3484             :                  SDValue LL = SDValue(), SDValue LH = SDValue(),
    3485             :                  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
    3486             : 
    3487             :   /// Expand float(f32) to SINT(i64) conversion
    3488             :   /// \param N Node to expand
    3489             :   /// \param Result output after conversion
    3490             :   /// \returns True, if the expansion was successful, false otherwise
    3491             :   bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
    3492             : 
    3493             :   /// Turn load of vector type into a load of the individual elements.
    3494             :   /// \param LD load to expand
    3495             :   /// \returns MERGE_VALUEs of the scalar loads with their chains.
    3496             :   SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
    3497             : 
    3498             :   // Turn a store of a vector type into stores of the individual elements.
    3499             :   /// \param ST Store with a vector value type
    3500             :   /// \returns MERGE_VALUs of the individual store chains.
    3501             :   SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
    3502             : 
    3503             :   /// Expands an unaligned load to 2 half-size loads for an integer, and
    3504             :   /// possibly more for vectors.
    3505             :   std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
    3506             :                                                   SelectionDAG &DAG) const;
    3507             : 
    3508             :   /// Expands an unaligned store to 2 half-size stores for integer values, and
    3509             :   /// possibly more for vectors.
    3510             :   SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
    3511             : 
    3512             :   /// Increments memory address \p Addr according to the type of the value
    3513             :   /// \p DataVT that should be stored. If the data is stored in compressed
    3514             :   /// form, the memory address should be incremented according to the number of
    3515             :   /// the stored elements. This number is equal to the number of '1's bits
    3516             :   /// in the \p Mask.
    3517             :   /// \p DataVT is a vector type. \p Mask is a vector value.
    3518             :   /// \p DataVT and \p Mask have the same number of vector elements.
    3519             :   SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
    3520             :                                  EVT DataVT, SelectionDAG &DAG,
    3521             :                                  bool IsCompressedMemory) const;
    3522             : 
    3523             :   /// Get a pointer to vector element \p Idx located in memory for a vector of
    3524             :   /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
    3525             :   /// bounds the returned pointer is unspecified, but will be within the vector
    3526             :   /// bounds.
    3527             :   SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
    3528             :                                   SDValue Idx) const;
    3529             : 
    3530             :   //===--------------------------------------------------------------------===//
    3531             :   // Instruction Emitting Hooks
    3532             :   //
    3533             : 
    3534             :   /// This method should be implemented by targets that mark instructions with
    3535             :   /// the 'usesCustomInserter' flag.  These instructions are special in various
    3536             :   /// ways, which require special support to insert.  The specified MachineInstr
    3537             :   /// is created but not inserted into any basic blocks, and this method is
    3538             :   /// called to expand it into a sequence of instructions, potentially also
    3539             :   /// creating new basic blocks and control flow.
    3540             :   /// As long as the returned basic block is different (i.e., we created a new
    3541             :   /// one), the custom inserter is free to modify the rest of \p MBB.
    3542             :   virtual MachineBasicBlock *
    3543             :   EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
    3544             : 
    3545             :   /// This method should be implemented by targets that mark instructions with
    3546             :   /// the 'hasPostISelHook' flag. These instructions must be adjusted after
    3547             :   /// instruction selection by target hooks.  e.g. To fill in optional defs for
    3548             :   /// ARM 's' setting instructions.
    3549             :   virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
    3550             :                                              SDNode *Node) const;
    3551             : 
    3552             :   /// If this function returns true, SelectionDAGBuilder emits a
    3553             :   /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
    3554           3 :   virtual bool useLoadStackGuardNode() const {
    3555           3 :     return false;
    3556             :   }
    3557             : 
    3558           0 :   virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
    3559             :                                       const SDLoc &DL) const {
    3560           0 :     llvm_unreachable("not implemented for this target");
    3561             :   }
    3562             : 
    3563             :   /// Lower TLS global address SDNode for target independent emulated TLS model.
    3564             :   virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
    3565             :                                           SelectionDAG &DAG) const;
    3566             : 
    3567             :   // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
    3568             :   // If we're comparing for equality to zero and isCtlzFast is true, expose the
    3569             :   // fact that this can be implemented as a ctlz/srl pair, so that the dag
    3570             :   // combiner can fold the new nodes.
    3571             :   SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
    3572             : 
    3573             : private:
    3574             :   SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
    3575             :                                ISD::CondCode Cond, DAGCombinerInfo &DCI,
    3576             :                                const SDLoc &DL) const;
    3577             : };
    3578             : 
    3579             : /// Given an LLVM IR type and return type attributes, compute the return value
    3580             : /// EVTs and flags, and optionally also the offsets, if the return value is
    3581             : /// being lowered to memory.
    3582             : void GetReturnInfo(Type *ReturnType, AttributeList attr,
    3583             :                    SmallVectorImpl<ISD::OutputArg> &Outs,
    3584             :                    const TargetLowering &TLI, const DataLayout &DL);
    3585             : 
    3586             : } // end namespace llvm
    3587             : 
    3588             : #endif // LLVM_CODEGEN_TARGETLOWERING_H

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