LCOV - code coverage report
Current view: top level - include/llvm/CodeGen - TargetLowering.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 465 529 87.9 %
Date: 2018-05-20 00:06:23 Functions: 156 195 80.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : ///
      10             : /// \file
      11             : /// This file describes how to lower LLVM code to machine code.  This has two
      12             : /// main components:
      13             : ///
      14             : ///  1. Which ValueTypes are natively supported by the target.
      15             : ///  2. Which operations are supported for supported ValueTypes.
      16             : ///  3. Cost thresholds for alternative implementations of certain operations.
      17             : ///
      18             : /// In addition it has a few other components, like information about FP
      19             : /// immediates.
      20             : ///
      21             : //===----------------------------------------------------------------------===//
      22             : 
      23             : #ifndef LLVM_CODEGEN_TARGETLOWERING_H
      24             : #define LLVM_CODEGEN_TARGETLOWERING_H
      25             : 
      26             : #include "llvm/ADT/APInt.h"
      27             : #include "llvm/ADT/ArrayRef.h"
      28             : #include "llvm/ADT/DenseMap.h"
      29             : #include "llvm/ADT/STLExtras.h"
      30             : #include "llvm/ADT/SmallVector.h"
      31             : #include "llvm/ADT/StringRef.h"
      32             : #include "llvm/Analysis/DivergenceAnalysis.h"
      33             : #include "llvm/CodeGen/DAGCombine.h"
      34             : #include "llvm/CodeGen/ISDOpcodes.h"
      35             : #include "llvm/CodeGen/RuntimeLibcalls.h"
      36             : #include "llvm/CodeGen/SelectionDAG.h"
      37             : #include "llvm/CodeGen/SelectionDAGNodes.h"
      38             : #include "llvm/CodeGen/TargetCallingConv.h"
      39             : #include "llvm/CodeGen/ValueTypes.h"
      40             : #include "llvm/IR/Attributes.h"
      41             : #include "llvm/IR/CallSite.h"
      42             : #include "llvm/IR/CallingConv.h"
      43             : #include "llvm/IR/DataLayout.h"
      44             : #include "llvm/IR/DerivedTypes.h"
      45             : #include "llvm/IR/Function.h"
      46             : #include "llvm/IR/IRBuilder.h"
      47             : #include "llvm/IR/InlineAsm.h"
      48             : #include "llvm/IR/Instruction.h"
      49             : #include "llvm/IR/Instructions.h"
      50             : #include "llvm/IR/Type.h"
      51             : #include "llvm/MC/MCRegisterInfo.h"
      52             : #include "llvm/Support/AtomicOrdering.h"
      53             : #include "llvm/Support/Casting.h"
      54             : #include "llvm/Support/ErrorHandling.h"
      55             : #include "llvm/Support/MachineValueType.h"
      56             : #include "llvm/Target/TargetMachine.h"
      57             : #include <algorithm>
      58             : #include <cassert>
      59             : #include <climits>
      60             : #include <cstdint>
      61             : #include <iterator>
      62             : #include <map>
      63             : #include <string>
      64             : #include <utility>
      65             : #include <vector>
      66             : 
      67             : namespace llvm {
      68             : 
      69             : class BranchProbability;
      70             : class CCState;
      71             : class CCValAssign;
      72             : class Constant;
      73             : class FastISel;
      74             : class FunctionLoweringInfo;
      75             : class GlobalValue;
      76             : class IntrinsicInst;
      77             : struct KnownBits;
      78             : class LLVMContext;
      79             : class MachineBasicBlock;
      80             : class MachineFunction;
      81             : class MachineInstr;
      82             : class MachineJumpTableInfo;
      83             : class MachineLoop;
      84             : class MachineRegisterInfo;
      85             : class MCContext;
      86             : class MCExpr;
      87             : class Module;
      88             : class TargetRegisterClass;
      89             : class TargetLibraryInfo;
      90             : class TargetRegisterInfo;
      91             : class Value;
      92             : 
      93             : namespace Sched {
      94             : 
      95             :   enum Preference {
      96             :     None,             // No preference
      97             :     Source,           // Follow source order.
      98             :     RegPressure,      // Scheduling for lowest register pressure.
      99             :     Hybrid,           // Scheduling for both latency and register pressure.
     100             :     ILP,              // Scheduling for ILP in low register pressure mode.
     101             :     VLIW              // Scheduling for VLIW targets.
     102             :   };
     103             : 
     104             : } // end namespace Sched
     105             : 
     106             : /// This base class for TargetLowering contains the SelectionDAG-independent
     107             : /// parts that can be used from the rest of CodeGen.
     108             : class TargetLoweringBase {
     109             : public:
     110             :   /// This enum indicates whether operations are valid for a target, and if not,
     111             :   /// what action should be used to make them valid.
     112             :   enum LegalizeAction : uint8_t {
     113             :     Legal,      // The target natively supports this operation.
     114             :     Promote,    // This operation should be executed in a larger type.
     115             :     Expand,     // Try to expand this to other ops, otherwise use a libcall.
     116             :     LibCall,    // Don't try to expand this to other ops, always use a libcall.
     117             :     Custom      // Use the LowerOperation hook to implement custom lowering.
     118             :   };
     119             : 
     120             :   /// This enum indicates whether a types are legal for a target, and if not,
     121             :   /// what action should be used to make them valid.
     122             :   enum LegalizeTypeAction : uint8_t {
     123             :     TypeLegal,           // The target natively supports this type.
     124             :     TypePromoteInteger,  // Replace this integer with a larger one.
     125             :     TypeExpandInteger,   // Split this integer into two of half the size.
     126             :     TypeSoftenFloat,     // Convert this float to a same size integer type,
     127             :                          // if an operation is not supported in target HW.
     128             :     TypeExpandFloat,     // Split this float into two of half the size.
     129             :     TypeScalarizeVector, // Replace this one-element vector with its element.
     130             :     TypeSplitVector,     // Split this vector into two of half the size.
     131             :     TypeWidenVector,     // This vector should be widened into a larger vector.
     132             :     TypePromoteFloat     // Replace this float with a larger one.
     133             :   };
     134             : 
     135             :   /// LegalizeKind holds the legalization kind that needs to happen to EVT
     136             :   /// in order to type-legalize it.
     137             :   using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
     138             : 
     139             :   /// Enum that describes how the target represents true/false values.
     140             :   enum BooleanContent {
     141             :     UndefinedBooleanContent,    // Only bit 0 counts, the rest can hold garbage.
     142             :     ZeroOrOneBooleanContent,        // All bits zero except for bit 0.
     143             :     ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
     144             :   };
     145             : 
     146             :   /// Enum that describes what type of support for selects the target has.
     147             :   enum SelectSupportKind {
     148             :     ScalarValSelect,      // The target supports scalar selects (ex: cmov).
     149             :     ScalarCondVectorVal,  // The target supports selects with a scalar condition
     150             :                           // and vector values (ex: cmov).
     151             :     VectorMaskSelect      // The target supports vector selects with a vector
     152             :                           // mask (ex: x86 blends).
     153             :   };
     154             : 
     155             :   /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
     156             :   /// to, if at all. Exists because different targets have different levels of
     157             :   /// support for these atomic instructions, and also have different options
     158             :   /// w.r.t. what they should expand to.
     159             :   enum class AtomicExpansionKind {
     160             :     None,    // Don't expand the instruction.
     161             :     LLSC,    // Expand the instruction into loadlinked/storeconditional; used
     162             :              // by ARM/AArch64.
     163             :     LLOnly,  // Expand the (load) instruction into just a load-linked, which has
     164             :              // greater atomic guarantees than a normal load.
     165             :     CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
     166             :   };
     167             : 
     168             :   /// Enum that specifies when a multiplication should be expanded.
     169             :   enum class MulExpansionKind {
     170             :     Always,            // Always expand the instruction.
     171             :     OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
     172             :                        // or custom.
     173             :   };
     174             : 
     175             :   class ArgListEntry {
     176             :   public:
     177             :     Value *Val = nullptr;
     178             :     SDValue Node = SDValue();
     179             :     Type *Ty = nullptr;
     180             :     bool IsSExt : 1;
     181             :     bool IsZExt : 1;
     182             :     bool IsInReg : 1;
     183             :     bool IsSRet : 1;
     184             :     bool IsNest : 1;
     185             :     bool IsByVal : 1;
     186             :     bool IsInAlloca : 1;
     187             :     bool IsReturned : 1;
     188             :     bool IsSwiftSelf : 1;
     189             :     bool IsSwiftError : 1;
     190             :     uint16_t Alignment = 0;
     191             : 
     192             :     ArgListEntry()
     193      380574 :         : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
     194             :           IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
     195      380574 :           IsSwiftSelf(false), IsSwiftError(false) {}
     196             : 
     197             :     void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
     198             :   };
     199             :   using ArgListTy = std::vector<ArgListEntry>;
     200             : 
     201        5143 :   virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
     202        5143 :                                      ArgListTy &Args) const {};
     203             : 
     204             :   static ISD::NodeType getExtendForContent(BooleanContent Content) {
     205       41718 :     switch (Content) {
     206             :     case UndefinedBooleanContent:
     207             :       // Extend by adding rubbish bits.
     208             :       return ISD::ANY_EXTEND;
     209       40736 :     case ZeroOrOneBooleanContent:
     210             :       // Extend by adding zero bits.
     211             :       return ISD::ZERO_EXTEND;
     212         878 :     case ZeroOrNegativeOneBooleanContent:
     213             :       // Extend by copying the sign bit.
     214             :       return ISD::SIGN_EXTEND;
     215             :     }
     216           0 :     llvm_unreachable("Invalid content kind");
     217             :   }
     218             : 
     219             :   /// NOTE: The TargetMachine owns TLOF.
     220             :   explicit TargetLoweringBase(const TargetMachine &TM);
     221             :   TargetLoweringBase(const TargetLoweringBase &) = delete;
     222             :   TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
     223       64100 :   virtual ~TargetLoweringBase() = default;
     224             : 
     225             : protected:
     226             :   /// Initialize all of the actions to default values.
     227             :   void initActions();
     228             : 
     229             : public:
     230             :   const TargetMachine &getTargetMachine() const { return TM; }
     231             : 
     232        7150 :   virtual bool useSoftFloat() const { return false; }
     233             : 
     234             :   /// Return the pointer type for the given address space, defaults to
     235             :   /// the pointer type from the data layout.
     236             :   /// FIXME: The default needs to be removed once all the code is updated.
     237             :   MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
     238     5887508 :     return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
     239             :   }
     240             : 
     241             :   /// Return the type for frame index, which is determined by
     242             :   /// the alloca address space specified through the data layout.
     243      184378 :   MVT getFrameIndexTy(const DataLayout &DL) const {
     244      368756 :     return getPointerTy(DL, DL.getAllocaAddrSpace());
     245             :   }
     246             : 
     247             :   /// Return the type for operands of fence.
     248             :   /// TODO: Let fence operands be of i32 type and remove this.
     249         516 :   virtual MVT getFenceOperandTy(const DataLayout &DL) const {
     250         516 :     return getPointerTy(DL);
     251             :   }
     252             : 
     253             :   /// EVT is not used in-tree, but is used by out-of-tree target.
     254             :   /// A documentation for this function would be nice...
     255             :   virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
     256             : 
     257             :   EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
     258             :                        bool LegalTypes = true) const;
     259             : 
     260             :   /// Returns the type to be used for the index operand of:
     261             :   /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
     262             :   /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
     263      127605 :   virtual MVT getVectorIdxTy(const DataLayout &DL) const {
     264      127605 :     return getPointerTy(DL);
     265             :   }
     266             : 
     267       55333 :   virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
     268       55333 :     return true;
     269             :   }
     270             : 
     271             :   /// Return true if multiple condition registers are available.
     272             :   bool hasMultipleConditionRegisters() const {
     273             :     return HasMultipleConditionRegisters;
     274             :   }
     275             : 
     276             :   /// Return true if the target has BitExtract instructions.
     277             :   bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
     278             : 
     279             :   /// Return the preferred vector type legalization action.
     280             :   virtual TargetLoweringBase::LegalizeTypeAction
     281     1423479 :   getPreferredVectorAction(EVT VT) const {
     282             :     // The default action for one element vectors is to scalarize
     283     2731529 :     if (VT.getVectorNumElements() == 1)
     284             :       return TypeScalarizeVector;
     285             :     // The default action for other vectors is to promote
     286     1195795 :     return TypePromoteInteger;
     287             :   }
     288             : 
     289             :   // There are two general methods for expanding a BUILD_VECTOR node:
     290             :   //  1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
     291             :   //     them together.
     292             :   //  2. Build the vector on the stack and then load it.
     293             :   // If this function returns true, then method (1) will be used, subject to
     294             :   // the constraint that all of the necessary shuffles are legal (as determined
     295             :   // by isShuffleMaskLegal). If this function returns false, then method (2) is
     296             :   // always used. The vector type, and the number of defined values, are
     297             :   // provided.
     298             :   virtual bool
     299        1532 :   shouldExpandBuildVectorWithShuffles(EVT /* VT */,
     300             :                                       unsigned DefinedValues) const {
     301        1554 :     return DefinedValues < 3;
     302             :   }
     303             : 
     304             :   /// Return true if integer divide is usually cheaper than a sequence of
     305             :   /// several shifts, adds, and multiplies for this target.
     306             :   /// The definition of "cheaper" may depend on whether we're optimizing
     307             :   /// for speed or for size.
     308         592 :   virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
     309             : 
     310             :   /// Return true if the target can handle a standalone remainder operation.
     311           0 :   virtual bool hasStandaloneRem(EVT VT) const {
     312           0 :     return true;
     313             :   }
     314             : 
     315             :   /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
     316          76 :   virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
     317             :     // Default behavior is to replace SQRT(X) with X*RSQRT(X).
     318          76 :     return false;
     319             :   }
     320             : 
     321             :   /// Reciprocal estimate status values used by the functions below.
     322             :   enum ReciprocalEstimate : int {
     323             :     Unspecified = -1,
     324             :     Disabled = 0,
     325             :     Enabled = 1
     326             :   };
     327             : 
     328             :   /// Return a ReciprocalEstimate enum value for a square root of the given type
     329             :   /// based on the function's attributes. If the operation is not overridden by
     330             :   /// the function's attributes, "Unspecified" is returned and target defaults
     331             :   /// are expected to be used for instruction selection.
     332             :   int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
     333             : 
     334             :   /// Return a ReciprocalEstimate enum value for a division of the given type
     335             :   /// based on the function's attributes. If the operation is not overridden by
     336             :   /// the function's attributes, "Unspecified" is returned and target defaults
     337             :   /// are expected to be used for instruction selection.
     338             :   int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
     339             : 
     340             :   /// Return the refinement step count for a square root of the given type based
     341             :   /// on the function's attributes. If the operation is not overridden by
     342             :   /// the function's attributes, "Unspecified" is returned and target defaults
     343             :   /// are expected to be used for instruction selection.
     344             :   int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
     345             : 
     346             :   /// Return the refinement step count for a division of the given type based
     347             :   /// on the function's attributes. If the operation is not overridden by
     348             :   /// the function's attributes, "Unspecified" is returned and target defaults
     349             :   /// are expected to be used for instruction selection.
     350             :   int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
     351             : 
     352             :   /// Returns true if target has indicated at least one type should be bypassed.
     353             :   bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
     354             : 
     355             :   /// Returns map of slow types for division or remainder with corresponding
     356             :   /// fast types
     357             :   const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
     358       13374 :     return BypassSlowDivWidths;
     359             :   }
     360             : 
     361             :   /// Return true if Flow Control is an expensive operation that should be
     362             :   /// avoided.
     363             :   bool isJumpExpensive() const { return JumpIsExpensive; }
     364             : 
     365             :   /// Return true if selects are only cheaper than branches if the branch is
     366             :   /// unlikely to be predicted right.
     367             :   bool isPredictableSelectExpensive() const {
     368             :     return PredictableSelectIsExpensive;
     369             :   }
     370             : 
     371             :   /// If a branch or a select condition is skewed in one direction by more than
     372             :   /// this factor, it is very likely to be predicted correctly.
     373             :   virtual BranchProbability getPredictableBranchThreshold() const;
     374             : 
     375             :   /// Return true if the following transform is beneficial:
     376             :   /// fold (conv (load x)) -> (load (conv*)x)
     377             :   /// On architectures that don't natively support some vector loads
     378             :   /// efficiently, casting the load to a smaller vector of larger types and
     379             :   /// loading is more efficient, however, this can be undone by optimizations in
     380             :   /// dag combiner.
     381       47250 :   virtual bool isLoadBitCastBeneficial(EVT LoadVT,
     382             :                                        EVT BitcastVT) const {
     383             :     // Don't do if we could do an indexed load on the original type, but not on
     384             :     // the new one.
     385       47250 :     if (!LoadVT.isSimple() || !BitcastVT.isSimple())
     386             :       return true;
     387             : 
     388             :     MVT LoadMVT = LoadVT.getSimpleVT();
     389             : 
     390             :     // Don't bother doing this if it's just going to be promoted again later, as
     391             :     // doing so might interfere with other combines.
     392       89337 :     if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
     393       86622 :         getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
     394             :       return false;
     395             : 
     396             :     return true;
     397             :   }
     398             : 
     399             :   /// Return true if the following transform is beneficial:
     400             :   /// (store (y (conv x)), y*)) -> (store x, (x*))
     401       51929 :   virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
     402             :     // Default to the same logic as loads.
     403       51929 :     return isLoadBitCastBeneficial(StoreVT, BitcastVT);
     404             :   }
     405             : 
     406             :   /// Return true if it is expected to be cheaper to do a store of a non-zero
     407             :   /// vector constant with the given size and type for the address space than to
     408             :   /// store the individual scalar element constants.
     409       13317 :   virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
     410             :                                             unsigned NumElem,
     411             :                                             unsigned AddrSpace) const {
     412       13317 :     return false;
     413             :   }
     414             : 
     415             :   /// Allow store merging after legalization in addition to before legalization.
     416             :   /// This may catch stores that do not exist earlier (eg, stores created from
     417             :   /// intrinsics).
     418       58713 :   virtual bool mergeStoresAfterLegalization() const { return true; }
     419             : 
     420             :   /// Returns if it's reasonable to merge stores to MemVT size.
     421        8021 :   virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
     422             :                                 const SelectionDAG &DAG) const {
     423        8021 :     return true;
     424             :   }
     425             : 
     426             :   /// Return true if it is cheap to speculate a call to intrinsic cttz.
     427           8 :   virtual bool isCheapToSpeculateCttz() const {
     428           8 :     return false;
     429             :   }
     430             : 
     431             :   /// Return true if it is cheap to speculate a call to intrinsic ctlz.
     432           5 :   virtual bool isCheapToSpeculateCtlz() const {
     433           5 :     return false;
     434             :   }
     435             : 
     436             :   /// Return true if ctlz instruction is fast.
     437           0 :   virtual bool isCtlzFast() const {
     438           0 :     return false;
     439             :   }
     440             : 
     441             :   /// Return true if it is safe to transform an integer-domain bitwise operation
     442             :   /// into the equivalent floating-point operation. This should be set to true
     443             :   /// if the target has IEEE-754-compliant fabs/fneg operations for the input
     444             :   /// type.
     445       17072 :   virtual bool hasBitPreservingFPLogic(EVT VT) const {
     446       17072 :     return false;
     447             :   }
     448             : 
     449             :   /// Return true if it is cheaper to split the store of a merged int val
     450             :   /// from a pair of smaller values into multiple stores.
     451          57 :   virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
     452          57 :     return false;
     453             :   }
     454             : 
     455             :   /// Return if the target supports combining a
     456             :   /// chain like:
     457             :   /// \code
     458             :   ///   %andResult = and %val1, #mask
     459             :   ///   %icmpResult = icmp %andResult, 0
     460             :   /// \endcode
     461             :   /// into a single machine instruction of a form like:
     462             :   /// \code
     463             :   ///   cc = test %register, #mask
     464             :   /// \endcode
     465          81 :   virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
     466          81 :     return false;
     467             :   }
     468             : 
     469             :   /// Use bitwise logic to make pairs of compares more efficient. For example:
     470             :   /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
     471             :   /// This should be true when it takes more than one instruction to lower
     472             :   /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
     473             :   /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
     474         437 :   virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
     475         437 :     return false;
     476             :   }
     477             : 
     478             :   /// Return the preferred operand type if the target has a quick way to compare
     479             :   /// integer values of the given size. Assume that any legal integer type can
     480             :   /// be compared efficiently. Targets may override this to allow illegal wide
     481             :   /// types to return a vector type if there is support to compare that type.
     482           0 :   virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
     483           0 :     MVT VT = MVT::getIntegerVT(NumBits);
     484           0 :     return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
     485             :   }
     486             : 
     487             :   /// Return true if the target should transform:
     488             :   /// (X & Y) == Y ---> (~X & Y) == 0
     489             :   /// (X & Y) != Y ---> (~X & Y) != 0
     490             :   ///
     491             :   /// This may be profitable if the target has a bitwise and-not operation that
     492             :   /// sets comparison flags. A target may want to limit the transformation based
     493             :   /// on the type of Y or if Y is a constant.
     494             :   ///
     495             :   /// Note that the transform will not occur if Y is known to be a power-of-2
     496             :   /// because a mask and compare of a single bit can be handled by inverting the
     497             :   /// predicate, for example:
     498             :   /// (X & 8) == 8 ---> (X & 8) != 0
     499         569 :   virtual bool hasAndNotCompare(SDValue Y) const {
     500         569 :     return false;
     501             :   }
     502             : 
     503             :   /// Return true if the target has a bitwise and-not operation:
     504             :   /// X = ~A & B
     505             :   /// This can be used to simplify select or other instructions.
     506         735 :   virtual bool hasAndNot(SDValue X) const {
     507             :     // If the target has the more complex version of this operation, assume that
     508             :     // it has this operation too.
     509         735 :     return hasAndNotCompare(X);
     510             :   }
     511             : 
     512             :   /// Return true if the target wants to use the optimization that
     513             :   /// turns ext(promotableInst1(...(promotableInstN(load)))) into
     514             :   /// promotedInst1(...(promotedInstN(ext(load)))).
     515             :   bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
     516             : 
     517             :   /// Return true if the target can combine store(extractelement VectorTy,
     518             :   /// Idx).
     519             :   /// \p Cost[out] gives the cost of that transformation when this is true.
     520       23172 :   virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
     521             :                                          unsigned &Cost) const {
     522       23172 :     return false;
     523             :   }
     524             : 
     525             :   /// Return true if target supports floating point exceptions.
     526             :   bool hasFloatingPointExceptions() const {
     527             :     return HasFloatingPointExceptions;
     528             :   }
     529             : 
     530             :   /// Return true if target always beneficiates from combining into FMA for a
     531             :   /// given value type. This must typically return false on targets where FMA
     532             :   /// takes more cycles to execute than FADD.
     533        4398 :   virtual bool enableAggressiveFMAFusion(EVT VT) const {
     534        4398 :     return false;
     535             :   }
     536             : 
     537             :   /// Return the ValueType of the result of SETCC operations.
     538             :   virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
     539             :                                  EVT VT) const;
     540             : 
     541             :   /// Return the ValueType for comparison libcalls. Comparions libcalls include
     542             :   /// floating point comparion calls, and Ordered/Unordered check calls on
     543             :   /// floating point numbers.
     544             :   virtual
     545             :   MVT::SimpleValueType getCmpLibcallReturnType() const;
     546             : 
     547             :   /// For targets without i1 registers, this gives the nature of the high-bits
     548             :   /// of boolean values held in types wider than i1.
     549             :   ///
     550             :   /// "Boolean values" are special true/false values produced by nodes like
     551             :   /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
     552             :   /// Not to be confused with general values promoted from i1.  Some cpus
     553             :   /// distinguish between vectors of boolean and scalars; the isVec parameter
     554             :   /// selects between the two kinds.  For example on X86 a scalar boolean should
     555             :   /// be zero extended from i1, while the elements of a vector of booleans
     556             :   /// should be sign extended from i1.
     557             :   ///
     558             :   /// Some cpus also treat floating point types the same way as they treat
     559             :   /// vectors instead of the way they treat scalars.
     560             :   BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
     561      843199 :     if (isVec)
     562      126341 :       return BooleanVectorContents;
     563      721605 :     return isFloat ? BooleanFloatContents : BooleanContents;
     564             :   }
     565             : 
     566      840818 :   BooleanContent getBooleanContents(EVT Type) const {
     567     1681636 :     return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
     568             :   }
     569             : 
     570             :   /// Return target scheduling preference.
     571             :   Sched::Preference getSchedulingPreference() const {
     572             :     return SchedPreferenceInfo;
     573             :   }
     574             : 
     575             :   /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
     576             :   /// for different nodes. This function returns the preference (or none) for
     577             :   /// the given node.
     578     3620497 :   virtual Sched::Preference getSchedulingPreference(SDNode *) const {
     579     3620497 :     return Sched::None;
     580             :   }
     581             : 
     582             :   /// Return the register class that should be used for the specified value
     583             :   /// type.
     584     7492434 :   virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
     585     7700219 :     const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
     586             :     assert(RC && "This value type is not natively supported!");
     587     7492434 :     return RC;
     588             :   }
     589             : 
     590             :   /// Return the 'representative' register class for the specified value
     591             :   /// type.
     592             :   ///
     593             :   /// The 'representative' register class is the largest legal super-reg
     594             :   /// register class for the register class of the value type.  For example, on
     595             :   /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
     596             :   /// register class is GR64 on x86_64.
     597      452335 :   virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
     598      865382 :     const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
     599      452335 :     return RC;
     600             :   }
     601             : 
     602             :   /// Return the cost of the 'representative' register class for the specified
     603             :   /// value type.
     604      526327 :   virtual uint8_t getRepRegClassCostFor(MVT VT) const {
     605      526327 :     return RepRegClassCostForVT[VT.SimpleTy];
     606             :   }
     607             : 
     608             :   /// Return true if the target has native support for the specified value type.
     609             :   /// This means that it has a register that directly holds it without
     610             :   /// promotions or expansions.
     611             :   bool isTypeLegal(EVT VT) const {
     612             :     assert(!VT.isSimple() ||
     613             :            (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
     614   149878106 :     return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
     615             :   }
     616             : 
     617             :   class ValueTypeActionImpl {
     618             :     /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
     619             :     /// that indicates how instruction selection should deal with the type.
     620             :     LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
     621             : 
     622             :   public:
     623       34773 :     ValueTypeActionImpl() {
     624       34773 :       std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
     625             :                 TypeLegal);
     626             :     }
     627             : 
     628             :     LegalizeTypeAction getTypeAction(MVT VT) const {
     629    28993912 :       return ValueTypeActions[VT.SimpleTy];
     630             :     }
     631             : 
     632             :     void setTypeAction(MVT VT, LegalizeTypeAction Action) {
     633     3351165 :       ValueTypeActions[VT.SimpleTy] = Action;
     634             :     }
     635             :   };
     636             : 
     637             :   const ValueTypeActionImpl &getValueTypeActions() const {
     638             :     return ValueTypeActions;
     639             :   }
     640             : 
     641             :   /// Return how we should legalize values of this type, either it is already
     642             :   /// legal (return 'Legal') or we need to promote it to a larger type (return
     643             :   /// 'Promote'), or we need to expand it into multiple registers of smaller
     644             :   /// integer type (return 'Expand').  'Custom' is not an option.
     645             :   LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
     646    27406425 :     return getTypeConversion(Context, VT).first;
     647             :   }
     648             :   LegalizeTypeAction getTypeAction(MVT VT) const {
     649             :     return ValueTypeActions.getTypeAction(VT);
     650             :   }
     651             : 
     652             :   /// For types supported by the target, this is an identity function.  For
     653             :   /// types that must be promoted to larger types, this returns the larger type
     654             :   /// to promote to.  For integer types that are larger than the largest integer
     655             :   /// register, this contains one step in the expansion to get to the smaller
     656             :   /// register. For illegal floating point types, this returns the integer type
     657             :   /// to transform to.
     658             :   EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
     659      710913 :     return getTypeConversion(Context, VT).second;
     660             :   }
     661             : 
     662             :   /// For types supported by the target, this is an identity function.  For
     663             :   /// types that must be expanded (i.e. integer types that are larger than the
     664             :   /// largest integer register or illegal floating point types), this returns
     665             :   /// the largest legal type it will be expanded to.
     666       73176 :   EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
     667             :     assert(!VT.isVector());
     668             :     while (true) {
     669       75926 :       switch (getTypeAction(Context, VT)) {
     670       73176 :       case TypeLegal:
     671       73176 :         return VT;
     672        1375 :       case TypeExpandInteger:
     673        1375 :         VT = getTypeToTransformTo(Context, VT);
     674             :         break;
     675           0 :       default:
     676           0 :         llvm_unreachable("Type is not legal nor is it to be expanded!");
     677             :       }
     678             :     }
     679             :   }
     680             : 
     681             :   /// Vector types are broken down into some number of legal first class types.
     682             :   /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
     683             :   /// promoted EVT::f64 values with the X86 FP stack.  Similarly, EVT::v2i64
     684             :   /// turns into 4 EVT::i32 values with both PPC and X86.
     685             :   ///
     686             :   /// This method returns the number of registers needed, and the VT for each
     687             :   /// register.  It also returns the VT and quantity of the intermediate values
     688             :   /// before they are promoted/expanded.
     689             :   unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
     690             :                                   EVT &IntermediateVT,
     691             :                                   unsigned &NumIntermediates,
     692             :                                   MVT &RegisterVT) const;
     693             : 
     694             :   /// Certain targets such as MIPS require that some types such as vectors are
     695             :   /// always broken down into scalars in some contexts. This occurs even if the
     696             :   /// vector type is legal.
     697       11686 :   virtual unsigned getVectorTypeBreakdownForCallingConv(
     698             :       LLVMContext &Context, EVT VT, EVT &IntermediateVT,
     699             :       unsigned &NumIntermediates, MVT &RegisterVT) const {
     700             :     return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
     701       11686 :                                   RegisterVT);
     702             :   }
     703             : 
     704             :   struct IntrinsicInfo {
     705             :     unsigned     opc = 0;          // target opcode
     706             :     EVT          memVT;            // memory VT
     707             : 
     708             :     // value representing memory location
     709             :     PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
     710             : 
     711             :     int          offset = 0;       // offset off of ptrVal
     712             :     unsigned     size = 0;         // the size of the memory location
     713             :                                    // (taken from memVT if zero)
     714             :     unsigned     align = 1;        // alignment
     715             : 
     716             :     MachineMemOperand::Flags flags = MachineMemOperand::MONone;
     717             :     IntrinsicInfo() = default;
     718             :   };
     719             : 
     720             :   /// Given an intrinsic, checks if on the target the intrinsic will need to map
     721             :   /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
     722             :   /// true and store the intrinsic information into the IntrinsicInfo that was
     723             :   /// passed to the function.
     724        3915 :   virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
     725             :                                   MachineFunction &,
     726             :                                   unsigned /*Intrinsic*/) const {
     727        3915 :     return false;
     728             :   }
     729             : 
     730             :   /// Returns true if the target can instruction select the specified FP
     731             :   /// immediate natively. If false, the legalizer will materialize the FP
     732             :   /// immediate as a load from a constant pool.
     733          65 :   virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
     734          65 :     return false;
     735             :   }
     736             : 
     737             :   /// Targets can use this to indicate that they only support *some*
     738             :   /// VECTOR_SHUFFLE operations, those with specific masks.  By default, if a
     739             :   /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
     740             :   /// legal.
     741         566 :   virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
     742         566 :     return true;
     743             :   }
     744             : 
     745             :   /// Returns true if the operation can trap for the value type.
     746             :   ///
     747             :   /// VT must be a legal type. By default, we optimistically assume most
     748             :   /// operations don't trap except for integer divide and remainder.
     749             :   virtual bool canOpTrap(unsigned Op, EVT VT) const;
     750             : 
     751             :   /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
     752             :   /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
     753             :   /// a VAND with a constant pool entry.
     754        1143 :   virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
     755             :                                       EVT /*VT*/) const {
     756        1143 :     return false;
     757             :   }
     758             : 
     759             :   /// Return how this operation should be treated: either it is legal, needs to
     760             :   /// be promoted to a larger size, needs to be expanded to some other code
     761             :   /// sequence, or the target has a custom expander for it.
     762             :   LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
     763    27548389 :     if (VT.isExtended()) return Expand;
     764             :     // If a target-specific SDNode requires legalization, require the target
     765             :     // to provide custom legalization for it.
     766     3293591 :     if (Op >= array_lengthof(OpActions[0])) return Custom;
     767    51173496 :     return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
     768             :   }
     769             : 
     770             :   /// Return true if the specified operation is legal on this target or can be
     771             :   /// made legal with custom lowering. This is used to help guide high-level
     772             :   /// lowering decisions.
     773       92851 :   bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
     774     4854244 :     return (VT == MVT::Other || isTypeLegal(VT)) &&
     775     4248326 :       (getOperationAction(Op, VT) == Legal ||
     776       92851 :        getOperationAction(Op, VT) == Custom);
     777             :   }
     778             : 
     779             :   /// Return true if the specified operation is legal on this target or can be
     780             :   /// made legal using promotion. This is used to help guide high-level lowering
     781             :   /// decisions.
     782      155617 :   bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
     783      155607 :     return (VT == MVT::Other || isTypeLegal(VT)) &&
     784        8346 :       (getOperationAction(Op, VT) == Legal ||
     785      155617 :        getOperationAction(Op, VT) == Promote);
     786             :   }
     787             : 
     788             :   /// Return true if the specified operation is legal on this target or can be
     789             :   /// made legal with custom lowering or using promotion. This is used to help
     790             :   /// guide high-level lowering decisions.
     791       63205 :   bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
     792       60185 :     return (VT == MVT::Other || isTypeLegal(VT)) &&
     793       35637 :       (getOperationAction(Op, VT) == Legal ||
     794       27690 :        getOperationAction(Op, VT) == Custom ||
     795       63205 :        getOperationAction(Op, VT) == Promote);
     796             :   }
     797             : 
     798             :   /// Return true if the operation uses custom lowering, regardless of whether
     799             :   /// the type is legal or not.
     800             :   bool isOperationCustom(unsigned Op, EVT VT) const {
     801             :     return getOperationAction(Op, VT) == Custom;
     802             :   }
     803             : 
     804             :   /// Return true if lowering to a jump table is allowed.
     805        2713 :   virtual bool areJTsAllowed(const Function *Fn) const {
     806        5424 :     if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
     807             :       return false;
     808             : 
     809             :     return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
     810             :            isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
     811             :   }
     812             : 
     813             :   /// Check whether the range [Low,High] fits in a machine word.
     814        3172 :   bool rangeFitsInWord(const APInt &Low, const APInt &High,
     815             :                        const DataLayout &DL) const {
     816             :     // FIXME: Using the pointer type doesn't seem ideal.
     817        3172 :     uint64_t BW = DL.getIndexSizeInBits(0u);
     818        9516 :     uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
     819        3172 :     return Range <= BW;
     820             :   }
     821             : 
     822             :   /// Return true if lowering to a jump table is suitable for a set of case
     823             :   /// clusters which may contain \p NumCases cases, \p Range range of values.
     824             :   /// FIXME: This function check the maximum table size and density, but the
     825             :   /// minimum size is not checked. It would be nice if the minimum size is
     826             :   /// also combined within this function. Currently, the minimum size check is
     827             :   /// performed in findJumpTable() in SelectionDAGBuiler and
     828             :   /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
     829        2177 :   virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
     830             :                                       uint64_t Range) const {
     831        2177 :     const bool OptForSize = SI->getParent()->getParent()->optForSize();
     832        2177 :     const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
     833             :     const unsigned MaxJumpTableSize =
     834        2125 :         OptForSize || getMaximumJumpTableSize() == 0
     835        2638 :             ? UINT_MAX
     836             :             : getMaximumJumpTableSize();
     837             :     // Check whether a range of clusters is dense enough for a jump table.
     838        4143 :     if (Range <= MaxJumpTableSize &&
     839        1966 :         (NumCases * 100 >= Range * MinDensity)) {
     840             :       return true;
     841             :     }
     842        1011 :     return false;
     843             :   }
     844             : 
     845             :   /// Return true if lowering to a bit test is suitable for a set of case
     846             :   /// clusters which contains \p NumDests unique destinations, \p Low and
     847             :   /// \p High as its lowest and highest case values, and expects \p NumCmps
     848             :   /// case value comparisons. Check if the number of destinations, comparison
     849             :   /// metric, and range are all suitable.
     850        2172 :   bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
     851             :                              const APInt &Low, const APInt &High,
     852             :                              const DataLayout &DL) const {
     853             :     // FIXME: I don't think NumCmps is the correct metric: a single case and a
     854             :     // range of cases both require only one branch to lower. Just looking at the
     855             :     // number of clusters and destinations should be enough to decide whether to
     856             :     // build bit tests.
     857             : 
     858             :     // To lower a range with bit tests, the range must fit the bitwidth of a
     859             :     // machine word.
     860        2172 :     if (!rangeFitsInWord(Low, High, DL))
     861             :       return false;
     862             : 
     863             :     // Decide whether it's profitable to lower this range with bit tests. Each
     864             :     // destination requires a bit test and branch, and there is an overall range
     865             :     // check branch. For a small number of clusters, separate comparisons might
     866             :     // be cheaper, and for many destinations, splitting the range might be
     867             :     // better.
     868        3847 :     return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
     869        1895 :            (NumDests == 3 && NumCmps >= 6);
     870             :   }
     871             : 
     872             :   /// Return true if the specified operation is illegal on this target or
     873             :   /// unlikely to be made legal with custom lowering. This is used to help guide
     874             :   /// high-level lowering decisions.
     875             :   bool isOperationExpand(unsigned Op, EVT VT) const {
     876       18277 :     return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
     877             :   }
     878             : 
     879             :   /// Return true if the specified operation is legal on this target.
     880             :   bool isOperationLegal(unsigned Op, EVT VT) const {
     881     1143155 :     return (VT == MVT::Other || isTypeLegal(VT)) &&
     882             :            getOperationAction(Op, VT) == Legal;
     883             :   }
     884             : 
     885             :   /// Return how this load with extension should be treated: either it is legal,
     886             :   /// needs to be promoted to a larger size, needs to be expanded to some other
     887             :   /// code sequence, or the target has a custom expander for it.
     888             :   LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
     889             :                                   EVT MemVT) const {
     890      129263 :     if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
     891      122489 :     unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
     892      121963 :     unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
     893             :     assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
     894             :            MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
     895       83888 :     unsigned Shift = 4 * ExtType;
     896      125264 :     return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
     897             :   }
     898             : 
     899             :   /// Return true if the specified load with extension is legal on this target.
     900             :   bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
     901       32672 :     return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
     902             :   }
     903             : 
     904             :   /// Return true if the specified load with extension is legal or custom
     905             :   /// on this target.
     906             :   bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
     907        2302 :     return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
     908             :            getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
     909             :   }
     910             : 
     911             :   /// Return how this store with truncation should be treated: either it is
     912             :   /// legal, needs to be promoted to a larger size, needs to be expanded to some
     913             :   /// other code sequence, or the target has a custom expander for it.
     914             :   LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
     915      215868 :     if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
     916       42208 :     unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
     917       42208 :     unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
     918             :     assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
     919             :            "Table isn't big enough!");
     920       42208 :     return TruncStoreActions[ValI][MemI];
     921             :   }
     922             : 
     923             :   /// Return true if the specified store with truncation is legal on this
     924             :   /// target.
     925             :   bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
     926       12639 :     return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
     927             :   }
     928             : 
     929             :   /// Return true if the specified store with truncation has solution on this
     930             :   /// target.
     931             :   bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
     932        1891 :     return isTypeLegal(ValVT) &&
     933        1011 :       (getTruncStoreAction(ValVT, MemVT) == Legal ||
     934             :        getTruncStoreAction(ValVT, MemVT) == Custom);
     935             :   }
     936             : 
     937             :   /// Return how the indexed load should be treated: either it is legal, needs
     938             :   /// to be promoted to a larger size, needs to be expanded to some other code
     939             :   /// sequence, or the target has a custom expander for it.
     940             :   LegalizeAction
     941             :   getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
     942             :     assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
     943             :            "Table isn't big enough!");
     944     2301672 :     unsigned Ty = (unsigned)VT.SimpleTy;
     945     2301672 :     return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
     946             :   }
     947             : 
     948             :   /// Return true if the specified indexed load is legal on this target.
     949             :   bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
     950     4603344 :     return VT.isSimple() &&
     951     2259224 :       (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
     952             :        getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
     953             :   }
     954             : 
     955             :   /// Return how the indexed store should be treated: either it is legal, needs
     956             :   /// to be promoted to a larger size, needs to be expanded to some other code
     957             :   /// sequence, or the target has a custom expander for it.
     958             :   LegalizeAction
     959             :   getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
     960             :     assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
     961             :            "Table isn't big enough!");
     962     3020728 :     unsigned Ty = (unsigned)VT.SimpleTy;
     963     3020728 :     return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
     964             :   }
     965             : 
     966             :   /// Return true if the specified indexed load is legal on this target.
     967             :   bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
     968     6041456 :     return VT.isSimple() &&
     969     2991274 :       (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
     970             :        getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
     971             :   }
     972             : 
     973             :   /// Return how the condition code should be treated: either it is legal, needs
     974             :   /// to be expanded to some other code sequence, or the target has a custom
     975             :   /// expander for it.
     976             :   LegalizeAction
     977             :   getCondCodeAction(ISD::CondCode CC, MVT VT) const {
     978             :     assert((unsigned)CC < array_lengthof(CondCodeActions) &&
     979             :            ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
     980             :            "Table isn't big enough!");
     981             :     // See setCondCodeAction for how this is encoded.
     982       87268 :     uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
     983       87951 :     uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
     984       87951 :     LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
     985             :     assert(Action != Promote && "Can't promote condition code!");
     986             :     return Action;
     987             :   }
     988             : 
     989             :   /// Return true if the specified condition code is legal on this target.
     990             :   bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
     991             :     return getCondCodeAction(CC, VT) == Legal;
     992             :   }
     993             : 
     994             :   /// Return true if the specified condition code is legal or custom on this
     995             :   /// target.
     996             :   bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
     997        3434 :     return getCondCodeAction(CC, VT) == Legal ||
     998             :            getCondCodeAction(CC, VT) == Custom;
     999             :   }
    1000             : 
    1001             :   /// If the action for this operation is to promote, this method returns the
    1002             :   /// ValueType to promote to.
    1003      135937 :   MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
    1004             :     assert(getOperationAction(Op, VT) == Promote &&
    1005             :            "This operation isn't promoted!");
    1006             : 
    1007             :     // See if this has an explicit type specified.
    1008             :     std::map<std::pair<unsigned, MVT::SimpleValueType>,
    1009             :              MVT::SimpleValueType>::const_iterator PTTI =
    1010      271874 :       PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
    1011      135937 :     if (PTTI != PromoteToType.end()) return PTTI->second;
    1012             : 
    1013             :     assert((VT.isInteger() || VT.isFloatingPoint()) &&
    1014             :            "Cannot autopromote this type, add it with AddPromotedToType.");
    1015             : 
    1016             :     MVT NVT = VT;
    1017             :     do {
    1018         883 :       NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
    1019             :       assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
    1020             :              "Didn't find type to promote to!");
    1021         877 :     } while (!isTypeLegal(NVT) ||
    1022             :               getOperationAction(Op, NVT) == Promote);
    1023         818 :     return NVT;
    1024             :   }
    1025             : 
    1026             :   /// Return the EVT corresponding to this LLVM type.  This is fixed by the LLVM
    1027             :   /// operations except for the pointer size.  If AllowUnknown is true, this
    1028             :   /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
    1029             :   /// otherwise it will assert.
    1030     8709941 :   EVT getValueType(const DataLayout &DL, Type *Ty,
    1031             :                    bool AllowUnknown = false) const {
    1032             :     // Lower scalar pointers to native pointer types.
    1033             :     if (PointerType *PTy = dyn_cast<PointerType>(Ty))
    1034     3191925 :       return getPointerTy(DL, PTy->getAddressSpace());
    1035             : 
    1036     5518016 :     if (Ty->isVectorTy()) {
    1037             :       VectorType *VTy = cast<VectorType>(Ty);
    1038     1485079 :       Type *Elm = VTy->getElementType();
    1039             :       // Lower vectors of pointers to native pointer types.
    1040             :       if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
    1041             :         EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
    1042        7904 :         Elm = PointerTy.getTypeForEVT(Ty->getContext());
    1043             :       }
    1044             : 
    1045             :       return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
    1046     1485079 :                        VTy->getNumElements());
    1047             :     }
    1048     4032937 :     return EVT::getEVT(Ty, AllowUnknown);
    1049             :   }
    1050             : 
    1051             :   /// Return the MVT corresponding to this LLVM type. See getValueType.
    1052             :   MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
    1053             :                          bool AllowUnknown = false) const {
    1054       73359 :     return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
    1055             :   }
    1056             : 
    1057             :   /// Return the desired alignment for ByVal or InAlloca aggregate function
    1058             :   /// arguments in the caller parameter area.  This is the actual alignment, not
    1059             :   /// its logarithm.
    1060             :   virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
    1061             : 
    1062             :   /// Return the type of registers that this ValueType will eventually require.
    1063             :   MVT getRegisterType(MVT VT) const {
    1064             :     assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
    1065     2947963 :     return RegisterTypeForVT[VT.SimpleTy];
    1066             :   }
    1067             : 
    1068             :   /// Return the type of registers that this ValueType will eventually require.
    1069     2182592 :   MVT getRegisterType(LLVMContext &Context, EVT VT) const {
    1070     2182592 :     if (VT.isSimple()) {
    1071             :       assert((unsigned)VT.getSimpleVT().SimpleTy <
    1072             :                 array_lengthof(RegisterTypeForVT));
    1073     2171181 :       return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
    1074             :     }
    1075       11411 :     if (VT.isVector()) {
    1076        3102 :       EVT VT1;
    1077        3102 :       MVT RegisterVT;
    1078             :       unsigned NumIntermediates;
    1079        3102 :       (void)getVectorTypeBreakdown(Context, VT, VT1,
    1080             :                                    NumIntermediates, RegisterVT);
    1081        3102 :       return RegisterVT;
    1082             :     }
    1083        8309 :     if (VT.isInteger()) {
    1084        8309 :       return getRegisterType(Context, getTypeToTransformTo(Context, VT));
    1085             :     }
    1086           0 :     llvm_unreachable("Unsupported extended type!");
    1087             :   }
    1088             : 
    1089             :   /// Return the number of registers that this ValueType will eventually
    1090             :   /// require.
    1091             :   ///
    1092             :   /// This is one for any types promoted to live in larger registers, but may be
    1093             :   /// more than one for types (like i64) that are split into pieces.  For types
    1094             :   /// like i140, which are first promoted then expanded, it is the number of
    1095             :   /// registers needed to hold all the bits of the original type.  For an i140
    1096             :   /// on a 32 bit machine this means 5 registers.
    1097     2339168 :   unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
    1098     2339168 :     if (VT.isSimple()) {
    1099             :       assert((unsigned)VT.getSimpleVT().SimpleTy <
    1100             :                 array_lengthof(NumRegistersForVT));
    1101     2332439 :       return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
    1102             :     }
    1103        6729 :     if (VT.isVector()) {
    1104        3756 :       EVT VT1;
    1105        3756 :       MVT VT2;
    1106             :       unsigned NumIntermediates;
    1107        3756 :       return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
    1108             :     }
    1109        2973 :     if (VT.isInteger()) {
    1110        2973 :       unsigned BitWidth = VT.getSizeInBits();
    1111        2973 :       unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
    1112        2973 :       return (BitWidth + RegWidth - 1) / RegWidth;
    1113             :     }
    1114           0 :     llvm_unreachable("Unsupported extended type!");
    1115             :   }
    1116             : 
    1117             :   /// Certain combinations of ABIs, Targets and features require that types
    1118             :   /// are legal for some operations and not for other operations.
    1119             :   /// For MIPS all vector types must be passed through the integer register set.
    1120        1237 :   virtual MVT getRegisterTypeForCallingConv(MVT VT) const {
    1121        1237 :     return getRegisterType(VT);
    1122             :   }
    1123             : 
    1124      400003 :   virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
    1125             :                                             EVT VT) const {
    1126     1372902 :     return getRegisterType(Context, VT);
    1127             :   }
    1128             : 
    1129             :   /// Certain targets require unusual breakdowns of certain types. For MIPS,
    1130             :   /// this occurs when a vector type is used, as vector are passed through the
    1131             :   /// integer register set.
    1132      400003 :   virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
    1133             :                                                  EVT VT) const {
    1134     1372902 :     return getNumRegisters(Context, VT);
    1135             :   }
    1136             : 
    1137             :   /// Certain targets have context senstive alignment requirements, where one
    1138             :   /// type has the alignment requirement of another type.
    1139      591143 :   virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
    1140             :                                                  DataLayout DL) const {
    1141      591143 :     return DL.getABITypeAlignment(ArgTy);
    1142             :   }
    1143             : 
    1144             :   /// If true, then instruction selection should seek to shrink the FP constant
    1145             :   /// of the specified type to a smaller type in order to save space and / or
    1146             :   /// reduce runtime.
    1147         284 :   virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
    1148             : 
    1149             :   // Return true if it is profitable to reduce the given load node to a smaller
    1150             :   // type.
    1151             :   //
    1152             :   // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
    1153         951 :   virtual bool shouldReduceLoadWidth(SDNode *Load,
    1154             :                                      ISD::LoadExtType ExtTy,
    1155             :                                      EVT NewVT) const {
    1156         951 :     return true;
    1157             :   }
    1158             : 
    1159             :   /// When splitting a value of the specified type into parts, does the Lo
    1160             :   /// or Hi part come first?  This usually follows the endianness, except
    1161             :   /// for ppcf128, where the Hi part always comes first.
    1162             :   bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
    1163      286123 :     return DL.isBigEndian() || VT == MVT::ppcf128;
    1164             :   }
    1165             : 
    1166             :   /// If true, the target has custom DAG combine transformations that it can
    1167             :   /// perform for the specified node.
    1168             :   bool hasTargetDAGCombine(ISD::NodeType NT) const {
    1169             :     assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
    1170    24899270 :     return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
    1171             :   }
    1172             : 
    1173             :   unsigned getGatherAllAliasesMaxDepth() const {
    1174             :     return GatherAllAliasesMaxDepth;
    1175             :   }
    1176             : 
    1177             :   /// Returns the size of the platform's va_list object.
    1178           0 :   virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
    1179           0 :     return getPointerTy(DL).getSizeInBits();
    1180             :   }
    1181             : 
    1182             :   /// Get maximum # of store operations permitted for llvm.memset
    1183             :   ///
    1184             :   /// This function returns the maximum number of store operations permitted
    1185             :   /// to replace a call to llvm.memset. The value is set by the target at the
    1186             :   /// performance threshold for such a replacement. If OptSize is true,
    1187             :   /// return the limit for functions that have OptSize attribute.
    1188             :   unsigned getMaxStoresPerMemset(bool OptSize) const {
    1189       23280 :     return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
    1190             :   }
    1191             : 
    1192             :   /// Get maximum # of store operations permitted for llvm.memcpy
    1193             :   ///
    1194             :   /// This function returns the maximum number of store operations permitted
    1195             :   /// to replace a call to llvm.memcpy. The value is set by the target at the
    1196             :   /// performance threshold for such a replacement. If OptSize is true,
    1197             :   /// return the limit for functions that have OptSize attribute.
    1198             :   unsigned getMaxStoresPerMemcpy(bool OptSize) const {
    1199        2491 :     return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
    1200             :   }
    1201             : 
    1202             :   /// \brief Get maximum # of store operations to be glued together
    1203             :   ///
    1204             :   /// This function returns the maximum number of store operations permitted
    1205             :   /// to glue together during lowering of llvm.memcpy. The value is set by
    1206             :   //  the target at the performance threshold for such a replacement.
    1207        2214 :   virtual unsigned getMaxGluedStoresPerMemcpy() const {
    1208        2214 :     return MaxGluedStoresPerMemcpy;
    1209             :   }
    1210             : 
    1211             :   /// Get maximum # of load operations permitted for memcmp
    1212             :   ///
    1213             :   /// This function returns the maximum number of load operations permitted
    1214             :   /// to replace a call to memcmp. The value is set by the target at the
    1215             :   /// performance threshold for such a replacement. If OptSize is true,
    1216             :   /// return the limit for functions that have OptSize attribute.
    1217             :   unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
    1218         393 :     return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
    1219             :   }
    1220             : 
    1221             :   /// For memcmp expansion when the memcmp result is only compared equal or
    1222             :   /// not-equal to 0, allow up to this number of load pairs per block. As an
    1223             :   /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
    1224             :   ///   a0 = load2bytes &a[0]
    1225             :   ///   b0 = load2bytes &b[0]
    1226             :   ///   a2 = load1byte  &a[2]
    1227             :   ///   b2 = load1byte  &b[2]
    1228             :   ///   r  = cmp eq (a0 ^ b0 | a2 ^ b2), 0
    1229          22 :   virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
    1230          22 :     return 1;
    1231             :   }
    1232             : 
    1233             :   /// Get maximum # of store operations permitted for llvm.memmove
    1234             :   ///
    1235             :   /// This function returns the maximum number of store operations permitted
    1236             :   /// to replace a call to llvm.memmove. The value is set by the target at the
    1237             :   /// performance threshold for such a replacement. If OptSize is true,
    1238             :   /// return the limit for functions that have OptSize attribute.
    1239             :   unsigned getMaxStoresPerMemmove(bool OptSize) const {
    1240          84 :     return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
    1241             :   }
    1242             : 
    1243             :   /// Determine if the target supports unaligned memory accesses.
    1244             :   ///
    1245             :   /// This function returns true if the target allows unaligned memory accesses
    1246             :   /// of the specified type in the given address space. If true, it also returns
    1247             :   /// whether the unaligned memory access is "fast" in the last argument by
    1248             :   /// reference. This is used, for example, in situations where an array
    1249             :   /// copy/move/set is converted to a sequence of store operations. Its use
    1250             :   /// helps to ensure that such replacements don't generate code that causes an
    1251             :   /// alignment error (trap) on the target machine.
    1252        1181 :   virtual bool allowsMisalignedMemoryAccesses(EVT,
    1253             :                                               unsigned AddrSpace = 0,
    1254             :                                               unsigned Align = 1,
    1255             :                                               bool * /*Fast*/ = nullptr) const {
    1256        1181 :     return false;
    1257             :   }
    1258             : 
    1259             :   /// Return true if the target supports a memory access of this type for the
    1260             :   /// given address space and alignment. If the access is allowed, the optional
    1261             :   /// final parameter returns if the access is also fast (as defined by the
    1262             :   /// target).
    1263             :   bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
    1264             :                           unsigned AddrSpace = 0, unsigned Alignment = 1,
    1265             :                           bool *Fast = nullptr) const;
    1266             : 
    1267             :   /// Returns the target specific optimal type for load and store operations as
    1268             :   /// a result of memset, memcpy, and memmove lowering.
    1269             :   ///
    1270             :   /// If DstAlign is zero that means it's safe to destination alignment can
    1271             :   /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
    1272             :   /// a need to check it against alignment requirement, probably because the
    1273             :   /// source does not need to be loaded. If 'IsMemset' is true, that means it's
    1274             :   /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
    1275             :   /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
    1276             :   /// does not need to be loaded.  It returns EVT::Other if the type should be
    1277             :   /// determined using generic target-independent logic.
    1278         133 :   virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
    1279             :                                   unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
    1280             :                                   bool /*IsMemset*/,
    1281             :                                   bool /*ZeroMemset*/,
    1282             :                                   bool /*MemcpyStrSrc*/,
    1283             :                                   MachineFunction &/*MF*/) const {
    1284         133 :     return MVT::Other;
    1285             :   }
    1286             : 
    1287             :   /// Returns true if it's safe to use load / store of the specified type to
    1288             :   /// expand memcpy / memset inline.
    1289             :   ///
    1290             :   /// This is mostly true for all types except for some special cases. For
    1291             :   /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
    1292             :   /// fstpl which also does type conversion. Note the specified type doesn't
    1293             :   /// have to be legal as the hook is used before type legalization.
    1294         406 :   virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
    1295             : 
    1296             :   /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
    1297             :   bool usesUnderscoreSetJmp() const {
    1298             :     return UseUnderscoreSetJmp;
    1299             :   }
    1300             : 
    1301             :   /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
    1302             :   bool usesUnderscoreLongJmp() const {
    1303             :     return UseUnderscoreLongJmp;
    1304             :   }
    1305             : 
    1306             :   /// Return lower limit for number of blocks in a jump table.
    1307             :   virtual unsigned getMinimumJumpTableEntries() const;
    1308             : 
    1309             :   /// Return lower limit of the density in a jump table.
    1310             :   unsigned getMinimumJumpTableDensity(bool OptForSize) const;
    1311             : 
    1312             :   /// Return upper limit for number of entries in a jump table.
    1313             :   /// Zero if no limit.
    1314             :   unsigned getMaximumJumpTableSize() const;
    1315             : 
    1316         180 :   virtual bool isJumpTableRelative() const {
    1317         186 :     return TM.isPositionIndependent();
    1318             :   }
    1319             : 
    1320             :   /// If a physical register, this specifies the register that
    1321             :   /// llvm.savestack/llvm.restorestack should save and restore.
    1322             :   unsigned getStackPointerRegisterToSaveRestore() const {
    1323             :     return StackPointerRegisterToSaveRestore;
    1324             :   }
    1325             : 
    1326             :   /// If a physical register, this returns the register that receives the
    1327             :   /// exception address on entry to an EH pad.
    1328             :   virtual unsigned
    1329           0 :   getExceptionPointerRegister(const Constant *PersonalityFn) const {
    1330             :     // 0 is guaranteed to be the NoRegister value on all targets
    1331           0 :     return 0;
    1332             :   }
    1333             : 
    1334             :   /// If a physical register, this returns the register that receives the
    1335             :   /// exception typeid on entry to a landing pad.
    1336             :   virtual unsigned
    1337           0 :   getExceptionSelectorRegister(const Constant *PersonalityFn) const {
    1338             :     // 0 is guaranteed to be the NoRegister value on all targets
    1339           0 :     return 0;
    1340             :   }
    1341             : 
    1342           0 :   virtual bool needsFixedCatchObjects() const {
    1343           0 :     report_fatal_error("Funclet EH is not implemented for this target");
    1344             :   }
    1345             : 
    1346             :   /// Returns the target's jmp_buf size in bytes (if never set, the default is
    1347             :   /// 200)
    1348             :   unsigned getJumpBufSize() const {
    1349             :     return JumpBufSize;
    1350             :   }
    1351             : 
    1352             :   /// Returns the target's jmp_buf alignment in bytes (if never set, the default
    1353             :   /// is 0)
    1354             :   unsigned getJumpBufAlignment() const {
    1355             :     return JumpBufAlignment;
    1356             :   }
    1357             : 
    1358             :   /// Return the minimum stack alignment of an argument.
    1359             :   unsigned getMinStackArgumentAlignment() const {
    1360             :     return MinStackArgumentAlignment;
    1361             :   }
    1362             : 
    1363             :   /// Return the minimum function alignment.
    1364             :   unsigned getMinFunctionAlignment() const {
    1365             :     return MinFunctionAlignment;
    1366             :   }
    1367             : 
    1368             :   /// Return the preferred function alignment.
    1369             :   unsigned getPrefFunctionAlignment() const {
    1370             :     return PrefFunctionAlignment;
    1371             :   }
    1372             : 
    1373             :   /// Return the preferred loop alignment.
    1374       25287 :   virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
    1375       26149 :     return PrefLoopAlignment;
    1376             :   }
    1377             : 
    1378             :   /// If the target has a standard location for the stack protector guard,
    1379             :   /// returns the address of that location. Otherwise, returns nullptr.
    1380             :   /// DEPRECATED: please override useLoadStackGuardNode and customize
    1381             :   ///             LOAD_STACK_GUARD, or customize \@llvm.stackguard().
    1382             :   virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
    1383             : 
    1384             :   /// Inserts necessary declarations for SSP (stack protection) purpose.
    1385             :   /// Should be used only when getIRStackGuard returns nullptr.
    1386             :   virtual void insertSSPDeclarations(Module &M) const;
    1387             : 
    1388             :   /// Return the variable that's previously inserted by insertSSPDeclarations,
    1389             :   /// if any, otherwise return nullptr. Should be used only when
    1390             :   /// getIRStackGuard returns nullptr.
    1391             :   virtual Value *getSDagStackGuard(const Module &M) const;
    1392             : 
    1393             :   /// If this function returns true, stack protection checks should XOR the
    1394             :   /// frame pointer (or whichever pointer is used to address locals) into the
    1395             :   /// stack guard value before checking it. getIRStackGuard must return nullptr
    1396             :   /// if this returns true.
    1397         200 :   virtual bool useStackGuardXorFP() const { return false; }
    1398             : 
    1399             :   /// If the target has a standard stack protection check function that
    1400             :   /// performs validation and error handling, returns the function. Otherwise,
    1401             :   /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
    1402             :   /// Should be used only when getIRStackGuard returns nullptr.
    1403             :   virtual Value *getSSPStackGuardCheck(const Module &M) const;
    1404             : 
    1405             : protected:
    1406             :   Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
    1407             :                                             bool UseTLS) const;
    1408             : 
    1409             : public:
    1410             :   /// Returns the target-specific address of the unsafe stack pointer.
    1411             :   virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
    1412             : 
    1413             :   /// Returns the name of the symbol used to emit stack probes or the empty
    1414             :   /// string if not applicable.
    1415           0 :   virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
    1416           0 :     return "";
    1417             :   }
    1418             : 
    1419             :   /// Returns true if a cast between SrcAS and DestAS is a noop.
    1420         465 :   virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
    1421         465 :     return false;
    1422             :   }
    1423             : 
    1424             :   /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
    1425             :   /// are happy to sink it into basic blocks.
    1426         200 :   virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
    1427         200 :     return isNoopAddrSpaceCast(SrcAS, DestAS);
    1428             :   }
    1429             : 
    1430             :   /// Return true if the pointer arguments to CI should be aligned by aligning
    1431             :   /// the object whose address is being passed. If so then MinSize is set to the
    1432             :   /// minimum size the object must be to be aligned and PrefAlign is set to the
    1433             :   /// preferred alignment.
    1434      465572 :   virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
    1435             :                                       unsigned & /*PrefAlign*/) const {
    1436      465572 :     return false;
    1437             :   }
    1438             : 
    1439             :   //===--------------------------------------------------------------------===//
    1440             :   /// \name Helpers for TargetTransformInfo implementations
    1441             :   /// @{
    1442             : 
    1443             :   /// Get the ISD node that corresponds to the Instruction class opcode.
    1444             :   int InstructionOpcodeToISD(unsigned Opcode) const;
    1445             : 
    1446             :   /// Estimate the cost of type-legalization and the legalized type.
    1447             :   std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
    1448             :                                               Type *Ty) const;
    1449             : 
    1450             :   /// @}
    1451             : 
    1452             :   //===--------------------------------------------------------------------===//
    1453             :   /// \name Helpers for atomic expansion.
    1454             :   /// @{
    1455             : 
    1456             :   /// Returns the maximum atomic operation size (in bits) supported by
    1457             :   /// the backend. Atomic operations greater than this size (as well
    1458             :   /// as ones that are not naturally aligned), will be expanded by
    1459             :   /// AtomicExpandPass into an __atomic_* library call.
    1460             :   unsigned getMaxAtomicSizeInBitsSupported() const {
    1461             :     return MaxAtomicSizeInBitsSupported;
    1462             :   }
    1463             : 
    1464             :   /// Returns the size of the smallest cmpxchg or ll/sc instruction
    1465             :   /// the backend supports.  Any smaller operations are widened in
    1466             :   /// AtomicExpandPass.
    1467             :   ///
    1468             :   /// Note that *unlike* operations above the maximum size, atomic ops
    1469             :   /// are still natively supported below the minimum; they just
    1470             :   /// require a more complex expansion.
    1471             :   unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
    1472             : 
    1473             :   /// Whether the target supports unaligned atomic operations.
    1474             :   bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
    1475             : 
    1476             :   /// Whether AtomicExpandPass should automatically insert fences and reduce
    1477             :   /// ordering for this atomic. This should be true for most architectures with
    1478             :   /// weak memory ordering. Defaults to false.
    1479        4574 :   virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
    1480        4574 :     return false;
    1481             :   }
    1482             : 
    1483             :   /// Perform a load-linked operation on Addr, returning a "Value *" with the
    1484             :   /// corresponding pointee type. This may entail some non-trivial operations to
    1485             :   /// truncate or reconstruct types that will be illegal in the backend. See
    1486             :   /// ARMISelLowering for an example implementation.
    1487           0 :   virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
    1488             :                                 AtomicOrdering Ord) const {
    1489           0 :     llvm_unreachable("Load linked unimplemented on this target");
    1490             :   }
    1491             : 
    1492             :   /// Perform a store-conditional operation to Addr. Return the status of the
    1493             :   /// store. This should be 0 if the store succeeded, non-zero otherwise.
    1494           0 :   virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
    1495             :                                       Value *Addr, AtomicOrdering Ord) const {
    1496           0 :     llvm_unreachable("Store conditional unimplemented on this target");
    1497             :   }
    1498             : 
    1499             :   /// Inserts in the IR a target-specific intrinsic specifying a fence.
    1500             :   /// It is called by AtomicExpandPass before expanding an
    1501             :   ///   AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
    1502             :   ///   if shouldInsertFencesForAtomic returns true.
    1503             :   ///
    1504             :   /// Inst is the original atomic instruction, prior to other expansions that
    1505             :   /// may be performed.
    1506             :   ///
    1507             :   /// This function should either return a nullptr, or a pointer to an IR-level
    1508             :   ///   Instruction*. Even complex fence sequences can be represented by a
    1509             :   ///   single Instruction* through an intrinsic to be lowered later.
    1510             :   /// Backends should override this method to produce target-specific intrinsic
    1511             :   ///   for their fences.
    1512             :   /// FIXME: Please note that the default implementation here in terms of
    1513             :   ///   IR-level fences exists for historical/compatibility reasons and is
    1514             :   ///   *unsound* ! Fences cannot, in general, be used to restore sequential
    1515             :   ///   consistency. For example, consider the following example:
    1516             :   /// atomic<int> x = y = 0;
    1517             :   /// int r1, r2, r3, r4;
    1518             :   /// Thread 0:
    1519             :   ///   x.store(1);
    1520             :   /// Thread 1:
    1521             :   ///   y.store(1);
    1522             :   /// Thread 2:
    1523             :   ///   r1 = x.load();
    1524             :   ///   r2 = y.load();
    1525             :   /// Thread 3:
    1526             :   ///   r3 = y.load();
    1527             :   ///   r4 = x.load();
    1528             :   ///  r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
    1529             :   ///  seq_cst. But if they are lowered to monotonic accesses, no amount of
    1530             :   ///  IR-level fences can prevent it.
    1531             :   /// @{
    1532         110 :   virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
    1533             :                                         AtomicOrdering Ord) const {
    1534         110 :     if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
    1535          77 :       return Builder.CreateFence(Ord);
    1536             :     else
    1537             :       return nullptr;
    1538             :   }
    1539             : 
    1540         110 :   virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
    1541             :                                          Instruction *Inst,
    1542             :                                          AtomicOrdering Ord) const {
    1543         110 :     if (isAcquireOrStronger(Ord))
    1544          87 :       return Builder.CreateFence(Ord);
    1545             :     else
    1546             :       return nullptr;
    1547             :   }
    1548             :   /// @}
    1549             : 
    1550             :   // Emits code that executes when the comparison result in the ll/sc
    1551             :   // expansion of a cmpxchg instruction is such that the store-conditional will
    1552             :   // not execute.  This makes it possible to balance out the load-linked with
    1553             :   // a dedicated instruction, if desired.
    1554             :   // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
    1555             :   // be unnecessarily held, except if clrex, inserted by this hook, is executed.
    1556           3 :   virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
    1557             : 
    1558             :   /// Returns true if the given (atomic) store should be expanded by the
    1559             :   /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
    1560          66 :   virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
    1561          66 :     return false;
    1562             :   }
    1563             : 
    1564             :   /// Returns true if arguments should be sign-extended in lib calls.
    1565       17616 :   virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
    1566       17616 :     return IsSigned;
    1567             :   }
    1568             : 
    1569             :   /// Returns how the given (atomic) load should be expanded by the
    1570             :   /// IR-level AtomicExpand pass.
    1571          79 :   virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
    1572          79 :     return AtomicExpansionKind::None;
    1573             :   }
    1574             : 
    1575             :   /// Returns true if the given atomic cmpxchg should be expanded by the
    1576             :   /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
    1577             :   /// (through emitLoadLinked() and emitStoreConditional()).
    1578         515 :   virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
    1579         515 :     return false;
    1580             :   }
    1581             : 
    1582             :   /// Returns how the IR-level AtomicExpand pass should expand the given
    1583             :   /// AtomicRMW, if at all. Default is to never expand.
    1584         613 :   virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
    1585         613 :     return AtomicExpansionKind::None;
    1586             :   }
    1587             : 
    1588             :   /// On some platforms, an AtomicRMW that never actually modifies the value
    1589             :   /// (such as fetch_add of 0) can be turned into a fence followed by an
    1590             :   /// atomic load. This may sound useless, but it makes it possible for the
    1591             :   /// processor to keep the cacheline shared, dramatically improving
    1592             :   /// performance. And such idempotent RMWs are useful for implementing some
    1593             :   /// kinds of locks, see for example (justification + benchmarks):
    1594             :   /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
    1595             :   /// This method tries doing that transformation, returning the atomic load if
    1596             :   /// it succeeds, and nullptr otherwise.
    1597             :   /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
    1598             :   /// another round of expansion.
    1599             :   virtual LoadInst *
    1600           0 :   lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
    1601           0 :     return nullptr;
    1602             :   }
    1603             : 
    1604             :   /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
    1605             :   /// SIGN_EXTEND, or ANY_EXTEND).
    1606         833 :   virtual ISD::NodeType getExtendForAtomicOps() const {
    1607         833 :     return ISD::ZERO_EXTEND;
    1608             :   }
    1609             : 
    1610             :   /// @}
    1611             : 
    1612             :   /// Returns true if we should normalize
    1613             :   /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
    1614             :   /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
    1615             :   /// that it saves us from materializing N0 and N1 in an integer register.
    1616             :   /// Targets that are able to perform and/or on flags should return false here.
    1617       41162 :   virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
    1618             :                                                EVT VT) const {
    1619             :     // If a target has multiple condition registers, then it likely has logical
    1620             :     // operations on those registers.
    1621       41162 :     if (hasMultipleConditionRegisters())
    1622             :       return false;
    1623             :     // Only do the transform if the value won't be split into multiple
    1624             :     // registers.
    1625             :     LegalizeTypeAction Action = getTypeAction(Context, VT);
    1626       30574 :     return Action != TypeExpandInteger && Action != TypeExpandFloat &&
    1627             :       Action != TypeSplitVector;
    1628             :   }
    1629             : 
    1630             :   /// Return true if a select of constants (select Cond, C1, C2) should be
    1631             :   /// transformed into simple math ops with the condition value. For example:
    1632             :   /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
    1633        1943 :   virtual bool convertSelectOfConstantsToMath(EVT VT) const {
    1634        1943 :     return false;
    1635             :   }
    1636             : 
    1637             :   //===--------------------------------------------------------------------===//
    1638             :   // TargetLowering Configuration Methods - These methods should be invoked by
    1639             :   // the derived class constructor to configure this object for the target.
    1640             :   //
    1641             : protected:
    1642             :   /// Specify how the target extends the result of integer and floating point
    1643             :   /// boolean values from i1 to a wider type.  See getBooleanContents.
    1644             :   void setBooleanContents(BooleanContent Ty) {
    1645       34770 :     BooleanContents = Ty;
    1646       34770 :     BooleanFloatContents = Ty;
    1647             :   }
    1648             : 
    1649             :   /// Specify how the target extends the result of integer and floating point
    1650             :   /// boolean values from i1 to a wider type.  See getBooleanContents.
    1651             :   void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
    1652             :     BooleanContents = IntTy;
    1653        1165 :     BooleanFloatContents = FloatTy;
    1654             :   }
    1655             : 
    1656             :   /// Specify how the target extends the result of a vector boolean value from a
    1657             :   /// vector of i1 to a wider type.  See getBooleanContents.
    1658             :   void setBooleanVectorContents(BooleanContent Ty) {
    1659       34078 :     BooleanVectorContents = Ty;
    1660             :   }
    1661             : 
    1662             :   /// Specify the target scheduling preference.
    1663             :   void setSchedulingPreference(Sched::Preference Pref) {
    1664       20679 :     SchedPreferenceInfo = Pref;
    1665             :   }
    1666             : 
    1667             :   /// Indicate whether this target prefers to use _setjmp to implement
    1668             :   /// llvm.setjmp or the version without _.  Defaults to false.
    1669             :   void setUseUnderscoreSetJmp(bool Val) {
    1670       13266 :     UseUnderscoreSetJmp = Val;
    1671             :   }
    1672             : 
    1673             :   /// Indicate whether this target prefers to use _longjmp to implement
    1674             :   /// llvm.longjmp or the version without _.  Defaults to false.
    1675             :   void setUseUnderscoreLongJmp(bool Val) {
    1676       13266 :     UseUnderscoreLongJmp = Val;
    1677             :   }
    1678             : 
    1679             :   /// Indicate the minimum number of blocks to generate jump tables.
    1680             :   void setMinimumJumpTableEntries(unsigned Val);
    1681             : 
    1682             :   /// Indicate the maximum number of entries in jump tables.
    1683             :   /// Set to zero to generate unlimited jump tables.
    1684             :   void setMaximumJumpTableSize(unsigned);
    1685             : 
    1686             :   /// If set to a physical register, this specifies the register that
    1687             :   /// llvm.savestack/llvm.restorestack should save and restore.
    1688             :   void setStackPointerRegisterToSaveRestore(unsigned R) {
    1689       31651 :     StackPointerRegisterToSaveRestore = R;
    1690             :   }
    1691             : 
    1692             :   /// Tells the code generator that the target has multiple (allocatable)
    1693             :   /// condition registers that can be used to store the results of comparisons
    1694             :   /// for use by selects and conditional branches. With multiple condition
    1695             :   /// registers, the code generator will not aggressively sink comparisons into
    1696             :   /// the blocks of their users.
    1697             :   void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
    1698        3861 :     HasMultipleConditionRegisters = hasManyRegs;
    1699             :   }
    1700             : 
    1701             :   /// Tells the code generator that the target has BitExtract instructions.
    1702             :   /// The code generator will aggressively sink "shift"s into the blocks of
    1703             :   /// their users if the users will generate "and" instructions which can be
    1704             :   /// combined with "shift" to BitExtract instructions.
    1705             :   void setHasExtractBitsInsn(bool hasExtractInsn = true) {
    1706        3861 :     HasExtractBitsInsn = hasExtractInsn;
    1707             :   }
    1708             : 
    1709             :   /// Tells the code generator not to expand logic operations on comparison
    1710             :   /// predicates into separate sequences that increase the amount of flow
    1711             :   /// control.
    1712             :   void setJumpIsExpensive(bool isExpensive = true);
    1713             : 
    1714             :   /// Tells the code generator that this target supports floating point
    1715             :   /// exceptions and cares about preserving floating point exception behavior.
    1716             :   void setHasFloatingPointExceptions(bool FPExceptions = true) {
    1717        2489 :     HasFloatingPointExceptions = FPExceptions;
    1718             :   }
    1719             : 
    1720             :   /// Tells the code generator which bitwidths to bypass.
    1721             :   void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
    1722        2306 :     BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
    1723             :   }
    1724             : 
    1725             :   /// Add the specified register class as an available regclass for the
    1726             :   /// specified value type. This indicates the selector can handle values of
    1727             :   /// that class natively.
    1728             :   void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
    1729             :     assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
    1730      248876 :     RegClassForVT[VT.SimpleTy] = RC;
    1731             :   }
    1732             : 
    1733             :   /// Return the largest legal super-reg register class of the register class
    1734             :   /// for the specified type and its associated "cost".
    1735             :   virtual std::pair<const TargetRegisterClass *, uint8_t>
    1736             :   findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
    1737             : 
    1738             :   /// Once all of the register classes are added, this allows us to compute
    1739             :   /// derived properties we expose.
    1740             :   void computeRegisterProperties(const TargetRegisterInfo *TRI);
    1741             : 
    1742             :   /// Indicate that the specified operation does not work with the specified
    1743             :   /// type and indicate what to do about it. Note that VT may refer to either
    1744             :   /// the type of a result or that of an operand of Op.
    1745             :   void setOperationAction(unsigned Op, MVT VT,
    1746             :                           LegalizeAction Action) {
    1747             :     assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
    1748    44499127 :     OpActions[(unsigned)VT.SimpleTy][Op] = Action;
    1749             :   }
    1750             : 
    1751             :   /// Indicate that the specified load with extension does not work with the
    1752             :   /// specified type and indicate what to do about it.
    1753             :   void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
    1754             :                         LegalizeAction Action) {
    1755             :     assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
    1756             :            MemVT.isValid() && "Table isn't big enough!");
    1757             :     assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
    1758       12964 :     unsigned Shift = 4 * ExtType;
    1759   517230431 :     LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
    1760   517230431 :     LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
    1761             :   }
    1762             : 
    1763             :   /// Indicate that the specified truncating store does not work with the
    1764             :   /// specified type and indicate what to do about it.
    1765             :   void setTruncStoreAction(MVT ValVT, MVT MemVT,
    1766             :                            LegalizeAction Action) {
    1767             :     assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
    1768   194739222 :     TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
    1769             :   }
    1770             : 
    1771             :   /// Indicate that the specified indexed load does or does not work with the
    1772             :   /// specified type and indicate what to do abort it.
    1773             :   ///
    1774             :   /// NOTE: All indexed mode loads are initialized to Expand in
    1775             :   /// TargetLowering.cpp
    1776             :   void setIndexedLoadAction(unsigned IdxMode, MVT VT,
    1777             :                             LegalizeAction Action) {
    1778             :     assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
    1779             :            (unsigned)Action < 0xf && "Table isn't big enough!");
    1780             :     // Load action are kept in the upper half.
    1781    15912294 :     IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
    1782      108952 :     IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
    1783             :   }
    1784             : 
    1785             :   /// Indicate that the specified indexed store does or does not work with the
    1786             :   /// specified type and indicate what to do about it.
    1787             :   ///
    1788             :   /// NOTE: All indexed mode stores are initialized to Expand in
    1789             :   /// TargetLowering.cpp
    1790             :   void setIndexedStoreAction(unsigned IdxMode, MVT VT,
    1791             :                              LegalizeAction Action) {
    1792             :     assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
    1793             :            (unsigned)Action < 0xf && "Table isn't big enough!");
    1794             :     // Store action are kept in the lower half.
    1795      108824 :     IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
    1796    15914301 :     IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
    1797             :   }
    1798             : 
    1799             :   /// Indicate that the specified condition code is or isn't supported on the
    1800             :   /// target and indicate what to do about it.
    1801             :   void setCondCodeAction(ISD::CondCode CC, MVT VT,
    1802             :                          LegalizeAction Action) {
    1803             :     assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
    1804             :            "Table isn't big enough!");
    1805             :     assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
    1806             :     /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
    1807             :     /// value and the upper 29 bits index into the second dimension of the array
    1808             :     /// to select what 32-bit value to use.
    1809        9952 :     uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
    1810      156378 :     CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
    1811      156378 :     CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
    1812             :   }
    1813             : 
    1814             :   /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
    1815             :   /// to trying a larger integer/fp until it can find one that works. If that
    1816             :   /// default is insufficient, this method can be used by the target to override
    1817             :   /// the default.
    1818             :   void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
    1819     1308984 :     PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
    1820             :   }
    1821             : 
    1822             :   /// Convenience method to set an operation to Promote and specify the type
    1823             :   /// in a single call.
    1824             :   void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
    1825             :     setOperationAction(Opc, OrigVT, Promote);
    1826             :     AddPromotedToType(Opc, OrigVT, DestVT);
    1827             :   }
    1828             : 
    1829             :   /// Targets should invoke this method for each target independent node that
    1830             :   /// they want to provide a custom DAG combiner for by implementing the
    1831             :   /// PerformDAGCombine virtual method.
    1832             :   void setTargetDAGCombine(ISD::NodeType NT) {
    1833             :     assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
    1834       53380 :     TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
    1835             :   }
    1836             : 
    1837             :   /// Set the target's required jmp_buf buffer size (in bytes); default is 200
    1838             :   void setJumpBufSize(unsigned Size) {
    1839             :     JumpBufSize = Size;
    1840             :   }
    1841             : 
    1842             :   /// Set the target's required jmp_buf buffer alignment (in bytes); default is
    1843             :   /// 0
    1844             :   void setJumpBufAlignment(unsigned Align) {
    1845             :     JumpBufAlignment = Align;
    1846             :   }
    1847             : 
    1848             :   /// Set the target's minimum function alignment (in log2(bytes))
    1849             :   void setMinFunctionAlignment(unsigned Align) {
    1850       19973 :     MinFunctionAlignment = Align;
    1851             :   }
    1852             : 
    1853             :   /// Set the target's preferred function alignment.  This should be set if
    1854             :   /// there is a performance benefit to higher-than-minimum alignment (in
    1855             :   /// log2(bytes))
    1856             :   void setPrefFunctionAlignment(unsigned Align) {
    1857       16409 :     PrefFunctionAlignment = Align;
    1858             :   }
    1859             : 
    1860             :   /// Set the target's preferred loop alignment. Default alignment is zero, it
    1861             :   /// means the target does not care about loop alignment.  The alignment is
    1862             :   /// specified in log2(bytes). The target may also override
    1863             :   /// getPrefLoopAlignment to provide per-loop values.
    1864             :   void setPrefLoopAlignment(unsigned Align) {
    1865       15072 :     PrefLoopAlignment = Align;
    1866             :   }
    1867             : 
    1868             :   /// Set the minimum stack alignment of an argument (in log2(bytes)).
    1869             :   void setMinStackArgumentAlignment(unsigned Align) {
    1870       16009 :     MinStackArgumentAlignment = Align;
    1871             :   }
    1872             : 
    1873             :   /// Set the maximum atomic operation size supported by the
    1874             :   /// backend. Atomic operations greater than this size (as well as
    1875             :   /// ones that are not naturally aligned), will be expanded by
    1876             :   /// AtomicExpandPass into an __atomic_* library call.
    1877             :   void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
    1878        1152 :     MaxAtomicSizeInBitsSupported = SizeInBits;
    1879             :   }
    1880             : 
    1881             :   /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
    1882             :   void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
    1883        1368 :     MinCmpXchgSizeInBits = SizeInBits;
    1884             :   }
    1885             : 
    1886             :   /// Sets whether unaligned atomic operations are supported.
    1887             :   void setSupportsUnalignedAtomics(bool UnalignedSupported) {
    1888             :     SupportsUnalignedAtomics = UnalignedSupported;
    1889             :   }
    1890             : 
    1891             : public:
    1892             :   //===--------------------------------------------------------------------===//
    1893             :   // Addressing mode description hooks (used by LSR etc).
    1894             :   //
    1895             : 
    1896             :   /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
    1897             :   /// instructions reading the address. This allows as much computation as
    1898             :   /// possible to be done in the address mode for that operand. This hook lets
    1899             :   /// targets also pass back when this should be done on intrinsics which
    1900             :   /// load/store.
    1901      236792 :   virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
    1902             :                                     SmallVectorImpl<Value*> &/*Ops*/,
    1903             :                                     Type *&/*AccessTy*/) const {
    1904      236792 :     return false;
    1905             :   }
    1906             : 
    1907             :   /// This represents an addressing mode of:
    1908             :   ///    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
    1909             :   /// If BaseGV is null,  there is no BaseGV.
    1910             :   /// If BaseOffs is zero, there is no base offset.
    1911             :   /// If HasBaseReg is false, there is no base register.
    1912             :   /// If Scale is zero, there is no ScaleReg.  Scale of 1 indicates a reg with
    1913             :   /// no scale.
    1914             :   struct AddrMode {
    1915             :     GlobalValue *BaseGV = nullptr;
    1916             :     int64_t      BaseOffs = 0;
    1917             :     bool         HasBaseReg = false;
    1918             :     int64_t      Scale = 0;
    1919             :     AddrMode() = default;
    1920             :   };
    1921             : 
    1922             :   /// Return true if the addressing mode represented by AM is legal for this
    1923             :   /// target, for a load/store of the specified type.
    1924             :   ///
    1925             :   /// The type may be VoidTy, in which case only return true if the addressing
    1926             :   /// mode is legal for a load/store of any legal type.  TODO: Handle
    1927             :   /// pre/postinc as well.
    1928             :   ///
    1929             :   /// If the address space cannot be determined, it will be -1.
    1930             :   ///
    1931             :   /// TODO: Remove default argument
    1932             :   virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
    1933             :                                      Type *Ty, unsigned AddrSpace,
    1934             :                                      Instruction *I = nullptr) const;
    1935             : 
    1936             :   /// Return the cost of the scaling factor used in the addressing mode
    1937             :   /// represented by AM for this target, for a load/store of the specified type.
    1938             :   ///
    1939             :   /// If the AM is supported, the return value must be >= 0.
    1940             :   /// If the AM is not supported, it returns a negative value.
    1941             :   /// TODO: Handle pre/postinc as well.
    1942             :   /// TODO: Remove default argument
    1943        6434 :   virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
    1944             :                                    Type *Ty, unsigned AS = 0) const {
    1945             :     // Default: assume that any scaling factor used in a legal AM is free.
    1946        6434 :     if (isLegalAddressingMode(DL, AM, Ty, AS))
    1947             :       return 0;
    1948           0 :     return -1;
    1949             :   }
    1950             : 
    1951             :   /// Return true if the specified immediate is legal icmp immediate, that is
    1952             :   /// the target has icmp instructions which can compare a register against the
    1953             :   /// immediate without having to materialize the immediate into a register.
    1954       33847 :   virtual bool isLegalICmpImmediate(int64_t) const {
    1955       33847 :     return true;
    1956             :   }
    1957             : 
    1958             :   /// Return true if the specified immediate is legal add immediate, that is the
    1959             :   /// target has add instructions which can add a register with the immediate
    1960             :   /// without having to materialize the immediate into a register.
    1961        1526 :   virtual bool isLegalAddImmediate(int64_t) const {
    1962        1526 :     return true;
    1963             :   }
    1964             : 
    1965             :   /// Return true if it's significantly cheaper to shift a vector by a uniform
    1966             :   /// scalar than by an amount which will vary across each lane. On x86, for
    1967             :   /// example, there is a "psllw" instruction for the former case, but no simple
    1968             :   /// instruction for a general "a << b" operation on vectors.
    1969        6728 :   virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
    1970        6728 :     return false;
    1971             :   }
    1972             : 
    1973             :   /// Returns true if the opcode is a commutative binary operation.
    1974    36003421 :   virtual bool isCommutativeBinOp(unsigned Opcode) const {
    1975             :     // FIXME: This should get its info from the td file.
    1976    36003421 :     switch (Opcode) {
    1977             :     case ISD::ADD:
    1978             :     case ISD::SMIN:
    1979             :     case ISD::SMAX:
    1980             :     case ISD::UMIN:
    1981             :     case ISD::UMAX:
    1982             :     case ISD::MUL:
    1983             :     case ISD::MULHU:
    1984             :     case ISD::MULHS:
    1985             :     case ISD::SMUL_LOHI:
    1986             :     case ISD::UMUL_LOHI:
    1987             :     case ISD::FADD:
    1988             :     case ISD::FMUL:
    1989             :     case ISD::AND:
    1990             :     case ISD::OR:
    1991             :     case ISD::XOR:
    1992             :     case ISD::SADDO:
    1993             :     case ISD::UADDO:
    1994             :     case ISD::ADDC:
    1995             :     case ISD::ADDE:
    1996             :     case ISD::FMINNUM:
    1997             :     case ISD::FMAXNUM:
    1998             :     case ISD::FMINNAN:
    1999             :     case ISD::FMAXNAN:
    2000             :       return true;
    2001    30011196 :     default: return false;
    2002             :     }
    2003             :   }
    2004             : 
    2005             :   /// Return true if it's free to truncate a value of type FromTy to type
    2006             :   /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
    2007             :   /// by referencing its sub-register AX.
    2008             :   /// Targets must return false when FromTy <= ToTy.
    2009          86 :   virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
    2010          86 :     return false;
    2011             :   }
    2012             : 
    2013             :   /// Return true if a truncation from FromTy to ToTy is permitted when deciding
    2014             :   /// whether a call is in tail position. Typically this means that both results
    2015             :   /// would be assigned to the same register or stack slot, but it could mean
    2016             :   /// the target performs adequate checks of its own before proceeding with the
    2017             :   /// tail call.  Targets must return false when FromTy <= ToTy.
    2018           2 :   virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
    2019           2 :     return false;
    2020             :   }
    2021             : 
    2022        5795 :   virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
    2023        5795 :     return false;
    2024             :   }
    2025             : 
    2026        3328 :   virtual bool isProfitableToHoist(Instruction *I) const { return true; }
    2027             : 
    2028             :   /// Return true if the extension represented by \p I is free.
    2029             :   /// Unlikely the is[Z|FP]ExtFree family which is based on types,
    2030             :   /// this method can use the context provided by \p I to decide
    2031             :   /// whether or not \p I is free.
    2032             :   /// This method extends the behavior of the is[Z|FP]ExtFree family.
    2033             :   /// In other words, if is[Z|FP]Free returns true, then this method
    2034             :   /// returns true as well. The converse is not true.
    2035             :   /// The target can perform the adequate checks by overriding isExtFreeImpl.
    2036             :   /// \pre \p I must be a sign, zero, or fp extension.
    2037       21314 :   bool isExtFree(const Instruction *I) const {
    2038       21314 :     switch (I->getOpcode()) {
    2039         117 :     case Instruction::FPExt:
    2040         234 :       if (isFPExtFree(EVT::getEVT(I->getType()),
    2041         117 :                       EVT::getEVT(I->getOperand(0)->getType())))
    2042             :         return true;
    2043             :       break;
    2044       18699 :     case Instruction::ZExt:
    2045       37398 :       if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
    2046             :         return true;
    2047             :       break;
    2048             :     case Instruction::SExt:
    2049             :       break;
    2050           0 :     default:
    2051           0 :       llvm_unreachable("Instruction is not an extension");
    2052             :     }
    2053       16251 :     return isExtFreeImpl(I);
    2054             :   }
    2055             : 
    2056             :   /// Return true if \p Load and \p Ext can form an ExtLoad.
    2057             :   /// For example, in AArch64
    2058             :   ///   %L = load i8, i8* %ptr
    2059             :   ///   %E = zext i8 %L to i32
    2060             :   /// can be lowered into one load instruction
    2061             :   ///   ldrb w0, [x0]
    2062        5525 :   bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
    2063             :                  const DataLayout &DL) const {
    2064        5525 :     EVT VT = getValueType(DL, Ext->getType());
    2065        5525 :     EVT LoadVT = getValueType(DL, Load->getType());
    2066             : 
    2067             :     // If the load has other users and the truncate is not free, the ext
    2068             :     // probably isn't free.
    2069        8145 :     if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
    2070        2620 :         !isTruncateFree(Ext->getType(), Load->getType()))
    2071             :       return false;
    2072             : 
    2073             :     // Check whether the target supports casts folded into loads.
    2074             :     unsigned LType;
    2075        5525 :     if (isa<ZExtInst>(Ext))
    2076             :       LType = ISD::ZEXTLOAD;
    2077             :     else {
    2078             :       assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
    2079             :       LType = ISD::SEXTLOAD;
    2080             :     }
    2081             : 
    2082        5525 :     return isLoadExtLegal(LType, VT, LoadVT);
    2083             :   }
    2084             : 
    2085             :   /// Return true if any actual instruction that defines a value of type FromTy
    2086             :   /// implicitly zero-extends the value to ToTy in the result register.
    2087             :   ///
    2088             :   /// The function should return true when it is likely that the truncate can
    2089             :   /// be freely folded with an instruction defining a value of FromTy. If
    2090             :   /// the defining instruction is unknown (because you're looking at a
    2091             :   /// function argument, PHI, etc.) then the target may require an
    2092             :   /// explicit truncate, which is not necessarily free, but this function
    2093             :   /// does not deal with those cases.
    2094             :   /// Targets must return false when FromTy >= ToTy.
    2095         323 :   virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
    2096         323 :     return false;
    2097             :   }
    2098             : 
    2099       15850 :   virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
    2100       15850 :     return false;
    2101             :   }
    2102             : 
    2103             :   /// Return true if the target supplies and combines to a paired load
    2104             :   /// two loaded values of type LoadedType next to each other in memory.
    2105             :   /// RequiredAlignment gives the minimal alignment constraints that must be met
    2106             :   /// to be able to select this paired load.
    2107             :   ///
    2108             :   /// This information is *not* used to generate actual paired loads, but it is
    2109             :   /// used to generate a sequence of loads that is easier to combine into a
    2110             :   /// paired load.
    2111             :   /// For instance, something like this:
    2112             :   /// a = load i64* addr
    2113             :   /// b = trunc i64 a to i32
    2114             :   /// c = lshr i64 a, 32
    2115             :   /// d = trunc i64 c to i32
    2116             :   /// will be optimized into:
    2117             :   /// b = load i32* addr1
    2118             :   /// d = load i32* addr2
    2119             :   /// Where addr1 = addr2 +/- sizeof(i32).
    2120             :   ///
    2121             :   /// In other words, unless the target performs a post-isel load combining,
    2122             :   /// this information should not be provided because it will generate more
    2123             :   /// loads.
    2124        7447 :   virtual bool hasPairedLoad(EVT /*LoadedType*/,
    2125             :                              unsigned & /*RequiredAlignment*/) const {
    2126        7447 :     return false;
    2127             :   }
    2128             : 
    2129             :   /// Return true if the target has a vector blend instruction.
    2130        8811 :   virtual bool hasVectorBlend() const { return false; }
    2131             : 
    2132             :   /// Get the maximum supported factor for interleaved memory accesses.
    2133             :   /// Default to be the minimum interleave factor: 2.
    2134           0 :   virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
    2135             : 
    2136             :   /// Lower an interleaved load to target specific intrinsics. Return
    2137             :   /// true on success.
    2138             :   ///
    2139             :   /// \p LI is the vector load instruction.
    2140             :   /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
    2141             :   /// \p Indices is the corresponding indices for each shufflevector.
    2142             :   /// \p Factor is the interleave factor.
    2143           0 :   virtual bool lowerInterleavedLoad(LoadInst *LI,
    2144             :                                     ArrayRef<ShuffleVectorInst *> Shuffles,
    2145             :                                     ArrayRef<unsigned> Indices,
    2146             :                                     unsigned Factor) const {
    2147           0 :     return false;
    2148             :   }
    2149             : 
    2150             :   /// Lower an interleaved store to target specific intrinsics. Return
    2151             :   /// true on success.
    2152             :   ///
    2153             :   /// \p SI is the vector store instruction.
    2154             :   /// \p SVI is the shufflevector to RE-interleave the stored vector.
    2155             :   /// \p Factor is the interleave factor.
    2156           0 :   virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
    2157             :                                      unsigned Factor) const {
    2158           0 :     return false;
    2159             :   }
    2160             : 
    2161             :   /// Return true if zero-extending the specific node Val to type VT2 is free
    2162             :   /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
    2163             :   /// because it's folded such as X86 zero-extending loads).
    2164       10550 :   virtual bool isZExtFree(SDValue Val, EVT VT2) const {
    2165       27662 :     return isZExtFree(Val.getValueType(), VT2);
    2166             :   }
    2167             : 
    2168             :   /// Return true if an fpext operation is free (for instance, because
    2169             :   /// single-precision floating-point numbers are implicitly extended to
    2170             :   /// double-precision).
    2171         408 :   virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
    2172             :     assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
    2173             :            "invalid fpext types");
    2174         408 :     return false;
    2175             :   }
    2176             : 
    2177             :   /// Return true if an fpext operation input to an \p Opcode operation is free
    2178             :   /// (for instance, because half-precision floating-point numbers are
    2179             :   /// implicitly extended to float-precision) for an FMA instruction.
    2180          44 :   virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
    2181             :     assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
    2182             :            "invalid fpext types");
    2183          44 :     return isFPExtFree(DestVT, SrcVT);
    2184             :   }
    2185             : 
    2186             :   /// Return true if folding a vector load into ExtVal (a sign, zero, or any
    2187             :   /// extend node) is profitable.
    2188        3455 :   virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
    2189             : 
    2190             :   /// Return true if an fneg operation is free to the point where it is never
    2191             :   /// worthwhile to replace it with a bitwise operation.
    2192        2043 :   virtual bool isFNegFree(EVT VT) const {
    2193             :     assert(VT.isFloatingPoint());
    2194        2043 :     return false;
    2195             :   }
    2196             : 
    2197             :   /// Return true if an fabs operation is free to the point where it is never
    2198             :   /// worthwhile to replace it with a bitwise operation.
    2199         637 :   virtual bool isFAbsFree(EVT VT) const {
    2200             :     assert(VT.isFloatingPoint());
    2201         637 :     return false;
    2202             :   }
    2203             : 
    2204             :   /// Return true if an FMA operation is faster than a pair of fmul and fadd
    2205             :   /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
    2206             :   /// returns true, otherwise fmuladd is expanded to fmul + fadd.
    2207             :   ///
    2208             :   /// NOTE: This may be called before legalization on types for which FMAs are
    2209             :   /// not legal, but should return true if those types will eventually legalize
    2210             :   /// to types that support FMAs. After legalization, it will only be called on
    2211             :   /// types that support FMAs (via Legal or Custom actions)
    2212        4825 :   virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
    2213        4825 :     return false;
    2214             :   }
    2215             : 
    2216             :   /// Return true if it's profitable to narrow operations of type VT1 to
    2217             :   /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
    2218             :   /// i32 to i16.
    2219         264 :   virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
    2220         264 :     return false;
    2221             :   }
    2222             : 
    2223             :   /// Return true if it is beneficial to convert a load of a constant to
    2224             :   /// just the constant itself.
    2225             :   /// On some targets it might be more efficient to use a combination of
    2226             :   /// arithmetic instructions to materialize the constant instead of loading it
    2227             :   /// from a constant pool.
    2228          12 :   virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
    2229             :                                                  Type *Ty) const {
    2230          12 :     return false;
    2231             :   }
    2232             : 
    2233             :   /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
    2234             :   /// from this source type with this index. This is needed because
    2235             :   /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
    2236             :   /// the first element, and only the target knows which lowering is cheap.
    2237          34 :   virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
    2238             :                                        unsigned Index) const {
    2239          34 :     return false;
    2240             :   }
    2241             : 
    2242             :   // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
    2243             :   // even if the vector itself has multiple uses.
    2244         629 :   virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
    2245         629 :     return false;
    2246             :   }
    2247             : 
    2248             :   // Return true if CodeGenPrepare should consider splitting large offset of a
    2249             :   // GEP to make the GEP fit into the addressing mode and can be sunk into the
    2250             :   // same blocks of its users.
    2251        3170 :   virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
    2252             : 
    2253             :   //===--------------------------------------------------------------------===//
    2254             :   // Runtime Library hooks
    2255             :   //
    2256             : 
    2257             :   /// Rename the default libcall routine name for the specified libcall.
    2258             :   void setLibcallName(RTLIB::Libcall Call, const char *Name) {
    2259     1528031 :     LibcallRoutineNames[Call] = Name;
    2260             :   }
    2261             : 
    2262             :   /// Get the libcall routine name for the specified libcall.
    2263             :   const char *getLibcallName(RTLIB::Libcall Call) const {
    2264       46100 :     return LibcallRoutineNames[Call];
    2265             :   }
    2266             : 
    2267             :   /// Override the default CondCode to be used to test the result of the
    2268             :   /// comparison libcall against zero.
    2269             :   void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
    2270       57280 :     CmpLibcallCCs[Call] = CC;
    2271             :   }
    2272             : 
    2273             :   /// Get the CondCode that's to be used to test the result of the comparison
    2274             :   /// libcall against zero.
    2275             :   ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
    2276         335 :     return CmpLibcallCCs[Call];
    2277             :   }
    2278             : 
    2279             :   /// Set the CallingConv that should be used for the specified libcall.
    2280             :   void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
    2281    18157062 :     LibcallCallingConvs[Call] = CC;
    2282             :   }
    2283             : 
    2284             :   /// Get the CallingConv that should be used for the specified libcall.
    2285             :   CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
    2286       11744 :     return LibcallCallingConvs[Call];
    2287             :   }
    2288             : 
    2289             :   /// Execute target specific actions to finalize target lowering.
    2290             :   /// This is used to set extra flags in MachineFrameInformation and freezing
    2291             :   /// the set of reserved registers.
    2292             :   /// The default implementation just freezes the set of reserved registers.
    2293             :   virtual void finalizeLowering(MachineFunction &MF) const;
    2294             : 
    2295             : private:
    2296             :   const TargetMachine &TM;
    2297             : 
    2298             :   /// Tells the code generator that the target has multiple (allocatable)
    2299             :   /// condition registers that can be used to store the results of comparisons
    2300             :   /// for use by selects and conditional branches. With multiple condition
    2301             :   /// registers, the code generator will not aggressively sink comparisons into
    2302             :   /// the blocks of their users.
    2303             :   bool HasMultipleConditionRegisters;
    2304             : 
    2305             :   /// Tells the code generator that the target has BitExtract instructions.
    2306             :   /// The code generator will aggressively sink "shift"s into the blocks of
    2307             :   /// their users if the users will generate "and" instructions which can be
    2308             :   /// combined with "shift" to BitExtract instructions.
    2309             :   bool HasExtractBitsInsn;
    2310             : 
    2311             :   /// Tells the code generator to bypass slow divide or remainder
    2312             :   /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
    2313             :   /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
    2314             :   /// div/rem when the operands are positive and less than 256.
    2315             :   DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
    2316             : 
    2317             :   /// Tells the code generator that it shouldn't generate extra flow control
    2318             :   /// instructions and should attempt to combine flow control instructions via
    2319             :   /// predication.
    2320             :   bool JumpIsExpensive;
    2321             : 
    2322             :   /// Whether the target supports or cares about preserving floating point
    2323             :   /// exception behavior.
    2324             :   bool HasFloatingPointExceptions;
    2325             : 
    2326             :   /// This target prefers to use _setjmp to implement llvm.setjmp.
    2327             :   ///
    2328             :   /// Defaults to false.
    2329             :   bool UseUnderscoreSetJmp;
    2330             : 
    2331             :   /// This target prefers to use _longjmp to implement llvm.longjmp.
    2332             :   ///
    2333             :   /// Defaults to false.
    2334             :   bool UseUnderscoreLongJmp;
    2335             : 
    2336             :   /// Information about the contents of the high-bits in boolean values held in
    2337             :   /// a type wider than i1. See getBooleanContents.
    2338             :   BooleanContent BooleanContents;
    2339             : 
    2340             :   /// Information about the contents of the high-bits in boolean values held in
    2341             :   /// a type wider than i1. See getBooleanContents.
    2342             :   BooleanContent BooleanFloatContents;
    2343             : 
    2344             :   /// Information about the contents of the high-bits in boolean vector values
    2345             :   /// when the element type is wider than i1. See getBooleanContents.
    2346             :   BooleanContent BooleanVectorContents;
    2347             : 
    2348             :   /// The target scheduling preference: shortest possible total cycles or lowest
    2349             :   /// register usage.
    2350             :   Sched::Preference SchedPreferenceInfo;
    2351             : 
    2352             :   /// The size, in bytes, of the target's jmp_buf buffers
    2353             :   unsigned JumpBufSize;
    2354             : 
    2355             :   /// The alignment, in bytes, of the target's jmp_buf buffers
    2356             :   unsigned JumpBufAlignment;
    2357             : 
    2358             :   /// The minimum alignment that any argument on the stack needs to have.
    2359             :   unsigned MinStackArgumentAlignment;
    2360             : 
    2361             :   /// The minimum function alignment (used when optimizing for size, and to
    2362             :   /// prevent explicitly provided alignment from leading to incorrect code).
    2363             :   unsigned MinFunctionAlignment;
    2364             : 
    2365             :   /// The preferred function alignment (used when alignment unspecified and
    2366             :   /// optimizing for speed).
    2367             :   unsigned PrefFunctionAlignment;
    2368             : 
    2369             :   /// The preferred loop alignment.
    2370             :   unsigned PrefLoopAlignment;
    2371             : 
    2372             :   /// Size in bits of the maximum atomics size the backend supports.
    2373             :   /// Accesses larger than this will be expanded by AtomicExpandPass.
    2374             :   unsigned MaxAtomicSizeInBitsSupported;
    2375             : 
    2376             :   /// Size in bits of the minimum cmpxchg or ll/sc operation the
    2377             :   /// backend supports.
    2378             :   unsigned MinCmpXchgSizeInBits;
    2379             : 
    2380             :   /// This indicates if the target supports unaligned atomic operations.
    2381             :   bool SupportsUnalignedAtomics;
    2382             : 
    2383             :   /// If set to a physical register, this specifies the register that
    2384             :   /// llvm.savestack/llvm.restorestack should save and restore.
    2385             :   unsigned StackPointerRegisterToSaveRestore;
    2386             : 
    2387             :   /// This indicates the default register class to use for each ValueType the
    2388             :   /// target supports natively.
    2389             :   const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
    2390             :   unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
    2391             :   MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
    2392             : 
    2393             :   /// This indicates the "representative" register class to use for each
    2394             :   /// ValueType the target supports natively. This information is used by the
    2395             :   /// scheduler to track register pressure. By default, the representative
    2396             :   /// register class is the largest legal super-reg register class of the
    2397             :   /// register class of the specified type. e.g. On x86, i8, i16, and i32's
    2398             :   /// representative class would be GR32.
    2399             :   const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
    2400             : 
    2401             :   /// This indicates the "cost" of the "representative" register class for each
    2402             :   /// ValueType. The cost is used by the scheduler to approximate register
    2403             :   /// pressure.
    2404             :   uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
    2405             : 
    2406             :   /// For any value types we are promoting or expanding, this contains the value
    2407             :   /// type that we are changing to.  For Expanded types, this contains one step
    2408             :   /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
    2409             :   /// (e.g. i64 -> i16).  For types natively supported by the system, this holds
    2410             :   /// the same type (e.g. i32 -> i32).
    2411             :   MVT TransformToType[MVT::LAST_VALUETYPE];
    2412             : 
    2413             :   /// For each operation and each value type, keep a LegalizeAction that
    2414             :   /// indicates how instruction selection should deal with the operation.  Most
    2415             :   /// operations are Legal (aka, supported natively by the target), but
    2416             :   /// operations that are not should be described.  Note that operations on
    2417             :   /// non-legal value types are not described here.
    2418             :   LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
    2419             : 
    2420             :   /// For each load extension type and each value type, keep a LegalizeAction
    2421             :   /// that indicates how instruction selection should deal with a load of a
    2422             :   /// specific value type and extension type. Uses 4-bits to store the action
    2423             :   /// for each of the 4 load ext types.
    2424             :   uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
    2425             : 
    2426             :   /// For each value type pair keep a LegalizeAction that indicates whether a
    2427             :   /// truncating store of a specific value type and truncating type is legal.
    2428             :   LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
    2429             : 
    2430             :   /// For each indexed mode and each value type, keep a pair of LegalizeAction
    2431             :   /// that indicates how instruction selection should deal with the load /
    2432             :   /// store.
    2433             :   ///
    2434             :   /// The first dimension is the value_type for the reference. The second
    2435             :   /// dimension represents the various modes for load store.
    2436             :   uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
    2437             : 
    2438             :   /// For each condition code (ISD::CondCode) keep a LegalizeAction that
    2439             :   /// indicates how instruction selection should deal with the condition code.
    2440             :   ///
    2441             :   /// Because each CC action takes up 4 bits, we need to have the array size be
    2442             :   /// large enough to fit all of the value types. This can be done by rounding
    2443             :   /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
    2444             :   uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
    2445             : 
    2446             : protected:
    2447             :   ValueTypeActionImpl ValueTypeActions;
    2448             : 
    2449             : private:
    2450             :   LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
    2451             : 
    2452             :   /// Targets can specify ISD nodes that they would like PerformDAGCombine
    2453             :   /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
    2454             :   /// array.
    2455             :   unsigned char
    2456             :   TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
    2457             : 
    2458             :   /// For operations that must be promoted to a specific type, this holds the
    2459             :   /// destination type.  This map should be sparse, so don't hold it as an
    2460             :   /// array.
    2461             :   ///
    2462             :   /// Targets add entries to this map with AddPromotedToType(..), clients access
    2463             :   /// this with getTypeToPromoteTo(..).
    2464             :   std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
    2465             :     PromoteToType;
    2466             : 
    2467             :   /// Stores the name each libcall.
    2468             :   const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
    2469             : 
    2470             :   /// The ISD::CondCode that should be used to test the result of each of the
    2471             :   /// comparison libcall against zero.
    2472             :   ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
    2473             : 
    2474             :   /// Stores the CallingConv that should be used for each libcall.
    2475             :   CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
    2476             : 
    2477             :   /// Set default libcall names and calling conventions.
    2478             :   void InitLibcalls(const Triple &TT);
    2479             : 
    2480             : protected:
    2481             :   /// Return true if the extension represented by \p I is free.
    2482             :   /// \pre \p I is a sign, zero, or fp extension and
    2483             :   ///      is[Z|FP]ExtFree of the related types is not true.
    2484       15783 :   virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
    2485             : 
    2486             :   /// Depth that GatherAllAliases should should continue looking for chain
    2487             :   /// dependencies when trying to find a more preferable chain. As an
    2488             :   /// approximation, this should be more than the number of consecutive stores
    2489             :   /// expected to be merged.
    2490             :   unsigned GatherAllAliasesMaxDepth;
    2491             : 
    2492             :   /// Specify maximum number of store instructions per memset call.
    2493             :   ///
    2494             :   /// When lowering \@llvm.memset this field specifies the maximum number of
    2495             :   /// store operations that may be substituted for the call to memset. Targets
    2496             :   /// must set this value based on the cost threshold for that target. Targets
    2497             :   /// should assume that the memset will be done using as many of the largest
    2498             :   /// store operations first, followed by smaller ones, if necessary, per
    2499             :   /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
    2500             :   /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
    2501             :   /// store.  This only applies to setting a constant array of a constant size.
    2502             :   unsigned MaxStoresPerMemset;
    2503             : 
    2504             :   /// Maximum number of stores operations that may be substituted for the call
    2505             :   /// to memset, used for functions with OptSize attribute.
    2506             :   unsigned MaxStoresPerMemsetOptSize;
    2507             : 
    2508             :   /// Specify maximum bytes of store instructions per memcpy call.
    2509             :   ///
    2510             :   /// When lowering \@llvm.memcpy this field specifies the maximum number of
    2511             :   /// store operations that may be substituted for a call to memcpy. Targets
    2512             :   /// must set this value based on the cost threshold for that target. Targets
    2513             :   /// should assume that the memcpy will be done using as many of the largest
    2514             :   /// store operations first, followed by smaller ones, if necessary, per
    2515             :   /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
    2516             :   /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
    2517             :   /// and one 1-byte store. This only applies to copying a constant array of
    2518             :   /// constant size.
    2519             :   unsigned MaxStoresPerMemcpy;
    2520             : 
    2521             : 
    2522             :   /// \brief Specify max number of store instructions to glue in inlined memcpy.
    2523             :   ///
    2524             :   /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
    2525             :   /// of store instructions to keep together. This helps in pairing and
    2526             :   //  vectorization later on.
    2527             :   unsigned MaxGluedStoresPerMemcpy = 0;
    2528             : 
    2529             :   /// Maximum number of store operations that may be substituted for a call to
    2530             :   /// memcpy, used for functions with OptSize attribute.
    2531             :   unsigned MaxStoresPerMemcpyOptSize;
    2532             :   unsigned MaxLoadsPerMemcmp;
    2533             :   unsigned MaxLoadsPerMemcmpOptSize;
    2534             : 
    2535             :   /// Specify maximum bytes of store instructions per memmove call.
    2536             :   ///
    2537             :   /// When lowering \@llvm.memmove this field specifies the maximum number of
    2538             :   /// store instructions that may be substituted for a call to memmove. Targets
    2539             :   /// must set this value based on the cost threshold for that target. Targets
    2540             :   /// should assume that the memmove will be done using as many of the largest
    2541             :   /// store operations first, followed by smaller ones, if necessary, per
    2542             :   /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
    2543             :   /// with 8-bit alignment would result in nine 1-byte stores.  This only
    2544             :   /// applies to copying a constant array of constant size.
    2545             :   unsigned MaxStoresPerMemmove;
    2546             : 
    2547             :   /// Maximum number of store instructions that may be substituted for a call to
    2548             :   /// memmove, used for functions with OptSize attribute.
    2549             :   unsigned MaxStoresPerMemmoveOptSize;
    2550             : 
    2551             :   /// Tells the code generator that select is more expensive than a branch if
    2552             :   /// the branch is usually predicted right.
    2553             :   bool PredictableSelectIsExpensive;
    2554             : 
    2555             :   /// \see enableExtLdPromotion.
    2556             :   bool EnableExtLdPromotion;
    2557             : 
    2558             :   /// Return true if the value types that can be represented by the specified
    2559             :   /// register class are all legal.
    2560             :   bool isLegalRC(const TargetRegisterInfo &TRI,
    2561             :                  const TargetRegisterClass &RC) const;
    2562             : 
    2563             :   /// Replace/modify any TargetFrameIndex operands with a targte-dependent
    2564             :   /// sequence of memory operands that is recognized by PrologEpilogInserter.
    2565             :   MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
    2566             :                                     MachineBasicBlock *MBB) const;
    2567             : 
    2568             :   /// Replace/modify the XRay custom event operands with target-dependent
    2569             :   /// details.
    2570             :   MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
    2571             :                                          MachineBasicBlock *MBB) const;
    2572             : 
    2573             :   /// Replace/modify the XRay typed event operands with target-dependent
    2574             :   /// details.
    2575             :   MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
    2576             :                                         MachineBasicBlock *MBB) const;
    2577             : };
    2578             : 
    2579             : /// This class defines information used to lower LLVM code to legal SelectionDAG
    2580             : /// operators that the target instruction selector can accept natively.
    2581             : ///
    2582             : /// This class also defines callbacks that targets must implement to lower
    2583             : /// target-specific constructs to SelectionDAG operators.
    2584       32050 : class TargetLowering : public TargetLoweringBase {
    2585             : public:
    2586             :   struct DAGCombinerInfo;
    2587             : 
    2588             :   TargetLowering(const TargetLowering &) = delete;
    2589             :   TargetLowering &operator=(const TargetLowering &) = delete;
    2590             : 
    2591             :   /// NOTE: The TargetMachine owns TLOF.
    2592             :   explicit TargetLowering(const TargetMachine &TM);
    2593             : 
    2594             :   bool isPositionIndependent() const;
    2595             : 
    2596    14333392 :   virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
    2597             :                                           FunctionLoweringInfo *FLI,
    2598             :                                           DivergenceAnalysis *DA) const {
    2599    14333392 :     return false;
    2600             :   }
    2601             : 
    2602    12577492 :   virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
    2603    12577492 :     return false;
    2604             :   }
    2605             : 
    2606             :   /// Returns true by value, base pointer and offset pointer and addressing mode
    2607             :   /// by reference if the node's address can be legally represented as
    2608             :   /// pre-indexed load / store address.
    2609           0 :   virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
    2610             :                                          SDValue &/*Offset*/,
    2611             :                                          ISD::MemIndexedMode &/*AM*/,
    2612             :                                          SelectionDAG &/*DAG*/) const {
    2613           0 :     return false;
    2614             :   }
    2615             : 
    2616             :   /// Returns true by value, base pointer and offset pointer and addressing mode
    2617             :   /// by reference if this node can be combined with a load / store to form a
    2618             :   /// post-indexed load / store.
    2619           0 :   virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
    2620             :                                           SDValue &/*Base*/,
    2621             :                                           SDValue &/*Offset*/,
    2622             :                                           ISD::MemIndexedMode &/*AM*/,
    2623             :                                           SelectionDAG &/*DAG*/) const {
    2624           0 :     return false;
    2625             :   }
    2626             : 
    2627             :   /// Return the entry encoding for a jump table in the current function.  The
    2628             :   /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
    2629             :   virtual unsigned getJumpTableEncoding() const;
    2630             : 
    2631             :   virtual const MCExpr *
    2632           0 :   LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
    2633             :                             const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
    2634             :                             MCContext &/*Ctx*/) const {
    2635           0 :     llvm_unreachable("Need to implement this hook if target has custom JTIs");
    2636             :   }
    2637             : 
    2638             :   /// Returns relocation base for the given PIC jumptable.
    2639             :   virtual SDValue getPICJumpTableRelocBase(SDValue Table,
    2640             :                                            SelectionDAG &DAG) const;
    2641             : 
    2642             :   /// This returns the relocation base for the given PIC jumptable, the same as
    2643             :   /// getPICJumpTableRelocBase, but as an MCExpr.
    2644             :   virtual const MCExpr *
    2645             :   getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
    2646             :                                unsigned JTI, MCContext &Ctx) const;
    2647             : 
    2648             :   /// Return true if folding a constant offset with the given GlobalAddress is
    2649             :   /// legal.  It is frequently not legal in PIC relocation models.
    2650             :   virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
    2651             : 
    2652             :   bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
    2653             :                             SDValue &Chain) const;
    2654             : 
    2655             :   void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
    2656             :                            SDValue &NewRHS, ISD::CondCode &CCCode,
    2657             :                            const SDLoc &DL) const;
    2658             : 
    2659             :   /// Returns a pair of (return value, chain).
    2660             :   /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
    2661             :   std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
    2662             :                                           EVT RetVT, ArrayRef<SDValue> Ops,
    2663             :                                           bool isSigned, const SDLoc &dl,
    2664             :                                           bool doesNotReturn = false,
    2665             :                                           bool isReturnValueUsed = true) const;
    2666             : 
    2667             :   /// Check whether parameters to a call that are passed in callee saved
    2668             :   /// registers are the same as from the calling function.  This needs to be
    2669             :   /// checked for tail call eligibility.
    2670             :   bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
    2671             :       const uint32_t *CallerPreservedMask,
    2672             :       const SmallVectorImpl<CCValAssign> &ArgLocs,
    2673             :       const SmallVectorImpl<SDValue> &OutVals) const;
    2674             : 
    2675             :   //===--------------------------------------------------------------------===//
    2676             :   // TargetLowering Optimization Methods
    2677             :   //
    2678             : 
    2679             :   /// A convenience struct that encapsulates a DAG, and two SDValues for
    2680             :   /// returning information from TargetLowering to its clients that want to
    2681             :   /// combine.
    2682             :   struct TargetLoweringOpt {
    2683             :     SelectionDAG &DAG;
    2684             :     bool LegalTys;
    2685             :     bool LegalOps;
    2686             :     SDValue Old;
    2687             :     SDValue New;
    2688             : 
    2689             :     explicit TargetLoweringOpt(SelectionDAG &InDAG,
    2690     2644247 :                                bool LT, bool LO) :
    2691     2644247 :       DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
    2692             : 
    2693             :     bool LegalTypes() const { return LegalTys; }
    2694             :     bool LegalOperations() const { return LegalOps; }
    2695             : 
    2696             :     bool CombineTo(SDValue O, SDValue N) {
    2697       90741 :       Old = O;
    2698       90741 :       New = N;
    2699             :       return true;
    2700             :     }
    2701             :   };
    2702             : 
    2703             :   /// Check to see if the specified operand of the specified instruction is a
    2704             :   /// constant integer.  If so, check to see if there are any bits set in the
    2705             :   /// constant that are not demanded.  If so, shrink the constant and return
    2706             :   /// true.
    2707             :   bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
    2708             :                               TargetLoweringOpt &TLO) const;
    2709             : 
    2710             :   // Target hook to do target-specific const optimization, which is called by
    2711             :   // ShrinkDemandedConstant. This function should return true if the target
    2712             :   // doesn't want ShrinkDemandedConstant to further optimize the constant.
    2713      271151 :   virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
    2714             :                                             TargetLoweringOpt &TLO) const {
    2715      271151 :     return false;
    2716             :   }
    2717             : 
    2718             :   /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.  This
    2719             :   /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
    2720             :   /// generalized for targets with other types of implicit widening casts.
    2721             :   bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
    2722             :                         TargetLoweringOpt &TLO) const;
    2723             : 
    2724             :   /// Helper for SimplifyDemandedBits that can simplify an operation with
    2725             :   /// multiple uses.  This function simplifies operand \p OpIdx of \p User and
    2726             :   /// then updates \p User with the simplified version. No other uses of
    2727             :   /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
    2728             :   /// function behaves exactly like function SimplifyDemandedBits declared
    2729             :   /// below except that it also updates the DAG by calling
    2730             :   /// DCI.CommitTargetLoweringOpt.
    2731             :   bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
    2732             :                             DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
    2733             : 
    2734             :   /// Look at Op.  At this point, we know that only the DemandedMask bits of the
    2735             :   /// result of Op are ever used downstream.  If we can use this information to
    2736             :   /// simplify Op, create a new simplified DAG node and return true, returning
    2737             :   /// the original and new nodes in Old and New.  Otherwise, analyze the
    2738             :   /// expression and return a mask of KnownOne and KnownZero bits for the
    2739             :   /// expression (used to simplify the caller).  The KnownZero/One bits may only
    2740             :   /// be accurate for those bits in the DemandedMask.
    2741             :   /// \p AssumeSingleUse When this parameter is true, this function will
    2742             :   ///    attempt to simplify \p Op even if there are multiple uses.
    2743             :   ///    Callers are responsible for correctly updating the DAG based on the
    2744             :   ///    results of this function, because simply replacing replacing TLO.Old
    2745             :   ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
    2746             :   ///    has multiple uses.
    2747             :   bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
    2748             :                             KnownBits &Known,
    2749             :                             TargetLoweringOpt &TLO,
    2750             :                             unsigned Depth = 0,
    2751             :                             bool AssumeSingleUse = false) const;
    2752             : 
    2753             :   /// Helper wrapper around SimplifyDemandedBits
    2754             :   bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
    2755             :                             DAGCombinerInfo &DCI) const;
    2756             : 
    2757             :   /// Look at Vector Op. At this point, we know that only the DemandedElts
    2758             :   /// elements of the result of Op are ever used downstream.  If we can use
    2759             :   /// this information to simplify Op, create a new simplified DAG node and
    2760             :   /// return true, storing the original and new nodes in TLO.
    2761             :   /// Otherwise, analyze the expression and return a mask of KnownUndef and
    2762             :   /// KnownZero elements for the expression (used to simplify the caller).
    2763             :   /// The KnownUndef/Zero elements may only be accurate for those bits
    2764             :   /// in the DemandedMask.
    2765             :   /// \p AssumeSingleUse When this parameter is true, this function will
    2766             :   ///    attempt to simplify \p Op even if there are multiple uses.
    2767             :   ///    Callers are responsible for correctly updating the DAG based on the
    2768             :   ///    results of this function, because simply replacing replacing TLO.Old
    2769             :   ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
    2770             :   ///    has multiple uses.
    2771             :   bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
    2772             :                                   APInt &KnownUndef, APInt &KnownZero,
    2773             :                                   TargetLoweringOpt &TLO, unsigned Depth = 0,
    2774             :                                   bool AssumeSingleUse = false) const;
    2775             : 
    2776             :   /// Helper wrapper around SimplifyDemandedVectorElts
    2777             :   bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
    2778             :                                   APInt &KnownUndef, APInt &KnownZero,
    2779             :                                   DAGCombinerInfo &DCI) const;
    2780             : 
    2781             :   /// Determine which of the bits specified in Mask are known to be either zero
    2782             :   /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
    2783             :   /// argument allows us to only collect the known bits that are shared by the
    2784             :   /// requested vector elements.
    2785             :   virtual void computeKnownBitsForTargetNode(const SDValue Op,
    2786             :                                              KnownBits &Known,
    2787             :                                              const APInt &DemandedElts,
    2788             :                                              const SelectionDAG &DAG,
    2789             :                                              unsigned Depth = 0) const;
    2790             : 
    2791             :   /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
    2792             :   /// Default implementation computes low bits based on alignment
    2793             :   /// information. This should preserve known bits passed into it.
    2794             :   virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
    2795             :                                              KnownBits &Known,
    2796             :                                              const APInt &DemandedElts,
    2797             :                                              const SelectionDAG &DAG,
    2798             :                                              unsigned Depth = 0) const;
    2799             : 
    2800             :   /// This method can be implemented by targets that want to expose additional
    2801             :   /// information about sign bits to the DAG Combiner. The DemandedElts
    2802             :   /// argument allows us to only collect the minimum sign bits that are shared
    2803             :   /// by the requested vector elements.
    2804             :   virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
    2805             :                                                    const APInt &DemandedElts,
    2806             :                                                    const SelectionDAG &DAG,
    2807             :                                                    unsigned Depth = 0) const;
    2808             : 
    2809             :   /// Attempt to simplify any target nodes based on the demanded vector
    2810             :   /// elements, returning true on success. Otherwise, analyze the expression and
    2811             :   /// return a mask of KnownUndef and KnownZero elements for the expression
    2812             :   /// (used to simplify the caller). The KnownUndef/Zero elements may only be
    2813             :   /// accurate for those bits in the DemandedMask
    2814             :   virtual bool SimplifyDemandedVectorEltsForTargetNode(
    2815             :       SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
    2816             :       APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
    2817             : 
    2818             :   struct DAGCombinerInfo {
    2819             :     void *DC;  // The DAG Combiner object.
    2820             :     CombineLevel Level;
    2821             :     bool CalledByLegalizer;
    2822             : 
    2823             :   public:
    2824             :     SelectionDAG &DAG;
    2825             : 
    2826             :     DAGCombinerInfo(SelectionDAG &dag, CombineLevel level,  bool cl, void *dc)
    2827    10631052 :       : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
    2828             : 
    2829             :     bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
    2830     1268559 :     bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
    2831             :     bool isAfterLegalizeDAG() const {
    2832             :       return Level == AfterLegalizeDAG;
    2833             :     }
    2834             :     CombineLevel getDAGCombineLevel() { return Level; }
    2835             :     bool isCalledByLegalizer() const { return CalledByLegalizer; }
    2836             : 
    2837             :     void AddToWorklist(SDNode *N);
    2838             :     SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
    2839             :     SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
    2840             :     SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
    2841             : 
    2842             :     void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
    2843             :   };
    2844             : 
    2845             :   /// Return if the N is a constant or constant vector equal to the true value
    2846             :   /// from getBooleanContents().
    2847             :   bool isConstTrueVal(const SDNode *N) const;
    2848             : 
    2849             :   /// Return if the N is a constant or constant vector equal to the false value
    2850             :   /// from getBooleanContents().
    2851             :   bool isConstFalseVal(const SDNode *N) const;
    2852             : 
    2853             :   /// Return if \p N is a True value when extended to \p VT.
    2854             :   bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
    2855             : 
    2856             :   /// Try to simplify a setcc built with the specified operands and cc. If it is
    2857             :   /// unable to simplify it, return a null SDValue.
    2858             :   SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
    2859             :                         bool foldBooleans, DAGCombinerInfo &DCI,
    2860             :                         const SDLoc &dl) const;
    2861             : 
    2862             :   // For targets which wrap address, unwrap for analysis.
    2863     2651335 :   virtual SDValue unwrapAddress(SDValue N) const { return N; }
    2864             : 
    2865             :   /// Returns true (and the GlobalValue and the offset) if the node is a
    2866             :   /// GlobalAddress + offset.
    2867             :   virtual bool
    2868             :   isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
    2869             : 
    2870             :   /// This method will be invoked for all target nodes and for any
    2871             :   /// target-independent nodes that the target has registered with invoke it
    2872             :   /// for.
    2873             :   ///
    2874             :   /// The semantics are as follows:
    2875             :   /// Return Value:
    2876             :   ///   SDValue.Val == 0   - No change was made
    2877             :   ///   SDValue.Val == N   - N was replaced, is dead, and is already handled.
    2878             :   ///   otherwise          - N should be replaced by the returned Operand.
    2879             :   ///
    2880             :   /// In addition, methods provided by DAGCombinerInfo may be used to perform
    2881             :   /// more complex transformations.
    2882             :   ///
    2883             :   virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
    2884             : 
    2885             :   /// Return true if it is profitable to move a following shift through this
    2886             :   //  node, adjusting any immediate operands as necessary to preserve semantics.
    2887             :   //  This transformation may not be desirable if it disrupts a particularly
    2888             :   //  auspicious target-specific tree (e.g. bitfield extraction in AArch64).
    2889             :   //  By default, it returns true.
    2890         799 :   virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
    2891         799 :     return true;
    2892             :   }
    2893             : 
    2894             :   // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
    2895             :   // to a shuffle and a truncate.
    2896             :   // Example of such a combine:
    2897             :   // v4i32 build_vector((extract_elt V, 1),
    2898             :   //                    (extract_elt V, 3),
    2899             :   //                    (extract_elt V, 5),
    2900             :   //                    (extract_elt V, 7))
    2901             :   //  -->
    2902             :   // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
    2903           0 :   virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
    2904             :       ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
    2905           0 :     return false;
    2906             :   }
    2907             : 
    2908             :   /// Return true if the target has native support for the specified value type
    2909             :   /// and it is 'desirable' to use the type for the given node type. e.g. On x86
    2910             :   /// i16 is legal, but undesirable since i16 instruction encodings are longer
    2911             :   /// and some i16 instructions are slow.
    2912      238973 :   virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
    2913             :     // By default, assume all legal types are desirable.
    2914      477946 :     return isTypeLegal(VT);
    2915             :   }
    2916             : 
    2917             :   /// Return true if it is profitable for dag combiner to transform a floating
    2918             :   /// point op of specified opcode to a equivalent op of an integer
    2919             :   /// type. e.g. f32 load -> i32 load can be profitable on ARM.
    2920         287 :   virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
    2921             :                                                  EVT /*VT*/) const {
    2922         287 :     return false;
    2923             :   }
    2924             : 
    2925             :   /// This method query the target whether it is beneficial for dag combiner to
    2926             :   /// promote the specified node. If true, it should return the desired
    2927             :   /// promotion type by reference.
    2928        3977 :   virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
    2929        3977 :     return false;
    2930             :   }
    2931             : 
    2932             :   /// Return true if the target supports swifterror attribute. It optimizes
    2933             :   /// loads and stores to reading and writing a specific register.
    2934      365399 :   virtual bool supportSwiftError() const {
    2935      365399 :     return false;
    2936             :   }
    2937             : 
    2938             :   /// Return true if the target supports that a subset of CSRs for the given
    2939             :   /// machine function is handled explicitly via copies.
    2940       26924 :   virtual bool supportSplitCSR(MachineFunction *MF) const {
    2941       26924 :     return false;
    2942             :   }
    2943             : 
    2944             :   /// Perform necessary initialization to handle a subset of CSRs explicitly
    2945             :   /// via copies. This function is called at the beginning of instruction
    2946             :   /// selection.
    2947           0 :   virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
    2948           0 :     llvm_unreachable("Not Implemented");
    2949             :   }
    2950             : 
    2951             :   /// Insert explicit copies in entry and exit blocks. We copy a subset of
    2952             :   /// CSRs to virtual registers in the entry block, and copy them back to
    2953             :   /// physical registers in the exit blocks. This function is called at the end
    2954             :   /// of instruction selection.
    2955           0 :   virtual void insertCopiesSplitCSR(
    2956             :       MachineBasicBlock *Entry,
    2957             :       const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
    2958           0 :     llvm_unreachable("Not Implemented");
    2959             :   }
    2960             : 
    2961             :   //===--------------------------------------------------------------------===//
    2962             :   // Lowering methods - These methods must be implemented by targets so that
    2963             :   // the SelectionDAGBuilder code knows how to lower these.
    2964             :   //
    2965             : 
    2966             :   /// This hook must be implemented to lower the incoming (formal) arguments,
    2967             :   /// described by the Ins array, into the specified DAG. The implementation
    2968             :   /// should fill in the InVals array with legal-type argument values, and
    2969             :   /// return the resulting token chain value.
    2970           0 :   virtual SDValue LowerFormalArguments(
    2971             :       SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
    2972             :       const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
    2973             :       SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
    2974           0 :     llvm_unreachable("Not Implemented");
    2975             :   }
    2976             : 
    2977             :   /// This structure contains all information that is necessary for lowering
    2978             :   /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
    2979             :   /// needs to lower a call, and targets will see this struct in their LowerCall
    2980             :   /// implementation.
    2981      356858 :   struct CallLoweringInfo {
    2982             :     SDValue Chain;
    2983             :     Type *RetTy = nullptr;
    2984             :     bool RetSExt           : 1;
    2985             :     bool RetZExt           : 1;
    2986             :     bool IsVarArg          : 1;
    2987             :     bool IsInReg           : 1;
    2988             :     bool DoesNotReturn     : 1;
    2989             :     bool IsReturnValueUsed : 1;
    2990             :     bool IsConvergent      : 1;
    2991             :     bool IsPatchPoint      : 1;
    2992             : 
    2993             :     // IsTailCall should be modified by implementations of
    2994             :     // TargetLowering::LowerCall that perform tail call conversions.
    2995             :     bool IsTailCall = false;
    2996             : 
    2997             :     // Is Call lowering done post SelectionDAG type legalization.
    2998             :     bool IsPostTypeLegalization = false;
    2999             : 
    3000             :     unsigned NumFixedArgs = -1;
    3001             :     CallingConv::ID CallConv = CallingConv::C;
    3002             :     SDValue Callee;
    3003             :     ArgListTy Args;
    3004             :     SelectionDAG &DAG;
    3005             :     SDLoc DL;
    3006             :     ImmutableCallSite CS;
    3007             :     SmallVector<ISD::OutputArg, 32> Outs;
    3008             :     SmallVector<SDValue, 32> OutVals;
    3009             :     SmallVector<ISD::InputArg, 32> Ins;
    3010             :     SmallVector<SDValue, 4> InVals;
    3011             : 
    3012      178435 :     CallLoweringInfo(SelectionDAG &DAG)
    3013      178435 :         : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
    3014             :           DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
    3015      535305 :           IsPatchPoint(false), DAG(DAG) {}
    3016             : 
    3017             :     CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
    3018             :       DL = dl;
    3019             :       return *this;
    3020             :     }
    3021             : 
    3022             :     CallLoweringInfo &setChain(SDValue InChain) {
    3023      220699 :       Chain = InChain;
    3024             :       return *this;
    3025             :     }
    3026             : 
    3027             :     // setCallee with target/module-specific attributes
    3028        8083 :     CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
    3029             :                                    SDValue Target, ArgListTy &&ArgsList) {
    3030        8083 :       RetTy = ResultType;
    3031        8083 :       Callee = Target;
    3032        8083 :       CallConv = CC;
    3033       16166 :       NumFixedArgs = ArgsList.size();
    3034        8083 :       Args = std::move(ArgsList);
    3035             : 
    3036       16166 :       DAG.getTargetLoweringInfo().markLibCallAttributes(
    3037        8083 :           &(DAG.getMachineFunction()), CC, Args);
    3038        8083 :       return *this;
    3039             :     }
    3040             : 
    3041             :     CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
    3042             :                                 SDValue Target, ArgListTy &&ArgsList) {
    3043         592 :       RetTy = ResultType;
    3044         592 :       Callee = Target;
    3045         592 :       CallConv = CC;
    3046        1184 :       NumFixedArgs = ArgsList.size();
    3047         216 :       Args = std::move(ArgsList);
    3048             :       return *this;
    3049             :     }
    3050             : 
    3051      169760 :     CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
    3052             :                                 SDValue Target, ArgListTy &&ArgsList,
    3053             :                                 ImmutableCallSite Call) {
    3054      169760 :       RetTy = ResultType;
    3055             : 
    3056      169760 :       IsInReg = Call.hasRetAttr(Attribute::InReg);
    3057      169760 :       DoesNotReturn =
    3058      169760 :           Call.doesNotReturn() ||
    3059      119270 :           (!Call.isInvoke() &&
    3060             :            isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
    3061      169760 :       IsVarArg = FTy->isVarArg();
    3062      169760 :       IsReturnValueUsed = !Call.getInstruction()->use_empty();
    3063      169760 :       RetSExt = Call.hasRetAttr(Attribute::SExt);
    3064      169760 :       RetZExt = Call.hasRetAttr(Attribute::ZExt);
    3065             : 
    3066      169760 :       Callee = Target;
    3067             : 
    3068      169760 :       CallConv = Call.getCallingConv();
    3069      339520 :       NumFixedArgs = FTy->getNumParams();
    3070      169760 :       Args = std::move(ArgsList);
    3071             : 
    3072      169760 :       CS = Call;
    3073             : 
    3074      169760 :       return *this;
    3075             :     }
    3076             : 
    3077             :     CallLoweringInfo &setInRegister(bool Value = true) {
    3078         197 :       IsInReg = Value;
    3079             :       return *this;
    3080             :     }
    3081             : 
    3082             :     CallLoweringInfo &setNoReturn(bool Value = true) {
    3083        2914 :       DoesNotReturn = Value;
    3084             :       return *this;
    3085             :     }
    3086             : 
    3087             :     CallLoweringInfo &setVarArg(bool Value = true) {
    3088             :       IsVarArg = Value;
    3089             :       return *this;
    3090             :     }
    3091             : 
    3092             :     CallLoweringInfo &setTailCall(bool Value = true) {
    3093      173987 :       IsTailCall = Value;
    3094             :       return *this;
    3095             :     }
    3096             : 
    3097             :     CallLoweringInfo &setDiscardResult(bool Value = true) {
    3098        4918 :       IsReturnValueUsed = !Value;
    3099             :       return *this;
    3100             :     }
    3101             : 
    3102             :     CallLoweringInfo &setConvergent(bool Value = true) {
    3103      169760 :       IsConvergent = Value;
    3104             :       return *this;
    3105             :     }
    3106             : 
    3107             :     CallLoweringInfo &setSExtResult(bool Value = true) {
    3108        6083 :       RetSExt = Value;
    3109             :       return *this;
    3110             :     }
    3111             : 
    3112             :     CallLoweringInfo &setZExtResult(bool Value = true) {
    3113        6074 :       RetZExt = Value;
    3114             :       return *this;
    3115             :     }
    3116             : 
    3117             :     CallLoweringInfo &setIsPatchPoint(bool Value = true) {
    3118         216 :       IsPatchPoint = Value;
    3119             :       return *this;
    3120             :     }
    3121             : 
    3122             :     CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
    3123        2595 :       IsPostTypeLegalization = Value;
    3124             :       return *this;
    3125             :     }
    3126             : 
    3127             :     ArgListTy &getArgs() {
    3128        4008 :       return Args;
    3129             :     }
    3130             :   };
    3131             : 
    3132             :   /// This function lowers an abstract call to a function into an actual call.
    3133             :   /// This returns a pair of operands.  The first element is the return value
    3134             :   /// for the function (if RetTy is not VoidTy).  The second element is the
    3135             :   /// outgoing token chain. It calls LowerCall to do the actual lowering.
    3136             :   std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
    3137             : 
    3138             :   /// This hook must be implemented to lower calls into the specified
    3139             :   /// DAG. The outgoing arguments to the call are described by the Outs array,
    3140             :   /// and the values to be returned by the call are described by the Ins
    3141             :   /// array. The implementation should fill in the InVals array with legal-type
    3142             :   /// return values from the call, and return the resulting token chain value.
    3143             :   virtual SDValue
    3144           0 :     LowerCall(CallLoweringInfo &/*CLI*/,
    3145             :               SmallVectorImpl<SDValue> &/*InVals*/) const {
    3146           0 :     llvm_unreachable("Not Implemented");
    3147             :   }
    3148             : 
    3149             :   /// Target-specific cleanup for formal ByVal parameters.
    3150        1114 :   virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
    3151             : 
    3152             :   /// This hook should be implemented to check whether the return values
    3153             :   /// described by the Outs array can fit into the return registers.  If false
    3154             :   /// is returned, an sret-demotion is performed.
    3155        5383 :   virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
    3156             :                               MachineFunction &/*MF*/, bool /*isVarArg*/,
    3157             :                const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
    3158             :                LLVMContext &/*Context*/) const
    3159             :   {
    3160             :     // Return true by default to get preexisting behavior.
    3161        5383 :     return true;
    3162             :   }
    3163             : 
    3164             :   /// This hook must be implemented to lower outgoing return values, described
    3165             :   /// by the Outs array, into the specified DAG. The implementation should
    3166             :   /// return the resulting token chain value.
    3167           0 :   virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
    3168             :                               bool /*isVarArg*/,
    3169             :                               const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
    3170             :                               const SmallVectorImpl<SDValue> & /*OutVals*/,
    3171             :                               const SDLoc & /*dl*/,
    3172             :                               SelectionDAG & /*DAG*/) const {
    3173           0 :     llvm_unreachable("Not Implemented");
    3174             :   }
    3175             : 
    3176             :   /// Return true if result of the specified node is used by a return node
    3177             :   /// only. It also compute and return the input chain for the tail call.
    3178             :   ///
    3179             :   /// This is used to determine whether it is possible to codegen a libcall as
    3180             :   /// tail call at legalization time.
    3181         591 :   virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
    3182         591 :     return false;
    3183             :   }
    3184             : 
    3185             :   /// Return true if the target may be able emit the call instruction as a tail
    3186             :   /// call. This is used by optimization passes to determine if it's profitable
    3187             :   /// to duplicate return instructions to enable tailcall optimization.
    3188         147 :   virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
    3189         147 :     return false;
    3190             :   }
    3191             : 
    3192             :   /// Return the builtin name for the __builtin___clear_cache intrinsic
    3193             :   /// Default is to invoke the clear cache library call
    3194           2 :   virtual const char * getClearCacheBuiltinName() const {
    3195           2 :     return "__clear_cache";
    3196             :   }
    3197             : 
    3198             :   /// Return the register ID of the name passed in. Used by named register
    3199             :   /// global variables extension. There is no target-independent behaviour
    3200             :   /// so the default action is to bail.
    3201           0 :   virtual unsigned getRegisterByName(const char* RegName, EVT VT,
    3202             :                                      SelectionDAG &DAG) const {
    3203           0 :     report_fatal_error("Named registers not implemented for this target");
    3204             :   }
    3205             : 
    3206             :   /// Return the type that should be used to zero or sign extend a
    3207             :   /// zeroext/signext integer return value.  FIXME: Some C calling conventions
    3208             :   /// require the return type to be promoted, but this is not true all the time,
    3209             :   /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
    3210             :   /// conventions. The frontend should handle this and include all of the
    3211             :   /// necessary information.
    3212        4700 :   virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
    3213             :                                        ISD::NodeType /*ExtendKind*/) const {
    3214       14100 :     EVT MinVT = getRegisterType(Context, MVT::i32);
    3215        4700 :     return VT.bitsLT(MinVT) ? MinVT : VT;
    3216             :   }
    3217             : 
    3218             :   /// For some targets, an LLVM struct type must be broken down into multiple
    3219             :   /// simple types, but the calling convention specifies that the entire struct
    3220             :   /// must be passed in a block of consecutive registers.
    3221             :   virtual bool
    3222      640572 :   functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
    3223             :                                             bool isVarArg) const {
    3224      640572 :     return false;
    3225             :   }
    3226             : 
    3227             :   /// Returns a 0 terminated array of registers that can be safely used as
    3228             :   /// scratch registers.
    3229           0 :   virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
    3230           0 :     return nullptr;
    3231             :   }
    3232             : 
    3233             :   /// This callback is used to prepare for a volatile or atomic load.
    3234             :   /// It takes a chain node as input and returns the chain for the load itself.
    3235             :   ///
    3236             :   /// Having a callback like this is necessary for targets like SystemZ,
    3237             :   /// which allows a CPU to reuse the result of a previous load indefinitely,
    3238             :   /// even if a cache-coherent store is performed by another CPU.  The default
    3239             :   /// implementation does nothing.
    3240       10993 :   virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
    3241             :                                               SelectionDAG &DAG) const {
    3242       10993 :     return Chain;
    3243             :   }
    3244             : 
    3245             :   /// This callback is used to inspect load/store instructions and add
    3246             :   /// target-specific MachineMemOperand flags to them.  The default
    3247             :   /// implementation does nothing.
    3248      631939 :   virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
    3249      631939 :     return MachineMemOperand::MONone;
    3250             :   }
    3251             : 
    3252             :   /// This callback is invoked by the type legalizer to legalize nodes with an
    3253             :   /// illegal operand type but legal result types.  It replaces the
    3254             :   /// LowerOperation callback in the type Legalizer.  The reason we can not do
    3255             :   /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
    3256             :   /// use this callback.
    3257             :   ///
    3258             :   /// TODO: Consider merging with ReplaceNodeResults.
    3259             :   ///
    3260             :   /// The target places new result values for the node in Results (their number
    3261             :   /// and types must exactly match those of the original return values of
    3262             :   /// the node), or leaves Results empty, which indicates that the node is not
    3263             :   /// to be custom lowered after all.
    3264             :   /// The default implementation calls LowerOperation.
    3265             :   virtual void LowerOperationWrapper(SDNode *N,
    3266             :                                      SmallVectorImpl<SDValue> &Results,
    3267             :                                      SelectionDAG &DAG) const;
    3268             : 
    3269             :   /// This callback is invoked for operations that are unsupported by the
    3270             :   /// target, which are registered to use 'custom' lowering, and whose defined
    3271             :   /// values are all legal.  If the target has no operations that require custom
    3272             :   /// lowering, it need not implement this.  The default implementation of this
    3273             :   /// aborts.
    3274             :   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
    3275             : 
    3276             :   /// This callback is invoked when a node result type is illegal for the
    3277             :   /// target, and the operation was registered to use 'custom' lowering for that
    3278             :   /// result type.  The target places new result values for the node in Results
    3279             :   /// (their number and types must exactly match those of the original return
    3280             :   /// values of the node), or leaves Results empty, which indicates that the
    3281             :   /// node is not to be custom lowered after all.
    3282             :   ///
    3283             :   /// If the target has no operations that require custom lowering, it need not
    3284             :   /// implement this.  The default implementation aborts.
    3285           0 :   virtual void ReplaceNodeResults(SDNode * /*N*/,
    3286             :                                   SmallVectorImpl<SDValue> &/*Results*/,
    3287             :                                   SelectionDAG &/*DAG*/) const {
    3288           0 :     llvm_unreachable("ReplaceNodeResults not implemented for this target!");
    3289             :   }
    3290             : 
    3291             :   /// This method returns the name of a target specific DAG node.
    3292             :   virtual const char *getTargetNodeName(unsigned Opcode) const;
    3293             : 
    3294             :   /// This method returns a target specific FastISel object, or null if the
    3295             :   /// target does not support "fast" ISel.
    3296        2553 :   virtual FastISel *createFastISel(FunctionLoweringInfo &,
    3297             :                                    const TargetLibraryInfo *) const {
    3298        2553 :     return nullptr;
    3299             :   }
    3300             : 
    3301             :   bool verifyReturnAddressArgumentIsConstant(SDValue Op,
    3302             :                                              SelectionDAG &DAG) const;
    3303             : 
    3304             :   //===--------------------------------------------------------------------===//
    3305             :   // Inline Asm Support hooks
    3306             :   //
    3307             : 
    3308             :   /// This hook allows the target to expand an inline asm call to be explicit
    3309             :   /// llvm code if it wants to.  This is useful for turning simple inline asms
    3310             :   /// into LLVM intrinsics, which gives the compiler more information about the
    3311             :   /// behavior of the code.
    3312        2579 :   virtual bool ExpandInlineAsm(CallInst *) const {
    3313        2579 :     return false;
    3314             :   }
    3315             : 
    3316             :   enum ConstraintType {
    3317             :     C_Register,            // Constraint represents specific register(s).
    3318             :     C_RegisterClass,       // Constraint represents any of register(s) in class.
    3319             :     C_Memory,              // Memory constraint.
    3320             :     C_Other,               // Something else.
    3321             :     C_Unknown              // Unsupported constraint.
    3322             :   };
    3323             : 
    3324             :   enum ConstraintWeight {
    3325             :     // Generic weights.
    3326             :     CW_Invalid  = -1,     // No match.
    3327             :     CW_Okay     = 0,      // Acceptable.
    3328             :     CW_Good     = 1,      // Good weight.
    3329             :     CW_Better   = 2,      // Better weight.
    3330             :     CW_Best     = 3,      // Best weight.
    3331             : 
    3332             :     // Well-known weights.
    3333             :     CW_SpecificReg  = CW_Okay,    // Specific register operands.
    3334             :     CW_Register     = CW_Good,    // Register operands.
    3335             :     CW_Memory       = CW_Better,  // Memory operands.
    3336             :     CW_Constant     = CW_Best,    // Constant operand.
    3337             :     CW_Default      = CW_Okay     // Default or don't know type.
    3338             :   };
    3339             : 
    3340             :   /// This contains information for each constraint that we are lowering.
    3341     2168420 :   struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
    3342             :     /// This contains the actual string for the code, like "m".  TargetLowering
    3343             :     /// picks the 'best' code from ConstraintInfo::Codes that most closely
    3344             :     /// matches the operand.
    3345             :     std::string ConstraintCode;
    3346             : 
    3347             :     /// Information about the constraint code, e.g. Register, RegisterClass,
    3348             :     /// Memory, Other, Unknown.
    3349             :     TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
    3350             : 
    3351             :     /// If this is the result output operand or a clobber, this is null,
    3352             :     /// otherwise it is the incoming operand to the CallInst.  This gets
    3353             :     /// modified as the asm is processed.
    3354             :     Value *CallOperandVal = nullptr;
    3355             : 
    3356             :     /// The ValueType for the operand value.
    3357             :     MVT ConstraintVT = MVT::Other;
    3358             : 
    3359             :     /// Copy constructor for copying from a ConstraintInfo.
    3360             :     AsmOperandInfo(InlineAsm::ConstraintInfo Info)
    3361      394268 :         : InlineAsm::ConstraintInfo(std::move(Info)) {}
    3362             : 
    3363             :     /// Return true of this is an input operand that is a matching constraint
    3364             :     /// like "4".
    3365             :     bool isMatchingInputConstraint() const;
    3366             : 
    3367             :     /// If this is an input matching constraint, this method returns the output
    3368             :     /// operand it matches.
    3369             :     unsigned getMatchedOperand() const;
    3370             :   };
    3371             : 
    3372             :   using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
    3373             : 
    3374             :   /// Split up the constraint string from the inline assembly value into the
    3375             :   /// specific constraints and their prefixes, and also tie in the associated
    3376             :   /// operand values.  If this returns an empty vector, and if the constraint
    3377             :   /// string itself isn't empty, there was an error parsing.
    3378             :   virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
    3379             :                                                 const TargetRegisterInfo *TRI,
    3380             :                                                 ImmutableCallSite CS) const;
    3381             : 
    3382             :   /// Examine constraint type and operand type and determine a weight value.
    3383             :   /// The operand object must already have been set up with the operand type.
    3384             :   virtual ConstraintWeight getMultipleConstraintMatchWeight(
    3385             :       AsmOperandInfo &info, int maIndex) const;
    3386             : 
    3387             :   /// Examine constraint string and operand type and determine a weight value.
    3388             :   /// The operand object must already have been set up with the operand type.
    3389             :   virtual ConstraintWeight getSingleConstraintMatchWeight(
    3390             :       AsmOperandInfo &info, const char *constraint) const;
    3391             : 
    3392             :   /// Determines the constraint code and constraint type to use for the specific
    3393             :   /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
    3394             :   /// If the actual operand being passed in is available, it can be passed in as
    3395             :   /// Op, otherwise an empty SDValue can be passed.
    3396             :   virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
    3397             :                                       SDValue Op,
    3398             :                                       SelectionDAG *DAG = nullptr) const;
    3399             : 
    3400             :   /// Given a constraint, return the type of constraint it is for this target.
    3401             :   virtual ConstraintType getConstraintType(StringRef Constraint) const;
    3402             : 
    3403             :   /// Given a physical register constraint (e.g.  {edx}), return the register
    3404             :   /// number and the register class for the register.
    3405             :   ///
    3406             :   /// Given a register class constraint, like 'r', if this corresponds directly
    3407             :   /// to an LLVM register class, return a register of 0 and the register class
    3408             :   /// pointer.
    3409             :   ///
    3410             :   /// This should only be used for C_Register constraints.  On error, this
    3411             :   /// returns a register number of 0 and a null register class pointer.
    3412             :   virtual std::pair<unsigned, const TargetRegisterClass *>
    3413             :   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
    3414             :                                StringRef Constraint, MVT VT) const;
    3415             : 
    3416          16 :   virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
    3417             :     if (ConstraintCode == "i")
    3418             :       return InlineAsm::Constraint_i;
    3419             :     else if (ConstraintCode == "m")
    3420             :       return InlineAsm::Constraint_m;
    3421             :     return InlineAsm::Constraint_Unknown;
    3422             :   }
    3423             : 
    3424             :   /// Try to replace an X constraint, which matches anything, with another that
    3425             :   /// has more specific requirements based on the type of the corresponding
    3426             :   /// operand.  This returns null if there is no replacement to make.
    3427             :   virtual const char *LowerXConstraint(EVT ConstraintVT) const;
    3428             : 
    3429             :   /// Lower the specified operand into the Ops vector.  If it is invalid, don't
    3430             :   /// add anything to Ops.
    3431             :   virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
    3432             :                                             std::vector<SDValue> &Ops,
    3433             :                                             SelectionDAG &DAG) const;
    3434             : 
    3435             :   //===--------------------------------------------------------------------===//
    3436             :   // Div utility functions
    3437             :   //
    3438             :   SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
    3439             :                     bool IsAfterLegalization,
    3440             :                     std::vector<SDNode *> *Created) const;
    3441             :   SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
    3442             :                     bool IsAfterLegalization,
    3443             :                     std::vector<SDNode *> *Created) const;
    3444             : 
    3445             :   /// Targets may override this function to provide custom SDIV lowering for
    3446             :   /// power-of-2 denominators.  If the target returns an empty SDValue, LLVM
    3447             :   /// assumes SDIV is expensive and replaces it with a series of other integer
    3448             :   /// operations.
    3449             :   virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
    3450             :                                 SelectionDAG &DAG,
    3451             :                                 std::vector<SDNode *> *Created) const;
    3452             : 
    3453             :   /// Indicate whether this target prefers to combine FDIVs with the same
    3454             :   /// divisor. If the transform should never be done, return zero. If the
    3455             :   /// transform should be done, return the minimum number of divisor uses
    3456             :   /// that must exist.
    3457         248 :   virtual unsigned combineRepeatedFPDivisors() const {
    3458         248 :     return 0;
    3459             :   }
    3460             : 
    3461             :   /// Hooks for building estimates in place of slower divisions and square
    3462             :   /// roots.
    3463             : 
    3464             :   /// Return either a square root or its reciprocal estimate value for the input
    3465             :   /// operand.
    3466             :   /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
    3467             :   /// 'Enabled' as set by a potential default override attribute.
    3468             :   /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
    3469             :   /// refinement iterations required to generate a sufficient (though not
    3470             :   /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
    3471             :   /// The boolean UseOneConstNR output is used to select a Newton-Raphson
    3472             :   /// algorithm implementation that uses either one or two constants.
    3473             :   /// The boolean Reciprocal is used to select whether the estimate is for the
    3474             :   /// square root of the input operand or the reciprocal of its square root.
    3475             :   /// A target may choose to implement its own refinement within this function.
    3476             :   /// If that's true, then return '0' as the number of RefinementSteps to avoid
    3477             :   /// any further refinement of the estimate.
    3478             :   /// An empty SDValue return means no estimate sequence can be created.
    3479           0 :   virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
    3480             :                                   int Enabled, int &RefinementSteps,
    3481             :                                   bool &UseOneConstNR, bool Reciprocal) const {
    3482           0 :     return SDValue();
    3483             :   }
    3484             : 
    3485             :   /// Return a reciprocal estimate value for the input operand.
    3486             :   /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
    3487             :   /// 'Enabled' as set by a potential default override attribute.
    3488             :   /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
    3489             :   /// refinement iterations required to generate a sufficient (though not
    3490             :   /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
    3491             :   /// A target may choose to implement its own refinement within this function.
    3492             :   /// If that's true, then return '0' as the number of RefinementSteps to avoid
    3493             :   /// any further refinement of the estimate.
    3494             :   /// An empty SDValue return means no estimate sequence can be created.
    3495          35 :   virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
    3496             :                                    int Enabled, int &RefinementSteps) const {
    3497          35 :     return SDValue();
    3498             :   }
    3499             : 
    3500             :   //===--------------------------------------------------------------------===//
    3501             :   // Legalization utility functions
    3502             :   //
    3503             : 
    3504             :   /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
    3505             :   /// respectively, each computing an n/2-bit part of the result.
    3506             :   /// \param Result A vector that will be filled with the parts of the result
    3507             :   ///        in little-endian order.
    3508             :   /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
    3509             :   ///        if you want to control how low bits are extracted from the LHS.
    3510             :   /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
    3511             :   /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
    3512             :   /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
    3513             :   /// \returns true if the node has been expanded, false if it has not
    3514             :   bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
    3515             :                       SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
    3516             :                       SelectionDAG &DAG, MulExpansionKind Kind,
    3517             :                       SDValue LL = SDValue(), SDValue LH = SDValue(),
    3518             :                       SDValue RL = SDValue(), SDValue RH = SDValue()) const;
    3519             : 
    3520             :   /// Expand a MUL into two nodes.  One that computes the high bits of
    3521             :   /// the result and one that computes the low bits.
    3522             :   /// \param HiLoVT The value type to use for the Lo and Hi nodes.
    3523             :   /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
    3524             :   ///        if you want to control how low bits are extracted from the LHS.
    3525             :   /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
    3526             :   /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
    3527             :   /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
    3528             :   /// \returns true if the node has been expanded. false if it has not
    3529             :   bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
    3530             :                  SelectionDAG &DAG, MulExpansionKind Kind,
    3531             :                  SDValue LL = SDValue(), SDValue LH = SDValue(),
    3532             :                  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
    3533             : 
    3534             :   /// Expand float(f32) to SINT(i64) conversion
    3535             :   /// \param N Node to expand
    3536             :   /// \param Result output after conversion
    3537             :   /// \returns True, if the expansion was successful, false otherwise
    3538             :   bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
    3539             : 
    3540             :   /// Turn load of vector type into a load of the individual elements.
    3541             :   /// \param LD load to expand
    3542             :   /// \returns MERGE_VALUEs of the scalar loads with their chains.
    3543             :   SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
    3544             : 
    3545             :   // Turn a store of a vector type into stores of the individual elements.
    3546             :   /// \param ST Store with a vector value type
    3547             :   /// \returns MERGE_VALUs of the individual store chains.
    3548             :   SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
    3549             : 
    3550             :   /// Expands an unaligned load to 2 half-size loads for an integer, and
    3551             :   /// possibly more for vectors.
    3552             :   std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
    3553             :                                                   SelectionDAG &DAG) const;
    3554             : 
    3555             :   /// Expands an unaligned store to 2 half-size stores for integer values, and
    3556             :   /// possibly more for vectors.
    3557             :   SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
    3558             : 
    3559             :   /// Increments memory address \p Addr according to the type of the value
    3560             :   /// \p DataVT that should be stored. If the data is stored in compressed
    3561             :   /// form, the memory address should be incremented according to the number of
    3562             :   /// the stored elements. This number is equal to the number of '1's bits
    3563             :   /// in the \p Mask.
    3564             :   /// \p DataVT is a vector type. \p Mask is a vector value.
    3565             :   /// \p DataVT and \p Mask have the same number of vector elements.
    3566             :   SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
    3567             :                                  EVT DataVT, SelectionDAG &DAG,
    3568             :                                  bool IsCompressedMemory) const;
    3569             : 
    3570             :   /// Get a pointer to vector element \p Idx located in memory for a vector of
    3571             :   /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
    3572             :   /// bounds the returned pointer is unspecified, but will be within the vector
    3573             :   /// bounds.
    3574             :   SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
    3575             :                                   SDValue Idx) const;
    3576             : 
    3577             :   //===--------------------------------------------------------------------===//
    3578             :   // Instruction Emitting Hooks
    3579             :   //
    3580             : 
    3581             :   /// This method should be implemented by targets that mark instructions with
    3582             :   /// the 'usesCustomInserter' flag.  These instructions are special in various
    3583             :   /// ways, which require special support to insert.  The specified MachineInstr
    3584             :   /// is created but not inserted into any basic blocks, and this method is
    3585             :   /// called to expand it into a sequence of instructions, potentially also
    3586             :   /// creating new basic blocks and control flow.
    3587             :   /// As long as the returned basic block is different (i.e., we created a new
    3588             :   /// one), the custom inserter is free to modify the rest of \p MBB.
    3589             :   virtual MachineBasicBlock *
    3590             :   EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
    3591             : 
    3592             :   /// This method should be implemented by targets that mark instructions with
    3593             :   /// the 'hasPostISelHook' flag. These instructions must be adjusted after
    3594             :   /// instruction selection by target hooks.  e.g. To fill in optional defs for
    3595             :   /// ARM 's' setting instructions.
    3596             :   virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
    3597             :                                              SDNode *Node) const;
    3598             : 
    3599             :   /// If this function returns true, SelectionDAGBuilder emits a
    3600             :   /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
    3601          12 :   virtual bool useLoadStackGuardNode() const {
    3602          12 :     return false;
    3603             :   }
    3604             : 
    3605           0 :   virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
    3606             :                                       const SDLoc &DL) const {
    3607           0 :     llvm_unreachable("not implemented for this target");
    3608             :   }
    3609             : 
    3610             :   /// Lower TLS global address SDNode for target independent emulated TLS model.
    3611             :   virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
    3612             :                                           SelectionDAG &DAG) const;
    3613             : 
    3614             :   /// Expands target specific indirect branch for the case of JumpTable
    3615             :   /// expanasion.
    3616         210 :   virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr,
    3617             :                                          SelectionDAG &DAG) const {
    3618         210 :     return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
    3619             :   }
    3620             : 
    3621             :   // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
    3622             :   // If we're comparing for equality to zero and isCtlzFast is true, expose the
    3623             :   // fact that this can be implemented as a ctlz/srl pair, so that the dag
    3624             :   // combiner can fold the new nodes.
    3625             :   SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
    3626             : 
    3627             : private:
    3628             :   SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
    3629             :                                ISD::CondCode Cond, DAGCombinerInfo &DCI,
    3630             :                                const SDLoc &DL) const;
    3631             : };
    3632             : 
    3633             : /// Given an LLVM IR type and return type attributes, compute the return value
    3634             : /// EVTs and flags, and optionally also the offsets, if the return value is
    3635             : /// being lowered to memory.
    3636             : void GetReturnInfo(Type *ReturnType, AttributeList attr,
    3637             :                    SmallVectorImpl<ISD::OutputArg> &Outs,
    3638             :                    const TargetLowering &TLI, const DataLayout &DL);
    3639             : 
    3640             : } // end namespace llvm
    3641             : 
    3642             : #endif // LLVM_CODEGEN_TARGETLOWERING_H

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