LCOV - code coverage report
Current view: top level - include/llvm/CodeGen - TargetPassConfig.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 25 41 61.0 %
Date: 2018-10-14 09:39:32 Functions: 13 42 31.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// Target-Independent Code Generator Pass Configuration Options pass.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
      15             : #define LLVM_CODEGEN_TARGETPASSCONFIG_H
      16             : 
      17             : #include "llvm/Pass.h"
      18             : #include "llvm/Support/CodeGen.h"
      19             : #include <cassert>
      20             : #include <string>
      21             : 
      22             : namespace llvm {
      23             : 
      24             : class LLVMTargetMachine;
      25             : struct MachineSchedContext;
      26             : class PassConfigImpl;
      27             : class ScheduleDAGInstrs;
      28             : 
      29             : // The old pass manager infrastructure is hidden in a legacy namespace now.
      30             : namespace legacy {
      31             : 
      32             : class PassManagerBase;
      33             : 
      34             : } // end namespace legacy
      35             : 
      36             : using legacy::PassManagerBase;
      37             : 
      38             : /// Discriminated union of Pass ID types.
      39             : ///
      40             : /// The PassConfig API prefers dealing with IDs because they are safer and more
      41             : /// efficient. IDs decouple configuration from instantiation. This way, when a
      42             : /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
      43             : /// refer to a Pass pointer after adding it to a pass manager, which deletes
      44             : /// redundant pass instances.
      45             : ///
      46             : /// However, it is convient to directly instantiate target passes with
      47             : /// non-default ctors. These often don't have a registered PassInfo. Rather than
      48             : /// force all target passes to implement the pass registry boilerplate, allow
      49             : /// the PassConfig API to handle either type.
      50             : ///
      51             : /// AnalysisID is sadly char*, so PointerIntPair won't work.
      52             : class IdentifyingPassPtr {
      53             :   union {
      54             :     AnalysisID ID;
      55             :     Pass *P;
      56             :   };
      57             :   bool IsInstance = false;
      58             : 
      59             : public:
      60       31922 :   IdentifyingPassPtr() : P(nullptr) {}
      61        6984 :   IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
      62             :   IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
      63             : 
      64           0 :   bool isValid() const { return P; }
      65           0 :   bool isInstance() const { return IsInstance; }
      66             : 
      67           0 :   AnalysisID getID() const {
      68             :     assert(!IsInstance && "Not a Pass ID");
      69           0 :     return ID;
      70             :   }
      71             : 
      72           0 :   Pass *getInstance() const {
      73             :     assert(IsInstance && "Not a Pass Instance");
      74           0 :     return P;
      75             :   }
      76             : };
      77             : 
      78             : template <> struct isPodLike<IdentifyingPassPtr> {
      79             :   static const bool value = true;
      80             : };
      81             : 
      82             : /// Target-Independent Code Generator Pass Configuration Options.
      83             : ///
      84             : /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
      85             : /// to the internals of other CodeGen passes.
      86             : class TargetPassConfig : public ImmutablePass {
      87             : private:
      88             :   PassManagerBase *PM = nullptr;
      89             :   AnalysisID StartBefore = nullptr;
      90             :   AnalysisID StartAfter = nullptr;
      91             :   AnalysisID StopBefore = nullptr;
      92             :   AnalysisID StopAfter = nullptr;
      93             :   bool Started = true;
      94             :   bool Stopped = false;
      95             :   bool AddingMachinePasses = false;
      96             : 
      97             :   /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
      98             :   /// a portion of the normal code-gen pass sequence.
      99             :   ///
     100             :   /// If the StartAfter and StartBefore pass ID is zero, then compilation will
     101             :   /// begin at the normal point; otherwise, clear the Started flag to indicate
     102             :   /// that passes should not be added until the starting pass is seen.  If the
     103             :   /// Stop pass ID is zero, then compilation will continue to the end.
     104             :   ///
     105             :   /// This function expects that at least one of the StartAfter or the
     106             :   /// StartBefore pass IDs is null.
     107             :   void setStartStopPasses();
     108             : 
     109             : protected:
     110             :   LLVMTargetMachine *TM;
     111             :   PassConfigImpl *Impl = nullptr; // Internal data structures
     112             :   bool Initialized = false; // Flagged after all passes are configured.
     113             : 
     114             :   // Target Pass Options
     115             :   // Targets provide a default setting, user flags override.
     116             :   bool DisableVerify = false;
     117             : 
     118             :   /// Default setting for -enable-tail-merge on this target.
     119             :   bool EnableTailMerge = true;
     120             : 
     121             :   /// Require processing of functions such that callees are generated before
     122             :   /// callers.
     123             :   bool RequireCodeGenSCCOrder = false;
     124             : 
     125             :   /// Add the actual instruction selection passes. This does not include
     126             :   /// preparation passes on IR.
     127             :   bool addCoreISelPasses();
     128             : 
     129             : public:
     130             :   TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm);
     131             :   // Dummy constructor.
     132             :   TargetPassConfig();
     133             : 
     134             :   ~TargetPassConfig() override;
     135             : 
     136             :   static char ID;
     137             : 
     138             :   /// Get the right type of TargetMachine for this target.
     139           0 :   template<typename TMC> TMC &getTM() const {
     140           0 :     return *static_cast<TMC*>(TM);
     141             :   }
     142             : 
     143             :   //
     144       28329 :   void setInitialized() { Initialized = true; }
     145             : 
     146             :   CodeGenOpt::Level getOptLevel() const;
     147             : 
     148             :   /// Describe the status of the codegen
     149             :   /// pipeline set by this target pass config.
     150             :   /// Having a limited codegen pipeline means that options
     151             :   /// have been used to restrict what codegen is doing.
     152             :   /// In particular, that means that codegen won't emit
     153             :   /// assembly code.
     154             :   bool hasLimitedCodeGenPipeline() const;
     155             : 
     156             :   /// If hasLimitedCodeGenPipeline is true, this method
     157             :   /// returns a string with the name of the options, separated
     158             :   /// by \p Separator that caused this pipeline to be limited.
     159             :   std::string
     160             :   getLimitedCodeGenPipelineReason(const char *Separator = "/") const;
     161             : 
     162             :   /// Check if the codegen pipeline is limited in such a way that it
     163             :   /// won't be complete. When the codegen pipeline is not complete,
     164             :   /// this means it may not be possible to generate assembly from it.
     165             :   bool willCompleteCodeGenPipeline() const {
     166       27245 :     return !hasLimitedCodeGenPipeline() || (!StopAfter && !StopBefore);
     167             :   }
     168             : 
     169       28329 :   void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
     170             : 
     171           0 :   bool getEnableTailMerge() const { return EnableTailMerge; }
     172             :   void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
     173             : 
     174           0 :   bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
     175             :   void setRequiresCodeGenSCCOrder(bool Enable = true) {
     176        4684 :     setOpt(RequireCodeGenSCCOrder, Enable);
     177             :   }
     178             : 
     179             :   /// Allow the target to override a specific pass without overriding the pass
     180             :   /// pipeline. When passes are added to the standard pipeline at the
     181             :   /// point where StandardID is expected, add TargetID in its place.
     182             :   void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
     183             : 
     184             :   /// Insert InsertedPassID pass after TargetPassID pass.
     185             :   void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
     186             :                   bool VerifyAfter = true, bool PrintAfter = true);
     187             : 
     188             :   /// Allow the target to enable a specific standard pass by default.
     189             :   void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
     190             : 
     191             :   /// Allow the target to disable a specific standard pass by default.
     192             :   void disablePass(AnalysisID PassID) {
     193        5394 :     substitutePass(PassID, IdentifyingPassPtr());
     194             :   }
     195             : 
     196             :   /// Return the pass substituted for StandardID by the target.
     197             :   /// If no substitution exists, return StandardID.
     198             :   IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
     199             : 
     200             :   /// Return true if the pass has been substituted by the target or
     201             :   /// overridden on the command line.
     202             :   bool isPassSubstitutedOrOverridden(AnalysisID ID) const;
     203             : 
     204             :   /// Return true if the optimized regalloc pipeline is enabled.
     205             :   bool getOptimizeRegAlloc() const;
     206             : 
     207             :   /// Return true if the default global register allocator is in use and
     208             :   /// has not be overriden on the command line with '-regalloc=...'
     209             :   bool usingDefaultRegAlloc() const;
     210             : 
     211             :   /// High level function that adds all passes necessary to go from llvm IR
     212             :   /// representation to the MI representation.
     213             :   /// Adds IR based lowering and target specific optimization passes and finally
     214             :   /// the core instruction selection passes.
     215             :   /// \returns true if an error occurred, false otherwise.
     216             :   bool addISelPasses();
     217             : 
     218             :   /// Add common target configurable passes that perform LLVM IR to IR
     219             :   /// transforms following machine independent optimization.
     220             :   virtual void addIRPasses();
     221             : 
     222             :   /// Add passes to lower exception handling for the code generator.
     223             :   void addPassesToHandleExceptions();
     224             : 
     225             :   /// Add pass to prepare the LLVM IR for code generation. This should be done
     226             :   /// before exception handling preparation passes.
     227             :   virtual void addCodeGenPrepare();
     228             : 
     229             :   /// Add common passes that perform LLVM IR to IR transforms in preparation for
     230             :   /// instruction selection.
     231             :   virtual void addISelPrepare();
     232             : 
     233             :   /// addInstSelector - This method should install an instruction selector pass,
     234             :   /// which converts from LLVM code to machine instructions.
     235           0 :   virtual bool addInstSelector() {
     236           0 :     return true;
     237             :   }
     238             : 
     239             :   /// This method should install an IR translator pass, which converts from
     240             :   /// LLVM code to machine instructions with possibly generic opcodes.
     241           0 :   virtual bool addIRTranslator() { return true; }
     242             : 
     243             :   /// This method may be implemented by targets that want to run passes
     244             :   /// immediately before legalization.
     245         126 :   virtual void addPreLegalizeMachineIR() {}
     246             : 
     247             :   /// This method should install a legalize pass, which converts the instruction
     248             :   /// sequence into one that can be selected by the target.
     249           0 :   virtual bool addLegalizeMachineIR() { return true; }
     250             : 
     251             :   /// This method may be implemented by targets that want to run passes
     252             :   /// immediately before the register bank selection.
     253         198 :   virtual void addPreRegBankSelect() {}
     254             : 
     255             :   /// This method should install a register bank selector pass, which
     256             :   /// assigns register banks to virtual registers without a register
     257             :   /// class or register banks.
     258           0 :   virtual bool addRegBankSelect() { return true; }
     259             : 
     260             :   /// This method may be implemented by targets that want to run passes
     261             :   /// immediately before the (global) instruction selection.
     262         126 :   virtual void addPreGlobalInstructionSelect() {}
     263             : 
     264             :   /// This method should install a (global) instruction selector pass, which
     265             :   /// converts possibly generic instructions to fully target-specific
     266             :   /// instructions, thereby constraining all generic virtual registers to
     267             :   /// register classes.
     268           0 :   virtual bool addGlobalInstructionSelect() { return true; }
     269             : 
     270             :   /// Add the complete, standard set of LLVM CodeGen passes.
     271             :   /// Fully developed targets will not generally override this.
     272             :   virtual void addMachinePasses();
     273             : 
     274             :   /// Create an instance of ScheduleDAGInstrs to be run within the standard
     275             :   /// MachineScheduler pass for this function and target at the current
     276             :   /// optimization level.
     277             :   ///
     278             :   /// This can also be used to plug a new MachineSchedStrategy into an instance
     279             :   /// of the standard ScheduleDAGMI:
     280             :   ///   return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
     281             :   ///
     282             :   /// Return NULL to select the default (generic) machine scheduler.
     283             :   virtual ScheduleDAGInstrs *
     284       16520 :   createMachineScheduler(MachineSchedContext *C) const {
     285       16520 :     return nullptr;
     286             :   }
     287             : 
     288             :   /// Similar to createMachineScheduler but used when postRA machine scheduling
     289             :   /// is enabled.
     290             :   virtual ScheduleDAGInstrs *
     291        8783 :   createPostMachineScheduler(MachineSchedContext *C) const {
     292        8783 :     return nullptr;
     293             :   }
     294             : 
     295             :   /// printAndVerify - Add a pass to dump then verify the machine function, if
     296             :   /// those steps are enabled.
     297             :   void printAndVerify(const std::string &Banner);
     298             : 
     299             :   /// Add a pass to print the machine function if printing is enabled.
     300             :   void addPrintPass(const std::string &Banner);
     301             : 
     302             :   /// Add a pass to perform basic verification of the machine function if
     303             :   /// verification is enabled.
     304             :   void addVerifyPass(const std::string &Banner);
     305             : 
     306             :   /// Check whether or not GlobalISel should abort on error.
     307             :   /// When this is disabled, GlobalISel will fall back on SDISel instead of
     308             :   /// erroring out.
     309             :   bool isGlobalISelAbortEnabled() const;
     310             : 
     311             :   /// Check whether or not a diagnostic should be emitted when GlobalISel
     312             :   /// uses the fallback path. In other words, it will emit a diagnostic
     313             :   /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
     314             :   virtual bool reportDiagnosticWhenGlobalISelFallback() const;
     315             : 
     316             : protected:
     317             :   // Helper to verify the analysis is really immutable.
     318             :   void setOpt(bool &Opt, bool Val);
     319             : 
     320             :   /// Methods with trivial inline returns are convenient points in the common
     321             :   /// codegen pass pipeline where targets may insert passes. Methods with
     322             :   /// out-of-line standard implementations are major CodeGen stages called by
     323             :   /// addMachinePasses. Some targets may override major stages when inserting
     324             :   /// passes is insufficient, but maintaining overriden stages is more work.
     325             :   ///
     326             : 
     327             :   /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
     328             :   /// passes (which are run just before instruction selector).
     329        4727 :   virtual bool addPreISel() {
     330        4727 :     return true;
     331             :   }
     332             : 
     333             :   /// addMachineSSAOptimization - Add standard passes that optimize machine
     334             :   /// instructions in SSA form.
     335             :   virtual void addMachineSSAOptimization();
     336             : 
     337             :   /// Add passes that optimize instruction level parallelism for out-of-order
     338             :   /// targets. These passes are run while the machine code is still in SSA
     339             :   /// form, so they can use MachineTraceMetrics to control their heuristics.
     340             :   ///
     341             :   /// All passes added here should preserve the MachineDominatorTree,
     342             :   /// MachineLoopInfo, and MachineTraceMetrics analyses.
     343        6447 :   virtual bool addILPOpts() {
     344        6447 :     return false;
     345             :   }
     346             : 
     347             :   /// This method may be implemented by targets that want to run passes
     348             :   /// immediately before register allocation.
     349        1855 :   virtual void addPreRegAlloc() { }
     350             : 
     351             :   /// createTargetRegisterAllocator - Create the register allocator pass for
     352             :   /// this target at the current optimization level.
     353             :   virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
     354             : 
     355             :   /// addFastRegAlloc - Add the minimum set of target-independent passes that
     356             :   /// are required for fast register allocation.
     357             :   virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
     358             : 
     359             :   /// addOptimizedRegAlloc - Add passes related to register allocation.
     360             :   /// LLVMTargetMachine provides standard regalloc passes for most targets.
     361             :   virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
     362             : 
     363             :   /// addPreRewrite - Add passes to the optimized register allocation pipeline
     364             :   /// after register allocation is complete, but before virtual registers are
     365             :   /// rewritten to physical registers.
     366             :   ///
     367             :   /// These passes must preserve VirtRegMap and LiveIntervals, and when running
     368             :   /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
     369             :   /// When these passes run, VirtRegMap contains legal physreg assignments for
     370             :   /// all virtual registers.
     371       19632 :   virtual bool addPreRewrite() {
     372       19632 :     return false;
     373             :   }
     374             : 
     375             :   /// This method may be implemented by targets that want to run passes after
     376             :   /// register allocation pass pipeline but before prolog-epilog insertion.
     377        8033 :   virtual void addPostRegAlloc() { }
     378             : 
     379             :   /// Add passes that optimize machine instructions after register allocation.
     380             :   virtual void addMachineLateOptimization();
     381             : 
     382             :   /// This method may be implemented by targets that want to run passes after
     383             :   /// prolog-epilog insertion and before the second instruction scheduling pass.
     384        2904 :   virtual void addPreSched2() { }
     385             : 
     386             :   /// addGCPasses - Add late codegen passes that analyze code for garbage
     387             :   /// collection. This should return true if GC info should be printed after
     388             :   /// these passes.
     389             :   virtual bool addGCPasses();
     390             : 
     391             :   /// Add standard basic block placement passes.
     392             :   virtual void addBlockPlacement();
     393             : 
     394             :   /// This pass may be implemented by targets that want to run passes
     395             :   /// immediately before machine code is emitted.
     396         246 :   virtual void addPreEmitPass() { }
     397             : 
     398             :   /// Targets may add passes immediately before machine code is emitted in this
     399             :   /// callback. This is called even later than `addPreEmitPass`.
     400             :   // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
     401             :   // position and remove the `2` suffix here as this callback is what
     402             :   // `addPreEmitPass` *should* be but in reality isn't.
     403       12636 :   virtual void addPreEmitPass2() {}
     404             : 
     405             :   /// Utilities for targets to add passes to the pass manager.
     406             :   ///
     407             : 
     408             :   /// Add a CodeGen pass at this point in the pipeline after checking overrides.
     409             :   /// Return the pass that was added, or zero if no pass was added.
     410             :   /// @p printAfter    if true and adding a machine function pass add an extra
     411             :   ///                  machine printer pass afterwards
     412             :   /// @p verifyAfter   if true and adding a machine function pass add an extra
     413             :   ///                  machine verification pass afterwards.
     414             :   AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
     415             :                      bool printAfter = true);
     416             : 
     417             :   /// Add a pass to the PassManager if that pass is supposed to be run, as
     418             :   /// determined by the StartAfter and StopAfter options. Takes ownership of the
     419             :   /// pass.
     420             :   /// @p printAfter    if true and adding a machine function pass add an extra
     421             :   ///                  machine printer pass afterwards
     422             :   /// @p verifyAfter   if true and adding a machine function pass add an extra
     423             :   ///                  machine verification pass afterwards.
     424             :   void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
     425             : 
     426             :   /// addMachinePasses helper to create the target-selected or overriden
     427             :   /// regalloc pass.
     428             :   FunctionPass *createRegAllocPass(bool Optimized);
     429             : };
     430             : 
     431             : } // end namespace llvm
     432             : 
     433             : #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H

Generated by: LCOV version 1.13