LCOV - code coverage report
Current view: top level - include/llvm/CodeGen - TargetRegisterInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 102 126 81.0 %
Date: 2018-02-18 03:11:45 Functions: 25 38 65.8 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file describes an abstract interface used to get information about a
      11             : // target machines register file.  This information is used for a variety of
      12             : // purposed, especially register allocation.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
      17             : #define LLVM_CODEGEN_TARGETREGISTERINFO_H
      18             : 
      19             : #include "llvm/ADT/ArrayRef.h"
      20             : #include "llvm/ADT/SmallVector.h"
      21             : #include "llvm/ADT/StringRef.h"
      22             : #include "llvm/ADT/iterator_range.h"
      23             : #include "llvm/CodeGen/MachineBasicBlock.h"
      24             : #include "llvm/CodeGen/MachineValueType.h"
      25             : #include "llvm/IR/CallingConv.h"
      26             : #include "llvm/MC/LaneBitmask.h"
      27             : #include "llvm/MC/MCRegisterInfo.h"
      28             : #include "llvm/Support/ErrorHandling.h"
      29             : #include "llvm/Support/MathExtras.h"
      30             : #include "llvm/Support/Printable.h"
      31             : #include <cassert>
      32             : #include <cstdint>
      33             : #include <functional>
      34             : 
      35             : namespace llvm {
      36             : 
      37             : class BitVector;
      38             : class LiveRegMatrix;
      39             : class MachineFunction;
      40             : class MachineInstr;
      41             : class RegScavenger;
      42             : class VirtRegMap;
      43             : class LiveIntervals;
      44             : 
      45             : class TargetRegisterClass {
      46             : public:
      47             :   using iterator = const MCPhysReg *;
      48             :   using const_iterator = const MCPhysReg *;
      49             :   using sc_iterator = const TargetRegisterClass* const *;
      50             : 
      51             :   // Instance variables filled by tablegen, do not use!
      52             :   const MCRegisterClass *MC;
      53             :   const uint32_t *SubClassMask;
      54             :   const uint16_t *SuperRegIndices;
      55             :   const LaneBitmask LaneMask;
      56             :   /// Classes with a higher priority value are assigned first by register
      57             :   /// allocators using a greedy heuristic. The value is in the range [0,63].
      58             :   const uint8_t AllocationPriority;
      59             :   /// Whether the class supports two (or more) disjunct subregister indices.
      60             :   const bool HasDisjunctSubRegs;
      61             :   /// Whether a combination of subregisters can cover every register in the
      62             :   /// class. See also the CoveredBySubRegs description in Target.td.
      63             :   const bool CoveredBySubRegs;
      64             :   const sc_iterator SuperClasses;
      65             :   ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
      66             : 
      67             :   /// Return the register class ID number.
      68             :   unsigned getID() const { return MC->getID(); }
      69             : 
      70             :   /// begin/end - Return all of the registers in this class.
      71             :   ///
      72             :   iterator       begin() const { return MC->begin(); }
      73             :   iterator         end() const { return MC->end(); }
      74             : 
      75             :   /// Return the number of registers in this class.
      76             :   unsigned getNumRegs() const { return MC->getNumRegs(); }
      77             : 
      78             :   iterator_range<SmallVectorImpl<MCPhysReg>::const_iterator>
      79             :   getRegisters() const {
      80             :     return make_range(MC->begin(), MC->end());
      81             :   }
      82             : 
      83             :   /// Return the specified register in the class.
      84             :   unsigned getRegister(unsigned i) const {
      85             :     return MC->getRegister(i);
      86             :   }
      87             : 
      88             :   /// Return true if the specified register is included in this register class.
      89             :   /// This does not include virtual registers.
      90             :   bool contains(unsigned Reg) const {
      91             :     return MC->contains(Reg);
      92             :   }
      93             : 
      94             :   /// Return true if both registers are in this class.
      95             :   bool contains(unsigned Reg1, unsigned Reg2) const {
      96      428842 :     return MC->contains(Reg1, Reg2);
      97             :   }
      98             : 
      99             :   /// Return the cost of copying a value between two registers in this class.
     100             :   /// A negative number means the register class is very expensive
     101             :   /// to copy e.g. status flag register classes.
     102             :   int getCopyCost() const { return MC->getCopyCost(); }
     103             : 
     104             :   /// Return true if this register class may be used to create virtual
     105             :   /// registers.
     106             :   bool isAllocatable() const { return MC->isAllocatable(); }
     107             : 
     108             :   /// Return true if the specified TargetRegisterClass
     109             :   /// is a proper sub-class of this TargetRegisterClass.
     110             :   bool hasSubClass(const TargetRegisterClass *RC) const {
     111     3409700 :     return RC != this && hasSubClassEq(RC);
     112             :   }
     113             : 
     114             :   /// Returns true if RC is a sub-class of or equal to this class.
     115             :   bool hasSubClassEq(const TargetRegisterClass *RC) const {
     116             :     unsigned ID = RC->getID();
     117    16373066 :     return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
     118             :   }
     119             : 
     120             :   /// Return true if the specified TargetRegisterClass is a
     121             :   /// proper super-class of this TargetRegisterClass.
     122             :   bool hasSuperClass(const TargetRegisterClass *RC) const {
     123             :     return RC->hasSubClass(this);
     124             :   }
     125             : 
     126             :   /// Returns true if RC is a super-class of or equal to this class.
     127             :   bool hasSuperClassEq(const TargetRegisterClass *RC) const {
     128             :     return RC->hasSubClassEq(this);
     129             :   }
     130             : 
     131             :   /// Returns a bit vector of subclasses, including this one.
     132             :   /// The vector is indexed by class IDs.
     133             :   ///
     134             :   /// To use it, consider the returned array as a chunk of memory that
     135             :   /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
     136             :   /// contains a bitset of the ID of the subclasses in big-endian style.
     137             : 
     138             :   /// I.e., the representation of the memory from left to right at the
     139             :   /// bit level looks like:
     140             :   /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
     141             :   ///                     [ XXX NumRegClasses NumRegClasses - 1 ... ]
     142             :   /// Where the number represents the class ID and XXX bits that
     143             :   /// should be ignored.
     144             :   ///
     145             :   /// See the implementation of hasSubClassEq for an example of how it
     146             :   /// can be used.
     147             :   const uint32_t *getSubClassMask() const {
     148             :     return SubClassMask;
     149             :   }
     150             : 
     151             :   /// Returns a 0-terminated list of sub-register indices that project some
     152             :   /// super-register class into this register class. The list has an entry for
     153             :   /// each Idx such that:
     154             :   ///
     155             :   ///   There exists SuperRC where:
     156             :   ///     For all Reg in SuperRC:
     157             :   ///       this->contains(Reg:Idx)
     158             :   const uint16_t *getSuperRegIndices() const {
     159             :     return SuperRegIndices;
     160             :   }
     161             : 
     162             :   /// Returns a NULL-terminated list of super-classes.  The
     163             :   /// classes are ordered by ID which is also a topological ordering from large
     164             :   /// to small classes.  The list does NOT include the current class.
     165             :   sc_iterator getSuperClasses() const {
     166             :     return SuperClasses;
     167             :   }
     168             : 
     169             :   /// Return true if this TargetRegisterClass is a subset
     170             :   /// class of at least one other TargetRegisterClass.
     171             :   bool isASubClass() const {
     172             :     return SuperClasses[0] != nullptr;
     173             :   }
     174             : 
     175             :   /// Returns the preferred order for allocating registers from this register
     176             :   /// class in MF. The raw order comes directly from the .td file and may
     177             :   /// include reserved registers that are not allocatable.
     178             :   /// Register allocators should also make sure to allocate
     179             :   /// callee-saved registers only after all the volatiles are used. The
     180             :   /// RegisterClassInfo class provides filtered allocation orders with
     181             :   /// callee-saved registers moved to the end.
     182             :   ///
     183             :   /// The MachineFunction argument can be used to tune the allocatable
     184             :   /// registers based on the characteristics of the function, subtarget, or
     185             :   /// other criteria.
     186             :   ///
     187             :   /// By default, this method returns all registers in the class.
     188             :   ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
     189      447803 :     return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
     190             :   }
     191             : 
     192             :   /// Returns the combination of all lane masks of register in this class.
     193             :   /// The lane masks of the registers are the combination of all lane masks
     194             :   /// of their subregisters. Returns 1 if there are no subregisters.
     195             :   LaneBitmask getLaneMask() const {
     196             :     return LaneMask;
     197             :   }
     198             : };
     199             : 
     200             : /// Extra information, not in MCRegisterDesc, about registers.
     201             : /// These are used by codegen, not by MC.
     202             : struct TargetRegisterInfoDesc {
     203             :   unsigned CostPerUse;          // Extra cost of instructions using register.
     204             :   bool inAllocatableClass;      // Register belongs to an allocatable regclass.
     205             : };
     206             : 
     207             : /// Each TargetRegisterClass has a per register weight, and weight
     208             : /// limit which must be less than the limits of its pressure sets.
     209             : struct RegClassWeight {
     210             :   unsigned RegWeight;
     211             :   unsigned WeightLimit;
     212             : };
     213             : 
     214             : /// TargetRegisterInfo base class - We assume that the target defines a static
     215             : /// array of TargetRegisterDesc objects that represent all of the machine
     216             : /// registers that the target has.  As such, we simply have to track a pointer
     217             : /// to this array so that we can turn register number into a register
     218             : /// descriptor.
     219             : ///
     220       60490 : class TargetRegisterInfo : public MCRegisterInfo {
     221             : public:
     222             :   using regclass_iterator = const TargetRegisterClass * const *;
     223             :   using vt_iterator = const MVT::SimpleValueType *;
     224             :   struct RegClassInfo {
     225             :     unsigned RegSize, SpillSize, SpillAlignment;
     226             :     vt_iterator VTList;
     227             :   };
     228             : private:
     229             :   const TargetRegisterInfoDesc *InfoDesc;     // Extra desc array for codegen
     230             :   const char *const *SubRegIndexNames;        // Names of subreg indexes.
     231             :   // Pointer to array of lane masks, one per sub-reg index.
     232             :   const LaneBitmask *SubRegIndexLaneMasks;
     233             : 
     234             :   regclass_iterator RegClassBegin, RegClassEnd;   // List of regclasses
     235             :   LaneBitmask CoveringLanes;
     236             :   const RegClassInfo *const RCInfos;
     237             :   unsigned HwMode;
     238             : 
     239             : protected:
     240             :   TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
     241             :                      regclass_iterator RegClassBegin,
     242             :                      regclass_iterator RegClassEnd,
     243             :                      const char *const *SRINames,
     244             :                      const LaneBitmask *SRILaneMasks,
     245             :                      LaneBitmask CoveringLanes,
     246             :                      const RegClassInfo *const RSI,
     247             :                      unsigned Mode = 0);
     248             :   virtual ~TargetRegisterInfo();
     249             : 
     250             : public:
     251             :   // Register numbers can represent physical registers, virtual registers, and
     252             :   // sometimes stack slots. The unsigned values are divided into these ranges:
     253             :   //
     254             :   //   0           Not a register, can be used as a sentinel.
     255             :   //   [1;2^30)    Physical registers assigned by TableGen.
     256             :   //   [2^30;2^31) Stack slots. (Rarely used.)
     257             :   //   [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
     258             :   //
     259             :   // Further sentinels can be allocated from the small negative integers.
     260             :   // DenseMapInfo<unsigned> uses -1u and -2u.
     261             : 
     262             :   /// isStackSlot - Sometimes it is useful the be able to store a non-negative
     263             :   /// frame index in a variable that normally holds a register. isStackSlot()
     264             :   /// returns true if Reg is in the range used for stack slots.
     265             :   ///
     266             :   /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
     267             :   /// slots, so if a variable may contains a stack slot, always check
     268             :   /// isStackSlot() first.
     269             :   ///
     270             :   static bool isStackSlot(unsigned Reg) {
     271     1516371 :     return int(Reg) >= (1 << 30);
     272             :   }
     273             : 
     274             :   /// Compute the frame index from a register value representing a stack slot.
     275             :   static int stackSlot2Index(unsigned Reg) {
     276             :     assert(isStackSlot(Reg) && "Not a stack slot");
     277       81069 :     return int(Reg - (1u << 30));
     278             :   }
     279             : 
     280             :   /// Convert a non-negative frame index to a stack slot register value.
     281             :   static unsigned index2StackSlot(int FI) {
     282             :     assert(FI >= 0 && "Cannot hold a negative frame index.");
     283       92983 :     return FI + (1u << 30);
     284             :   }
     285             : 
     286             :   /// Return true if the specified register number is in
     287             :   /// the physical register namespace.
     288             :   static bool isPhysicalRegister(unsigned Reg) {
     289             :     assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
     290   241516309 :     return int(Reg) > 0;
     291             :   }
     292             : 
     293             :   /// Return true if the specified register number is in
     294             :   /// the virtual register namespace.
     295             :   static bool isVirtualRegister(unsigned Reg) {
     296             :     assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
     297   582787481 :     return int(Reg) < 0;
     298             :   }
     299             : 
     300             :   /// Convert a virtual register number to a 0-based index.
     301             :   /// The first virtual register in a function will get the index 0.
     302             :   static unsigned virtReg2Index(unsigned Reg) {
     303             :     assert(isVirtualRegister(Reg) && "Not a virtual register");
     304   297177135 :     return Reg & ~(1u << 31);
     305             :   }
     306             : 
     307             :   /// Convert a 0-based index to a virtual register number.
     308             :   /// This is the inverse operation of VirtReg2IndexFunctor below.
     309             :   static unsigned index2VirtReg(unsigned Index) {
     310    29553103 :     return Index | (1u << 31);
     311             :   }
     312             : 
     313             :   /// Return the size in bits of a register from class RC.
     314             :   unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
     315    15253848 :     return getRegClassInfo(RC).RegSize;
     316             :   }
     317             : 
     318             :   /// Return the size in bytes of the stack slot allocated to hold a spilled
     319             :   /// copy of a register from class RC.
     320             :   unsigned getSpillSize(const TargetRegisterClass &RC) const {
     321     2983493 :     return getRegClassInfo(RC).SpillSize / 8;
     322             :   }
     323             : 
     324             :   /// Return the minimum required alignment in bytes for a spill slot for
     325             :   /// a register of this class.
     326             :   unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
     327       91728 :     return getRegClassInfo(RC).SpillAlignment / 8;
     328             :   }
     329             : 
     330             :   /// Return true if the given TargetRegisterClass has the ValueType T.
     331             :   bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
     332   141675372 :     for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
     333    60229999 :       if (MVT(*I) == T)
     334             :         return true;
     335             :     return false;
     336             :   }
     337             : 
     338             :   /// Loop over all of the value types that can be represented by values
     339             :   /// in the given register class.
     340             :   vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const {
     341    43259369 :     return getRegClassInfo(RC).VTList;
     342             :   }
     343             : 
     344             :   vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const {
     345             :     vt_iterator I = legalclasstypes_begin(RC);
     346             :     while (*I != MVT::Other)
     347             :       ++I;
     348             :     return I;
     349             :   }
     350             : 
     351             :   /// Returns the Register Class of a physical register of the given type,
     352             :   /// picking the most sub register class of the right type that contains this
     353             :   /// physreg.
     354             :   const TargetRegisterClass *
     355             :     getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
     356             : 
     357             :   /// Return the maximal subclass of the given register class that is
     358             :   /// allocatable or NULL.
     359             :   const TargetRegisterClass *
     360             :     getAllocatableClass(const TargetRegisterClass *RC) const;
     361             : 
     362             :   /// Returns a bitset indexed by register number indicating if a register is
     363             :   /// allocatable or not. If a register class is specified, returns the subset
     364             :   /// for the class.
     365             :   BitVector getAllocatableSet(const MachineFunction &MF,
     366             :                               const TargetRegisterClass *RC = nullptr) const;
     367             : 
     368             :   /// Return the additional cost of using this register instead
     369             :   /// of other registers in its class.
     370             :   unsigned getCostPerUse(unsigned RegNo) const {
     371    17924726 :     return InfoDesc[RegNo].CostPerUse;
     372             :   }
     373             : 
     374             :   /// Return true if the register is in the allocation of any register class.
     375             :   bool isInAllocatableClass(unsigned RegNo) const {
     376    22687783 :     return InfoDesc[RegNo].inAllocatableClass;
     377             :   }
     378             : 
     379             :   /// Return the human-readable symbolic target-specific
     380             :   /// name for the specified SubRegIndex.
     381             :   const char *getSubRegIndexName(unsigned SubIdx) const {
     382             :     assert(SubIdx && SubIdx < getNumSubRegIndices() &&
     383             :            "This is not a subregister index");
     384        7680 :     return SubRegIndexNames[SubIdx-1];
     385             :   }
     386             : 
     387             :   /// Return a bitmask representing the parts of a register that are covered by
     388             :   /// SubIdx \see LaneBitmask.
     389             :   ///
     390             :   /// SubIdx == 0 is allowed, it has the lane mask ~0u.
     391             :   LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
     392             :     assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
     393    11682079 :     return SubRegIndexLaneMasks[SubIdx];
     394             :   }
     395             : 
     396             :   /// The lane masks returned by getSubRegIndexLaneMask() above can only be
     397             :   /// used to determine if sub-registers overlap - they can't be used to
     398             :   /// determine if a set of sub-registers completely cover another
     399             :   /// sub-register.
     400             :   ///
     401             :   /// The X86 general purpose registers have two lanes corresponding to the
     402             :   /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
     403             :   /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
     404             :   /// sub_32bit sub-register.
     405             :   ///
     406             :   /// On the other hand, the ARM NEON lanes fully cover their registers: The
     407             :   /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
     408             :   /// This is related to the CoveredBySubRegs property on register definitions.
     409             :   ///
     410             :   /// This function returns a bit mask of lanes that completely cover their
     411             :   /// sub-registers. More precisely, given:
     412             :   ///
     413             :   ///   Covering = getCoveringLanes();
     414             :   ///   MaskA = getSubRegIndexLaneMask(SubA);
     415             :   ///   MaskB = getSubRegIndexLaneMask(SubB);
     416             :   ///
     417             :   /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
     418             :   /// SubB.
     419             :   LaneBitmask getCoveringLanes() const { return CoveringLanes; }
     420             : 
     421             :   /// Returns true if the two registers are equal or alias each other.
     422             :   /// The registers may be virtual registers.
     423     3096585 :   bool regsOverlap(unsigned regA, unsigned regB) const {
     424     3096585 :     if (regA == regB) return true;
     425     5691283 :     if (isVirtualRegister(regA) || isVirtualRegister(regB))
     426             :       return false;
     427             : 
     428             :     // Regunits are numerically ordered. Find a common unit.
     429             :     MCRegUnitIterator RUA(regA, this);
     430             :     MCRegUnitIterator RUB(regB, this);
     431             :     do {
     432     4316970 :       if (*RUA == *RUB) return true;
     433     4300857 :       if (*RUA < *RUB) ++RUA;
     434             :       else             ++RUB;
     435     4300857 :     } while (RUA.isValid() && RUB.isValid());
     436             :     return false;
     437             :   }
     438             : 
     439             :   /// Returns true if Reg contains RegUnit.
     440     4578762 :   bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
     441     9029176 :     for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
     442     4628177 :       if (*Units == RegUnit)
     443             :         return true;
     444     4400999 :     return false;
     445             :   }
     446             : 
     447             :   /// Return a null-terminated list of all of the callee-saved registers on
     448             :   /// this target. The register should be in the order of desired callee-save
     449             :   /// stack frame offset. The first register is closest to the incoming stack
     450             :   /// pointer if stack grows down, and vice versa.
     451             :   /// Notice: This function does not take into account disabled CSRs.
     452             :   ///         In most cases you will want to use instead the function 
     453             :   ///         getCalleeSavedRegs that is implemented in MachineRegisterInfo.
     454             :   virtual const MCPhysReg*
     455             :   getCalleeSavedRegs(const MachineFunction *MF) const = 0;
     456             : 
     457             :   /// Return a mask of call-preserved registers for the given calling convention
     458             :   /// on the current function. The mask should include all call-preserved
     459             :   /// aliases. This is used by the register allocator to determine which
     460             :   /// registers can be live across a call.
     461             :   ///
     462             :   /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
     463             :   /// A set bit indicates that all bits of the corresponding register are
     464             :   /// preserved across the function call.  The bit mask is expected to be
     465             :   /// sub-register complete, i.e. if A is preserved, so are all its
     466             :   /// sub-registers.
     467             :   ///
     468             :   /// Bits are numbered from the LSB, so the bit for physical register Reg can
     469             :   /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
     470             :   ///
     471             :   /// A NULL pointer means that no register mask will be used, and call
     472             :   /// instructions should use implicit-def operands to indicate call clobbered
     473             :   /// registers.
     474             :   ///
     475           0 :   virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
     476             :                                                CallingConv::ID) const {
     477             :     // The default mask clobbers everything.  All targets should override.
     478           0 :     return nullptr;
     479             :   }
     480             : 
     481             :   /// Return a register mask that clobbers everything.
     482           0 :   virtual const uint32_t *getNoPreservedMask() const {
     483           0 :     llvm_unreachable("target does not provide no preserved mask");
     484             :   }
     485             : 
     486             :   /// Return true if all bits that are set in mask \p mask0 are also set in
     487             :   /// \p mask1.
     488             :   bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
     489             : 
     490             :   /// Return all the call-preserved register masks defined for this target.
     491             :   virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
     492             :   virtual ArrayRef<const char *> getRegMaskNames() const = 0;
     493             : 
     494             :   /// Returns a bitset indexed by physical register number indicating if a
     495             :   /// register is a special register that has particular uses and should be
     496             :   /// considered unavailable at all times, e.g. stack pointer, return address.
     497             :   /// A reserved register:
     498             :   /// - is not allocatable
     499             :   /// - is considered always live
     500             :   /// - is ignored by liveness tracking
     501             :   /// It is often necessary to reserve the super registers of a reserved
     502             :   /// register as well, to avoid them getting allocated indirectly. You may use
     503             :   /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
     504             :   virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
     505             : 
     506             :   /// Returns true if PhysReg is unallocatable and constant throughout the
     507             :   /// function.  Used by MachineRegisterInfo::isConstantPhysReg().
     508     6818221 :   virtual bool isConstantPhysReg(unsigned PhysReg) const { return false; }
     509             : 
     510             :   /// Physical registers that may be modified within a function but are
     511             :   /// guaranteed to be restored before any uses. This is useful for targets that
     512             :   /// have call sequences where a GOT register may be updated by the caller
     513             :   /// prior to a call and is guaranteed to be restored (also by the caller)
     514             :   /// after the call. 
     515      678150 :   virtual bool isCallerPreservedPhysReg(unsigned PhysReg,
     516             :                                         const MachineFunction &MF) const {
     517      678150 :     return false;
     518             :   }
     519             : 
     520             :   /// Prior to adding the live-out mask to a stackmap or patchpoint
     521             :   /// instruction, provide the target the opportunity to adjust it (mainly to
     522             :   /// remove pseudo-registers that should be ignored).
     523          46 :   virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
     524             : 
     525             :   /// Return a super-register of the specified register
     526             :   /// Reg so its sub-register of index SubIdx is Reg.
     527             :   unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
     528             :                                const TargetRegisterClass *RC) const {
     529       65772 :     return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
     530             :   }
     531             : 
     532             :   /// Return a subclass of the specified register
     533             :   /// class A so that each register in it has a sub-register of the
     534             :   /// specified sub-register index which is in the specified register class B.
     535             :   ///
     536             :   /// TableGen will synthesize missing A sub-classes.
     537             :   virtual const TargetRegisterClass *
     538             :   getMatchingSuperRegClass(const TargetRegisterClass *A,
     539             :                            const TargetRegisterClass *B, unsigned Idx) const;
     540             : 
     541             :   // For a copy-like instruction that defines a register of class DefRC with
     542             :   // subreg index DefSubReg, reading from another source with class SrcRC and
     543             :   // subregister SrcSubReg return true if this is a preferable copy
     544             :   // instruction or an earlier use should be used.
     545             :   virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
     546             :                                     unsigned DefSubReg,
     547             :                                     const TargetRegisterClass *SrcRC,
     548             :                                     unsigned SrcSubReg) const;
     549             : 
     550             :   /// Returns the largest legal sub-class of RC that
     551             :   /// supports the sub-register index Idx.
     552             :   /// If no such sub-class exists, return NULL.
     553             :   /// If all registers in RC already have an Idx sub-register, return RC.
     554             :   ///
     555             :   /// TableGen generates a version of this function that is good enough in most
     556             :   /// cases.  Targets can override if they have constraints that TableGen
     557             :   /// doesn't understand.  For example, the x86 sub_8bit sub-register index is
     558             :   /// supported by the full GR32 register class in 64-bit mode, but only by the
     559             :   /// GR32_ABCD regiister class in 32-bit mode.
     560             :   ///
     561             :   /// TableGen will synthesize missing RC sub-classes.
     562             :   virtual const TargetRegisterClass *
     563           0 :   getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
     564             :     assert(Idx == 0 && "Target has no sub-registers");
     565           0 :     return RC;
     566             :   }
     567             : 
     568             :   /// Return the subregister index you get from composing
     569             :   /// two subregister indices.
     570             :   ///
     571             :   /// The special null sub-register index composes as the identity.
     572             :   ///
     573             :   /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
     574             :   /// returns c. Note that composeSubRegIndices does not tell you about illegal
     575             :   /// compositions. If R does not have a subreg a, or R:a does not have a subreg
     576             :   /// b, composeSubRegIndices doesn't tell you.
     577             :   ///
     578             :   /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
     579             :   /// ssub_0:S0 - ssub_3:S3 subregs.
     580             :   /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
     581             :   unsigned composeSubRegIndices(unsigned a, unsigned b) const {
     582     5213444 :     if (!a) return b;
     583      921654 :     if (!b) return a;
     584      328244 :     return composeSubRegIndicesImpl(a, b);
     585             :   }
     586             : 
     587             :   /// Transforms a LaneMask computed for one subregister to the lanemask that
     588             :   /// would have been computed when composing the subsubregisters with IdxA
     589             :   /// first. @sa composeSubRegIndices()
     590             :   LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA,
     591             :                                          LaneBitmask Mask) const {
     592      201383 :     if (!IdxA)
     593        8354 :       return Mask;
     594      268347 :     return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
     595             :   }
     596             : 
     597             :   /// Transform a lanemask given for a virtual register to the corresponding
     598             :   /// lanemask before using subregister with index \p IdxA.
     599             :   /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
     600             :   /// valie lane mask (no invalid bits set) the following holds:
     601             :   /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
     602             :   /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
     603             :   /// => X1 == Mask
     604             :   LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA,
     605             :                                                 LaneBitmask LaneMask) const {
     606      486089 :     if (!IdxA)
     607      167724 :       return LaneMask;
     608      323738 :     return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
     609             :   }
     610             : 
     611             :   /// Debugging helper: dump register in human readable form to dbgs() stream.
     612             :   static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
     613             :                       const TargetRegisterInfo* TRI = nullptr);
     614             : 
     615             : protected:
     616             :   /// Overridden by TableGen in targets that have sub-registers.
     617           0 :   virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
     618           0 :     llvm_unreachable("Target has no sub-registers");
     619             :   }
     620             : 
     621             :   /// Overridden by TableGen in targets that have sub-registers.
     622             :   virtual LaneBitmask
     623           0 :   composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const {
     624           0 :     llvm_unreachable("Target has no sub-registers");
     625             :   }
     626             : 
     627           0 :   virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned,
     628             :                                                             LaneBitmask) const {
     629           0 :     llvm_unreachable("Target has no sub-registers");
     630             :   }
     631             : 
     632             : public:
     633             :   /// Find a common super-register class if it exists.
     634             :   ///
     635             :   /// Find a register class, SuperRC and two sub-register indices, PreA and
     636             :   /// PreB, such that:
     637             :   ///
     638             :   ///   1. PreA + SubA == PreB + SubB  (using composeSubRegIndices()), and
     639             :   ///
     640             :   ///   2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
     641             :   ///
     642             :   ///   3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
     643             :   ///
     644             :   /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
     645             :   /// requirements, and there is no register class with a smaller spill size
     646             :   /// that satisfies the requirements.
     647             :   ///
     648             :   /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
     649             :   ///
     650             :   /// Either of the PreA and PreB sub-register indices may be returned as 0. In
     651             :   /// that case, the returned register class will be a sub-class of the
     652             :   /// corresponding argument register class.
     653             :   ///
     654             :   /// The function returns NULL if no register class can be found.
     655             :   const TargetRegisterClass*
     656             :   getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
     657             :                          const TargetRegisterClass *RCB, unsigned SubB,
     658             :                          unsigned &PreA, unsigned &PreB) const;
     659             : 
     660             :   //===--------------------------------------------------------------------===//
     661             :   // Register Class Information
     662             :   //
     663             : protected:
     664             :   const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
     665   180033806 :     return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
     666             :   }
     667             : 
     668             : public:
     669             :   /// Register class iterators
     670             :   regclass_iterator regclass_begin() const { return RegClassBegin; }
     671             :   regclass_iterator regclass_end() const { return RegClassEnd; }
     672             :   iterator_range<regclass_iterator> regclasses() const {
     673             :     return make_range(regclass_begin(), regclass_end());
     674             :   }
     675             : 
     676             :   unsigned getNumRegClasses() const {
     677    70213090 :     return (unsigned)(regclass_end()-regclass_begin());
     678             :   }
     679             : 
     680             :   /// Returns the register class associated with the enumeration value.
     681             :   /// See class MCOperandInfo.
     682             :   const TargetRegisterClass *getRegClass(unsigned i) const {
     683             :     assert(i < getNumRegClasses() && "Register Class ID out of range");
     684    51415120 :     return RegClassBegin[i];
     685             :   }
     686             : 
     687             :   /// Returns the name of the register class.
     688             :   const char *getRegClassName(const TargetRegisterClass *Class) const {
     689             :     return MCRegisterInfo::getRegClassName(Class->MC);
     690             :   }
     691             : 
     692             :   /// Find the largest common subclass of A and B.
     693             :   /// Return NULL if there is no common subclass.
     694             :   /// The common subclass should contain
     695             :   /// simple value type SVT if it is not the Any type.
     696             :   const TargetRegisterClass *
     697             :   getCommonSubClass(const TargetRegisterClass *A,
     698             :                     const TargetRegisterClass *B,
     699             :                     const MVT::SimpleValueType SVT =
     700             :                     MVT::SimpleValueType::Any) const;
     701             : 
     702             :   /// Returns a TargetRegisterClass used for pointer values.
     703             :   /// If a target supports multiple different pointer register classes,
     704             :   /// kind specifies which one is indicated.
     705             :   virtual const TargetRegisterClass *
     706           0 :   getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
     707           0 :     llvm_unreachable("Target didn't implement getPointerRegClass!");
     708             :   }
     709             : 
     710             :   /// Returns a legal register class to copy a register in the specified class
     711             :   /// to or from. If it is possible to copy the register directly without using
     712             :   /// a cross register class copy, return the specified RC. Returns NULL if it
     713             :   /// is not possible to copy between two registers of the specified class.
     714             :   virtual const TargetRegisterClass *
     715           0 :   getCrossCopyRegClass(const TargetRegisterClass *RC) const {
     716           0 :     return RC;
     717             :   }
     718             : 
     719             :   /// Returns the largest super class of RC that is legal to use in the current
     720             :   /// sub-target and has the same spill size.
     721             :   /// The returned register class can be used to create virtual registers which
     722             :   /// means that all its registers can be copied and spilled.
     723             :   virtual const TargetRegisterClass *
     724      919013 :   getLargestLegalSuperClass(const TargetRegisterClass *RC,
     725             :                             const MachineFunction &) const {
     726             :     /// The default implementation is very conservative and doesn't allow the
     727             :     /// register allocator to inflate register classes.
     728      919013 :     return RC;
     729             :   }
     730             : 
     731             :   /// Return the register pressure "high water mark" for the specific register
     732             :   /// class. The scheduler is in high register pressure mode (for the specific
     733             :   /// register class) if it goes over the limit.
     734             :   ///
     735             :   /// Note: this is the old register pressure model that relies on a manually
     736             :   /// specified representative register class per value type.
     737        1194 :   virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
     738             :                                        MachineFunction &MF) const {
     739        1194 :     return 0;
     740             :   }
     741             : 
     742             :   /// Return a heuristic for the machine scheduler to compare the profitability
     743             :   /// of increasing one register pressure set versus another.  The scheduler
     744             :   /// will prefer increasing the register pressure of the set which returns
     745             :   /// the largest value for this function.
     746      288100 :   virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
     747             :                                           unsigned PSetID) const {
     748      288100 :     return PSetID;
     749             :   }
     750             : 
     751             :   /// Get the weight in units of pressure for this register class.
     752             :   virtual const RegClassWeight &getRegClassWeight(
     753             :     const TargetRegisterClass *RC) const = 0;
     754             : 
     755             :   /// Returns size in bits of a phys/virtual/generic register.
     756             :   unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const;
     757             : 
     758             :   /// Get the weight in units of pressure for this register unit.
     759             :   virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
     760             : 
     761             :   /// Get the number of dimensions of register pressure.
     762             :   virtual unsigned getNumRegPressureSets() const = 0;
     763             : 
     764             :   /// Get the name of this register unit pressure set.
     765             :   virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
     766             : 
     767             :   /// Get the register unit pressure limit for this dimension.
     768             :   /// This limit must be adjusted dynamically for reserved registers.
     769             :   virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
     770             :                                           unsigned Idx) const = 0;
     771             : 
     772             :   /// Get the dimensions of register pressure impacted by this register class.
     773             :   /// Returns a -1 terminated array of pressure set IDs.
     774             :   virtual const int *getRegClassPressureSets(
     775             :     const TargetRegisterClass *RC) const = 0;
     776             : 
     777             :   /// Get the dimensions of register pressure impacted by this register unit.
     778             :   /// Returns a -1 terminated array of pressure set IDs.
     779             :   virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
     780             : 
     781             :   /// Get a list of 'hint' registers that the register allocator should try
     782             :   /// first when allocating a physical register for the virtual register
     783             :   /// VirtReg. These registers are effectively moved to the front of the
     784             :   /// allocation order. If true is returned, regalloc will try to only use
     785             :   /// hints to the greatest extent possible even if it means spilling.
     786             :   ///
     787             :   /// The Order argument is the allocation order for VirtReg's register class
     788             :   /// as returned from RegisterClassInfo::getOrder(). The hint registers must
     789             :   /// come from Order, and they must not be reserved.
     790             :   ///
     791             :   /// The default implementation of this function will only add target
     792             :   /// independent register allocation hints. Targets that override this
     793             :   /// function should typically call this default implementation as well and
     794             :   /// expect to see generic copy hints added.
     795             :   virtual bool getRegAllocationHints(unsigned VirtReg,
     796             :                                      ArrayRef<MCPhysReg> Order,
     797             :                                      SmallVectorImpl<MCPhysReg> &Hints,
     798             :                                      const MachineFunction &MF,
     799             :                                      const VirtRegMap *VRM = nullptr,
     800             :                                      const LiveRegMatrix *Matrix = nullptr)
     801             :     const;
     802             : 
     803             :   /// A callback to allow target a chance to update register allocation hints
     804             :   /// when a register is "changed" (e.g. coalesced) to another register.
     805             :   /// e.g. On ARM, some virtual registers should target register pairs,
     806             :   /// if one of pair is coalesced to another register, the allocation hint of
     807             :   /// the other half of the pair should be changed to point to the new register.
     808      593729 :   virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
     809             :                                   MachineFunction &MF) const {
     810             :     // Do nothing.
     811      593729 :   }
     812             : 
     813             :   /// The creation of multiple copy hints have been implemented in
     814             :   /// weightCalcHelper(), but since this affects so many tests for many
     815             :   /// targets, this is temporarily disabled per default. THIS SHOULD BE
     816             :   /// "GENERAL GOODNESS" and hopefully all targets will update their tests
     817             :   /// and enable this soon. This hook should then be removed.
     818     1870936 :   virtual bool enableMultipleCopyHints() const { return false; }
     819             : 
     820             :   /// Allow the target to reverse allocation order of local live ranges. This
     821             :   /// will generally allocate shorter local live ranges first. For targets with
     822             :   /// many registers, this could reduce regalloc compile time by a large
     823             :   /// factor. It is disabled by default for three reasons:
     824             :   /// (1) Top-down allocation is simpler and easier to debug for targets that
     825             :   /// don't benefit from reversing the order.
     826             :   /// (2) Bottom-up allocation could result in poor evicition decisions on some
     827             :   /// targets affecting the performance of compiled code.
     828             :   /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
     829     1366223 :   virtual bool reverseLocalAssignment() const { return false; }
     830             : 
     831             :   /// Allow the target to override the cost of using a callee-saved register for
     832             :   /// the first time. Default value of 0 means we will use a callee-saved
     833             :   /// register if it is available.
     834      129306 :   virtual unsigned getCSRFirstUseCost() const { return 0; }
     835             : 
     836             :   /// Returns true if the target requires (and can make use of) the register
     837             :   /// scavenger.
     838      275109 :   virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
     839      275109 :     return false;
     840             :   }
     841             : 
     842             :   /// Returns true if the target wants to use frame pointer based accesses to
     843             :   /// spill to the scavenger emergency spill slot.
     844       38831 :   virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
     845       38831 :     return true;
     846             :   }
     847             : 
     848             :   /// Returns true if the target requires post PEI scavenging of registers for
     849             :   /// materializing frame index constants.
     850      125961 :   virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
     851      125961 :     return false;
     852             :   }
     853             : 
     854             :   /// Returns true if the target requires using the RegScavenger directly for
     855             :   /// frame elimination despite using requiresFrameIndexScavenging.
     856      182918 :   virtual bool requiresFrameIndexReplacementScavenging(
     857             :       const MachineFunction &MF) const {
     858      182918 :     return false;
     859             :   }
     860             : 
     861             :   /// Returns true if the target wants the LocalStackAllocation pass to be run
     862             :   /// and virtual base registers used for more efficient stack access.
     863      149616 :   virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
     864      149616 :     return false;
     865             :   }
     866             : 
     867             :   /// Return true if target has reserved a spill slot in the stack frame of
     868             :   /// the given function for the specified register. e.g. On x86, if the frame
     869             :   /// register is required, the first fixed stack object is reserved as its
     870             :   /// spill slot. This tells PEI not to create a new stack frame
     871             :   /// object for the given register. It should be called only after
     872             :   /// determineCalleeSaves().
     873       23043 :   virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
     874             :                                     int &FrameIdx) const {
     875       23043 :     return false;
     876             :   }
     877             : 
     878             :   /// Returns true if the live-ins should be tracked after register allocation.
     879        4091 :   virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
     880        4091 :     return false;
     881             :   }
     882             : 
     883             :   /// True if the stack can be realigned for the target.
     884             :   virtual bool canRealignStack(const MachineFunction &MF) const;
     885             : 
     886             :   /// True if storage within the function requires the stack pointer to be
     887             :   /// aligned more than the normal calling convention calls for.
     888             :   /// This cannot be overriden by the target, but canRealignStack can be
     889             :   /// overridden.
     890             :   bool needsStackRealignment(const MachineFunction &MF) const;
     891             : 
     892             :   /// Get the offset from the referenced frame index in the instruction,
     893             :   /// if there is one.
     894          18 :   virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
     895             :                                            int Idx) const {
     896          18 :     return 0;
     897             :   }
     898             : 
     899             :   /// Returns true if the instruction's frame index reference would be better
     900             :   /// served by a base register other than FP or SP.
     901             :   /// Used by LocalStackFrameAllocation to determine which frame index
     902             :   /// references it should create new base registers for.
     903           0 :   virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
     904           0 :     return false;
     905             :   }
     906             : 
     907             :   /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
     908             :   /// before insertion point I.
     909           0 :   virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
     910             :                                             unsigned BaseReg, int FrameIdx,
     911             :                                             int64_t Offset) const {
     912           0 :     llvm_unreachable("materializeFrameBaseRegister does not exist on this "
     913             :                      "target");
     914             :   }
     915             : 
     916             :   /// Resolve a frame index operand of an instruction
     917             :   /// to reference the indicated base register plus offset instead.
     918           0 :   virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
     919             :                                  int64_t Offset) const {
     920           0 :     llvm_unreachable("resolveFrameIndex does not exist on this target");
     921             :   }
     922             : 
     923             :   /// Determine whether a given base register plus offset immediate is
     924             :   /// encodable to resolve a frame index.
     925           0 :   virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
     926             :                                   int64_t Offset) const {
     927           0 :     llvm_unreachable("isFrameOffsetLegal does not exist on this target");
     928             :   }
     929             : 
     930             :   /// Spill the register so it can be used by the register scavenger.
     931             :   /// Return true if the register was spilled, false otherwise.
     932             :   /// If this function does not spill the register, the scavenger
     933             :   /// will instead spill it to the emergency spill slot.
     934          25 :   virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
     935             :                                      MachineBasicBlock::iterator I,
     936             :                                      MachineBasicBlock::iterator &UseMI,
     937             :                                      const TargetRegisterClass *RC,
     938             :                                      unsigned Reg) const {
     939          25 :     return false;
     940             :   }
     941             : 
     942             :   /// This method must be overriden to eliminate abstract frame indices from
     943             :   /// instructions which may use them. The instruction referenced by the
     944             :   /// iterator contains an MO_FrameIndex operand which must be eliminated by
     945             :   /// this method. This method may modify or replace the specified instruction,
     946             :   /// as long as it keeps the iterator pointing at the finished product.
     947             :   /// SPAdj is the SP adjustment due to call frame setup instruction.
     948             :   /// FIOperandNum is the FI operand number.
     949             :   virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
     950             :                                    int SPAdj, unsigned FIOperandNum,
     951             :                                    RegScavenger *RS = nullptr) const = 0;
     952             : 
     953             :   /// Return the assembly name for \p Reg.
     954    66123928 :   virtual StringRef getRegAsmName(unsigned Reg) const {
     955             :     // FIXME: We are assuming that the assembly name is equal to the TableGen
     956             :     // name converted to lower case
     957             :     //
     958             :     // The TableGen name is the name of the definition for this register in the
     959             :     // target's tablegen files.  For example, the TableGen name of
     960             :     // def EAX : Register <...>; is "EAX"
     961    66123928 :     return StringRef(getName(Reg));
     962             :   }
     963             : 
     964             :   //===--------------------------------------------------------------------===//
     965             :   /// Subtarget Hooks
     966             : 
     967             :   /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true.
     968      473957 :   virtual bool shouldCoalesce(MachineInstr *MI,
     969             :                               const TargetRegisterClass *SrcRC,
     970             :                               unsigned SubReg,
     971             :                               const TargetRegisterClass *DstRC,
     972             :                               unsigned DstSubReg,
     973             :                               const TargetRegisterClass *NewRC,
     974             :                               LiveIntervals &LIS) const
     975      473957 :   { return true; }
     976             : 
     977             :   //===--------------------------------------------------------------------===//
     978             :   /// Debug information queries.
     979             : 
     980             :   /// getFrameRegister - This method should return the register used as a base
     981             :   /// for values allocated in the current stack frame.
     982             :   virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
     983             : 
     984             :   /// Mark a register and all its aliases as reserved in the given set.
     985             :   void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const;
     986             : 
     987             :   /// Returns true if for every register in the set all super registers are part
     988             :   /// of the set as well.
     989             :   bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
     990             :       ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
     991             : };
     992             : 
     993             : //===----------------------------------------------------------------------===//
     994             : //                           SuperRegClassIterator
     995             : //===----------------------------------------------------------------------===//
     996             : //
     997             : // Iterate over the possible super-registers for a given register class. The
     998             : // iterator will visit a list of pairs (Idx, Mask) corresponding to the
     999             : // possible classes of super-registers.
    1000             : //
    1001             : // Each bit mask will have at least one set bit, and each set bit in Mask
    1002             : // corresponds to a SuperRC such that:
    1003             : //
    1004             : //   For all Reg in SuperRC: Reg:Idx is in RC.
    1005             : //
    1006             : // The iterator can include (O, RC->getSubClassMask()) as the first entry which
    1007             : // also satisfies the above requirement, assuming Reg:0 == Reg.
    1008             : //
    1009             : class SuperRegClassIterator {
    1010             :   const unsigned RCMaskWords;
    1011             :   unsigned SubReg = 0;
    1012             :   const uint16_t *Idx;
    1013             :   const uint32_t *Mask;
    1014             : 
    1015             : public:
    1016             :   /// Create a SuperRegClassIterator that visits all the super-register classes
    1017             :   /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
    1018             :   SuperRegClassIterator(const TargetRegisterClass *RC,
    1019             :                         const TargetRegisterInfo *TRI,
    1020             :                         bool IncludeSelf = false)
    1021     1880077 :     : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
    1022             :       Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
    1023             :     if (!IncludeSelf)
    1024             :       ++*this;
    1025             :   }
    1026             : 
    1027             :   /// Returns true if this iterator is still pointing at a valid entry.
    1028             :   bool isValid() const { return Idx; }
    1029             : 
    1030             :   /// Returns the current sub-register index.
    1031             :   unsigned getSubReg() const { return SubReg; }
    1032             : 
    1033             :   /// Returns the bit mask of register classes that getSubReg() projects into
    1034             :   /// RC.
    1035             :   /// See TargetRegisterClass::getSubClassMask() for how to use it.
    1036             :   const uint32_t *getMask() const { return Mask; }
    1037             : 
    1038             :   /// Advance iterator to the next entry.
    1039             :   void operator++() {
    1040             :     assert(isValid() && "Cannot move iterator past end.");
    1041     4163186 :     Mask += RCMaskWords;
    1042     4163186 :     SubReg = *Idx++;
    1043     4163186 :     if (!SubReg)
    1044             :       Idx = nullptr;
    1045             :   }
    1046             : };
    1047             : 
    1048             : //===----------------------------------------------------------------------===//
    1049             : //                           BitMaskClassIterator
    1050             : //===----------------------------------------------------------------------===//
    1051             : /// This class encapuslates the logic to iterate over bitmask returned by
    1052             : /// the various RegClass related APIs.
    1053             : /// E.g., this class can be used to iterate over the subclasses provided by
    1054             : /// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
    1055             : class BitMaskClassIterator {
    1056             :   /// Total number of register classes.
    1057             :   const unsigned NumRegClasses;
    1058             :   /// Base index of CurrentChunk.
    1059             :   /// In other words, the number of bit we read to get at the
    1060             :   /// beginning of that chunck.
    1061             :   unsigned Base = 0;
    1062             :   /// Adjust base index of CurrentChunk.
    1063             :   /// Base index + how many bit we read within CurrentChunk.
    1064             :   unsigned Idx = 0;
    1065             :   /// Current register class ID.
    1066             :   unsigned ID = 0;
    1067             :   /// Mask we are iterating over.
    1068             :   const uint32_t *Mask;
    1069             :   /// Current chunk of the Mask we are traversing.
    1070             :   uint32_t CurrentChunk;
    1071             : 
    1072             :   /// Move ID to the next set bit.
    1073       27745 :   void moveToNextID() {
    1074             :     // If the current chunk of memory is empty, move to the next one,
    1075             :     // while making sure we do not go pass the number of register
    1076             :     // classes.
    1077      108357 :     while (!CurrentChunk) {
    1078             :       // Move to the next chunk.
    1079       53895 :       Base += 32;
    1080       53895 :       if (Base >= NumRegClasses) {
    1081       13589 :         ID = NumRegClasses;
    1082       13589 :         return;
    1083             :       }
    1084       40306 :       CurrentChunk = *++Mask;
    1085       40306 :       Idx = Base;
    1086             :     }
    1087             :     // Otherwise look for the first bit set from the right
    1088             :     // (representation of the class ID is big endian).
    1089             :     // See getSubClassMask for more details on the representation.
    1090       14156 :     unsigned Offset = countTrailingZeros(CurrentChunk);
    1091             :     // Add the Offset to the adjusted base number of this chunk: Idx.
    1092             :     // This is the ID of the register class.
    1093       14156 :     ID = Idx + Offset;
    1094             : 
    1095             :     // Consume the zeros, if any, and the bit we just read
    1096             :     // so that we are at the right spot for the next call.
    1097             :     // Do not do Offset + 1 because Offset may be 31 and 32
    1098             :     // will be UB for the shift, though in that case we could
    1099             :     // have make the chunk being equal to 0, but that would
    1100             :     // have introduced a if statement.
    1101             :     moveNBits(Offset);
    1102             :     moveNBits(1);
    1103             :   }
    1104             : 
    1105             :   /// Move \p NumBits Bits forward in CurrentChunk.
    1106             :   void moveNBits(unsigned NumBits) {
    1107             :     assert(NumBits < 32 && "Undefined behavior spotted!");
    1108             :     // Consume the bit we read for the next call.
    1109       14156 :     CurrentChunk >>= NumBits;
    1110             :     // Adjust the base for the chunk.
    1111       14156 :     Idx += NumBits;
    1112             :   }
    1113             : 
    1114             : public:
    1115             :   /// Create a BitMaskClassIterator that visits all the register classes
    1116             :   /// represented by \p Mask.
    1117             :   ///
    1118             :   /// \pre \p Mask != nullptr
    1119             :   BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
    1120       27714 :       : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
    1121             :     // Move to the first ID.
    1122       13857 :     moveToNextID();
    1123             :   }
    1124             : 
    1125             :   /// Returns true if this iterator is still pointing at a valid entry.
    1126       27745 :   bool isValid() const { return getID() != NumRegClasses; }
    1127             : 
    1128             :   /// Returns the current register class ID.
    1129             :   unsigned getID() const { return ID; }
    1130             : 
    1131             :   /// Advance iterator to the next entry.
    1132             :   void operator++() {
    1133             :     assert(isValid() && "Cannot move iterator past end.");
    1134       13888 :     moveToNextID();
    1135             :   }
    1136             : };
    1137             : 
    1138             : // This is useful when building IndexedMaps keyed on virtual registers
    1139             : struct VirtReg2IndexFunctor {
    1140             :   using argument_type = unsigned;
    1141             :   unsigned operator()(unsigned Reg) const {
    1142             :     return TargetRegisterInfo::virtReg2Index(Reg);
    1143             :   }
    1144             : };
    1145             : 
    1146             : /// Prints virtual and physical registers with or without a TRI instance.
    1147             : ///
    1148             : /// The format is:
    1149             : ///   %noreg          - NoRegister
    1150             : ///   %5              - a virtual register.
    1151             : ///   %5:sub_8bit     - a virtual register with sub-register index (with TRI).
    1152             : ///   %eax            - a physical register
    1153             : ///   %physreg17      - a physical register when no TRI instance given.
    1154             : ///
    1155             : /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
    1156             : Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
    1157             :                    unsigned SubRegIdx = 0);
    1158             : 
    1159             : /// Create Printable object to print register units on a \ref raw_ostream.
    1160             : ///
    1161             : /// Register units are named after their root registers:
    1162             : ///
    1163             : ///   al      - Single root.
    1164             : ///   fp0~st7 - Dual roots.
    1165             : ///
    1166             : /// Usage: OS << printRegUnit(Unit, TRI) << '\n';
    1167             : Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
    1168             : 
    1169             : /// \brief Create Printable object to print virtual registers and physical
    1170             : /// registers on a \ref raw_ostream.
    1171             : Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
    1172             : 
    1173             : /// \brief Create Printable object to print register classes or register banks
    1174             : /// on a \ref raw_ostream.
    1175             : Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
    1176             :                               const TargetRegisterInfo *TRI);
    1177             : 
    1178             : } // end namespace llvm
    1179             : 
    1180             : #endif // LLVM_CODEGEN_TARGETREGISTERINFO_H

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