LCOV - code coverage report
Current view: top level - include/llvm/MC - MCInstrAnalysis.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 7 16 43.8 %
Date: 2018-07-13 00:08:38 Functions: 3 9 33.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/MC/MCInstrAnalysis.h - InstrDesc target hooks -------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines the MCInstrAnalysis class which the MCTargetDescs can
      11             : // derive from to give additional information to MC.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #ifndef LLVM_MC_MCINSTRANALYSIS_H
      16             : #define LLVM_MC_MCINSTRANALYSIS_H
      17             : 
      18             : #include "llvm/MC/MCInst.h"
      19             : #include "llvm/MC/MCInstrDesc.h"
      20             : #include "llvm/MC/MCInstrInfo.h"
      21             : #include <cstdint>
      22             : 
      23             : namespace llvm {
      24             : 
      25             : class MCRegisterInfo;
      26             : 
      27             : class MCInstrAnalysis {
      28             : protected:
      29             :   friend class Target;
      30             : 
      31             :   const MCInstrInfo *Info;
      32             : 
      33             : public:
      34        1569 :   MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {}
      35           0 :   virtual ~MCInstrAnalysis() = default;
      36             : 
      37           0 :   virtual bool isBranch(const MCInst &Inst) const {
      38           0 :     return Info->get(Inst.getOpcode()).isBranch();
      39             :   }
      40             : 
      41      327217 :   virtual bool isConditionalBranch(const MCInst &Inst) const {
      42      669293 :     return Info->get(Inst.getOpcode()).isConditionalBranch();
      43             :   }
      44             : 
      45      332244 :   virtual bool isUnconditionalBranch(const MCInst &Inst) const {
      46      679437 :     return Info->get(Inst.getOpcode()).isUnconditionalBranch();
      47             :   }
      48             : 
      49           0 :   virtual bool isIndirectBranch(const MCInst &Inst) const {
      50           0 :     return Info->get(Inst.getOpcode()).isIndirectBranch();
      51             :   }
      52             : 
      53     3166633 :   virtual bool isCall(const MCInst &Inst) const {
      54     9499899 :     return Info->get(Inst.getOpcode()).isCall();
      55             :   }
      56             : 
      57           0 :   virtual bool isReturn(const MCInst &Inst) const {
      58           0 :     return Info->get(Inst.getOpcode()).isReturn();
      59             :   }
      60             : 
      61           0 :   virtual bool isTerminator(const MCInst &Inst) const {
      62           0 :     return Info->get(Inst.getOpcode()).isTerminator();
      63             :   }
      64             : 
      65             :   /// Returns true if at least one of the register writes performed by
      66             :   /// \param Inst implicitly clears the upper portion of all super-registers.
      67             :   /// 
      68             :   /// Example: on X86-64, a write to EAX implicitly clears the upper half of
      69             :   /// RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit
      70             :   /// instruction implicitly clears the upper portion of the correspondent
      71             :   /// YMM register.
      72             :   ///
      73             :   /// This method also updates an APInt which is used as mask of register
      74             :   /// writes. There is one bit for every explicit/implicit write performed by
      75             :   /// the instruction. If a write implicitly clears its super-registers, then
      76             :   /// the corresponding bit is set (vic. the corresponding bit is cleared).
      77             :   ///
      78             :   /// The first bits in the APint are related to explicit writes. The remaining
      79             :   /// bits are related to implicit writes. The sequence of writes follows the
      80             :   /// machine operand sequence. For implicit writes, the sequence is defined by
      81             :   /// the MCInstrDesc.
      82             :   ///
      83             :   /// The assumption is that the bit-width of the APInt is correctly set by
      84             :   /// the caller. The default implementation conservatively assumes that none of
      85             :   /// the writes clears the upper portion of a super-register.
      86             :   virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI,
      87             :                                     const MCInst &Inst,
      88             :                                     APInt &Writes) const;
      89             : 
      90             :   /// Given a branch instruction try to get the address the branch
      91             :   /// targets. Return true on success, and the address in Target.
      92             :   virtual bool
      93             :   evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
      94             :                  uint64_t &Target) const;
      95             : };
      96             : 
      97             : } // end namespace llvm
      98             : 
      99             : #endif // LLVM_MC_MCINSTRANALYSIS_H

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