LCOV - code coverage report
Current view: top level - include/llvm/MC - MCInstrDesc.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 40 42 95.2 %
Date: 2018-05-20 00:06:23 Functions: 0 0 -
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines the MCOperandInfo and MCInstrDesc classes, which
      11             : // are used to describe target instructions and their operands.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #ifndef LLVM_MC_MCINSTRDESC_H
      16             : #define LLVM_MC_MCINSTRDESC_H
      17             : 
      18             : #include "llvm/MC/MCRegisterInfo.h"
      19             : #include "llvm/Support/DataTypes.h"
      20             : #include <string>
      21             : 
      22             : namespace llvm {
      23             :   class MCInst;
      24             :   class MCSubtargetInfo;
      25             :   class FeatureBitset;
      26             : 
      27             : //===----------------------------------------------------------------------===//
      28             : // Machine Operand Flags and Description
      29             : //===----------------------------------------------------------------------===//
      30             : 
      31             : namespace MCOI {
      32             : // Operand constraints
      33             : enum OperandConstraint {
      34             :   TIED_TO = 0,  // Must be allocated the same register as.
      35             :   EARLY_CLOBBER // Operand is an early clobber register operand
      36             : };
      37             : 
      38             : /// These are flags set on operands, but should be considered
      39             : /// private, all access should go through the MCOperandInfo accessors.
      40             : /// See the accessors for a description of what these are.
      41             : enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef };
      42             : 
      43             : /// Operands are tagged with one of the values of this enum.
      44             : enum OperandType {
      45             :   OPERAND_UNKNOWN = 0,
      46             :   OPERAND_IMMEDIATE = 1,
      47             :   OPERAND_REGISTER = 2,
      48             :   OPERAND_MEMORY = 3,
      49             :   OPERAND_PCREL = 4,
      50             : 
      51             :   OPERAND_FIRST_GENERIC = 6,
      52             :   OPERAND_GENERIC_0 = 6,
      53             :   OPERAND_GENERIC_1 = 7,
      54             :   OPERAND_GENERIC_2 = 8,
      55             :   OPERAND_GENERIC_3 = 9,
      56             :   OPERAND_GENERIC_4 = 10,
      57             :   OPERAND_GENERIC_5 = 11,
      58             :   OPERAND_LAST_GENERIC = 11,
      59             : 
      60             :   OPERAND_FIRST_TARGET = 12,
      61             : };
      62             : 
      63             : }
      64             : 
      65             : /// This holds information about one operand of a machine instruction,
      66             : /// indicating the register class for register operands, etc.
      67             : class MCOperandInfo {
      68             : public:
      69             :   /// This specifies the register class enumeration of the operand
      70             :   /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
      71             :   /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
      72             :   /// get a dynamic register class.
      73             :   int16_t RegClass;
      74             : 
      75             :   /// These are flags from the MCOI::OperandFlags enum.
      76             :   uint8_t Flags;
      77             : 
      78             :   /// Information about the type of the operand.
      79             :   uint8_t OperandType;
      80             :   /// The lower 16 bits are used to specify which constraints are set.
      81             :   /// The higher 16 bits are used to specify the value of constraints (4 bits
      82             :   /// each).
      83             :   uint32_t Constraints;
      84             : 
      85             :   /// Set if this operand is a pointer value and it requires a callback
      86             :   /// to look up its register class.
      87             :   bool isLookupPtrRegClass() const {
      88             :     return Flags & (1 << MCOI::LookupPtrRegClass);
      89             :   }
      90             : 
      91             :   /// Set if this is one of the operands that made up of the predicate
      92             :   /// operand that controls an isPredicable() instruction.
      93             :   bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
      94             : 
      95             :   /// Set if this operand is a optional def.
      96             :   bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
      97             : 
      98             :   bool isGenericType() const {
      99      141176 :     return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
     100             :            OperandType <= MCOI::OPERAND_LAST_GENERIC;
     101             :   }
     102             : 
     103             :   unsigned getGenericTypeIndex() const {
     104             :     assert(isGenericType() && "non-generic types don't have an index");
     105       48011 :     return OperandType - MCOI::OPERAND_FIRST_GENERIC;
     106             :   }
     107             : };
     108             : 
     109             : //===----------------------------------------------------------------------===//
     110             : // Machine Instruction Flags and Description
     111             : //===----------------------------------------------------------------------===//
     112             : 
     113             : namespace MCID {
     114             : /// These should be considered private to the implementation of the
     115             : /// MCInstrDesc class.  Clients should use the predicate methods on MCInstrDesc,
     116             : /// not use these directly.  These all correspond to bitfields in the
     117             : /// MCInstrDesc::Flags field.
     118             : enum Flag {
     119             :   Variadic = 0,
     120             :   HasOptionalDef,
     121             :   Pseudo,
     122             :   Return,
     123             :   Call,
     124             :   Barrier,
     125             :   Terminator,
     126             :   Branch,
     127             :   IndirectBranch,
     128             :   Compare,
     129             :   MoveImm,
     130             :   Bitcast,
     131             :   Select,
     132             :   DelaySlot,
     133             :   FoldableAsLoad,
     134             :   MayLoad,
     135             :   MayStore,
     136             :   Predicable,
     137             :   NotDuplicable,
     138             :   UnmodeledSideEffects,
     139             :   Commutable,
     140             :   ConvertibleTo3Addr,
     141             :   UsesCustomInserter,
     142             :   HasPostISelHook,
     143             :   Rematerializable,
     144             :   CheapAsAMove,
     145             :   ExtraSrcRegAllocReq,
     146             :   ExtraDefRegAllocReq,
     147             :   RegSequence,
     148             :   ExtractSubreg,
     149             :   InsertSubreg,
     150             :   Convergent,
     151             :   Add
     152             : };
     153             : }
     154             : 
     155             : /// Describe properties that are true of each instruction in the target
     156             : /// description file.  This captures information about side effects, register
     157             : /// use and many other things.  There is one instance of this struct for each
     158             : /// target instruction class, and the MachineInstr class points to this struct
     159             : /// directly to describe itself.
     160             : class MCInstrDesc {
     161             : public:
     162             :   unsigned short Opcode;         // The opcode number
     163             :   unsigned short NumOperands;    // Num of args (may be more if variable_ops)
     164             :   unsigned char NumDefs;         // Num of args that are definitions
     165             :   unsigned char Size;            // Number of bytes in encoding.
     166             :   unsigned short SchedClass;     // enum identifying instr sched class
     167             :   uint64_t Flags;                // Flags identifying machine instr class
     168             :   uint64_t TSFlags;              // Target Specific Flag values
     169             :   const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
     170             :   const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
     171             :   const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
     172             :   // Subtarget feature that this is deprecated on, if any
     173             :   // -1 implies this is not deprecated by any single feature. It may still be
     174             :   // deprecated due to a "complex" reason, below.
     175             :   int64_t DeprecatedFeature;
     176             : 
     177             :   // A complex method to determine if a certain instruction is deprecated or
     178             :   // not, and return the reason for deprecation.
     179             :   bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
     180             :                                  std::string &);
     181             : 
     182             :   /// Returns the value of the specific constraint if
     183             :   /// it is set. Returns -1 if it is not set.
     184             :   int getOperandConstraint(unsigned OpNum,
     185             :                            MCOI::OperandConstraint Constraint) const {
     186   182574270 :     if (OpNum < NumOperands &&
     187    91034868 :         (OpInfo[OpNum].Constraints & (1 << Constraint))) {
     188             :       unsigned Pos = 16 + Constraint * 4;
     189     1619784 :       return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
     190             :     }
     191             :     return -1;
     192             :   }
     193             : 
     194             :   /// Returns true if a certain instruction is deprecated and if so
     195             :   /// returns the reason in \p Info.
     196             :   bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
     197             :                          std::string &Info) const;
     198             : 
     199             :   /// Return the opcode number for this descriptor.
     200    32528416 :   unsigned getOpcode() const { return Opcode; }
     201             : 
     202             :   /// Return the number of declared MachineOperands for this
     203             :   /// MachineInstruction.  Note that variadic (isVariadic() returns true)
     204             :   /// instructions may have additional operands at the end of the list, and note
     205             :   /// that the machine instruction may include implicit register def/uses as
     206             :   /// well.
     207   269659554 :   unsigned getNumOperands() const { return NumOperands; }
     208             : 
     209             :   using const_opInfo_iterator = const MCOperandInfo *;
     210             : 
     211             :   const_opInfo_iterator opInfo_begin() const { return OpInfo; }
     212           2 :   const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
     213             : 
     214             :   iterator_range<const_opInfo_iterator> operands() const {
     215           2 :     return make_range(opInfo_begin(), opInfo_end());
     216             :   }
     217             : 
     218             :   /// Return the number of MachineOperands that are register
     219             :   /// definitions.  Register definitions always occur at the start of the
     220             :   /// machine operand list.  This is the number of "outs" in the .td file,
     221             :   /// and does not include implicit defs.
     222   114759101 :   unsigned getNumDefs() const { return NumDefs; }
     223             : 
     224             :   /// Return flags of this instruction.
     225             :   uint64_t getFlags() const { return Flags; }
     226             : 
     227             :   /// Return true if this instruction can have a variable number of
     228             :   /// operands.  In this case, the variable operands will be after the normal
     229             :   /// operands but before the implicit definitions and uses (if any are
     230             :   /// present).
     231    27095563 :   bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
     232             : 
     233             :   /// Set if this instruction has an optional definition, e.g.
     234             :   /// ARM instructions which can set condition code if 's' bit is set.
     235      731855 :   bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
     236             : 
     237             :   /// Return true if this is a pseudo instruction that doesn't
     238             :   /// correspond to a real machine instruction.
     239        3940 :   bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
     240             : 
     241             :   /// Return true if the instruction is a return.
     242      282578 :   bool isReturn() const { return Flags & (1ULL << MCID::Return); }
     243             : 
     244             :   /// Return true if the instruction is an add instruction.
     245        1582 :   bool isAdd() const { return Flags & (1ULL << MCID::Add); }
     246             : 
     247             :   ///  Return true if the instruction is a call.
     248     8685691 :   bool isCall() const { return Flags & (1ULL << MCID::Call); }
     249             : 
     250             :   /// Returns true if the specified instruction stops control flow
     251             :   /// from executing the instruction immediately following it.  Examples include
     252             :   /// unconditional branches and return instructions.
     253      661898 :   bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
     254             : 
     255             :   /// Returns true if this instruction part of the terminator for
     256             :   /// a basic block.  Typically this is things like return and branch
     257             :   /// instructions.
     258             :   ///
     259             :   /// Various passes use this to insert code into the bottom of a basic block,
     260             :   /// but before control flow occurs.
     261      123710 :   bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
     262             : 
     263             :   /// Returns true if this is a conditional, unconditional, or
     264             :   /// indirect branch.  Predicates below can be used to discriminate between
     265             :   /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
     266             :   /// get more information.
     267      845105 :   bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
     268             : 
     269             :   /// Return true if this is an indirect branch, such as a
     270             :   /// branch through a register.
     271      662807 :   bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
     272             : 
     273             :   /// Return true if this is a branch which may fall
     274             :   /// through to the next instruction or may transfer control flow to some other
     275             :   /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
     276             :   /// information about this branch.
     277             :   bool isConditionalBranch() const {
     278      985265 :     return isBranch() & !isBarrier() & !isIndirectBranch();
     279             :   }
     280             : 
     281             :   /// Return true if this is a branch which always
     282             :   /// transfers control flow to some other block.  The
     283             :   /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
     284             :   /// about this branch.
     285             :   bool isUnconditionalBranch() const {
     286      666982 :     return isBranch() & isBarrier() & !isIndirectBranch();
     287             :   }
     288             : 
     289             :   /// Return true if this is a branch or an instruction which directly
     290             :   /// writes to the program counter. Considered 'may' affect rather than
     291             :   /// 'does' affect as things like predication are not taken into account.
     292             :   bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
     293             : 
     294             :   /// Return true if this instruction has a predicate operand
     295             :   /// that controls execution. It may be set to 'always', or may be set to other
     296             :   /// values. There are various methods in TargetInstrInfo that can be used to
     297             :   /// control and modify the predicate in this instruction.
     298     1170658 :   bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
     299             : 
     300             :   /// Return true if this instruction is a comparison.
     301             :   bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
     302             : 
     303             :   /// Return true if this instruction is a move immediate
     304             :   /// (including conditional moves) instruction.
     305             :   bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
     306             : 
     307             :   /// Return true if this instruction is a bitcast instruction.
     308             :   bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
     309             : 
     310             :   /// Return true if this is a select instruction.
     311             :   bool isSelect() const { return Flags & (1ULL << MCID::Select); }
     312             : 
     313             :   /// Return true if this instruction cannot be safely
     314             :   /// duplicated.  For example, if the instruction has a unique labels attached
     315             :   /// to it, duplicating it would cause multiple definition errors.
     316             :   bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
     317             : 
     318             :   /// Returns true if the specified instruction has a delay slot which
     319             :   /// must be filled by the code generator.
     320       35839 :   bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
     321             : 
     322             :   /// Return true for instructions that can be folded as memory operands
     323             :   /// in other instructions. The most common use for this is instructions that
     324             :   /// are simple loads from memory that don't modify the loaded value in any
     325             :   /// way, but it can also be used for instructions that can be expressed as
     326             :   /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
     327             :   /// folded when it is beneficial.  This should only be set on instructions
     328             :   /// that return a value in their only virtual register definition.
     329             :   bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
     330             : 
     331             :   /// Return true if this instruction behaves
     332             :   /// the same way as the generic REG_SEQUENCE instructions.
     333             :   /// E.g., on ARM,
     334             :   /// dX VMOVDRR rY, rZ
     335             :   /// is equivalent to
     336             :   /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
     337             :   ///
     338             :   /// Note that for the optimizers to be able to take advantage of
     339             :   /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
     340             :   /// override accordingly.
     341             :   bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
     342             : 
     343             :   /// Return true if this instruction behaves
     344             :   /// the same way as the generic EXTRACT_SUBREG instructions.
     345             :   /// E.g., on ARM,
     346             :   /// rX, rY VMOVRRD dZ
     347             :   /// is equivalent to two EXTRACT_SUBREG:
     348             :   /// rX = EXTRACT_SUBREG dZ, ssub_0
     349             :   /// rY = EXTRACT_SUBREG dZ, ssub_1
     350             :   ///
     351             :   /// Note that for the optimizers to be able to take advantage of
     352             :   /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
     353             :   /// override accordingly.
     354             :   bool isExtractSubregLike() const {
     355             :     return Flags & (1ULL << MCID::ExtractSubreg);
     356             :   }
     357             : 
     358             :   /// Return true if this instruction behaves
     359             :   /// the same way as the generic INSERT_SUBREG instructions.
     360             :   /// E.g., on ARM,
     361             :   /// dX = VSETLNi32 dY, rZ, Imm
     362             :   /// is equivalent to a INSERT_SUBREG:
     363             :   /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
     364             :   ///
     365             :   /// Note that for the optimizers to be able to take advantage of
     366             :   /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
     367             :   /// override accordingly.
     368             :   bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
     369             : 
     370             : 
     371             :   /// Return true if this instruction is convergent.
     372             :   ///
     373             :   /// Convergent instructions may not be made control-dependent on any
     374             :   /// additional values.
     375             :   bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
     376             : 
     377             :   //===--------------------------------------------------------------------===//
     378             :   // Side Effect Analysis
     379             :   //===--------------------------------------------------------------------===//
     380             : 
     381             :   /// Return true if this instruction could possibly read memory.
     382             :   /// Instructions with this flag set are not necessarily simple load
     383             :   /// instructions, they may load a value and modify it, for example.
     384     5065876 :   bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
     385             : 
     386             :   /// Return true if this instruction could possibly modify memory.
     387             :   /// Instructions with this flag set are not necessarily simple store
     388             :   /// instructions, they may store a modified value based on their operands, or
     389             :   /// may not actually modify anything, for example.
     390     1179451 :   bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
     391             : 
     392             :   /// Return true if this instruction has side
     393             :   /// effects that are not modeled by other flags.  This does not return true
     394             :   /// for instructions whose effects are captured by:
     395             :   ///
     396             :   ///  1. Their operand list and implicit definition/use list.  Register use/def
     397             :   ///     info is explicit for instructions.
     398             :   ///  2. Memory accesses.  Use mayLoad/mayStore.
     399             :   ///  3. Calling, branching, returning: use isCall/isReturn/isBranch.
     400             :   ///
     401             :   /// Examples of side effects would be modifying 'invisible' machine state like
     402             :   /// a control register, flushing a cache, modifying a register invisible to
     403             :   /// LLVM, etc.
     404             :   bool hasUnmodeledSideEffects() const {
     405       42009 :     return Flags & (1ULL << MCID::UnmodeledSideEffects);
     406             :   }
     407             : 
     408             :   //===--------------------------------------------------------------------===//
     409             :   // Flags that indicate whether an instruction can be modified by a method.
     410             :   //===--------------------------------------------------------------------===//
     411             : 
     412             :   /// Return true if this may be a 2- or 3-address instruction (of the
     413             :   /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
     414             :   /// exchanged.  If this flag is set, then the
     415             :   /// TargetInstrInfo::commuteInstruction method may be used to hack on the
     416             :   /// instruction.
     417             :   ///
     418             :   /// Note that this flag may be set on instructions that are only commutable
     419             :   /// sometimes.  In these cases, the call to commuteInstruction will fail.
     420             :   /// Also note that some instructions require non-trivial modification to
     421             :   /// commute them.
     422     3510119 :   bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
     423             : 
     424             :   /// Return true if this is a 2-address instruction which can be changed
     425             :   /// into a 3-address instruction if needed.  Doing this transformation can be
     426             :   /// profitable in the register allocator, because it means that the
     427             :   /// instruction can use a 2-address form if possible, but degrade into a less
     428             :   /// efficient form if the source and dest register cannot be assigned to the
     429             :   /// same register.  For example, this allows the x86 backend to turn a "shl
     430             :   /// reg, 3" instruction into an LEA instruction, which is the same speed as
     431             :   /// the shift but has bigger code size.
     432             :   ///
     433             :   /// If this returns true, then the target must implement the
     434             :   /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
     435             :   /// is allowed to fail if the transformation isn't valid for this specific
     436             :   /// instruction (e.g. shl reg, 4 on x86).
     437             :   ///
     438             :   bool isConvertibleTo3Addr() const {
     439             :     return Flags & (1ULL << MCID::ConvertibleTo3Addr);
     440             :   }
     441             : 
     442             :   /// Return true if this instruction requires custom insertion support
     443             :   /// when the DAG scheduler is inserting it into a machine basic block.  If
     444             :   /// this is true for the instruction, it basically means that it is a pseudo
     445             :   /// instruction used at SelectionDAG time that is expanded out into magic code
     446             :   /// by the target when MachineInstrs are formed.
     447             :   ///
     448             :   /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
     449             :   /// is used to insert this into the MachineBasicBlock.
     450             :   bool usesCustomInsertionHook() const {
     451             :     return Flags & (1ULL << MCID::UsesCustomInserter);
     452             :   }
     453             : 
     454             :   /// Return true if this instruction requires *adjustment* after
     455             :   /// instruction selection by calling a target hook. For example, this can be
     456             :   /// used to fill in ARM 's' optional operand depending on whether the
     457             :   /// conditional flag register is used.
     458     2791099 :   bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
     459             : 
     460             :   /// Returns true if this instruction is a candidate for remat. This
     461             :   /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
     462             :   ///
     463             :   /// If this flag is set, the isReallyTriviallyReMaterializable()
     464             :   /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
     465             :   /// the instruction is really rematable.
     466             :   bool isRematerializable() const {
     467      833074 :     return Flags & (1ULL << MCID::Rematerializable);
     468             :   }
     469             : 
     470             :   /// Returns true if this instruction has the same cost (or less) than a
     471             :   /// move instruction. This is useful during certain types of optimizations
     472             :   /// (e.g., remat during two-address conversion or machine licm) where we would
     473             :   /// like to remat or hoist the instruction, but not if it costs more than
     474             :   /// moving the instruction into the appropriate register. Note, we are not
     475             :   /// marking copies from and to the same register class with this flag.
     476             :   ///
     477             :   /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
     478             :   /// for different subtargets.
     479             :   bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
     480             : 
     481             :   /// Returns true if this instruction source operands have special
     482             :   /// register allocation requirements that are not captured by the operand
     483             :   /// register classes. e.g. ARM::STRD's two source registers must be an even /
     484             :   /// odd pair, ARM::STM registers have to be in ascending order.  Post-register
     485             :   /// allocation passes should not attempt to change allocations for sources of
     486             :   /// instructions with this flag.
     487             :   bool hasExtraSrcRegAllocReq() const {
     488             :     return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
     489             :   }
     490             : 
     491             :   /// Returns true if this instruction def operands have special register
     492             :   /// allocation requirements that are not captured by the operand register
     493             :   /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
     494             :   /// ARM::LDM registers have to be in ascending order.  Post-register
     495             :   /// allocation passes should not attempt to change allocations for definitions
     496             :   /// of instructions with this flag.
     497             :   bool hasExtraDefRegAllocReq() const {
     498             :     return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
     499             :   }
     500             : 
     501             :   /// Return a list of registers that are potentially read by any
     502             :   /// instance of this machine instruction.  For example, on X86, the "adc"
     503             :   /// instruction adds two register operands and adds the carry bit in from the
     504             :   /// flags register.  In this case, the instruction is marked as implicitly
     505             :   /// reading the flags.  Likewise, the variable shift instruction on X86 is
     506             :   /// marked as implicitly reading the 'CL' register, which it always does.
     507             :   ///
     508             :   /// This method returns null if the instruction has no implicit uses.
     509             :   const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
     510             : 
     511             :   /// Return the number of implicit uses this instruction has.
     512             :   unsigned getNumImplicitUses() const {
     513     8350309 :     if (!ImplicitUses)
     514             :       return 0;
     515             :     unsigned i = 0;
     516     4600001 :     for (; ImplicitUses[i]; ++i) /*empty*/
     517             :       ;
     518             :     return i;
     519             :   }
     520             : 
     521             :   /// Return a list of registers that are potentially written by any
     522             :   /// instance of this machine instruction.  For example, on X86, many
     523             :   /// instructions implicitly set the flags register.  In this case, they are
     524             :   /// marked as setting the FLAGS.  Likewise, many instructions always deposit
     525             :   /// their result in a physical register.  For example, the X86 divide
     526             :   /// instruction always deposits the quotient and remainder in the EAX/EDX
     527             :   /// registers.  For that instruction, this will return a list containing the
     528             :   /// EAX/EDX/EFLAGS registers.
     529             :   ///
     530             :   /// This method returns null if the instruction has no implicit defs.
     531             :   const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
     532             : 
     533             :   /// Return the number of implicit defs this instruct has.
     534             :   unsigned getNumImplicitDefs() const {
     535     8071197 :     if (!ImplicitDefs)
     536             :       return 0;
     537             :     unsigned i = 0;
     538     3546348 :     for (; ImplicitDefs[i]; ++i) /*empty*/
     539             :       ;
     540             :     return i;
     541             :   }
     542             : 
     543             :   /// Return true if this instruction implicitly
     544             :   /// uses the specified physical register.
     545             :   bool hasImplicitUseOfPhysReg(unsigned Reg) const {
     546         281 :     if (const MCPhysReg *ImpUses = ImplicitUses)
     547           0 :       for (; *ImpUses; ++ImpUses)
     548           0 :         if (*ImpUses == Reg)
     549             :           return true;
     550             :     return false;
     551             :   }
     552             : 
     553             :   /// Return true if this instruction implicitly
     554             :   /// defines the specified physical register.
     555             :   bool hasImplicitDefOfPhysReg(unsigned Reg,
     556             :                                const MCRegisterInfo *MRI = nullptr) const;
     557             : 
     558             :   /// Return the scheduling class for this instruction.  The
     559             :   /// scheduling class is an index into the InstrItineraryData table.  This
     560             :   /// returns zero if there is no known scheduling information for the
     561             :   /// instruction.
     562    15439330 :   unsigned getSchedClass() const { return SchedClass; }
     563             : 
     564             :   /// Return the number of bytes in the encoding of this instruction,
     565             :   /// or zero if the encoding size cannot be known from the opcode.
     566     2404513 :   unsigned getSize() const { return Size; }
     567             : 
     568             :   /// Find the index of the first operand in the
     569             :   /// operand list that is used to represent the predicate. It returns -1 if
     570             :   /// none is found.
     571             :   int findFirstPredOperandIdx() const {
     572             :     if (isPredicable()) {
     573       75452 :       for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
     574       37726 :         if (OpInfo[i].isPredicate())
     575        9630 :           return i;
     576             :     }
     577             :     return -1;
     578             :   }
     579             : 
     580             :   /// Return true if this instruction defines the specified physical
     581             :   /// register, either explicitly or implicitly.
     582             :   bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
     583             :                        const MCRegisterInfo &RI) const;
     584             : };
     585             : 
     586             : } // end namespace llvm
     587             : 
     588             : #endif

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