LCOV - code coverage report
Current view: top level - include/llvm/MC/MCParser - MCTargetAsmParser.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 37 41 90.2 %
Date: 2017-09-14 15:23:50 Functions: 11 15 73.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/MC/MCTargetAsmParser.h - Target Assembly Parser -----*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : 
      10             : #ifndef LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
      11             : #define LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
      12             : 
      13             : #include "llvm/ADT/StringRef.h"
      14             : #include "llvm/MC/MCExpr.h"
      15             : #include "llvm/MC/MCParser/MCAsmLexer.h"
      16             : #include "llvm/MC/MCParser/MCAsmParserExtension.h"
      17             : #include "llvm/MC/MCTargetOptions.h"
      18             : #include "llvm/Support/SMLoc.h"
      19             : #include <cstdint>
      20             : #include <memory>
      21             : 
      22             : namespace llvm {
      23             : 
      24             : class MCInst;
      25             : class MCParsedAsmOperand;
      26             : class MCStreamer;
      27             : class MCSubtargetInfo;
      28             : template <typename T> class SmallVectorImpl;
      29             : 
      30             : using OperandVector = SmallVectorImpl<std::unique_ptr<MCParsedAsmOperand>>;
      31             : 
      32             : enum AsmRewriteKind {
      33             :   AOK_Align,          // Rewrite align as .align.
      34             :   AOK_EVEN,           // Rewrite even as .even.
      35             :   AOK_Emit,           // Rewrite _emit as .byte.
      36             :   AOK_Input,          // Rewrite in terms of $N.
      37             :   AOK_Output,         // Rewrite in terms of $N.
      38             :   AOK_SizeDirective,  // Add a sizing directive (e.g., dword ptr).
      39             :   AOK_Label,          // Rewrite local labels.
      40             :   AOK_EndOfStatement, // Add EndOfStatement (e.g., "\n\t").
      41             :   AOK_Skip,           // Skip emission (e.g., offset/type operators).
      42             :   AOK_IntelExpr       // SizeDirective SymDisp [BaseReg + IndexReg * Scale + ImmDisp]
      43             : };
      44             : 
      45             : const char AsmRewritePrecedence [] = {
      46             :   2, // AOK_Align
      47             :   2, // AOK_EVEN
      48             :   2, // AOK_Emit
      49             :   3, // AOK_Input
      50             :   3, // AOK_Output
      51             :   5, // AOK_SizeDirective
      52             :   1, // AOK_Label
      53             :   5, // AOK_EndOfStatement
      54             :   2, // AOK_Skip
      55             :   2  // AOK_IntelExpr
      56             : };
      57             : 
      58             : // Represnt the various parts which makes up an intel expression,
      59             : // used for emitting compound intel expressions
      60             : struct IntelExpr {
      61             :   bool NeedBracs;
      62             :   int64_t Imm;
      63             :   StringRef BaseReg;
      64             :   StringRef IndexReg;
      65             :   unsigned Scale;
      66             : 
      67         679 :   IntelExpr(bool needBracs = false) : NeedBracs(needBracs), Imm(0),
      68             :     BaseReg(StringRef()), IndexReg(StringRef()),
      69         679 :     Scale(1) {}
      70             :   // Compund immediate expression
      71         348 :   IntelExpr(int64_t imm, bool needBracs) : IntelExpr(needBracs) {
      72         174 :     Imm = imm;
      73             :   }
      74             :   // [Reg + ImmediateExpression]
      75             :   // We don't bother to emit an immediate expression evaluated to zero
      76             :   IntelExpr(StringRef reg, int64_t imm = 0, unsigned scale = 0,
      77             :     bool needBracs = true) :
      78         348 :     IntelExpr(imm, needBracs) {
      79         174 :     IndexReg = reg;
      80         174 :     if (scale)
      81         174 :       Scale = scale;
      82             :   }
      83             :   // [BaseReg + IndexReg * ScaleExpression + ImmediateExpression]
      84             :   IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale = 0,
      85             :     int64_t imm = 0, bool needBracs = true) :
      86         348 :     IntelExpr(indexReg, imm, scale, needBracs) {
      87         174 :     BaseReg = baseReg;
      88             :   }
      89             :   bool hasBaseReg() const {
      90         722 :     return BaseReg.size();
      91             :   }
      92             :   bool hasIndexReg() const {
      93         654 :     return IndexReg.size();
      94             :   }
      95             :   bool hasRegs() const {
      96         341 :     return hasBaseReg() || hasIndexReg();
      97             :   }
      98             :   bool isValid() const {
      99             :     return (Scale == 1) ||
     100             :            (hasIndexReg() && (Scale == 2 || Scale == 4 || Scale == 8));
     101             :   }
     102             : };
     103             : 
     104             : struct AsmRewrite {
     105             :   AsmRewriteKind Kind;
     106             :   SMLoc Loc;
     107             :   unsigned Len;
     108             :   int64_t Val;
     109             :   StringRef Label;
     110             :   IntelExpr IntelExp;
     111             : 
     112             : public:
     113             :   AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len = 0, int64_t val = 0)
     114        1472 :     : Kind(kind), Loc(loc), Len(len), Val(val) {}
     115             :   AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len, StringRef label)
     116          86 :     : AsmRewrite(kind, loc, len) { Label = label; }
     117             :   AsmRewrite(SMLoc loc, unsigned len, IntelExpr exp)
     118         348 :     : AsmRewrite(AOK_IntelExpr, loc, len) { IntelExp = exp; }
     119             : };
     120             : 
     121             : struct ParseInstructionInfo {
     122             :   SmallVectorImpl<AsmRewrite> *AsmRewrites = nullptr;
     123             : 
     124             :   ParseInstructionInfo() = default;
     125             :   ParseInstructionInfo(SmallVectorImpl<AsmRewrite> *rewrites)
     126      264194 :     : AsmRewrites(rewrites) {}
     127             : };
     128             : 
     129             : enum OperandMatchResultTy {
     130             :   MatchOperand_Success,  // operand matched successfully
     131             :   MatchOperand_NoMatch,  // operand did not match
     132             :   MatchOperand_ParseFail // operand matched but had errors
     133             : };
     134             : 
     135             : /// MCTargetAsmParser - Generic interface to target specific assembly parsers.
     136        7411 : class MCTargetAsmParser : public MCAsmParserExtension {
     137             : public:
     138             :   enum MatchResultTy {
     139             :     Match_InvalidOperand,
     140             :     Match_MissingFeature,
     141             :     Match_MnemonicFail,
     142             :     Match_Success,
     143             :     FIRST_TARGET_MATCH_RESULT_TY
     144             :   };
     145             : 
     146             : protected: // Can only create subclasses.
     147             :   MCTargetAsmParser(MCTargetOptions const &, const MCSubtargetInfo &STI);
     148             : 
     149             :   /// Create a copy of STI and return a non-const reference to it.
     150             :   MCSubtargetInfo &copySTI();
     151             : 
     152             :   /// AvailableFeatures - The current set of available features.
     153             :   uint64_t AvailableFeatures = 0;
     154             : 
     155             :   /// ParsingInlineAsm - Are we parsing ms-style inline assembly?
     156             :   bool ParsingInlineAsm = false;
     157             : 
     158             :   /// SemaCallback - The Sema callback implementation.  Must be set when parsing
     159             :   /// ms-style inline assembly.
     160             :   MCAsmParserSemaCallback *SemaCallback;
     161             : 
     162             :   /// Set of options which affects instrumentation of inline assembly.
     163             :   MCTargetOptions MCOptions;
     164             : 
     165             :   /// Current STI.
     166             :   const MCSubtargetInfo *STI;
     167             : 
     168             : public:
     169             :   MCTargetAsmParser(const MCTargetAsmParser &) = delete;
     170             :   MCTargetAsmParser &operator=(const MCTargetAsmParser &) = delete;
     171             : 
     172             :   ~MCTargetAsmParser() override;
     173             : 
     174             :   const MCSubtargetInfo &getSTI() const;
     175             : 
     176             :   uint64_t getAvailableFeatures() const { return AvailableFeatures; }
     177      151696 :   void setAvailableFeatures(uint64_t Value) { AvailableFeatures = Value; }
     178             : 
     179             :   bool isParsingInlineAsm () { return ParsingInlineAsm; }
     180         215 :   void setParsingInlineAsm (bool Value) { ParsingInlineAsm = Value; }
     181             : 
     182       31973 :   MCTargetOptions getTargetOptions() const { return MCOptions; }
     183             : 
     184             :   void setSemaCallback(MCAsmParserSemaCallback *Callback) {
     185         215 :     SemaCallback = Callback;
     186             :   }
     187             : 
     188             :   virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
     189             :                              SMLoc &EndLoc) = 0;
     190             : 
     191             :   /// Sets frame register corresponding to the current MachineFunction.
     192         727 :   virtual void SetFrameRegister(unsigned RegNo) {}
     193             : 
     194             :   /// ParseInstruction - Parse one assembly instruction.
     195             :   ///
     196             :   /// The parser is positioned following the instruction name. The target
     197             :   /// specific instruction parser should parse the entire instruction and
     198             :   /// construct the appropriate MCInst, or emit an error. On success, the entire
     199             :   /// line should be parsed up to and including the end-of-statement token. On
     200             :   /// failure, the parser is not required to read to the end of the line.
     201             :   //
     202             :   /// \param Name - The instruction name.
     203             :   /// \param NameLoc - The source location of the name.
     204             :   /// \param Operands [out] - The list of parsed operands, this returns
     205             :   ///        ownership of them to the caller.
     206             :   /// \return True on failure.
     207             :   virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
     208             :                                 SMLoc NameLoc, OperandVector &Operands) = 0;
     209      260020 :   virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
     210             :                                 AsmToken Token, OperandVector &Operands) {
     211      260020 :     return ParseInstruction(Info, Name, Token.getLoc(), Operands);
     212             :   }
     213             : 
     214             :   /// ParseDirective - Parse a target specific assembler directive
     215             :   ///
     216             :   /// The parser is positioned following the directive name.  The target
     217             :   /// specific directive parser should parse the entire directive doing or
     218             :   /// recording any target specific work, or return true and do nothing if the
     219             :   /// directive is not target specific. If the directive is specific for
     220             :   /// the target, the entire line is parsed up to and including the
     221             :   /// end-of-statement token and false is returned.
     222             :   ///
     223             :   /// \param DirectiveID - the identifier token of the directive.
     224             :   virtual bool ParseDirective(AsmToken DirectiveID) = 0;
     225             : 
     226             :   /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
     227             :   /// instruction as an actual MCInst and emit it to the specified MCStreamer.
     228             :   /// This returns false on success and returns true on failure to match.
     229             :   ///
     230             :   /// On failure, the target parser is responsible for emitting a diagnostic
     231             :   /// explaining the match failure.
     232             :   virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     233             :                                        OperandVector &Operands, MCStreamer &Out,
     234             :                                        uint64_t &ErrorInfo,
     235             :                                        bool MatchingInlineAsm) = 0;
     236             : 
     237             :   /// Allows targets to let registers opt out of clobber lists.
     238           0 :   virtual bool OmitRegisterFromClobberLists(unsigned RegNo) { return false; }
     239             : 
     240             :   /// Allow a target to add special case operand matching for things that
     241             :   /// tblgen doesn't/can't handle effectively. For example, literal
     242             :   /// immediates on ARM. TableGen expects a token operand, but the parser
     243             :   /// will recognize them as immediates.
     244      467627 :   virtual unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
     245             :                                               unsigned Kind) {
     246      467627 :     return Match_InvalidOperand;
     247             :   }
     248             : 
     249             :   /// Validate the instruction match against any complex target predicates
     250             :   /// before rendering any operands to it.
     251             :   virtual unsigned
     252      222269 :   checkEarlyTargetMatchPredicate(MCInst &Inst, const OperandVector &Operands) {
     253      222269 :     return Match_Success;
     254             :   }
     255             : 
     256             :   /// checkTargetMatchPredicate - Validate the instruction match against
     257             :   /// any complex target predicates not expressible via match classes.
     258       87901 :   virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
     259       87901 :     return Match_Success;
     260             :   }
     261             : 
     262             :   virtual void convertToMapAndConstraints(unsigned Kind,
     263             :                                           const OperandVector &Operands) = 0;
     264             : 
     265             :   // Return whether this parser uses assignment statements with equals tokens
     266         373 :   virtual bool equalIsAsmAssignment() { return true; };
     267             :   // Return whether this start of statement identifier is a label
     268        6670 :   virtual bool isLabel(AsmToken &Token) { return true; };
     269             :   // Return whether this parser accept star as start of statement
     270           0 :   virtual bool starIsStartOfStatement() { return false; };
     271             : 
     272          26 :   virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
     273             :                                             MCSymbolRefExpr::VariantKind,
     274             :                                             MCContext &Ctx) {
     275          26 :     return nullptr;
     276             :   }
     277             : 
     278        5387 :   virtual void onLabelParsed(MCSymbol *Symbol) {}
     279             : 
     280             :   /// Ensure that all previously parsed instructions have been emitted to the
     281             :   /// output streamer, if the target does not emit them immediately.
     282      517982 :   virtual void flushPendingInstructions(MCStreamer &Out) {}
     283             : 
     284           0 :   virtual const MCExpr *createTargetUnaryExpr(const MCExpr *E,
     285             :                                               AsmToken::TokenKind OperatorToken,
     286             :                                               MCContext &Ctx) {
     287           0 :     return nullptr;
     288             :   }
     289             : };
     290             : 
     291             : } // end namespace llvm
     292             : 
     293             : #endif // LLVM_MC_MCPARSER_MCTARGETASMPARSER_H

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