LCOV - code coverage report
Current view: top level - include/llvm/MC - MCRegisterInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 104 104 100.0 %
Date: 2018-06-17 00:07:59 Functions: 6 6 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file describes an abstract interface used to get information about a
      11             : // target machines register file.  This information is used for a variety of
      12             : // purposed, especially register allocation.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #ifndef LLVM_MC_MCREGISTERINFO_H
      17             : #define LLVM_MC_MCREGISTERINFO_H
      18             : 
      19             : #include "llvm/ADT/DenseMap.h"
      20             : #include "llvm/ADT/iterator_range.h"
      21             : #include "llvm/MC/LaneBitmask.h"
      22             : #include <cassert>
      23             : #include <cstdint>
      24             : #include <utility>
      25             : 
      26             : namespace llvm {
      27             : 
      28             : /// An unsigned integer type large enough to represent all physical registers,
      29             : /// but not necessarily virtual registers.
      30             : using MCPhysReg = uint16_t;
      31             : 
      32             : /// MCRegisterClass - Base class of TargetRegisterClass.
      33             : class MCRegisterClass {
      34             : public:
      35             :   using iterator = const MCPhysReg*;
      36             :   using const_iterator = const MCPhysReg*;
      37             : 
      38             :   const iterator RegsBegin;
      39             :   const uint8_t *const RegSet;
      40             :   const uint32_t NameIdx;
      41             :   const uint16_t RegsSize;
      42             :   const uint16_t RegSetSize;
      43             :   const uint16_t ID;
      44             :   const uint16_t PhysRegSize;
      45             :   const int8_t CopyCost;
      46             :   const bool Allocatable;
      47             : 
      48             :   /// getID() - Return the register class ID number.
      49             :   ///
      50   141639560 :   unsigned getID() const { return ID; }
      51             : 
      52             :   /// begin/end - Return all of the registers in this class.
      53             :   ///
      54             :   iterator       begin() const { return RegsBegin; }
      55     6814094 :   iterator         end() const { return RegsBegin + RegsSize; }
      56             : 
      57             :   /// getNumRegs - Return the number of registers in this class.
      58             :   ///
      59     2576263 :   unsigned getNumRegs() const { return RegsSize; }
      60             : 
      61             :   /// getRegister - Return the specified register in the class.
      62             :   ///
      63             :   unsigned getRegister(unsigned i) const {
      64             :     assert(i < getNumRegs() && "Register number out of range!");
      65     1023465 :     return RegsBegin[i];
      66             :   }
      67             : 
      68             :   /// contains - Return true if the specified register is included in this
      69             :   /// register class.  This does not include virtual registers.
      70             :   bool contains(unsigned Reg) const {
      71   843504163 :     unsigned InByte = Reg % 8;
      72   843504163 :     unsigned Byte = Reg / 8;
      73   847602816 :     if (Byte >= RegSetSize)
      74             :       return false;
      75   739297173 :     return (RegSet[Byte] & (1 << InByte)) != 0;
      76             :   }
      77             : 
      78             :   /// contains - Return true if both registers are in this class.
      79      481454 :   bool contains(unsigned Reg1, unsigned Reg2) const {
      80     1117241 :     return contains(Reg1) && contains(Reg2);
      81             :   }
      82             : 
      83             :   /// Return the size of the physical register in bytes.
      84             :   unsigned getPhysRegSize() const { return PhysRegSize; }
      85             :   /// Temporary function to allow out-of-tree targets to switch.
      86             :   unsigned getSize() const { return getPhysRegSize(); }
      87             : 
      88             :   /// getCopyCost - Return the cost of copying a value between two registers in
      89             :   /// this class. A negative number means the register class is very expensive
      90             :   /// to copy e.g. status flag register classes.
      91      143069 :   int getCopyCost() const { return CopyCost; }
      92             : 
      93             :   /// isAllocatable - Return true if this register class may be used to create
      94             :   /// virtual registers.
      95             :   bool isAllocatable() const { return Allocatable; }
      96             : };
      97             : 
      98             : /// MCRegisterDesc - This record contains information about a particular
      99             : /// register.  The SubRegs field is a zero terminated array of registers that
     100             : /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
     101             : /// of AX. The SuperRegs field is a zero terminated array of registers that are
     102             : /// super-registers of the specific register, e.g. RAX, EAX, are
     103             : /// super-registers of AX.
     104             : ///
     105             : struct MCRegisterDesc {
     106             :   uint32_t Name;      // Printable name for the reg (for debugging)
     107             :   uint32_t SubRegs;   // Sub-register set, described above
     108             :   uint32_t SuperRegs; // Super-register set, described above
     109             : 
     110             :   // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
     111             :   // sub-register in SubRegs.
     112             :   uint32_t SubRegIndices;
     113             : 
     114             :   // RegUnits - Points to the list of register units. The low 4 bits holds the
     115             :   // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
     116             :   uint32_t RegUnits;
     117             : 
     118             :   /// Index into list with lane mask sequences. The sequence contains a lanemask
     119             :   /// for every register unit.
     120             :   uint16_t RegUnitLaneMasks;
     121             : };
     122             : 
     123             : /// MCRegisterInfo base class - We assume that the target defines a static
     124             : /// array of MCRegisterDesc objects that represent all of the machine
     125             : /// registers that the target has.  As such, we simply have to track a pointer
     126             : /// to this array so that we can turn register number into a register
     127             : /// descriptor.
     128             : ///
     129             : /// Note this class is designed to be a base class of TargetRegisterInfo, which
     130             : /// is the interface used by codegen. However, specific targets *should never*
     131             : /// specialize this class. MCRegisterInfo should only contain getters to access
     132             : /// TableGen generated physical register data. It must not be extended with
     133             : /// virtual methods.
     134             : ///
     135      204547 : class MCRegisterInfo {
     136             : public:
     137             :   using regclass_iterator = const MCRegisterClass *;
     138             : 
     139             :   /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
     140             :   /// performed with a binary search.
     141             :   struct DwarfLLVMRegPair {
     142             :     unsigned FromReg;
     143             :     unsigned ToReg;
     144             : 
     145             :     bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
     146             :   };
     147             : 
     148             :   /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
     149             :   /// index, -1 in any being invalid.
     150             :   struct SubRegCoveredBits {
     151             :     uint16_t Offset;
     152             :     uint16_t Size;
     153             :   };
     154             : 
     155             : private:
     156             :   const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
     157             :   unsigned NumRegs;                           // Number of entries in the array
     158             :   unsigned RAReg;                             // Return address register
     159             :   unsigned PCReg;                             // Program counter register
     160             :   const MCRegisterClass *Classes;             // Pointer to the regclass array
     161             :   unsigned NumClasses;                        // Number of entries in the array
     162             :   unsigned NumRegUnits;                       // Number of regunits.
     163             :   const MCPhysReg (*RegUnitRoots)[2];         // Pointer to regunit root table.
     164             :   const MCPhysReg *DiffLists;                 // Pointer to the difflists array
     165             :   const LaneBitmask *RegUnitMaskSequences;    // Pointer to lane mask sequences
     166             :                                               // for register units.
     167             :   const char *RegStrings;                     // Pointer to the string table.
     168             :   const char *RegClassStrings;                // Pointer to the class strings.
     169             :   const uint16_t *SubRegIndices;              // Pointer to the subreg lookup
     170             :                                               // array.
     171             :   const SubRegCoveredBits *SubRegIdxRanges;   // Pointer to the subreg covered
     172             :                                               // bit ranges array.
     173             :   unsigned NumSubRegIndices;                  // Number of subreg indices.
     174             :   const uint16_t *RegEncodingTable;           // Pointer to array of register
     175             :                                               // encodings.
     176             : 
     177             :   unsigned L2DwarfRegsSize;
     178             :   unsigned EHL2DwarfRegsSize;
     179             :   unsigned Dwarf2LRegsSize;
     180             :   unsigned EHDwarf2LRegsSize;
     181             :   const DwarfLLVMRegPair *L2DwarfRegs;        // LLVM to Dwarf regs mapping
     182             :   const DwarfLLVMRegPair *EHL2DwarfRegs;      // LLVM to Dwarf regs mapping EH
     183             :   const DwarfLLVMRegPair *Dwarf2LRegs;        // Dwarf to LLVM regs mapping
     184             :   const DwarfLLVMRegPair *EHDwarf2LRegs;      // Dwarf to LLVM regs mapping EH
     185             :   DenseMap<unsigned, int> L2SEHRegs;          // LLVM to SEH regs mapping
     186             :   DenseMap<unsigned, int> L2CVRegs;           // LLVM to CV regs mapping
     187             : 
     188             : public:
     189             :   /// DiffListIterator - Base iterator class that can traverse the
     190             :   /// differentially encoded register and regunit lists in DiffLists.
     191             :   /// Don't use this class directly, use one of the specialized sub-classes
     192             :   /// defined below.
     193             :   class DiffListIterator {
     194             :     uint16_t Val = 0;
     195             :     const MCPhysReg *List = nullptr;
     196             : 
     197             :   protected:
     198             :     /// Create an invalid iterator. Call init() to point to something useful.
     199   153566798 :     DiffListIterator() = default;
     200             : 
     201             :     /// init - Point the iterator to InitVal, decoding subsequent values from
     202             :     /// DiffList. The iterator will initially point to InitVal, sub-classes are
     203             :     /// responsible for skipping the seed value if it is not part of the list.
     204             :     void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
     205             :       Val = InitVal;
     206             :       List = DiffList;
     207             :     }
     208             : 
     209             :     /// advance - Move to the next list position, return the applied
     210             :     /// differential. This function does not detect the end of the list, that
     211             :     /// is the caller's responsibility (by checking for a 0 return value).
     212             :     unsigned advance() {
     213             :       assert(isValid() && "Cannot move off the end of the list.");
     214  1116122374 :       MCPhysReg D = *List++;
     215  1115918018 :       Val += D;
     216             :       return D;
     217             :     }
     218             : 
     219             :   public:
     220             :     /// isValid - returns true if this iterator is not yet at the end.
     221             :     bool isValid() const { return List; }
     222             : 
     223             :     /// Dereference the iterator to get the value at the current position.
     224   886861841 :     unsigned operator*() const { return Val; }
     225             : 
     226             :     /// Pre-increment to move to the next position.
     227             :     void operator++() {
     228             :       // The end of the list is encoded as a 0 differential.
     229   984571561 :       if (!advance())
     230   160497500 :         List = nullptr;
     231             :     }
     232             :   };
     233             : 
     234             :   // These iterators are allowed to sub-class DiffListIterator and access
     235             :   // internal list pointers.
     236             :   friend class MCSubRegIterator;
     237             :   friend class MCSubRegIndexIterator;
     238             :   friend class MCSuperRegIterator;
     239             :   friend class MCRegUnitIterator;
     240             :   friend class MCRegUnitMaskIterator;
     241             :   friend class MCRegUnitRootIterator;
     242             : 
     243             :   /// Initialize MCRegisterInfo, called by TableGen
     244             :   /// auto-generated routines. *DO NOT USE*.
     245             :   void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
     246             :                           unsigned PC,
     247             :                           const MCRegisterClass *C, unsigned NC,
     248             :                           const MCPhysReg (*RURoots)[2],
     249             :                           unsigned NRU,
     250             :                           const MCPhysReg *DL,
     251             :                           const LaneBitmask *RUMS,
     252             :                           const char *Strings,
     253             :                           const char *ClassStrings,
     254             :                           const uint16_t *SubIndices,
     255             :                           unsigned NumIndices,
     256             :                           const SubRegCoveredBits *SubIdxRanges,
     257             :                           const uint16_t *RET) {
     258       80998 :     Desc = D;
     259       80998 :     NumRegs = NR;
     260       80998 :     RAReg = RA;
     261       80998 :     PCReg = PC;
     262       80998 :     Classes = C;
     263       80998 :     DiffLists = DL;
     264       80998 :     RegUnitMaskSequences = RUMS;
     265       80998 :     RegStrings = Strings;
     266       80998 :     RegClassStrings = ClassStrings;
     267       80998 :     NumClasses = NC;
     268       80998 :     RegUnitRoots = RURoots;
     269       80998 :     NumRegUnits = NRU;
     270       80998 :     SubRegIndices = SubIndices;
     271       80998 :     NumSubRegIndices = NumIndices;
     272       80998 :     SubRegIdxRanges = SubIdxRanges;
     273       80998 :     RegEncodingTable = RET;
     274             : 
     275             :     // Initialize DWARF register mapping variables
     276       42611 :     EHL2DwarfRegs = nullptr;
     277       42611 :     EHL2DwarfRegsSize = 0;
     278       42611 :     L2DwarfRegs = nullptr;
     279       42611 :     L2DwarfRegsSize = 0;
     280       42611 :     EHDwarf2LRegs = nullptr;
     281       42611 :     EHDwarf2LRegsSize = 0;
     282       42611 :     Dwarf2LRegs = nullptr;
     283       42611 :     Dwarf2LRegsSize = 0;
     284             :   }
     285             : 
     286             :   /// Used to initialize LLVM register to Dwarf
     287             :   /// register number mapping. Called by TableGen auto-generated routines.
     288             :   /// *DO NOT USE*.
     289             :   void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
     290             :                               bool isEH) {
     291             :     if (isEH) {
     292       79317 :       EHL2DwarfRegs = Map;
     293       79317 :       EHL2DwarfRegsSize = Size;
     294             :     } else {
     295       79317 :       L2DwarfRegs = Map;
     296       79317 :       L2DwarfRegsSize = Size;
     297             :     }
     298             :   }
     299             : 
     300             :   /// Used to initialize Dwarf register to LLVM
     301             :   /// register number mapping. Called by TableGen auto-generated routines.
     302             :   /// *DO NOT USE*.
     303             :   void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
     304             :                               bool isEH) {
     305             :     if (isEH) {
     306       79317 :       EHDwarf2LRegs = Map;
     307       79317 :       EHDwarf2LRegsSize = Size;
     308             :     } else {
     309       79317 :       Dwarf2LRegs = Map;
     310       79317 :       Dwarf2LRegsSize = Size;
     311             :     }
     312             :   }
     313             : 
     314             :   /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
     315             :   /// number mapping. By default the SEH register number is just the same
     316             :   /// as the LLVM register number.
     317             :   /// FIXME: TableGen these numbers. Currently this requires target specific
     318             :   /// initialization code.
     319             :   void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
     320    18337280 :     L2SEHRegs[LLVMReg] = SEHReg;
     321             :   }
     322             : 
     323             :   void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) {
     324    13795190 :     L2CVRegs[LLVMReg] = CVReg;
     325             :   }
     326             : 
     327             :   /// This method should return the register where the return
     328             :   /// address can be found.
     329             :   unsigned getRARegister() const {
     330             :     return RAReg;
     331             :   }
     332             : 
     333             :   /// Return the register which is the program counter.
     334             :   unsigned getProgramCounter() const {
     335             :     return PCReg;
     336             :   }
     337             : 
     338             :   const MCRegisterDesc &operator[](unsigned RegNo) const {
     339             :     assert(RegNo < NumRegs &&
     340             :            "Attempting to access record for invalid register number!");
     341   447861428 :     return Desc[RegNo];
     342             :   }
     343             : 
     344             :   /// Provide a get method, equivalent to [], but more useful with a
     345             :   /// pointer to this object.
     346             :   const MCRegisterDesc &get(unsigned RegNo) const {
     347   367964866 :     return operator[](RegNo);
     348             :   }
     349             : 
     350             :   /// Returns the physical register number of sub-register "Index"
     351             :   /// for physical register RegNo. Return zero if the sub-register does not
     352             :   /// exist.
     353             :   unsigned getSubReg(unsigned Reg, unsigned Idx) const;
     354             : 
     355             :   /// Return a super-register of the specified register
     356             :   /// Reg so its sub-register of index SubIdx is Reg.
     357             :   unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
     358             :                                const MCRegisterClass *RC) const;
     359             : 
     360             :   /// For a given register pair, return the sub-register index
     361             :   /// if the second register is a sub-register of the first. Return zero
     362             :   /// otherwise.
     363             :   unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
     364             : 
     365             :   /// Get the size of the bit range covered by a sub-register index.
     366             :   /// If the index isn't continuous, return the sum of the sizes of its parts.
     367             :   /// If the index is used to access subregisters of different sizes, return -1.
     368             :   unsigned getSubRegIdxSize(unsigned Idx) const;
     369             : 
     370             :   /// Get the offset of the bit range covered by a sub-register index.
     371             :   /// If an Offset doesn't make sense (the index isn't continuous, or is used to
     372             :   /// access sub-registers at different offsets), return -1.
     373             :   unsigned getSubRegIdxOffset(unsigned Idx) const;
     374             : 
     375             :   /// Return the human-readable symbolic target-specific name for the
     376             :   /// specified physical register.
     377             :   const char *getName(unsigned RegNo) const {
     378   146309684 :     return RegStrings + get(RegNo).Name;
     379             :   }
     380             : 
     381             :   /// Return the number of registers this target has (useful for
     382             :   /// sizing arrays holding per register information)
     383             :   unsigned getNumRegs() const {
     384             :     return NumRegs;
     385             :   }
     386             : 
     387             :   /// Return the number of sub-register indices
     388             :   /// understood by the target. Index 0 is reserved for the no-op sub-register,
     389             :   /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
     390             :   unsigned getNumSubRegIndices() const {
     391             :     return NumSubRegIndices;
     392             :   }
     393             : 
     394             :   /// Return the number of (native) register units in the
     395             :   /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
     396             :   /// can be accessed through MCRegUnitIterator defined below.
     397             :   unsigned getNumRegUnits() const {
     398             :     return NumRegUnits;
     399             :   }
     400             : 
     401             :   /// Map a target register to an equivalent dwarf register
     402             :   /// number.  Returns -1 if there is no equivalent value.  The second
     403             :   /// parameter allows targets to use different numberings for EH info and
     404             :   /// debugging info.
     405             :   int getDwarfRegNum(unsigned RegNum, bool isEH) const;
     406             : 
     407             :   /// Map a dwarf register back to a target register.
     408             :   int getLLVMRegNum(unsigned RegNum, bool isEH) const;
     409             : 
     410             :   /// Map a DWARF EH register back to a target register (same as
     411             :   /// getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping,
     412             :   /// rather than asserting that there must be one.
     413             :   int getLLVMRegNumFromEH(unsigned RegNum) const;
     414             : 
     415             :   /// Map a target EH register number to an equivalent DWARF register
     416             :   /// number.
     417             :   int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
     418             : 
     419             :   /// Map a target register to an equivalent SEH register
     420             :   /// number.  Returns LLVM register number if there is no equivalent value.
     421             :   int getSEHRegNum(unsigned RegNum) const;
     422             : 
     423             :   /// Map a target register to an equivalent CodeView register
     424             :   /// number.
     425             :   int getCodeViewRegNum(unsigned RegNum) const;
     426             : 
     427             :   regclass_iterator regclass_begin() const { return Classes; }
     428             :   regclass_iterator regclass_end() const { return Classes+NumClasses; }
     429             :   iterator_range<regclass_iterator> regclasses() const {
     430             :     return make_range(regclass_begin(), regclass_end());
     431             :   }
     432             : 
     433             :   unsigned getNumRegClasses() const {
     434             :     return (unsigned)(regclass_end()-regclass_begin());
     435             :   }
     436             : 
     437             :   /// Returns the register class associated with the enumeration
     438             :   /// value.  See class MCOperandInfo.
     439             :   const MCRegisterClass& getRegClass(unsigned i) const {
     440             :     assert(i < getNumRegClasses() && "Register Class ID out of range");
     441      570167 :     return Classes[i];
     442             :   }
     443             : 
     444             :   const char *getRegClassName(const MCRegisterClass *Class) const {
     445      116303 :     return RegClassStrings + Class->NameIdx;
     446             :   }
     447             : 
     448             :    /// Returns the encoding for RegNo
     449             :   uint16_t getEncodingValue(unsigned RegNo) const {
     450             :     assert(RegNo < NumRegs &&
     451             :            "Attempting to get encoding for invalid register number!");
     452    24955723 :     return RegEncodingTable[RegNo];
     453             :   }
     454             : 
     455             :   /// Returns true if RegB is a sub-register of RegA.
     456             :   bool isSubRegister(unsigned RegA, unsigned RegB) const {
     457     6473636 :     return isSuperRegister(RegB, RegA);
     458             :   }
     459             : 
     460             :   /// Returns true if RegB is a super-register of RegA.
     461             :   bool isSuperRegister(unsigned RegA, unsigned RegB) const;
     462             : 
     463             :   /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
     464             :   bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
     465             :     return isSuperRegisterEq(RegB, RegA);
     466             :   }
     467             : 
     468             :   /// Returns true if RegB is a super-register of RegA or if
     469             :   /// RegB == RegA.
     470             :   bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
     471       14095 :     return RegA == RegB || isSuperRegister(RegA, RegB);
     472             :   }
     473             : 
     474             :   /// Returns true if RegB is a super-register or sub-register of RegA
     475             :   /// or if RegB == RegA.
     476         758 :   bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
     477         544 :     return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
     478             :   }
     479             : };
     480             : 
     481             : //===----------------------------------------------------------------------===//
     482             : //                          Register List Iterators
     483             : //===----------------------------------------------------------------------===//
     484             : 
     485             : // MCRegisterInfo provides lists of super-registers, sub-registers, and
     486             : // aliasing registers. Use these iterator classes to traverse the lists.
     487             : 
     488             : /// MCSubRegIterator enumerates all sub-registers of Reg.
     489             : /// If IncludeSelf is set, Reg itself is included in the list.
     490             : class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
     491             : public:
     492             :   MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
     493             :                      bool IncludeSelf = false) {
     494   219109644 :     init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
     495             :     // Initially, the iterator points to Reg itself.
     496             :     if (!IncludeSelf)
     497             :       ++*this;
     498             :   }
     499             : };
     500             : 
     501             : /// Iterator that enumerates the sub-registers of a Reg and the associated
     502             : /// sub-register indices.
     503             : class MCSubRegIndexIterator {
     504             :   MCSubRegIterator SRIter;
     505             :   const uint16_t *SRIndex;
     506             : 
     507             : public:
     508             :   /// Constructs an iterator that traverses subregisters and their
     509             :   /// associated subregister indices.
     510             :   MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
     511             :     : SRIter(Reg, MCRI) {
     512      952658 :     SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
     513             :   }
     514             : 
     515             :   /// Returns current sub-register.
     516             :   unsigned getSubReg() const {
     517             :     return *SRIter;
     518             :   }
     519             : 
     520             :   /// Returns sub-register index of the current sub-register.
     521             :   unsigned getSubRegIndex() const {
     522       11609 :     return *SRIndex;
     523             :   }
     524             : 
     525             :   /// Returns true if this iterator is not yet at the end.
     526             :   bool isValid() const { return SRIter.isValid(); }
     527             : 
     528             :   /// Moves to the next position.
     529             :   void operator++() {
     530             :     ++SRIter;
     531       11609 :     ++SRIndex;
     532             :   }
     533             : };
     534             : 
     535             : /// MCSuperRegIterator enumerates all super-registers of Reg.
     536             : /// If IncludeSelf is set, Reg itself is included in the list.
     537             : class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
     538             : public:
     539             :   MCSuperRegIterator() = default;
     540             : 
     541             :   MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
     542             :                      bool IncludeSelf = false) {
     543   190592251 :     init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
     544             :     // Initially, the iterator points to Reg itself.
     545             :     if (!IncludeSelf)
     546             :       ++*this;
     547             :   }
     548             : };
     549             : 
     550             : // Definition for isSuperRegister. Put it down here since it needs the
     551             : // iterator defined above in addition to the MCRegisterInfo class itself.
     552    16718027 : inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
     553    74502246 :   for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
     554    62537585 :     if (*I == RegB)
     555             :       return true;
     556    11964661 :   return false;
     557             : }
     558             : 
     559             : //===----------------------------------------------------------------------===//
     560             : //                               Register Units
     561             : //===----------------------------------------------------------------------===//
     562             : 
     563             : // Register units are used to compute register aliasing. Every register has at
     564             : // least one register unit, but it can have more. Two registers overlap if and
     565             : // only if they have a common register unit.
     566             : //
     567             : // A target with a complicated sub-register structure will typically have many
     568             : // fewer register units than actual registers. MCRI::getNumRegUnits() returns
     569             : // the number of register units in the target.
     570             : 
     571             : // MCRegUnitIterator enumerates a list of register units for Reg. The list is
     572             : // in ascending numerical order.
     573             : class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
     574             : public:
     575             :   /// MCRegUnitIterator - Create an iterator that traverses the register units
     576             :   /// in Reg.
     577             :   MCRegUnitIterator() = default;
     578             : 
     579             :   MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
     580             :     assert(Reg && "Null register has no regunits");
     581             :     // Decode the RegUnits MCRegisterDesc field.
     582   131550795 :     unsigned RU = MCRI->get(Reg).RegUnits;
     583   131550795 :     unsigned Scale = RU & 15;
     584   131550795 :     unsigned Offset = RU >> 4;
     585             : 
     586             :     // Initialize the iterator to Reg * Scale, and the List pointer to
     587             :     // DiffLists + Offset.
     588   131550795 :     init(Reg * Scale, MCRI->DiffLists + Offset);
     589             : 
     590             :     // That may not be a valid unit, we need to advance by one to get the real
     591             :     // unit number. The first differential can be 0 which would normally
     592             :     // terminate the list, but since we know every register has at least one
     593             :     // unit, we can allow a 0 differential here.
     594             :     advance();
     595             :   }
     596             : };
     597             : 
     598             : /// MCRegUnitMaskIterator enumerates a list of register units and their
     599             : /// associated lane masks for Reg. The register units are in ascending
     600             : /// numerical order.
     601             : class MCRegUnitMaskIterator {
     602             :   MCRegUnitIterator RUIter;
     603             :   const LaneBitmask *MaskListIter;
     604             : 
     605             : public:
     606             :   MCRegUnitMaskIterator() = default;
     607             : 
     608             :   /// Constructs an iterator that traverses the register units and their
     609             :   /// associated LaneMasks in Reg.
     610             :   MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
     611             :     : RUIter(Reg, MCRI) {
     612     5962626 :       uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
     613     5962626 :       MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
     614             :   }
     615             : 
     616             :   /// Returns a (RegUnit, LaneMask) pair.
     617             :   std::pair<unsigned,LaneBitmask> operator*() const {
     618             :     return std::make_pair(*RUIter, *MaskListIter);
     619             :   }
     620             : 
     621             :   /// Returns true if this iterator is not yet at the end.
     622             :   bool isValid() const { return RUIter.isValid(); }
     623             : 
     624             :   /// Moves to the next position.
     625             :   void operator++() {
     626     6157337 :     ++MaskListIter;
     627             :     ++RUIter;
     628             :   }
     629             : };
     630             : 
     631             : // Each register unit has one or two root registers. The complete set of
     632             : // registers containing a register unit is the union of the roots and their
     633             : // super-registers. All registers aliasing Unit can be visited like this:
     634             : //
     635             : //   for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
     636             : //     for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
     637             : //       visit(*SI);
     638             : //    }
     639             : 
     640             : /// MCRegUnitRootIterator enumerates the root registers of a register unit.
     641             : class MCRegUnitRootIterator {
     642             :   uint16_t Reg0 = 0;
     643             :   uint16_t Reg1 = 0;
     644             : 
     645             : public:
     646    76783399 :   MCRegUnitRootIterator() = default;
     647             : 
     648             :   MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
     649             :     assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
     650   113833984 :     Reg0 = MCRI->RegUnitRoots[RegUnit][0];
     651   113833984 :     Reg1 = MCRI->RegUnitRoots[RegUnit][1];
     652             :   }
     653             : 
     654             :   /// Dereference to get the current root register.
     655             :   unsigned operator*() const {
     656     1204332 :     return Reg0;
     657             :   }
     658             : 
     659             :   /// Check if the iterator is at the end of the list.
     660             :   bool isValid() const {
     661             :     return Reg0;
     662             :   }
     663             : 
     664             :   /// Preincrement to move to the next root register.
     665             :   void operator++() {
     666             :     assert(isValid() && "Cannot move off the end of the list.");
     667    96626416 :     Reg0 = Reg1;
     668    96626416 :     Reg1 = 0;
     669             :   }
     670             : };
     671             : 
     672             : /// MCRegAliasIterator enumerates all registers aliasing Reg.  If IncludeSelf is
     673             : /// set, Reg itself is included in the list.  This iterator does not guarantee
     674             : /// any ordering or that entries are unique.
     675             : class MCRegAliasIterator {
     676             : private:
     677             :   unsigned Reg;
     678             :   const MCRegisterInfo *MCRI;
     679             :   bool IncludeSelf;
     680             : 
     681             :   MCRegUnitIterator RI;
     682             :   MCRegUnitRootIterator RRI;
     683             :   MCSuperRegIterator SI;
     684             : 
     685             : public:
     686    76783399 :   MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
     687             :                      bool IncludeSelf)
     688    76783399 :     : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
     689             :     // Initialize the iterators.
     690    76783399 :     for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
     691   153566796 :       for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
     692    76792679 :         for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
     693    96134384 :           if (!(!IncludeSelf && Reg == *SI))
     694             :             return;
     695             :         }
     696             :       }
     697             :     }
     698             :   }
     699             : 
     700   626317924 :   bool isValid() const { return RI.isValid(); }
     701             : 
     702             :   unsigned operator*() const {
     703             :     assert(SI.isValid() && "Cannot dereference an invalid iterator.");
     704   610184364 :     return *SI;
     705             :   }
     706             : 
     707   533152127 :   void advance() {
     708             :     // Assuming SI is valid.
     709             :     ++SI;
     710   533152127 :     if (SI.isValid()) return;
     711             : 
     712             :     ++RRI;
     713    95262063 :     if (RRI.isValid()) {
     714       96798 :       SI = MCSuperRegIterator(*RRI, MCRI, true);
     715       48399 :       return;
     716             :     }
     717             : 
     718             :     ++RI;
     719    95213664 :     if (RI.isValid()) {
     720    65395304 :       RRI = MCRegUnitRootIterator(*RI, MCRI);
     721    32697652 :       SI = MCSuperRegIterator(*RRI, MCRI, true);
     722             :     }
     723             :   }
     724             : 
     725   528727116 :   void operator++() {
     726             :     assert(isValid() && "Cannot move off the end of the list.");
     727   533152127 :     do advance();
     728   572203577 :     while (!IncludeSelf && isValid() && *SI == Reg);
     729   528727116 :   }
     730             : };
     731             : 
     732             : } // end namespace llvm
     733             : 
     734             : #endif // LLVM_MC_MCREGISTERINFO_H

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