LCOV - code coverage report
Current view: top level - include/llvm/MC - MCSubtargetInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 19 23 82.6 %
Date: 2017-09-14 15:23:50 Functions: 4 6 66.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file describes the subtarget options of a Target machine.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_MC_MCSUBTARGETINFO_H
      15             : #define LLVM_MC_MCSUBTARGETINFO_H
      16             : 
      17             : #include "llvm/ADT/ArrayRef.h"
      18             : #include "llvm/ADT/StringRef.h"
      19             : #include "llvm/ADT/Triple.h"
      20             : #include "llvm/MC/MCInstrItineraries.h"
      21             : #include "llvm/MC/MCSchedule.h"
      22             : #include "llvm/MC/SubtargetFeature.h"
      23             : #include <algorithm>
      24             : #include <cassert>
      25             : #include <cstdint>
      26             : #include <string>
      27             : 
      28             : namespace llvm {
      29             : 
      30             : class MachineInstr;
      31             : class MCInst;
      32             : 
      33             : //===----------------------------------------------------------------------===//
      34             : ///
      35             : /// MCSubtargetInfo - Generic base class for all target subtargets.
      36             : ///
      37             : class MCSubtargetInfo {
      38             :   Triple TargetTriple;                        // Target triple
      39             :   std::string CPU; // CPU being targeted.
      40             :   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
      41             :   ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
      42             : 
      43             :   // Scheduler machine model
      44             :   const SubtargetInfoKV *ProcSchedModels;
      45             :   const MCWriteProcResEntry *WriteProcResTable;
      46             :   const MCWriteLatencyEntry *WriteLatencyTable;
      47             :   const MCReadAdvanceEntry *ReadAdvanceTable;
      48             :   const MCSchedModel *CPUSchedModel;
      49             : 
      50             :   const InstrStage *Stages;            // Instruction itinerary stages
      51             :   const unsigned *OperandCycles;       // Itinerary operand cycles
      52             :   const unsigned *ForwardingPaths;     // Forwarding paths
      53             :   FeatureBitset FeatureBits;           // Feature bits for current CPU + FS
      54             : 
      55             : public:
      56        3296 :   MCSubtargetInfo(const MCSubtargetInfo &) = default;
      57             :   MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
      58             :                   ArrayRef<SubtargetFeatureKV> PF,
      59             :                   ArrayRef<SubtargetFeatureKV> PD,
      60             :                   const SubtargetInfoKV *ProcSched,
      61             :                   const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
      62             :                   const MCReadAdvanceEntry *RA, const InstrStage *IS,
      63             :                   const unsigned *OC, const unsigned *FP);
      64             :   MCSubtargetInfo() = delete;
      65             :   MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
      66             :   MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete;
      67      226328 :   virtual ~MCSubtargetInfo() = default;
      68             : 
      69             :   /// getTargetTriple - Return the target triple string.
      70        6211 :   const Triple &getTargetTriple() const { return TargetTriple; }
      71             : 
      72             :   /// getCPU - Return the CPU string.
      73             :   StringRef getCPU() const {
      74      274634 :     return CPU;
      75             :   }
      76             : 
      77             :   /// getFeatureBits - Return the feature bits.
      78             :   ///
      79             :   const FeatureBitset& getFeatureBits() const {
      80     1433086 :     return FeatureBits;
      81             :   }
      82             : 
      83             :   /// setFeatureBits - Set the feature bits.
      84             :   ///
      85             :   void setFeatureBits(const FeatureBitset &FeatureBits_) {
      86         137 :     FeatureBits = FeatureBits_;
      87             :   }
      88             : 
      89             :   bool hasFeature(unsigned Feature) const {
      90      101826 :     return FeatureBits[Feature];
      91             :   }
      92             : 
      93             : protected:
      94             :   /// Initialize the scheduling model and feature bits.
      95             :   ///
      96             :   /// FIXME: Find a way to stick this in the constructor, since it should only
      97             :   /// be called during initialization.
      98             :   void InitMCProcessorInfo(StringRef CPU, StringRef FS);
      99             : 
     100             : public:
     101             :   /// Set the features to the default for the given CPU with an appended feature
     102             :   /// string.
     103             :   void setDefaultFeatures(StringRef CPU, StringRef FS);
     104             : 
     105             :   /// ToggleFeature - Toggle a feature and returns the re-computed feature
     106             :   /// bits. This version does not change the implied bits.
     107             :   FeatureBitset ToggleFeature(uint64_t FB);
     108             : 
     109             :   /// ToggleFeature - Toggle a feature and returns the re-computed feature
     110             :   /// bits. This version does not change the implied bits.
     111             :   FeatureBitset ToggleFeature(const FeatureBitset& FB);
     112             : 
     113             :   /// ToggleFeature - Toggle a set of features and returns the re-computed
     114             :   /// feature bits. This version will also change all implied bits.
     115             :   FeatureBitset ToggleFeature(StringRef FS);
     116             : 
     117             :   /// Apply a feature flag and return the re-computed feature bits, including
     118             :   /// all feature bits implied by the flag.
     119             :   FeatureBitset ApplyFeatureFlag(StringRef FS);
     120             : 
     121             :   /// getSchedModelForCPU - Get the machine model of a CPU.
     122             :   ///
     123             :   const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
     124             : 
     125             :   /// Get the machine model for this subtarget's CPU.
     126             :   const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
     127             : 
     128             :   /// Return an iterator at the first process resource consumed by the given
     129             :   /// scheduling class.
     130             :   const MCWriteProcResEntry *getWriteProcResBegin(
     131             :     const MCSchedClassDesc *SC) const {
     132     4240731 :     return &WriteProcResTable[SC->WriteProcResIdx];
     133             :   }
     134             :   const MCWriteProcResEntry *getWriteProcResEnd(
     135             :     const MCSchedClassDesc *SC) const {
     136     1249829 :     return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
     137             :   }
     138             : 
     139             :   const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
     140             :                                                   unsigned DefIdx) const {
     141             :     assert(DefIdx < SC->NumWriteLatencyEntries &&
     142             :            "MachineModel does not specify a WriteResource for DefIdx");
     143             : 
     144     2034070 :     return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
     145             :   }
     146             : 
     147             :   int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
     148             :                            unsigned WriteResID) const {
     149             :     // TODO: The number of read advance entries in a class can be significant
     150             :     // (~50). Consider compressing the WriteID into a dense ID of those that are
     151             :     // used by ReadAdvance and representing them as a bitset.
     152        5325 :     for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
     153        3252 :            *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
     154        4814 :       if (I->UseIdx < UseIdx)
     155             :         continue;
     156        3231 :       if (I->UseIdx > UseIdx)
     157             :         break;
     158             :       // Find the first WriteResIdx match, which has the highest cycle count.
     159        3210 :       if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
     160        2720 :         return I->Cycles;
     161             :       }
     162             :     }
     163             :     return 0;
     164             :   }
     165             : 
     166             :   /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
     167             :   ///
     168             :   InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
     169             : 
     170             :   /// Initialize an InstrItineraryData instance.
     171             :   void initInstrItins(InstrItineraryData &InstrItins) const;
     172             : 
     173             :   /// Check whether the CPU string is valid.
     174          31 :   bool isCPUStringValid(StringRef CPU) const {
     175          93 :     auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
     176         124 :     return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
     177             :   }
     178             : 
     179             :   /// Returns string representation of scheduler comment
     180           0 :   virtual std::string getSchedInfoStr(const MachineInstr &MI) const {
     181           0 :     return {};
     182             :   }
     183             : 
     184           0 :   virtual std::string getSchedInfoStr(MCInst const &MCI) const {
     185           0 :     return {};
     186             :   }
     187             : };
     188             : 
     189             : } // end namespace llvm
     190             : 
     191             : #endif // LLVM_MC_MCSUBTARGETINFO_H

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