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1 : //===- llvm/Target/TargetLowering.h - Target Lowering Info ------*- C++ -*-===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : ///
10 : /// \file
11 : /// This file describes how to lower LLVM code to machine code. This has two
12 : /// main components:
13 : ///
14 : /// 1. Which ValueTypes are natively supported by the target.
15 : /// 2. Which operations are supported for supported ValueTypes.
16 : /// 3. Cost thresholds for alternative implementations of certain operations.
17 : ///
18 : /// In addition it has a few other components, like information about FP
19 : /// immediates.
20 : ///
21 : //===----------------------------------------------------------------------===//
22 :
23 : #ifndef LLVM_TARGET_TARGETLOWERING_H
24 : #define LLVM_TARGET_TARGETLOWERING_H
25 :
26 : #include "llvm/ADT/APInt.h"
27 : #include "llvm/ADT/ArrayRef.h"
28 : #include "llvm/ADT/DenseMap.h"
29 : #include "llvm/ADT/STLExtras.h"
30 : #include "llvm/ADT/SmallVector.h"
31 : #include "llvm/ADT/StringRef.h"
32 : #include "llvm/CodeGen/DAGCombine.h"
33 : #include "llvm/CodeGen/ISDOpcodes.h"
34 : #include "llvm/CodeGen/MachineValueType.h"
35 : #include "llvm/CodeGen/RuntimeLibcalls.h"
36 : #include "llvm/CodeGen/SelectionDAG.h"
37 : #include "llvm/CodeGen/SelectionDAGNodes.h"
38 : #include "llvm/CodeGen/ValueTypes.h"
39 : #include "llvm/IR/Attributes.h"
40 : #include "llvm/IR/CallSite.h"
41 : #include "llvm/IR/CallingConv.h"
42 : #include "llvm/IR/DataLayout.h"
43 : #include "llvm/IR/DerivedTypes.h"
44 : #include "llvm/IR/Function.h"
45 : #include "llvm/IR/IRBuilder.h"
46 : #include "llvm/IR/InlineAsm.h"
47 : #include "llvm/IR/Instruction.h"
48 : #include "llvm/IR/Instructions.h"
49 : #include "llvm/IR/Type.h"
50 : #include "llvm/MC/MCRegisterInfo.h"
51 : #include "llvm/Support/AtomicOrdering.h"
52 : #include "llvm/Support/Casting.h"
53 : #include "llvm/Support/ErrorHandling.h"
54 : #include "llvm/Target/TargetCallingConv.h"
55 : #include "llvm/Target/TargetMachine.h"
56 : #include <algorithm>
57 : #include <cassert>
58 : #include <climits>
59 : #include <cstdint>
60 : #include <iterator>
61 : #include <map>
62 : #include <string>
63 : #include <utility>
64 : #include <vector>
65 :
66 : namespace llvm {
67 :
68 : class BranchProbability;
69 : class CCState;
70 : class CCValAssign;
71 : class Constant;
72 : class FastISel;
73 : class FunctionLoweringInfo;
74 : class GlobalValue;
75 : class IntrinsicInst;
76 : struct KnownBits;
77 : class LLVMContext;
78 : class MachineBasicBlock;
79 : class MachineFunction;
80 : class MachineInstr;
81 : class MachineJumpTableInfo;
82 : class MachineLoop;
83 : class MachineRegisterInfo;
84 : class MCContext;
85 : class MCExpr;
86 : class Module;
87 : class TargetRegisterClass;
88 : class TargetLibraryInfo;
89 : class TargetRegisterInfo;
90 : class Value;
91 :
92 : namespace Sched {
93 :
94 : enum Preference {
95 : None, // No preference
96 : Source, // Follow source order.
97 : RegPressure, // Scheduling for lowest register pressure.
98 : Hybrid, // Scheduling for both latency and register pressure.
99 : ILP, // Scheduling for ILP in low register pressure mode.
100 : VLIW // Scheduling for VLIW targets.
101 : };
102 :
103 : } // end namespace Sched
104 :
105 : /// This base class for TargetLowering contains the SelectionDAG-independent
106 : /// parts that can be used from the rest of CodeGen.
107 : class TargetLoweringBase {
108 : public:
109 : /// This enum indicates whether operations are valid for a target, and if not,
110 : /// what action should be used to make them valid.
111 : enum LegalizeAction : uint8_t {
112 : Legal, // The target natively supports this operation.
113 : Promote, // This operation should be executed in a larger type.
114 : Expand, // Try to expand this to other ops, otherwise use a libcall.
115 : LibCall, // Don't try to expand this to other ops, always use a libcall.
116 : Custom // Use the LowerOperation hook to implement custom lowering.
117 : };
118 :
119 : /// This enum indicates whether a types are legal for a target, and if not,
120 : /// what action should be used to make them valid.
121 : enum LegalizeTypeAction : uint8_t {
122 : TypeLegal, // The target natively supports this type.
123 : TypePromoteInteger, // Replace this integer with a larger one.
124 : TypeExpandInteger, // Split this integer into two of half the size.
125 : TypeSoftenFloat, // Convert this float to a same size integer type,
126 : // if an operation is not supported in target HW.
127 : TypeExpandFloat, // Split this float into two of half the size.
128 : TypeScalarizeVector, // Replace this one-element vector with its element.
129 : TypeSplitVector, // Split this vector into two of half the size.
130 : TypeWidenVector, // This vector should be widened into a larger vector.
131 : TypePromoteFloat // Replace this float with a larger one.
132 : };
133 :
134 : /// LegalizeKind holds the legalization kind that needs to happen to EVT
135 : /// in order to type-legalize it.
136 : using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
137 :
138 : /// Enum that describes how the target represents true/false values.
139 : enum BooleanContent {
140 : UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
141 : ZeroOrOneBooleanContent, // All bits zero except for bit 0.
142 : ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
143 : };
144 :
145 : /// Enum that describes what type of support for selects the target has.
146 : enum SelectSupportKind {
147 : ScalarValSelect, // The target supports scalar selects (ex: cmov).
148 : ScalarCondVectorVal, // The target supports selects with a scalar condition
149 : // and vector values (ex: cmov).
150 : VectorMaskSelect // The target supports vector selects with a vector
151 : // mask (ex: x86 blends).
152 : };
153 :
154 : /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
155 : /// to, if at all. Exists because different targets have different levels of
156 : /// support for these atomic instructions, and also have different options
157 : /// w.r.t. what they should expand to.
158 : enum class AtomicExpansionKind {
159 : None, // Don't expand the instruction.
160 : LLSC, // Expand the instruction into loadlinked/storeconditional; used
161 : // by ARM/AArch64.
162 : LLOnly, // Expand the (load) instruction into just a load-linked, which has
163 : // greater atomic guarantees than a normal load.
164 : CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
165 : };
166 :
167 : /// Enum that specifies when a multiplication should be expanded.
168 : enum class MulExpansionKind {
169 : Always, // Always expand the instruction.
170 : OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
171 : // or custom.
172 : };
173 :
174 : class ArgListEntry {
175 : public:
176 : Value *Val = nullptr;
177 : SDValue Node = SDValue();
178 : Type *Ty = nullptr;
179 : bool IsSExt : 1;
180 : bool IsZExt : 1;
181 : bool IsInReg : 1;
182 : bool IsSRet : 1;
183 : bool IsNest : 1;
184 : bool IsByVal : 1;
185 : bool IsInAlloca : 1;
186 : bool IsReturned : 1;
187 : bool IsSwiftSelf : 1;
188 : bool IsSwiftError : 1;
189 : uint16_t Alignment = 0;
190 :
191 : ArgListEntry()
192 411369 : : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
193 : IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
194 411369 : IsSwiftSelf(false), IsSwiftError(false) {}
195 :
196 : void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
197 : };
198 : using ArgListTy = std::vector<ArgListEntry>;
199 :
200 4195 : virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
201 4195 : ArgListTy &Args) const {};
202 :
203 : static ISD::NodeType getExtendForContent(BooleanContent Content) {
204 38930 : switch (Content) {
205 : case UndefinedBooleanContent:
206 : // Extend by adding rubbish bits.
207 : return ISD::ANY_EXTEND;
208 36479 : case ZeroOrOneBooleanContent:
209 : // Extend by adding zero bits.
210 : return ISD::ZERO_EXTEND;
211 2444 : case ZeroOrNegativeOneBooleanContent:
212 : // Extend by copying the sign bit.
213 : return ISD::SIGN_EXTEND;
214 : }
215 0 : llvm_unreachable("Invalid content kind");
216 : }
217 :
218 : /// NOTE: The TargetMachine owns TLOF.
219 : explicit TargetLoweringBase(const TargetMachine &TM);
220 : TargetLoweringBase(const TargetLoweringBase &) = delete;
221 : TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
222 83991 : virtual ~TargetLoweringBase() = default;
223 :
224 : protected:
225 : /// \brief Initialize all of the actions to default values.
226 : void initActions();
227 :
228 : public:
229 : const TargetMachine &getTargetMachine() const { return TM; }
230 :
231 5794 : virtual bool useSoftFloat() const { return false; }
232 :
233 : /// Return the pointer type for the given address space, defaults to
234 : /// the pointer type from the data layout.
235 : /// FIXME: The default needs to be removed once all the code is updated.
236 : MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
237 5514572 : return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
238 : }
239 :
240 : /// Return the type for frame index, which is determined by
241 : /// the alloca address space specified through the data layout.
242 149156 : MVT getFrameIndexTy(const DataLayout &DL) const {
243 298312 : return getPointerTy(DL, DL.getAllocaAddrSpace());
244 : }
245 :
246 : /// Return the type for operands of fence.
247 : /// TODO: Let fence operands be of i32 type and remove this.
248 502 : virtual MVT getFenceOperandTy(const DataLayout &DL) const {
249 1004 : return getPointerTy(DL);
250 : }
251 :
252 : /// EVT is not used in-tree, but is used by out-of-tree target.
253 : /// A documentation for this function would be nice...
254 : virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
255 :
256 : EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
257 :
258 : /// Returns the type to be used for the index operand of:
259 : /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
260 : /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
261 128223 : virtual MVT getVectorIdxTy(const DataLayout &DL) const {
262 256446 : return getPointerTy(DL);
263 : }
264 :
265 52523 : virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
266 52523 : return true;
267 : }
268 :
269 : /// Return true if multiple condition registers are available.
270 : bool hasMultipleConditionRegisters() const {
271 : return HasMultipleConditionRegisters;
272 : }
273 :
274 : /// Return true if the target has BitExtract instructions.
275 : bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
276 :
277 : /// Return the preferred vector type legalization action.
278 : virtual TargetLoweringBase::LegalizeTypeAction
279 1341150 : getPreferredVectorAction(EVT VT) const {
280 : // The default action for one element vectors is to scalarize
281 2279327 : if (VT.getVectorNumElements() == 1)
282 : return TypeScalarizeVector;
283 : // The default action for other vectors is to promote
284 1123235 : return TypePromoteInteger;
285 : }
286 :
287 : // There are two general methods for expanding a BUILD_VECTOR node:
288 : // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
289 : // them together.
290 : // 2. Build the vector on the stack and then load it.
291 : // If this function returns true, then method (1) will be used, subject to
292 : // the constraint that all of the necessary shuffles are legal (as determined
293 : // by isShuffleMaskLegal). If this function returns false, then method (2) is
294 : // always used. The vector type, and the number of defined values, are
295 : // provided.
296 : virtual bool
297 1554 : shouldExpandBuildVectorWithShuffles(EVT /* VT */,
298 : unsigned DefinedValues) const {
299 1580 : return DefinedValues < 3;
300 : }
301 :
302 : /// Return true if integer divide is usually cheaper than a sequence of
303 : /// several shifts, adds, and multiplies for this target.
304 : /// The definition of "cheaper" may depend on whether we're optimizing
305 : /// for speed or for size.
306 506 : virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
307 :
308 : /// Return true if the target can handle a standalone remainder operation.
309 0 : virtual bool hasStandaloneRem(EVT VT) const {
310 0 : return true;
311 : }
312 :
313 : /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
314 70 : virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
315 : // Default behavior is to replace SQRT(X) with X*RSQRT(X).
316 70 : return false;
317 : }
318 :
319 : /// Reciprocal estimate status values used by the functions below.
320 : enum ReciprocalEstimate : int {
321 : Unspecified = -1,
322 : Disabled = 0,
323 : Enabled = 1
324 : };
325 :
326 : /// Return a ReciprocalEstimate enum value for a square root of the given type
327 : /// based on the function's attributes. If the operation is not overridden by
328 : /// the function's attributes, "Unspecified" is returned and target defaults
329 : /// are expected to be used for instruction selection.
330 : int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
331 :
332 : /// Return a ReciprocalEstimate enum value for a division of the given type
333 : /// based on the function's attributes. If the operation is not overridden by
334 : /// the function's attributes, "Unspecified" is returned and target defaults
335 : /// are expected to be used for instruction selection.
336 : int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
337 :
338 : /// Return the refinement step count for a square root of the given type based
339 : /// on the function's attributes. If the operation is not overridden by
340 : /// the function's attributes, "Unspecified" is returned and target defaults
341 : /// are expected to be used for instruction selection.
342 : int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
343 :
344 : /// Return the refinement step count for a division of the given type based
345 : /// on the function's attributes. If the operation is not overridden by
346 : /// the function's attributes, "Unspecified" is returned and target defaults
347 : /// are expected to be used for instruction selection.
348 : int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
349 :
350 : /// Returns true if target has indicated at least one type should be bypassed.
351 269560 : bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
352 :
353 : /// Returns map of slow types for division or remainder with corresponding
354 : /// fast types
355 : const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
356 11773 : return BypassSlowDivWidths;
357 : }
358 :
359 : /// Return true if Flow Control is an expensive operation that should be
360 : /// avoided.
361 : bool isJumpExpensive() const { return JumpIsExpensive; }
362 :
363 : /// Return true if selects are only cheaper than branches if the branch is
364 : /// unlikely to be predicted right.
365 : bool isPredictableSelectExpensive() const {
366 : return PredictableSelectIsExpensive;
367 : }
368 :
369 : /// If a branch or a select condition is skewed in one direction by more than
370 : /// this factor, it is very likely to be predicted correctly.
371 : virtual BranchProbability getPredictableBranchThreshold() const;
372 :
373 : /// Return true if the following transform is beneficial:
374 : /// fold (conv (load x)) -> (load (conv*)x)
375 : /// On architectures that don't natively support some vector loads
376 : /// efficiently, casting the load to a smaller vector of larger types and
377 : /// loading is more efficient, however, this can be undone by optimizations in
378 : /// dag combiner.
379 43282 : virtual bool isLoadBitCastBeneficial(EVT LoadVT,
380 : EVT BitcastVT) const {
381 : // Don't do if we could do an indexed load on the original type, but not on
382 : // the new one.
383 43282 : if (!LoadVT.isSimple() || !BitcastVT.isSimple())
384 : return true;
385 :
386 43260 : MVT LoadMVT = LoadVT.getSimpleVT();
387 :
388 : // Don't bother doing this if it's just going to be promoted again later, as
389 : // doing so might interfere with other combines.
390 125361 : if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
391 119563 : getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
392 : return false;
393 :
394 : return true;
395 : }
396 :
397 : /// Return true if the following transform is beneficial:
398 : /// (store (y (conv x)), y*)) -> (store x, (x*))
399 47053 : virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
400 : // Default to the same logic as loads.
401 47053 : return isLoadBitCastBeneficial(StoreVT, BitcastVT);
402 : }
403 :
404 : /// Return true if it is expected to be cheaper to do a store of a non-zero
405 : /// vector constant with the given size and type for the address space than to
406 : /// store the individual scalar element constants.
407 107534 : virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
408 : unsigned NumElem,
409 : unsigned AddrSpace) const {
410 107534 : return false;
411 : }
412 :
413 : /// Should we merge stores after Legalization (generally
414 : /// better quality) or before (simpler)
415 396530 : virtual bool mergeStoresAfterLegalization() const { return false; }
416 :
417 : /// Returns if it's reasonable to merge stores to MemVT size.
418 4087 : virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
419 : const SelectionDAG &DAG) const {
420 4087 : return true;
421 : }
422 :
423 : /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
424 8 : virtual bool isCheapToSpeculateCttz() const {
425 8 : return false;
426 : }
427 :
428 : /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
429 5 : virtual bool isCheapToSpeculateCtlz() const {
430 5 : return false;
431 : }
432 :
433 : /// \brief Return true if ctlz instruction is fast.
434 0 : virtual bool isCtlzFast() const {
435 0 : return false;
436 : }
437 :
438 : /// Return true if it is safe to transform an integer-domain bitwise operation
439 : /// into the equivalent floating-point operation. This should be set to true
440 : /// if the target has IEEE-754-compliant fabs/fneg operations for the input
441 : /// type.
442 35259 : virtual bool hasBitPreservingFPLogic(EVT VT) const {
443 35259 : return false;
444 : }
445 :
446 : /// \brief Return true if it is cheaper to split the store of a merged int val
447 : /// from a pair of smaller values into multiple stores.
448 55 : virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
449 55 : return false;
450 : }
451 :
452 : /// \brief Return if the target supports combining a
453 : /// chain like:
454 : /// \code
455 : /// %andResult = and %val1, #mask
456 : /// %icmpResult = icmp %andResult, 0
457 : /// \endcode
458 : /// into a single machine instruction of a form like:
459 : /// \code
460 : /// cc = test %register, #mask
461 : /// \endcode
462 36 : virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
463 36 : return false;
464 : }
465 :
466 : /// Use bitwise logic to make pairs of compares more efficient. For example:
467 : /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
468 : /// This should be true when it takes more than one instruction to lower
469 : /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
470 : /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
471 344 : virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
472 344 : return false;
473 : }
474 :
475 : /// Return the preferred operand type if the target has a quick way to compare
476 : /// integer values of the given size. Assume that any legal integer type can
477 : /// be compared efficiently. Targets may override this to allow illegal wide
478 : /// types to return a vector type if there is support to compare that type.
479 0 : virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
480 0 : MVT VT = MVT::getIntegerVT(NumBits);
481 0 : return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
482 : }
483 :
484 : /// Return true if the target should transform:
485 : /// (X & Y) == Y ---> (~X & Y) == 0
486 : /// (X & Y) != Y ---> (~X & Y) != 0
487 : ///
488 : /// This may be profitable if the target has a bitwise and-not operation that
489 : /// sets comparison flags. A target may want to limit the transformation based
490 : /// on the type of Y or if Y is a constant.
491 : ///
492 : /// Note that the transform will not occur if Y is known to be a power-of-2
493 : /// because a mask and compare of a single bit can be handled by inverting the
494 : /// predicate, for example:
495 : /// (X & 8) == 8 ---> (X & 8) != 0
496 415 : virtual bool hasAndNotCompare(SDValue Y) const {
497 415 : return false;
498 : }
499 :
500 : /// Return true if the target has a bitwise and-not operation:
501 : /// X = ~A & B
502 : /// This can be used to simplify select or other instructions.
503 860 : virtual bool hasAndNot(SDValue X) const {
504 : // If the target has the more complex version of this operation, assume that
505 : // it has this operation too.
506 860 : return hasAndNotCompare(X);
507 : }
508 :
509 : /// \brief Return true if the target wants to use the optimization that
510 : /// turns ext(promotableInst1(...(promotableInstN(load)))) into
511 : /// promotedInst1(...(promotedInstN(ext(load)))).
512 : bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
513 :
514 : /// Return true if the target can combine store(extractelement VectorTy,
515 : /// Idx).
516 : /// \p Cost[out] gives the cost of that transformation when this is true.
517 11447 : virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
518 : unsigned &Cost) const {
519 11447 : return false;
520 : }
521 :
522 : /// Return true if target supports floating point exceptions.
523 : bool hasFloatingPointExceptions() const {
524 : return HasFloatingPointExceptions;
525 : }
526 :
527 : /// Return true if target always beneficiates from combining into FMA for a
528 : /// given value type. This must typically return false on targets where FMA
529 : /// takes more cycles to execute than FADD.
530 4259 : virtual bool enableAggressiveFMAFusion(EVT VT) const {
531 4259 : return false;
532 : }
533 :
534 : /// Return the ValueType of the result of SETCC operations.
535 : virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
536 : EVT VT) const;
537 :
538 : /// Return the ValueType for comparison libcalls. Comparions libcalls include
539 : /// floating point comparion calls, and Ordered/Unordered check calls on
540 : /// floating point numbers.
541 : virtual
542 : MVT::SimpleValueType getCmpLibcallReturnType() const;
543 :
544 : /// For targets without i1 registers, this gives the nature of the high-bits
545 : /// of boolean values held in types wider than i1.
546 : ///
547 : /// "Boolean values" are special true/false values produced by nodes like
548 : /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
549 : /// Not to be confused with general values promoted from i1. Some cpus
550 : /// distinguish between vectors of boolean and scalars; the isVec parameter
551 : /// selects between the two kinds. For example on X86 a scalar boolean should
552 : /// be zero extended from i1, while the elements of a vector of booleans
553 : /// should be sign extended from i1.
554 : ///
555 : /// Some cpus also treat floating point types the same way as they treat
556 : /// vectors instead of the way they treat scalars.
557 : BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
558 763737 : if (isVec)
559 98123 : return BooleanVectorContents;
560 670988 : return isFloat ? BooleanFloatContents : BooleanContents;
561 : }
562 :
563 763546 : BooleanContent getBooleanContents(EVT Type) const {
564 2290638 : return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
565 : }
566 :
567 : /// Return target scheduling preference.
568 : Sched::Preference getSchedulingPreference() const {
569 : return SchedPreferenceInfo;
570 : }
571 :
572 : /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
573 : /// for different nodes. This function returns the preference (or none) for
574 : /// the given node.
575 3363304 : virtual Sched::Preference getSchedulingPreference(SDNode *) const {
576 3363304 : return Sched::None;
577 : }
578 :
579 : /// Return the register class that should be used for the specified value
580 : /// type.
581 4778352 : virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
582 4848259 : const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
583 : assert(RC && "This value type is not natively supported!");
584 4778352 : return RC;
585 : }
586 :
587 : /// Return the 'representative' register class for the specified value
588 : /// type.
589 : ///
590 : /// The 'representative' register class is the largest legal super-reg
591 : /// register class for the register class of the value type. For example, on
592 : /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
593 : /// register class is GR64 on x86_64.
594 432250 : virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
595 850944 : const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
596 432250 : return RC;
597 : }
598 :
599 : /// Return the cost of the 'representative' register class for the specified
600 : /// value type.
601 506106 : virtual uint8_t getRepRegClassCostFor(MVT VT) const {
602 506106 : return RepRegClassCostForVT[VT.SimpleTy];
603 : }
604 :
605 : /// Return true if the target has native support for the specified value type.
606 : /// This means that it has a register that directly holds it without
607 : /// promotions or expansions.
608 : bool isTypeLegal(EVT VT) const {
609 : assert(!VT.isSimple() ||
610 : (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
611 133565263 : return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
612 : }
613 :
614 : class ValueTypeActionImpl {
615 : /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
616 : /// that indicates how instruction selection should deal with the type.
617 : LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
618 :
619 : public:
620 28520 : ValueTypeActionImpl() {
621 85560 : std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
622 : TypeLegal);
623 : }
624 :
625 : LegalizeTypeAction getTypeAction(MVT VT) const {
626 29048530 : return ValueTypeActions[VT.SimpleTy];
627 : }
628 :
629 : void setTypeAction(MVT VT, LegalizeTypeAction Action) {
630 2736558 : ValueTypeActions[VT.SimpleTy] = Action;
631 : }
632 : };
633 :
634 : const ValueTypeActionImpl &getValueTypeActions() const {
635 : return ValueTypeActions;
636 : }
637 :
638 : /// Return how we should legalize values of this type, either it is already
639 : /// legal (return 'Legal') or we need to promote it to a larger type (return
640 : /// 'Promote'), or we need to expand it into multiple registers of smaller
641 : /// integer type (return 'Expand'). 'Custom' is not an option.
642 : LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
643 27625177 : return getTypeConversion(Context, VT).first;
644 : }
645 : LegalizeTypeAction getTypeAction(MVT VT) const {
646 : return ValueTypeActions.getTypeAction(VT);
647 : }
648 :
649 : /// For types supported by the target, this is an identity function. For
650 : /// types that must be promoted to larger types, this returns the larger type
651 : /// to promote to. For integer types that are larger than the largest integer
652 : /// register, this contains one step in the expansion to get to the smaller
653 : /// register. For illegal floating point types, this returns the integer type
654 : /// to transform to.
655 : EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
656 588281 : return getTypeConversion(Context, VT).second;
657 : }
658 :
659 : /// For types supported by the target, this is an identity function. For
660 : /// types that must be expanded (i.e. integer types that are larger than the
661 : /// largest integer register or illegal floating point types), this returns
662 : /// the largest legal type it will be expanded to.
663 70636 : EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
664 : assert(!VT.isVector());
665 : while (true) {
666 73286 : switch (getTypeAction(Context, VT)) {
667 70636 : case TypeLegal:
668 70636 : return VT;
669 1325 : case TypeExpandInteger:
670 1325 : VT = getTypeToTransformTo(Context, VT);
671 : break;
672 0 : default:
673 0 : llvm_unreachable("Type is not legal nor is it to be expanded!");
674 : }
675 : }
676 : }
677 :
678 : /// Vector types are broken down into some number of legal first class types.
679 : /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
680 : /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
681 : /// turns into 4 EVT::i32 values with both PPC and X86.
682 : ///
683 : /// This method returns the number of registers needed, and the VT for each
684 : /// register. It also returns the VT and quantity of the intermediate values
685 : /// before they are promoted/expanded.
686 : unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
687 : EVT &IntermediateVT,
688 : unsigned &NumIntermediates,
689 : MVT &RegisterVT) const;
690 :
691 : /// Certain targets such as MIPS require that some types such as vectors are
692 : /// always broken down into scalars in some contexts. This occurs even if the
693 : /// vector type is legal.
694 9878 : virtual unsigned getVectorTypeBreakdownForCallingConv(
695 : LLVMContext &Context, EVT VT, EVT &IntermediateVT,
696 : unsigned &NumIntermediates, MVT &RegisterVT) const {
697 : return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
698 9878 : RegisterVT);
699 : }
700 :
701 : struct IntrinsicInfo {
702 : unsigned opc = 0; // target opcode
703 : EVT memVT; // memory VT
704 : const Value* ptrVal = nullptr; // value representing memory location
705 : int offset = 0; // offset off of ptrVal
706 : unsigned size = 0; // the size of the memory location
707 : // (taken from memVT if zero)
708 : unsigned align = 1; // alignment
709 : bool vol = false; // is volatile?
710 : bool readMem = false; // reads memory?
711 : bool writeMem = false; // writes memory?
712 :
713 : IntrinsicInfo() = default;
714 : };
715 :
716 : /// Given an intrinsic, checks if on the target the intrinsic will need to map
717 : /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
718 : /// true and store the intrinsic information into the IntrinsicInfo that was
719 : /// passed to the function.
720 6233 : virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
721 : unsigned /*Intrinsic*/) const {
722 6233 : return false;
723 : }
724 :
725 : /// Returns true if the target can instruction select the specified FP
726 : /// immediate natively. If false, the legalizer will materialize the FP
727 : /// immediate as a load from a constant pool.
728 65 : virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
729 65 : return false;
730 : }
731 :
732 : /// Targets can use this to indicate that they only support *some*
733 : /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
734 : /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
735 : /// legal.
736 564 : virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
737 564 : return true;
738 : }
739 :
740 : /// Returns true if the operation can trap for the value type.
741 : ///
742 : /// VT must be a legal type. By default, we optimistically assume most
743 : /// operations don't trap except for integer divide and remainder.
744 : virtual bool canOpTrap(unsigned Op, EVT VT) const;
745 :
746 : /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
747 : /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
748 : /// a VAND with a constant pool entry.
749 1155 : virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
750 : EVT /*VT*/) const {
751 1155 : return false;
752 : }
753 :
754 : /// Return how this operation should be treated: either it is legal, needs to
755 : /// be promoted to a larger size, needs to be expanded to some other code
756 : /// sequence, or the target has a custom expander for it.
757 : LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
758 48748452 : if (VT.isExtended()) return Expand;
759 : // If a target-specific SDNode requires legalization, require the target
760 : // to provide custom legalization for it.
761 48645457 : if (Op >= array_lengthof(OpActions[0])) return Custom;
762 48645076 : return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
763 : }
764 :
765 : /// Return true if the specified operation is legal on this target or can be
766 : /// made legal with custom lowering. This is used to help guide high-level
767 : /// lowering decisions.
768 83063 : bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
769 14798208 : return (VT == MVT::Other || isTypeLegal(VT)) &&
770 13408511 : (getOperationAction(Op, VT) == Legal ||
771 8357209 : getOperationAction(Op, VT) == Custom);
772 : }
773 :
774 : /// Return true if the specified operation is legal on this target or can be
775 : /// made legal using promotion. This is used to help guide high-level lowering
776 : /// decisions.
777 147500 : bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
778 442490 : return (VT == MVT::Other || isTypeLegal(VT)) &&
779 298939 : (getOperationAction(Op, VT) == Legal ||
780 155418 : getOperationAction(Op, VT) == Promote);
781 : }
782 :
783 : /// Return true if the specified operation is legal on this target or can be
784 : /// made legal with custom lowering or using promotion. This is used to help
785 : /// guide high-level lowering decisions.
786 43308 : bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
787 127334 : return (VT == MVT::Other || isTypeLegal(VT)) &&
788 104069 : (getOperationAction(Op, VT) == Legal ||
789 64456 : getOperationAction(Op, VT) == Custom ||
790 81688 : getOperationAction(Op, VT) == Promote);
791 : }
792 :
793 : /// Return true if the operation uses custom lowering, regardless of whether
794 : /// the type is legal or not.
795 : bool isOperationCustom(unsigned Op, EVT VT) const {
796 1446 : return getOperationAction(Op, VT) == Custom;
797 : }
798 :
799 : /// Return true if lowering to a jump table is allowed.
800 1795 : bool areJTsAllowed(const Function *Fn) const {
801 5385 : if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
802 : return false;
803 :
804 3505 : return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
805 1712 : isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
806 : }
807 :
808 : /// Check whether the range [Low,High] fits in a machine word.
809 2729 : bool rangeFitsInWord(const APInt &Low, const APInt &High,
810 : const DataLayout &DL) const {
811 : // FIXME: Using the pointer type doesn't seem ideal.
812 2729 : uint64_t BW = DL.getPointerSizeInBits();
813 13645 : uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
814 2729 : return Range <= BW;
815 : }
816 :
817 : /// Return true if lowering to a jump table is suitable for a set of case
818 : /// clusters which may contain \p NumCases cases, \p Range range of values.
819 : /// FIXME: This function check the maximum table size and density, but the
820 : /// minimum size is not checked. It would be nice if the the minimum size is
821 : /// also combined within this function. Currently, the minimum size check is
822 : /// performed in findJumpTable() in SelectionDAGBuiler and
823 : /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
824 2093 : bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
825 : uint64_t Range) const {
826 2093 : const bool OptForSize = SI->getParent()->getParent()->optForSize();
827 2093 : const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
828 : const unsigned MaxJumpTableSize =
829 2041 : OptForSize || getMaximumJumpTableSize() == 0
830 2552 : ? UINT_MAX
831 2093 : : getMaximumJumpTableSize();
832 : // Check whether a range of clusters is dense enough for a jump table.
833 3975 : if (Range <= MaxJumpTableSize &&
834 1882 : (NumCases * 100 >= Range * MinDensity)) {
835 : return true;
836 : }
837 992 : return false;
838 : }
839 :
840 : /// Return true if lowering to a bit test is suitable for a set of case
841 : /// clusters which contains \p NumDests unique destinations, \p Low and
842 : /// \p High as its lowest and highest case values, and expects \p NumCmps
843 : /// case value comparisons. Check if the number of destinations, comparison
844 : /// metric, and range are all suitable.
845 1773 : bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
846 : const APInt &Low, const APInt &High,
847 : const DataLayout &DL) const {
848 : // FIXME: I don't think NumCmps is the correct metric: a single case and a
849 : // range of cases both require only one branch to lower. Just looking at the
850 : // number of clusters and destinations should be enough to decide whether to
851 : // build bit tests.
852 :
853 : // To lower a range with bit tests, the range must fit the bitwidth of a
854 : // machine word.
855 1773 : if (!rangeFitsInWord(Low, High, DL))
856 : return false;
857 :
858 : // Decide whether it's profitable to lower this range with bit tests. Each
859 : // destination requires a bit test and branch, and there is an overall range
860 : // check branch. For a small number of clusters, separate comparisons might
861 : // be cheaper, and for many destinations, splitting the range might be
862 : // better.
863 3055 : return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
864 1501 : (NumDests == 3 && NumCmps >= 6);
865 : }
866 :
867 : /// Return true if the specified operation is illegal on this target or
868 : /// unlikely to be made legal with custom lowering. This is used to help guide
869 : /// high-level lowering decisions.
870 : bool isOperationExpand(unsigned Op, EVT VT) const {
871 43329 : return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
872 : }
873 :
874 : /// Return true if the specified operation is legal on this target.
875 : bool isOperationLegal(unsigned Op, EVT VT) const {
876 3221822 : return (VT == MVT::Other || isTypeLegal(VT)) &&
877 2140468 : getOperationAction(Op, VT) == Legal;
878 : }
879 :
880 : /// Return how this load with extension should be treated: either it is legal,
881 : /// needs to be promoted to a larger size, needs to be expanded to some other
882 : /// code sequence, or the target has a custom expander for it.
883 : LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
884 : EVT MemVT) const {
885 260411 : if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
886 225723 : unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
887 225723 : unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
888 : assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
889 : MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
890 225723 : unsigned Shift = 4 * ExtType;
891 225723 : return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
892 : }
893 :
894 : /// Return true if the specified load with extension is legal on this target.
895 : bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
896 365118 : return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
897 : }
898 :
899 : /// Return true if the specified load with extension is legal or custom
900 : /// on this target.
901 : bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
902 4253 : return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
903 2638 : getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
904 : }
905 :
906 : /// Return how this store with truncation should be treated: either it is
907 : /// legal, needs to be promoted to a larger size, needs to be expanded to some
908 : /// other code sequence, or the target has a custom expander for it.
909 : LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
910 116764 : if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
911 45787 : unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
912 45787 : unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
913 : assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
914 : "Table isn't big enough!");
915 45787 : return TruncStoreActions[ValI][MemI];
916 : }
917 :
918 : /// Return true if the specified store with truncation is legal on this
919 : /// target.
920 : bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
921 218338 : return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
922 : }
923 :
924 : /// Return true if the specified store with truncation has solution on this
925 : /// target.
926 : bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
927 9912 : return isTypeLegal(ValVT) &&
928 9208 : (getTruncStoreAction(ValVT, MemVT) == Legal ||
929 5220 : getTruncStoreAction(ValVT, MemVT) == Custom);
930 : }
931 :
932 : /// Return how the indexed load should be treated: either it is legal, needs
933 : /// to be promoted to a larger size, needs to be expanded to some other code
934 : /// sequence, or the target has a custom expander for it.
935 : LegalizeAction
936 : getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
937 : assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
938 : "Table isn't big enough!");
939 4083260 : unsigned Ty = (unsigned)VT.SimpleTy;
940 2061122 : return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
941 : }
942 :
943 : /// Return true if the specified indexed load is legal on this target.
944 : bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
945 4122244 : return VT.isSimple() &&
946 6144382 : (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
947 4044276 : getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
948 : }
949 :
950 : /// Return how the indexed store should be treated: either it is legal, needs
951 : /// to be promoted to a larger size, needs to be expanded to some other code
952 : /// sequence, or the target has a custom expander for it.
953 : LegalizeAction
954 : getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
955 : assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
956 : "Table isn't big enough!");
957 6369952 : unsigned Ty = (unsigned)VT.SimpleTy;
958 3198650 : return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
959 : }
960 :
961 : /// Return true if the specified indexed load is legal on this target.
962 : bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
963 6397300 : return VT.isSimple() &&
964 9568602 : (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
965 6342604 : getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
966 : }
967 :
968 : /// Return how the condition code should be treated: either it is legal, needs
969 : /// to be expanded to some other code sequence, or the target has a custom
970 : /// expander for it.
971 : LegalizeAction
972 : getCondCodeAction(ISD::CondCode CC, MVT VT) const {
973 : assert((unsigned)CC < array_lengthof(CondCodeActions) &&
974 : ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
975 : "Table isn't big enough!");
976 : // See setCondCodeAction for how this is encoded.
977 86379 : uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
978 86379 : uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
979 86379 : LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
980 : assert(Action != Promote && "Can't promote condition code!");
981 : return Action;
982 : }
983 :
984 : /// Return true if the specified condition code is legal on this target.
985 : bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
986 : return
987 10458 : getCondCodeAction(CC, VT) == Legal ||
988 1082 : getCondCodeAction(CC, VT) == Custom;
989 : }
990 :
991 : /// If the action for this operation is to promote, this method returns the
992 : /// ValueType to promote to.
993 114907 : MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
994 : assert(getOperationAction(Op, VT) == Promote &&
995 : "This operation isn't promoted!");
996 :
997 : // See if this has an explicit type specified.
998 : std::map<std::pair<unsigned, MVT::SimpleValueType>,
999 : MVT::SimpleValueType>::const_iterator PTTI =
1000 344721 : PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1001 344112 : if (PTTI != PromoteToType.end()) return PTTI->second;
1002 :
1003 : assert((VT.isInteger() || VT.isFloatingPoint()) &&
1004 : "Cannot autopromote this type, add it with AddPromotedToType.");
1005 :
1006 : MVT NVT = VT;
1007 : do {
1008 654 : NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1009 : assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1010 : "Didn't find type to promote to!");
1011 1950 : } while (!isTypeLegal(NVT) ||
1012 1296 : getOperationAction(Op, NVT) == Promote);
1013 609 : return NVT;
1014 : }
1015 :
1016 : /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1017 : /// operations except for the pointer size. If AllowUnknown is true, this
1018 : /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1019 : /// otherwise it will assert.
1020 6833953 : EVT getValueType(const DataLayout &DL, Type *Ty,
1021 : bool AllowUnknown = false) const {
1022 : // Lower scalar pointers to native pointer types.
1023 2208880 : if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1024 4417760 : return getPointerTy(DL, PTy->getAddressSpace());
1025 :
1026 4625073 : if (Ty->isVectorTy()) {
1027 1216214 : VectorType *VTy = cast<VectorType>(Ty);
1028 1216214 : Type *Elm = VTy->getElementType();
1029 : // Lower vectors of pointers to native pointer types.
1030 6866 : if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1031 20598 : EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1032 6866 : Elm = PointerTy.getTypeForEVT(Ty->getContext());
1033 : }
1034 :
1035 : return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1036 1216214 : VTy->getNumElements());
1037 : }
1038 3408859 : return EVT::getEVT(Ty, AllowUnknown);
1039 : }
1040 :
1041 : /// Return the MVT corresponding to this LLVM type. See getValueType.
1042 : MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
1043 : bool AllowUnknown = false) const {
1044 17491 : return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1045 : }
1046 :
1047 : /// Return the desired alignment for ByVal or InAlloca aggregate function
1048 : /// arguments in the caller parameter area. This is the actual alignment, not
1049 : /// its logarithm.
1050 : virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1051 :
1052 : /// Return the type of registers that this ValueType will eventually require.
1053 : MVT getRegisterType(MVT VT) const {
1054 : assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1055 2409785 : return RegisterTypeForVT[VT.SimpleTy];
1056 : }
1057 :
1058 : /// Return the type of registers that this ValueType will eventually require.
1059 1627073 : MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1060 1627073 : if (VT.isSimple()) {
1061 : assert((unsigned)VT.getSimpleVT().SimpleTy <
1062 : array_lengthof(RegisterTypeForVT));
1063 1616533 : return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1064 : }
1065 10540 : if (VT.isVector()) {
1066 2630 : EVT VT1;
1067 2630 : MVT RegisterVT;
1068 : unsigned NumIntermediates;
1069 2630 : (void)getVectorTypeBreakdown(Context, VT, VT1,
1070 : NumIntermediates, RegisterVT);
1071 2630 : return RegisterVT;
1072 : }
1073 7910 : if (VT.isInteger()) {
1074 7910 : return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1075 : }
1076 0 : llvm_unreachable("Unsupported extended type!");
1077 : }
1078 :
1079 : /// Return the number of registers that this ValueType will eventually
1080 : /// require.
1081 : ///
1082 : /// This is one for any types promoted to live in larger registers, but may be
1083 : /// more than one for types (like i64) that are split into pieces. For types
1084 : /// like i140, which are first promoted then expanded, it is the number of
1085 : /// registers needed to hold all the bits of the original type. For an i140
1086 : /// on a 32 bit machine this means 5 registers.
1087 1812122 : unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1088 1812122 : if (VT.isSimple()) {
1089 : assert((unsigned)VT.getSimpleVT().SimpleTy <
1090 : array_lengthof(NumRegistersForVT));
1091 1806091 : return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1092 : }
1093 6031 : if (VT.isVector()) {
1094 3267 : EVT VT1;
1095 3267 : MVT VT2;
1096 : unsigned NumIntermediates;
1097 3267 : return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1098 : }
1099 2764 : if (VT.isInteger()) {
1100 2764 : unsigned BitWidth = VT.getSizeInBits();
1101 2764 : unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1102 2764 : return (BitWidth + RegWidth - 1) / RegWidth;
1103 : }
1104 0 : llvm_unreachable("Unsupported extended type!");
1105 : }
1106 :
1107 : /// Certain combinations of ABIs, Targets and features require that types
1108 : /// are legal for some operations and not for other operations.
1109 : /// For MIPS all vector types must be passed through the integer register set.
1110 7442 : virtual MVT getRegisterTypeForCallingConv(MVT VT) const {
1111 7442 : return getRegisterType(VT);
1112 : }
1113 :
1114 1142632 : virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
1115 : EVT VT) const {
1116 1142632 : return getRegisterType(Context, VT);
1117 : }
1118 :
1119 : /// Certain targets require unusual breakdowns of certain types. For MIPS,
1120 : /// this occurs when a vector type is used, as vector are passed through the
1121 : /// integer register set.
1122 1142632 : virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1123 : EVT VT) const {
1124 1142632 : return getNumRegisters(Context, VT);
1125 : }
1126 :
1127 : /// Certain targets have context senstive alignment requirements, where one
1128 : /// type has the alignment requirement of another type.
1129 643686 : virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1130 : DataLayout DL) const {
1131 643686 : return DL.getABITypeAlignment(ArgTy);
1132 : }
1133 :
1134 : /// If true, then instruction selection should seek to shrink the FP constant
1135 : /// of the specified type to a smaller type in order to save space and / or
1136 : /// reduce runtime.
1137 282 : virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1138 :
1139 : // Return true if it is profitable to reduce the given load node to a smaller
1140 : // type.
1141 : //
1142 : // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
1143 437 : virtual bool shouldReduceLoadWidth(SDNode *Load,
1144 : ISD::LoadExtType ExtTy,
1145 : EVT NewVT) const {
1146 437 : return true;
1147 : }
1148 :
1149 : /// When splitting a value of the specified type into parts, does the Lo
1150 : /// or Hi part come first? This usually follows the endianness, except
1151 : /// for ppcf128, where the Hi part always comes first.
1152 : bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1153 515042 : return DL.isBigEndian() || VT == MVT::ppcf128;
1154 : }
1155 :
1156 : /// If true, the target has custom DAG combine transformations that it can
1157 : /// perform for the specified node.
1158 : bool hasTargetDAGCombine(ISD::NodeType NT) const {
1159 : assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1160 22140776 : return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1161 : }
1162 :
1163 : unsigned getGatherAllAliasesMaxDepth() const {
1164 : return GatherAllAliasesMaxDepth;
1165 : }
1166 :
1167 : /// Returns the size of the platform's va_list object.
1168 0 : virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1169 0 : return getPointerTy(DL).getSizeInBits();
1170 : }
1171 :
1172 : /// \brief Get maximum # of store operations permitted for llvm.memset
1173 : ///
1174 : /// This function returns the maximum number of store operations permitted
1175 : /// to replace a call to llvm.memset. The value is set by the target at the
1176 : /// performance threshold for such a replacement. If OptSize is true,
1177 : /// return the limit for functions that have OptSize attribute.
1178 : unsigned getMaxStoresPerMemset(bool OptSize) const {
1179 21446 : return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1180 : }
1181 :
1182 : /// \brief Get maximum # of store operations permitted for llvm.memcpy
1183 : ///
1184 : /// This function returns the maximum number of store operations permitted
1185 : /// to replace a call to llvm.memcpy. The value is set by the target at the
1186 : /// performance threshold for such a replacement. If OptSize is true,
1187 : /// return the limit for functions that have OptSize attribute.
1188 : unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1189 1420 : return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1190 : }
1191 :
1192 : /// Get maximum # of load operations permitted for memcmp
1193 : ///
1194 : /// This function returns the maximum number of load operations permitted
1195 : /// to replace a call to memcmp. The value is set by the target at the
1196 : /// performance threshold for such a replacement. If OptSize is true,
1197 : /// return the limit for functions that have OptSize attribute.
1198 : unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1199 302 : return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1200 : }
1201 :
1202 : /// \brief Get maximum # of store operations permitted for llvm.memmove
1203 : ///
1204 : /// This function returns the maximum number of store operations permitted
1205 : /// to replace a call to llvm.memmove. The value is set by the target at the
1206 : /// performance threshold for such a replacement. If OptSize is true,
1207 : /// return the limit for functions that have OptSize attribute.
1208 : unsigned getMaxStoresPerMemmove(bool OptSize) const {
1209 83 : return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1210 : }
1211 :
1212 : /// \brief Determine if the target supports unaligned memory accesses.
1213 : ///
1214 : /// This function returns true if the target allows unaligned memory accesses
1215 : /// of the specified type in the given address space. If true, it also returns
1216 : /// whether the unaligned memory access is "fast" in the last argument by
1217 : /// reference. This is used, for example, in situations where an array
1218 : /// copy/move/set is converted to a sequence of store operations. Its use
1219 : /// helps to ensure that such replacements don't generate code that causes an
1220 : /// alignment error (trap) on the target machine.
1221 851 : virtual bool allowsMisalignedMemoryAccesses(EVT,
1222 : unsigned AddrSpace = 0,
1223 : unsigned Align = 1,
1224 : bool * /*Fast*/ = nullptr) const {
1225 851 : return false;
1226 : }
1227 :
1228 : /// Return true if the target supports a memory access of this type for the
1229 : /// given address space and alignment. If the access is allowed, the optional
1230 : /// final parameter returns if the access is also fast (as defined by the
1231 : /// target).
1232 : bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1233 : unsigned AddrSpace = 0, unsigned Alignment = 1,
1234 : bool *Fast = nullptr) const;
1235 :
1236 : /// Returns the target specific optimal type for load and store operations as
1237 : /// a result of memset, memcpy, and memmove lowering.
1238 : ///
1239 : /// If DstAlign is zero that means it's safe to destination alignment can
1240 : /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1241 : /// a need to check it against alignment requirement, probably because the
1242 : /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1243 : /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1244 : /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1245 : /// does not need to be loaded. It returns EVT::Other if the type should be
1246 : /// determined using generic target-independent logic.
1247 131 : virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1248 : unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1249 : bool /*IsMemset*/,
1250 : bool /*ZeroMemset*/,
1251 : bool /*MemcpyStrSrc*/,
1252 : MachineFunction &/*MF*/) const {
1253 131 : return MVT::Other;
1254 : }
1255 :
1256 : /// Returns true if it's safe to use load / store of the specified type to
1257 : /// expand memcpy / memset inline.
1258 : ///
1259 : /// This is mostly true for all types except for some special cases. For
1260 : /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1261 : /// fstpl which also does type conversion. Note the specified type doesn't
1262 : /// have to be legal as the hook is used before type legalization.
1263 361 : virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1264 :
1265 : /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1266 : bool usesUnderscoreSetJmp() const {
1267 : return UseUnderscoreSetJmp;
1268 : }
1269 :
1270 : /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1271 : bool usesUnderscoreLongJmp() const {
1272 : return UseUnderscoreLongJmp;
1273 : }
1274 :
1275 : /// Return lower limit for number of blocks in a jump table.
1276 : unsigned getMinimumJumpTableEntries() const;
1277 :
1278 : /// Return lower limit of the density in a jump table.
1279 : unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1280 :
1281 : /// Return upper limit for number of entries in a jump table.
1282 : /// Zero if no limit.
1283 : unsigned getMaximumJumpTableSize() const;
1284 :
1285 130 : virtual bool isJumpTableRelative() const {
1286 136 : return TM.isPositionIndependent();
1287 : }
1288 :
1289 : /// If a physical register, this specifies the register that
1290 : /// llvm.savestack/llvm.restorestack should save and restore.
1291 : unsigned getStackPointerRegisterToSaveRestore() const {
1292 : return StackPointerRegisterToSaveRestore;
1293 : }
1294 :
1295 : /// If a physical register, this returns the register that receives the
1296 : /// exception address on entry to an EH pad.
1297 : virtual unsigned
1298 0 : getExceptionPointerRegister(const Constant *PersonalityFn) const {
1299 : // 0 is guaranteed to be the NoRegister value on all targets
1300 0 : return 0;
1301 : }
1302 :
1303 : /// If a physical register, this returns the register that receives the
1304 : /// exception typeid on entry to a landing pad.
1305 : virtual unsigned
1306 0 : getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1307 : // 0 is guaranteed to be the NoRegister value on all targets
1308 0 : return 0;
1309 : }
1310 :
1311 0 : virtual bool needsFixedCatchObjects() const {
1312 0 : report_fatal_error("Funclet EH is not implemented for this target");
1313 : }
1314 :
1315 : /// Returns the target's jmp_buf size in bytes (if never set, the default is
1316 : /// 200)
1317 : unsigned getJumpBufSize() const {
1318 : return JumpBufSize;
1319 : }
1320 :
1321 : /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1322 : /// is 0)
1323 : unsigned getJumpBufAlignment() const {
1324 : return JumpBufAlignment;
1325 : }
1326 :
1327 : /// Return the minimum stack alignment of an argument.
1328 : unsigned getMinStackArgumentAlignment() const {
1329 : return MinStackArgumentAlignment;
1330 : }
1331 :
1332 : /// Return the minimum function alignment.
1333 : unsigned getMinFunctionAlignment() const {
1334 : return MinFunctionAlignment;
1335 : }
1336 :
1337 : /// Return the preferred function alignment.
1338 : unsigned getPrefFunctionAlignment() const {
1339 : return PrefFunctionAlignment;
1340 : }
1341 :
1342 : /// Return the preferred loop alignment.
1343 23186 : virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1344 24009 : return PrefLoopAlignment;
1345 : }
1346 :
1347 : /// If the target has a standard location for the stack protector guard,
1348 : /// returns the address of that location. Otherwise, returns nullptr.
1349 : /// DEPRECATED: please override useLoadStackGuardNode and customize
1350 : /// LOAD_STACK_GUARD, or customize @llvm.stackguard().
1351 : virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1352 :
1353 : /// Inserts necessary declarations for SSP (stack protection) purpose.
1354 : /// Should be used only when getIRStackGuard returns nullptr.
1355 : virtual void insertSSPDeclarations(Module &M) const;
1356 :
1357 : /// Return the variable that's previously inserted by insertSSPDeclarations,
1358 : /// if any, otherwise return nullptr. Should be used only when
1359 : /// getIRStackGuard returns nullptr.
1360 : virtual Value *getSDagStackGuard(const Module &M) const;
1361 :
1362 : /// If the target has a standard stack protection check function that
1363 : /// performs validation and error handling, returns the function. Otherwise,
1364 : /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1365 : /// Should be used only when getIRStackGuard returns nullptr.
1366 : virtual Value *getSSPStackGuardCheck(const Module &M) const;
1367 :
1368 : protected:
1369 : Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1370 : bool UseTLS) const;
1371 :
1372 : public:
1373 : /// Returns the target-specific address of the unsafe stack pointer.
1374 : virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1375 :
1376 : /// Returns the name of the symbol used to emit stack probes or the empty
1377 : /// string if not applicable.
1378 0 : virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
1379 0 : return "";
1380 : }
1381 :
1382 : /// Returns true if a cast between SrcAS and DestAS is a noop.
1383 451 : virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1384 451 : return false;
1385 : }
1386 :
1387 : /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1388 : /// are happy to sink it into basic blocks.
1389 198 : virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1390 198 : return isNoopAddrSpaceCast(SrcAS, DestAS);
1391 : }
1392 :
1393 : /// Return true if the pointer arguments to CI should be aligned by aligning
1394 : /// the object whose address is being passed. If so then MinSize is set to the
1395 : /// minimum size the object must be to be aligned and PrefAlign is set to the
1396 : /// preferred alignment.
1397 456729 : virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1398 : unsigned & /*PrefAlign*/) const {
1399 456729 : return false;
1400 : }
1401 :
1402 : //===--------------------------------------------------------------------===//
1403 : /// \name Helpers for TargetTransformInfo implementations
1404 : /// @{
1405 :
1406 : /// Get the ISD node that corresponds to the Instruction class opcode.
1407 : int InstructionOpcodeToISD(unsigned Opcode) const;
1408 :
1409 : /// Estimate the cost of type-legalization and the legalized type.
1410 : std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1411 : Type *Ty) const;
1412 :
1413 : /// @}
1414 :
1415 : //===--------------------------------------------------------------------===//
1416 : /// \name Helpers for atomic expansion.
1417 : /// @{
1418 :
1419 : /// Returns the maximum atomic operation size (in bits) supported by
1420 : /// the backend. Atomic operations greater than this size (as well
1421 : /// as ones that are not naturally aligned), will be expanded by
1422 : /// AtomicExpandPass into an __atomic_* library call.
1423 : unsigned getMaxAtomicSizeInBitsSupported() const {
1424 : return MaxAtomicSizeInBitsSupported;
1425 : }
1426 :
1427 : /// Returns the size of the smallest cmpxchg or ll/sc instruction
1428 : /// the backend supports. Any smaller operations are widened in
1429 : /// AtomicExpandPass.
1430 : ///
1431 : /// Note that *unlike* operations above the maximum size, atomic ops
1432 : /// are still natively supported below the minimum; they just
1433 : /// require a more complex expansion.
1434 : unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1435 :
1436 : /// Whether AtomicExpandPass should automatically insert fences and reduce
1437 : /// ordering for this atomic. This should be true for most architectures with
1438 : /// weak memory ordering. Defaults to false.
1439 2496 : virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1440 2496 : return false;
1441 : }
1442 :
1443 : /// Perform a load-linked operation on Addr, returning a "Value *" with the
1444 : /// corresponding pointee type. This may entail some non-trivial operations to
1445 : /// truncate or reconstruct types that will be illegal in the backend. See
1446 : /// ARMISelLowering for an example implementation.
1447 0 : virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1448 : AtomicOrdering Ord) const {
1449 0 : llvm_unreachable("Load linked unimplemented on this target");
1450 : }
1451 :
1452 : /// Perform a store-conditional operation to Addr. Return the status of the
1453 : /// store. This should be 0 if the store succeeded, non-zero otherwise.
1454 0 : virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1455 : Value *Addr, AtomicOrdering Ord) const {
1456 0 : llvm_unreachable("Store conditional unimplemented on this target");
1457 : }
1458 :
1459 : /// Inserts in the IR a target-specific intrinsic specifying a fence.
1460 : /// It is called by AtomicExpandPass before expanding an
1461 : /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1462 : /// if shouldInsertFencesForAtomic returns true.
1463 : ///
1464 : /// Inst is the original atomic instruction, prior to other expansions that
1465 : /// may be performed.
1466 : ///
1467 : /// This function should either return a nullptr, or a pointer to an IR-level
1468 : /// Instruction*. Even complex fence sequences can be represented by a
1469 : /// single Instruction* through an intrinsic to be lowered later.
1470 : /// Backends should override this method to produce target-specific intrinsic
1471 : /// for their fences.
1472 : /// FIXME: Please note that the default implementation here in terms of
1473 : /// IR-level fences exists for historical/compatibility reasons and is
1474 : /// *unsound* ! Fences cannot, in general, be used to restore sequential
1475 : /// consistency. For example, consider the following example:
1476 : /// atomic<int> x = y = 0;
1477 : /// int r1, r2, r3, r4;
1478 : /// Thread 0:
1479 : /// x.store(1);
1480 : /// Thread 1:
1481 : /// y.store(1);
1482 : /// Thread 2:
1483 : /// r1 = x.load();
1484 : /// r2 = y.load();
1485 : /// Thread 3:
1486 : /// r3 = y.load();
1487 : /// r4 = x.load();
1488 : /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1489 : /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1490 : /// IR-level fences can prevent it.
1491 : /// @{
1492 111 : virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
1493 : AtomicOrdering Ord) const {
1494 111 : if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1495 77 : return Builder.CreateFence(Ord);
1496 : else
1497 : return nullptr;
1498 : }
1499 :
1500 111 : virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1501 : Instruction *Inst,
1502 : AtomicOrdering Ord) const {
1503 111 : if (isAcquireOrStronger(Ord))
1504 88 : return Builder.CreateFence(Ord);
1505 : else
1506 : return nullptr;
1507 : }
1508 : /// @}
1509 :
1510 : // Emits code that executes when the comparison result in the ll/sc
1511 : // expansion of a cmpxchg instruction is such that the store-conditional will
1512 : // not execute. This makes it possible to balance out the load-linked with
1513 : // a dedicated instruction, if desired.
1514 : // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1515 : // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1516 3 : virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1517 :
1518 : /// Returns true if the given (atomic) store should be expanded by the
1519 : /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1520 66 : virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1521 66 : return false;
1522 : }
1523 :
1524 : /// Returns true if arguments should be sign-extended in lib calls.
1525 7743 : virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1526 7743 : return IsSigned;
1527 : }
1528 :
1529 : /// Returns how the given (atomic) load should be expanded by the
1530 : /// IR-level AtomicExpand pass.
1531 80 : virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1532 80 : return AtomicExpansionKind::None;
1533 : }
1534 :
1535 : /// Returns true if the given atomic cmpxchg should be expanded by the
1536 : /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
1537 : /// (through emitLoadLinked() and emitStoreConditional()).
1538 481 : virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1539 481 : return false;
1540 : }
1541 :
1542 : /// Returns how the IR-level AtomicExpand pass should expand the given
1543 : /// AtomicRMW, if at all. Default is to never expand.
1544 613 : virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1545 613 : return AtomicExpansionKind::None;
1546 : }
1547 :
1548 : /// On some platforms, an AtomicRMW that never actually modifies the value
1549 : /// (such as fetch_add of 0) can be turned into a fence followed by an
1550 : /// atomic load. This may sound useless, but it makes it possible for the
1551 : /// processor to keep the cacheline shared, dramatically improving
1552 : /// performance. And such idempotent RMWs are useful for implementing some
1553 : /// kinds of locks, see for example (justification + benchmarks):
1554 : /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1555 : /// This method tries doing that transformation, returning the atomic load if
1556 : /// it succeeds, and nullptr otherwise.
1557 : /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1558 : /// another round of expansion.
1559 : virtual LoadInst *
1560 0 : lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1561 0 : return nullptr;
1562 : }
1563 :
1564 : /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1565 : /// SIGN_EXTEND, or ANY_EXTEND).
1566 756 : virtual ISD::NodeType getExtendForAtomicOps() const {
1567 756 : return ISD::ZERO_EXTEND;
1568 : }
1569 :
1570 : /// @}
1571 :
1572 : /// Returns true if we should normalize
1573 : /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1574 : /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1575 : /// that it saves us from materializing N0 and N1 in an integer register.
1576 : /// Targets that are able to perform and/or on flags should return false here.
1577 42938 : virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1578 : EVT VT) const {
1579 : // If a target has multiple condition registers, then it likely has logical
1580 : // operations on those registers.
1581 42938 : if (hasMultipleConditionRegisters())
1582 : return false;
1583 : // Only do the transform if the value won't be split into multiple
1584 : // registers.
1585 28325 : LegalizeTypeAction Action = getTypeAction(Context, VT);
1586 28325 : return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1587 : Action != TypeSplitVector;
1588 : }
1589 :
1590 : /// Return true if a select of constants (select Cond, C1, C2) should be
1591 : /// transformed into simple math ops with the condition value. For example:
1592 : /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1593 1945 : virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1594 1945 : return false;
1595 : }
1596 :
1597 : //===--------------------------------------------------------------------===//
1598 : // TargetLowering Configuration Methods - These methods should be invoked by
1599 : // the derived class constructor to configure this object for the target.
1600 : //
1601 : protected:
1602 : /// Specify how the target extends the result of integer and floating point
1603 : /// boolean values from i1 to a wider type. See getBooleanContents.
1604 : void setBooleanContents(BooleanContent Ty) {
1605 28042 : BooleanContents = Ty;
1606 28042 : BooleanFloatContents = Ty;
1607 : }
1608 :
1609 : /// Specify how the target extends the result of integer and floating point
1610 : /// boolean values from i1 to a wider type. See getBooleanContents.
1611 : void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1612 : BooleanContents = IntTy;
1613 1087 : BooleanFloatContents = FloatTy;
1614 : }
1615 :
1616 : /// Specify how the target extends the result of a vector boolean value from a
1617 : /// vector of i1 to a wider type. See getBooleanContents.
1618 : void setBooleanVectorContents(BooleanContent Ty) {
1619 27382 : BooleanVectorContents = Ty;
1620 : }
1621 :
1622 : /// Specify the target scheduling preference.
1623 : void setSchedulingPreference(Sched::Preference Pref) {
1624 21182 : SchedPreferenceInfo = Pref;
1625 : }
1626 :
1627 : /// Indicate whether this target prefers to use _setjmp to implement
1628 : /// llvm.setjmp or the version without _. Defaults to false.
1629 : void setUseUnderscoreSetJmp(bool Val) {
1630 9398 : UseUnderscoreSetJmp = Val;
1631 : }
1632 :
1633 : /// Indicate whether this target prefers to use _longjmp to implement
1634 : /// llvm.longjmp or the version without _. Defaults to false.
1635 : void setUseUnderscoreLongJmp(bool Val) {
1636 9398 : UseUnderscoreLongJmp = Val;
1637 : }
1638 :
1639 : /// Indicate the minimum number of blocks to generate jump tables.
1640 : void setMinimumJumpTableEntries(unsigned Val);
1641 :
1642 : /// Indicate the maximum number of entries in jump tables.
1643 : /// Set to zero to generate unlimited jump tables.
1644 : void setMaximumJumpTableSize(unsigned);
1645 :
1646 : /// If set to a physical register, this specifies the register that
1647 : /// llvm.savestack/llvm.restorestack should save and restore.
1648 : void setStackPointerRegisterToSaveRestore(unsigned R) {
1649 25898 : StackPointerRegisterToSaveRestore = R;
1650 : }
1651 :
1652 : /// Tells the code generator that the target has multiple (allocatable)
1653 : /// condition registers that can be used to store the results of comparisons
1654 : /// for use by selects and conditional branches. With multiple condition
1655 : /// registers, the code generator will not aggressively sink comparisons into
1656 : /// the blocks of their users.
1657 : void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1658 3225 : HasMultipleConditionRegisters = hasManyRegs;
1659 : }
1660 :
1661 : /// Tells the code generator that the target has BitExtract instructions.
1662 : /// The code generator will aggressively sink "shift"s into the blocks of
1663 : /// their users if the users will generate "and" instructions which can be
1664 : /// combined with "shift" to BitExtract instructions.
1665 : void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1666 3226 : HasExtractBitsInsn = hasExtractInsn;
1667 : }
1668 :
1669 : /// Tells the code generator not to expand logic operations on comparison
1670 : /// predicates into separate sequences that increase the amount of flow
1671 : /// control.
1672 : void setJumpIsExpensive(bool isExpensive = true);
1673 :
1674 : /// Tells the code generator that this target supports floating point
1675 : /// exceptions and cares about preserving floating point exception behavior.
1676 : void setHasFloatingPointExceptions(bool FPExceptions = true) {
1677 2049 : HasFloatingPointExceptions = FPExceptions;
1678 : }
1679 :
1680 : /// Tells the code generator which bitwidths to bypass.
1681 : void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1682 1908 : BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1683 : }
1684 :
1685 : /// Add the specified register class as an available regclass for the
1686 : /// specified value type. This indicates the selector can handle values of
1687 : /// that class natively.
1688 : void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1689 : assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1690 274454 : RegClassForVT[VT.SimpleTy] = RC;
1691 : }
1692 :
1693 : /// Return the largest legal super-reg register class of the register class
1694 : /// for the specified type and its associated "cost".
1695 : virtual std::pair<const TargetRegisterClass *, uint8_t>
1696 : findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1697 :
1698 : /// Once all of the register classes are added, this allows us to compute
1699 : /// derived properties we expose.
1700 : void computeRegisterProperties(const TargetRegisterInfo *TRI);
1701 :
1702 : /// Indicate that the specified operation does not work with the specified
1703 : /// type and indicate what to do about it. Note that VT may refer to either
1704 : /// the type of a result or that of an operand of Op.
1705 : void setOperationAction(unsigned Op, MVT VT,
1706 : LegalizeAction Action) {
1707 : assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1708 167259733 : OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1709 : }
1710 :
1711 : /// Indicate that the specified load with extension does not work with the
1712 : /// specified type and indicate what to do about it.
1713 : void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1714 : LegalizeAction Action) {
1715 : assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1716 : MemVT.isValid() && "Table isn't big enough!");
1717 : assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1718 397059212 : unsigned Shift = 4 * ExtType;
1719 397059212 : LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1720 395076812 : LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1721 : }
1722 :
1723 : /// Indicate that the specified truncating store does not work with the
1724 : /// specified type and indicate what to do about it.
1725 : void setTruncStoreAction(MVT ValVT, MVT MemVT,
1726 : LegalizeAction Action) {
1727 : assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1728 146739937 : TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1729 : }
1730 :
1731 : /// Indicate that the specified indexed load does or does not work with the
1732 : /// specified type and indicate what to do abort it.
1733 : ///
1734 : /// NOTE: All indexed mode loads are initialized to Expand in
1735 : /// TargetLowering.cpp
1736 : void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1737 : LegalizeAction Action) {
1738 : assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1739 : (unsigned)Action < 0xf && "Table isn't big enough!");
1740 : // Load action are kept in the upper half.
1741 12832248 : IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1742 99144 : IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1743 : }
1744 :
1745 : /// Indicate that the specified indexed store does or does not work with the
1746 : /// specified type and indicate what to do about it.
1747 : ///
1748 : /// NOTE: All indexed mode stores are initialized to Expand in
1749 : /// TargetLowering.cpp
1750 : void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1751 : LegalizeAction Action) {
1752 : assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1753 : (unsigned)Action < 0xf && "Table isn't big enough!");
1754 : // Store action are kept in the lower half.
1755 99016 : IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1756 12842269 : IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1757 : }
1758 :
1759 : /// Indicate that the specified condition code is or isn't supported on the
1760 : /// target and indicate what to do about it.
1761 : void setCondCodeAction(ISD::CondCode CC, MVT VT,
1762 : LegalizeAction Action) {
1763 : assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1764 : "Table isn't big enough!");
1765 : assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1766 : /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1767 : /// value and the upper 29 bits index into the second dimension of the array
1768 : /// to select what 32-bit value to use.
1769 104728 : uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1770 104728 : CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1771 104728 : CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1772 : }
1773 :
1774 : /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1775 : /// to trying a larger integer/fp until it can find one that works. If that
1776 : /// default is insufficient, this method can be used by the target to override
1777 : /// the default.
1778 : void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1779 1967176 : PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1780 : }
1781 :
1782 : /// Convenience method to set an operation to Promote and specify the type
1783 : /// in a single call.
1784 : void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1785 155375 : setOperationAction(Opc, OrigVT, Promote);
1786 155375 : AddPromotedToType(Opc, OrigVT, DestVT);
1787 : }
1788 :
1789 : /// Targets should invoke this method for each target independent node that
1790 : /// they want to provide a custom DAG combiner for by implementing the
1791 : /// PerformDAGCombine virtual method.
1792 : void setTargetDAGCombine(ISD::NodeType NT) {
1793 : assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1794 623210 : TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1795 : }
1796 :
1797 : /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1798 : void setJumpBufSize(unsigned Size) {
1799 : JumpBufSize = Size;
1800 : }
1801 :
1802 : /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1803 : /// 0
1804 : void setJumpBufAlignment(unsigned Align) {
1805 : JumpBufAlignment = Align;
1806 : }
1807 :
1808 : /// Set the target's minimum function alignment (in log2(bytes))
1809 : void setMinFunctionAlignment(unsigned Align) {
1810 17878 : MinFunctionAlignment = Align;
1811 : }
1812 :
1813 : /// Set the target's preferred function alignment. This should be set if
1814 : /// there is a performance benefit to higher-than-minimum alignment (in
1815 : /// log2(bytes))
1816 : void setPrefFunctionAlignment(unsigned Align) {
1817 10908 : PrefFunctionAlignment = Align;
1818 : }
1819 :
1820 : /// Set the target's preferred loop alignment. Default alignment is zero, it
1821 : /// means the target does not care about loop alignment. The alignment is
1822 : /// specified in log2(bytes). The target may also override
1823 : /// getPrefLoopAlignment to provide per-loop values.
1824 : void setPrefLoopAlignment(unsigned Align) {
1825 10533 : PrefLoopAlignment = Align;
1826 : }
1827 :
1828 : /// Set the minimum stack alignment of an argument (in log2(bytes)).
1829 : void setMinStackArgumentAlignment(unsigned Align) {
1830 14737 : MinStackArgumentAlignment = Align;
1831 : }
1832 :
1833 : /// Set the maximum atomic operation size supported by the
1834 : /// backend. Atomic operations greater than this size (as well as
1835 : /// ones that are not naturally aligned), will be expanded by
1836 : /// AtomicExpandPass into an __atomic_* library call.
1837 : void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1838 854 : MaxAtomicSizeInBitsSupported = SizeInBits;
1839 : }
1840 :
1841 : // Sets the minimum cmpxchg or ll/sc size supported by the backend.
1842 : void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1843 854 : MinCmpXchgSizeInBits = SizeInBits;
1844 : }
1845 :
1846 : public:
1847 : //===--------------------------------------------------------------------===//
1848 : // Addressing mode description hooks (used by LSR etc).
1849 : //
1850 :
1851 : /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1852 : /// instructions reading the address. This allows as much computation as
1853 : /// possible to be done in the address mode for that operand. This hook lets
1854 : /// targets also pass back when this should be done on intrinsics which
1855 : /// load/store.
1856 199552 : virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
1857 : SmallVectorImpl<Value*> &/*Ops*/,
1858 : Type *&/*AccessTy*/) const {
1859 199552 : return false;
1860 : }
1861 :
1862 : /// This represents an addressing mode of:
1863 : /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1864 : /// If BaseGV is null, there is no BaseGV.
1865 : /// If BaseOffs is zero, there is no base offset.
1866 : /// If HasBaseReg is false, there is no base register.
1867 : /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1868 : /// no scale.
1869 : struct AddrMode {
1870 : GlobalValue *BaseGV = nullptr;
1871 : int64_t BaseOffs = 0;
1872 : bool HasBaseReg = false;
1873 : int64_t Scale = 0;
1874 : AddrMode() = default;
1875 : };
1876 :
1877 : /// Return true if the addressing mode represented by AM is legal for this
1878 : /// target, for a load/store of the specified type.
1879 : ///
1880 : /// The type may be VoidTy, in which case only return true if the addressing
1881 : /// mode is legal for a load/store of any legal type. TODO: Handle
1882 : /// pre/postinc as well.
1883 : ///
1884 : /// If the address space cannot be determined, it will be -1.
1885 : ///
1886 : /// TODO: Remove default argument
1887 : virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1888 : Type *Ty, unsigned AddrSpace,
1889 : Instruction *I = nullptr) const;
1890 :
1891 : /// \brief Return the cost of the scaling factor used in the addressing mode
1892 : /// represented by AM for this target, for a load/store of the specified type.
1893 : ///
1894 : /// If the AM is supported, the return value must be >= 0.
1895 : /// If the AM is not supported, it returns a negative value.
1896 : /// TODO: Handle pre/postinc as well.
1897 : /// TODO: Remove default argument
1898 6084 : virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
1899 : Type *Ty, unsigned AS = 0) const {
1900 : // Default: assume that any scaling factor used in a legal AM is free.
1901 6084 : if (isLegalAddressingMode(DL, AM, Ty, AS))
1902 : return 0;
1903 0 : return -1;
1904 : }
1905 :
1906 : /// Return true if the specified immediate is legal icmp immediate, that is
1907 : /// the target has icmp instructions which can compare a register against the
1908 : /// immediate without having to materialize the immediate into a register.
1909 32481 : virtual bool isLegalICmpImmediate(int64_t) const {
1910 32481 : return true;
1911 : }
1912 :
1913 : /// Return true if the specified immediate is legal add immediate, that is the
1914 : /// target has add instructions which can add a register with the immediate
1915 : /// without having to materialize the immediate into a register.
1916 1117 : virtual bool isLegalAddImmediate(int64_t) const {
1917 1117 : return true;
1918 : }
1919 :
1920 : /// Return true if it's significantly cheaper to shift a vector by a uniform
1921 : /// scalar than by an amount which will vary across each lane. On x86, for
1922 : /// example, there is a "psllw" instruction for the former case, but no simple
1923 : /// instruction for a general "a << b" operation on vectors.
1924 4949 : virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1925 4949 : return false;
1926 : }
1927 :
1928 : /// Returns true if the opcode is a commutative binary operation.
1929 32763917 : virtual bool isCommutativeBinOp(unsigned Opcode) const {
1930 : // FIXME: This should get its info from the td file.
1931 32763917 : switch (Opcode) {
1932 : case ISD::ADD:
1933 : case ISD::SMIN:
1934 : case ISD::SMAX:
1935 : case ISD::UMIN:
1936 : case ISD::UMAX:
1937 : case ISD::MUL:
1938 : case ISD::MULHU:
1939 : case ISD::MULHS:
1940 : case ISD::SMUL_LOHI:
1941 : case ISD::UMUL_LOHI:
1942 : case ISD::FADD:
1943 : case ISD::FMUL:
1944 : case ISD::AND:
1945 : case ISD::OR:
1946 : case ISD::XOR:
1947 : case ISD::SADDO:
1948 : case ISD::UADDO:
1949 : case ISD::ADDC:
1950 : case ISD::ADDE:
1951 : case ISD::FMINNUM:
1952 : case ISD::FMAXNUM:
1953 : case ISD::FMINNAN:
1954 : case ISD::FMAXNAN:
1955 : return true;
1956 27141599 : default: return false;
1957 : }
1958 : }
1959 :
1960 : /// Return true if it's free to truncate a value of type FromTy to type
1961 : /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1962 : /// by referencing its sub-register AX.
1963 : /// Targets must return false when FromTy <= ToTy.
1964 487 : virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
1965 487 : return false;
1966 : }
1967 :
1968 : /// Return true if a truncation from FromTy to ToTy is permitted when deciding
1969 : /// whether a call is in tail position. Typically this means that both results
1970 : /// would be assigned to the same register or stack slot, but it could mean
1971 : /// the target performs adequate checks of its own before proceeding with the
1972 : /// tail call. Targets must return false when FromTy <= ToTy.
1973 2 : virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
1974 2 : return false;
1975 : }
1976 :
1977 6895 : virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
1978 6895 : return false;
1979 : }
1980 :
1981 3362 : virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1982 :
1983 : /// Return true if the extension represented by \p I is free.
1984 : /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1985 : /// this method can use the context provided by \p I to decide
1986 : /// whether or not \p I is free.
1987 : /// This method extends the behavior of the is[Z|FP]ExtFree family.
1988 : /// In other words, if is[Z|FP]Free returns true, then this method
1989 : /// returns true as well. The converse is not true.
1990 : /// The target can perform the adequate checks by overriding isExtFreeImpl.
1991 : /// \pre \p I must be a sign, zero, or fp extension.
1992 18415 : bool isExtFree(const Instruction *I) const {
1993 18415 : switch (I->getOpcode()) {
1994 31 : case Instruction::FPExt:
1995 31 : if (isFPExtFree(EVT::getEVT(I->getType())))
1996 : return true;
1997 : break;
1998 15847 : case Instruction::ZExt:
1999 31694 : if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2000 : return true;
2001 : break;
2002 : case Instruction::SExt:
2003 : break;
2004 0 : default:
2005 0 : llvm_unreachable("Instruction is not an extension");
2006 : }
2007 13866 : return isExtFreeImpl(I);
2008 : }
2009 :
2010 : /// Return true if \p Load and \p Ext can form an ExtLoad.
2011 : /// For example, in AArch64
2012 : /// %L = load i8, i8* %ptr
2013 : /// %E = zext i8 %L to i32
2014 : /// can be lowered into one load instruction
2015 : /// ldrb w0, [x0]
2016 4856 : bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2017 : const DataLayout &DL) const {
2018 4856 : EVT VT = getValueType(DL, Ext->getType());
2019 4856 : EVT LoadVT = getValueType(DL, Load->getType());
2020 :
2021 : // If the load has other users and the truncate is not free, the ext
2022 : // probably isn't free.
2023 12111 : if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2024 2371 : !isTruncateFree(Ext->getType(), Load->getType()))
2025 : return false;
2026 :
2027 : // Check whether the target supports casts folded into loads.
2028 : unsigned LType;
2029 9712 : if (isa<ZExtInst>(Ext))
2030 : LType = ISD::ZEXTLOAD;
2031 : else {
2032 : assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2033 777 : LType = ISD::SEXTLOAD;
2034 : }
2035 :
2036 9712 : return isLoadExtLegal(LType, VT, LoadVT);
2037 : }
2038 :
2039 : /// Return true if any actual instruction that defines a value of type FromTy
2040 : /// implicitly zero-extends the value to ToTy in the result register.
2041 : ///
2042 : /// The function should return true when it is likely that the truncate can
2043 : /// be freely folded with an instruction defining a value of FromTy. If
2044 : /// the defining instruction is unknown (because you're looking at a
2045 : /// function argument, PHI, etc.) then the target may require an
2046 : /// explicit truncate, which is not necessarily free, but this function
2047 : /// does not deal with those cases.
2048 : /// Targets must return false when FromTy >= ToTy.
2049 167 : virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2050 167 : return false;
2051 : }
2052 :
2053 11877 : virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2054 11877 : return false;
2055 : }
2056 :
2057 : /// Return true if the target supplies and combines to a paired load
2058 : /// two loaded values of type LoadedType next to each other in memory.
2059 : /// RequiredAlignment gives the minimal alignment constraints that must be met
2060 : /// to be able to select this paired load.
2061 : ///
2062 : /// This information is *not* used to generate actual paired loads, but it is
2063 : /// used to generate a sequence of loads that is easier to combine into a
2064 : /// paired load.
2065 : /// For instance, something like this:
2066 : /// a = load i64* addr
2067 : /// b = trunc i64 a to i32
2068 : /// c = lshr i64 a, 32
2069 : /// d = trunc i64 c to i32
2070 : /// will be optimized into:
2071 : /// b = load i32* addr1
2072 : /// d = load i32* addr2
2073 : /// Where addr1 = addr2 +/- sizeof(i32).
2074 : ///
2075 : /// In other words, unless the target performs a post-isel load combining,
2076 : /// this information should not be provided because it will generate more
2077 : /// loads.
2078 2770 : virtual bool hasPairedLoad(EVT /*LoadedType*/,
2079 : unsigned & /*RequiredAlignment*/) const {
2080 2770 : return false;
2081 : }
2082 :
2083 : /// \brief Get the maximum supported factor for interleaved memory accesses.
2084 : /// Default to be the minimum interleave factor: 2.
2085 0 : virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2086 :
2087 : /// \brief Lower an interleaved load to target specific intrinsics. Return
2088 : /// true on success.
2089 : ///
2090 : /// \p LI is the vector load instruction.
2091 : /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2092 : /// \p Indices is the corresponding indices for each shufflevector.
2093 : /// \p Factor is the interleave factor.
2094 0 : virtual bool lowerInterleavedLoad(LoadInst *LI,
2095 : ArrayRef<ShuffleVectorInst *> Shuffles,
2096 : ArrayRef<unsigned> Indices,
2097 : unsigned Factor) const {
2098 0 : return false;
2099 : }
2100 :
2101 : /// \brief Lower an interleaved store to target specific intrinsics. Return
2102 : /// true on success.
2103 : ///
2104 : /// \p SI is the vector store instruction.
2105 : /// \p SVI is the shufflevector to RE-interleave the stored vector.
2106 : /// \p Factor is the interleave factor.
2107 0 : virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
2108 : unsigned Factor) const {
2109 0 : return false;
2110 : }
2111 :
2112 : /// Return true if zero-extending the specific node Val to type VT2 is free
2113 : /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2114 : /// because it's folded such as X86 zero-extending loads).
2115 8168 : virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2116 21358 : return isZExtFree(Val.getValueType(), VT2);
2117 : }
2118 :
2119 : /// Return true if an fpext operation is free (for instance, because
2120 : /// single-precision floating-point numbers are implicitly extended to
2121 : /// double-precision).
2122 7130 : virtual bool isFPExtFree(EVT VT) const {
2123 : assert(VT.isFloatingPoint());
2124 7130 : return false;
2125 : }
2126 :
2127 : /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2128 : /// extend node) is profitable.
2129 2754 : virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2130 :
2131 : /// Return true if an fneg operation is free to the point where it is never
2132 : /// worthwhile to replace it with a bitwise operation.
2133 1535 : virtual bool isFNegFree(EVT VT) const {
2134 : assert(VT.isFloatingPoint());
2135 1535 : return false;
2136 : }
2137 :
2138 : /// Return true if an fabs operation is free to the point where it is never
2139 : /// worthwhile to replace it with a bitwise operation.
2140 536 : virtual bool isFAbsFree(EVT VT) const {
2141 : assert(VT.isFloatingPoint());
2142 536 : return false;
2143 : }
2144 :
2145 : /// Return true if an FMA operation is faster than a pair of fmul and fadd
2146 : /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2147 : /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2148 : ///
2149 : /// NOTE: This may be called before legalization on types for which FMAs are
2150 : /// not legal, but should return true if those types will eventually legalize
2151 : /// to types that support FMAs. After legalization, it will only be called on
2152 : /// types that support FMAs (via Legal or Custom actions)
2153 4679 : virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2154 4679 : return false;
2155 : }
2156 :
2157 : /// Return true if it's profitable to narrow operations of type VT1 to
2158 : /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2159 : /// i32 to i16.
2160 194 : virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2161 194 : return false;
2162 : }
2163 :
2164 : /// \brief Return true if it is beneficial to convert a load of a constant to
2165 : /// just the constant itself.
2166 : /// On some targets it might be more efficient to use a combination of
2167 : /// arithmetic instructions to materialize the constant instead of loading it
2168 : /// from a constant pool.
2169 12 : virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2170 : Type *Ty) const {
2171 12 : return false;
2172 : }
2173 :
2174 : /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2175 : /// from this source type with this index. This is needed because
2176 : /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2177 : /// the first element, and only the target knows which lowering is cheap.
2178 44 : virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2179 : unsigned Index) const {
2180 44 : return false;
2181 : }
2182 :
2183 : // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2184 : // even if the vector itself has multiple uses.
2185 619 : virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2186 619 : return false;
2187 : }
2188 :
2189 : //===--------------------------------------------------------------------===//
2190 : // Runtime Library hooks
2191 : //
2192 :
2193 : /// Rename the default libcall routine name for the specified libcall.
2194 : void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2195 1224829 : LibcallRoutineNames[Call] = Name;
2196 : }
2197 :
2198 : /// Get the libcall routine name for the specified libcall.
2199 : const char *getLibcallName(RTLIB::Libcall Call) const {
2200 24264 : return LibcallRoutineNames[Call];
2201 : }
2202 :
2203 : /// Override the default CondCode to be used to test the result of the
2204 : /// comparison libcall against zero.
2205 : void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
2206 54656 : CmpLibcallCCs[Call] = CC;
2207 : }
2208 :
2209 : /// Get the CondCode that's to be used to test the result of the comparison
2210 : /// libcall against zero.
2211 : ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
2212 302 : return CmpLibcallCCs[Call];
2213 : }
2214 :
2215 : /// Set the CallingConv that should be used for the specified libcall.
2216 : void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
2217 1830256 : LibcallCallingConvs[Call] = CC;
2218 : }
2219 :
2220 : /// Get the CallingConv that should be used for the specified libcall.
2221 : CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
2222 9128 : return LibcallCallingConvs[Call];
2223 : }
2224 :
2225 : /// Execute target specific actions to finalize target lowering.
2226 : /// This is used to set extra flags in MachineFrameInformation and freezing
2227 : /// the set of reserved registers.
2228 : /// The default implementation just freezes the set of reserved registers.
2229 : virtual void finalizeLowering(MachineFunction &MF) const;
2230 :
2231 : private:
2232 : const TargetMachine &TM;
2233 :
2234 : /// Tells the code generator that the target has multiple (allocatable)
2235 : /// condition registers that can be used to store the results of comparisons
2236 : /// for use by selects and conditional branches. With multiple condition
2237 : /// registers, the code generator will not aggressively sink comparisons into
2238 : /// the blocks of their users.
2239 : bool HasMultipleConditionRegisters;
2240 :
2241 : /// Tells the code generator that the target has BitExtract instructions.
2242 : /// The code generator will aggressively sink "shift"s into the blocks of
2243 : /// their users if the users will generate "and" instructions which can be
2244 : /// combined with "shift" to BitExtract instructions.
2245 : bool HasExtractBitsInsn;
2246 :
2247 : /// Tells the code generator to bypass slow divide or remainder
2248 : /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2249 : /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2250 : /// div/rem when the operands are positive and less than 256.
2251 : DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2252 :
2253 : /// Tells the code generator that it shouldn't generate extra flow control
2254 : /// instructions and should attempt to combine flow control instructions via
2255 : /// predication.
2256 : bool JumpIsExpensive;
2257 :
2258 : /// Whether the target supports or cares about preserving floating point
2259 : /// exception behavior.
2260 : bool HasFloatingPointExceptions;
2261 :
2262 : /// This target prefers to use _setjmp to implement llvm.setjmp.
2263 : ///
2264 : /// Defaults to false.
2265 : bool UseUnderscoreSetJmp;
2266 :
2267 : /// This target prefers to use _longjmp to implement llvm.longjmp.
2268 : ///
2269 : /// Defaults to false.
2270 : bool UseUnderscoreLongJmp;
2271 :
2272 : /// Information about the contents of the high-bits in boolean values held in
2273 : /// a type wider than i1. See getBooleanContents.
2274 : BooleanContent BooleanContents;
2275 :
2276 : /// Information about the contents of the high-bits in boolean values held in
2277 : /// a type wider than i1. See getBooleanContents.
2278 : BooleanContent BooleanFloatContents;
2279 :
2280 : /// Information about the contents of the high-bits in boolean vector values
2281 : /// when the element type is wider than i1. See getBooleanContents.
2282 : BooleanContent BooleanVectorContents;
2283 :
2284 : /// The target scheduling preference: shortest possible total cycles or lowest
2285 : /// register usage.
2286 : Sched::Preference SchedPreferenceInfo;
2287 :
2288 : /// The size, in bytes, of the target's jmp_buf buffers
2289 : unsigned JumpBufSize;
2290 :
2291 : /// The alignment, in bytes, of the target's jmp_buf buffers
2292 : unsigned JumpBufAlignment;
2293 :
2294 : /// The minimum alignment that any argument on the stack needs to have.
2295 : unsigned MinStackArgumentAlignment;
2296 :
2297 : /// The minimum function alignment (used when optimizing for size, and to
2298 : /// prevent explicitly provided alignment from leading to incorrect code).
2299 : unsigned MinFunctionAlignment;
2300 :
2301 : /// The preferred function alignment (used when alignment unspecified and
2302 : /// optimizing for speed).
2303 : unsigned PrefFunctionAlignment;
2304 :
2305 : /// The preferred loop alignment.
2306 : unsigned PrefLoopAlignment;
2307 :
2308 : /// Size in bits of the maximum atomics size the backend supports.
2309 : /// Accesses larger than this will be expanded by AtomicExpandPass.
2310 : unsigned MaxAtomicSizeInBitsSupported;
2311 :
2312 : /// Size in bits of the minimum cmpxchg or ll/sc operation the
2313 : /// backend supports.
2314 : unsigned MinCmpXchgSizeInBits;
2315 :
2316 : /// If set to a physical register, this specifies the register that
2317 : /// llvm.savestack/llvm.restorestack should save and restore.
2318 : unsigned StackPointerRegisterToSaveRestore;
2319 :
2320 : /// This indicates the default register class to use for each ValueType the
2321 : /// target supports natively.
2322 : const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2323 : unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2324 : MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2325 :
2326 : /// This indicates the "representative" register class to use for each
2327 : /// ValueType the target supports natively. This information is used by the
2328 : /// scheduler to track register pressure. By default, the representative
2329 : /// register class is the largest legal super-reg register class of the
2330 : /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2331 : /// representative class would be GR32.
2332 : const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2333 :
2334 : /// This indicates the "cost" of the "representative" register class for each
2335 : /// ValueType. The cost is used by the scheduler to approximate register
2336 : /// pressure.
2337 : uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2338 :
2339 : /// For any value types we are promoting or expanding, this contains the value
2340 : /// type that we are changing to. For Expanded types, this contains one step
2341 : /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2342 : /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2343 : /// the same type (e.g. i32 -> i32).
2344 : MVT TransformToType[MVT::LAST_VALUETYPE];
2345 :
2346 : /// For each operation and each value type, keep a LegalizeAction that
2347 : /// indicates how instruction selection should deal with the operation. Most
2348 : /// operations are Legal (aka, supported natively by the target), but
2349 : /// operations that are not should be described. Note that operations on
2350 : /// non-legal value types are not described here.
2351 : LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2352 :
2353 : /// For each load extension type and each value type, keep a LegalizeAction
2354 : /// that indicates how instruction selection should deal with a load of a
2355 : /// specific value type and extension type. Uses 4-bits to store the action
2356 : /// for each of the 4 load ext types.
2357 : uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2358 :
2359 : /// For each value type pair keep a LegalizeAction that indicates whether a
2360 : /// truncating store of a specific value type and truncating type is legal.
2361 : LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2362 :
2363 : /// For each indexed mode and each value type, keep a pair of LegalizeAction
2364 : /// that indicates how instruction selection should deal with the load /
2365 : /// store.
2366 : ///
2367 : /// The first dimension is the value_type for the reference. The second
2368 : /// dimension represents the various modes for load store.
2369 : uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2370 :
2371 : /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2372 : /// indicates how instruction selection should deal with the condition code.
2373 : ///
2374 : /// Because each CC action takes up 4 bits, we need to have the array size be
2375 : /// large enough to fit all of the value types. This can be done by rounding
2376 : /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2377 : uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2378 :
2379 : protected:
2380 : ValueTypeActionImpl ValueTypeActions;
2381 :
2382 : private:
2383 : LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2384 :
2385 : /// Targets can specify ISD nodes that they would like PerformDAGCombine
2386 : /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2387 : /// array.
2388 : unsigned char
2389 : TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2390 :
2391 : /// For operations that must be promoted to a specific type, this holds the
2392 : /// destination type. This map should be sparse, so don't hold it as an
2393 : /// array.
2394 : ///
2395 : /// Targets add entries to this map with AddPromotedToType(..), clients access
2396 : /// this with getTypeToPromoteTo(..).
2397 : std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2398 : PromoteToType;
2399 :
2400 : /// Stores the name each libcall.
2401 : const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
2402 :
2403 : /// The ISD::CondCode that should be used to test the result of each of the
2404 : /// comparison libcall against zero.
2405 : ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2406 :
2407 : /// Stores the CallingConv that should be used for each libcall.
2408 : CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2409 :
2410 : protected:
2411 : /// Return true if the extension represented by \p I is free.
2412 : /// \pre \p I is a sign, zero, or fp extension and
2413 : /// is[Z|FP]ExtFree of the related types is not true.
2414 13461 : virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2415 :
2416 : /// Depth that GatherAllAliases should should continue looking for chain
2417 : /// dependencies when trying to find a more preferable chain. As an
2418 : /// approximation, this should be more than the number of consecutive stores
2419 : /// expected to be merged.
2420 : unsigned GatherAllAliasesMaxDepth;
2421 :
2422 : /// \brief Specify maximum number of store instructions per memset call.
2423 : ///
2424 : /// When lowering \@llvm.memset this field specifies the maximum number of
2425 : /// store operations that may be substituted for the call to memset. Targets
2426 : /// must set this value based on the cost threshold for that target. Targets
2427 : /// should assume that the memset will be done using as many of the largest
2428 : /// store operations first, followed by smaller ones, if necessary, per
2429 : /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2430 : /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2431 : /// store. This only applies to setting a constant array of a constant size.
2432 : unsigned MaxStoresPerMemset;
2433 :
2434 : /// Maximum number of stores operations that may be substituted for the call
2435 : /// to memset, used for functions with OptSize attribute.
2436 : unsigned MaxStoresPerMemsetOptSize;
2437 :
2438 : /// \brief Specify maximum bytes of store instructions per memcpy call.
2439 : ///
2440 : /// When lowering \@llvm.memcpy this field specifies the maximum number of
2441 : /// store operations that may be substituted for a call to memcpy. Targets
2442 : /// must set this value based on the cost threshold for that target. Targets
2443 : /// should assume that the memcpy will be done using as many of the largest
2444 : /// store operations first, followed by smaller ones, if necessary, per
2445 : /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2446 : /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2447 : /// and one 1-byte store. This only applies to copying a constant array of
2448 : /// constant size.
2449 : unsigned MaxStoresPerMemcpy;
2450 :
2451 : /// Maximum number of store operations that may be substituted for a call to
2452 : /// memcpy, used for functions with OptSize attribute.
2453 : unsigned MaxStoresPerMemcpyOptSize;
2454 : unsigned MaxLoadsPerMemcmp;
2455 : unsigned MaxLoadsPerMemcmpOptSize;
2456 :
2457 : /// \brief Specify maximum bytes of store instructions per memmove call.
2458 : ///
2459 : /// When lowering \@llvm.memmove this field specifies the maximum number of
2460 : /// store instructions that may be substituted for a call to memmove. Targets
2461 : /// must set this value based on the cost threshold for that target. Targets
2462 : /// should assume that the memmove will be done using as many of the largest
2463 : /// store operations first, followed by smaller ones, if necessary, per
2464 : /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2465 : /// with 8-bit alignment would result in nine 1-byte stores. This only
2466 : /// applies to copying a constant array of constant size.
2467 : unsigned MaxStoresPerMemmove;
2468 :
2469 : /// Maximum number of store instructions that may be substituted for a call to
2470 : /// memmove, used for functions with OptSize attribute.
2471 : unsigned MaxStoresPerMemmoveOptSize;
2472 :
2473 : /// Tells the code generator that select is more expensive than a branch if
2474 : /// the branch is usually predicted right.
2475 : bool PredictableSelectIsExpensive;
2476 :
2477 : /// \see enableExtLdPromotion.
2478 : bool EnableExtLdPromotion;
2479 :
2480 : /// Return true if the value types that can be represented by the specified
2481 : /// register class are all legal.
2482 : bool isLegalRC(const TargetRegisterInfo &TRI,
2483 : const TargetRegisterClass &RC) const;
2484 :
2485 : /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2486 : /// sequence of memory operands that is recognized by PrologEpilogInserter.
2487 : MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2488 : MachineBasicBlock *MBB) const;
2489 : };
2490 :
2491 : /// This class defines information used to lower LLVM code to legal SelectionDAG
2492 : /// operators that the target instruction selector can accept natively.
2493 : ///
2494 : /// This class also defines callbacks that targets must implement to lower
2495 : /// target-specific constructs to SelectionDAG operators.
2496 27997 : class TargetLowering : public TargetLoweringBase {
2497 : public:
2498 : struct DAGCombinerInfo;
2499 :
2500 : TargetLowering(const TargetLowering &) = delete;
2501 : TargetLowering &operator=(const TargetLowering &) = delete;
2502 :
2503 : /// NOTE: The TargetMachine owns TLOF.
2504 : explicit TargetLowering(const TargetMachine &TM);
2505 :
2506 : bool isPositionIndependent() const;
2507 :
2508 : /// Returns true by value, base pointer and offset pointer and addressing mode
2509 : /// by reference if the node's address can be legally represented as
2510 : /// pre-indexed load / store address.
2511 0 : virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2512 : SDValue &/*Offset*/,
2513 : ISD::MemIndexedMode &/*AM*/,
2514 : SelectionDAG &/*DAG*/) const {
2515 0 : return false;
2516 : }
2517 :
2518 : /// Returns true by value, base pointer and offset pointer and addressing mode
2519 : /// by reference if this node can be combined with a load / store to form a
2520 : /// post-indexed load / store.
2521 0 : virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2522 : SDValue &/*Base*/,
2523 : SDValue &/*Offset*/,
2524 : ISD::MemIndexedMode &/*AM*/,
2525 : SelectionDAG &/*DAG*/) const {
2526 0 : return false;
2527 : }
2528 :
2529 : /// Return the entry encoding for a jump table in the current function. The
2530 : /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2531 : virtual unsigned getJumpTableEncoding() const;
2532 :
2533 : virtual const MCExpr *
2534 0 : LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2535 : const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2536 : MCContext &/*Ctx*/) const {
2537 0 : llvm_unreachable("Need to implement this hook if target has custom JTIs");
2538 : }
2539 :
2540 : /// Returns relocation base for the given PIC jumptable.
2541 : virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2542 : SelectionDAG &DAG) const;
2543 :
2544 : /// This returns the relocation base for the given PIC jumptable, the same as
2545 : /// getPICJumpTableRelocBase, but as an MCExpr.
2546 : virtual const MCExpr *
2547 : getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2548 : unsigned JTI, MCContext &Ctx) const;
2549 :
2550 : /// Return true if folding a constant offset with the given GlobalAddress is
2551 : /// legal. It is frequently not legal in PIC relocation models.
2552 : virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2553 :
2554 : bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2555 : SDValue &Chain) const;
2556 :
2557 : void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2558 : SDValue &NewRHS, ISD::CondCode &CCCode,
2559 : const SDLoc &DL) const;
2560 :
2561 : /// Returns a pair of (return value, chain).
2562 : /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2563 : std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2564 : EVT RetVT, ArrayRef<SDValue> Ops,
2565 : bool isSigned, const SDLoc &dl,
2566 : bool doesNotReturn = false,
2567 : bool isReturnValueUsed = true) const;
2568 :
2569 : /// Check whether parameters to a call that are passed in callee saved
2570 : /// registers are the same as from the calling function. This needs to be
2571 : /// checked for tail call eligibility.
2572 : bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2573 : const uint32_t *CallerPreservedMask,
2574 : const SmallVectorImpl<CCValAssign> &ArgLocs,
2575 : const SmallVectorImpl<SDValue> &OutVals) const;
2576 :
2577 : //===--------------------------------------------------------------------===//
2578 : // TargetLowering Optimization Methods
2579 : //
2580 :
2581 : /// A convenience struct that encapsulates a DAG, and two SDValues for
2582 : /// returning information from TargetLowering to its clients that want to
2583 : /// combine.
2584 : struct TargetLoweringOpt {
2585 : SelectionDAG &DAG;
2586 : bool LegalTys;
2587 : bool LegalOps;
2588 : SDValue Old;
2589 : SDValue New;
2590 :
2591 : explicit TargetLoweringOpt(SelectionDAG &InDAG,
2592 2474652 : bool LT, bool LO) :
2593 7423956 : DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2594 :
2595 : bool LegalTypes() const { return LegalTys; }
2596 : bool LegalOperations() const { return LegalOps; }
2597 :
2598 : bool CombineTo(SDValue O, SDValue N) {
2599 83119 : Old = O;
2600 83119 : New = N;
2601 : return true;
2602 : }
2603 : };
2604 :
2605 : /// Check to see if the specified operand of the specified instruction is a
2606 : /// constant integer. If so, check to see if there are any bits set in the
2607 : /// constant that are not demanded. If so, shrink the constant and return
2608 : /// true.
2609 : bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2610 : TargetLoweringOpt &TLO) const;
2611 :
2612 : // Target hook to do target-specific const optimization, which is called by
2613 : // ShrinkDemandedConstant. This function should return true if the target
2614 : // doesn't want ShrinkDemandedConstant to further optimize the constant.
2615 491492 : virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2616 : TargetLoweringOpt &TLO) const {
2617 491492 : return false;
2618 : }
2619 :
2620 : /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2621 : /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2622 : /// generalized for targets with other types of implicit widening casts.
2623 : bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2624 : TargetLoweringOpt &TLO) const;
2625 :
2626 : /// Helper for SimplifyDemandedBits that can simplify an operation with
2627 : /// multiple uses. This function simplifies operand \p OpIdx of \p User and
2628 : /// then updates \p User with the simplified version. No other uses of
2629 : /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2630 : /// function behaves exactly like function SimplifyDemandedBits declared
2631 : /// below except that it also updates the DAG by calling
2632 : /// DCI.CommitTargetLoweringOpt.
2633 : bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2634 : DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2635 :
2636 : /// Look at Op. At this point, we know that only the DemandedMask bits of the
2637 : /// result of Op are ever used downstream. If we can use this information to
2638 : /// simplify Op, create a new simplified DAG node and return true, returning
2639 : /// the original and new nodes in Old and New. Otherwise, analyze the
2640 : /// expression and return a mask of KnownOne and KnownZero bits for the
2641 : /// expression (used to simplify the caller). The KnownZero/One bits may only
2642 : /// be accurate for those bits in the DemandedMask.
2643 : /// \p AssumeSingleUse When this parameter is true, this function will
2644 : /// attempt to simplify \p Op even if there are multiple uses.
2645 : /// Callers are responsible for correctly updating the DAG based on the
2646 : /// results of this function, because simply replacing replacing TLO.Old
2647 : /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2648 : /// has multiple uses.
2649 : bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2650 : KnownBits &Known,
2651 : TargetLoweringOpt &TLO,
2652 : unsigned Depth = 0,
2653 : bool AssumeSingleUse = false) const;
2654 :
2655 : /// Helper wrapper around SimplifyDemandedBits
2656 : bool SimplifyDemandedBits(SDValue Op, APInt &DemandedMask,
2657 : DAGCombinerInfo &DCI) const;
2658 :
2659 : /// Determine which of the bits specified in Mask are known to be either zero
2660 : /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2661 : /// argument allows us to only collect the known bits that are shared by the
2662 : /// requested vector elements.
2663 : virtual void computeKnownBitsForTargetNode(const SDValue Op,
2664 : KnownBits &Known,
2665 : const APInt &DemandedElts,
2666 : const SelectionDAG &DAG,
2667 : unsigned Depth = 0) const;
2668 :
2669 : /// This method can be implemented by targets that want to expose additional
2670 : /// information about sign bits to the DAG Combiner. The DemandedElts
2671 : /// argument allows us to only collect the minimum sign bits that are shared
2672 : /// by the requested vector elements.
2673 : virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2674 : const APInt &DemandedElts,
2675 : const SelectionDAG &DAG,
2676 : unsigned Depth = 0) const;
2677 :
2678 : struct DAGCombinerInfo {
2679 : void *DC; // The DAG Combiner object.
2680 : CombineLevel Level;
2681 : bool CalledByLegalizer;
2682 :
2683 : public:
2684 : SelectionDAG &DAG;
2685 :
2686 : DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2687 9646370 : : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2688 :
2689 : bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2690 557339 : bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2691 : bool isAfterLegalizeVectorOps() const {
2692 : return Level == AfterLegalizeDAG;
2693 : }
2694 : CombineLevel getDAGCombineLevel() { return Level; }
2695 : bool isCalledByLegalizer() const { return CalledByLegalizer; }
2696 :
2697 : void AddToWorklist(SDNode *N);
2698 : SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2699 : SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2700 : SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2701 :
2702 : void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2703 : };
2704 :
2705 : /// Return if the N is a constant or constant vector equal to the true value
2706 : /// from getBooleanContents().
2707 : bool isConstTrueVal(const SDNode *N) const;
2708 :
2709 : /// Return if the N is a constant or constant vector equal to the false value
2710 : /// from getBooleanContents().
2711 : bool isConstFalseVal(const SDNode *N) const;
2712 :
2713 : /// Return a constant of type VT that contains a true value that respects
2714 : /// getBooleanContents()
2715 : SDValue getConstTrueVal(SelectionDAG &DAG, EVT VT, const SDLoc &DL) const;
2716 :
2717 : /// Return if \p N is a True value when extended to \p VT.
2718 : bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
2719 :
2720 : /// Try to simplify a setcc built with the specified operands and cc. If it is
2721 : /// unable to simplify it, return a null SDValue.
2722 : SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2723 : bool foldBooleans, DAGCombinerInfo &DCI,
2724 : const SDLoc &dl) const;
2725 :
2726 : // For targets which wrap address, unwrap for analysis.
2727 2297062 : virtual SDValue unwrapAddress(SDValue N) const { return N; }
2728 :
2729 : /// Returns true (and the GlobalValue and the offset) if the node is a
2730 : /// GlobalAddress + offset.
2731 : virtual bool
2732 : isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2733 :
2734 : /// This method will be invoked for all target nodes and for any
2735 : /// target-independent nodes that the target has registered with invoke it
2736 : /// for.
2737 : ///
2738 : /// The semantics are as follows:
2739 : /// Return Value:
2740 : /// SDValue.Val == 0 - No change was made
2741 : /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2742 : /// otherwise - N should be replaced by the returned Operand.
2743 : ///
2744 : /// In addition, methods provided by DAGCombinerInfo may be used to perform
2745 : /// more complex transformations.
2746 : ///
2747 : virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2748 :
2749 : /// Return true if it is profitable to move a following shift through this
2750 : // node, adjusting any immediate operands as necessary to preserve semantics.
2751 : // This transformation may not be desirable if it disrupts a particularly
2752 : // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2753 : // By default, it returns true.
2754 702 : virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
2755 702 : return true;
2756 : }
2757 :
2758 : // Return true if it is profitable to combine a BUILD_VECTOR to a TRUNCATE.
2759 : // Example of such a combine:
2760 : // v4i32 build_vector((extract_elt V, 0),
2761 : // (extract_elt V, 2),
2762 : // (extract_elt V, 4),
2763 : // (extract_elt V, 6))
2764 : // -->
2765 : // v4i32 truncate (bitcast V to v4i64)
2766 113426 : virtual bool isDesirableToCombineBuildVectorToTruncate() const {
2767 113426 : return false;
2768 : }
2769 :
2770 : // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
2771 : // to a shuffle and a truncate.
2772 : // Example of such a combine:
2773 : // v4i32 build_vector((extract_elt V, 1),
2774 : // (extract_elt V, 3),
2775 : // (extract_elt V, 5),
2776 : // (extract_elt V, 7))
2777 : // -->
2778 : // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
2779 0 : virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
2780 : ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
2781 0 : return false;
2782 : }
2783 :
2784 : /// Return true if the target has native support for the specified value type
2785 : /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2786 : /// i16 is legal, but undesirable since i16 instruction encodings are longer
2787 : /// and some i16 instructions are slow.
2788 230496 : virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2789 : // By default, assume all legal types are desirable.
2790 682904 : return isTypeLegal(VT);
2791 : }
2792 :
2793 : /// Return true if it is profitable for dag combiner to transform a floating
2794 : /// point op of specified opcode to a equivalent op of an integer
2795 : /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2796 251 : virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2797 : EVT /*VT*/) const {
2798 251 : return false;
2799 : }
2800 :
2801 : /// This method query the target whether it is beneficial for dag combiner to
2802 : /// promote the specified node. If true, it should return the desired
2803 : /// promotion type by reference.
2804 2170 : virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2805 2170 : return false;
2806 : }
2807 :
2808 : /// Return true if the target supports swifterror attribute. It optimizes
2809 : /// loads and stores to reading and writing a specific register.
2810 313550 : virtual bool supportSwiftError() const {
2811 313550 : return false;
2812 : }
2813 :
2814 : /// Return true if the target supports that a subset of CSRs for the given
2815 : /// machine function is handled explicitly via copies.
2816 23714 : virtual bool supportSplitCSR(MachineFunction *MF) const {
2817 23714 : return false;
2818 : }
2819 :
2820 : /// Perform necessary initialization to handle a subset of CSRs explicitly
2821 : /// via copies. This function is called at the beginning of instruction
2822 : /// selection.
2823 0 : virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
2824 0 : llvm_unreachable("Not Implemented");
2825 : }
2826 :
2827 : /// Insert explicit copies in entry and exit blocks. We copy a subset of
2828 : /// CSRs to virtual registers in the entry block, and copy them back to
2829 : /// physical registers in the exit blocks. This function is called at the end
2830 : /// of instruction selection.
2831 0 : virtual void insertCopiesSplitCSR(
2832 : MachineBasicBlock *Entry,
2833 : const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
2834 0 : llvm_unreachable("Not Implemented");
2835 : }
2836 :
2837 : //===--------------------------------------------------------------------===//
2838 : // Lowering methods - These methods must be implemented by targets so that
2839 : // the SelectionDAGBuilder code knows how to lower these.
2840 : //
2841 :
2842 : /// This hook must be implemented to lower the incoming (formal) arguments,
2843 : /// described by the Ins array, into the specified DAG. The implementation
2844 : /// should fill in the InVals array with legal-type argument values, and
2845 : /// return the resulting token chain value.
2846 0 : virtual SDValue LowerFormalArguments(
2847 : SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
2848 : const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
2849 : SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
2850 0 : llvm_unreachable("Not Implemented");
2851 : }
2852 :
2853 : /// This structure contains all information that is necessary for lowering
2854 : /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2855 : /// needs to lower a call, and targets will see this struct in their LowerCall
2856 : /// implementation.
2857 1322230 : struct CallLoweringInfo {
2858 : SDValue Chain;
2859 : Type *RetTy = nullptr;
2860 : bool RetSExt : 1;
2861 : bool RetZExt : 1;
2862 : bool IsVarArg : 1;
2863 : bool IsInReg : 1;
2864 : bool DoesNotReturn : 1;
2865 : bool IsReturnValueUsed : 1;
2866 : bool IsConvergent : 1;
2867 : bool IsPatchPoint : 1;
2868 :
2869 : // IsTailCall should be modified by implementations of
2870 : // TargetLowering::LowerCall that perform tail call conversions.
2871 : bool IsTailCall = false;
2872 :
2873 : // Is Call lowering done post SelectionDAG type legalization.
2874 : bool IsPostTypeLegalization = false;
2875 :
2876 : unsigned NumFixedArgs = -1;
2877 : CallingConv::ID CallConv = CallingConv::C;
2878 : SDValue Callee;
2879 : ArgListTy Args;
2880 : SelectionDAG &DAG;
2881 : SDLoc DL;
2882 : ImmutableCallSite CS;
2883 : SmallVector<ISD::OutputArg, 32> Outs;
2884 : SmallVector<SDValue, 32> OutVals;
2885 : SmallVector<ISD::InputArg, 32> Ins;
2886 : SmallVector<SDValue, 4> InVals;
2887 :
2888 188896 : CallLoweringInfo(SelectionDAG &DAG)
2889 188896 : : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
2890 : DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
2891 1888960 : IsPatchPoint(false), DAG(DAG) {}
2892 :
2893 : CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
2894 377764 : DL = dl;
2895 : return *this;
2896 : }
2897 :
2898 : CallLoweringInfo &setChain(SDValue InChain) {
2899 215594 : Chain = InChain;
2900 : return *this;
2901 : }
2902 :
2903 : // setCallee with target/module-specific attributes
2904 6883 : CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
2905 : SDValue Target, ArgListTy &&ArgsList) {
2906 6883 : RetTy = ResultType;
2907 6883 : Callee = Target;
2908 6883 : CallConv = CC;
2909 13766 : NumFixedArgs = Args.size();
2910 13766 : Args = std::move(ArgsList);
2911 :
2912 13766 : DAG.getTargetLoweringInfo().markLibCallAttributes(
2913 6883 : &(DAG.getMachineFunction()), CC, Args);
2914 6883 : return *this;
2915 : }
2916 :
2917 : CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2918 : SDValue Target, ArgListTy &&ArgsList) {
2919 543 : RetTy = ResultType;
2920 543 : Callee = Target;
2921 543 : CallConv = CC;
2922 1086 : NumFixedArgs = Args.size();
2923 1086 : Args = std::move(ArgsList);
2924 : return *this;
2925 : }
2926 :
2927 181470 : CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2928 : SDValue Target, ArgListTy &&ArgsList,
2929 : ImmutableCallSite Call) {
2930 181470 : RetTy = ResultType;
2931 :
2932 181470 : IsInReg = Call.hasRetAttr(Attribute::InReg);
2933 181470 : DoesNotReturn =
2934 181470 : Call.doesNotReturn() ||
2935 146881 : (!Call.isInvoke() &&
2936 475232 : isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
2937 181470 : IsVarArg = FTy->isVarArg();
2938 362940 : IsReturnValueUsed = !Call.getInstruction()->use_empty();
2939 181470 : RetSExt = Call.hasRetAttr(Attribute::SExt);
2940 181470 : RetZExt = Call.hasRetAttr(Attribute::ZExt);
2941 :
2942 181470 : Callee = Target;
2943 :
2944 181470 : CallConv = Call.getCallingConv();
2945 362940 : NumFixedArgs = FTy->getNumParams();
2946 362940 : Args = std::move(ArgsList);
2947 :
2948 181470 : CS = Call;
2949 :
2950 181470 : return *this;
2951 : }
2952 :
2953 : CallLoweringInfo &setInRegister(bool Value = true) {
2954 193 : IsInReg = Value;
2955 : return *this;
2956 : }
2957 :
2958 : CallLoweringInfo &setNoReturn(bool Value = true) {
2959 2716 : DoesNotReturn = Value;
2960 : return *this;
2961 : }
2962 :
2963 : CallLoweringInfo &setVarArg(bool Value = true) {
2964 : IsVarArg = Value;
2965 : return *this;
2966 : }
2967 :
2968 : CallLoweringInfo &setTailCall(bool Value = true) {
2969 184808 : IsTailCall = Value;
2970 : return *this;
2971 : }
2972 :
2973 : CallLoweringInfo &setDiscardResult(bool Value = true) {
2974 4534 : IsReturnValueUsed = !Value;
2975 : return *this;
2976 : }
2977 :
2978 : CallLoweringInfo &setConvergent(bool Value = true) {
2979 181470 : IsConvergent = Value;
2980 : return *this;
2981 : }
2982 :
2983 : CallLoweringInfo &setSExtResult(bool Value = true) {
2984 5146 : RetSExt = Value;
2985 : return *this;
2986 : }
2987 :
2988 : CallLoweringInfo &setZExtResult(bool Value = true) {
2989 5137 : RetZExt = Value;
2990 : return *this;
2991 : }
2992 :
2993 : CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2994 185 : IsPatchPoint = Value;
2995 : return *this;
2996 : }
2997 :
2998 : CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
2999 1860 : IsPostTypeLegalization = Value;
3000 : return *this;
3001 : }
3002 :
3003 : ArgListTy &getArgs() {
3004 4101 : return Args;
3005 : }
3006 : };
3007 :
3008 : /// This function lowers an abstract call to a function into an actual call.
3009 : /// This returns a pair of operands. The first element is the return value
3010 : /// for the function (if RetTy is not VoidTy). The second element is the
3011 : /// outgoing token chain. It calls LowerCall to do the actual lowering.
3012 : std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3013 :
3014 : /// This hook must be implemented to lower calls into the specified
3015 : /// DAG. The outgoing arguments to the call are described by the Outs array,
3016 : /// and the values to be returned by the call are described by the Ins
3017 : /// array. The implementation should fill in the InVals array with legal-type
3018 : /// return values from the call, and return the resulting token chain value.
3019 : virtual SDValue
3020 0 : LowerCall(CallLoweringInfo &/*CLI*/,
3021 : SmallVectorImpl<SDValue> &/*InVals*/) const {
3022 0 : llvm_unreachable("Not Implemented");
3023 : }
3024 :
3025 : /// Target-specific cleanup for formal ByVal parameters.
3026 969 : virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3027 :
3028 : /// This hook should be implemented to check whether the return values
3029 : /// described by the Outs array can fit into the return registers. If false
3030 : /// is returned, an sret-demotion is performed.
3031 4967 : virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3032 : MachineFunction &/*MF*/, bool /*isVarArg*/,
3033 : const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3034 : LLVMContext &/*Context*/) const
3035 : {
3036 : // Return true by default to get preexisting behavior.
3037 4967 : return true;
3038 : }
3039 :
3040 : /// This hook must be implemented to lower outgoing return values, described
3041 : /// by the Outs array, into the specified DAG. The implementation should
3042 : /// return the resulting token chain value.
3043 0 : virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3044 : bool /*isVarArg*/,
3045 : const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3046 : const SmallVectorImpl<SDValue> & /*OutVals*/,
3047 : const SDLoc & /*dl*/,
3048 : SelectionDAG & /*DAG*/) const {
3049 0 : llvm_unreachable("Not Implemented");
3050 : }
3051 :
3052 : /// Return true if result of the specified node is used by a return node
3053 : /// only. It also compute and return the input chain for the tail call.
3054 : ///
3055 : /// This is used to determine whether it is possible to codegen a libcall as
3056 : /// tail call at legalization time.
3057 336 : virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3058 336 : return false;
3059 : }
3060 :
3061 : /// Return true if the target may be able emit the call instruction as a tail
3062 : /// call. This is used by optimization passes to determine if it's profitable
3063 : /// to duplicate return instructions to enable tailcall optimization.
3064 302 : virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3065 302 : return false;
3066 : }
3067 :
3068 : /// Return the builtin name for the __builtin___clear_cache intrinsic
3069 : /// Default is to invoke the clear cache library call
3070 2 : virtual const char * getClearCacheBuiltinName() const {
3071 2 : return "__clear_cache";
3072 : }
3073 :
3074 : /// Return the register ID of the name passed in. Used by named register
3075 : /// global variables extension. There is no target-independent behaviour
3076 : /// so the default action is to bail.
3077 0 : virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3078 : SelectionDAG &DAG) const {
3079 0 : report_fatal_error("Named registers not implemented for this target");
3080 : }
3081 :
3082 : /// Return the type that should be used to zero or sign extend a
3083 : /// zeroext/signext integer return value. FIXME: Some C calling conventions
3084 : /// require the return type to be promoted, but this is not true all the time,
3085 : /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3086 : /// conventions. The frontend should handle this and include all of the
3087 : /// necessary information.
3088 4054 : virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
3089 : ISD::NodeType /*ExtendKind*/) const {
3090 12162 : EVT MinVT = getRegisterType(Context, MVT::i32);
3091 4054 : return VT.bitsLT(MinVT) ? MinVT : VT;
3092 : }
3093 :
3094 : /// For some targets, an LLVM struct type must be broken down into multiple
3095 : /// simple types, but the calling convention specifies that the entire struct
3096 : /// must be passed in a block of consecutive registers.
3097 : virtual bool
3098 593424 : functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
3099 : bool isVarArg) const {
3100 593424 : return false;
3101 : }
3102 :
3103 : /// Returns a 0 terminated array of registers that can be safely used as
3104 : /// scratch registers.
3105 0 : virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3106 0 : return nullptr;
3107 : }
3108 :
3109 : /// This callback is used to prepare for a volatile or atomic load.
3110 : /// It takes a chain node as input and returns the chain for the load itself.
3111 : ///
3112 : /// Having a callback like this is necessary for targets like SystemZ,
3113 : /// which allows a CPU to reuse the result of a previous load indefinitely,
3114 : /// even if a cache-coherent store is performed by another CPU. The default
3115 : /// implementation does nothing.
3116 9207 : virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
3117 : SelectionDAG &DAG) const {
3118 9207 : return Chain;
3119 : }
3120 :
3121 : /// This callback is used to inspect load/store instructions and add
3122 : /// target-specific MachineMemOperand flags to them. The default
3123 : /// implementation does nothing.
3124 547519 : virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
3125 547519 : return MachineMemOperand::MONone;
3126 : }
3127 :
3128 : /// This callback is invoked by the type legalizer to legalize nodes with an
3129 : /// illegal operand type but legal result types. It replaces the
3130 : /// LowerOperation callback in the type Legalizer. The reason we can not do
3131 : /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3132 : /// use this callback.
3133 : ///
3134 : /// TODO: Consider merging with ReplaceNodeResults.
3135 : ///
3136 : /// The target places new result values for the node in Results (their number
3137 : /// and types must exactly match those of the original return values of
3138 : /// the node), or leaves Results empty, which indicates that the node is not
3139 : /// to be custom lowered after all.
3140 : /// The default implementation calls LowerOperation.
3141 : virtual void LowerOperationWrapper(SDNode *N,
3142 : SmallVectorImpl<SDValue> &Results,
3143 : SelectionDAG &DAG) const;
3144 :
3145 : /// This callback is invoked for operations that are unsupported by the
3146 : /// target, which are registered to use 'custom' lowering, and whose defined
3147 : /// values are all legal. If the target has no operations that require custom
3148 : /// lowering, it need not implement this. The default implementation of this
3149 : /// aborts.
3150 : virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3151 :
3152 : /// This callback is invoked when a node result type is illegal for the
3153 : /// target, and the operation was registered to use 'custom' lowering for that
3154 : /// result type. The target places new result values for the node in Results
3155 : /// (their number and types must exactly match those of the original return
3156 : /// values of the node), or leaves Results empty, which indicates that the
3157 : /// node is not to be custom lowered after all.
3158 : ///
3159 : /// If the target has no operations that require custom lowering, it need not
3160 : /// implement this. The default implementation aborts.
3161 0 : virtual void ReplaceNodeResults(SDNode * /*N*/,
3162 : SmallVectorImpl<SDValue> &/*Results*/,
3163 : SelectionDAG &/*DAG*/) const {
3164 0 : llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3165 : }
3166 :
3167 : /// This method returns the name of a target specific DAG node.
3168 : virtual const char *getTargetNodeName(unsigned Opcode) const;
3169 :
3170 : /// This method returns a target specific FastISel object, or null if the
3171 : /// target does not support "fast" ISel.
3172 2456 : virtual FastISel *createFastISel(FunctionLoweringInfo &,
3173 : const TargetLibraryInfo *) const {
3174 2456 : return nullptr;
3175 : }
3176 :
3177 : bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3178 : SelectionDAG &DAG) const;
3179 :
3180 : //===--------------------------------------------------------------------===//
3181 : // Inline Asm Support hooks
3182 : //
3183 :
3184 : /// This hook allows the target to expand an inline asm call to be explicit
3185 : /// llvm code if it wants to. This is useful for turning simple inline asms
3186 : /// into LLVM intrinsics, which gives the compiler more information about the
3187 : /// behavior of the code.
3188 2364 : virtual bool ExpandInlineAsm(CallInst *) const {
3189 2364 : return false;
3190 : }
3191 :
3192 : enum ConstraintType {
3193 : C_Register, // Constraint represents specific register(s).
3194 : C_RegisterClass, // Constraint represents any of register(s) in class.
3195 : C_Memory, // Memory constraint.
3196 : C_Other, // Something else.
3197 : C_Unknown // Unsupported constraint.
3198 : };
3199 :
3200 : enum ConstraintWeight {
3201 : // Generic weights.
3202 : CW_Invalid = -1, // No match.
3203 : CW_Okay = 0, // Acceptable.
3204 : CW_Good = 1, // Good weight.
3205 : CW_Better = 2, // Better weight.
3206 : CW_Best = 3, // Best weight.
3207 :
3208 : // Well-known weights.
3209 : CW_SpecificReg = CW_Okay, // Specific register operands.
3210 : CW_Register = CW_Good, // Register operands.
3211 : CW_Memory = CW_Better, // Memory operands.
3212 : CW_Constant = CW_Best, // Constant operand.
3213 : CW_Default = CW_Okay // Default or don't know type.
3214 : };
3215 :
3216 : /// This contains information for each constraint that we are lowering.
3217 2372388 : struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3218 : /// This contains the actual string for the code, like "m". TargetLowering
3219 : /// picks the 'best' code from ConstraintInfo::Codes that most closely
3220 : /// matches the operand.
3221 : std::string ConstraintCode;
3222 :
3223 : /// Information about the constraint code, e.g. Register, RegisterClass,
3224 : /// Memory, Other, Unknown.
3225 : TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
3226 :
3227 : /// If this is the result output operand or a clobber, this is null,
3228 : /// otherwise it is the incoming operand to the CallInst. This gets
3229 : /// modified as the asm is processed.
3230 : Value *CallOperandVal = nullptr;
3231 :
3232 : /// The ValueType for the operand value.
3233 : MVT ConstraintVT = MVT::Other;
3234 :
3235 : /// Copy constructor for copying from a ConstraintInfo.
3236 : AsmOperandInfo(InlineAsm::ConstraintInfo Info)
3237 494238 : : InlineAsm::ConstraintInfo(std::move(Info)) {}
3238 :
3239 : /// Return true of this is an input operand that is a matching constraint
3240 : /// like "4".
3241 : bool isMatchingInputConstraint() const;
3242 :
3243 : /// If this is an input matching constraint, this method returns the output
3244 : /// operand it matches.
3245 : unsigned getMatchedOperand() const;
3246 : };
3247 :
3248 : using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3249 :
3250 : /// Split up the constraint string from the inline assembly value into the
3251 : /// specific constraints and their prefixes, and also tie in the associated
3252 : /// operand values. If this returns an empty vector, and if the constraint
3253 : /// string itself isn't empty, there was an error parsing.
3254 : virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3255 : const TargetRegisterInfo *TRI,
3256 : ImmutableCallSite CS) const;
3257 :
3258 : /// Examine constraint type and operand type and determine a weight value.
3259 : /// The operand object must already have been set up with the operand type.
3260 : virtual ConstraintWeight getMultipleConstraintMatchWeight(
3261 : AsmOperandInfo &info, int maIndex) const;
3262 :
3263 : /// Examine constraint string and operand type and determine a weight value.
3264 : /// The operand object must already have been set up with the operand type.
3265 : virtual ConstraintWeight getSingleConstraintMatchWeight(
3266 : AsmOperandInfo &info, const char *constraint) const;
3267 :
3268 : /// Determines the constraint code and constraint type to use for the specific
3269 : /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3270 : /// If the actual operand being passed in is available, it can be passed in as
3271 : /// Op, otherwise an empty SDValue can be passed.
3272 : virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3273 : SDValue Op,
3274 : SelectionDAG *DAG = nullptr) const;
3275 :
3276 : /// Given a constraint, return the type of constraint it is for this target.
3277 : virtual ConstraintType getConstraintType(StringRef Constraint) const;
3278 :
3279 : /// Given a physical register constraint (e.g. {edx}), return the register
3280 : /// number and the register class for the register.
3281 : ///
3282 : /// Given a register class constraint, like 'r', if this corresponds directly
3283 : /// to an LLVM register class, return a register of 0 and the register class
3284 : /// pointer.
3285 : ///
3286 : /// This should only be used for C_Register constraints. On error, this
3287 : /// returns a register number of 0 and a null register class pointer.
3288 : virtual std::pair<unsigned, const TargetRegisterClass *>
3289 : getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3290 : StringRef Constraint, MVT VT) const;
3291 :
3292 12 : virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3293 328 : if (ConstraintCode == "i")
3294 : return InlineAsm::Constraint_i;
3295 656 : else if (ConstraintCode == "m")
3296 : return InlineAsm::Constraint_m;
3297 : return InlineAsm::Constraint_Unknown;
3298 : }
3299 :
3300 : /// Try to replace an X constraint, which matches anything, with another that
3301 : /// has more specific requirements based on the type of the corresponding
3302 : /// operand. This returns null if there is no replacement to make.
3303 : virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3304 :
3305 : /// Lower the specified operand into the Ops vector. If it is invalid, don't
3306 : /// add anything to Ops.
3307 : virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3308 : std::vector<SDValue> &Ops,
3309 : SelectionDAG &DAG) const;
3310 :
3311 : //===--------------------------------------------------------------------===//
3312 : // Div utility functions
3313 : //
3314 : SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3315 : bool IsAfterLegalization,
3316 : std::vector<SDNode *> *Created) const;
3317 : SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3318 : bool IsAfterLegalization,
3319 : std::vector<SDNode *> *Created) const;
3320 :
3321 : /// Targets may override this function to provide custom SDIV lowering for
3322 : /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3323 : /// assumes SDIV is expensive and replaces it with a series of other integer
3324 : /// operations.
3325 : virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3326 : SelectionDAG &DAG,
3327 : std::vector<SDNode *> *Created) const;
3328 :
3329 : /// Indicate whether this target prefers to combine FDIVs with the same
3330 : /// divisor. If the transform should never be done, return zero. If the
3331 : /// transform should be done, return the minimum number of divisor uses
3332 : /// that must exist.
3333 240 : virtual unsigned combineRepeatedFPDivisors() const {
3334 240 : return 0;
3335 : }
3336 :
3337 : /// Hooks for building estimates in place of slower divisions and square
3338 : /// roots.
3339 :
3340 : /// Return either a square root or its reciprocal estimate value for the input
3341 : /// operand.
3342 : /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3343 : /// 'Enabled' as set by a potential default override attribute.
3344 : /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3345 : /// refinement iterations required to generate a sufficient (though not
3346 : /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3347 : /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3348 : /// algorithm implementation that uses either one or two constants.
3349 : /// The boolean Reciprocal is used to select whether the estimate is for the
3350 : /// square root of the input operand or the reciprocal of its square root.
3351 : /// A target may choose to implement its own refinement within this function.
3352 : /// If that's true, then return '0' as the number of RefinementSteps to avoid
3353 : /// any further refinement of the estimate.
3354 : /// An empty SDValue return means no estimate sequence can be created.
3355 0 : virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
3356 : int Enabled, int &RefinementSteps,
3357 : bool &UseOneConstNR, bool Reciprocal) const {
3358 0 : return SDValue();
3359 : }
3360 :
3361 : /// Return a reciprocal estimate value for the input operand.
3362 : /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3363 : /// 'Enabled' as set by a potential default override attribute.
3364 : /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3365 : /// refinement iterations required to generate a sufficient (though not
3366 : /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3367 : /// A target may choose to implement its own refinement within this function.
3368 : /// If that's true, then return '0' as the number of RefinementSteps to avoid
3369 : /// any further refinement of the estimate.
3370 : /// An empty SDValue return means no estimate sequence can be created.
3371 35 : virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
3372 : int Enabled, int &RefinementSteps) const {
3373 35 : return SDValue();
3374 : }
3375 :
3376 : //===--------------------------------------------------------------------===//
3377 : // Legalization utility functions
3378 : //
3379 :
3380 : /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3381 : /// respectively, each computing an n/2-bit part of the result.
3382 : /// \param Result A vector that will be filled with the parts of the result
3383 : /// in little-endian order.
3384 : /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3385 : /// if you want to control how low bits are extracted from the LHS.
3386 : /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3387 : /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3388 : /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3389 : /// \returns true if the node has been expanded, false if it has not
3390 : bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3391 : SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3392 : SelectionDAG &DAG, MulExpansionKind Kind,
3393 : SDValue LL = SDValue(), SDValue LH = SDValue(),
3394 : SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3395 :
3396 : /// Expand a MUL into two nodes. One that computes the high bits of
3397 : /// the result and one that computes the low bits.
3398 : /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3399 : /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3400 : /// if you want to control how low bits are extracted from the LHS.
3401 : /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3402 : /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3403 : /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3404 : /// \returns true if the node has been expanded. false if it has not
3405 : bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3406 : SelectionDAG &DAG, MulExpansionKind Kind,
3407 : SDValue LL = SDValue(), SDValue LH = SDValue(),
3408 : SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3409 :
3410 : /// Expand float(f32) to SINT(i64) conversion
3411 : /// \param N Node to expand
3412 : /// \param Result output after conversion
3413 : /// \returns True, if the expansion was successful, false otherwise
3414 : bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3415 :
3416 : /// Turn load of vector type into a load of the individual elements.
3417 : /// \param LD load to expand
3418 : /// \returns MERGE_VALUEs of the scalar loads with their chains.
3419 : SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3420 :
3421 : // Turn a store of a vector type into stores of the individual elements.
3422 : /// \param ST Store with a vector value type
3423 : /// \returns MERGE_VALUs of the individual store chains.
3424 : SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3425 :
3426 : /// Expands an unaligned load to 2 half-size loads for an integer, and
3427 : /// possibly more for vectors.
3428 : std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3429 : SelectionDAG &DAG) const;
3430 :
3431 : /// Expands an unaligned store to 2 half-size stores for integer values, and
3432 : /// possibly more for vectors.
3433 : SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3434 :
3435 : /// Increments memory address \p Addr according to the type of the value
3436 : /// \p DataVT that should be stored. If the data is stored in compressed
3437 : /// form, the memory address should be incremented according to the number of
3438 : /// the stored elements. This number is equal to the number of '1's bits
3439 : /// in the \p Mask.
3440 : /// \p DataVT is a vector type. \p Mask is a vector value.
3441 : /// \p DataVT and \p Mask have the same number of vector elements.
3442 : SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3443 : EVT DataVT, SelectionDAG &DAG,
3444 : bool IsCompressedMemory) const;
3445 :
3446 : /// Get a pointer to vector element \p Idx located in memory for a vector of
3447 : /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3448 : /// bounds the returned pointer is unspecified, but will be within the vector
3449 : /// bounds.
3450 : SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3451 : SDValue Idx) const;
3452 :
3453 : //===--------------------------------------------------------------------===//
3454 : // Instruction Emitting Hooks
3455 : //
3456 :
3457 : /// This method should be implemented by targets that mark instructions with
3458 : /// the 'usesCustomInserter' flag. These instructions are special in various
3459 : /// ways, which require special support to insert. The specified MachineInstr
3460 : /// is created but not inserted into any basic blocks, and this method is
3461 : /// called to expand it into a sequence of instructions, potentially also
3462 : /// creating new basic blocks and control flow.
3463 : /// As long as the returned basic block is different (i.e., we created a new
3464 : /// one), the custom inserter is free to modify the rest of \p MBB.
3465 : virtual MachineBasicBlock *
3466 : EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3467 :
3468 : /// This method should be implemented by targets that mark instructions with
3469 : /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3470 : /// instruction selection by target hooks. e.g. To fill in optional defs for
3471 : /// ARM 's' setting instructions.
3472 : virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3473 : SDNode *Node) const;
3474 :
3475 : /// If this function returns true, SelectionDAGBuilder emits a
3476 : /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3477 0 : virtual bool useLoadStackGuardNode() const {
3478 0 : return false;
3479 : }
3480 :
3481 : /// Lower TLS global address SDNode for target independent emulated TLS model.
3482 : virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3483 : SelectionDAG &DAG) const;
3484 :
3485 : // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3486 : // If we're comparing for equality to zero and isCtlzFast is true, expose the
3487 : // fact that this can be implemented as a ctlz/srl pair, so that the dag
3488 : // combiner can fold the new nodes.
3489 : SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3490 :
3491 : private:
3492 : SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3493 : ISD::CondCode Cond, DAGCombinerInfo &DCI,
3494 : const SDLoc &DL) const;
3495 : };
3496 :
3497 : /// Given an LLVM IR type and return type attributes, compute the return value
3498 : /// EVTs and flags, and optionally also the offsets, if the return value is
3499 : /// being lowered to memory.
3500 : void GetReturnInfo(Type *ReturnType, AttributeList attr,
3501 : SmallVectorImpl<ISD::OutputArg> &Outs,
3502 : const TargetLowering &TLI, const DataLayout &DL);
3503 :
3504 : } // end namespace llvm
3505 :
3506 : #endif // LLVM_TARGET_TARGETLOWERING_H
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