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1 : //==- Target/TargetRegisterInfo.h - Target Register Information --*- C++ -*-==//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file describes an abstract interface used to get information about a
11 : // target machines register file. This information is used for a variety of
12 : // purposed, especially register allocation.
13 : //
14 : //===----------------------------------------------------------------------===//
15 :
16 : #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 : #define LLVM_TARGET_TARGETREGISTERINFO_H
18 :
19 : #include "llvm/ADT/ArrayRef.h"
20 : #include "llvm/ADT/SmallVector.h"
21 : #include "llvm/ADT/StringRef.h"
22 : #include "llvm/ADT/iterator_range.h"
23 : #include "llvm/CodeGen/MachineBasicBlock.h"
24 : #include "llvm/CodeGen/MachineValueType.h"
25 : #include "llvm/IR/CallingConv.h"
26 : #include "llvm/MC/LaneBitmask.h"
27 : #include "llvm/MC/MCRegisterInfo.h"
28 : #include "llvm/Support/ErrorHandling.h"
29 : #include "llvm/Support/MathExtras.h"
30 : #include "llvm/Support/Printable.h"
31 : #include <cassert>
32 : #include <cstdint>
33 : #include <functional>
34 :
35 : namespace llvm {
36 :
37 : class BitVector;
38 : class LiveRegMatrix;
39 : class MachineFunction;
40 : class MachineInstr;
41 : class RegScavenger;
42 : class VirtRegMap;
43 :
44 : class TargetRegisterClass {
45 : public:
46 : using iterator = const MCPhysReg *;
47 : using const_iterator = const MCPhysReg *;
48 : using sc_iterator = const TargetRegisterClass* const *;
49 :
50 : // Instance variables filled by tablegen, do not use!
51 : const MCRegisterClass *MC;
52 : const uint16_t SpillSize, SpillAlignment;
53 : const MVT::SimpleValueType *VTs;
54 : const uint32_t *SubClassMask;
55 : const uint16_t *SuperRegIndices;
56 : const LaneBitmask LaneMask;
57 : /// Classes with a higher priority value are assigned first by register
58 : /// allocators using a greedy heuristic. The value is in the range [0,63].
59 : const uint8_t AllocationPriority;
60 : /// Whether the class supports two (or more) disjunct subregister indices.
61 : const bool HasDisjunctSubRegs;
62 : /// Whether a combination of subregisters can cover every register in the
63 : /// class. See also the CoveredBySubRegs description in Target.td.
64 : const bool CoveredBySubRegs;
65 : const sc_iterator SuperClasses;
66 : ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
67 :
68 : /// Return the register class ID number.
69 72103269 : unsigned getID() const { return MC->getID(); }
70 :
71 : /// begin/end - Return all of the registers in this class.
72 : ///
73 7790658 : iterator begin() const { return MC->begin(); }
74 7315603 : iterator end() const { return MC->end(); }
75 :
76 : /// Return the number of registers in this class.
77 2341777 : unsigned getNumRegs() const { return MC->getNumRegs(); }
78 :
79 : iterator_range<SmallVectorImpl<MCPhysReg>::const_iterator>
80 : getRegisters() const {
81 86364 : return make_range(MC->begin(), MC->end());
82 : }
83 :
84 : /// Return the specified register in the class.
85 : unsigned getRegister(unsigned i) const {
86 709252 : return MC->getRegister(i);
87 : }
88 :
89 : /// Return true if the specified register is included in this register class.
90 : /// This does not include virtual registers.
91 : bool contains(unsigned Reg) const {
92 135463923 : return MC->contains(Reg);
93 : }
94 :
95 : /// Return true if both registers are in this class.
96 : bool contains(unsigned Reg1, unsigned Reg2) const {
97 366466 : return MC->contains(Reg1, Reg2);
98 : }
99 :
100 : /// Return the cost of copying a value between two registers in this class.
101 : /// A negative number means the register class is very expensive
102 : /// to copy e.g. status flag register classes.
103 264185 : int getCopyCost() const { return MC->getCopyCost(); }
104 :
105 : /// Return true if this register class may be used to create virtual
106 : /// registers.
107 1570975 : bool isAllocatable() const { return MC->isAllocatable(); }
108 :
109 : /// Return true if the specified TargetRegisterClass
110 : /// is a proper sub-class of this TargetRegisterClass.
111 : bool hasSubClass(const TargetRegisterClass *RC) const {
112 3696886 : return RC != this && hasSubClassEq(RC);
113 : }
114 :
115 : /// Returns true if RC is a sub-class of or equal to this class.
116 : bool hasSubClassEq(const TargetRegisterClass *RC) const {
117 26298904 : unsigned ID = RC->getID();
118 13282649 : return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
119 : }
120 :
121 : /// Return true if the specified TargetRegisterClass is a
122 : /// proper super-class of this TargetRegisterClass.
123 : bool hasSuperClass(const TargetRegisterClass *RC) const {
124 : return RC->hasSubClass(this);
125 : }
126 :
127 : /// Returns true if RC is a super-class of or equal to this class.
128 : bool hasSuperClassEq(const TargetRegisterClass *RC) const {
129 22189540 : return RC->hasSubClassEq(this);
130 : }
131 :
132 : /// Returns a bit vector of subclasses, including this one.
133 : /// The vector is indexed by class IDs.
134 : ///
135 : /// To use it, consider the returned array as a chunk of memory that
136 : /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
137 : /// contains a bitset of the ID of the subclasses in big-endian style.
138 :
139 : /// I.e., the representation of the memory from left to right at the
140 : /// bit level looks like:
141 : /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
142 : /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
143 : /// Where the number represents the class ID and XXX bits that
144 : /// should be ignored.
145 : ///
146 : /// See the implementation of hasSubClassEq for an example of how it
147 : /// can be used.
148 : const uint32_t *getSubClassMask() const {
149 : return SubClassMask;
150 : }
151 :
152 : /// Returns a 0-terminated list of sub-register indices that project some
153 : /// super-register class into this register class. The list has an entry for
154 : /// each Idx such that:
155 : ///
156 : /// There exists SuperRC where:
157 : /// For all Reg in SuperRC:
158 : /// this->contains(Reg:Idx)
159 : const uint16_t *getSuperRegIndices() const {
160 : return SuperRegIndices;
161 : }
162 :
163 : /// Returns a NULL-terminated list of super-classes. The
164 : /// classes are ordered by ID which is also a topological ordering from large
165 : /// to small classes. The list does NOT include the current class.
166 : sc_iterator getSuperClasses() const {
167 : return SuperClasses;
168 : }
169 :
170 : /// Return true if this TargetRegisterClass is a subset
171 : /// class of at least one other TargetRegisterClass.
172 : bool isASubClass() const {
173 : return SuperClasses[0] != nullptr;
174 : }
175 :
176 : /// Returns the preferred order for allocating registers from this register
177 : /// class in MF. The raw order comes directly from the .td file and may
178 : /// include reserved registers that are not allocatable.
179 : /// Register allocators should also make sure to allocate
180 : /// callee-saved registers only after all the volatiles are used. The
181 : /// RegisterClassInfo class provides filtered allocation orders with
182 : /// callee-saved registers moved to the end.
183 : ///
184 : /// The MachineFunction argument can be used to tune the allocatable
185 : /// registers based on the characteristics of the function, subtarget, or
186 : /// other criteria.
187 : ///
188 : /// By default, this method returns all registers in the class.
189 : ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
190 954294 : return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
191 : }
192 :
193 : /// Returns the combination of all lane masks of register in this class.
194 : /// The lane masks of the registers are the combination of all lane masks
195 : /// of their subregisters. Returns 1 if there are no subregisters.
196 : LaneBitmask getLaneMask() const {
197 : return LaneMask;
198 : }
199 : };
200 :
201 : /// Extra information, not in MCRegisterDesc, about registers.
202 : /// These are used by codegen, not by MC.
203 : struct TargetRegisterInfoDesc {
204 : unsigned CostPerUse; // Extra cost of instructions using register.
205 : bool inAllocatableClass; // Register belongs to an allocatable regclass.
206 : };
207 :
208 : /// Each TargetRegisterClass has a per register weight, and weight
209 : /// limit which must be less than the limits of its pressure sets.
210 : struct RegClassWeight {
211 : unsigned RegWeight;
212 : unsigned WeightLimit;
213 : };
214 :
215 : /// TargetRegisterInfo base class - We assume that the target defines a static
216 : /// array of TargetRegisterDesc objects that represent all of the machine
217 : /// registers that the target has. As such, we simply have to track a pointer
218 : /// to this array so that we can turn register number into a register
219 : /// descriptor.
220 : ///
221 56000 : class TargetRegisterInfo : public MCRegisterInfo {
222 : public:
223 : using regclass_iterator = const TargetRegisterClass * const *;
224 : using vt_iterator = const MVT::SimpleValueType *;
225 :
226 : private:
227 : const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
228 : const char *const *SubRegIndexNames; // Names of subreg indexes.
229 : // Pointer to array of lane masks, one per sub-reg index.
230 : const LaneBitmask *SubRegIndexLaneMasks;
231 :
232 : regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
233 : LaneBitmask CoveringLanes;
234 :
235 : protected:
236 : TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
237 : regclass_iterator RegClassBegin,
238 : regclass_iterator RegClassEnd,
239 : const char *const *SRINames,
240 : const LaneBitmask *SRILaneMasks,
241 : LaneBitmask CoveringLanes);
242 : virtual ~TargetRegisterInfo();
243 :
244 : public:
245 : // Register numbers can represent physical registers, virtual registers, and
246 : // sometimes stack slots. The unsigned values are divided into these ranges:
247 : //
248 : // 0 Not a register, can be used as a sentinel.
249 : // [1;2^30) Physical registers assigned by TableGen.
250 : // [2^30;2^31) Stack slots. (Rarely used.)
251 : // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
252 : //
253 : // Further sentinels can be allocated from the small negative integers.
254 : // DenseMapInfo<unsigned> uses -1u and -2u.
255 :
256 : /// isStackSlot - Sometimes it is useful the be able to store a non-negative
257 : /// frame index in a variable that normally holds a register. isStackSlot()
258 : /// returns true if Reg is in the range used for stack slots.
259 : ///
260 : /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
261 : /// slots, so if a variable may contains a stack slot, always check
262 : /// isStackSlot() first.
263 : ///
264 : static bool isStackSlot(unsigned Reg) {
265 1201395 : return int(Reg) >= (1 << 30);
266 : }
267 :
268 : /// Compute the frame index from a register value representing a stack slot.
269 : static int stackSlot2Index(unsigned Reg) {
270 : assert(isStackSlot(Reg) && "Not a stack slot");
271 69981 : return int(Reg - (1u << 30));
272 : }
273 :
274 : /// Convert a non-negative frame index to a stack slot register value.
275 : static unsigned index2StackSlot(int FI) {
276 : assert(FI >= 0 && "Cannot hold a negative frame index.");
277 79981 : return FI + (1u << 30);
278 : }
279 :
280 : /// Return true if the specified register number is in
281 : /// the physical register namespace.
282 : static bool isPhysicalRegister(unsigned Reg) {
283 : assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
284 210568282 : return int(Reg) > 0;
285 : }
286 :
287 : /// Return true if the specified register number is in
288 : /// the virtual register namespace.
289 : static bool isVirtualRegister(unsigned Reg) {
290 : assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
291 448074307 : return int(Reg) < 0;
292 : }
293 :
294 : /// Convert a virtual register number to a 0-based index.
295 : /// The first virtual register in a function will get the index 0.
296 : static unsigned virtReg2Index(unsigned Reg) {
297 : assert(isVirtualRegister(Reg) && "Not a virtual register");
298 267631737 : return Reg & ~(1u << 31);
299 : }
300 :
301 : /// Convert a 0-based index to a virtual register number.
302 : /// This is the inverse operation of VirtReg2IndexFunctor below.
303 : static unsigned index2VirtReg(unsigned Index) {
304 27243929 : return Index | (1u << 31);
305 : }
306 :
307 : /// Return the size in bits of a register from class RC.
308 : unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
309 12974156 : return RC.SpillSize * 8;
310 : }
311 :
312 : /// Return the size in bytes of the stack slot allocated to hold a spilled
313 : /// copy of a register from class RC.
314 : unsigned getSpillSize(const TargetRegisterClass &RC) const {
315 131990 : return RC.SpillSize;
316 : }
317 :
318 : /// Return the minimum required alignment in bytes for a spill slot for
319 : /// a register of this class.
320 : unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
321 42163 : return RC.SpillAlignment;
322 : }
323 :
324 : /// Return true if the given TargetRegisterClass has the ValueType T.
325 : bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
326 143491275 : for (int i = 0; RC.VTs[i] != MVT::Other; ++i)
327 61253884 : if (MVT(RC.VTs[i]) == T)
328 : return true;
329 : return false;
330 : }
331 :
332 : /// Loop over all of the value types that can be represented by values
333 : /// in the given register class.
334 : vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const {
335 : return RC.VTs;
336 : }
337 :
338 : vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const {
339 : vt_iterator I = RC.VTs;
340 : while (*I != MVT::Other)
341 : ++I;
342 : return I;
343 : }
344 :
345 : /// Returns the Register Class of a physical register of the given type,
346 : /// picking the most sub register class of the right type that contains this
347 : /// physreg.
348 : const TargetRegisterClass *
349 : getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
350 :
351 : /// Return the maximal subclass of the given register class that is
352 : /// allocatable or NULL.
353 : const TargetRegisterClass *
354 : getAllocatableClass(const TargetRegisterClass *RC) const;
355 :
356 : /// Returns a bitset indexed by register number indicating if a register is
357 : /// allocatable or not. If a register class is specified, returns the subset
358 : /// for the class.
359 : BitVector getAllocatableSet(const MachineFunction &MF,
360 : const TargetRegisterClass *RC = nullptr) const;
361 :
362 : /// Return the additional cost of using this register instead
363 : /// of other registers in its class.
364 : unsigned getCostPerUse(unsigned RegNo) const {
365 13423792 : return InfoDesc[RegNo].CostPerUse;
366 : }
367 :
368 : /// Return true if the register is in the allocation of any register class.
369 : bool isInAllocatableClass(unsigned RegNo) const {
370 18362117 : return InfoDesc[RegNo].inAllocatableClass;
371 : }
372 :
373 : /// Return the human-readable symbolic target-specific
374 : /// name for the specified SubRegIndex.
375 : const char *getSubRegIndexName(unsigned SubIdx) const {
376 : assert(SubIdx && SubIdx < getNumSubRegIndices() &&
377 : "This is not a subregister index");
378 5620 : return SubRegIndexNames[SubIdx-1];
379 : }
380 :
381 : /// Return a bitmask representing the parts of a register that are covered by
382 : /// SubIdx \see LaneBitmask.
383 : ///
384 : /// SubIdx == 0 is allowed, it has the lane mask ~0u.
385 : LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
386 : assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
387 11312607 : return SubRegIndexLaneMasks[SubIdx];
388 : }
389 :
390 : /// The lane masks returned by getSubRegIndexLaneMask() above can only be
391 : /// used to determine if sub-registers overlap - they can't be used to
392 : /// determine if a set of sub-registers completely cover another
393 : /// sub-register.
394 : ///
395 : /// The X86 general purpose registers have two lanes corresponding to the
396 : /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
397 : /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
398 : /// sub_32bit sub-register.
399 : ///
400 : /// On the other hand, the ARM NEON lanes fully cover their registers: The
401 : /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
402 : /// This is related to the CoveredBySubRegs property on register definitions.
403 : ///
404 : /// This function returns a bit mask of lanes that completely cover their
405 : /// sub-registers. More precisely, given:
406 : ///
407 : /// Covering = getCoveringLanes();
408 : /// MaskA = getSubRegIndexLaneMask(SubA);
409 : /// MaskB = getSubRegIndexLaneMask(SubB);
410 : ///
411 : /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
412 : /// SubB.
413 : LaneBitmask getCoveringLanes() const { return CoveringLanes; }
414 :
415 : /// Returns true if the two registers are equal or alias each other.
416 : /// The registers may be virtual registers.
417 2552227 : bool regsOverlap(unsigned regA, unsigned regB) const {
418 2552227 : if (regA == regB) return true;
419 4611910 : if (isVirtualRegister(regA) || isVirtualRegister(regB))
420 : return false;
421 :
422 : // Regunits are numerically ordered. Find a common unit.
423 4484546 : MCRegUnitIterator RUA(regA, this);
424 2242273 : MCRegUnitIterator RUB(regB, this);
425 : do {
426 9872874 : if (*RUA == *RUB) return true;
427 3277129 : if (*RUA < *RUB) ++RUA;
428 : else ++RUB;
429 3277129 : } while (RUA.isValid() && RUB.isValid());
430 : return false;
431 : }
432 :
433 : /// Returns true if Reg contains RegUnit.
434 4081652 : bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
435 12120324 : for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
436 8265356 : if (*Units == RegUnit)
437 : return true;
438 3905994 : return false;
439 : }
440 :
441 : /// Return a null-terminated list of all of the callee-saved registers on
442 : /// this target. The register should be in the order of desired callee-save
443 : /// stack frame offset. The first register is closest to the incoming stack
444 : /// pointer if stack grows down, and vice versa.
445 : /// Notice: This function does not take into account disabled CSRs.
446 : /// In most cases you will want to use instead the function
447 : /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
448 : virtual const MCPhysReg*
449 : getCalleeSavedRegs(const MachineFunction *MF) const = 0;
450 :
451 : /// Return a mask of call-preserved registers for the given calling convention
452 : /// on the current function. The mask should include all call-preserved
453 : /// aliases. This is used by the register allocator to determine which
454 : /// registers can be live across a call.
455 : ///
456 : /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
457 : /// A set bit indicates that all bits of the corresponding register are
458 : /// preserved across the function call. The bit mask is expected to be
459 : /// sub-register complete, i.e. if A is preserved, so are all its
460 : /// sub-registers.
461 : ///
462 : /// Bits are numbered from the LSB, so the bit for physical register Reg can
463 : /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
464 : ///
465 : /// A NULL pointer means that no register mask will be used, and call
466 : /// instructions should use implicit-def operands to indicate call clobbered
467 : /// registers.
468 : ///
469 0 : virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
470 : CallingConv::ID) const {
471 : // The default mask clobbers everything. All targets should override.
472 0 : return nullptr;
473 : }
474 :
475 : /// Return a register mask that clobbers everything.
476 0 : virtual const uint32_t *getNoPreservedMask() const {
477 0 : llvm_unreachable("target does not provide no preserved mask");
478 : }
479 :
480 : /// Return true if all bits that are set in mask \p mask0 are also set in
481 : /// \p mask1.
482 : bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
483 :
484 : /// Return all the call-preserved register masks defined for this target.
485 : virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
486 : virtual ArrayRef<const char *> getRegMaskNames() const = 0;
487 :
488 : /// Returns a bitset indexed by physical register number indicating if a
489 : /// register is a special register that has particular uses and should be
490 : /// considered unavailable at all times, e.g. stack pointer, return address.
491 : /// A reserved register:
492 : /// - is not allocatable
493 : /// - is considered always live
494 : /// - is ignored by liveness tracking
495 : /// It is often necessary to reserve the super registers of a reserved
496 : /// register as well, to avoid them getting allocated indirectly. You may use
497 : /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
498 : virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
499 :
500 : /// Returns true if PhysReg is unallocatable and constant throughout the
501 : /// function. Used by MachineRegisterInfo::isConstantPhysReg().
502 6158609 : virtual bool isConstantPhysReg(unsigned PhysReg) const { return false; }
503 :
504 : /// Physical registers that may be modified within a function but are
505 : /// guaranteed to be restored before any uses. This is useful for targets that
506 : /// have call sequences where a GOT register may be updated by the caller
507 : /// prior to a call and is guaranteed to be restored (also by the caller)
508 : /// after the call.
509 44757 : virtual bool isCallerPreservedPhysReg(unsigned PhysReg,
510 : const MachineFunction &MF) const {
511 44757 : return false;
512 : }
513 :
514 : /// Prior to adding the live-out mask to a stackmap or patchpoint
515 : /// instruction, provide the target the opportunity to adjust it (mainly to
516 : /// remove pseudo-registers that should be ignored).
517 46 : virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
518 :
519 : /// Return a super-register of the specified register
520 : /// Reg so its sub-register of index SubIdx is Reg.
521 : unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
522 : const TargetRegisterClass *RC) const {
523 60814 : return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
524 : }
525 :
526 : /// Return a subclass of the specified register
527 : /// class A so that each register in it has a sub-register of the
528 : /// specified sub-register index which is in the specified register class B.
529 : ///
530 : /// TableGen will synthesize missing A sub-classes.
531 : virtual const TargetRegisterClass *
532 : getMatchingSuperRegClass(const TargetRegisterClass *A,
533 : const TargetRegisterClass *B, unsigned Idx) const;
534 :
535 : // For a copy-like instruction that defines a register of class DefRC with
536 : // subreg index DefSubReg, reading from another source with class SrcRC and
537 : // subregister SrcSubReg return true if this is a preferable copy
538 : // instruction or an earlier use should be used.
539 : virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
540 : unsigned DefSubReg,
541 : const TargetRegisterClass *SrcRC,
542 : unsigned SrcSubReg) const;
543 :
544 : /// Returns the largest legal sub-class of RC that
545 : /// supports the sub-register index Idx.
546 : /// If no such sub-class exists, return NULL.
547 : /// If all registers in RC already have an Idx sub-register, return RC.
548 : ///
549 : /// TableGen generates a version of this function that is good enough in most
550 : /// cases. Targets can override if they have constraints that TableGen
551 : /// doesn't understand. For example, the x86 sub_8bit sub-register index is
552 : /// supported by the full GR32 register class in 64-bit mode, but only by the
553 : /// GR32_ABCD regiister class in 32-bit mode.
554 : ///
555 : /// TableGen will synthesize missing RC sub-classes.
556 : virtual const TargetRegisterClass *
557 0 : getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
558 : assert(Idx == 0 && "Target has no sub-registers");
559 0 : return RC;
560 : }
561 :
562 : /// Return the subregister index you get from composing
563 : /// two subregister indices.
564 : ///
565 : /// The special null sub-register index composes as the identity.
566 : ///
567 : /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
568 : /// returns c. Note that composeSubRegIndices does not tell you about illegal
569 : /// compositions. If R does not have a subreg a, or R:a does not have a subreg
570 : /// b, composeSubRegIndices doesn't tell you.
571 : ///
572 : /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
573 : /// ssub_0:S0 - ssub_3:S3 subregs.
574 : /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
575 : unsigned composeSubRegIndices(unsigned a, unsigned b) const {
576 4911633 : if (!a) return b;
577 865149 : if (!b) return a;
578 294252 : return composeSubRegIndicesImpl(a, b);
579 : }
580 :
581 : /// Transforms a LaneMask computed for one subregister to the lanemask that
582 : /// would have been computed when composing the subsubregisters with IdxA
583 : /// first. @sa composeSubRegIndices()
584 : LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA,
585 : LaneBitmask Mask) const {
586 196883 : if (!IdxA)
587 10567 : return Mask;
588 258959 : return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
589 : }
590 :
591 : /// Transform a lanemask given for a virtual register to the corresponding
592 : /// lanemask before using subregister with index \p IdxA.
593 : /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
594 : /// valie lane mask (no invalid bits set) the following holds:
595 : /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
596 : /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
597 : /// => X1 == Mask
598 : LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA,
599 : LaneBitmask LaneMask) const {
600 475292 : if (!IdxA)
601 160506 : return LaneMask;
602 319717 : return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
603 : }
604 :
605 : /// Debugging helper: dump register in human readable form to dbgs() stream.
606 : static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
607 : const TargetRegisterInfo* TRI = nullptr);
608 :
609 : protected:
610 : /// Overridden by TableGen in targets that have sub-registers.
611 0 : virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
612 0 : llvm_unreachable("Target has no sub-registers");
613 : }
614 :
615 : /// Overridden by TableGen in targets that have sub-registers.
616 : virtual LaneBitmask
617 0 : composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const {
618 0 : llvm_unreachable("Target has no sub-registers");
619 : }
620 :
621 0 : virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned,
622 : LaneBitmask) const {
623 0 : llvm_unreachable("Target has no sub-registers");
624 : }
625 :
626 : public:
627 : /// Find a common super-register class if it exists.
628 : ///
629 : /// Find a register class, SuperRC and two sub-register indices, PreA and
630 : /// PreB, such that:
631 : ///
632 : /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
633 : ///
634 : /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
635 : ///
636 : /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
637 : ///
638 : /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
639 : /// requirements, and there is no register class with a smaller spill size
640 : /// that satisfies the requirements.
641 : ///
642 : /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
643 : ///
644 : /// Either of the PreA and PreB sub-register indices may be returned as 0. In
645 : /// that case, the returned register class will be a sub-class of the
646 : /// corresponding argument register class.
647 : ///
648 : /// The function returns NULL if no register class can be found.
649 : const TargetRegisterClass*
650 : getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
651 : const TargetRegisterClass *RCB, unsigned SubB,
652 : unsigned &PreA, unsigned &PreB) const;
653 :
654 : //===--------------------------------------------------------------------===//
655 : // Register Class Information
656 : //
657 :
658 : /// Register class iterators
659 : regclass_iterator regclass_begin() const { return RegClassBegin; }
660 : regclass_iterator regclass_end() const { return RegClassEnd; }
661 : iterator_range<regclass_iterator> regclasses() const {
662 2339950 : return make_range(regclass_begin(), regclass_end());
663 : }
664 :
665 : unsigned getNumRegClasses() const {
666 10049647 : return (unsigned)(regclass_end()-regclass_begin());
667 : }
668 :
669 : /// Returns the register class associated with the enumeration value.
670 : /// See class MCOperandInfo.
671 : const TargetRegisterClass *getRegClass(unsigned i) const {
672 : assert(i < getNumRegClasses() && "Register Class ID out of range");
673 44733936 : return RegClassBegin[i];
674 : }
675 :
676 : /// Returns the name of the register class.
677 : const char *getRegClassName(const TargetRegisterClass *Class) const {
678 76161 : return MCRegisterInfo::getRegClassName(Class->MC);
679 : }
680 :
681 : /// Find the largest common subclass of A and B.
682 : /// Return NULL if there is no common subclass.
683 : /// The common subclass should contain
684 : /// simple value type SVT if it is not the Any type.
685 : const TargetRegisterClass *
686 : getCommonSubClass(const TargetRegisterClass *A,
687 : const TargetRegisterClass *B,
688 : const MVT::SimpleValueType SVT =
689 : MVT::SimpleValueType::Any) const;
690 :
691 : /// Returns a TargetRegisterClass used for pointer values.
692 : /// If a target supports multiple different pointer register classes,
693 : /// kind specifies which one is indicated.
694 : virtual const TargetRegisterClass *
695 0 : getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
696 0 : llvm_unreachable("Target didn't implement getPointerRegClass!");
697 : }
698 :
699 : /// Returns a legal register class to copy a register in the specified class
700 : /// to or from. If it is possible to copy the register directly without using
701 : /// a cross register class copy, return the specified RC. Returns NULL if it
702 : /// is not possible to copy between two registers of the specified class.
703 : virtual const TargetRegisterClass *
704 0 : getCrossCopyRegClass(const TargetRegisterClass *RC) const {
705 0 : return RC;
706 : }
707 :
708 : /// Returns the largest super class of RC that is legal to use in the current
709 : /// sub-target and has the same spill size.
710 : /// The returned register class can be used to create virtual registers which
711 : /// means that all its registers can be copied and spilled.
712 : virtual const TargetRegisterClass *
713 848411 : getLargestLegalSuperClass(const TargetRegisterClass *RC,
714 : const MachineFunction &) const {
715 : /// The default implementation is very conservative and doesn't allow the
716 : /// register allocator to inflate register classes.
717 848411 : return RC;
718 : }
719 :
720 : /// Return the register pressure "high water mark" for the specific register
721 : /// class. The scheduler is in high register pressure mode (for the specific
722 : /// register class) if it goes over the limit.
723 : ///
724 : /// Note: this is the old register pressure model that relies on a manually
725 : /// specified representative register class per value type.
726 881 : virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
727 : MachineFunction &MF) const {
728 881 : return 0;
729 : }
730 :
731 : /// Return a heuristic for the machine scheduler to compare the profitability
732 : /// of increasing one register pressure set versus another. The scheduler
733 : /// will prefer increasing the register pressure of the set which returns
734 : /// the largest value for this function.
735 293809 : virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
736 : unsigned PSetID) const {
737 293809 : return PSetID;
738 : }
739 :
740 : /// Get the weight in units of pressure for this register class.
741 : virtual const RegClassWeight &getRegClassWeight(
742 : const TargetRegisterClass *RC) const = 0;
743 :
744 : /// Get the weight in units of pressure for this register unit.
745 : virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
746 :
747 : /// Get the number of dimensions of register pressure.
748 : virtual unsigned getNumRegPressureSets() const = 0;
749 :
750 : /// Get the name of this register unit pressure set.
751 : virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
752 :
753 : /// Get the register unit pressure limit for this dimension.
754 : /// This limit must be adjusted dynamically for reserved registers.
755 : virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
756 : unsigned Idx) const = 0;
757 :
758 : /// Get the dimensions of register pressure impacted by this register class.
759 : /// Returns a -1 terminated array of pressure set IDs.
760 : virtual const int *getRegClassPressureSets(
761 : const TargetRegisterClass *RC) const = 0;
762 :
763 : /// Get the dimensions of register pressure impacted by this register unit.
764 : /// Returns a -1 terminated array of pressure set IDs.
765 : virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
766 :
767 : /// Get a list of 'hint' registers that the register allocator should try
768 : /// first when allocating a physical register for the virtual register
769 : /// VirtReg. These registers are effectively moved to the front of the
770 : /// allocation order.
771 : ///
772 : /// The Order argument is the allocation order for VirtReg's register class
773 : /// as returned from RegisterClassInfo::getOrder(). The hint registers must
774 : /// come from Order, and they must not be reserved.
775 : ///
776 : /// The default implementation of this function can resolve
777 : /// target-independent hints provided to MRI::setRegAllocationHint with
778 : /// HintType == 0. Targets that override this function should defer to the
779 : /// default implementation if they have no reason to change the allocation
780 : /// order for VirtReg. There may be target-independent hints.
781 : virtual void getRegAllocationHints(unsigned VirtReg,
782 : ArrayRef<MCPhysReg> Order,
783 : SmallVectorImpl<MCPhysReg> &Hints,
784 : const MachineFunction &MF,
785 : const VirtRegMap *VRM = nullptr,
786 : const LiveRegMatrix *Matrix = nullptr)
787 : const;
788 :
789 : /// A callback to allow target a chance to update register allocation hints
790 : /// when a register is "changed" (e.g. coalesced) to another register.
791 : /// e.g. On ARM, some virtual registers should target register pairs,
792 : /// if one of pair is coalesced to another register, the allocation hint of
793 : /// the other half of the pair should be changed to point to the new register.
794 556849 : virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
795 : MachineFunction &MF) const {
796 : // Do nothing.
797 556849 : }
798 :
799 : /// Allow the target to reverse allocation order of local live ranges. This
800 : /// will generally allocate shorter local live ranges first. For targets with
801 : /// many registers, this could reduce regalloc compile time by a large
802 : /// factor. It is disabled by default for three reasons:
803 : /// (1) Top-down allocation is simpler and easier to debug for targets that
804 : /// don't benefit from reversing the order.
805 : /// (2) Bottom-up allocation could result in poor evicition decisions on some
806 : /// targets affecting the performance of compiled code.
807 : /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
808 1275095 : virtual bool reverseLocalAssignment() const { return false; }
809 :
810 : /// Allow the target to override the cost of using a callee-saved register for
811 : /// the first time. Default value of 0 means we will use a callee-saved
812 : /// register if it is available.
813 108947 : virtual unsigned getCSRFirstUseCost() const { return 0; }
814 :
815 : /// Returns true if the target requires (and can make use of) the register
816 : /// scavenger.
817 169616 : virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
818 169616 : return false;
819 : }
820 :
821 : /// Returns true if the target wants to use frame pointer based accesses to
822 : /// spill to the scavenger emergency spill slot.
823 5012 : virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
824 5012 : return true;
825 : }
826 :
827 : /// Returns true if the target requires post PEI scavenging of registers for
828 : /// materializing frame index constants.
829 74129 : virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
830 74129 : return false;
831 : }
832 :
833 : /// Returns true if the target requires using the RegScavenger directly for
834 : /// frame elimination despite using requiresFrameIndexScavenging.
835 126071 : virtual bool requiresFrameIndexReplacementScavenging(
836 : const MachineFunction &MF) const {
837 126071 : return false;
838 : }
839 :
840 : /// Returns true if the target wants the LocalStackAllocation pass to be run
841 : /// and virtual base registers used for more efficient stack access.
842 96916 : virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
843 96916 : return false;
844 : }
845 :
846 : /// Return true if target has reserved a spill slot in the stack frame of
847 : /// the given function for the specified register. e.g. On x86, if the frame
848 : /// register is required, the first fixed stack object is reserved as its
849 : /// spill slot. This tells PEI not to create a new stack frame
850 : /// object for the given register. It should be called only after
851 : /// determineCalleeSaves().
852 21849 : virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
853 : int &FrameIdx) const {
854 21849 : return false;
855 : }
856 :
857 : /// Returns true if the live-ins should be tracked after register allocation.
858 3907 : virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
859 3907 : return false;
860 : }
861 :
862 : /// True if the stack can be realigned for the target.
863 : virtual bool canRealignStack(const MachineFunction &MF) const;
864 :
865 : /// True if storage within the function requires the stack pointer to be
866 : /// aligned more than the normal calling convention calls for.
867 : /// This cannot be overriden by the target, but canRealignStack can be
868 : /// overridden.
869 : bool needsStackRealignment(const MachineFunction &MF) const;
870 :
871 : /// Get the offset from the referenced frame index in the instruction,
872 : /// if there is one.
873 12 : virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
874 : int Idx) const {
875 12 : return 0;
876 : }
877 :
878 : /// Returns true if the instruction's frame index reference would be better
879 : /// served by a base register other than FP or SP.
880 : /// Used by LocalStackFrameAllocation to determine which frame index
881 : /// references it should create new base registers for.
882 0 : virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
883 0 : return false;
884 : }
885 :
886 : /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
887 : /// before insertion point I.
888 0 : virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
889 : unsigned BaseReg, int FrameIdx,
890 : int64_t Offset) const {
891 0 : llvm_unreachable("materializeFrameBaseRegister does not exist on this "
892 : "target");
893 : }
894 :
895 : /// Resolve a frame index operand of an instruction
896 : /// to reference the indicated base register plus offset instead.
897 0 : virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
898 : int64_t Offset) const {
899 0 : llvm_unreachable("resolveFrameIndex does not exist on this target");
900 : }
901 :
902 : /// Determine whether a given base register plus offset immediate is
903 : /// encodable to resolve a frame index.
904 0 : virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
905 : int64_t Offset) const {
906 0 : llvm_unreachable("isFrameOffsetLegal does not exist on this target");
907 : }
908 :
909 : /// Spill the register so it can be used by the register scavenger.
910 : /// Return true if the register was spilled, false otherwise.
911 : /// If this function does not spill the register, the scavenger
912 : /// will instead spill it to the emergency spill slot.
913 24 : virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
914 : MachineBasicBlock::iterator I,
915 : MachineBasicBlock::iterator &UseMI,
916 : const TargetRegisterClass *RC,
917 : unsigned Reg) const {
918 24 : return false;
919 : }
920 :
921 : /// This method must be overriden to eliminate abstract frame indices from
922 : /// instructions which may use them. The instruction referenced by the
923 : /// iterator contains an MO_FrameIndex operand which must be eliminated by
924 : /// this method. This method may modify or replace the specified instruction,
925 : /// as long as it keeps the iterator pointing at the finished product.
926 : /// SPAdj is the SP adjustment due to call frame setup instruction.
927 : /// FIOperandNum is the FI operand number.
928 : virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
929 : int SPAdj, unsigned FIOperandNum,
930 : RegScavenger *RS = nullptr) const = 0;
931 :
932 : /// Return the assembly name for \p Reg.
933 70052576 : virtual StringRef getRegAsmName(unsigned Reg) const {
934 : // FIXME: We are assuming that the assembly name is equal to the TableGen
935 : // name converted to lower case
936 : //
937 : // The TableGen name is the name of the definition for this register in the
938 : // target's tablegen files. For example, the TableGen name of
939 : // def EAX : Register <...>; is "EAX"
940 210157728 : return StringRef(getName(Reg));
941 : }
942 :
943 : //===--------------------------------------------------------------------===//
944 : /// Subtarget Hooks
945 :
946 : /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true.
947 449367 : virtual bool shouldCoalesce(MachineInstr *MI,
948 : const TargetRegisterClass *SrcRC,
949 : unsigned SubReg,
950 : const TargetRegisterClass *DstRC,
951 : unsigned DstSubReg,
952 : const TargetRegisterClass *NewRC) const
953 449367 : { return true; }
954 :
955 : //===--------------------------------------------------------------------===//
956 : /// Debug information queries.
957 :
958 : /// getFrameRegister - This method should return the register used as a base
959 : /// for values allocated in the current stack frame.
960 : virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
961 :
962 : /// Mark a register and all its aliases as reserved in the given set.
963 : void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const;
964 :
965 : /// Returns true if for every register in the set all super registers are part
966 : /// of the set as well.
967 : bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
968 : ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
969 : };
970 :
971 : //===----------------------------------------------------------------------===//
972 : // SuperRegClassIterator
973 : //===----------------------------------------------------------------------===//
974 : //
975 : // Iterate over the possible super-registers for a given register class. The
976 : // iterator will visit a list of pairs (Idx, Mask) corresponding to the
977 : // possible classes of super-registers.
978 : //
979 : // Each bit mask will have at least one set bit, and each set bit in Mask
980 : // corresponds to a SuperRC such that:
981 : //
982 : // For all Reg in SuperRC: Reg:Idx is in RC.
983 : //
984 : // The iterator can include (O, RC->getSubClassMask()) as the first entry which
985 : // also satisfies the above requirement, assuming Reg:0 == Reg.
986 : //
987 : class SuperRegClassIterator {
988 : const unsigned RCMaskWords;
989 : unsigned SubReg = 0;
990 : const uint16_t *Idx;
991 : const uint32_t *Mask;
992 :
993 : public:
994 : /// Create a SuperRegClassIterator that visits all the super-register classes
995 : /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
996 : SuperRegClassIterator(const TargetRegisterClass *RC,
997 : const TargetRegisterInfo *TRI,
998 : bool IncludeSelf = false)
999 3587336 : : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1000 1793668 : Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1001 : if (!IncludeSelf)
1002 : ++*this;
1003 : }
1004 :
1005 : /// Returns true if this iterator is still pointing at a valid entry.
1006 : bool isValid() const { return Idx; }
1007 :
1008 : /// Returns the current sub-register index.
1009 : unsigned getSubReg() const { return SubReg; }
1010 :
1011 : /// Returns the bit mask of register classes that getSubReg() projects into
1012 : /// RC.
1013 : /// See TargetRegisterClass::getSubClassMask() for how to use it.
1014 : const uint32_t *getMask() const { return Mask; }
1015 :
1016 : /// Advance iterator to the next entry.
1017 : void operator++() {
1018 : assert(isValid() && "Cannot move iterator past end.");
1019 3918005 : Mask += RCMaskWords;
1020 3918005 : SubReg = *Idx++;
1021 3918005 : if (!SubReg)
1022 152575 : Idx = nullptr;
1023 : }
1024 : };
1025 :
1026 : //===----------------------------------------------------------------------===//
1027 : // BitMaskClassIterator
1028 : //===----------------------------------------------------------------------===//
1029 : /// This class encapuslates the logic to iterate over bitmask returned by
1030 : /// the various RegClass related APIs.
1031 : /// E.g., this class can be used to iterate over the subclasses provided by
1032 : /// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1033 : class BitMaskClassIterator {
1034 : /// Total number of register classes.
1035 : const unsigned NumRegClasses;
1036 : /// Base index of CurrentChunk.
1037 : /// In other words, the number of bit we read to get at the
1038 : /// beginning of that chunck.
1039 : unsigned Base = 0;
1040 : /// Adjust base index of CurrentChunk.
1041 : /// Base index + how many bit we read within CurrentChunk.
1042 : unsigned Idx = 0;
1043 : /// Current register class ID.
1044 : unsigned ID = 0;
1045 : /// Mask we are iterating over.
1046 : const uint32_t *Mask;
1047 : /// Current chunk of the Mask we are traversing.
1048 : uint32_t CurrentChunk;
1049 :
1050 : /// Move ID to the next set bit.
1051 4783 : void moveToNextID() {
1052 : // If the current chunk of memory is empty, move to the next one,
1053 : // while making sure we do not go pass the number of register
1054 : // classes.
1055 17495 : while (!CurrentChunk) {
1056 : // Move to the next chunk.
1057 8468 : Base += 32;
1058 8468 : if (Base >= NumRegClasses) {
1059 2112 : ID = NumRegClasses;
1060 2112 : return;
1061 : }
1062 6356 : CurrentChunk = *++Mask;
1063 6356 : Idx = Base;
1064 : }
1065 : // Otherwise look for the first bit set from the right
1066 : // (representation of the class ID is big endian).
1067 : // See getSubClassMask for more details on the representation.
1068 5342 : unsigned Offset = countTrailingZeros(CurrentChunk);
1069 : // Add the Offset to the adjusted base number of this chunk: Idx.
1070 : // This is the ID of the register class.
1071 2671 : ID = Idx + Offset;
1072 :
1073 : // Consume the zeros, if any, and the bit we just read
1074 : // so that we are at the right spot for the next call.
1075 : // Do not do Offset + 1 because Offset may be 31 and 32
1076 : // will be UB for the shift, though in that case we could
1077 : // have make the chunk being equal to 0, but that would
1078 : // have introduced a if statement.
1079 5342 : moveNBits(Offset);
1080 2671 : moveNBits(1);
1081 : }
1082 :
1083 : /// Move \p NumBits Bits forward in CurrentChunk.
1084 : void moveNBits(unsigned NumBits) {
1085 : assert(NumBits < 32 && "Undefined behavior spotted!");
1086 : // Consume the bit we read for the next call.
1087 5342 : CurrentChunk >>= NumBits;
1088 : // Adjust the base for the chunk.
1089 2671 : Idx += NumBits;
1090 : }
1091 :
1092 : public:
1093 : /// Create a BitMaskClassIterator that visits all the register classes
1094 : /// represented by \p Mask.
1095 : ///
1096 : /// \pre \p Mask != nullptr
1097 : BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
1098 4754 : : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1099 : // Move to the first ID.
1100 2377 : moveToNextID();
1101 : }
1102 :
1103 : /// Returns true if this iterator is still pointing at a valid entry.
1104 4783 : bool isValid() const { return getID() != NumRegClasses; }
1105 :
1106 : /// Returns the current register class ID.
1107 : unsigned getID() const { return ID; }
1108 :
1109 : /// Advance iterator to the next entry.
1110 : void operator++() {
1111 : assert(isValid() && "Cannot move iterator past end.");
1112 2406 : moveToNextID();
1113 : }
1114 : };
1115 :
1116 : // This is useful when building IndexedMaps keyed on virtual registers
1117 : struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
1118 : unsigned operator()(unsigned Reg) const {
1119 303655789 : return TargetRegisterInfo::virtReg2Index(Reg);
1120 : }
1121 : };
1122 :
1123 : /// Prints virtual and physical registers with or without a TRI instance.
1124 : ///
1125 : /// The format is:
1126 : /// %noreg - NoRegister
1127 : /// %vreg5 - a virtual register.
1128 : /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
1129 : /// %EAX - a physical register
1130 : /// %physreg17 - a physical register when no TRI instance given.
1131 : ///
1132 : /// Usage: OS << PrintReg(Reg, TRI) << '\n';
1133 : Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
1134 : unsigned SubRegIdx = 0);
1135 :
1136 : /// Create Printable object to print register units on a \ref raw_ostream.
1137 : ///
1138 : /// Register units are named after their root registers:
1139 : ///
1140 : /// AL - Single root.
1141 : /// FP0~ST7 - Dual roots.
1142 : ///
1143 : /// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
1144 : Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1145 :
1146 : /// \brief Create Printable object to print virtual registers and physical
1147 : /// registers on a \ref raw_ostream.
1148 : Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1149 :
1150 : } // end namespace llvm
1151 :
1152 : #endif // LLVM_TARGET_TARGETREGISTERINFO_H
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