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1 : //===- llvm/Target/TargetSubtargetInfo.h - Target Information ---*- C++ -*-===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file describes the subtarget options of a Target machine.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15 : #define LLVM_TARGET_TARGETSUBTARGETINFO_H
16 :
17 : #include "llvm/ADT/ArrayRef.h"
18 : #include "llvm/ADT/SmallVector.h"
19 : #include "llvm/ADT/StringRef.h"
20 : #include "llvm/CodeGen/PBQPRAConstraint.h"
21 : #include "llvm/CodeGen/ScheduleDAGMutation.h"
22 : #include "llvm/CodeGen/SchedulerRegistry.h"
23 : #include "llvm/MC/MCSubtargetInfo.h"
24 : #include "llvm/Support/CodeGen.h"
25 : #include <memory>
26 : #include <vector>
27 :
28 :
29 : namespace llvm {
30 :
31 : class CallLowering;
32 : class InstrItineraryData;
33 : struct InstrStage;
34 : class InstructionSelector;
35 : class LegalizerInfo;
36 : class MachineInstr;
37 : struct MachineSchedPolicy;
38 : struct MCReadAdvanceEntry;
39 : struct MCWriteLatencyEntry;
40 : struct MCWriteProcResEntry;
41 : class RegisterBankInfo;
42 : class SDep;
43 : class SelectionDAGTargetInfo;
44 : struct SubtargetFeatureKV;
45 : struct SubtargetInfoKV;
46 : class SUnit;
47 : class TargetFrameLowering;
48 : class TargetInstrInfo;
49 : class TargetLowering;
50 : class TargetRegisterClass;
51 : class TargetRegisterInfo;
52 : class TargetSchedModel;
53 : class Triple;
54 :
55 : //===----------------------------------------------------------------------===//
56 : ///
57 : /// TargetSubtargetInfo - Generic base class for all target subtargets. All
58 : /// Target-specific options that control code generation and printing should
59 : /// be exposed through a TargetSubtargetInfo-derived class.
60 : ///
61 27996 : class TargetSubtargetInfo : public MCSubtargetInfo {
62 : protected: // Can only create subclasses...
63 : TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
64 : ArrayRef<SubtargetFeatureKV> PF,
65 : ArrayRef<SubtargetFeatureKV> PD,
66 : const SubtargetInfoKV *ProcSched,
67 : const MCWriteProcResEntry *WPR,
68 : const MCWriteLatencyEntry *WL,
69 : const MCReadAdvanceEntry *RA, const InstrStage *IS,
70 : const unsigned *OC, const unsigned *FP);
71 :
72 : public:
73 : // AntiDepBreakMode - Type of anti-dependence breaking that should
74 : // be performed before post-RA scheduling.
75 : using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
76 : using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>;
77 :
78 : TargetSubtargetInfo() = delete;
79 : TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
80 : TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete;
81 : ~TargetSubtargetInfo() override;
82 :
83 0 : virtual bool isXRaySupported() const { return false; }
84 :
85 : // Interfaces to the major aspects of target machine information:
86 : //
87 : // -- Instruction opcode and operand information
88 : // -- Pipelines and scheduling information
89 : // -- Stack frame information
90 : // -- Selection DAG lowering information
91 : // -- Call lowering information
92 : //
93 : // N.B. These objects may change during compilation. It's not safe to cache
94 : // them between functions.
95 0 : virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
96 0 : virtual const TargetFrameLowering *getFrameLowering() const {
97 0 : return nullptr;
98 : }
99 0 : virtual const TargetLowering *getTargetLowering() const { return nullptr; }
100 0 : virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const {
101 0 : return nullptr;
102 : }
103 0 : virtual const CallLowering *getCallLowering() const { return nullptr; }
104 :
105 : // FIXME: This lets targets specialize the selector by subtarget (which lets
106 : // us do things like a dedicated avx512 selector). However, we might want
107 : // to also specialize selectors by MachineFunction, which would let us be
108 : // aware of optsize/optnone and such.
109 0 : virtual const InstructionSelector *getInstructionSelector() const {
110 0 : return nullptr;
111 : }
112 :
113 : /// Target can subclass this hook to select a different DAG scheduler.
114 : virtual RegisterScheduler::FunctionPassCtor
115 277990 : getDAGScheduler(CodeGenOpt::Level) const {
116 277990 : return nullptr;
117 : }
118 :
119 0 : virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
120 :
121 : /// getRegisterInfo - If register information is available, return it. If
122 : /// not, return null.
123 0 : virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
124 :
125 : /// If the information for the register banks is available, return it.
126 : /// Otherwise return nullptr.
127 75 : virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; }
128 :
129 : /// getInstrItineraryData - Returns instruction itinerary data for the target
130 : /// or specific subtarget.
131 45458 : virtual const InstrItineraryData *getInstrItineraryData() const {
132 45458 : return nullptr;
133 : }
134 :
135 : /// Resolve a SchedClass at runtime, where SchedClass identifies an
136 : /// MCSchedClassDesc with the isVariant property. This may return the ID of
137 : /// another variant SchedClass, but repeated invocation must quickly terminate
138 : /// in a nonvariant SchedClass.
139 0 : virtual unsigned resolveSchedClass(unsigned SchedClass,
140 : const MachineInstr *MI,
141 : const TargetSchedModel *SchedModel) const {
142 0 : return 0;
143 : }
144 :
145 : /// \brief True if the subtarget should run MachineScheduler after aggressive
146 : /// coalescing.
147 : ///
148 : /// This currently replaces the SelectionDAG scheduler with the "source" order
149 : /// scheduler (though see below for an option to turn this off and use the
150 : /// TargetLowering preference). It does not yet disable the postRA scheduler.
151 : virtual bool enableMachineScheduler() const;
152 :
153 : /// \brief Support printing of [latency:throughput] comment in output .S file.
154 72104 : virtual bool supportPrintSchedInfo() const { return false; }
155 :
156 : /// \brief True if the machine scheduler should disable the TLI preference
157 : /// for preRA scheduling with the source level scheduler.
158 229470 : virtual bool enableMachineSchedDefaultSched() const { return true; }
159 :
160 : /// \brief True if the subtarget should enable joining global copies.
161 : ///
162 : /// By default this is enabled if the machine scheduler is enabled, but
163 : /// can be overridden.
164 : virtual bool enableJoinGlobalCopies() const;
165 :
166 : /// True if the subtarget should run a scheduler after register allocation.
167 : ///
168 : /// By default this queries the PostRAScheduling bit in the scheduling model
169 : /// which is the preferred way to influence this.
170 : virtual bool enablePostRAScheduler() const;
171 :
172 : /// \brief True if the subtarget should run the atomic expansion pass.
173 : virtual bool enableAtomicExpand() const;
174 :
175 : /// \brief Override generic scheduling policy within a region.
176 : ///
177 : /// This is a convenient way for targets that don't provide any custom
178 : /// scheduling heuristics (no custom MachineSchedStrategy) to make
179 : /// changes to the generic scheduling policy.
180 968340 : virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
181 968340 : unsigned NumRegionInstrs) const {}
182 :
183 : // \brief Perform target specific adjustments to the latency of a schedule
184 : // dependency.
185 3696041 : virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
186 :
187 : // For use with PostRAScheduling: get the anti-dependence breaking that should
188 : // be performed before post-RA scheduling.
189 40513 : virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
190 :
191 : // For use with PostRAScheduling: in CriticalPathRCs, return any register
192 : // classes that should only be considered for anti-dependence breaking if they
193 : // are on the critical path.
194 98279 : virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
195 98279 : return CriticalPathRCs.clear();
196 : }
197 :
198 : // \brief Provide an ordered list of schedule DAG mutations for the post-RA
199 : // scheduler.
200 31659 : virtual void getPostRAMutations(
201 : std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
202 31659 : }
203 :
204 : // \brief Provide an ordered list of schedule DAG mutations for the machine
205 : // pipeliner.
206 0 : virtual void getSMSMutations(
207 : std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
208 0 : }
209 :
210 : // For use with PostRAScheduling: get the minimum optimization level needed
211 : // to enable post-RA scheduling.
212 32934 : virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
213 32934 : return CodeGenOpt::Default;
214 : }
215 :
216 : /// \brief True if the subtarget should run the local reassignment
217 : /// heuristic of the register allocator.
218 : /// This heuristic may be compile time intensive, \p OptLevel provides
219 : /// a finer grain to tune the register allocator.
220 : virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
221 :
222 : /// \brief Enable use of alias analysis during code generation (during MI
223 : /// scheduling, DAGCombine, etc.).
224 : virtual bool useAA() const;
225 :
226 : /// \brief Enable the use of the early if conversion pass.
227 0 : virtual bool enableEarlyIfConversion() const { return false; }
228 :
229 : /// \brief Return PBQPConstraint(s) for the target.
230 : ///
231 : /// Override to provide custom PBQP constraints.
232 2 : virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
233 : return nullptr;
234 : }
235 :
236 : /// Enable tracking of subregister liveness in register allocator.
237 : /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
238 : /// possible.
239 118478 : virtual bool enableSubRegLiveness() const { return false; }
240 :
241 : /// Returns string representation of scheduler comment
242 : std::string getSchedInfoStr(const MachineInstr &MI) const override;
243 : std::string getSchedInfoStr(MCInst const &MCI) const override;
244 : };
245 :
246 : } // end namespace llvm
247 :
248 : #endif // LLVM_TARGET_TARGETSUBTARGETINFO_H
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