LCOV - code coverage report
Current view: top level - lib/CodeGen - AggressiveAntiDepBreaker.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 336 342 98.2 %
Date: 2018-05-20 00:06:23 Functions: 22 24 91.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AggressiveAntiDepBreaker.cpp - Anti-dep breaker --------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the AggressiveAntiDepBreaker class, which
      11             : // implements register anti-dependence breaking during post-RA
      12             : // scheduling. It attempts to break all anti-dependencies within a
      13             : // block.
      14             : //
      15             : //===----------------------------------------------------------------------===//
      16             : 
      17             : #include "AggressiveAntiDepBreaker.h"
      18             : #include "llvm/ADT/ArrayRef.h"
      19             : #include "llvm/ADT/BitVector.h"
      20             : #include "llvm/ADT/SmallSet.h"
      21             : #include "llvm/ADT/iterator_range.h"
      22             : #include "llvm/CodeGen/MachineBasicBlock.h"
      23             : #include "llvm/CodeGen/MachineFrameInfo.h"
      24             : #include "llvm/CodeGen/MachineFunction.h"
      25             : #include "llvm/CodeGen/MachineInstr.h"
      26             : #include "llvm/CodeGen/MachineOperand.h"
      27             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      28             : #include "llvm/CodeGen/RegisterClassInfo.h"
      29             : #include "llvm/CodeGen/ScheduleDAG.h"
      30             : #include "llvm/CodeGen/TargetInstrInfo.h"
      31             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      32             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      33             : #include "llvm/MC/MCInstrDesc.h"
      34             : #include "llvm/MC/MCRegisterInfo.h"
      35             : #include "llvm/Support/CommandLine.h"
      36             : #include "llvm/Support/Debug.h"
      37             : #include "llvm/Support/MachineValueType.h"
      38             : #include "llvm/Support/raw_ostream.h"
      39             : #include <cassert>
      40             : #include <map>
      41             : #include <set>
      42             : #include <utility>
      43             : #include <vector>
      44             : 
      45             : using namespace llvm;
      46             : 
      47             : #define DEBUG_TYPE "post-RA-sched"
      48             : 
      49             : // If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod
      50             : static cl::opt<int>
      51       99237 : DebugDiv("agg-antidep-debugdiv",
      52       99237 :          cl::desc("Debug control for aggressive anti-dep breaker"),
      53      297711 :          cl::init(0), cl::Hidden);
      54             : 
      55             : static cl::opt<int>
      56       99237 : DebugMod("agg-antidep-debugmod",
      57       99237 :          cl::desc("Debug control for aggressive anti-dep breaker"),
      58      297711 :          cl::init(0), cl::Hidden);
      59             : 
      60       17185 : AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
      61       17185 :                                                MachineBasicBlock *BB)
      62             :     : NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
      63             :       GroupNodeIndices(TargetRegs, 0), KillIndices(TargetRegs, 0),
      64       34370 :       DefIndices(TargetRegs, 0) {
      65             :   const unsigned BBSize = BB->size();
      66     9500895 :   for (unsigned i = 0; i < NumTargetRegs; ++i) {
      67             :     // Initialize all registers to be in their own group. Initially we
      68             :     // assign the register to the same-indexed GroupNode.
      69     9483710 :     GroupNodeIndices[i] = i;
      70             :     // Initialize the indices to indicate that no registers are live.
      71     9483710 :     KillIndices[i] = ~0u;
      72     9483710 :     DefIndices[i] = BBSize;
      73             :   }
      74       17185 : }
      75             : 
      76           0 : unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
      77    17710692 :   unsigned Node = GroupNodeIndices[Reg];
      78    27122046 :   while (GroupNodes[Node] != Node)
      79             :     Node = GroupNodes[Node];
      80             : 
      81           0 :   return Node;
      82             : }
      83             : 
      84        2694 : void AggressiveAntiDepState::GetGroupRegs(
      85             :   unsigned Group,
      86             :   std::vector<unsigned> &Regs,
      87             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
      88             : {
      89      717796 :   for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
      90      719610 :     if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
      91        2935 :       Regs.push_back(Reg);
      92             :   }
      93        2694 : }
      94             : 
      95     4067309 : unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) {
      96             :   assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
      97             :   assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
      98             : 
      99             :   // find group for each register
     100             :   unsigned Group1 = GetGroup(Reg1);
     101             :   unsigned Group2 = GetGroup(Reg2);
     102             : 
     103             :   // if either group is 0, then that must become the parent
     104     4067309 :   unsigned Parent = (Group1 == 0) ? Group1 : Group2;
     105     4067309 :   unsigned Other = (Parent == Group1) ? Group2 : Group1;
     106     8134618 :   GroupNodes.at(Other) = Parent;
     107     4067309 :   return Parent;
     108             : }
     109             : 
     110      168276 : unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) {
     111             :   // Create a new GroupNode for Reg. Reg's existing GroupNode must
     112             :   // stay as is because there could be other GroupNodes referring to
     113             :   // it.
     114      336552 :   unsigned idx = GroupNodes.size();
     115      168276 :   GroupNodes.push_back(idx);
     116      336552 :   GroupNodeIndices[Reg] = idx;
     117      168276 :   return idx;
     118             : }
     119             : 
     120           0 : bool AggressiveAntiDepState::IsLive(unsigned Reg) {
     121             :   // KillIndex must be defined and DefIndex not defined for a register
     122             :   // to be live.
     123    15597958 :   return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
     124             : }
     125             : 
     126       11134 : AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(
     127             :     MachineFunction &MFi, const RegisterClassInfo &RCI,
     128       11134 :     TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
     129       11134 :     : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
     130       11134 :       TII(MF.getSubtarget().getInstrInfo()),
     131       44536 :       TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) {
     132             :   /* Collect a bitset of all registers that are only broken if they
     133             :      are on the critical path. */
     134       19093 :   for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
     135       15918 :     BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
     136        7959 :     if (CriticalPathSet.none())
     137        7959 :       CriticalPathSet = CPSet;
     138             :     else
     139           0 :       CriticalPathSet |= CPSet;
     140             :    }
     141             : 
     142             :    LLVM_DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
     143             :    LLVM_DEBUG(for (unsigned r
     144             :                    : CriticalPathSet.set_bits()) dbgs()
     145             :               << " " << printReg(r, TRI));
     146             :    LLVM_DEBUG(dbgs() << '\n');
     147       11134 : }
     148             : 
     149       33402 : AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
     150       11134 :   delete State;
     151       22268 : }
     152             : 
     153       17185 : void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
     154             :   assert(!State);
     155       17185 :   State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
     156             : 
     157       17185 :   bool IsReturnBlock = BB->isReturnBlock();
     158       17185 :   std::vector<unsigned> &KillIndices = State->GetKillIndices();
     159             :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     160             : 
     161             :   // Examine the live-in regs of all successors.
     162             :   for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
     163       26126 :          SE = BB->succ_end(); SI != SE; ++SI)
     164       49274 :     for (const auto &LI : (*SI)->liveins()) {
     165      197564 :       for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
     166             :         unsigned Reg = *AI;
     167       67390 :         State->UnionGroups(Reg, 0);
     168      134780 :         KillIndices[Reg] = BB->size();
     169      134780 :         DefIndices[Reg] = ~0u;
     170             :       }
     171             :     }
     172             : 
     173             :   // Mark live-out callee-saved registers. In a return block this is
     174             :   // all callee-saved registers. In non-return this is any
     175             :   // callee-saved register that is not saved in the prolog.
     176       17185 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     177       17185 :   BitVector Pristine = MFI.getPristineRegs(MF);
     178      678183 :   for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;
     179             :        ++I) {
     180      660998 :     unsigned Reg = *I;
     181      881957 :     if (!IsReturnBlock && !Pristine.test(Reg))
     182       10664 :       continue;
     183     4774082 :     for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
     184             :       unsigned AliasReg = *AI;
     185     1736707 :       State->UnionGroups(AliasReg, 0);
     186     3473414 :       KillIndices[AliasReg] = BB->size();
     187     3473414 :       DefIndices[AliasReg] = ~0u;
     188             :     }
     189             :   }
     190       17185 : }
     191             : 
     192       17185 : void AggressiveAntiDepBreaker::FinishBlock() {
     193       17185 :   delete State;
     194       17185 :   State = nullptr;
     195       17185 : }
     196             : 
     197       21298 : void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
     198             :                                        unsigned InsertPosIndex) {
     199             :   assert(Count < InsertPosIndex && "Instruction index out of expected range!");
     200             : 
     201             :   std::set<unsigned> PassthruRegs;
     202       21298 :   GetPassthruRegs(MI, PassthruRegs);
     203       21298 :   PrescanInstruction(MI, Count, PassthruRegs);
     204       21298 :   ScanInstruction(MI, Count);
     205             : 
     206             :   LLVM_DEBUG(dbgs() << "Observe: ");
     207             :   LLVM_DEBUG(MI.dump());
     208             :   LLVM_DEBUG(dbgs() << "\tRegs:");
     209             : 
     210       21298 :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     211    12029622 :   for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
     212             :     // If Reg is current live, then mark that it can't be renamed as
     213             :     // we don't know the extent of its live-range anymore (now that it
     214             :     // has been scheduled). If it is not live but was defined in the
     215             :     // previous schedule region, then set its def index to the most
     216             :     // conservative location (i.e. the beginning of the previous
     217             :     // schedule region).
     218     6004162 :     if (State->IsLive(Reg)) {
     219             :       LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs()
     220             :                  << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)
     221             :                  << "->g0(region live-out)");
     222     2177020 :       State->UnionGroups(Reg, 0);
     223     7654284 :     } else if ((DefIndices[Reg] < InsertPosIndex)
     224     3827142 :                && (DefIndices[Reg] >= Count)) {
     225       33107 :       DefIndices[Reg] = Count;
     226             :     }
     227             :   }
     228             :   LLVM_DEBUG(dbgs() << '\n');
     229       21298 : }
     230             : 
     231      231375 : bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI,
     232             :                                                 MachineOperand &MO) {
     233      462750 :   if (!MO.isReg() || !MO.isImplicit())
     234             :     return false;
     235             : 
     236       65406 :   unsigned Reg = MO.getReg();
     237       65406 :   if (Reg == 0)
     238             :     return false;
     239             : 
     240             :   MachineOperand *Op = nullptr;
     241       65406 :   if (MO.isDef())
     242             :     Op = MI.findRegisterUseOperand(Reg, true);
     243             :   else
     244             :     Op = MI.findRegisterDefOperand(Reg);
     245             : 
     246        7430 :   return(Op && Op->isImplicit());
     247             : }
     248             : 
     249       92935 : void AggressiveAntiDepBreaker::GetPassthruRegs(
     250             :     MachineInstr &MI, std::set<unsigned> &PassthruRegs) {
     251      391066 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     252      298131 :     MachineOperand &MO = MI.getOperand(i);
     253      298131 :     if (!MO.isReg()) continue;
     254      466753 :     if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) ||
     255      231375 :         IsImplicitDefUse(MI, MO)) {
     256        7209 :       const unsigned Reg = MO.getReg();
     257        7209 :       for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
     258       17296 :            SubRegs.isValid(); ++SubRegs)
     259       20174 :         PassthruRegs.insert(*SubRegs);
     260             :     }
     261             :   }
     262       92935 : }
     263             : 
     264             : /// AntiDepEdges - Return in Edges the anti- and output- dependencies
     265             : /// in SU that we want to consider for breaking.
     266       71637 : static void AntiDepEdges(const SUnit *SU, std::vector<const SDep *> &Edges) {
     267       71637 :   SmallSet<unsigned, 4> RegSet;
     268      113848 :   for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
     269      185485 :        P != PE; ++P) {
     270      113848 :     if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) {
     271       40289 :       if (RegSet.insert(P->getReg()).second)
     272       49952 :         Edges.push_back(&*P);
     273             :     }
     274             :   }
     275       71637 : }
     276             : 
     277             : /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
     278             : /// critical path.
     279       32262 : static const SUnit *CriticalPathStep(const SUnit *SU) {
     280             :   const SDep *Next = nullptr;
     281             :   unsigned NextDepth = 0;
     282             :   // Find the predecessor edge with the greatest depth.
     283       32262 :   if (SU) {
     284       49632 :     for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
     285       81894 :          P != PE; ++P) {
     286             :       const SUnit *PredSU = P->getSUnit();
     287       49632 :       unsigned PredLatency = P->getLatency();
     288       49632 :       unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
     289             :       // In the case of a latency tie, prefer an anti-dependency edge over
     290             :       // other types of edges.
     291       49632 :       if (NextDepth < PredTotalLatency ||
     292        9572 :           (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
     293             :         NextDepth = PredTotalLatency;
     294             :         Next = &*P;
     295             :       }
     296             :     }
     297             :   }
     298             : 
     299       64524 :   return (Next) ? Next->getSUnit() : nullptr;
     300             : }
     301             : 
     302      235378 : void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
     303             :                                              const char *tag,
     304             :                                              const char *header,
     305             :                                              const char *footer) {
     306      235378 :   std::vector<unsigned> &KillIndices = State->GetKillIndices();
     307             :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     308             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
     309             :     RegRefs = State->GetRegRefs();
     310             : 
     311             :   // FIXME: We must leave subregisters of live super registers as live, so that
     312             :   // we don't clear out the register tracking information for subregisters of
     313             :   // super registers we're still tracking (and with which we're unioning
     314             :   // subregister definitions).
     315     1444738 :   for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
     316     1025060 :     if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
     317             :       LLVM_DEBUG(if (!header && footer) dbgs() << footer);
     318       25539 :       return;
     319             :     }
     320             : 
     321      209839 :   if (!State->IsLive(Reg)) {
     322      225010 :     KillIndices[Reg] = KillIdx;
     323      225010 :     DefIndices[Reg] = ~0u;
     324             :     RegRefs.erase(Reg);
     325      112505 :     State->LeaveGroup(Reg);
     326             :     LLVM_DEBUG(if (header) {
     327             :       dbgs() << header << printReg(Reg, TRI);
     328             :       header = nullptr;
     329             :     });
     330             :     LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
     331             :     // Repeat for subregisters. Note that we only do this if the superregister
     332             :     // was not live because otherwise, regardless whether we have an explicit
     333             :     // use of the subregister, the subregister's contents are needed for the
     334             :     // uses of the superregister.
     335      284522 :     for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
     336       59512 :       unsigned SubregReg = *SubRegs;
     337       59512 :       if (!State->IsLive(SubregReg)) {
     338      111542 :         KillIndices[SubregReg] = KillIdx;
     339      111542 :         DefIndices[SubregReg] = ~0u;
     340             :         RegRefs.erase(SubregReg);
     341       55771 :         State->LeaveGroup(SubregReg);
     342             :         LLVM_DEBUG(if (header) {
     343             :           dbgs() << header << printReg(Reg, TRI);
     344             :           header = nullptr;
     345             :         });
     346             :         LLVM_DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g"
     347             :                           << State->GetGroup(SubregReg) << tag);
     348             :       }
     349             :     }
     350             :   }
     351             : 
     352             :   LLVM_DEBUG(if (!header && footer) dbgs() << footer);
     353             : }
     354             : 
     355       92935 : void AggressiveAntiDepBreaker::PrescanInstruction(
     356             :     MachineInstr &MI, unsigned Count, std::set<unsigned> &PassthruRegs) {
     357       92935 :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     358             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
     359             :     RegRefs = State->GetRegRefs();
     360             : 
     361             :   // Handle dead defs by simulating a last-use of the register just
     362             :   // after the def. A dead def can occur because the def is truly
     363             :   // dead, or because only a subregister is live at the def. If we
     364             :   // don't do this the dead def will be incorrectly merged into the
     365             :   // previous def.
     366      391066 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     367      298131 :     MachineOperand &MO = MI.getOperand(i);
     368      533509 :     if (!MO.isReg() || !MO.isDef()) continue;
     369       80559 :     unsigned Reg = MO.getReg();
     370       80559 :     if (Reg == 0) continue;
     371             : 
     372       80559 :     HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
     373             :   }
     374             : 
     375             :   LLVM_DEBUG(dbgs() << "\tDef Groups:");
     376      391066 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     377      298131 :     MachineOperand &MO = MI.getOperand(i);
     378      751081 :     if (!MO.isReg() || !MO.isDef()) continue;
     379       80559 :     unsigned Reg = MO.getReg();
     380       80559 :     if (Reg == 0) continue;
     381             : 
     382             :     LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
     383             :                       << State->GetGroup(Reg));
     384             : 
     385             :     // If MI's defs have a special allocation requirement, don't allow
     386             :     // any def registers to be changed. Also assume all registers
     387             :     // defined in a call must not be changed (ABI). Inline assembly may
     388             :     // reference either system calls or the register directly. Skip it until we
     389             :     // can tell user specified registers from compiler-specified.
     390      226567 :     if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) ||
     391             :         MI.isInlineAsm()) {
     392             :       LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
     393        9773 :       State->UnionGroups(Reg, 0);
     394             :     }
     395             : 
     396             :     // Any aliased that are live at this point are completely or
     397             :     // partially defined here, so group those aliases with Reg.
     398      359714 :     for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
     399             :       unsigned AliasReg = *AI;
     400       99298 :       if (State->IsLive(AliasReg)) {
     401       59778 :         State->UnionGroups(Reg, AliasReg);
     402             :         LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via "
     403             :                           << printReg(AliasReg, TRI) << ")");
     404             :       }
     405             :     }
     406             : 
     407             :     // Note register reference...
     408             :     const TargetRegisterClass *RC = nullptr;
     409      161118 :     if (i < MI.getDesc().getNumOperands())
     410       60876 :       RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
     411             :     AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
     412       80559 :     RegRefs.insert(std::make_pair(Reg, RR));
     413             :   }
     414             : 
     415             :   LLVM_DEBUG(dbgs() << '\n');
     416             : 
     417             :   // Scan the register defs for this instruction and update
     418             :   // live-ranges.
     419      391066 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     420      298131 :     MachineOperand &MO = MI.getOperand(i);
     421      751081 :     if (!MO.isReg() || !MO.isDef()) continue;
     422       80559 :     unsigned Reg = MO.getReg();
     423       80559 :     if (Reg == 0) continue;
     424             :     // Ignore KILLs and passthru registers for liveness...
     425       87824 :     if (MI.isKill() || (PassthruRegs.count(Reg) != 0))
     426        7265 :       continue;
     427             : 
     428             :     // Update def for Reg and aliases.
     429      572110 :     for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
     430             :       // We need to be careful here not to define already-live super registers.
     431             :       // If the super register is already live, then this definition is not
     432             :       // a definition of the whole super register (just a partial insertion
     433             :       // into it). Earlier subregister definitions (which we've not yet visited
     434             :       // because we're iterating bottom-up) need to be linked to the same group
     435             :       // as this definition.
     436      363290 :       if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
     437       11062 :         continue;
     438             : 
     439      330104 :       DefIndices[*AI] = Count;
     440             :     }
     441             :   }
     442       92935 : }
     443             : 
     444       92935 : void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
     445             :                                                unsigned Count) {
     446             :   LLVM_DEBUG(dbgs() << "\tUse Groups:");
     447             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
     448       92935 :     RegRefs = State->GetRegRefs();
     449             : 
     450             :   // If MI's uses have special allocation requirement, don't allow
     451             :   // any use registers to be changed. Also assume all registers
     452             :   // used in a call must not be changed (ABI).
     453             :   // Inline Assembly register uses also cannot be safely changed.
     454             :   // FIXME: The issue with predicated instruction is more complex. We are being
     455             :   // conservatively here because the kill markers cannot be trusted after
     456             :   // if-conversion:
     457             :   // %r6 = LDR %sp, %reg0, 92, 14, %reg0; mem:LD4[FixedStack14]
     458             :   // ...
     459             :   // STR %r0, killed %r6, %reg0, 0, 0, %cpsr; mem:ST4[%395]
     460             :   // %r6 = LDR %sp, %reg0, 100, 0, %cpsr; mem:LD4[FixedStack12]
     461             :   // STR %r0, killed %r6, %reg0, 0, 14, %reg0; mem:ST4[%396](align=8)
     462             :   //
     463             :   // The first R6 kill is not really a kill since it's killed by a predicated
     464             :   // instruction which may not be executed. The second R6 def may or may not
     465             :   // re-define R6 so it's not safe to change it since the last R6 use cannot be
     466             :   // changed.
     467      181301 :   bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() ||
     468      272658 :                  TII->isPredicated(MI) || MI.isInlineAsm();
     469             : 
     470             :   // Scan the register uses for this instruction and update
     471             :   // live-ranges, groups and RegRefs.
     472      391066 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     473      298131 :     MachineOperand &MO = MI.getOperand(i);
     474      533509 :     if (!MO.isReg() || !MO.isUse()) continue;
     475      154819 :     unsigned Reg = MO.getReg();
     476      154819 :     if (Reg == 0) continue;
     477             : 
     478             :     LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
     479             :                       << State->GetGroup(Reg));
     480             : 
     481             :     // It wasn't previously live but now it is, this is a kill. Forget
     482             :     // the previous live-range information and start a new live-range
     483             :     // for the register.
     484      154819 :     HandleLastUse(Reg, Count, "(last-use)");
     485             : 
     486      154819 :     if (Special) {
     487             :       LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
     488       11231 :       State->UnionGroups(Reg, 0);
     489             :     }
     490             : 
     491             :     // Note register reference...
     492             :     const TargetRegisterClass *RC = nullptr;
     493      309638 :     if (i < MI.getDesc().getNumOperands())
     494      108074 :       RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
     495             :     AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
     496      154819 :     RegRefs.insert(std::make_pair(Reg, RR));
     497             :   }
     498             : 
     499             :   LLVM_DEBUG(dbgs() << '\n');
     500             : 
     501             :   // Form a group of all defs and uses of a KILL instruction to ensure
     502             :   // that all registers are renamed as a group.
     503       92935 :   if (MI.isKill()) {
     504             :     LLVM_DEBUG(dbgs() << "\tKill Group:");
     505             : 
     506             :     unsigned FirstReg = 0;
     507         712 :     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     508         532 :       MachineOperand &MO = MI.getOperand(i);
     509         532 :       if (!MO.isReg()) continue;
     510         532 :       unsigned Reg = MO.getReg();
     511         532 :       if (Reg == 0) continue;
     512             : 
     513         532 :       if (FirstReg != 0) {
     514             :         LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI));
     515         352 :         State->UnionGroups(FirstReg, Reg);
     516             :       } else {
     517             :         LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
     518             :         FirstReg = Reg;
     519             :       }
     520             :     }
     521             : 
     522             :     LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
     523             :   }
     524       92935 : }
     525             : 
     526        2935 : BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
     527        2935 :   BitVector BV(TRI->getNumRegs(), false);
     528             :   bool first = true;
     529             : 
     530             :   // Check all references that need rewriting for Reg. For each, use
     531             :   // the corresponding register class to narrow the set of registers
     532             :   // that are appropriate for renaming.
     533       12025 :   for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) {
     534        6155 :     const TargetRegisterClass *RC = Q.second.RC;
     535        6155 :     if (!RC) continue;
     536             : 
     537        6018 :     BitVector RCBV = TRI->getAllocatableSet(MF, RC);
     538        6018 :     if (first) {
     539        2935 :       BV |= RCBV;
     540             :       first = false;
     541             :     } else {
     542        3083 :       BV &= RCBV;
     543             :     }
     544             : 
     545             :     LLVM_DEBUG(dbgs() << " " << TRI->getRegClassName(RC));
     546             :   }
     547             : 
     548        2935 :   return BV;
     549             : }
     550             : 
     551        2694 : bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
     552             :                                 unsigned AntiDepGroupIndex,
     553             :                                 RenameOrderType& RenameOrder,
     554             :                                 std::map<unsigned, unsigned> &RenameMap) {
     555        2694 :   std::vector<unsigned> &KillIndices = State->GetKillIndices();
     556             :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     557             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
     558             :     RegRefs = State->GetRegRefs();
     559             : 
     560             :   // Collect all referenced registers in the same group as
     561             :   // AntiDepReg. These all need to be renamed together if we are to
     562             :   // break the anti-dependence.
     563             :   std::vector<unsigned> Regs;
     564        2694 :   State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
     565             :   assert(!Regs.empty() && "Empty register group!");
     566        2694 :   if (Regs.empty())
     567             :     return false;
     568             : 
     569             :   // Find the "superest" register in the group. At the same time,
     570             :   // collect the BitVector of registers that can be used to rename
     571             :   // each register.
     572             :   LLVM_DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
     573             :                     << ":\n");
     574             :   std::map<unsigned, BitVector> RenameRegisterMap;
     575             :   unsigned SuperReg = 0;
     576        5629 :   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
     577        5870 :     unsigned Reg = Regs[i];
     578        2935 :     if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
     579        2825 :       SuperReg = Reg;
     580             : 
     581             :     // If Reg has any references, then collect possible rename regs
     582        2935 :     if (RegRefs.count(Reg) > 0) {
     583             :       LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
     584             : 
     585        2935 :       BitVector &BV = RenameRegisterMap[Reg];
     586             :       assert(BV.empty());
     587        5870 :       BV = GetRenameRegisters(Reg);
     588             : 
     589             :       LLVM_DEBUG({
     590             :         dbgs() << " ::";
     591             :         for (unsigned r : BV.set_bits())
     592             :           dbgs() << " " << printReg(r, TRI);
     593             :         dbgs() << "\n";
     594             :       });
     595             :     }
     596             :   }
     597             : 
     598             :   // All group registers should be a subreg of SuperReg.
     599        8323 :   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
     600        5870 :     unsigned Reg = Regs[i];
     601        2935 :     if (Reg == SuperReg) continue;
     602         241 :     bool IsSub = TRI->isSubRegister(SuperReg, Reg);
     603             :     // FIXME: remove this once PR18663 has been properly fixed. For now,
     604             :     // return a conservative answer:
     605             :     // assert(IsSub && "Expecting group subregister");
     606         241 :     if (!IsSub)
     607             :       return false;
     608             :   }
     609             : 
     610             : #ifndef NDEBUG
     611             :   // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
     612             :   if (DebugDiv > 0) {
     613             :     static int renamecnt = 0;
     614             :     if (renamecnt++ % DebugDiv != DebugMod)
     615             :       return false;
     616             : 
     617             :     dbgs() << "*** Performing rename " << printReg(SuperReg, TRI)
     618             :            << " for debug ***\n";
     619             :   }
     620             : #endif
     621             : 
     622             :   // Check each possible rename register for SuperReg in round-robin
     623             :   // order. If that register is available, and the corresponding
     624             :   // registers are available for the other group subregisters, then we
     625             :   // can use those registers to rename.
     626             : 
     627             :   // FIXME: Using getMinimalPhysRegClass is very conservative. We should
     628             :   // check every use of the register and find the largest register class
     629             :   // that can be used in all of them.
     630             :   const TargetRegisterClass *SuperRC =
     631        5388 :     TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
     632             : 
     633        2694 :   ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
     634        2694 :   if (Order.empty()) {
     635             :     LLVM_DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
     636             :     return false;
     637             :   }
     638             : 
     639             :   LLVM_DEBUG(dbgs() << "\tFind Registers:");
     640             : 
     641        2694 :   RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
     642             : 
     643        2694 :   unsigned OrigR = RenameOrder[SuperRC];
     644        2694 :   unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR);
     645             :   unsigned R = OrigR;
     646             :   do {
     647       18832 :     if (R == 0) R = Order.size();
     648       18832 :     --R;
     649       37664 :     const unsigned NewSuperReg = Order[R];
     650             :     // Don't consider non-allocatable registers
     651       18832 :     if (!MRI.isAllocatable(NewSuperReg)) continue;
     652             :     // Don't replace a register with itself.
     653       18832 :     if (NewSuperReg == SuperReg) continue;
     654             : 
     655             :     LLVM_DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':');
     656             :     RenameMap.clear();
     657             : 
     658             :     // For each referenced group register (which must be a SuperReg or
     659             :     // a subregister of SuperReg), find the corresponding subregister
     660             :     // of NewSuperReg and make sure it is free to be renamed.
     661       38831 :     for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
     662       36654 :       unsigned Reg = Regs[i];
     663             :       unsigned NewReg = 0;
     664       18327 :       if (Reg == SuperReg) {
     665             :         NewReg = NewSuperReg;
     666             :       } else {
     667         457 :         unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
     668         457 :         if (NewSubRegIdx != 0)
     669         457 :           NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
     670             :       }
     671             : 
     672             :       LLVM_DEBUG(dbgs() << " " << printReg(NewReg, TRI));
     673             : 
     674             :       // Check if Reg can be renamed to NewReg.
     675       36654 :       if (!RenameRegisterMap[Reg].test(NewReg)) {
     676             :         LLVM_DEBUG(dbgs() << "(no rename)");
     677       15782 :         goto next_super_reg;
     678             :       }
     679             : 
     680             :       // If NewReg is dead and NewReg's most recent def is not before
     681             :       // Regs's kill, it's safe to replace Reg with NewReg. We
     682             :       // must also check all aliases of NewReg, because we can't define a
     683             :       // register when any sub or super is already live.
     684       28628 :       if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
     685             :         LLVM_DEBUG(dbgs() << "(live)");
     686             :         goto next_super_reg;
     687             :       } else {
     688             :         bool found = false;
     689       12228 :         for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
     690             :           unsigned AliasReg = *AI;
     691        6870 :           if (State->IsLive(AliasReg) ||
     692        9903 :               (KillIndices[Reg] > DefIndices[AliasReg])) {
     693             :             LLVM_DEBUG(dbgs()
     694             :                        << "(alias " << printReg(AliasReg, TRI) << " live)");
     695             :             found = true;
     696             :             break;
     697             :           }
     698             :         }
     699        2980 :         if (found)
     700             :           goto next_super_reg;
     701             :       }
     702             : 
     703             :       // We cannot rename 'Reg' to 'NewReg' if one of the uses of 'Reg' also
     704             :       // defines 'NewReg' via an early-clobber operand.
     705        7766 :       for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
     706        5221 :         MachineInstr *UseMI = Q.second.Operand->getParent();
     707        5221 :         int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI);
     708        5221 :         if (Idx == -1)
     709        5201 :           continue;
     710             : 
     711          40 :         if (UseMI->getOperand(Idx).isEarlyClobber()) {
     712             :           LLVM_DEBUG(dbgs() << "(ec)");
     713             :           goto next_super_reg;
     714             :         }
     715             :       }
     716             : 
     717             :       // Also, we cannot rename 'Reg' to 'NewReg' if the instruction defining
     718             :       // 'Reg' is an early-clobber define and that instruction also uses
     719             :       // 'NewReg'.
     720        7766 :       for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
     721       18136 :         if (!Q.second.Operand->isDef() || !Q.second.Operand->isEarlyClobber())
     722        5221 :           continue;
     723             : 
     724           0 :         MachineInstr *DefMI = Q.second.Operand->getParent();
     725           0 :         if (DefMI->readsRegister(NewReg, TRI)) {
     726             :           LLVM_DEBUG(dbgs() << "(ec)");
     727             :           goto next_super_reg;
     728             :         }
     729             :       }
     730             : 
     731             :       // Record that 'Reg' can be renamed to 'NewReg'.
     732        2545 :       RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
     733             :     }
     734             : 
     735             :     // If we fall-out here, then every register in the group can be
     736             :     // renamed, as recorded in RenameMap.
     737             :     RenameOrder.erase(SuperRC);
     738        2361 :     RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
     739             :     LLVM_DEBUG(dbgs() << "]\n");
     740        2361 :     return true;
     741             : 
     742       16471 :   next_super_reg:
     743             :     LLVM_DEBUG(dbgs() << ']');
     744       16471 :   } while (R != EndR);
     745             : 
     746             :   LLVM_DEBUG(dbgs() << '\n');
     747             : 
     748             :   // No registers are free and available!
     749             :   return false;
     750             : }
     751             : 
     752             : /// BreakAntiDependencies - Identifiy anti-dependencies within the
     753             : /// ScheduleDAG and break them by renaming registers.
     754       38483 : unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
     755             :                               const std::vector<SUnit> &SUnits,
     756             :                               MachineBasicBlock::iterator Begin,
     757             :                               MachineBasicBlock::iterator End,
     758             :                               unsigned InsertPosIndex,
     759             :                               DbgValueVector &DbgValues) {
     760       38483 :   std::vector<unsigned> &KillIndices = State->GetKillIndices();
     761             :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     762             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
     763             :     RegRefs = State->GetRegRefs();
     764             : 
     765             :   // The code below assumes that there is at least one instruction,
     766             :   // so just duck out immediately if the block is empty.
     767       38483 :   if (SUnits.empty()) return 0;
     768             : 
     769             :   // For each regclass the next register to use for renaming.
     770             :   RenameOrderType RenameOrder;
     771             : 
     772             :   // ...need a map from MI to SUnit.
     773             :   std::map<MachineInstr *, const SUnit *> MISUnitMap;
     774       90009 :   for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
     775       71637 :     const SUnit *SU = &SUnits[i];
     776      143274 :     MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
     777             :                                                                SU));
     778             :   }
     779             : 
     780             :   // Track progress along the critical path through the SUnit graph as
     781             :   // we walk the instructions. This is needed for regclasses that only
     782             :   // break critical-path anti-dependencies.
     783             :   const SUnit *CriticalPathSU = nullptr;
     784             :   MachineInstr *CriticalPathMI = nullptr;
     785       18372 :   if (CriticalPathSet.any()) {
     786       76678 :     for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
     787       50332 :       const SUnit *SU = &SUnits[i];
     788       87491 :       if (!CriticalPathSU ||
     789       37159 :           ((SU->getDepth() + SU->Latency) >
     790       37159 :            (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
     791             :         CriticalPathSU = SU;
     792             :       }
     793             :     }
     794             : 
     795       13173 :     CriticalPathMI = CriticalPathSU->getInstr();
     796             :   }
     797             : 
     798             : #ifndef NDEBUG
     799             :   LLVM_DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
     800             :   LLVM_DEBUG(dbgs() << "Available regs:");
     801             :   for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
     802             :     if (!State->IsLive(Reg))
     803             :       LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
     804             :   }
     805             :   LLVM_DEBUG(dbgs() << '\n');
     806             : #endif
     807             : 
     808       18372 :   BitVector RegAliases(TRI->getNumRegs());
     809             : 
     810             :   // Attempt to break anti-dependence edges. Walk the instructions
     811             :   // from the bottom up, tracking information about liveness as we go
     812             :   // to help determine which registers are available.
     813             :   unsigned Broken = 0;
     814       18372 :   unsigned Count = InsertPosIndex - 1;
     815       90031 :   for (MachineBasicBlock::iterator I = End, E = Begin;
     816       90031 :        I != E; --Count) {
     817             :     MachineInstr &MI = *--I;
     818             : 
     819          22 :     if (MI.isDebugInstr())
     820          22 :       continue;
     821             : 
     822             :     LLVM_DEBUG(dbgs() << "Anti: ");
     823             :     LLVM_DEBUG(MI.dump());
     824             : 
     825             :     std::set<unsigned> PassthruRegs;
     826       71637 :     GetPassthruRegs(MI, PassthruRegs);
     827             : 
     828             :     // Process the defs in MI...
     829       71637 :     PrescanInstruction(MI, Count, PassthruRegs);
     830             : 
     831             :     // The dependence edges that represent anti- and output-
     832             :     // dependencies that are candidates for breaking.
     833             :     std::vector<const SDep *> Edges;
     834       71637 :     const SUnit *PathSU = MISUnitMap[&MI];
     835       71637 :     AntiDepEdges(PathSU, Edges);
     836             : 
     837             :     // If MI is not on the critical path, then we don't rename
     838             :     // registers in the CriticalPathSet.
     839             :     BitVector *ExcludeRegs = nullptr;
     840       71637 :     if (&MI == CriticalPathMI) {
     841       32262 :       CriticalPathSU = CriticalPathStep(CriticalPathSU);
     842       32262 :       CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr;
     843       39375 :     } else if (CriticalPathSet.any()) {
     844       18070 :       ExcludeRegs = &CriticalPathSet;
     845             :     }
     846             : 
     847             :     // Ignore KILL instructions (they form a group in ScanInstruction
     848             :     // but don't cause any anti-dependence breaking themselves)
     849       71637 :     if (!MI.isKill()) {
     850             :       // Attempt to break each anti-dependency...
     851      167842 :       for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
     852       49856 :         const SDep *Edge = Edges[i];
     853             :         SUnit *NextSU = Edge->getSUnit();
     854             : 
     855       24928 :         if ((Edge->getKind() != SDep::Anti) &&
     856       22234 :             (Edge->getKind() != SDep::Output)) continue;
     857             : 
     858       24928 :         unsigned AntiDepReg = Edge->getReg();
     859             :         LLVM_DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
     860             :         assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
     861             : 
     862       25256 :         if (!MRI.isAllocatable(AntiDepReg)) {
     863             :           // Don't break anti-dependencies on non-allocatable registers.
     864             :           LLVM_DEBUG(dbgs() << " (non-allocatable)\n");
     865         328 :           continue;
     866       35171 :         } else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
     867             :           // Don't break anti-dependencies for critical path registers
     868             :           // if not on the critical path
     869             :           LLVM_DEBUG(dbgs() << " (not critical-path)\n");
     870        3951 :           continue;
     871        2033 :         } else if (PassthruRegs.count(AntiDepReg) != 0) {
     872             :           // If the anti-dep register liveness "passes-thru", then
     873             :           // don't try to change it. It will be changed along with
     874             :           // the use if required to break an earlier antidep.
     875             :           LLVM_DEBUG(dbgs() << " (passthru)\n");
     876        2033 :           continue;
     877             :         } else {
     878             :           // No anti-dep breaking for implicit deps
     879             :           MachineOperand *AntiDepOp = MI.findRegisterDefOperand(AntiDepReg);
     880             :           assert(AntiDepOp && "Can't find index for defined register operand");
     881       38245 :           if (!AntiDepOp || AntiDepOp->isImplicit()) {
     882             :             LLVM_DEBUG(dbgs() << " (implicit)\n");
     883        1013 :             continue;
     884             :           }
     885             : 
     886             :           // If the SUnit has other dependencies on the SUnit that
     887             :           // it anti-depends on, don't bother breaking the
     888             :           // anti-dependency since those edges would prevent such
     889             :           // units from being scheduled past each other
     890             :           // regardless.
     891             :           //
     892             :           // Also, if there are dependencies on other SUnits with the
     893             :           // same register as the anti-dependency, don't attempt to
     894             :           // break it.
     895       21421 :           for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
     896       39024 :                  PE = PathSU->Preds.end(); P != PE; ++P) {
     897       32916 :             if (P->getSUnit() == NextSU ?
     898       18292 :                 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
     899       14624 :                 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
     900             :               AntiDepReg = 0;
     901             :               break;
     902             :             }
     903             :           }
     904       32607 :           for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
     905       50210 :                  PE = PathSU->Preds.end(); P != PE; ++P) {
     906       71104 :             if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
     907             :                 (P->getKind() != SDep::Output)) {
     908             :               LLVM_DEBUG(dbgs() << " (real dependency)\n");
     909             :               AntiDepReg = 0;
     910             :               break;
     911       15616 :             } else if ((P->getSUnit() != NextSU) &&
     912       39173 :                        (P->getKind() == SDep::Data) &&
     913        6566 :                        (P->getReg() == AntiDepReg)) {
     914             :               LLVM_DEBUG(dbgs() << " (other dependency)\n");
     915             :               AntiDepReg = 0;
     916             :               break;
     917             :             }
     918             :           }
     919             : 
     920       17603 :           if (AntiDepReg == 0) continue;
     921             : 
     922             :           // If the definition of the anti-dependency register does not start
     923             :           // a new live range, bail out. This can happen if the anti-dep
     924             :           // register is a sub-register of another register whose live range
     925             :           // spans over PathSU. In such case, PathSU defines only a part of
     926             :           // the larger register.
     927             :           RegAliases.reset();
     928       41706 :           for (MCRegAliasIterator AI(AntiDepReg, TRI, true); AI.isValid(); ++AI)
     929             :             RegAliases.set(*AI);
     930       32088 :           for (SDep S : PathSU->Succs) {
     931             :             SDep::Kind K = S.getKind();
     932       13472 :             if (K != SDep::Data && K != SDep::Output && K != SDep::Anti)
     933        2642 :               continue;
     934             :             unsigned R = S.getReg();
     935       10830 :             if (!RegAliases[R])
     936        2078 :               continue;
     937       10922 :             if (R == AntiDepReg || TRI->isSubRegister(AntiDepReg, R))
     938        8270 :               continue;
     939             :             AntiDepReg = 0;
     940             :             break;
     941             :           }
     942             : 
     943        6108 :           if (AntiDepReg == 0) continue;
     944             :         }
     945             : 
     946             :         assert(AntiDepReg != 0);
     947             :         if (AntiDepReg == 0) continue;
     948             : 
     949             :         // Determine AntiDepReg's register group.
     950        5626 :         const unsigned GroupIndex = State->GetGroup(AntiDepReg);
     951        5626 :         if (GroupIndex == 0) {
     952             :           LLVM_DEBUG(dbgs() << " (zero group)\n");
     953        2932 :           continue;
     954             :         }
     955             : 
     956             :         LLVM_DEBUG(dbgs() << '\n');
     957             : 
     958             :         // Look for a suitable register to use to break the anti-dependence.
     959             :         std::map<unsigned, unsigned> RenameMap;
     960        2694 :         if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
     961             :           LLVM_DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
     962             :                             << printReg(AntiDepReg, TRI) << ":");
     963             : 
     964             :           // Handle each group register...
     965             :           for (std::map<unsigned, unsigned>::iterator
     966        4890 :                  S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
     967        2529 :             unsigned CurrReg = S->first;
     968        2529 :             unsigned NewReg = S->second;
     969             : 
     970             :             LLVM_DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
     971             :                               << printReg(NewReg, TRI) << "("
     972             :                               << RegRefs.count(CurrReg) << " refs)");
     973             : 
     974             :             // Update the references to the old register CurrReg to
     975             :             // refer to the new register NewReg.
     976        7732 :             for (const auto &Q : make_range(RegRefs.equal_range(CurrReg))) {
     977        5203 :               Q.second.Operand->setReg(NewReg);
     978             :               // If the SU for the instruction being updated has debug
     979             :               // information related to the anti-dependency register, make
     980             :               // sure to update that as well.
     981        5203 :               const SUnit *SU = MISUnitMap[Q.second.Operand->getParent()];
     982        5203 :               if (!SU) continue;
     983        5203 :               UpdateDbgValues(DbgValues, Q.second.Operand->getParent(),
     984             :                               AntiDepReg, NewReg);
     985             :             }
     986             : 
     987             :             // We just went back in time and modified history; the
     988             :             // liveness information for CurrReg is now inconsistent. Set
     989             :             // the state as if it were dead.
     990        2529 :             State->UnionGroups(NewReg, 0);
     991             :             RegRefs.erase(NewReg);
     992        7587 :             DefIndices[NewReg] = DefIndices[CurrReg];
     993        7587 :             KillIndices[NewReg] = KillIndices[CurrReg];
     994             : 
     995        2529 :             State->UnionGroups(CurrReg, 0);
     996             :             RegRefs.erase(CurrReg);
     997        7587 :             DefIndices[CurrReg] = KillIndices[CurrReg];
     998        5058 :             KillIndices[CurrReg] = ~0u;
     999             :             assert(((KillIndices[CurrReg] == ~0u) !=
    1000             :                     (DefIndices[CurrReg] == ~0u)) &&
    1001             :                    "Kill and Def maps aren't consistent for AntiDepReg!");
    1002             :           }
    1003             : 
    1004        2361 :           ++Broken;
    1005             :           LLVM_DEBUG(dbgs() << '\n');
    1006             :         }
    1007             :       }
    1008             :     }
    1009             : 
    1010       71637 :     ScanInstruction(MI, Count);
    1011             :   }
    1012             : 
    1013             :   return Broken;
    1014      297711 : }

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