LCOV - code coverage report
Current view: top level - lib/CodeGen - AggressiveAntiDepBreaker.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 336 342 98.2 %
Date: 2018-02-21 06:32:55 Functions: 22 24 91.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- AggressiveAntiDepBreaker.cpp - Anti-dep breaker --------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the AggressiveAntiDepBreaker class, which
      11             : // implements register anti-dependence breaking during post-RA
      12             : // scheduling. It attempts to break all anti-dependencies within a
      13             : // block.
      14             : //
      15             : //===----------------------------------------------------------------------===//
      16             : 
      17             : #include "AggressiveAntiDepBreaker.h"
      18             : #include "llvm/ADT/ArrayRef.h"
      19             : #include "llvm/ADT/BitVector.h"
      20             : #include "llvm/ADT/SmallSet.h"
      21             : #include "llvm/ADT/iterator_range.h"
      22             : #include "llvm/CodeGen/MachineBasicBlock.h"
      23             : #include "llvm/CodeGen/MachineFrameInfo.h"
      24             : #include "llvm/CodeGen/MachineFunction.h"
      25             : #include "llvm/CodeGen/MachineInstr.h"
      26             : #include "llvm/CodeGen/MachineOperand.h"
      27             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      28             : #include "llvm/CodeGen/MachineValueType.h"
      29             : #include "llvm/CodeGen/RegisterClassInfo.h"
      30             : #include "llvm/CodeGen/ScheduleDAG.h"
      31             : #include "llvm/CodeGen/TargetInstrInfo.h"
      32             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      33             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      34             : #include "llvm/MC/MCInstrDesc.h"
      35             : #include "llvm/MC/MCRegisterInfo.h"
      36             : #include "llvm/Support/CommandLine.h"
      37             : #include "llvm/Support/Debug.h"
      38             : #include "llvm/Support/raw_ostream.h"
      39             : #include <cassert>
      40             : #include <map>
      41             : #include <set>
      42             : #include <utility>
      43             : #include <vector>
      44             : 
      45             : using namespace llvm;
      46             : 
      47             : #define DEBUG_TYPE "post-RA-sched"
      48             : 
      49             : // If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod
      50             : static cl::opt<int>
      51       97171 : DebugDiv("agg-antidep-debugdiv",
      52       97171 :          cl::desc("Debug control for aggressive anti-dep breaker"),
      53      291513 :          cl::init(0), cl::Hidden);
      54             : 
      55             : static cl::opt<int>
      56       97171 : DebugMod("agg-antidep-debugmod",
      57       97171 :          cl::desc("Debug control for aggressive anti-dep breaker"),
      58      291513 :          cl::init(0), cl::Hidden);
      59             : 
      60       14662 : AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
      61       14662 :                                                MachineBasicBlock *BB)
      62             :     : NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
      63             :       GroupNodeIndices(TargetRegs, 0), KillIndices(TargetRegs, 0),
      64       29324 :       DefIndices(TargetRegs, 0) {
      65             :   const unsigned BBSize = BB->size();
      66     8227986 :   for (unsigned i = 0; i < NumTargetRegs; ++i) {
      67             :     // Initialize all registers to be in their own group. Initially we
      68             :     // assign the register to the same-indexed GroupNode.
      69     8213324 :     GroupNodeIndices[i] = i;
      70             :     // Initialize the indices to indicate that no registers are live.
      71     8213324 :     KillIndices[i] = ~0u;
      72     8213324 :     DefIndices[i] = BBSize;
      73             :   }
      74       14662 : }
      75             : 
      76           0 : unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
      77    16614022 :   unsigned Node = GroupNodeIndices[Reg];
      78    25378394 :   while (GroupNodes[Node] != Node)
      79             :     Node = GroupNodes[Node];
      80             : 
      81           0 :   return Node;
      82             : }
      83             : 
      84        2281 : void AggressiveAntiDepState::GetGroupRegs(
      85             :   unsigned Group,
      86             :   std::vector<unsigned> &Regs,
      87             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
      88             : {
      89      611712 :   for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
      90      613327 :     if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
      91        2520 :       Regs.push_back(Reg);
      92             :   }
      93        2281 : }
      94             : 
      95     3846777 : unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) {
      96             :   assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
      97             :   assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
      98             : 
      99             :   // find group for each register
     100             :   unsigned Group1 = GetGroup(Reg1);
     101             :   unsigned Group2 = GetGroup(Reg2);
     102             : 
     103             :   // if either group is 0, then that must become the parent
     104     3846777 :   unsigned Parent = (Group1 == 0) ? Group1 : Group2;
     105     3846777 :   unsigned Other = (Parent == Group1) ? Group2 : Group1;
     106     7693554 :   GroupNodes.at(Other) = Parent;
     107     3846777 :   return Parent;
     108             : }
     109             : 
     110      148458 : unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) {
     111             :   // Create a new GroupNode for Reg. Reg's existing GroupNode must
     112             :   // stay as is because there could be other GroupNodes referring to
     113             :   // it.
     114      296916 :   unsigned idx = GroupNodes.size();
     115      148458 :   GroupNodes.push_back(idx);
     116      296916 :   GroupNodeIndices[Reg] = idx;
     117      148458 :   return idx;
     118             : }
     119             : 
     120           0 : bool AggressiveAntiDepState::IsLive(unsigned Reg) {
     121             :   // KillIndex must be defined and DefIndex not defined for a register
     122             :   // to be live.
     123    13864845 :   return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
     124             : }
     125             : 
     126        9602 : AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(
     127             :     MachineFunction &MFi, const RegisterClassInfo &RCI,
     128        9602 :     TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
     129        9602 :     : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
     130        9602 :       TII(MF.getSubtarget().getInstrInfo()),
     131       38408 :       TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) {
     132             :   /* Collect a bitset of all registers that are only broken if they
     133             :      are on the critical path. */
     134       17373 :   for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
     135       15542 :     BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
     136        7771 :     if (CriticalPathSet.none())
     137        7771 :       CriticalPathSet = CPSet;
     138             :     else
     139           0 :       CriticalPathSet |= CPSet;
     140             :    }
     141             : 
     142             :   DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
     143             :   DEBUG(for (unsigned r : CriticalPathSet.set_bits())
     144             :           dbgs() << " " << printReg(r, TRI));
     145             :   DEBUG(dbgs() << '\n');
     146        9602 : }
     147             : 
     148       28806 : AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
     149        9602 :   delete State;
     150       19204 : }
     151             : 
     152       14662 : void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
     153             :   assert(!State);
     154       14662 :   State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
     155             : 
     156       14662 :   bool IsReturnBlock = BB->isReturnBlock();
     157       14662 :   std::vector<unsigned> &KillIndices = State->GetKillIndices();
     158             :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     159             : 
     160             :   // Examine the live-in regs of all successors.
     161             :   for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
     162       22126 :          SE = BB->succ_end(); SI != SE; ++SI)
     163       34993 :     for (const auto &LI : (*SI)->liveins()) {
     164      128822 :       for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
     165             :         unsigned Reg = *AI;
     166       44346 :         State->UnionGroups(Reg, 0);
     167       88692 :         KillIndices[Reg] = BB->size();
     168       88692 :         DefIndices[Reg] = ~0u;
     169             :       }
     170             :     }
     171             : 
     172             :   // Mark live-out callee-saved registers. In a return block this is
     173             :   // all callee-saved registers. In non-return this is any
     174             :   // callee-saved register that is not saved in the prolog.
     175       14662 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
     176       14662 :   BitVector Pristine = MFI.getPristineRegs(MF);
     177      635912 :   for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;
     178             :        ++I) {
     179      621250 :     unsigned Reg = *I;
     180      828190 :     if (!IsReturnBlock && !Pristine.test(Reg))
     181        7870 :       continue;
     182     4534438 :     for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
     183             :       unsigned AliasReg = *AI;
     184     1653839 :       State->UnionGroups(AliasReg, 0);
     185     3307678 :       KillIndices[AliasReg] = BB->size();
     186     3307678 :       DefIndices[AliasReg] = ~0u;
     187             :     }
     188             :   }
     189       14662 : }
     190             : 
     191       14662 : void AggressiveAntiDepBreaker::FinishBlock() {
     192       14662 :   delete State;
     193       14662 :   State = nullptr;
     194       14662 : }
     195             : 
     196       18484 : void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
     197             :                                        unsigned InsertPosIndex) {
     198             :   assert(Count < InsertPosIndex && "Instruction index out of expected range!");
     199             : 
     200             :   std::set<unsigned> PassthruRegs;
     201       18484 :   GetPassthruRegs(MI, PassthruRegs);
     202       18484 :   PrescanInstruction(MI, Count, PassthruRegs);
     203       18484 :   ScanInstruction(MI, Count);
     204             : 
     205             :   DEBUG(dbgs() << "Observe: ");
     206             :   DEBUG(MI.dump());
     207             :   DEBUG(dbgs() << "\tRegs:");
     208             : 
     209       18484 :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     210    10624392 :   for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
     211             :     // If Reg is current live, then mark that it can't be renamed as
     212             :     // we don't know the extent of its live-range anymore (now that it
     213             :     // has been scheduled). If it is not live but was defined in the
     214             :     // previous schedule region, then set its def index to the most
     215             :     // conservative location (i.e. the beginning of the previous
     216             :     // schedule region).
     217     5302954 :     if (State->IsLive(Reg)) {
     218             :       DEBUG(if (State->GetGroup(Reg) != 0)
     219             :               dbgs() << " " << printReg(Reg, TRI) << "=g" <<
     220             :                 State->GetGroup(Reg) << "->g0(region live-out)");
     221     2076967 :       State->UnionGroups(Reg, 0);
     222     6451974 :     } else if ((DefIndices[Reg] < InsertPosIndex)
     223     3225987 :                && (DefIndices[Reg] >= Count)) {
     224       25375 :       DefIndices[Reg] = Count;
     225             :     }
     226             :   }
     227             :   DEBUG(dbgs() << '\n');
     228       18484 : }
     229             : 
     230      196021 : bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI,
     231             :                                                 MachineOperand &MO) {
     232      392042 :   if (!MO.isReg() || !MO.isImplicit())
     233             :     return false;
     234             : 
     235       56101 :   unsigned Reg = MO.getReg();
     236       56101 :   if (Reg == 0)
     237             :     return false;
     238             : 
     239             :   MachineOperand *Op = nullptr;
     240       56101 :   if (MO.isDef())
     241             :     Op = MI.findRegisterUseOperand(Reg, true);
     242             :   else
     243             :     Op = MI.findRegisterDefOperand(Reg);
     244             : 
     245        4970 :   return(Op && Op->isImplicit());
     246             : }
     247             : 
     248       78557 : void AggressiveAntiDepBreaker::GetPassthruRegs(
     249             :     MachineInstr &MI, std::set<unsigned> &PassthruRegs) {
     250      330795 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     251      252238 :     MachineOperand &MO = MI.getOperand(i);
     252      252238 :     if (!MO.isReg()) continue;
     253      394906 :     if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) ||
     254      196021 :         IsImplicitDefUse(MI, MO)) {
     255        4963 :       const unsigned Reg = MO.getReg();
     256        4963 :       for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
     257       12026 :            SubRegs.isValid(); ++SubRegs)
     258       14126 :         PassthruRegs.insert(*SubRegs);
     259             :     }
     260             :   }
     261       78557 : }
     262             : 
     263             : /// AntiDepEdges - Return in Edges the anti- and output- dependencies
     264             : /// in SU that we want to consider for breaking.
     265       60073 : static void AntiDepEdges(const SUnit *SU, std::vector<const SDep *> &Edges) {
     266       60073 :   SmallSet<unsigned, 4> RegSet;
     267       98391 :   for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
     268      158464 :        P != PE; ++P) {
     269       98391 :     if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) {
     270       34594 :       if (RegSet.insert(P->getReg()).second)
     271       42666 :         Edges.push_back(&*P);
     272             :     }
     273             :   }
     274       60073 : }
     275             : 
     276             : /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
     277             : /// critical path.
     278       31536 : static const SUnit *CriticalPathStep(const SUnit *SU) {
     279             :   const SDep *Next = nullptr;
     280             :   unsigned NextDepth = 0;
     281             :   // Find the predecessor edge with the greatest depth.
     282       31536 :   if (SU) {
     283       48624 :     for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
     284       80160 :          P != PE; ++P) {
     285             :       const SUnit *PredSU = P->getSUnit();
     286       48624 :       unsigned PredLatency = P->getLatency();
     287       48624 :       unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
     288             :       // In the case of a latency tie, prefer an anti-dependency edge over
     289             :       // other types of edges.
     290       48624 :       if (NextDepth < PredTotalLatency ||
     291        9508 :           (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
     292             :         NextDepth = PredTotalLatency;
     293             :         Next = &*P;
     294             :       }
     295             :     }
     296             :   }
     297             : 
     298       63072 :   return (Next) ? Next->getSUnit() : nullptr;
     299             : }
     300             : 
     301      198885 : void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
     302             :                                              const char *tag,
     303             :                                              const char *header,
     304             :                                              const char *footer) {
     305      198885 :   std::vector<unsigned> &KillIndices = State->GetKillIndices();
     306             :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     307             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
     308             :     RegRefs = State->GetRegRefs();
     309             : 
     310             :   // FIXME: We must leave subregisters of live super registers as live, so that
     311             :   // we don't clear out the register tracking information for subregisters of
     312             :   // super registers we're still tracking (and with which we're unioning
     313             :   // subregister definitions).
     314     1223948 :   for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
     315      858812 :     if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
     316             :       DEBUG(if (!header && footer) dbgs() << footer);
     317       16317 :       return;
     318             :     }
     319             : 
     320      182568 :   if (!State->IsLive(Reg)) {
     321      193986 :     KillIndices[Reg] = KillIdx;
     322      193986 :     DefIndices[Reg] = ~0u;
     323             :     RegRefs.erase(Reg);
     324       96993 :     State->LeaveGroup(Reg);
     325             :     DEBUG(if (header) {
     326             :         dbgs() << header << printReg(Reg, TRI); header = nullptr; });
     327             :     DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
     328             :     // Repeat for subregisters. Note that we only do this if the superregister
     329             :     // was not live because otherwise, regardless whether we have an explicit
     330             :     // use of the subregister, the subregister's contents are needed for the
     331             :     // uses of the superregister.
     332      248731 :     for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
     333       54745 :       unsigned SubregReg = *SubRegs;
     334       54745 :       if (!State->IsLive(SubregReg)) {
     335      102930 :         KillIndices[SubregReg] = KillIdx;
     336      102930 :         DefIndices[SubregReg] = ~0u;
     337             :         RegRefs.erase(SubregReg);
     338       51465 :         State->LeaveGroup(SubregReg);
     339             :         DEBUG(if (header) {
     340             :             dbgs() << header << printReg(Reg, TRI); header = nullptr; });
     341             :         DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" <<
     342             :               State->GetGroup(SubregReg) << tag);
     343             :       }
     344             :     }
     345             :   }
     346             : 
     347             :   DEBUG(if (!header && footer) dbgs() << footer);
     348             : }
     349             : 
     350       78557 : void AggressiveAntiDepBreaker::PrescanInstruction(
     351             :     MachineInstr &MI, unsigned Count, std::set<unsigned> &PassthruRegs) {
     352       78557 :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     353             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
     354             :     RegRefs = State->GetRegRefs();
     355             : 
     356             :   // Handle dead defs by simulating a last-use of the register just
     357             :   // after the def. A dead def can occur because the def is truly
     358             :   // dead, or because only a subregister is live at the def. If we
     359             :   // don't do this the dead def will be incorrectly merged into the
     360             :   // previous def.
     361      330795 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     362      252238 :     MachineOperand &MO = MI.getOperand(i);
     363      451123 :     if (!MO.isReg() || !MO.isDef()) continue;
     364       65508 :     unsigned Reg = MO.getReg();
     365       65508 :     if (Reg == 0) continue;
     366             : 
     367       65508 :     HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
     368             :   }
     369             : 
     370             :   DEBUG(dbgs() << "\tDef Groups:");
     371      330795 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     372      252238 :     MachineOperand &MO = MI.getOperand(i);
     373      637853 :     if (!MO.isReg() || !MO.isDef()) continue;
     374       65508 :     unsigned Reg = MO.getReg();
     375       65508 :     if (Reg == 0) continue;
     376             : 
     377             :     DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg));
     378             : 
     379             :     // If MI's defs have a special allocation requirement, don't allow
     380             :     // any def registers to be changed. Also assume all registers
     381             :     // defined in a call must not be changed (ABI). Inline assembly may
     382             :     // reference either system calls or the register directly. Skip it until we
     383             :     // can tell user specified registers from compiler-specified.
     384      185929 :     if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) ||
     385             :         MI.isInlineAsm()) {
     386             :       DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
     387        7107 :       State->UnionGroups(Reg, 0);
     388             :     }
     389             : 
     390             :     // Any aliased that are live at this point are completely or
     391             :     // partially defined here, so group those aliases with Reg.
     392      294144 :     for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
     393             :       unsigned AliasReg = *AI;
     394       81564 :       if (State->IsLive(AliasReg)) {
     395       50999 :         State->UnionGroups(Reg, AliasReg);
     396             :         DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via "
     397             :                      << printReg(AliasReg, TRI) << ")");
     398             :       }
     399             :     }
     400             : 
     401             :     // Note register reference...
     402             :     const TargetRegisterClass *RC = nullptr;
     403      131016 :     if (i < MI.getDesc().getNumOperands())
     404       50708 :       RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
     405             :     AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
     406       65508 :     RegRefs.insert(std::make_pair(Reg, RR));
     407             :   }
     408             : 
     409             :   DEBUG(dbgs() << '\n');
     410             : 
     411             :   // Scan the register defs for this instruction and update
     412             :   // live-ranges.
     413      330795 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     414      252238 :     MachineOperand &MO = MI.getOperand(i);
     415      637853 :     if (!MO.isReg() || !MO.isDef()) continue;
     416       65508 :     unsigned Reg = MO.getReg();
     417       65508 :     if (Reg == 0) continue;
     418             :     // Ignore KILLs and passthru registers for liveness...
     419       70564 :     if (MI.isKill() || (PassthruRegs.count(Reg) != 0))
     420        5056 :       continue;
     421             : 
     422             :     // Update def for Reg and aliases.
     423      473566 :     for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
     424             :       // We need to be careful here not to define already-live super registers.
     425             :       // If the super register is already live, then this definition is not
     426             :       // a definition of the whole super register (just a partial insertion
     427             :       // into it). Earlier subregister definitions (which we've not yet visited
     428             :       // because we're iterating bottom-up) need to be linked to the same group
     429             :       // as this definition.
     430      300152 :       if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
     431        7942 :         continue;
     432             : 
     433      276326 :       DefIndices[*AI] = Count;
     434             :     }
     435             :   }
     436       78557 : }
     437             : 
     438       78557 : void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
     439             :                                                unsigned Count) {
     440             :   DEBUG(dbgs() << "\tUse Groups:");
     441             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
     442       78557 :     RegRefs = State->GetRegRefs();
     443             : 
     444             :   // If MI's uses have special allocation requirement, don't allow
     445             :   // any use registers to be changed. Also assume all registers
     446             :   // used in a call must not be changed (ABI).
     447             :   // Inline Assembly register uses also cannot be safely changed.
     448             :   // FIXME: The issue with predicated instruction is more complex. We are being
     449             :   // conservatively here because the kill markers cannot be trusted after
     450             :   // if-conversion:
     451             :   // %r6 = LDR %sp, %reg0, 92, 14, %reg0; mem:LD4[FixedStack14]
     452             :   // ...
     453             :   // STR %r0, killed %r6, %reg0, 0, 0, %cpsr; mem:ST4[%395]
     454             :   // %r6 = LDR %sp, %reg0, 100, 0, %cpsr; mem:LD4[FixedStack12]
     455             :   // STR %r0, killed %r6, %reg0, 0, 14, %reg0; mem:ST4[%396](align=8)
     456             :   //
     457             :   // The first R6 kill is not really a kill since it's killed by a predicated
     458             :   // instruction which may not be executed. The second R6 def may or may not
     459             :   // re-define R6 so it's not safe to change it since the last R6 use cannot be
     460             :   // changed.
     461      153575 :   bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() ||
     462      231174 :                  TII->isPredicated(MI) || MI.isInlineAsm();
     463             : 
     464             :   // Scan the register uses for this instruction and update
     465             :   // live-ranges, groups and RegRefs.
     466      330795 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     467      252238 :     MachineOperand &MO = MI.getOperand(i);
     468      451123 :     if (!MO.isReg() || !MO.isUse()) continue;
     469      133377 :     unsigned Reg = MO.getReg();
     470      133377 :     if (Reg == 0) continue;
     471             : 
     472             :     DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg));
     473             : 
     474             :     // It wasn't previously live but now it is, this is a kill. Forget
     475             :     // the previous live-range information and start a new live-range
     476             :     // for the register.
     477      133377 :     HandleLastUse(Reg, Count, "(last-use)");
     478             : 
     479      133377 :     if (Special) {
     480             :       DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
     481        8829 :       State->UnionGroups(Reg, 0);
     482             :     }
     483             : 
     484             :     // Note register reference...
     485             :     const TargetRegisterClass *RC = nullptr;
     486      266754 :     if (i < MI.getDesc().getNumOperands())
     487       91087 :       RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
     488             :     AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
     489      133377 :     RegRefs.insert(std::make_pair(Reg, RR));
     490             :   }
     491             : 
     492             :   DEBUG(dbgs() << '\n');
     493             : 
     494             :   // Form a group of all defs and uses of a KILL instruction to ensure
     495             :   // that all registers are renamed as a group.
     496       78557 :   if (MI.isKill()) {
     497             :     DEBUG(dbgs() << "\tKill Group:");
     498             : 
     499             :     unsigned FirstReg = 0;
     500         712 :     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     501         532 :       MachineOperand &MO = MI.getOperand(i);
     502         532 :       if (!MO.isReg()) continue;
     503         532 :       unsigned Reg = MO.getReg();
     504         532 :       if (Reg == 0) continue;
     505             : 
     506         532 :       if (FirstReg != 0) {
     507             :         DEBUG(dbgs() << "=" << printReg(Reg, TRI));
     508         352 :         State->UnionGroups(FirstReg, Reg);
     509             :       } else {
     510             :         DEBUG(dbgs() << " " << printReg(Reg, TRI));
     511             :         FirstReg = Reg;
     512             :       }
     513             :     }
     514             : 
     515             :     DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
     516             :   }
     517       78557 : }
     518             : 
     519        2520 : BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
     520        2520 :   BitVector BV(TRI->getNumRegs(), false);
     521             :   bool first = true;
     522             : 
     523             :   // Check all references that need rewriting for Reg. For each, use
     524             :   // the corresponding register class to narrow the set of registers
     525             :   // that are appropriate for renaming.
     526       10327 :   for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) {
     527        5287 :     const TargetRegisterClass *RC = Q.second.RC;
     528        5287 :     if (!RC) continue;
     529             : 
     530        5146 :     BitVector RCBV = TRI->getAllocatableSet(MF, RC);
     531        5146 :     if (first) {
     532        2520 :       BV |= RCBV;
     533             :       first = false;
     534             :     } else {
     535        2626 :       BV &= RCBV;
     536             :     }
     537             : 
     538             :     DEBUG(dbgs() << " " << TRI->getRegClassName(RC));
     539             :   }
     540             : 
     541        2520 :   return BV;
     542             : }
     543             : 
     544        2281 : bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
     545             :                                 unsigned AntiDepGroupIndex,
     546             :                                 RenameOrderType& RenameOrder,
     547             :                                 std::map<unsigned, unsigned> &RenameMap) {
     548        2281 :   std::vector<unsigned> &KillIndices = State->GetKillIndices();
     549             :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     550             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
     551             :     RegRefs = State->GetRegRefs();
     552             : 
     553             :   // Collect all referenced registers in the same group as
     554             :   // AntiDepReg. These all need to be renamed together if we are to
     555             :   // break the anti-dependence.
     556             :   std::vector<unsigned> Regs;
     557        2281 :   State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
     558             :   assert(!Regs.empty() && "Empty register group!");
     559        2281 :   if (Regs.empty())
     560             :     return false;
     561             : 
     562             :   // Find the "superest" register in the group. At the same time,
     563             :   // collect the BitVector of registers that can be used to rename
     564             :   // each register.
     565             :   DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
     566             :         << ":\n");
     567             :   std::map<unsigned, BitVector> RenameRegisterMap;
     568             :   unsigned SuperReg = 0;
     569        4801 :   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
     570        5040 :     unsigned Reg = Regs[i];
     571        2520 :     if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
     572        2407 :       SuperReg = Reg;
     573             : 
     574             :     // If Reg has any references, then collect possible rename regs
     575        2520 :     if (RegRefs.count(Reg) > 0) {
     576             :       DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
     577             : 
     578        2520 :       BitVector &BV = RenameRegisterMap[Reg];
     579             :       assert(BV.empty());
     580        5040 :       BV = GetRenameRegisters(Reg);
     581             : 
     582             :       DEBUG({
     583             :         dbgs() << " ::";
     584             :         for (unsigned r : BV.set_bits())
     585             :           dbgs() << " " << printReg(r, TRI);
     586             :         dbgs() << "\n";
     587             :       });
     588             :     }
     589             :   }
     590             : 
     591             :   // All group registers should be a subreg of SuperReg.
     592        7082 :   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
     593        5040 :     unsigned Reg = Regs[i];
     594        2520 :     if (Reg == SuperReg) continue;
     595         239 :     bool IsSub = TRI->isSubRegister(SuperReg, Reg);
     596             :     // FIXME: remove this once PR18663 has been properly fixed. For now,
     597             :     // return a conservative answer:
     598             :     // assert(IsSub && "Expecting group subregister");
     599         239 :     if (!IsSub)
     600             :       return false;
     601             :   }
     602             : 
     603             : #ifndef NDEBUG
     604             :   // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
     605             :   if (DebugDiv > 0) {
     606             :     static int renamecnt = 0;
     607             :     if (renamecnt++ % DebugDiv != DebugMod)
     608             :       return false;
     609             : 
     610             :     dbgs() << "*** Performing rename " << printReg(SuperReg, TRI)
     611             :            << " for debug ***\n";
     612             :   }
     613             : #endif
     614             : 
     615             :   // Check each possible rename register for SuperReg in round-robin
     616             :   // order. If that register is available, and the corresponding
     617             :   // registers are available for the other group subregisters, then we
     618             :   // can use those registers to rename.
     619             : 
     620             :   // FIXME: Using getMinimalPhysRegClass is very conservative. We should
     621             :   // check every use of the register and find the largest register class
     622             :   // that can be used in all of them.
     623             :   const TargetRegisterClass *SuperRC =
     624        4562 :     TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
     625             : 
     626        2281 :   ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
     627        2281 :   if (Order.empty()) {
     628             :     DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
     629             :     return false;
     630             :   }
     631             : 
     632             :   DEBUG(dbgs() << "\tFind Registers:");
     633             : 
     634        2281 :   RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
     635             : 
     636        2281 :   unsigned OrigR = RenameOrder[SuperRC];
     637        2281 :   unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR);
     638             :   unsigned R = OrigR;
     639             :   do {
     640       17175 :     if (R == 0) R = Order.size();
     641       17175 :     --R;
     642       34350 :     const unsigned NewSuperReg = Order[R];
     643             :     // Don't consider non-allocatable registers
     644       17175 :     if (!MRI.isAllocatable(NewSuperReg)) continue;
     645             :     // Don't replace a register with itself.
     646       17175 :     if (NewSuperReg == SuperReg) continue;
     647             : 
     648             :     DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':');
     649             :     RenameMap.clear();
     650             : 
     651             :     // For each referenced group register (which must be a SuperReg or
     652             :     // a subregister of SuperReg), find the corresponding subregister
     653             :     // of NewSuperReg and make sure it is free to be renamed.
     654       35536 :     for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
     655       33726 :       unsigned Reg = Regs[i];
     656             :       unsigned NewReg = 0;
     657       16863 :       if (Reg == SuperReg) {
     658             :         NewReg = NewSuperReg;
     659             :       } else {
     660         369 :         unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
     661         369 :         if (NewSubRegIdx != 0)
     662         369 :           NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
     663             :       }
     664             : 
     665             :       DEBUG(dbgs() << " " << printReg(NewReg, TRI));
     666             : 
     667             :       // Check if Reg can be renamed to NewReg.
     668       33726 :       if (!RenameRegisterMap[Reg].test(NewReg)) {
     669             :         DEBUG(dbgs() << "(no rename)");
     670       14681 :         goto next_super_reg;
     671             :       }
     672             : 
     673             :       // If NewReg is dead and NewReg's most recent def is not before
     674             :       // Regs's kill, it's safe to replace Reg with NewReg. We
     675             :       // must also check all aliases of NewReg, because we can't define a
     676             :       // register when any sub or super is already live.
     677       25475 :       if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
     678             :         DEBUG(dbgs() << "(live)");
     679             :         goto next_super_reg;
     680             :       } else {
     681             :         bool found = false;
     682       10336 :         for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
     683             :           unsigned AliasReg = *AI;
     684        5782 :           if (State->IsLive(AliasReg) ||
     685        8388 :               (KillIndices[Reg] > DefIndices[AliasReg])) {
     686             :             DEBUG(dbgs() << "(alias " << printReg(AliasReg, TRI) << " live)");
     687             :             found = true;
     688             :             break;
     689             :           }
     690             :         }
     691        2480 :         if (found)
     692             :           goto next_super_reg;
     693             :       }
     694             : 
     695             :       // We cannot rename 'Reg' to 'NewReg' if one of the uses of 'Reg' also
     696             :       // defines 'NewReg' via an early-clobber operand.
     697        6620 :       for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
     698        4438 :         MachineInstr *UseMI = Q.second.Operand->getParent();
     699        4438 :         int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI);
     700        4438 :         if (Idx == -1)
     701        4428 :           continue;
     702             : 
     703          20 :         if (UseMI->getOperand(Idx).isEarlyClobber()) {
     704             :           DEBUG(dbgs() << "(ec)");
     705             :           goto next_super_reg;
     706             :         }
     707             :       }
     708             : 
     709             :       // Also, we cannot rename 'Reg' to 'NewReg' if the instruction defining
     710             :       // 'Reg' is an early-clobber define and that instruction also uses
     711             :       // 'NewReg'.
     712        6620 :       for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
     713       15390 :         if (!Q.second.Operand->isDef() || !Q.second.Operand->isEarlyClobber())
     714        4438 :           continue;
     715             : 
     716           0 :         MachineInstr *DefMI = Q.second.Operand->getParent();
     717           0 :         if (DefMI->readsRegister(NewReg, TRI)) {
     718             :           DEBUG(dbgs() << "(ec)");
     719             :           goto next_super_reg;
     720             :         }
     721             :       }
     722             : 
     723             :       // Record that 'Reg' can be renamed to 'NewReg'.
     724        2182 :       RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
     725             :     }
     726             : 
     727             :     // If we fall-out here, then every register in the group can be
     728             :     // renamed, as recorded in RenameMap.
     729             :     RenameOrder.erase(SuperRC);
     730        1996 :     RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
     731             :     DEBUG(dbgs() << "]\n");
     732        1996 :     return true;
     733             : 
     734       15179 :   next_super_reg:
     735             :     DEBUG(dbgs() << ']');
     736       15179 :   } while (R != EndR);
     737             : 
     738             :   DEBUG(dbgs() << '\n');
     739             : 
     740             :   // No registers are free and available!
     741             :   return false;
     742             : }
     743             : 
     744             : /// BreakAntiDependencies - Identifiy anti-dependencies within the
     745             : /// ScheduleDAG and break them by renaming registers.
     746       33146 : unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
     747             :                               const std::vector<SUnit> &SUnits,
     748             :                               MachineBasicBlock::iterator Begin,
     749             :                               MachineBasicBlock::iterator End,
     750             :                               unsigned InsertPosIndex,
     751             :                               DbgValueVector &DbgValues) {
     752       33146 :   std::vector<unsigned> &KillIndices = State->GetKillIndices();
     753             :   std::vector<unsigned> &DefIndices = State->GetDefIndices();
     754             :   std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
     755             :     RegRefs = State->GetRegRefs();
     756             : 
     757             :   // The code below assumes that there is at least one instruction,
     758             :   // so just duck out immediately if the block is empty.
     759       33146 :   if (SUnits.empty()) return 0;
     760             : 
     761             :   // For each regclass the next register to use for renaming.
     762             :   RenameOrderType RenameOrder;
     763             : 
     764             :   // ...need a map from MI to SUnit.
     765             :   std::map<MachineInstr *, const SUnit *> MISUnitMap;
     766       75616 :   for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
     767       60073 :     const SUnit *SU = &SUnits[i];
     768      120146 :     MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
     769             :                                                                SU));
     770             :   }
     771             : 
     772             :   // Track progress along the critical path through the SUnit graph as
     773             :   // we walk the instructions. This is needed for regclasses that only
     774             :   // break critical-path anti-dependencies.
     775             :   const SUnit *CriticalPathSU = nullptr;
     776             :   MachineInstr *CriticalPathMI = nullptr;
     777       15543 :   if (CriticalPathSet.any()) {
     778       75251 :     for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
     779       49479 :       const SUnit *SU = &SUnits[i];
     780       86072 :       if (!CriticalPathSU ||
     781       36593 :           ((SU->getDepth() + SU->Latency) >
     782       36593 :            (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
     783             :         CriticalPathSU = SU;
     784             :       }
     785             :     }
     786             : 
     787       12886 :     CriticalPathMI = CriticalPathSU->getInstr();
     788             :   }
     789             : 
     790             : #ifndef NDEBUG
     791             :   DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
     792             :   DEBUG(dbgs() << "Available regs:");
     793             :   for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
     794             :     if (!State->IsLive(Reg))
     795             :       DEBUG(dbgs() << " " << printReg(Reg, TRI));
     796             :   }
     797             :   DEBUG(dbgs() << '\n');
     798             : #endif
     799             : 
     800       15543 :   BitVector RegAliases(TRI->getNumRegs());
     801             : 
     802             :   // Attempt to break anti-dependence edges. Walk the instructions
     803             :   // from the bottom up, tracking information about liveness as we go
     804             :   // to help determine which registers are available.
     805             :   unsigned Broken = 0;
     806       15543 :   unsigned Count = InsertPosIndex - 1;
     807       75631 :   for (MachineBasicBlock::iterator I = End, E = Begin;
     808       75631 :        I != E; --Count) {
     809             :     MachineInstr &MI = *--I;
     810             : 
     811       60088 :     if (MI.isDebugValue())
     812          15 :       continue;
     813             : 
     814             :     DEBUG(dbgs() << "Anti: ");
     815             :     DEBUG(MI.dump());
     816             : 
     817             :     std::set<unsigned> PassthruRegs;
     818       60073 :     GetPassthruRegs(MI, PassthruRegs);
     819             : 
     820             :     // Process the defs in MI...
     821       60073 :     PrescanInstruction(MI, Count, PassthruRegs);
     822             : 
     823             :     // The dependence edges that represent anti- and output-
     824             :     // dependencies that are candidates for breaking.
     825             :     std::vector<const SDep *> Edges;
     826       60073 :     const SUnit *PathSU = MISUnitMap[&MI];
     827       60073 :     AntiDepEdges(PathSU, Edges);
     828             : 
     829             :     // If MI is not on the critical path, then we don't rename
     830             :     // registers in the CriticalPathSet.
     831             :     BitVector *ExcludeRegs = nullptr;
     832       60073 :     if (&MI == CriticalPathMI) {
     833       31536 :       CriticalPathSU = CriticalPathStep(CriticalPathSU);
     834       31536 :       CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr;
     835       28537 :     } else if (CriticalPathSet.any()) {
     836       17943 :       ExcludeRegs = &CriticalPathSet;
     837             :     }
     838             : 
     839             :     // Ignore KILL instructions (they form a group in ScanInstruction
     840             :     // but don't cause any anti-dependence breaking themselves)
     841       60073 :     if (!MI.isKill()) {
     842             :       // Attempt to break each anti-dependency...
     843      141071 :       for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
     844       42570 :         const SDep *Edge = Edges[i];
     845             :         SUnit *NextSU = Edge->getSUnit();
     846             : 
     847       21285 :         if ((Edge->getKind() != SDep::Anti) &&
     848       19004 :             (Edge->getKind() != SDep::Output)) continue;
     849             : 
     850       21285 :         unsigned AntiDepReg = Edge->getReg();
     851             :         DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
     852             :         assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
     853             : 
     854       21493 :         if (!MRI.isAllocatable(AntiDepReg)) {
     855             :           // Don't break anti-dependencies on non-allocatable registers.
     856             :           DEBUG(dbgs() << " (non-allocatable)\n");
     857         208 :           continue;
     858       31731 :         } else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
     859             :           // Don't break anti-dependencies for critical path registers
     860             :           // if not on the critical path
     861             :           DEBUG(dbgs() << " (not critical-path)\n");
     862        3946 :           continue;
     863        1349 :         } else if (PassthruRegs.count(AntiDepReg) != 0) {
     864             :           // If the anti-dep register liveness "passes-thru", then
     865             :           // don't try to change it. It will be changed along with
     866             :           // the use if required to break an earlier antidep.
     867             :           DEBUG(dbgs() << " (passthru)\n");
     868        1349 :           continue;
     869             :         } else {
     870             :           // No anti-dep breaking for implicit deps
     871             :           MachineOperand *AntiDepOp = MI.findRegisterDefOperand(AntiDepReg);
     872             :           assert(AntiDepOp && "Can't find index for defined register operand");
     873       32586 :           if (!AntiDepOp || AntiDepOp->isImplicit()) {
     874             :             DEBUG(dbgs() << " (implicit)\n");
     875        1022 :             continue;
     876             :           }
     877             : 
     878             :           // If the SUnit has other dependencies on the SUnit that
     879             :           // it anti-depends on, don't bother breaking the
     880             :           // anti-dependency since those edges would prevent such
     881             :           // units from being scheduled past each other
     882             :           // regardless.
     883             :           //
     884             :           // Also, if there are dependencies on other SUnits with the
     885             :           // same register as the anti-dependency, don't attempt to
     886             :           // break it.
     887       16572 :           for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
     888       31332 :                  PE = PathSU->Preds.end(); P != PE; ++P) {
     889       27006 :             if (P->getSUnit() == NextSU ?
     890       15421 :                 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
     891       11585 :                 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
     892             :               AntiDepReg = 0;
     893             :               break;
     894             :             }
     895             :           }
     896       27085 :           for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
     897       41845 :                  PE = PathSU->Preds.end(); P != PE; ++P) {
     898       60858 :             if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
     899             :                 (P->getKind() != SDep::Output)) {
     900             :               DEBUG(dbgs() << " (real dependency)\n");
     901             :               AntiDepReg = 0;
     902             :               break;
     903       12826 :             } else if ((P->getSUnit() != NextSU) &&
     904       32538 :                        (P->getKind() == SDep::Data) &&
     905        5453 :                        (P->getReg() == AntiDepReg)) {
     906             :               DEBUG(dbgs() << " (other dependency)\n");
     907             :               AntiDepReg = 0;
     908             :               break;
     909             :             }
     910             :           }
     911             : 
     912       14760 :           if (AntiDepReg == 0) continue;
     913             : 
     914             :           // If the definition of the anti-dependency register does not start
     915             :           // a new live range, bail out. This can happen if the anti-dep
     916             :           // register is a sub-register of another register whose live range
     917             :           // spans over PathSU. In such case, PathSU defines only a part of
     918             :           // the larger register.
     919             :           RegAliases.reset();
     920       29330 :           for (MCRegAliasIterator AI(AntiDepReg, TRI, true); AI.isValid(); ++AI)
     921             :             RegAliases.set(*AI);
     922       24312 :           for (SDep S : PathSU->Succs) {
     923             :             SDep::Kind K = S.getKind();
     924       10293 :             if (K != SDep::Data && K != SDep::Output && K != SDep::Anti)
     925        1645 :               continue;
     926             :             unsigned R = S.getReg();
     927        8648 :             if (!RegAliases[R])
     928        1654 :               continue;
     929        8815 :             if (R == AntiDepReg || TRI->isSubRegister(AntiDepReg, R))
     930        6694 :               continue;
     931             :             AntiDepReg = 0;
     932             :             break;
     933             :           }
     934             : 
     935        4326 :           if (AntiDepReg == 0) continue;
     936             :         }
     937             : 
     938             :         assert(AntiDepReg != 0);
     939             :         if (AntiDepReg == 0) continue;
     940             : 
     941             :         // Determine AntiDepReg's register group.
     942        4026 :         const unsigned GroupIndex = State->GetGroup(AntiDepReg);
     943        4026 :         if (GroupIndex == 0) {
     944             :           DEBUG(dbgs() << " (zero group)\n");
     945        1745 :           continue;
     946             :         }
     947             : 
     948             :         DEBUG(dbgs() << '\n');
     949             : 
     950             :         // Look for a suitable register to use to break the anti-dependence.
     951             :         std::map<unsigned, unsigned> RenameMap;
     952        2281 :         if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
     953             :           DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
     954             :                        << printReg(AntiDepReg, TRI) << ":");
     955             : 
     956             :           // Handle each group register...
     957             :           for (std::map<unsigned, unsigned>::iterator
     958        4165 :                  S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
     959        2169 :             unsigned CurrReg = S->first;
     960        2169 :             unsigned NewReg = S->second;
     961             : 
     962             :             DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
     963             :                          << printReg(NewReg, TRI) << "("
     964             :                          << RegRefs.count(CurrReg) << " refs)");
     965             : 
     966             :             // Update the references to the old register CurrReg to
     967             :             // refer to the new register NewReg.
     968        6593 :             for (const auto &Q : make_range(RegRefs.equal_range(CurrReg))) {
     969        4424 :               Q.second.Operand->setReg(NewReg);
     970             :               // If the SU for the instruction being updated has debug
     971             :               // information related to the anti-dependency register, make
     972             :               // sure to update that as well.
     973        4424 :               const SUnit *SU = MISUnitMap[Q.second.Operand->getParent()];
     974        4424 :               if (!SU) continue;
     975        4424 :               UpdateDbgValues(DbgValues, Q.second.Operand->getParent(),
     976             :                               AntiDepReg, NewReg);
     977             :             }
     978             : 
     979             :             // We just went back in time and modified history; the
     980             :             // liveness information for CurrReg is now inconsistent. Set
     981             :             // the state as if it were dead.
     982        2169 :             State->UnionGroups(NewReg, 0);
     983             :             RegRefs.erase(NewReg);
     984        6507 :             DefIndices[NewReg] = DefIndices[CurrReg];
     985        6507 :             KillIndices[NewReg] = KillIndices[CurrReg];
     986             : 
     987        2169 :             State->UnionGroups(CurrReg, 0);
     988             :             RegRefs.erase(CurrReg);
     989        6507 :             DefIndices[CurrReg] = KillIndices[CurrReg];
     990        4338 :             KillIndices[CurrReg] = ~0u;
     991             :             assert(((KillIndices[CurrReg] == ~0u) !=
     992             :                     (DefIndices[CurrReg] == ~0u)) &&
     993             :                    "Kill and Def maps aren't consistent for AntiDepReg!");
     994             :           }
     995             : 
     996        1996 :           ++Broken;
     997             :           DEBUG(dbgs() << '\n');
     998             :         }
     999             :       }
    1000             :     }
    1001             : 
    1002       60073 :     ScanInstruction(MI, Count);
    1003             :   }
    1004             : 
    1005             :   return Broken;
    1006      291513 : }

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