LCOV - code coverage report
Current view: top level - lib/CodeGen - AllocationOrder.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 9 9 100.0 %
Date: 2017-09-14 15:23:50 Functions: 1 1 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements an allocation order for virtual registers.
      11             : //
      12             : // The preferred allocation order for a virtual register depends on allocation
      13             : // hints and target hooks. The AllocationOrder class encapsulates all of that.
      14             : //
      15             : //===----------------------------------------------------------------------===//
      16             : 
      17             : #include "AllocationOrder.h"
      18             : #include "llvm/CodeGen/MachineFunction.h"
      19             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      20             : #include "llvm/CodeGen/RegisterClassInfo.h"
      21             : #include "llvm/CodeGen/VirtRegMap.h"
      22             : #include "llvm/Support/Debug.h"
      23             : #include "llvm/Support/raw_ostream.h"
      24             : 
      25             : using namespace llvm;
      26             : 
      27             : #define DEBUG_TYPE "regalloc"
      28             : 
      29             : // Compare VirtRegMap::getRegAllocPref().
      30     1437607 : AllocationOrder::AllocationOrder(unsigned VirtReg,
      31             :                                  const VirtRegMap &VRM,
      32             :                                  const RegisterClassInfo &RegClassInfo,
      33     1437607 :                                  const LiveRegMatrix *Matrix)
      34     4312821 :   : Pos(0) {
      35     1437607 :   const MachineFunction &MF = VRM.getMachineFunction();
      36     1437607 :   const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
      37     2875214 :   Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
      38     1437607 :   TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
      39     1437607 :   rewind();
      40             : 
      41             :   DEBUG({
      42             :     if (!Hints.empty()) {
      43             :       dbgs() << "hints:";
      44             :       for (unsigned I = 0, E = Hints.size(); I != E; ++I)
      45             :         dbgs() << ' ' << PrintReg(Hints[I], TRI);
      46             :       dbgs() << '\n';
      47             :     }
      48             :   });
      49             : #ifndef NDEBUG
      50             :   for (unsigned I = 0, E = Hints.size(); I != E; ++I)
      51             :     assert(is_contained(Order, Hints[I]) &&
      52             :            "Target hint is outside allocation order.");
      53             : #endif
      54     1437607 : }

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