LCOV - code coverage report
Current view: top level - lib/CodeGen - AllocationOrder.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 11 11 100.0 %
Date: 2017-09-14 15:23:50 Functions: 1 1 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements an allocation order for virtual registers.
      11             : //
      12             : // The preferred allocation order for a virtual register depends on allocation
      13             : // hints and target hooks. The AllocationOrder class encapsulates all of that.
      14             : //
      15             : //===----------------------------------------------------------------------===//
      16             : 
      17             : #ifndef LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
      18             : #define LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
      19             : 
      20             : #include "llvm/ADT/ArrayRef.h"
      21             : #include "llvm/ADT/STLExtras.h"
      22             : #include "llvm/MC/MCRegisterInfo.h"
      23             : 
      24             : namespace llvm {
      25             : 
      26             : class RegisterClassInfo;
      27             : class VirtRegMap;
      28             : class LiveRegMatrix;
      29             : 
      30     2875214 : class LLVM_LIBRARY_VISIBILITY AllocationOrder {
      31             :   SmallVector<MCPhysReg, 16> Hints;
      32             :   ArrayRef<MCPhysReg> Order;
      33             :   int Pos;
      34             : 
      35             : public:
      36             :   /// Create a new AllocationOrder for VirtReg.
      37             :   /// @param VirtReg      Virtual register to allocate for.
      38             :   /// @param VRM          Virtual register map for function.
      39             :   /// @param RegClassInfo Information about reserved and allocatable registers.
      40             :   AllocationOrder(unsigned VirtReg,
      41             :                   const VirtRegMap &VRM,
      42             :                   const RegisterClassInfo &RegClassInfo,
      43             :                   const LiveRegMatrix *Matrix);
      44             : 
      45             :   /// Get the allocation order without reordered hints.
      46             :   ArrayRef<MCPhysReg> getOrder() const { return Order; }
      47             : 
      48             :   /// Return the next physical register in the allocation order, or 0.
      49             :   /// It is safe to call next() again after it returned 0, it will keep
      50             :   /// returning 0 until rewind() is called.
      51    22675345 :   unsigned next(unsigned Limit = 0) {
      52    22675345 :     if (Pos < 0)
      53     1290862 :       return Hints.end()[Pos++];
      54    22029914 :     if (!Limit)
      55    20299680 :       Limit = Order.size();
      56    22210991 :     while (Pos < int(Limit)) {
      57    43673612 :       unsigned Reg = Order[Pos++];
      58    21836806 :       if (!isHint(Reg))
      59             :         return Reg;
      60             :     }
      61             :     return 0;
      62             :   }
      63             : 
      64             :   /// As next(), but allow duplicates to be returned, and stop before the
      65             :   /// Limit'th register in the RegisterClassInfo allocation order.
      66             :   ///
      67             :   /// This can produce more than Limit registers if there are hints.
      68             :   unsigned nextWithDups(unsigned Limit) {
      69             :     if (Pos < 0)
      70             :       return Hints.end()[Pos++];
      71             :     if (Pos < int(Limit))
      72             :       return Order[Pos++];
      73             :     return 0;
      74             :   }
      75             : 
      76             :   /// Start over from the beginning.
      77     5799502 :   void rewind() { Pos = -int(Hints.size()); }
      78             : 
      79             :   /// Return true if the last register returned from next() was a preferred register.
      80             :   bool isHint() const { return Pos <= 0; }
      81             : 
      82             :   /// Return true if PhysReg is a preferred register.
      83    43950538 :   bool isHint(unsigned PhysReg) const { return is_contained(Hints, PhysReg); }
      84             : };
      85             : 
      86             : } // end namespace llvm
      87             : 
      88             : #endif

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