LCOV - code coverage report
Current view: top level - lib/CodeGen/AsmPrinter - DwarfExpression.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 181 193 93.8 %
Date: 2018-06-17 00:07:59 Functions: 16 17 94.1 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains support for writing dwarf debug info into asm files.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "DwarfExpression.h"
      15             : #include "llvm/ADT/APInt.h"
      16             : #include "llvm/ADT/SmallBitVector.h"
      17             : #include "llvm/BinaryFormat/Dwarf.h"
      18             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      19             : #include "llvm/IR/DebugInfoMetadata.h"
      20             : #include "llvm/Support/ErrorHandling.h"
      21             : #include <algorithm>
      22             : #include <cassert>
      23             : #include <cstdint>
      24             : 
      25             : using namespace llvm;
      26             : 
      27       57130 : void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
      28             :  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
      29             :  assert((LocationKind == Unknown || LocationKind == Register) &&
      30             :         "location description already locked down");
      31       57130 :  LocationKind = Register;
      32       57130 :  if (DwarfReg < 32) {
      33       57103 :    emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
      34             :   } else {
      35          27 :     emitOp(dwarf::DW_OP_regx, Comment);
      36          27 :     emitUnsigned(DwarfReg);
      37             :   }
      38       57130 : }
      39             : 
      40        8072 : void DwarfExpression::addBReg(int DwarfReg, int Offset) {
      41             :   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
      42             :   assert(LocationKind != Register && "location description already locked down");
      43        8072 :   if (DwarfReg < 32) {
      44        8069 :     emitOp(dwarf::DW_OP_breg0 + DwarfReg);
      45             :   } else {
      46           3 :     emitOp(dwarf::DW_OP_bregx);
      47           3 :     emitUnsigned(DwarfReg);
      48             :   }
      49        8072 :   emitSigned(Offset);
      50        8072 : }
      51             : 
      52       68360 : void DwarfExpression::addFBReg(int Offset) {
      53       68360 :   emitOp(dwarf::DW_OP_fbreg);
      54       68360 :   emitSigned(Offset);
      55       68360 : }
      56             : 
      57       57365 : void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
      58       57365 :   if (!SizeInBits)
      59             :     return;
      60             : 
      61             :   const unsigned SizeOfByte = 8;
      62         246 :   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
      63           6 :     emitOp(dwarf::DW_OP_bit_piece);
      64           6 :     emitUnsigned(SizeInBits);
      65           6 :     emitUnsigned(OffsetInBits);
      66             :   } else {
      67         240 :     emitOp(dwarf::DW_OP_piece);
      68         240 :     unsigned ByteSize = SizeInBits / SizeOfByte;
      69         240 :     emitUnsigned(ByteSize);
      70             :   }
      71         246 :   this->OffsetInBits += SizeInBits;
      72             : }
      73             : 
      74           0 : void DwarfExpression::addShr(unsigned ShiftBy) {
      75           0 :   emitOp(dwarf::DW_OP_constu);
      76           0 :   emitUnsigned(ShiftBy);
      77           0 :   emitOp(dwarf::DW_OP_shr);
      78           0 : }
      79             : 
      80           1 : void DwarfExpression::addAnd(unsigned Mask) {
      81           1 :   emitOp(dwarf::DW_OP_constu);
      82           1 :   emitUnsigned(Mask);
      83           1 :   emitOp(dwarf::DW_OP_and);
      84           1 : }
      85             : 
      86      133615 : bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
      87             :                                     unsigned MachineReg, unsigned MaxSize) {
      88      133615 :   if (!TRI.isPhysicalRegister(MachineReg)) {
      89          26 :     if (isFrameRegister(TRI, MachineReg)) {
      90           0 :       DwarfRegs.push_back({-1, 0, nullptr});
      91           0 :       return true;
      92             :     }
      93             :     return false;
      94             :   }
      95             : 
      96      133589 :   int Reg = TRI.getDwarfRegNum(MachineReg, false);
      97             : 
      98             :   // If this is a valid register number, emit it.
      99      133589 :   if (Reg >= 0) {
     100      132788 :     DwarfRegs.push_back({Reg, 0, nullptr});
     101      132788 :     return true;
     102             :   }
     103             : 
     104             :   // Walk up the super-register chain until we find a valid number.
     105             :   // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
     106        1418 :   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
     107        1383 :     Reg = TRI.getDwarfRegNum(*SR, false);
     108        1383 :     if (Reg >= 0) {
     109         766 :       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
     110         766 :       unsigned Size = TRI.getSubRegIdxSize(Idx);
     111         766 :       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
     112         766 :       DwarfRegs.push_back({Reg, 0, "super-register"});
     113             :       // Use a DW_OP_bit_piece to describe the sub-register.
     114             :       setSubRegisterPiece(Size, RegOffset);
     115             :       return true;
     116             :     }
     117             :   }
     118             : 
     119             :   // Otherwise, attempt to find a covering set of sub-register numbers.
     120             :   // For example, Q0 on ARM is a composition of D0+D1.
     121             :   unsigned CurPos = 0;
     122             :   // The size of the register in bits.
     123          35 :   const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
     124             :   unsigned RegSize = TRI.getRegSizeInBits(*RC);
     125             :   // Keep track of the bits in the register we already emitted, so we
     126             :   // can avoid emitting redundant aliasing subregs. Because this is
     127             :   // just doing a greedy scan of all subregisters, it is possible that
     128             :   // this doesn't find a combination of subregisters that fully cover
     129             :   // the register (even though one may exist).
     130          70 :   SmallBitVector Coverage(RegSize, false);
     131          87 :   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
     132          52 :     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
     133          52 :     unsigned Size = TRI.getSubRegIdxSize(Idx);
     134          52 :     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
     135          52 :     Reg = TRI.getDwarfRegNum(*SR, false);
     136          52 :     if (Reg < 0)
     137          24 :       continue;
     138             : 
     139             :     // Intersection between the bits we already emitted and the bits
     140             :     // covered by this subregister.
     141          56 :     SmallBitVector CurSubReg(RegSize, false);
     142          28 :     CurSubReg.set(Offset, Offset + Size);
     143             : 
     144             :     // If this sub-register has a DWARF number and we haven't covered
     145             :     // its range, emit a DWARF piece for it.
     146          28 :     if (CurSubReg.test(Coverage)) {
     147             :       // Emit a piece for any gap in the coverage.
     148          24 :       if (Offset > CurPos)
     149           0 :         DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
     150          48 :       DwarfRegs.push_back(
     151          72 :           {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
     152          24 :       if (Offset >= MaxSize)
     153             :         break;
     154             : 
     155             :       // Mark it as emitted.
     156          24 :       Coverage.set(Offset, Offset + Size);
     157             :       CurPos = Offset + Size;
     158             :     }
     159             :   }
     160             :   // Failed to find any DWARF encoding.
     161          35 :   if (CurPos == 0)
     162             :     return false;
     163             :   // Found a partial or complete DWARF encoding.
     164          12 :   if (CurPos < RegSize)
     165           0 :     DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
     166             :   return true;
     167             : }
     168             : 
     169        6468 : void DwarfExpression::addStackValue() {
     170        6468 :   if (DwarfVersion >= 4)
     171        6444 :     emitOp(dwarf::DW_OP_stack_value);
     172        6468 : }
     173             : 
     174          49 : void DwarfExpression::addSignedConstant(int64_t Value) {
     175             :   assert(LocationKind == Implicit || LocationKind == Unknown);
     176          49 :   LocationKind = Implicit;
     177          49 :   emitOp(dwarf::DW_OP_consts);
     178          49 :   emitSigned(Value);
     179          49 : }
     180             : 
     181         441 : void DwarfExpression::addUnsignedConstant(uint64_t Value) {
     182             :   assert(LocationKind == Implicit || LocationKind == Unknown);
     183         441 :   LocationKind = Implicit;
     184         441 :   emitOp(dwarf::DW_OP_constu);
     185         441 :   emitUnsigned(Value);
     186         441 : }
     187             : 
     188          12 : void DwarfExpression::addUnsignedConstant(const APInt &Value) {
     189             :   assert(LocationKind == Implicit || LocationKind == Unknown);
     190          12 :   LocationKind = Implicit;
     191             : 
     192          12 :   unsigned Size = Value.getBitWidth();
     193             :   const uint64_t *Data = Value.getRawData();
     194             : 
     195             :   // Chop it up into 64-bit pieces, because that's the maximum that
     196             :   // addUnsignedConstant takes.
     197             :   unsigned Offset = 0;
     198          24 :   while (Offset < Size) {
     199          15 :     addUnsignedConstant(*Data++);
     200          15 :     if (Offset == 0 && Size <= 64)
     201             :       break;
     202           6 :     addStackValue();
     203          12 :     addOpPiece(std::min(Size - Offset, 64u), Offset);
     204           6 :     Offset += 64;
     205             :   }
     206          12 : }
     207             : 
     208      133615 : bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
     209             :                                               DIExpressionCursor &ExprCursor,
     210             :                                               unsigned MachineReg,
     211             :                                               unsigned FragmentOffsetInBits) {
     212             :   auto Fragment = ExprCursor.getFragmentInfo();
     213      133615 :   if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
     214          49 :     LocationKind = Unknown;
     215          49 :     return false;
     216             :   }
     217             : 
     218             :   bool HasComplexExpression = false;
     219             :   auto Op = ExprCursor.peek();
     220      209669 :   if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
     221             :     HasComplexExpression = true;
     222             : 
     223             :   // If the register can only be described by a complex expression (i.e.,
     224             :   // multiple subregisters) it doesn't safely compose with another complex
     225             :   // expression. For example, it is not possible to apply a DW_OP_deref
     226             :   // operation to multiple DW_OP_pieces.
     227       75998 :   if (HasComplexExpression && DwarfRegs.size() > 1) {
     228             :     DwarfRegs.clear();
     229           4 :     LocationKind = Unknown;
     230           4 :     return false;
     231             :   }
     232             : 
     233             :   // Handle simple register locations.
     234      196458 :   if (LocationKind != Memory && !HasComplexExpression) {
     235      171382 :     for (auto &Reg : DwarfRegs) {
     236       57130 :       if (Reg.DwarfRegNo >= 0)
     237       57130 :         addReg(Reg.DwarfRegNo, Reg.Comment);
     238       57130 :       addOpPiece(Reg.Size);
     239             :     }
     240             :     DwarfRegs.clear();
     241       57122 :     return true;
     242             :   }
     243             : 
     244             :   // Don't emit locations that cannot be expressed without DW_OP_stack_value.
     245       76440 :   if (DwarfVersion < 4)
     246         153 :     if (std::any_of(ExprCursor.begin(), ExprCursor.end(),
     247             :                     [](DIExpression::ExprOperand Op) -> bool {
     248             :                       return Op.getOp() == dwarf::DW_OP_stack_value;
     249             :                     })) {
     250             :       DwarfRegs.clear();
     251           8 :       LocationKind = Unknown;
     252           8 :       return false;
     253             :     }
     254             : 
     255             :   assert(DwarfRegs.size() == 1);
     256       76432 :   auto Reg = DwarfRegs[0];
     257       76432 :   bool FBReg = isFrameRegister(TRI, MachineReg);
     258             :   int SignedOffset = 0;
     259             :   assert(Reg.Size == 0 && "subregister has same size as superregister");
     260             : 
     261             :   // Pattern-match combinations for which more efficient representations exist.
     262             :   // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
     263      152420 :   if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
     264       74025 :     SignedOffset = Op->getArg(0);
     265             :     ExprCursor.take();
     266             :   }
     267             : 
     268             :   // [Reg, DW_OP_constu, Offset, DW_OP_plus]  --> [DW_OP_breg, Offset]
     269             :   // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
     270             :   // If Reg is a subregister we need to mask it out before subtracting.
     271      152420 :   if (Op && Op->getOp() == dwarf::DW_OP_constu) {
     272         225 :     auto N = ExprCursor.peekNext();
     273         450 :     if (N && (N->getOp() == dwarf::DW_OP_plus ||
     274         408 :              (N->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) {
     275         183 :       int Offset = Op->getArg(0);
     276         183 :       SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? -Offset : Offset;
     277             :       ExprCursor.consume(2);
     278             :     }
     279             :   }
     280             : 
     281       76432 :   if (FBReg)
     282       68360 :     addFBReg(SignedOffset);
     283             :   else
     284        8072 :     addBReg(Reg.DwarfRegNo, SignedOffset);
     285             :   DwarfRegs.clear();
     286       76432 :   return true;
     287             : }
     288             : 
     289             : /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
     290         503 : static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
     291         504 :   while (ExprCursor) {
     292             :     auto Op = ExprCursor.take();
     293         486 :     switch (Op->getOp()) {
     294             :     case dwarf::DW_OP_deref:
     295             :     case dwarf::DW_OP_LLVM_fragment:
     296             :       break;
     297         485 :     default:
     298             :       return false;
     299             :     }
     300             :   }
     301             :   return true;
     302             : }
     303             : 
     304      137183 : void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
     305             :                                     unsigned FragmentOffsetInBits) {
     306             :   // If we need to mask out a subregister, do it now, unless the next
     307             :   // operation would emit an OpPiece anyway.
     308             :   auto N = ExprCursor.peek();
     309      137216 :   if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
     310           1 :     maskSubRegister();
     311             : 
     312      147594 :   while (ExprCursor) {
     313             :     auto Op = ExprCursor.take();
     314       10611 :     switch (Op->getOp()) {
     315             :     case dwarf::DW_OP_LLVM_fragment: {
     316         200 :       unsigned SizeInBits = Op->getArg(1);
     317         200 :       unsigned FragmentOffset = Op->getArg(0);
     318             :       // The fragment offset must have already been adjusted by emitting an
     319             :       // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
     320             :       // location.
     321             :       assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
     322             : 
     323             :       // If addMachineReg already emitted DW_OP_piece operations to represent
     324             :       // a super-register by splicing together sub-registers, subtract the size
     325             :       // of the pieces that was already emitted.
     326         200 :       SizeInBits -= OffsetInBits - FragmentOffset;
     327             : 
     328             :       // If addMachineReg requested a DW_OP_bit_piece to stencil out a
     329             :       // sub-register that is smaller than the current fragment's size, use it.
     330         200 :       if (SubRegisterSizeInBits)
     331          64 :         SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
     332             : 
     333             :       // Emit a DW_OP_stack_value for implicit location descriptions.
     334         200 :       if (LocationKind == Implicit)
     335          73 :         addStackValue();
     336             : 
     337             :       // Emit the DW_OP_piece.
     338         200 :       addOpPiece(SizeInBits, SubRegisterOffsetInBits);
     339             :       setSubRegisterPiece(0, 0);
     340             :       // Reset the location description kind.
     341         200 :       LocationKind = Unknown;
     342             :       return;
     343             :     }
     344        3557 :     case dwarf::DW_OP_plus_uconst:
     345             :       assert(LocationKind != Register);
     346        3557 :       emitOp(dwarf::DW_OP_plus_uconst);
     347        7114 :       emitUnsigned(Op->getArg(0));
     348        3557 :       break;
     349          59 :     case dwarf::DW_OP_plus:
     350             :     case dwarf::DW_OP_minus:
     351             :     case dwarf::DW_OP_mul:
     352             :     case dwarf::DW_OP_div:
     353             :     case dwarf::DW_OP_mod:
     354             :     case dwarf::DW_OP_or:
     355             :     case dwarf::DW_OP_and:
     356             :     case dwarf::DW_OP_xor:
     357             :     case dwarf::DW_OP_shl:
     358             :     case dwarf::DW_OP_shr:
     359             :     case dwarf::DW_OP_shra:
     360          59 :       emitOp(Op->getOp());
     361          59 :       break;
     362         725 :     case dwarf::DW_OP_deref:
     363             :       assert(LocationKind != Register);
     364         725 :       if (LocationKind != Memory && ::isMemoryLocation(ExprCursor))
     365             :         // Turning this into a memory location description makes the deref
     366             :         // implicit.
     367          18 :         LocationKind = Memory;
     368             :       else
     369         707 :         emitOp(dwarf::DW_OP_deref);
     370             :       break;
     371          76 :     case dwarf::DW_OP_constu:
     372             :       assert(LocationKind != Register);
     373          76 :       emitOp(dwarf::DW_OP_constu);
     374         152 :       emitUnsigned(Op->getArg(0));
     375          76 :       break;
     376        5974 :     case dwarf::DW_OP_stack_value:
     377        5974 :       LocationKind = Implicit;
     378        5974 :       break;
     379          10 :     case dwarf::DW_OP_swap:
     380             :       assert(LocationKind != Register);
     381          10 :       emitOp(dwarf::DW_OP_swap);
     382          10 :       break;
     383          10 :     case dwarf::DW_OP_xderef:
     384             :       assert(LocationKind != Register);
     385          10 :       emitOp(dwarf::DW_OP_xderef);
     386          10 :       break;
     387           0 :     default:
     388           0 :       llvm_unreachable("unhandled opcode found in expression");
     389             :     }
     390             :   }
     391             : 
     392      136983 :   if (LocationKind == Implicit)
     393             :     // Turn this into an implicit location description.
     394        6389 :     addStackValue();
     395             : }
     396             : 
     397             : /// add masking operations to stencil out a subregister.
     398           1 : void DwarfExpression::maskSubRegister() {
     399             :   assert(SubRegisterSizeInBits && "no subregister was registered");
     400           1 :   if (SubRegisterOffsetInBits > 0)
     401           0 :     addShr(SubRegisterOffsetInBits);
     402           1 :   uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
     403           1 :   addAnd(Mask);
     404           1 : }
     405             : 
     406      137120 : void DwarfExpression::finalize() {
     407             :   assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
     408             :   // Emit any outstanding DW_OP_piece operations to mask out subregisters.
     409      137120 :   if (SubRegisterSizeInBits == 0)
     410             :     return;
     411             :   // Don't emit a DW_OP_piece for a subregister at offset 0.
     412         734 :   if (SubRegisterOffsetInBits == 0)
     413             :     return;
     414           1 :   addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
     415             : }
     416             : 
     417       98095 : void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
     418      196190 :   if (!Expr || !Expr->isFragment())
     419             :     return;
     420             : 
     421         206 :   uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
     422             :   assert(FragmentOffset >= OffsetInBits &&
     423             :          "overlapping or duplicate fragments");
     424         206 :   if (FragmentOffset > OffsetInBits)
     425          28 :     addOpPiece(FragmentOffset - OffsetInBits);
     426         206 :   OffsetInBits = FragmentOffset;
     427             : }

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