LCOV - code coverage report
Current view: top level - lib/CodeGen/AsmPrinter - DwarfExpression.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 202 211 95.7 %
Date: 2017-09-14 15:23:50 Functions: 16 17 94.1 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains support for writing dwarf debug info into asm files.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "DwarfExpression.h"
      15             : #include "llvm/ADT/APInt.h"
      16             : #include "llvm/ADT/SmallBitVector.h"
      17             : #include "llvm/BinaryFormat/Dwarf.h"
      18             : #include "llvm/IR/DebugInfoMetadata.h"
      19             : #include "llvm/Support/ErrorHandling.h"
      20             : #include "llvm/Target/TargetRegisterInfo.h"
      21             : #include <algorithm>
      22             : #include <cassert>
      23             : #include <cstdint>
      24             : 
      25             : using namespace llvm;
      26             : 
      27       11776 : void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
      28             :  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
      29             :  assert((LocationKind == Unknown || LocationKind == Register) &&
      30             :         "location description already locked down");
      31       11776 :  LocationKind = Register;
      32       11776 :  if (DwarfReg < 32) {
      33       11750 :    emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
      34             :   } else {
      35          26 :     emitOp(dwarf::DW_OP_regx, Comment);
      36          26 :     emitUnsigned(DwarfReg);
      37             :   }
      38       11776 : }
      39             : 
      40        1764 : void DwarfExpression::addBReg(int DwarfReg, int Offset) {
      41             :   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
      42             :   assert(LocationKind != Register && "location description already locked down");
      43        1764 :   if (DwarfReg < 32) {
      44        1761 :     emitOp(dwarf::DW_OP_breg0 + DwarfReg);
      45             :   } else {
      46           3 :     emitOp(dwarf::DW_OP_bregx);
      47           3 :     emitUnsigned(DwarfReg);
      48             :   }
      49        1764 :   emitSigned(Offset);
      50        1764 : }
      51             : 
      52         432 : void DwarfExpression::addFBReg(int Offset) {
      53         432 :   emitOp(dwarf::DW_OP_fbreg);
      54         432 :   emitSigned(Offset);
      55         432 : }
      56             : 
      57       11929 : void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
      58       11929 :   if (!SizeInBits)
      59             :     return;
      60             : 
      61         164 :   const unsigned SizeOfByte = 8;
      62         164 :   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
      63           5 :     emitOp(dwarf::DW_OP_bit_piece);
      64           5 :     emitUnsigned(SizeInBits);
      65           5 :     emitUnsigned(OffsetInBits);
      66             :   } else {
      67         159 :     emitOp(dwarf::DW_OP_piece);
      68         159 :     unsigned ByteSize = SizeInBits / SizeOfByte;
      69         159 :     emitUnsigned(ByteSize);
      70             :   }
      71         164 :   this->OffsetInBits += SizeInBits;
      72             : }
      73             : 
      74           0 : void DwarfExpression::addShr(unsigned ShiftBy) {
      75           0 :   emitOp(dwarf::DW_OP_constu);
      76           0 :   emitUnsigned(ShiftBy);
      77           0 :   emitOp(dwarf::DW_OP_shr);
      78           0 : }
      79             : 
      80           1 : void DwarfExpression::addAnd(unsigned Mask) {
      81           1 :   emitOp(dwarf::DW_OP_constu);
      82           1 :   emitUnsigned(Mask);
      83           1 :   emitOp(dwarf::DW_OP_and);
      84           1 : }
      85             : 
      86       14007 : bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
      87             :                                     unsigned MachineReg, unsigned MaxSize) {
      88       14007 :   if (!TRI.isPhysicalRegister(MachineReg)) {
      89          53 :     if (isFrameRegister(TRI, MachineReg)) {
      90          22 :       DwarfRegs.push_back({-1, 0, nullptr});
      91          22 :       return true;
      92             :     }
      93             :     return false;
      94             :   }
      95             : 
      96       13954 :   int Reg = TRI.getDwarfRegNum(MachineReg, false);
      97             : 
      98             :   // If this is a valid register number, emit it.
      99       13954 :   if (Reg >= 0) {
     100       13250 :     DwarfRegs.push_back({Reg, 0, nullptr});
     101       13250 :     return true;
     102             :   }
     103             : 
     104             :   // Walk up the super-register chain until we find a valid number.
     105             :   // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
     106        2098 :   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
     107        2764 :     Reg = TRI.getDwarfRegNum(*SR, false);
     108        1382 :     if (Reg >= 0) {
     109         692 :       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
     110         692 :       unsigned Size = TRI.getSubRegIdxSize(Idx);
     111         692 :       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
     112         692 :       DwarfRegs.push_back({Reg, 0, "super-register"});
     113             :       // Use a DW_OP_bit_piece to describe the sub-register.
     114        1384 :       setSubRegisterPiece(Size, RegOffset);
     115             :       return true;
     116             :     }
     117             :   }
     118             : 
     119             :   // Otherwise, attempt to find a covering set of sub-register numbers.
     120             :   // For example, Q0 on ARM is a composition of D0+D1.
     121          12 :   unsigned CurPos = 0;
     122             :   // The size of the register in bits.
     123          12 :   const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
     124          24 :   unsigned RegSize = TRI.getRegSizeInBits(*RC);
     125             :   // Keep track of the bits in the register we already emitted, so we
     126             :   // can avoid emitting redundant aliasing subregs.
     127          24 :   SmallBitVector Coverage(RegSize, false);
     128          76 :   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
     129         104 :     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
     130          52 :     unsigned Size = TRI.getSubRegIdxSize(Idx);
     131          52 :     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
     132          52 :     Reg = TRI.getDwarfRegNum(*SR, false);
     133             : 
     134             :     // Intersection between the bits we already emitted and the bits
     135             :     // covered by this subregister.
     136         104 :     SmallBitVector CurSubReg(RegSize, false);
     137          52 :     CurSubReg.set(Offset, Offset + Size);
     138             : 
     139             :     // If this sub-register has a DWARF number and we haven't covered
     140             :     // its range, emit a DWARF piece for it.
     141          52 :     if (Reg >= 0 && CurSubReg.test(Coverage)) {
     142             :       // Emit a piece for any gap in the coverage.
     143          24 :       if (Offset > CurPos)
     144           0 :         DwarfRegs.push_back({-1, Offset - CurPos, nullptr});
     145          48 :       DwarfRegs.push_back(
     146          72 :           {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
     147          24 :       if (Offset >= MaxSize)
     148             :         break;
     149             : 
     150             :       // Mark it as emitted.
     151          24 :       Coverage.set(Offset, Offset + Size);
     152          24 :       CurPos = Offset + Size;
     153             :     }
     154             :   }
     155             : 
     156          12 :   return CurPos;
     157             : }
     158             : 
     159        1096 : void DwarfExpression::addStackValue() {
     160        1096 :   if (DwarfVersion >= 4)
     161        1072 :     emitOp(dwarf::DW_OP_stack_value);
     162        1096 : }
     163             : 
     164          39 : void DwarfExpression::addSignedConstant(int64_t Value) {
     165             :   assert(LocationKind == Implicit || LocationKind == Unknown);
     166          39 :   LocationKind = Implicit;
     167          39 :   emitOp(dwarf::DW_OP_consts);
     168          39 :   emitSigned(Value);
     169          39 : }
     170             : 
     171         403 : void DwarfExpression::addUnsignedConstant(uint64_t Value) {
     172             :   assert(LocationKind == Implicit || LocationKind == Unknown);
     173         403 :   LocationKind = Implicit;
     174         403 :   emitOp(dwarf::DW_OP_constu);
     175         403 :   emitUnsigned(Value);
     176         403 : }
     177             : 
     178          10 : void DwarfExpression::addUnsignedConstant(const APInt &Value) {
     179             :   assert(LocationKind == Implicit || LocationKind == Unknown);
     180          10 :   LocationKind = Implicit;
     181             : 
     182          10 :   unsigned Size = Value.getBitWidth();
     183             :   const uint64_t *Data = Value.getRawData();
     184             : 
     185             :   // Chop it up into 64-bit pieces, because that's the maximum that
     186             :   // addUnsignedConstant takes.
     187             :   unsigned Offset = 0;
     188          22 :   while (Offset < Size) {
     189          13 :     addUnsignedConstant(*Data++);
     190          13 :     if (Offset == 0 && Size <= 64)
     191             :       break;
     192           6 :     addStackValue();
     193          12 :     addOpPiece(std::min(Size - Offset, 64u), Offset);
     194           6 :     Offset += 64;
     195             :   }
     196          10 : }
     197             : 
     198       14007 : bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
     199             :                                               DIExpressionCursor &ExprCursor,
     200             :                                               unsigned MachineReg,
     201             :                                               unsigned FragmentOffsetInBits) {
     202       28014 :   auto Fragment = ExprCursor.getFragmentInfo();
     203       14094 :   if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
     204          31 :     LocationKind = Unknown;
     205          31 :     return false;
     206             :   }
     207             : 
     208       13976 :   bool HasComplexExpression = false;
     209       13976 :   auto Op = ExprCursor.peek();
     210       18110 :   if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
     211        1999 :     HasComplexExpression = true;
     212             : 
     213             :   // If the register can only be described by a complex expression (i.e.,
     214             :   // multiple subregisters) it doesn't safely compose with another complex
     215             :   // expression. For example, it is not possible to apply a DW_OP_deref
     216             :   // operation to multiple DW_OP_pieces.
     217        3998 :   if (HasComplexExpression && DwarfRegs.size() > 1) {
     218           8 :     DwarfRegs.clear();
     219           4 :     LocationKind = Unknown;
     220           4 :     return false;
     221             :   }
     222             : 
     223             :   // Handle simple register locations.
     224       26354 :   if (LocationKind != Memory && !HasComplexExpression) {
     225       47080 :     for (auto &Reg : DwarfRegs) {
     226       11776 :       if (Reg.DwarfRegNo >= 0)
     227       11776 :         addReg(Reg.DwarfRegNo, Reg.Comment);
     228       11776 :       addOpPiece(Reg.Size);
     229             :     }
     230       23536 :     DwarfRegs.clear();
     231       11768 :     return true;
     232             :   }
     233             : 
     234             :   // Don't emit locations that cannot be expressed without DW_OP_stack_value.
     235        2204 :   if (DwarfVersion < 4)
     236         258 :     if (std::any_of(ExprCursor.begin(), ExprCursor.end(),
     237             :                     [](DIExpression::ExprOperand Op) -> bool {
     238         202 :                       return Op.getOp() == dwarf::DW_OP_stack_value;
     239             :                     })) {
     240          16 :       DwarfRegs.clear();
     241           8 :       LocationKind = Unknown;
     242           8 :       return false;
     243             :     }
     244             : 
     245             :   assert(DwarfRegs.size() == 1);
     246        4392 :   auto Reg = DwarfRegs[0];
     247        2196 :   bool FBReg = isFrameRegister(TRI, MachineReg);
     248        2196 :   int SignedOffset = 0;
     249             :   assert(Reg.Size == 0 && "subregister has same size as superregister");
     250             : 
     251             :   // Pattern-match combinations for which more efficient representations exist.
     252             :   // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
     253        6170 :   if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
     254        3086 :     SignedOffset = Op->getArg(0);
     255        3086 :     ExprCursor.take();
     256             :   }
     257             : 
     258             :   // [Reg, DW_OP_constu, Offset, DW_OP_plus]  --> [DW_OP_breg, Offset]
     259             :   // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
     260             :   // If Reg is a subregister we need to mask it out before subtracting.
     261        6170 :   if (Op && Op->getOp() == dwarf::DW_OP_constu) {
     262          44 :     auto N = ExprCursor.peekNext();
     263          87 :     if (N && (N->getOp() == dwarf::DW_OP_plus ||
     264          61 :              (N->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) {
     265          36 :       int Offset = Op->getArg(0);
     266          18 :       SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? -Offset : Offset;
     267             :       ExprCursor.consume(2);
     268             :     }
     269             :   }
     270             : 
     271        2196 :   if (FBReg)
     272         432 :     addFBReg(SignedOffset);
     273             :   else
     274        1764 :     addBReg(Reg.DwarfRegNo, SignedOffset);
     275        4392 :   DwarfRegs.clear();
     276        2196 :   return true;
     277             : }
     278             : 
     279             : /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
     280          53 : static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
     281          54 :   while (ExprCursor) {
     282          21 :     auto Op = ExprCursor.take();
     283          40 :     switch (Op->getOp()) {
     284             :     case dwarf::DW_OP_deref:
     285             :     case dwarf::DW_OP_LLVM_fragment:
     286             :       break;
     287          19 :     default:
     288          38 :       return false;
     289             :     }
     290             :   }
     291             :   return true;
     292             : }
     293             : 
     294       14701 : void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
     295             :                                     unsigned FragmentOffsetInBits) {
     296             :   // If we need to mask out a subregister, do it now, unless the next
     297             :   // operation would emit an OpPiece anyway.
     298       29289 :   auto N = ExprCursor.peek();
     299       14739 :   if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
     300           1 :     maskSubRegister();
     301             : 
     302       15626 :   while (ExprCursor) {
     303        1963 :     auto Op = ExprCursor.take();
     304        2076 :     switch (Op->getOp()) {
     305         113 :     case dwarf::DW_OP_LLVM_fragment: {
     306         226 :       unsigned SizeInBits = Op->getArg(1);
     307         226 :       unsigned FragmentOffset = Op->getArg(0);
     308             :       // The fragment offset must have already been adjusted by emitting an
     309             :       // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
     310             :       // location.
     311             :       assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
     312             : 
     313             :       // If addMachineReg already emitted DW_OP_piece operations to represent
     314             :       // a super-register by splicing together sub-registers, subtract the size
     315             :       // of the pieces that was already emitted.
     316         113 :       SizeInBits -= OffsetInBits - FragmentOffset;
     317             : 
     318             :       // If addMachineReg requested a DW_OP_bit_piece to stencil out a
     319             :       // sub-register that is smaller than the current fragment's size, use it.
     320         113 :       if (SubRegisterSizeInBits)
     321          36 :         SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
     322             : 
     323             :       // Emit a DW_OP_stack_value for implicit location descriptions.
     324         113 :       if (LocationKind == Implicit)
     325          29 :         addStackValue();
     326             : 
     327             :       // Emit the DW_OP_piece.
     328         113 :       addOpPiece(SizeInBits, SubRegisterOffsetInBits);
     329         226 :       setSubRegisterPiece(0, 0);
     330             :       // Reset the location description kind.
     331         113 :       LocationKind = Unknown;
     332             :       return;
     333             :     }
     334          56 :     case dwarf::DW_OP_plus_uconst:
     335             :       assert(LocationKind != Register);
     336          56 :       emitOp(dwarf::DW_OP_plus_uconst);
     337         168 :       emitUnsigned(Op->getArg(0));
     338          56 :       break;
     339           2 :     case dwarf::DW_OP_plus:
     340             :     case dwarf::DW_OP_minus:
     341           4 :       emitOp(Op->getOp());
     342           2 :       break;
     343         177 :     case dwarf::DW_OP_deref:
     344             :       assert(LocationKind != Register);
     345         177 :       if (LocationKind != Memory && isMemoryLocation(ExprCursor))
     346             :         // Turning this into a memory location description makes the deref
     347             :         // implicit.
     348          34 :         LocationKind = Memory;
     349             :       else
     350         143 :         emitOp(dwarf::DW_OP_deref);
     351             :       break;
     352          19 :     case dwarf::DW_OP_constu:
     353             :       assert(LocationKind != Register);
     354          19 :       emitOp(dwarf::DW_OP_constu);
     355          57 :       emitUnsigned(Op->getArg(0));
     356          19 :       break;
     357         651 :     case dwarf::DW_OP_stack_value:
     358         651 :       LocationKind = Implicit;
     359         651 :       break;
     360          10 :     case dwarf::DW_OP_swap:
     361             :       assert(LocationKind != Register);
     362          10 :       emitOp(dwarf::DW_OP_swap);
     363          10 :       break;
     364          10 :     case dwarf::DW_OP_xderef:
     365             :       assert(LocationKind != Register);
     366          10 :       emitOp(dwarf::DW_OP_xderef);
     367          10 :       break;
     368           0 :     default:
     369           0 :       llvm_unreachable("unhandled opcode found in expression");
     370             :     }
     371             :   }
     372             : 
     373       14588 :   if (LocationKind == Implicit)
     374             :     // Turn this into an implicit location description.
     375        1061 :     addStackValue();
     376             : }
     377             : 
     378             : /// add masking operations to stencil out a subregister.
     379           1 : void DwarfExpression::maskSubRegister() {
     380             :   assert(SubRegisterSizeInBits && "no subregister was registered");
     381           1 :   if (SubRegisterOffsetInBits > 0)
     382           0 :     addShr(SubRegisterOffsetInBits);
     383           1 :   uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
     384           1 :   addAnd(Mask);
     385           1 : }
     386             : 
     387       14670 : void DwarfExpression::finalize() {
     388             :   assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
     389             :   // Emit any outstanding DW_OP_piece operations to mask out subregisters.
     390       14670 :   if (SubRegisterSizeInBits == 0)
     391             :     return;
     392             :   // Don't emit a DW_OP_piece for a subregister at offset 0.
     393         674 :   if (SubRegisterOffsetInBits == 0)
     394             :     return;
     395           1 :   addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
     396             : }
     397             : 
     398       13535 : void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
     399       27070 :   if (!Expr || !Expr->isFragment())
     400             :     return;
     401             : 
     402         357 :   uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
     403             :   assert(FragmentOffset >= OffsetInBits &&
     404             :          "overlapping or duplicate fragments");
     405         119 :   if (FragmentOffset > OffsetInBits)
     406          33 :     addOpPiece(FragmentOffset - OffsetInBits);
     407         119 :   OffsetInBits = FragmentOffset;
     408             : }

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