LCOV - code coverage report
Current view: top level - lib/CodeGen - CriticalAntiDepBreaker.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 249 252 98.8 %
Date: 2017-09-14 15:23:50 Functions: 12 12 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the CriticalAntiDepBreaker class, which
      11             : // implements register anti-dependence breaking along a blocks
      12             : // critical path during post-RA scheduler.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #include "CriticalAntiDepBreaker.h"
      17             : #include "llvm/CodeGen/MachineBasicBlock.h"
      18             : #include "llvm/CodeGen/MachineFrameInfo.h"
      19             : #include "llvm/Support/Debug.h"
      20             : #include "llvm/Support/ErrorHandling.h"
      21             : #include "llvm/Support/raw_ostream.h"
      22             : #include "llvm/Target/TargetInstrInfo.h"
      23             : #include "llvm/Target/TargetRegisterInfo.h"
      24             : #include "llvm/Target/TargetSubtargetInfo.h"
      25             : 
      26             : using namespace llvm;
      27             : 
      28             : #define DEBUG_TYPE "post-RA-sched"
      29             : 
      30        4584 : CriticalAntiDepBreaker::CriticalAntiDepBreaker(MachineFunction &MFi,
      31        4584 :                                                const RegisterClassInfo &RCI)
      32        4584 :     : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
      33        4584 :       TII(MF.getSubtarget().getInstrInfo()),
      34        4584 :       TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
      35        9168 :       Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0),
      36       64176 :       DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {}
      37             : 
      38       36672 : CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
      39        9168 : }
      40             : 
      41       61106 : void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
      42       61106 :   const unsigned BBSize = BB->size();
      43    15093182 :   for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
      44             :     // Clear out the register class data.
      45    30064152 :     Classes[i] = nullptr;
      46             : 
      47             :     // Initialize the indices to indicate that no registers are live.
      48    30064152 :     KillIndices[i] = ~0u;
      49    30064152 :     DefIndices[i] = BBSize;
      50             :   }
      51             : 
      52             :   // Clear "do not change" set.
      53      122212 :   KeepRegs.reset();
      54             : 
      55       61106 :   bool IsReturnBlock = BB->isReturnBlock();
      56             : 
      57             :   // Examine the live-in regs of all successors.
      58       61106 :   for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
      59      203415 :          SE = BB->succ_end(); SI != SE; ++SI)
      60      465049 :     for (const auto &LI : (*SI)->liveins()) {
      61     3129890 :       for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
      62     1343505 :         unsigned Reg = *AI;
      63     2687010 :         Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
      64     2687010 :         KillIndices[Reg] = BBSize;
      65     2687010 :         DefIndices[Reg] = ~0u;
      66             :       }
      67             :     }
      68             : 
      69             :   // Mark live-out callee-saved registers. In a return block this is
      70             :   // all callee-saved registers. In non-return this is any
      71             :   // callee-saved register that is not saved in the prolog.
      72       61106 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
      73      122212 :   BitVector Pristine = MFI.getPristineRegs(MF);
      74      309808 :   for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;
      75             :        ++I) {
      76      248702 :     unsigned Reg = *I;
      77      475112 :     if (!IsReturnBlock && !Pristine.test(Reg))
      78      217470 :       continue;
      79      350836 :     for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
      80      144186 :       unsigned Reg = *AI;
      81      288372 :       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
      82      288372 :       KillIndices[Reg] = BBSize;
      83      288372 :       DefIndices[Reg] = ~0u;
      84             :     }
      85             :   }
      86       61106 : }
      87             : 
      88       61106 : void CriticalAntiDepBreaker::FinishBlock() {
      89      122212 :   RegRefs.clear();
      90      122212 :   KeepRegs.reset();
      91       61106 : }
      92             : 
      93      449124 : void CriticalAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
      94             :                                      unsigned InsertPosIndex) {
      95             :   // Kill instructions can define registers but are really nops, and there might
      96             :   // be a real definition earlier that needs to be paired with uses dominated by
      97             :   // this kill.
      98             : 
      99             :   // FIXME: It may be possible to remove the isKill() restriction once PR18663
     100             :   // has been properly fixed. There can be value in processing kills as seen in
     101             :   // the AggressiveAntiDepBreaker class.
     102      898248 :   if (MI.isDebugValue() || MI.isKill())
     103             :     return;
     104             :   assert(Count < InsertPosIndex && "Instruction index out of expected range!");
     105             : 
     106   221418132 :   for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
     107   220969008 :     if (KillIndices[Reg] != ~0u) {
     108             :       // If Reg is currently live, then mark that it can't be renamed as
     109             :       // we don't know the extent of its live-range anymore (now that it
     110             :       // has been scheduled).
     111    16420962 :       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
     112     8210481 :       KillIndices[Reg] = Count;
     113   204548046 :     } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
     114             :       // Any register which was defined within the previous scheduling region
     115             :       // may have been rescheduled and its lifetime may overlap with registers
     116             :       // in ways not reflected in our current liveness state. For each such
     117             :       // register, adjust the liveness state to be conservatively correct.
     118      673204 :       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
     119             : 
     120             :       // Move the def index to the end of the previous region, to reflect
     121             :       // that the def could theoretically have been scheduled at the end.
     122      336602 :       DefIndices[Reg] = InsertPosIndex;
     123             :     }
     124             :   }
     125             : 
     126      449124 :   PrescanInstruction(MI);
     127      449124 :   ScanInstruction(MI, Count);
     128             : }
     129             : 
     130             : /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
     131             : /// critical path.
     132      325292 : static const SDep *CriticalPathStep(const SUnit *SU) {
     133      325292 :   const SDep *Next = nullptr;
     134      325292 :   unsigned NextDepth = 0;
     135             :   // Find the predecessor edge with the greatest depth.
     136     1621556 :   for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
     137      970972 :        P != PE; ++P) {
     138      645680 :     const SUnit *PredSU = P->getSUnit();
     139      645680 :     unsigned PredLatency = P->getLatency();
     140      645680 :     unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
     141             :     // In the case of a latency tie, prefer an anti-dependency edge over
     142             :     // other types of edges.
     143      645680 :     if (NextDepth < PredTotalLatency ||
     144       78674 :         (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
     145             :       NextDepth = PredTotalLatency;
     146             :       Next = &*P;
     147             :     }
     148             :   }
     149      325292 :   return Next;
     150             : }
     151             : 
     152      997968 : void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) {
     153             :   // It's not safe to change register allocation for source operands of
     154             :   // instructions that have special allocation requirements. Also assume all
     155             :   // registers used in a call must not be changed (ABI).
     156             :   // FIXME: The issue with predicated instruction is more complex. We are being
     157             :   // conservative here because the kill markers cannot be trusted after
     158             :   // if-conversion:
     159             :   // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
     160             :   // ...
     161             :   // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
     162             :   // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
     163             :   // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
     164             :   //
     165             :   // The first R6 kill is not really a kill since it's killed by a predicated
     166             :   // instruction which may not be executed. The second R6 def may or may not
     167             :   // re-define R6 so it's not safe to change it since the last R6 use cannot be
     168             :   // changed.
     169             :   bool Special =
     170     1921017 :       MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI);
     171             : 
     172             :   // Scan the register operands for this instruction and update
     173             :   // Classes and RegRefs.
     174     5211846 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     175     8427756 :     MachineOperand &MO = MI.getOperand(i);
     176     4213878 :     if (!MO.isReg()) continue;
     177     2759104 :     unsigned Reg = MO.getReg();
     178     2759104 :     if (Reg == 0) continue;
     179     1993219 :     const TargetRegisterClass *NewRC = nullptr;
     180             : 
     181     3986438 :     if (i < MI.getDesc().getNumOperands())
     182     1175001 :       NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
     183             : 
     184             :     // For now, only allow the register to be changed if its register
     185             :     // class is consistent across all uses.
     186     3986438 :     if (!Classes[Reg] && NewRC)
     187      197891 :       Classes[Reg] = NewRC;
     188     1795328 :     else if (!NewRC || Classes[Reg] != NewRC)
     189     1553056 :       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
     190             : 
     191             :     // Now check for aliases.
     192    17949322 :     for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
     193             :       // If an alias of the reg is used during the live range, give up.
     194             :       // Note that this allows us to skip checking if AntiDepReg
     195             :       // overlaps with any of the aliases, among other things.
     196     6981442 :       unsigned AliasReg = *AI;
     197    13962884 :       if (Classes[AliasReg]) {
     198     4017093 :         Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
     199     8034186 :         Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
     200             :       }
     201             :     }
     202             : 
     203             :     // If we're still willing to consider this register, note the reference.
     204     3986438 :     if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
     205     1209306 :       RegRefs.insert(std::make_pair(Reg, &MO));
     206             : 
     207             :     // If this reg is tied and live (Classes[Reg] is set to -1), we can't change
     208             :     // it or any of its sub or super regs. We need to use KeepRegs to mark the
     209             :     // reg because not all uses of the same reg within an instruction are
     210             :     // necessarily tagged as tied.
     211             :     // Example: an x86 "xor %eax, %eax" will have one source operand tied to the
     212             :     // def register but not the second (see PR20020 for details).
     213             :     // FIXME: can this check be relaxed to account for undef uses
     214             :     // of a register? In the above 'xor' example, the uses of %eax are undef, so
     215             :     // earlier instructions could still replace %eax even though the 'xor'
     216             :     // itself can't be changed.
     217     2124662 :     if (MI.isRegTiedToUseOperand(i) &&
     218      262886 :         Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) {
     219       82808 :       for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
     220      323471 :            SubRegs.isValid(); ++SubRegs) {
     221      721989 :         KeepRegs.set(*SubRegs);
     222             :       }
     223       82808 :       for (MCSuperRegIterator SuperRegs(Reg, TRI);
     224      180981 :            SuperRegs.isValid(); ++SuperRegs) {
     225      294519 :         KeepRegs.set(*SuperRegs);
     226             :       }
     227             :     }
     228             : 
     229     1993219 :     if (MO.isUse() && Special) {
     230      385270 :       if (!KeepRegs.test(Reg)) {
     231      127042 :         for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
     232      584447 :              SubRegs.isValid(); ++SubRegs)
     233     1372215 :           KeepRegs.set(*SubRegs);
     234             :       }
     235             :     }
     236             :   }
     237      997968 : }
     238             : 
     239      997968 : void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {
     240             :   // Update liveness.
     241             :   // Proceeding upwards, registers that are defed but not used in this
     242             :   // instruction are now dead.
     243             :   assert(!MI.isKill() && "Attempting to scan a kill instruction");
     244             : 
     245      997968 :   if (!TII->isPredicated(MI)) {
     246             :     // Predicated defs are modeled as read + write, i.e. similar to two
     247             :     // address updates.
     248     5211846 :     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     249     8427756 :       MachineOperand &MO = MI.getOperand(i);
     250             : 
     251     4213878 :       if (MO.isRegMask())
     252    18504993 :         for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
     253    36860148 :           if (MO.clobbersPhysReg(i)) {
     254    34910682 :             DefIndices[i] = Count;
     255    34910682 :             KillIndices[i] = ~0u;
     256    34910682 :             KeepRegs.reset(i);
     257    34910682 :             Classes[i] = nullptr;
     258    17455341 :             RegRefs.erase(i);
     259             :           }
     260             : 
     261     4213878 :       if (!MO.isReg()) continue;
     262     2759104 :       unsigned Reg = MO.getReg();
     263     2759104 :       if (Reg == 0) continue;
     264     1993219 :       if (!MO.isDef()) continue;
     265             : 
     266             :       // Ignore two-addr defs.
     267      751624 :       if (MI.isRegTiedToUseOperand(i))
     268      131443 :         continue;
     269             : 
     270             :       // If we've already marked this reg as unchangeable, don't remove
     271             :       // it or any of its subregs from KeepRegs.
     272     1240362 :       bool Keep = KeepRegs.test(Reg);
     273             : 
     274             :       // For the reg itself and all subregs: update the def to current;
     275             :       // reset the kill state, any restrictions, and references.
     276     2668570 :       for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) {
     277     2856416 :         unsigned SubregReg = *SRI;
     278     2856416 :         DefIndices[SubregReg] = Count;
     279     2856416 :         KillIndices[SubregReg] = ~0u;
     280     2856416 :         Classes[SubregReg] = nullptr;
     281     2856416 :         RegRefs.erase(SubregReg);
     282     1428208 :         if (!Keep)
     283     1373860 :           KeepRegs.reset(SubregReg);
     284             :       }
     285             :       // Conservatively mark super-registers as unusable.
     286     1706265 :       for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
     287      931806 :         Classes[*SR] = reinterpret_cast<TargetRegisterClass *>(-1);
     288             :     }
     289             :   }
     290     5211846 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     291     8427756 :     MachineOperand &MO = MI.getOperand(i);
     292     4213878 :     if (!MO.isReg()) continue;
     293     2759104 :     unsigned Reg = MO.getReg();
     294     2759104 :     if (Reg == 0) continue;
     295     1993219 :     if (!MO.isUse()) continue;
     296             : 
     297     1241595 :     const TargetRegisterClass *NewRC = nullptr;
     298     2483190 :     if (i < MI.getDesc().getNumOperands())
     299      845164 :       NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
     300             : 
     301             :     // For now, only allow the register to be changed if its register
     302             :     // class is consistent across all uses.
     303     2483190 :     if (!Classes[Reg] && NewRC)
     304        7443 :       Classes[Reg] = NewRC;
     305     1234152 :     else if (!NewRC || Classes[Reg] != NewRC)
     306      945017 :       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
     307             : 
     308     3724785 :     RegRefs.insert(std::make_pair(Reg, &MO));
     309             : 
     310             :     // It wasn't previously live but now it is, this is a kill.
     311             :     // Repeat for all aliases.
     312    16166058 :     for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
     313     6841434 :       unsigned AliasReg = *AI;
     314    13682868 :       if (KillIndices[AliasReg] == ~0u) {
     315     1838286 :         KillIndices[AliasReg] = Count;
     316     3676572 :         DefIndices[AliasReg] = ~0u;
     317             :       }
     318             :     }
     319             :   }
     320      997968 : }
     321             : 
     322             : // Check all machine operands that reference the antidependent register and must
     323             : // be replaced by NewReg. Return true if any of their parent instructions may
     324             : // clobber the new register.
     325             : //
     326             : // Note: AntiDepReg may be referenced by a two-address instruction such that
     327             : // it's use operand is tied to a def operand. We guard against the case in which
     328             : // the two-address instruction also defines NewReg, as may happen with
     329             : // pre/postincrement loads. In this case, both the use and def operands are in
     330             : // RegRefs because the def is inserted by PrescanInstruction and not erased
     331             : // during ScanInstruction. So checking for an instruction with definitions of
     332             : // both NewReg and AntiDepReg covers it.
     333             : bool
     334       27166 : CriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin,
     335             :                                                 RegRefIter RegRefEnd,
     336             :                                                 unsigned NewReg)
     337             : {
     338      203848 :   for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) {
     339      149516 :     MachineOperand *RefOper = I->second;
     340             : 
     341             :     // Don't allow the instruction defining AntiDepReg to earlyclobber its
     342             :     // operands, in case they may be assigned to NewReg. In this case antidep
     343             :     // breaking must fail, but it's too rare to bother optimizing.
     344      198536 :     if (RefOper->isDef() && RefOper->isEarlyClobber())
     345             :       return true;
     346             : 
     347             :     // Handle cases in which this instruction defines NewReg.
     348      149516 :     MachineInstr *MI = RefOper->getParent();
     349      846742 :     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     350     1394452 :       const MachineOperand &CheckOper = MI->getOperand(i);
     351             : 
     352      697226 :       if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
     353             :         return true;
     354             : 
     355     1926098 :       if (!CheckOper.isReg() || !CheckOper.isDef() ||
     356             :           CheckOper.getReg() != NewReg)
     357      696734 :         continue;
     358             : 
     359             :       // Don't allow the instruction to define NewReg and AntiDepReg.
     360             :       // When AntiDepReg is renamed it will be an illegal op.
     361         492 :       if (RefOper->isDef())
     362             :         return true;
     363             : 
     364             :       // Don't allow an instruction using AntiDepReg to be earlyclobbered by
     365             :       // NewReg.
     366         492 :       if (CheckOper.isEarlyClobber())
     367             :         return true;
     368             : 
     369             :       // Don't allow inline asm to define NewReg at all. Who knows what it's
     370             :       // doing with it.
     371         492 :       if (MI->isInlineAsm())
     372             :         return true;
     373             :     }
     374             :   }
     375             :   return false;
     376             : }
     377             : 
     378       15017 : unsigned CriticalAntiDepBreaker::
     379             : findSuitableFreeRegister(RegRefIter RegRefBegin,
     380             :                          RegRefIter RegRefEnd,
     381             :                          unsigned AntiDepReg,
     382             :                          unsigned LastNewReg,
     383             :                          const TargetRegisterClass *RC,
     384             :                          SmallVectorImpl<unsigned> &Forbid)
     385             : {
     386       15017 :   ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
     387       47440 :   for (unsigned i = 0; i != Order.size(); ++i) {
     388       94506 :     unsigned NewReg = Order[i];
     389             :     // Don't replace a register with itself.
     390       47253 :     if (NewReg == AntiDepReg) continue;
     391             :     // Don't replace a register with one that was recently used to repair
     392             :     // an anti-dependence with this AntiDepReg, because that would
     393             :     // re-introduce that anti-dependence.
     394       32240 :     if (NewReg == LastNewReg) continue;
     395             :     // If any instructions that define AntiDepReg also define the NewReg, it's
     396             :     // not suitable.  For example, Instruction with multiple definitions can
     397             :     // result in this condition.
     398       27166 :     if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
     399             :     // If NewReg is dead and NewReg's most recent def is not before
     400             :     // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
     401             :     assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))
     402             :            && "Kill and Def maps aren't consistent for AntiDepReg!");
     403             :     assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
     404             :            && "Kill and Def maps aren't consistent for NewReg!");
     405       81790 :     if (KillIndices[NewReg] != ~0u ||
     406       57394 :         Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
     407       45318 :         KillIndices[AntiDepReg] > DefIndices[NewReg])
     408       12336 :       continue;
     409             :     // If NewReg overlaps any of the forbidden registers, we can't use it.
     410       14830 :     bool Forbidden = false;
     411       29660 :     for (SmallVectorImpl<unsigned>::iterator it = Forbid.begin(),
     412       29660 :            ite = Forbid.end(); it != ite; ++it)
     413           0 :       if (TRI->regsOverlap(NewReg, *it)) {
     414             :         Forbidden = true;
     415             :         break;
     416             :       }
     417       14830 :     if (Forbidden) continue;
     418             :     return NewReg;
     419             :   }
     420             : 
     421             :   // No registers are free and available!
     422             :   return 0;
     423             : }
     424             : 
     425      510230 : unsigned CriticalAntiDepBreaker::
     426             : BreakAntiDependencies(const std::vector<SUnit>& SUnits,
     427             :                       MachineBasicBlock::iterator Begin,
     428             :                       MachineBasicBlock::iterator End,
     429             :                       unsigned InsertPosIndex,
     430             :                       DbgValueVector &DbgValues) {
     431             :   // The code below assumes that there is at least one instruction,
     432             :   // so just duck out immediately if the block is empty.
     433      510230 :   if (SUnits.empty()) return 0;
     434             : 
     435             :   // Keep a map of the MachineInstr*'s back to the SUnit representing them.
     436             :   // This is used for updating debug information.
     437             :   //
     438             :   // FIXME: Replace this with the existing map in ScheduleDAGInstrs::MISUnitMap
     439      123357 :   DenseMap<MachineInstr*,const SUnit*> MISUnitMap;
     440             : 
     441             :   // Find the node at the bottom of the critical path.
     442      123357 :   const SUnit *Max = nullptr;
     443      796042 :   for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
     444     1098656 :     const SUnit *SU = &SUnits[i];
     445     1098656 :     MISUnitMap[SU->getInstr()] = SU;
     446     1401270 :     if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
     447             :       Max = SU;
     448             :   }
     449             : 
     450             : #ifndef NDEBUG
     451             :   {
     452             :     DEBUG(dbgs() << "Critical path has total latency "
     453             :           << (Max->getDepth() + Max->Latency) << "\n");
     454             :     DEBUG(dbgs() << "Available regs:");
     455             :     for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
     456             :       if (KillIndices[Reg] == ~0u)
     457             :         DEBUG(dbgs() << " " << TRI->getName(Reg));
     458             :     }
     459             :     DEBUG(dbgs() << '\n');
     460             :   }
     461             : #endif
     462             : 
     463             :   // Track progress along the critical path through the SUnit graph as we walk
     464             :   // the instructions.
     465      123357 :   const SUnit *CriticalPathSU = Max;
     466      123357 :   MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
     467             : 
     468             :   // Consider this pattern:
     469             :   //   A = ...
     470             :   //   ... = A
     471             :   //   A = ...
     472             :   //   ... = A
     473             :   //   A = ...
     474             :   //   ... = A
     475             :   //   A = ...
     476             :   //   ... = A
     477             :   // There are three anti-dependencies here, and without special care,
     478             :   // we'd break all of them using the same register:
     479             :   //   A = ...
     480             :   //   ... = A
     481             :   //   B = ...
     482             :   //   ... = B
     483             :   //   B = ...
     484             :   //   ... = B
     485             :   //   B = ...
     486             :   //   ... = B
     487             :   // because at each anti-dependence, B is the first register that
     488             :   // isn't A which is free.  This re-introduces anti-dependencies
     489             :   // at all but one of the original anti-dependencies that we were
     490             :   // trying to break.  To avoid this, keep track of the most recent
     491             :   // register that each register was replaced with, avoid
     492             :   // using it to repair an anti-dependence on the same register.
     493             :   // This lets us produce this:
     494             :   //   A = ...
     495             :   //   ... = A
     496             :   //   B = ...
     497             :   //   ... = B
     498             :   //   C = ...
     499             :   //   ... = C
     500             :   //   B = ...
     501             :   //   ... = B
     502             :   // This still has an anti-dependence on B, but at least it isn't on the
     503             :   // original critical path.
     504             :   //
     505             :   // TODO: If we tracked more than one register here, we could potentially
     506             :   // fix that remaining critical edge too. This is a little more involved,
     507             :   // because unlike the most recent register, less recent registers should
     508             :   // still be considered, though only if no other registers are available.
     509      370071 :   std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
     510             : 
     511             :   // Attempt to break anti-dependence edges on the critical path. Walk the
     512             :   // instructions from the bottom up, tracking information about liveness
     513             :   // as we go to help determine which registers are available.
     514      123357 :   unsigned Broken = 0;
     515      123357 :   unsigned Count = InsertPosIndex - 1;
     516     1345388 :   for (MachineBasicBlock::iterator I = End, E = Begin; I != E; --Count) {
     517     1098674 :     MachineInstr &MI = *--I;
     518             :     // Kill instructions can define registers but are really nops, and there
     519             :     // might be a real definition earlier that needs to be paired with uses
     520             :     // dominated by this kill.
     521             :     
     522             :     // FIXME: It may be possible to remove the isKill() restriction once PR18663
     523             :     // has been properly fixed. There can be value in processing kills as seen
     524             :     // in the AggressiveAntiDepBreaker class.
     525     1099158 :     if (MI.isDebugValue() || MI.isKill())
     526         493 :       continue;
     527             : 
     528             :     // Check if this instruction has a dependence on the critical path that
     529             :     // is an anti-dependence that we may be able to break. If it is, set
     530             :     // AntiDepReg to the non-zero register associated with the anti-dependence.
     531             :     //
     532             :     // We limit our attention to the critical path as a heuristic to avoid
     533             :     // breaking anti-dependence edges that aren't going to significantly
     534             :     // impact the overall schedule. There are a limited number of registers
     535             :     // and we want to save them for the important edges.
     536             :     //
     537             :     // TODO: Instructions with multiple defs could have multiple
     538             :     // anti-dependencies. The current code here only knows how to break one
     539             :     // edge per instruction. Note that we'd have to be able to break all of
     540             :     // the anti-dependencies in an instruction in order to be effective.
     541      548844 :     unsigned AntiDepReg = 0;
     542      548844 :     if (&MI == CriticalPathMI) {
     543      325292 :       if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
     544      202001 :         const SUnit *NextSU = Edge->getSUnit();
     545             : 
     546             :         // Only consider anti-dependence edges.
     547      202001 :         if (Edge->getKind() == SDep::Anti) {
     548       30509 :           AntiDepReg = Edge->getReg();
     549             :           assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
     550       30509 :           if (!MRI.isAllocatable(AntiDepReg))
     551             :             // Don't break anti-dependencies on non-allocatable registers.
     552       12097 :             AntiDepReg = 0;
     553       36824 :           else if (KeepRegs.test(AntiDepReg))
     554             :             // Don't break anti-dependencies if a use down below requires
     555             :             // this exact register.
     556        1668 :             AntiDepReg = 0;
     557             :           else {
     558             :             // If the SUnit has other dependencies on the SUnit that it
     559             :             // anti-depends on, don't bother breaking the anti-dependency
     560             :             // since those edges would prevent such units from being
     561             :             // scheduled past each other regardless.
     562             :             //
     563             :             // Also, if there are dependencies on other SUnits with the
     564             :             // same register as the anti-dependency, don't attempt to
     565             :             // break it.
     566       69972 :             for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(),
     567       33488 :                  PE = CriticalPathSU->Preds.end(); P != PE; ++P)
     568       36747 :               if (P->getSUnit() == NextSU ?
     569       16744 :                     (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
     570       20003 :                     (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
     571         263 :                 AntiDepReg = 0;
     572         263 :                 break;
     573             :               }
     574             :           }
     575             :         }
     576      202001 :         CriticalPathSU = NextSU;
     577      202001 :         CriticalPathMI = CriticalPathSU->getInstr();
     578             :       } else {
     579             :         // We've reached the end of the critical path.
     580             :         CriticalPathSU = nullptr;
     581             :         CriticalPathMI = nullptr;
     582             :       }
     583             :     }
     584             : 
     585      548844 :     PrescanInstruction(MI);
     586             : 
     587     1097688 :     SmallVector<unsigned, 2> ForbidRegs;
     588             : 
     589             :     // If MI's defs have a special allocation requirement, don't allow
     590             :     // any def registers to be changed. Also assume all registers
     591             :     // defined in a call must not be changed (ABI).
     592     1097688 :     if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI))
     593             :       // If this instruction's defs have special allocation requirement, don't
     594             :       // break this anti-dependency.
     595           0 :       AntiDepReg = 0;
     596      548844 :     else if (AntiDepReg) {
     597             :       // If this instruction has a use of AntiDepReg, breaking it
     598             :       // is invalid.  If the instruction defines other registers,
     599             :       // save a list of them so that we don't pick a new register
     600             :       // that overlaps any of them.
     601      114208 :       for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     602      195754 :         MachineOperand &MO = MI.getOperand(i);
     603      162793 :         if (!MO.isReg()) continue;
     604       65393 :         unsigned Reg = MO.getReg();
     605       65393 :         if (Reg == 0) continue;
     606       32961 :         if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
     607         150 :           AntiDepReg = 0;
     608         150 :           break;
     609             :         }
     610       49292 :         if (MO.isDef() && Reg != AntiDepReg)
     611           0 :           ForbidRegs.push_back(Reg);
     612             :       }
     613             :     }
     614             : 
     615             :     // Determine AntiDepReg's register class, if it is live and is
     616             :     // consistently used within a single class.
     617      565175 :     const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg]
     618       16331 :                                                     : nullptr;
     619             :     assert((AntiDepReg == 0 || RC != nullptr) &&
     620             :            "Register should be live if it's causing an anti-dependence!");
     621       16331 :     if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
     622        1314 :       AntiDepReg = 0;
     623             : 
     624             :     // Look for a suitable register to use to break the anti-dependence.
     625             :     //
     626             :     // TODO: Instead of picking the first free register, consider which might
     627             :     // be the best.
     628      548844 :     if (AntiDepReg != 0) {
     629             :       std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
     630             :                 std::multimap<unsigned, MachineOperand *>::iterator>
     631       30034 :         Range = RegRefs.equal_range(AntiDepReg);
     632       60068 :       if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
     633             :                                                      AntiDepReg,
     634       30034 :                                                      LastNewReg[AntiDepReg],
     635       15017 :                                                      RC, ForbidRegs)) {
     636             :         DEBUG(dbgs() << "Breaking anti-dependence edge on "
     637             :               << TRI->getName(AntiDepReg)
     638             :               << " with " << RegRefs.count(AntiDepReg) << " references"
     639             :               << " using " << TRI->getName(NewReg) << "!\n");
     640             : 
     641             :         // Update the references to the old register to refer to the new
     642             :         // register.
     643             :         for (std::multimap<unsigned, MachineOperand *>::iterator
     644       91683 :              Q = Range.first, QE = Range.second; Q != QE; ++Q) {
     645       76853 :           Q->second->setReg(NewReg);
     646             :           // If the SU for the instruction being updated has debug information
     647             :           // related to the anti-dependency register, make sure to update that
     648             :           // as well.
     649      153706 :           const SUnit *SU = MISUnitMap[Q->second->getParent()];
     650       76853 :           if (!SU) continue;
     651      153706 :           UpdateDbgValues(DbgValues, Q->second->getParent(),
     652             :                           AntiDepReg, NewReg);
     653             :         }
     654             : 
     655             :         // We just went back in time and modified history; the
     656             :         // liveness information for the anti-dependence reg is now
     657             :         // inconsistent. Set the state as if it were dead.
     658       44490 :         Classes[NewReg] = Classes[AntiDepReg];
     659       44490 :         DefIndices[NewReg] = DefIndices[AntiDepReg];
     660       44490 :         KillIndices[NewReg] = KillIndices[AntiDepReg];
     661             :         assert(((KillIndices[NewReg] == ~0u) !=
     662             :                 (DefIndices[NewReg] == ~0u)) &&
     663             :              "Kill and Def maps aren't consistent for NewReg!");
     664             : 
     665       29660 :         Classes[AntiDepReg] = nullptr;
     666       44490 :         DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
     667       29660 :         KillIndices[AntiDepReg] = ~0u;
     668             :         assert(((KillIndices[AntiDepReg] == ~0u) !=
     669             :                 (DefIndices[AntiDepReg] == ~0u)) &&
     670             :              "Kill and Def maps aren't consistent for AntiDepReg!");
     671             : 
     672       29660 :         RegRefs.erase(AntiDepReg);
     673       29660 :         LastNewReg[AntiDepReg] = NewReg;
     674       14830 :         ++Broken;
     675             :       }
     676             :     }
     677             : 
     678      548844 :     ScanInstruction(MI, Count);
     679             :   }
     680             : 
     681      123357 :   return Broken;
     682             : }

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