LCOV - code coverage report
Current view: top level - lib/CodeGen - DetectDeadLanes.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 201 206 97.6 %
Date: 2018-05-20 00:06:23 Functions: 19 19 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- DetectDeadLanes.cpp - SubRegister Lane Usage Analysis --*- C++ -*---===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// Analysis that tracks defined/used subregister lanes across COPY instructions
      12             : /// and instructions that get lowered to a COPY (PHI, REG_SEQUENCE,
      13             : /// INSERT_SUBREG, EXTRACT_SUBREG).
      14             : /// The information is used to detect dead definitions and the usage of
      15             : /// (completely) undefined values and mark the operands as such.
      16             : /// This pass is necessary because the dead/undef status is not obvious anymore
      17             : /// when subregisters are involved.
      18             : ///
      19             : /// Example:
      20             : ///    %0 = some definition
      21             : ///    %1 = IMPLICIT_DEF
      22             : ///    %2 = REG_SEQUENCE %0, sub0, %1, sub1
      23             : ///    %3 = EXTRACT_SUBREG %2, sub1
      24             : ///       = use %3
      25             : /// The %0 definition is dead and %3 contains an undefined value.
      26             : //
      27             : //===----------------------------------------------------------------------===//
      28             : 
      29             : #include <deque>
      30             : #include <vector>
      31             : 
      32             : #include "llvm/ADT/BitVector.h"
      33             : #include "llvm/ADT/SetVector.h"
      34             : #include "llvm/CodeGen/MachineFunctionPass.h"
      35             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      36             : #include "llvm/CodeGen/Passes.h"
      37             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      38             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      39             : #include "llvm/InitializePasses.h"
      40             : #include "llvm/Pass.h"
      41             : #include "llvm/PassRegistry.h"
      42             : #include "llvm/Support/Debug.h"
      43             : #include "llvm/Support/raw_ostream.h"
      44             : 
      45             : using namespace llvm;
      46             : 
      47             : #define DEBUG_TYPE "detect-dead-lanes"
      48             : 
      49             : namespace {
      50             : 
      51             : /// Contains a bitmask of which lanes of a given virtual register are
      52             : /// defined and which ones are actually used.
      53             : struct VRegInfo {
      54             :   LaneBitmask UsedLanes;
      55             :   LaneBitmask DefinedLanes;
      56             : };
      57             : 
      58       54636 : class DetectDeadLanes : public MachineFunctionPass {
      59             : public:
      60             :   bool runOnMachineFunction(MachineFunction &MF) override;
      61             : 
      62             :   static char ID;
      63       36610 :   DetectDeadLanes() : MachineFunctionPass(ID) {}
      64             : 
      65       18177 :   StringRef getPassName() const override { return "Detect Dead Lanes"; }
      66             : 
      67       18161 :   void getAnalysisUsage(AnalysisUsage &AU) const override {
      68       18161 :     AU.setPreservesCFG();
      69       18161 :     MachineFunctionPass::getAnalysisUsage(AU);
      70       18161 :   }
      71             : 
      72             : private:
      73             :   /// Add used lane bits on the register used by operand \p MO. This translates
      74             :   /// the bitmask based on the operands subregister, and puts the register into
      75             :   /// the worklist if any new bits were added.
      76             :   void addUsedLanesOnOperand(const MachineOperand &MO, LaneBitmask UsedLanes);
      77             : 
      78             :   /// Given a bitmask \p UsedLanes for the used lanes on a def output of a
      79             :   /// COPY-like instruction determine the lanes used on the use operands
      80             :   /// and call addUsedLanesOnOperand() for them.
      81             :   void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes);
      82             : 
      83             :   /// Given a use regiser operand \p Use and a mask of defined lanes, check
      84             :   /// if the operand belongs to a lowersToCopies() instruction, transfer the
      85             :   /// mask to the def and put the instruction into the worklist.
      86             :   void transferDefinedLanesStep(const MachineOperand &Use,
      87             :                                 LaneBitmask DefinedLanes);
      88             : 
      89             :   /// Given a mask \p DefinedLanes of lanes defined at operand \p OpNum
      90             :   /// of COPY-like instruction, determine which lanes are defined at the output
      91             :   /// operand \p Def.
      92             :   LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
      93             :                                    LaneBitmask DefinedLanes) const;
      94             : 
      95             :   /// Given a mask \p UsedLanes used from the output of instruction \p MI
      96             :   /// determine which lanes are used from operand \p MO of this instruction.
      97             :   LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes,
      98             :                                 const MachineOperand &MO) const;
      99             : 
     100             :   bool runOnce(MachineFunction &MF);
     101             : 
     102             :   LaneBitmask determineInitialDefinedLanes(unsigned Reg);
     103             :   LaneBitmask determineInitialUsedLanes(unsigned Reg);
     104             : 
     105             :   bool isUndefRegAtInput(const MachineOperand &MO,
     106             :                          const VRegInfo &RegInfo) const;
     107             : 
     108             :   bool isUndefInput(const MachineOperand &MO, bool *CrossCopy) const;
     109             : 
     110             :   const MachineRegisterInfo *MRI;
     111             :   const TargetRegisterInfo *TRI;
     112             : 
     113      256195 :   void PutInWorklist(unsigned RegIdx) {
     114      512390 :     if (WorklistMembers.test(RegIdx))
     115             :       return;
     116             :     WorklistMembers.set(RegIdx);
     117      194835 :     Worklist.push_back(RegIdx);
     118             :   }
     119             : 
     120             :   VRegInfo *VRegInfos;
     121             :   /// Worklist containing virtreg indexes.
     122             :   std::deque<unsigned> Worklist;
     123             :   BitVector WorklistMembers;
     124             :   /// This bitvector is set for each vreg index where the vreg is defined
     125             :   /// by an instruction where lowersToCopies()==true.
     126             :   BitVector DefinedByCopy;
     127             : };
     128             : 
     129             : } // end anonymous namespace
     130             : 
     131             : char DetectDeadLanes::ID = 0;
     132             : char &llvm::DetectDeadLanesID = DetectDeadLanes::ID;
     133             : 
     134      143808 : INITIALIZE_PASS(DetectDeadLanes, DEBUG_TYPE, "Detect Dead Lanes", false, false)
     135             : 
     136             : /// Returns true if \p MI will get lowered to a series of COPY instructions.
     137             : /// We call this a COPY-like instruction.
     138             : static bool lowersToCopies(const MachineInstr &MI) {
     139             :   // Note: We could support instructions with MCInstrDesc::isRegSequenceLike(),
     140             :   // isExtractSubRegLike(), isInsertSubregLike() in the future even though they
     141             :   // are not lowered to a COPY.
     142     1142803 :   switch (MI.getOpcode()) {
     143             :   case TargetOpcode::COPY:
     144             :   case TargetOpcode::PHI:
     145             :   case TargetOpcode::INSERT_SUBREG:
     146             :   case TargetOpcode::REG_SEQUENCE:
     147             :   case TargetOpcode::EXTRACT_SUBREG:
     148             :     return true;
     149             :   }
     150             :   return false;
     151             : }
     152             : 
     153      425728 : static bool isCrossCopy(const MachineRegisterInfo &MRI,
     154             :                         const MachineInstr &MI,
     155             :                         const TargetRegisterClass *DstRC,
     156             :                         const MachineOperand &MO) {
     157             :   assert(lowersToCopies(MI));
     158      425728 :   unsigned SrcReg = MO.getReg();
     159             :   const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
     160      425728 :   if (DstRC == SrcRC)
     161             :     return false;
     162             : 
     163             :   unsigned SrcSubIdx = MO.getSubReg();
     164             : 
     165      387330 :   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
     166             :   unsigned DstSubIdx = 0;
     167      774660 :   switch (MI.getOpcode()) {
     168             :   case TargetOpcode::INSERT_SUBREG:
     169        1409 :     if (MI.getOperandNo(&MO) == 2)
     170        1375 :       DstSubIdx = MI.getOperand(3).getImm();
     171             :     break;
     172             :   case TargetOpcode::REG_SEQUENCE: {
     173             :     unsigned OpNum = MI.getOperandNo(&MO);
     174      496240 :     DstSubIdx = MI.getOperand(OpNum+1).getImm();
     175      248120 :     break;
     176             :   }
     177          10 :   case TargetOpcode::EXTRACT_SUBREG: {
     178          10 :     unsigned SubReg = MI.getOperand(2).getImm();
     179             :     SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
     180             :   }
     181             :   }
     182             : 
     183             :   unsigned PreA, PreB; // Unused.
     184      387330 :   if (SrcSubIdx && DstSubIdx)
     185          26 :     return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
     186          26 :                                        PreB);
     187      387304 :   if (SrcSubIdx)
     188       84847 :     return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
     189      302457 :   if (DstSubIdx)
     190      249469 :     return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
     191       52988 :   return !TRI.getCommonSubClass(SrcRC, DstRC);
     192             : }
     193             : 
     194      262986 : void DetectDeadLanes::addUsedLanesOnOperand(const MachineOperand &MO,
     195             :                                             LaneBitmask UsedLanes) {
     196             :   if (!MO.readsReg())
     197             :     return;
     198      262873 :   unsigned MOReg = MO.getReg();
     199      262873 :   if (!TargetRegisterInfo::isVirtualRegister(MOReg))
     200             :     return;
     201             : 
     202             :   unsigned MOSubReg = MO.getSubReg();
     203      262873 :   if (MOSubReg != 0)
     204       77271 :     UsedLanes = TRI->composeSubRegIndexLaneMask(MOSubReg, UsedLanes);
     205      262873 :   UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg);
     206             : 
     207             :   unsigned MORegIdx = TargetRegisterInfo::virtReg2Index(MOReg);
     208      262873 :   VRegInfo &MORegInfo = VRegInfos[MORegIdx];
     209      262873 :   LaneBitmask PrevUsedLanes = MORegInfo.UsedLanes;
     210             :   // Any change at all?
     211      262873 :   if ((UsedLanes & ~PrevUsedLanes).none())
     212             :     return;
     213             : 
     214             :   // Set UsedLanes and remember instruction for further propagation.
     215      161702 :   MORegInfo.UsedLanes = PrevUsedLanes | UsedLanes;
     216      161702 :   if (DefinedByCopy.test(MORegIdx))
     217       50814 :     PutInWorklist(MORegIdx);
     218             : }
     219             : 
     220      194835 : void DetectDeadLanes::transferUsedLanesStep(const MachineInstr &MI,
     221             :                                             LaneBitmask UsedLanes) {
     222     1133343 :   for (const MachineOperand &MO : MI.uses()) {
     223      773128 :     if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
     224      206268 :       continue;
     225      262986 :     LaneBitmask UsedOnMO = transferUsedLanes(MI, UsedLanes, MO);
     226      262986 :     addUsedLanesOnOperand(MO, UsedOnMO);
     227             :   }
     228      194835 : }
     229             : 
     230      468439 : LaneBitmask DetectDeadLanes::transferUsedLanes(const MachineInstr &MI,
     231             :                                                LaneBitmask UsedLanes,
     232             :                                                const MachineOperand &MO) const {
     233             :   unsigned OpNum = MI.getOperandNo(&MO);
     234             :   assert(lowersToCopies(MI) && DefinedByCopy[
     235             :            TargetRegisterInfo::virtReg2Index(MI.getOperand(0).getReg())]);
     236             : 
     237      936878 :   switch (MI.getOpcode()) {
     238      185137 :   case TargetOpcode::COPY:
     239             :   case TargetOpcode::PHI:
     240      185137 :     return UsedLanes;
     241      280005 :   case TargetOpcode::REG_SEQUENCE: {
     242             :     assert(OpNum % 2 == 1);
     243      560010 :     unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
     244      280005 :     return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
     245             :   }
     246        3287 :   case TargetOpcode::INSERT_SUBREG: {
     247        3287 :     unsigned SubIdx = MI.getOperand(3).getImm();
     248             :     LaneBitmask MO2UsedLanes =
     249        3287 :         TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
     250        3287 :     if (OpNum == 2)
     251        1775 :       return MO2UsedLanes;
     252             : 
     253        1512 :     const MachineOperand &Def = MI.getOperand(0);
     254        1512 :     unsigned DefReg = Def.getReg();
     255        1512 :     const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
     256             :     LaneBitmask MO1UsedLanes;
     257        1512 :     if (RC->CoveredBySubRegs)
     258        1329 :       MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
     259             :     else
     260         183 :       MO1UsedLanes = RC->LaneMask;
     261             : 
     262             :     assert(OpNum == 1);
     263        1512 :     return MO1UsedLanes;
     264             :   }
     265          10 :   case TargetOpcode::EXTRACT_SUBREG: {
     266             :     assert(OpNum == 1);
     267          10 :     unsigned SubIdx = MI.getOperand(2).getImm();
     268          10 :     return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes);
     269             :   }
     270           0 :   default:
     271           0 :     llvm_unreachable("function must be called with COPY-like instruction");
     272             :   }
     273             : }
     274             : 
     275      257200 : void DetectDeadLanes::transferDefinedLanesStep(const MachineOperand &Use,
     276             :                                                LaneBitmask DefinedLanes) {
     277             :   if (!Use.readsReg())
     278             :     return;
     279             :   // Check whether the operand writes a vreg and is part of a COPY-like
     280             :   // instruction.
     281      257080 :   const MachineInstr &MI = *Use.getParent();
     282      514160 :   if (MI.getDesc().getNumDefs() != 1)
     283             :     return;
     284             :   // FIXME: PATCHPOINT instructions announce a Def that does not always exist,
     285             :   // they really need to be modeled differently!
     286      201316 :   if (MI.getOpcode() == TargetOpcode::PATCHPOINT)
     287             :     return;
     288             :   const MachineOperand &Def = *MI.defs().begin();
     289      201316 :   unsigned DefReg = Def.getReg();
     290      201316 :   if (!TargetRegisterInfo::isVirtualRegister(DefReg))
     291             :     return;
     292             :   unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg);
     293      196224 :   if (!DefinedByCopy.test(DefRegIdx))
     294             :     return;
     295             : 
     296             :   unsigned OpNum = MI.getOperandNo(&Use);
     297             :   DefinedLanes =
     298      107122 :       TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
     299      107122 :   DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes);
     300             : 
     301      107122 :   VRegInfo &RegInfo = VRegInfos[DefRegIdx];
     302      107122 :   LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes;
     303             :   // Any change at all?
     304      107122 :   if ((DefinedLanes & ~PrevDefinedLanes).none())
     305             :     return;
     306             : 
     307       51174 :   RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes;
     308       51174 :   PutInWorklist(DefRegIdx);
     309             : }
     310             : 
     311      297800 : LaneBitmask DetectDeadLanes::transferDefinedLanes(const MachineOperand &Def,
     312             :     unsigned OpNum, LaneBitmask DefinedLanes) const {
     313      297800 :   const MachineInstr &MI = *Def.getParent();
     314             :   // Translate DefinedLanes if necessary.
     315      595600 :   switch (MI.getOpcode()) {
     316      168664 :   case TargetOpcode::REG_SEQUENCE: {
     317      337328 :     unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
     318      168664 :     DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
     319      168664 :     DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
     320             :     break;
     321             :   }
     322        2031 :   case TargetOpcode::INSERT_SUBREG: {
     323        2031 :     unsigned SubIdx = MI.getOperand(3).getImm();
     324        2031 :     if (OpNum == 2) {
     325        1203 :       DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
     326        1203 :       DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
     327             :     } else {
     328             :       assert(OpNum == 1 && "INSERT_SUBREG must have two operands");
     329             :       // Ignore lanes defined by operand 2.
     330         828 :       DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx);
     331             :     }
     332             :     break;
     333             :   }
     334           6 :   case TargetOpcode::EXTRACT_SUBREG: {
     335           6 :     unsigned SubIdx = MI.getOperand(2).getImm();
     336             :     assert(OpNum == 1 && "EXTRACT_SUBREG must have one register operand only");
     337           6 :     DefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(SubIdx, DefinedLanes);
     338             :     break;
     339             :   }
     340             :   case TargetOpcode::COPY:
     341             :   case TargetOpcode::PHI:
     342             :     break;
     343           0 :   default:
     344           0 :     llvm_unreachable("function must be called with COPY-like instruction");
     345             :   }
     346             : 
     347             :   assert(Def.getSubReg() == 0 &&
     348             :          "Should not have subregister defs in machine SSA phase");
     349      297800 :   DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg());
     350      297800 :   return DefinedLanes;
     351             : }
     352             : 
     353      717718 : LaneBitmask DetectDeadLanes::determineInitialDefinedLanes(unsigned Reg) {
     354             :   // Live-In or unused registers have no definition but are considered fully
     355             :   // defined.
     356      717718 :   if (!MRI->hasOneDef(Reg))
     357      316814 :     return LaneBitmask::getAll();
     358             : 
     359      801808 :   const MachineOperand &Def = *MRI->def_begin(Reg);
     360      400904 :   const MachineInstr &DefMI = *Def.getParent();
     361             :   if (lowersToCopies(DefMI)) {
     362             :     // Start optimisatically with no used or defined lanes for copy
     363             :     // instructions. The following dataflow analysis will add more bits.
     364             :     unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg);
     365             :     DefinedByCopy.set(RegIdx);
     366      154207 :     PutInWorklist(RegIdx);
     367             : 
     368      154207 :     if (Def.isDead())
     369          34 :       return LaneBitmask::getNone();
     370             : 
     371             :     // COPY/PHI can copy across unrelated register classes (example: float/int)
     372             :     // with incompatible subregister structure. Do not include these in the
     373             :     // dataflow analysis since we cannot transfer lanemasks in a meaningful way.
     374      154173 :     const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
     375             : 
     376             :     // Determine initially DefinedLanes.
     377             :     LaneBitmask DefinedLanes;
     378      943153 :     for (const MachineOperand &MO : DefMI.uses()) {
     379      539396 :       if (!MO.isReg() || !MO.readsReg())
     380      144906 :         continue;
     381      249584 :       unsigned MOReg = MO.getReg();
     382      249584 :       if (!MOReg)
     383           0 :         continue;
     384             : 
     385             :       LaneBitmask MODefinedLanes;
     386      249584 :       if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
     387             :         MODefinedLanes = LaneBitmask::getAll();
     388      214347 :       } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
     389             :         MODefinedLanes = LaneBitmask::getAll();
     390             :       } else {
     391             :         assert(TargetRegisterInfo::isVirtualRegister(MOReg));
     392      187979 :         if (MRI->hasOneDef(MOReg)) {
     393      375958 :           const MachineOperand &MODef = *MRI->def_begin(MOReg);
     394      187979 :           const MachineInstr &MODefMI = *MODef.getParent();
     395             :           // Bits from copy-like operations will be added later.
     396      132917 :           if (lowersToCopies(MODefMI) || MODefMI.isImplicitDef())
     397       58906 :             continue;
     398             :         }
     399             :         unsigned MOSubReg = MO.getSubReg();
     400      129073 :         MODefinedLanes = MRI->getMaxLaneMaskForVReg(MOReg);
     401      129073 :         MODefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(
     402             :             MOSubReg, MODefinedLanes);
     403             :       }
     404             : 
     405             :       unsigned OpNum = DefMI.getOperandNo(&MO);
     406             :       DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes);
     407             :     }
     408      154173 :     return DefinedLanes;
     409             :   }
     410      487378 :   if (DefMI.isImplicitDef() || Def.isDead())
     411       11223 :     return LaneBitmask::getNone();
     412             : 
     413             :   assert(Def.getSubReg() == 0 &&
     414             :          "Should not have subregister defs in machine SSA phase");
     415      235474 :   return MRI->getMaxLaneMaskForVReg(Reg);
     416             : }
     417             : 
     418      717718 : LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) {
     419             :   LaneBitmask UsedLanes = LaneBitmask::getNone();
     420     1653120 :   for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
     421         162 :     if (!MO.readsReg())
     422             :       continue;
     423             : 
     424      466641 :     const MachineInstr &UseMI = *MO.getParent();
     425      466641 :     if (UseMI.isKill())
     426             :       continue;
     427             : 
     428             :     unsigned SubReg = MO.getSubReg();
     429             :     if (lowersToCopies(UseMI)) {
     430             :       assert(UseMI.getDesc().getNumDefs() == 1);
     431             :       const MachineOperand &Def = *UseMI.defs().begin();
     432      219906 :       unsigned DefReg = Def.getReg();
     433             :       // The used lanes of COPY-like instruction operands are determined by the
     434             :       // following dataflow analysis.
     435      219906 :       if (TargetRegisterInfo::isVirtualRegister(DefReg)) {
     436             :         // But ignore copies across incompatible register classes.
     437             :         bool CrossCopy = false;
     438             :         if (lowersToCopies(UseMI)) {
     439      211249 :           const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
     440      211249 :           CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
     441             :           if (CrossCopy)
     442             :             LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
     443             :         }
     444             : 
     445      211249 :         if (!CrossCopy)
     446             :           continue;
     447             :       }
     448             :     }
     449             : 
     450             :     // Shortcut: All lanes are used.
     451      281547 :     if (SubReg == 0)
     452      249119 :       return MRI->getMaxLaneMaskForVReg(Reg);
     453             : 
     454       32428 :     UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
     455             :   }
     456      468599 :   return UsedLanes;
     457             : }
     458             : 
     459             : bool DetectDeadLanes::isUndefRegAtInput(const MachineOperand &MO,
     460             :                                         const VRegInfo &RegInfo) const {
     461             :   unsigned SubReg = MO.getSubReg();
     462      564663 :   LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
     463             :   return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none();
     464             : }
     465             : 
     466      553920 : bool DetectDeadLanes::isUndefInput(const MachineOperand &MO,
     467             :                                    bool *CrossCopy) const {
     468      553920 :   if (!MO.isUse())
     469             :     return false;
     470      553920 :   const MachineInstr &MI = *MO.getParent();
     471             :   if (!lowersToCopies(MI))
     472             :     return false;
     473      214112 :   const MachineOperand &Def = MI.getOperand(0);
     474      214112 :   unsigned DefReg = Def.getReg();
     475      214112 :   if (!TargetRegisterInfo::isVirtualRegister(DefReg))
     476             :     return false;
     477             :   unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg);
     478      205453 :   if (!DefinedByCopy.test(DefRegIdx))
     479             :     return false;
     480             : 
     481      205453 :   const VRegInfo &DefRegInfo = VRegInfos[DefRegIdx];
     482      205453 :   LaneBitmask UsedLanes = transferUsedLanes(MI, DefRegInfo.UsedLanes, MO);
     483      205453 :   if (UsedLanes.any())
     484             :     return false;
     485             : 
     486         132 :   unsigned MOReg = MO.getReg();
     487         132 :   if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
     488         132 :     const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
     489         132 :     *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO);
     490             :   }
     491             :   return true;
     492             : }
     493             : 
     494       22767 : bool DetectDeadLanes::runOnce(MachineFunction &MF) {
     495             :   // First pass: Populate defs/uses of vregs with initial values
     496       22767 :   unsigned NumVirtRegs = MRI->getNumVirtRegs();
     497     1458203 :   for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
     498             :     unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
     499             : 
     500             :     // Determine used/defined lanes and add copy instructions to worklist.
     501      717718 :     VRegInfo &Info = VRegInfos[RegIdx];
     502      717718 :     Info.DefinedLanes = determineInitialDefinedLanes(Reg);
     503      717718 :     Info.UsedLanes = determineInitialUsedLanes(Reg);
     504             :   }
     505             : 
     506             :   // Iterate as long as defined lanes/used lanes keep changing.
     507      217602 :   while (!Worklist.empty()) {
     508      194835 :     unsigned RegIdx = Worklist.front();
     509      194835 :     Worklist.pop_front();
     510             :     WorklistMembers.reset(RegIdx);
     511      194835 :     VRegInfo &Info = VRegInfos[RegIdx];
     512             :     unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
     513             : 
     514             :     // Transfer UsedLanes to operands of DefMI (backwards dataflow).
     515      389670 :     MachineOperand &Def = *MRI->def_begin(Reg);
     516      194835 :     const MachineInstr &MI = *Def.getParent();
     517      194835 :     transferUsedLanesStep(MI, Info.UsedLanes);
     518             :     // Transfer DefinedLanes to users of Reg (forward dataflow).
     519      646870 :     for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg))
     520      257200 :       transferDefinedLanesStep(MO, Info.DefinedLanes);
     521             :   }
     522             : 
     523             :   LLVM_DEBUG(dbgs() << "Defined/Used lanes:\n"; for (unsigned RegIdx = 0;
     524             :                                                      RegIdx < NumVirtRegs;
     525             :                                                      ++RegIdx) {
     526             :     unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
     527             :     const VRegInfo &Info = VRegInfos[RegIdx];
     528             :     dbgs() << printReg(Reg, nullptr)
     529             :            << " Used: " << PrintLaneMask(Info.UsedLanes)
     530             :            << " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
     531             :   } dbgs() << "\n";);
     532             : 
     533             :   bool Again = false;
     534             :   // Mark operands as dead/unused.
     535       50021 :   for (MachineBasicBlock &MBB : MF) {
     536      529924 :     for (MachineInstr &MI : MBB) {
     537     5587408 :       for (MachineOperand &MO : MI.operands()) {
     538     2555996 :         if (!MO.isReg())
     539     1240170 :           continue;
     540     1315826 :         unsigned Reg = MO.getReg();
     541     1315826 :         if (!TargetRegisterInfo::isVirtualRegister(Reg))
     542      350093 :           continue;
     543             :         unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg);
     544      965733 :         const VRegInfo &RegInfo = VRegInfos[RegIdx];
     545     1762291 :         if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) {
     546             :           LLVM_DEBUG(dbgs()
     547             :                      << "Marking operand '" << MO << "' as dead in " << MI);
     548             :           MO.setIsDead();
     549             :         }
     550             :         if (MO.readsReg()) {
     551      564663 :           bool CrossCopy = false;
     552     1129326 :           if (isUndefRegAtInput(MO, RegInfo)) {
     553             :             LLVM_DEBUG(dbgs()
     554             :                        << "Marking operand '" << MO << "' as undef in " << MI);
     555             :             MO.setIsUndef();
     556      553920 :           } else if (isUndefInput(MO, &CrossCopy)) {
     557             :             LLVM_DEBUG(dbgs()
     558             :                        << "Marking operand '" << MO << "' as undef in " << MI);
     559             :             MO.setIsUndef();
     560         132 :             if (CrossCopy)
     561             :               Again = true;
     562             :           }
     563             :         }
     564             :       }
     565             :     }
     566             :   }
     567             : 
     568       22767 :   return Again;
     569             : }
     570             : 
     571      169103 : bool DetectDeadLanes::runOnMachineFunction(MachineFunction &MF) {
     572             :   // Don't bother if we won't track subregister liveness later.  This pass is
     573             :   // required for correctness if subregister liveness is enabled because the
     574             :   // register coalescer cannot deal with hidden dead defs. However without
     575             :   // subregister liveness enabled, the expected benefits of this pass are small
     576             :   // so we safe the compile time.
     577      169103 :   MRI = &MF.getRegInfo();
     578      169103 :   if (!MRI->subRegLivenessEnabled()) {
     579             :     LLVM_DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");
     580             :     return false;
     581             :   }
     582             : 
     583       45508 :   TRI = MRI->getTargetRegisterInfo();
     584             : 
     585       22754 :   unsigned NumVirtRegs = MRI->getNumVirtRegs();
     586      739635 :   VRegInfos = new VRegInfo[NumVirtRegs];
     587       22754 :   WorklistMembers.resize(NumVirtRegs);
     588       22754 :   DefinedByCopy.resize(NumVirtRegs);
     589             : 
     590             :   bool Again;
     591       22767 :   do {
     592       22767 :     Again = runOnce(MF);
     593             :   } while(Again);
     594             : 
     595             :   DefinedByCopy.clear();
     596             :   WorklistMembers.clear();
     597       22754 :   delete[] VRegInfos;
     598             :   return true;
     599             : }

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