LCOV - code coverage report
Current view: top level - lib/CodeGen - DetectDeadLanes.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 240 245 98.0 %
Date: 2017-09-14 15:23:50 Functions: 19 19 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- DetectDeadLanes.cpp - SubRegister Lane Usage Analysis --*- C++ -*---===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : /// \file
      11             : /// Analysis that tracks defined/used subregister lanes across COPY instructions
      12             : /// and instructions that get lowered to a COPY (PHI, REG_SEQUENCE,
      13             : /// INSERT_SUBREG, EXTRACT_SUBREG).
      14             : /// The information is used to detect dead definitions and the usage of
      15             : /// (completely) undefined values and mark the operands as such.
      16             : /// This pass is necessary because the dead/undef status is not obvious anymore
      17             : /// when subregisters are involved.
      18             : ///
      19             : /// Example:
      20             : ///    %vreg0 = some definition
      21             : ///    %vreg1 = IMPLICIT_DEF
      22             : ///    %vreg2 = REG_SEQUENCE %vreg0, sub0, %vreg1, sub1
      23             : ///    %vreg3 = EXTRACT_SUBREG %vreg2, sub1
      24             : ///           = use %vreg3
      25             : /// The %vreg0 definition is dead and %vreg3 contains an undefined value.
      26             : //
      27             : //===----------------------------------------------------------------------===//
      28             : 
      29             : #include <deque>
      30             : #include <vector>
      31             : 
      32             : #include "llvm/ADT/BitVector.h"
      33             : #include "llvm/ADT/SetVector.h"
      34             : #include "llvm/CodeGen/MachineFunctionPass.h"
      35             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      36             : #include "llvm/CodeGen/Passes.h"
      37             : #include "llvm/InitializePasses.h"
      38             : #include "llvm/Pass.h"
      39             : #include "llvm/PassRegistry.h"
      40             : #include "llvm/Support/Debug.h"
      41             : #include "llvm/Support/raw_ostream.h"
      42             : #include "llvm/Target/TargetInstrInfo.h"
      43             : #include "llvm/Target/TargetRegisterInfo.h"
      44             : #include "llvm/Target/TargetSubtargetInfo.h"
      45             : 
      46             : using namespace llvm;
      47             : 
      48             : #define DEBUG_TYPE "detect-dead-lanes"
      49             : 
      50             : namespace {
      51             : 
      52             : /// Contains a bitmask of which lanes of a given virtual register are
      53             : /// defined and which ones are actually used.
      54     1920669 : struct VRegInfo {
      55             :   LaneBitmask UsedLanes;
      56             :   LaneBitmask DefinedLanes;
      57             : };
      58             : 
      59       76534 : class DetectDeadLanes : public MachineFunctionPass {
      60             : public:
      61             :   bool runOnMachineFunction(MachineFunction &MF) override;
      62             : 
      63             :   static char ID;
      64       61592 :   DetectDeadLanes() : MachineFunctionPass(ID) {}
      65             : 
      66       15362 :   StringRef getPassName() const override { return "Detect Dead Lanes"; }
      67             : 
      68       15347 :   void getAnalysisUsage(AnalysisUsage &AU) const override {
      69       15347 :     AU.setPreservesCFG();
      70       15347 :     MachineFunctionPass::getAnalysisUsage(AU);
      71       15347 :   }
      72             : 
      73             : private:
      74             :   /// Add used lane bits on the register used by operand \p MO. This translates
      75             :   /// the bitmask based on the operands subregister, and puts the register into
      76             :   /// the worklist if any new bits were added.
      77             :   void addUsedLanesOnOperand(const MachineOperand &MO, LaneBitmask UsedLanes);
      78             : 
      79             :   /// Given a bitmask \p UsedLanes for the used lanes on a def output of a
      80             :   /// COPY-like instruction determine the lanes used on the use operands
      81             :   /// and call addUsedLanesOnOperand() for them.
      82             :   void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes);
      83             : 
      84             :   /// Given a use regiser operand \p Use and a mask of defined lanes, check
      85             :   /// if the operand belongs to a lowersToCopies() instruction, transfer the
      86             :   /// mask to the def and put the instruction into the worklist.
      87             :   void transferDefinedLanesStep(const MachineOperand &Use,
      88             :                                 LaneBitmask DefinedLanes);
      89             : 
      90             :   /// Given a mask \p DefinedLanes of lanes defined at operand \p OpNum
      91             :   /// of COPY-like instruction, determine which lanes are defined at the output
      92             :   /// operand \p Def.
      93             :   LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
      94             :                                    LaneBitmask DefinedLanes) const;
      95             : 
      96             :   /// Given a mask \p UsedLanes used from the output of instruction \p MI
      97             :   /// determine which lanes are used from operand \p MO of this instruction.
      98             :   LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes,
      99             :                                 const MachineOperand &MO) const;
     100             : 
     101             :   bool runOnce(MachineFunction &MF);
     102             : 
     103             :   LaneBitmask determineInitialDefinedLanes(unsigned Reg);
     104             :   LaneBitmask determineInitialUsedLanes(unsigned Reg);
     105             : 
     106             :   bool isUndefRegAtInput(const MachineOperand &MO,
     107             :                          const VRegInfo &RegInfo) const;
     108             : 
     109             :   bool isUndefInput(const MachineOperand &MO, bool *CrossCopy) const;
     110             : 
     111             :   const MachineRegisterInfo *MRI;
     112             :   const TargetRegisterInfo *TRI;
     113             : 
     114      231232 :   void PutInWorklist(unsigned RegIdx) {
     115      462464 :     if (WorklistMembers.test(RegIdx))
     116             :       return;
     117      340726 :     WorklistMembers.set(RegIdx);
     118      170363 :     Worklist.push_back(RegIdx);
     119             :   }
     120             : 
     121             :   VRegInfo *VRegInfos;
     122             :   /// Worklist containing virtreg indexes.
     123             :   std::deque<unsigned> Worklist;
     124             :   BitVector WorklistMembers;
     125             :   /// This bitvector is set for each vreg index where the vreg is defined
     126             :   /// by an instruction where lowersToCopies()==true.
     127             :   BitVector DefinedByCopy;
     128             : };
     129             : 
     130             : } // end anonymous namespace
     131             : 
     132             : char DetectDeadLanes::ID = 0;
     133             : char &llvm::DetectDeadLanesID = DetectDeadLanes::ID;
     134             : 
     135      151199 : INITIALIZE_PASS(DetectDeadLanes, DEBUG_TYPE, "Detect Dead Lanes", false, false)
     136             : 
     137             : /// Returns true if \p MI will get lowered to a series of COPY instructions.
     138             : /// We call this a COPY-like instruction.
     139             : static bool lowersToCopies(const MachineInstr &MI) {
     140             :   // Note: We could support instructions with MCInstrDesc::isRegSequenceLike(),
     141             :   // isExtractSubRegLike(), isInsertSubregLike() in the future even though they
     142             :   // are not lowered to a COPY.
     143      606806 :   switch (MI.getOpcode()) {
     144             :   case TargetOpcode::COPY:
     145             :   case TargetOpcode::PHI:
     146             :   case TargetOpcode::INSERT_SUBREG:
     147             :   case TargetOpcode::REG_SEQUENCE:
     148             :   case TargetOpcode::EXTRACT_SUBREG:
     149             :     return true;
     150             :   }
     151             :   return false;
     152             : }
     153             : 
     154      390289 : static bool isCrossCopy(const MachineRegisterInfo &MRI,
     155             :                         const MachineInstr &MI,
     156             :                         const TargetRegisterClass *DstRC,
     157             :                         const MachineOperand &MO) {
     158             :   assert(lowersToCopies(MI));
     159      390289 :   unsigned SrcReg = MO.getReg();
     160      390289 :   const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
     161      390289 :   if (DstRC == SrcRC)
     162             :     return false;
     163             : 
     164      358093 :   unsigned SrcSubIdx = MO.getSubReg();
     165             : 
     166      716186 :   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
     167      358093 :   unsigned DstSubIdx = 0;
     168      716186 :   switch (MI.getOpcode()) {
     169         379 :   case TargetOpcode::INSERT_SUBREG:
     170         379 :     if (MI.getOperandNo(&MO) == 2)
     171         345 :       DstSubIdx = MI.getOperand(3).getImm();
     172             :     break;
     173      228995 :   case TargetOpcode::REG_SEQUENCE: {
     174      228995 :     unsigned OpNum = MI.getOperandNo(&MO);
     175      457990 :     DstSubIdx = MI.getOperand(OpNum+1).getImm();
     176      228995 :     break;
     177             :   }
     178          10 :   case TargetOpcode::EXTRACT_SUBREG: {
     179          10 :     unsigned SubReg = MI.getOperand(2).getImm();
     180             :     SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
     181             :   }
     182             :   }
     183             : 
     184             :   unsigned PreA, PreB; // Unused.
     185      358093 :   if (SrcSubIdx && DstSubIdx)
     186          49 :     return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
     187          49 :                                        PreB);
     188      358044 :   if (SrcSubIdx)
     189       78933 :     return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
     190      279111 :   if (DstSubIdx)
     191      229291 :     return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
     192       49820 :   return !TRI.getCommonSubClass(SrcRC, DstRC);
     193             : }
     194             : 
     195      245442 : void DetectDeadLanes::addUsedLanesOnOperand(const MachineOperand &MO,
     196             :                                             LaneBitmask UsedLanes) {
     197             :   if (!MO.readsReg())
     198             :     return;
     199      245371 :   unsigned MOReg = MO.getReg();
     200      245371 :   if (!TargetRegisterInfo::isVirtualRegister(MOReg))
     201             :     return;
     202             : 
     203      245371 :   unsigned MOSubReg = MO.getSubReg();
     204      245371 :   if (MOSubReg != 0)
     205      145286 :     UsedLanes = TRI->composeSubRegIndexLaneMask(MOSubReg, UsedLanes);
     206      490742 :   UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg);
     207             : 
     208      245371 :   unsigned MORegIdx = TargetRegisterInfo::virtReg2Index(MOReg);
     209      245371 :   VRegInfo &MORegInfo = VRegInfos[MORegIdx];
     210      245371 :   LaneBitmask PrevUsedLanes = MORegInfo.UsedLanes;
     211             :   // Any change at all?
     212      490742 :   if ((UsedLanes & ~PrevUsedLanes).none())
     213             :     return;
     214             : 
     215             :   // Set UsedLanes and remember instruction for further propagation.
     216      146377 :   MORegInfo.UsedLanes = PrevUsedLanes | UsedLanes;
     217      292754 :   if (DefinedByCopy.test(MORegIdx))
     218       48784 :     PutInWorklist(MORegIdx);
     219             : }
     220             : 
     221      170363 : void DetectDeadLanes::transferUsedLanesStep(const MachineInstr &MI,
     222             :                                             LaneBitmask UsedLanes) {
     223      596496 :   for (const MachineOperand &MO : MI.uses()) {
     224      697628 :     if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
     225      180691 :       continue;
     226      245442 :     LaneBitmask UsedOnMO = transferUsedLanes(MI, UsedLanes, MO);
     227      245442 :     addUsedLanesOnOperand(MO, UsedOnMO);
     228             :   }
     229      170363 : }
     230             : 
     231      434002 : LaneBitmask DetectDeadLanes::transferUsedLanes(const MachineInstr &MI,
     232             :                                                LaneBitmask UsedLanes,
     233             :                                                const MachineOperand &MO) const {
     234      434002 :   unsigned OpNum = MI.getOperandNo(&MO);
     235             :   assert(lowersToCopies(MI) && DefinedByCopy[
     236             :            TargetRegisterInfo::virtReg2Index(MI.getOperand(0).getReg())]);
     237             : 
     238      868004 :   switch (MI.getOpcode()) {
     239      169914 :   case TargetOpcode::COPY:
     240             :   case TargetOpcode::PHI:
     241      169914 :     return UsedLanes;
     242      263393 :   case TargetOpcode::REG_SEQUENCE: {
     243             :     assert(OpNum % 2 == 1);
     244      526786 :     unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
     245      263393 :     return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
     246             :   }
     247         685 :   case TargetOpcode::INSERT_SUBREG: {
     248         685 :     unsigned SubIdx = MI.getOperand(3).getImm();
     249             :     LaneBitmask MO2UsedLanes =
     250        1370 :         TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
     251         685 :     if (OpNum == 2)
     252         394 :       return MO2UsedLanes;
     253             : 
     254         291 :     const MachineOperand &Def = MI.getOperand(0);
     255         291 :     unsigned DefReg = Def.getReg();
     256         582 :     const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
     257         291 :     LaneBitmask MO1UsedLanes;
     258         291 :     if (RC->CoveredBySubRegs)
     259         416 :       MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
     260             :     else
     261         187 :       MO1UsedLanes = RC->LaneMask;
     262             : 
     263             :     assert(OpNum == 1);
     264         291 :     return MO1UsedLanes;
     265             :   }
     266          10 :   case TargetOpcode::EXTRACT_SUBREG: {
     267             :     assert(OpNum == 1);
     268          10 :     unsigned SubIdx = MI.getOperand(2).getImm();
     269          10 :     return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes);
     270             :   }
     271           0 :   default:
     272           0 :     llvm_unreachable("function must be called with COPY-like instruction");
     273             :   }
     274             : }
     275             : 
     276      225121 : void DetectDeadLanes::transferDefinedLanesStep(const MachineOperand &Use,
     277             :                                                LaneBitmask DefinedLanes) {
     278             :   if (!Use.readsReg())
     279             :     return;
     280             :   // Check whether the operand writes a vreg and is part of a COPY-like
     281             :   // instruction.
     282      225014 :   const MachineInstr &MI = *Use.getParent();
     283      225014 :   if (MI.getDesc().getNumDefs() != 1)
     284             :     return;
     285             :   // FIXME: PATCHPOINT instructions announce a Def that does not always exist,
     286             :   // they really need to be modeled differently!
     287      178600 :   if (MI.getOpcode() == TargetOpcode::PATCHPOINT)
     288             :     return;
     289      178600 :   const MachineOperand &Def = *MI.defs().begin();
     290      178600 :   unsigned DefReg = Def.getReg();
     291             :   if (!TargetRegisterInfo::isVirtualRegister(DefReg))
     292             :     return;
     293      175413 :   unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg);
     294      350826 :   if (!DefinedByCopy.test(DefRegIdx))
     295             :     return;
     296             : 
     297       95586 :   unsigned OpNum = MI.getOperandNo(&Use);
     298       95586 :   DefinedLanes =
     299      191172 :       TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
     300       95586 :   DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes);
     301             : 
     302       95586 :   VRegInfo &RegInfo = VRegInfos[DefRegIdx];
     303       95586 :   LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes;
     304             :   // Any change at all?
     305      191172 :   if ((DefinedLanes & ~PrevDefinedLanes).none())
     306             :     return;
     307             : 
     308       48942 :   RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes;
     309       48942 :   PutInWorklist(DefRegIdx);
     310             : }
     311             : 
     312      259753 : LaneBitmask DetectDeadLanes::transferDefinedLanes(const MachineOperand &Def,
     313             :     unsigned OpNum, LaneBitmask DefinedLanes) const {
     314      259753 :   const MachineInstr &MI = *Def.getParent();
     315             :   // Translate DefinedLanes if necessary.
     316      259753 :   switch (MI.getOpcode()) {
     317      154038 :   case TargetOpcode::REG_SEQUENCE: {
     318      308076 :     unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
     319      308076 :     DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
     320      308076 :     DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
     321             :     break;
     322             :   }
     323         294 :   case TargetOpcode::INSERT_SUBREG: {
     324         294 :     unsigned SubIdx = MI.getOperand(3).getImm();
     325         294 :     if (OpNum == 2) {
     326         348 :       DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
     327         348 :       DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
     328             :     } else {
     329             :       assert(OpNum == 1 && "INSERT_SUBREG must have two operands");
     330             :       // Ignore lanes defined by operand 2.
     331         480 :       DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx);
     332             :     }
     333             :     break;
     334             :   }
     335           6 :   case TargetOpcode::EXTRACT_SUBREG: {
     336           6 :     unsigned SubIdx = MI.getOperand(2).getImm();
     337             :     assert(OpNum == 1 && "EXTRACT_SUBREG must have one register operand only");
     338          12 :     DefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(SubIdx, DefinedLanes);
     339             :     break;
     340             :   }
     341             :   case TargetOpcode::COPY:
     342             :   case TargetOpcode::PHI:
     343             :     break;
     344           0 :   default:
     345           0 :     llvm_unreachable("function must be called with COPY-like instruction");
     346             :   }
     347             : 
     348             :   assert(Def.getSubReg() == 0 &&
     349             :          "Should not have subregister defs in machine SSA phase");
     350      519506 :   DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg());
     351      259753 :   return DefinedLanes;
     352             : }
     353             : 
     354      640858 : LaneBitmask DetectDeadLanes::determineInitialDefinedLanes(unsigned Reg) {
     355             :   // Live-In or unused registers have no definition but are considered fully
     356             :   // defined.
     357      640858 :   if (!MRI->hasOneDef(Reg))
     358             :     return LaneBitmask::getAll();
     359             : 
     360      691786 :   const MachineOperand &Def = *MRI->def_begin(Reg);
     361      345893 :   const MachineInstr &DefMI = *Def.getParent();
     362      345893 :   if (lowersToCopies(DefMI)) {
     363             :     // Start optimisatically with no used or defined lanes for copy
     364             :     // instructions. The following dataflow analysis will add more bits.
     365      133506 :     unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg);
     366      267012 :     DefinedByCopy.set(RegIdx);
     367      133506 :     PutInWorklist(RegIdx);
     368             : 
     369      133506 :     if (Def.isDead())
     370             :       return LaneBitmask::getNone();
     371             : 
     372             :     // COPY/PHI can copy across unrelated register classes (example: float/int)
     373             :     // with incompatible subregister structure. Do not include these in the
     374             :     // dataflow analysis since we cannot transfer lanemasks in a meaningful way.
     375      266982 :     const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
     376             : 
     377             :     // Determine initially DefinedLanes.
     378      133491 :     LaneBitmask DefinedLanes;
     379      485512 :     for (const MachineOperand &MO : DefMI.uses()) {
     380      483945 :       if (!MO.isReg() || !MO.readsReg())
     381      131924 :         continue;
     382      220097 :       unsigned MOReg = MO.getReg();
     383      220097 :       if (!MOReg)
     384           0 :         continue;
     385             : 
     386      220097 :       LaneBitmask MODefinedLanes;
     387      220097 :       if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
     388             :         MODefinedLanes = LaneBitmask::getAll();
     389      196292 :       } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
     390             :         MODefinedLanes = LaneBitmask::getAll();
     391             :       } else {
     392             :         assert(TargetRegisterInfo::isVirtualRegister(MOReg));
     393      171552 :         if (MRI->hasOneDef(MOReg)) {
     394      343104 :           const MachineOperand &MODef = *MRI->def_begin(MOReg);
     395      171552 :           const MachineInstr &MODefMI = *MODef.getParent();
     396             :           // Bits from copy-like operations will be added later.
     397      238354 :           if (lowersToCopies(MODefMI) || MODefMI.isImplicitDef())
     398       55930 :             continue;
     399             :         }
     400      115622 :         unsigned MOSubReg = MO.getSubReg();
     401      115622 :         MODefinedLanes = MRI->getMaxLaneMaskForVReg(MOReg);
     402      231244 :         MODefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(
     403             :             MOSubReg, MODefinedLanes);
     404             :       }
     405             : 
     406      164167 :       unsigned OpNum = DefMI.getOperandNo(&MO);
     407      328334 :       DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes);
     408             :     }
     409      133491 :     return DefinedLanes;
     410             :   }
     411      419765 :   if (DefMI.isImplicitDef() || Def.isDead())
     412             :     return LaneBitmask::getNone();
     413             : 
     414             :   assert(Def.getSubReg() == 0 &&
     415             :          "Should not have subregister defs in machine SSA phase");
     416      207023 :   return MRI->getMaxLaneMaskForVReg(Reg);
     417             : }
     418             : 
     419      640858 : LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) {
     420      640858 :   LaneBitmask UsedLanes = LaneBitmask::getNone();
     421     2121594 :   for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
     422         147 :     if (!MO.readsReg())
     423             :       continue;
     424             : 
     425      412903 :     const MachineInstr &UseMI = *MO.getParent();
     426      412903 :     if (UseMI.isKill())
     427             :       continue;
     428             : 
     429      412902 :     unsigned SubReg = MO.getSubReg();
     430      198049 :     if (lowersToCopies(UseMI)) {
     431             :       assert(UseMI.getDesc().getNumDefs() == 1);
     432      198049 :       const MachineOperand &Def = *UseMI.defs().begin();
     433      198049 :       unsigned DefReg = Def.getReg();
     434             :       // The used lanes of COPY-like instruction operands are determined by the
     435             :       // following dataflow analysis.
     436      198049 :       if (TargetRegisterInfo::isVirtualRegister(DefReg)) {
     437             :         // But ignore copies across incompatible register classes.
     438      193904 :         bool CrossCopy = false;
     439      193904 :         if (lowersToCopies(UseMI)) {
     440      387808 :           const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
     441      193904 :           CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
     442             :           if (CrossCopy)
     443             :             DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
     444             :         }
     445             : 
     446      193904 :         if (!CrossCopy)
     447             :           continue;
     448             :       }
     449             :     }
     450             : 
     451             :     // Shortcut: All lanes are used.
     452      243548 :     if (SubReg == 0)
     453      214030 :       return MRI->getMaxLaneMaskForVReg(Reg);
     454             : 
     455       59036 :     UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
     456             :   }
     457      426828 :   return UsedLanes;
     458             : }
     459             : 
     460             : bool DetectDeadLanes::isUndefRegAtInput(const MachineOperand &MO,
     461             :                                         const VRegInfo &RegInfo) const {
     462      503190 :   unsigned SubReg = MO.getSubReg();
     463     1006380 :   LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
     464     1509570 :   return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none();
     465             : }
     466             : 
     467      494008 : bool DetectDeadLanes::isUndefInput(const MachineOperand &MO,
     468             :                                    bool *CrossCopy) const {
     469      494008 :   if (!MO.isUse())
     470             :     return false;
     471      494008 :   const MachineInstr &MI = *MO.getParent();
     472      192702 :   if (!lowersToCopies(MI))
     473             :     return false;
     474      192702 :   const MachineOperand &Def = MI.getOperand(0);
     475      192702 :   unsigned DefReg = Def.getReg();
     476      192702 :   if (!TargetRegisterInfo::isVirtualRegister(DefReg))
     477             :     return false;
     478      188560 :   unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg);
     479      377120 :   if (!DefinedByCopy.test(DefRegIdx))
     480             :     return false;
     481             : 
     482      188560 :   const VRegInfo &DefRegInfo = VRegInfos[DefRegIdx];
     483      188560 :   LaneBitmask UsedLanes = transferUsedLanes(MI, DefRegInfo.UsedLanes, MO);
     484      188560 :   if (UsedLanes.any())
     485             :     return false;
     486             : 
     487          93 :   unsigned MOReg = MO.getReg();
     488          93 :   if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
     489         186 :     const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
     490          93 :     *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO);
     491             :   }
     492             :   return true;
     493             : }
     494             : 
     495       17592 : bool DetectDeadLanes::runOnce(MachineFunction &MF) {
     496             :   // First pass: Populate defs/uses of vregs with initial values
     497       35184 :   unsigned NumVirtRegs = MRI->getNumVirtRegs();
     498      658450 :   for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
     499      640858 :     unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
     500             : 
     501             :     // Determine used/defined lanes and add copy instructions to worklist.
     502      640858 :     VRegInfo &Info = VRegInfos[RegIdx];
     503      640858 :     Info.DefinedLanes = determineInitialDefinedLanes(Reg);
     504      640858 :     Info.UsedLanes = determineInitialUsedLanes(Reg);
     505             :   }
     506             : 
     507             :   // Iterate as long as defined lanes/used lanes keep changing.
     508      375910 :   while (!Worklist.empty()) {
     509      340726 :     unsigned RegIdx = Worklist.front();
     510      170363 :     Worklist.pop_front();
     511      340726 :     WorklistMembers.reset(RegIdx);
     512      170363 :     VRegInfo &Info = VRegInfos[RegIdx];
     513      170363 :     unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
     514             : 
     515             :     // Transfer UsedLanes to operands of DefMI (backwards dataflow).
     516      340726 :     MachineOperand &Def = *MRI->def_begin(Reg);
     517      170363 :     const MachineInstr &MI = *Def.getParent();
     518      170363 :     transferUsedLanesStep(MI, Info.UsedLanes);
     519             :     // Transfer DefinedLanes to users of Reg (forward dataflow).
     520      736210 :     for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg))
     521      225121 :       transferDefinedLanesStep(MO, Info.DefinedLanes);
     522             :   }
     523             : 
     524             :   DEBUG(
     525             :     dbgs() << "Defined/Used lanes:\n";
     526             :     for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
     527             :       unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
     528             :       const VRegInfo &Info = VRegInfos[RegIdx];
     529             :       dbgs() << PrintReg(Reg, nullptr)
     530             :              << " Used: " << PrintLaneMask(Info.UsedLanes)
     531             :              << " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
     532             :     }
     533             :     dbgs() << "\n";
     534             :   );
     535             : 
     536       17592 :   bool Again = false;
     537             :   // Mark operands as dead/unused.
     538       73573 :   for (MachineBasicBlock &MBB : MF) {
     539      906434 :     for (MachineInstr &MI : MBB) {
     540     2727875 :       for (MachineOperand &MO : MI.operands()) {
     541     2316252 :         if (!MO.isReg())
     542     1156361 :           continue;
     543     1159891 :         unsigned Reg = MO.getReg();
     544     1159891 :         if (!TargetRegisterInfo::isVirtualRegister(Reg))
     545      310649 :           continue;
     546      849242 :         unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg);
     547      849242 :         const VRegInfo &RegInfo = VRegInfos[RegIdx];
     548     1540650 :         if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) {
     549             :           DEBUG(dbgs() << "Marking operand '" << MO << "' as dead in " << MI);
     550             :           MO.setIsDead();
     551             :         }
     552             :         if (MO.readsReg()) {
     553      503190 :           bool CrossCopy = false;
     554     1006380 :           if (isUndefRegAtInput(MO, RegInfo)) {
     555             :             DEBUG(dbgs() << "Marking operand '" << MO << "' as undef in "
     556             :                   << MI);
     557             :             MO.setIsUndef();
     558      494008 :           } else if (isUndefInput(MO, &CrossCopy)) {
     559             :             DEBUG(dbgs() << "Marking operand '" << MO << "' as undef in "
     560             :                   << MI);
     561          93 :             MO.setIsUndef();
     562          93 :             if (CrossCopy)
     563          10 :               Again = true;
     564             :           }
     565             :         }
     566             :       }
     567             :     }
     568             :   }
     569             : 
     570       17592 :   return Again;
     571             : }
     572             : 
     573      134824 : bool DetectDeadLanes::runOnMachineFunction(MachineFunction &MF) {
     574             :   // Don't bother if we won't track subregister liveness later.  This pass is
     575             :   // required for correctness if subregister liveness is enabled because the
     576             :   // register coalescer cannot deal with hidden dead defs. However without
     577             :   // subregister liveness enabled, the expected benefits of this pass are small
     578             :   // so we safe the compile time.
     579      134824 :   MRI = &MF.getRegInfo();
     580      134824 :   if (!MRI->subRegLivenessEnabled()) {
     581             :     DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");
     582             :     return false;
     583             :   }
     584             : 
     585       35166 :   TRI = MRI->getTargetRegisterInfo();
     586             : 
     587       35166 :   unsigned NumVirtRegs = MRI->getNumVirtRegs();
     588      657806 :   VRegInfos = new VRegInfo[NumVirtRegs];
     589       17583 :   WorklistMembers.resize(NumVirtRegs);
     590       17583 :   DefinedByCopy.resize(NumVirtRegs);
     591             : 
     592             :   bool Again;
     593       17592 :   do {
     594       17592 :     Again = runOnce(MF);
     595             :   } while(Again);
     596             : 
     597       17583 :   DefinedByCopy.clear();
     598       17583 :   WorklistMembers.clear();
     599       17583 :   delete[] VRegInfos;
     600             :   return true;
     601             : }

Generated by: LCOV version 1.13