LCOV - code coverage report
Current view: top level - lib/CodeGen - EarlyIfConversion.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 279 280 99.6 %
Date: 2017-09-14 15:23:50 Functions: 22 23 95.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- EarlyIfConversion.cpp - If-conversion on SSA form machine code ----===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // Early if-conversion is for out-of-order CPUs that don't have a lot of
      11             : // predicable instructions. The goal is to eliminate conditional branches that
      12             : // may mispredict.
      13             : //
      14             : // Instructions from both sides of the branch are executed specutatively, and a
      15             : // cmov instruction selects the result.
      16             : //
      17             : //===----------------------------------------------------------------------===//
      18             : 
      19             : #include "llvm/ADT/BitVector.h"
      20             : #include "llvm/ADT/PostOrderIterator.h"
      21             : #include "llvm/ADT/SetVector.h"
      22             : #include "llvm/ADT/SmallPtrSet.h"
      23             : #include "llvm/ADT/SparseSet.h"
      24             : #include "llvm/ADT/Statistic.h"
      25             : #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
      26             : #include "llvm/CodeGen/MachineDominators.h"
      27             : #include "llvm/CodeGen/MachineFunction.h"
      28             : #include "llvm/CodeGen/MachineFunctionPass.h"
      29             : #include "llvm/CodeGen/MachineLoopInfo.h"
      30             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      31             : #include "llvm/CodeGen/MachineTraceMetrics.h"
      32             : #include "llvm/CodeGen/Passes.h"
      33             : #include "llvm/Support/CommandLine.h"
      34             : #include "llvm/Support/Debug.h"
      35             : #include "llvm/Support/raw_ostream.h"
      36             : #include "llvm/Target/TargetInstrInfo.h"
      37             : #include "llvm/Target/TargetRegisterInfo.h"
      38             : #include "llvm/Target/TargetSubtargetInfo.h"
      39             : 
      40             : using namespace llvm;
      41             : 
      42             : #define DEBUG_TYPE "early-ifcvt"
      43             : 
      44             : // Absolute maximum number of instructions allowed per speculated block.
      45             : // This bypasses all other heuristics, so it should be set fairly high.
      46             : static cl::opt<unsigned>
      47      289224 : BlockInstrLimit("early-ifcvt-limit", cl::init(30), cl::Hidden,
      48      289224 :   cl::desc("Maximum number of instructions per speculated block."));
      49             : 
      50             : // Stress testing mode - disable heuristics.
      51       72306 : static cl::opt<bool> Stress("stress-early-ifcvt", cl::Hidden,
      52      144612 :   cl::desc("Turn all knobs to 11"));
      53             : 
      54             : STATISTIC(NumDiamondsSeen,  "Number of diamonds");
      55             : STATISTIC(NumDiamondsConv,  "Number of diamonds converted");
      56             : STATISTIC(NumTrianglesSeen, "Number of triangles");
      57             : STATISTIC(NumTrianglesConv, "Number of triangles converted");
      58             : 
      59             : //===----------------------------------------------------------------------===//
      60             : //                                 SSAIfConv
      61             : //===----------------------------------------------------------------------===//
      62             : //
      63             : // The SSAIfConv class performs if-conversion on SSA form machine code after
      64             : // determining if it is possible. The class contains no heuristics; external
      65             : // code should be used to determine when if-conversion is a good idea.
      66             : //
      67             : // SSAIfConv can convert both triangles and diamonds:
      68             : //
      69             : //   Triangle: Head              Diamond: Head
      70             : //              | \                       /  \_
      71             : //              |  \                     /    |
      72             : //              |  [TF]BB              FBB    TBB
      73             : //              |  /                     \    /
      74             : //              | /                       \  /
      75             : //             Tail                       Tail
      76             : //
      77             : // Instructions in the conditional blocks TBB and/or FBB are spliced into the
      78             : // Head block, and phis in the Tail block are converted to select instructions.
      79             : //
      80             : namespace {
      81      108838 : class SSAIfConv {
      82             :   const TargetInstrInfo *TII;
      83             :   const TargetRegisterInfo *TRI;
      84             :   MachineRegisterInfo *MRI;
      85             : 
      86             : public:
      87             :   /// The block containing the conditional branch.
      88             :   MachineBasicBlock *Head;
      89             : 
      90             :   /// The block containing phis after the if-then-else.
      91             :   MachineBasicBlock *Tail;
      92             : 
      93             :   /// The 'true' conditional block as determined by AnalyzeBranch.
      94             :   MachineBasicBlock *TBB;
      95             : 
      96             :   /// The 'false' conditional block as determined by AnalyzeBranch.
      97             :   MachineBasicBlock *FBB;
      98             : 
      99             :   /// isTriangle - When there is no 'else' block, either TBB or FBB will be
     100             :   /// equal to Tail.
     101         153 :   bool isTriangle() const { return TBB == Tail || FBB == Tail; }
     102             : 
     103             :   /// Returns the Tail predecessor for the True side.
     104        1199 :   MachineBasicBlock *getTPred() const { return TBB == Tail ? Head : TBB; }
     105             : 
     106             :   /// Returns the Tail predecessor for the  False side.
     107        1188 :   MachineBasicBlock *getFPred() const { return FBB == Tail ? Head : FBB; }
     108             : 
     109             :   /// Information about each phi in the Tail block.
     110             :   struct PHIInfo {
     111             :     MachineInstr *PHI;
     112             :     unsigned TReg, FReg;
     113             :     // Latencies from Cond+Branch, TReg, and FReg to DstReg.
     114             :     int CondCycles, TCycles, FCycles;
     115             : 
     116             :     PHIInfo(MachineInstr *phi)
     117        1129 :       : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
     118             :   };
     119             : 
     120             :   SmallVector<PHIInfo, 8> PHIs;
     121             : 
     122             : private:
     123             :   /// The branch condition determined by AnalyzeBranch.
     124             :   SmallVector<MachineOperand, 4> Cond;
     125             : 
     126             :   /// Instructions in Head that define values used by the conditional blocks.
     127             :   /// The hoisted instructions must be inserted after these instructions.
     128             :   SmallPtrSet<MachineInstr*, 8> InsertAfter;
     129             : 
     130             :   /// Register units clobbered by the conditional blocks.
     131             :   BitVector ClobberedRegUnits;
     132             : 
     133             :   // Scratch pad for findInsertionPoint.
     134             :   SparseSet<unsigned> LiveRegUnits;
     135             : 
     136             :   /// Insertion point in Head for speculatively executed instructions form TBB
     137             :   /// and FBB.
     138             :   MachineBasicBlock::iterator InsertionPoint;
     139             : 
     140             :   /// Return true if all non-terminator instructions in MBB can be safely
     141             :   /// speculated.
     142             :   bool canSpeculateInstrs(MachineBasicBlock *MBB);
     143             : 
     144             :   /// Find a valid insertion point in Head.
     145             :   bool findInsertionPoint();
     146             : 
     147             :   /// Replace PHI instructions in Tail with selects.
     148             :   void replacePHIInstrs();
     149             : 
     150             :   /// Insert selects and rewrite PHI operands to use them.
     151             :   void rewritePHIOperands();
     152             : 
     153             : public:
     154             :   /// runOnMachineFunction - Initialize per-function data structures.
     155       24350 :   void runOnMachineFunction(MachineFunction &MF) {
     156       24350 :     TII = MF.getSubtarget().getInstrInfo();
     157       24350 :     TRI = MF.getSubtarget().getRegisterInfo();
     158       24350 :     MRI = &MF.getRegInfo();
     159       48700 :     LiveRegUnits.clear();
     160       24350 :     LiveRegUnits.setUniverse(TRI->getNumRegUnits());
     161       24350 :     ClobberedRegUnits.clear();
     162       24350 :     ClobberedRegUnits.resize(TRI->getNumRegUnits());
     163       24350 :   }
     164             : 
     165             :   /// canConvertIf - If the sub-CFG headed by MBB can be if-converted,
     166             :   /// initialize the internal state, and return true.
     167             :   bool canConvertIf(MachineBasicBlock *MBB);
     168             : 
     169             :   /// convertIf - If-convert the last block passed to canConvertIf(), assuming
     170             :   /// it is possible. Add any erased blocks to RemovedBlocks.
     171             :   void convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks);
     172             : };
     173             : } // end anonymous namespace
     174             : 
     175             : 
     176             : /// canSpeculateInstrs - Returns true if all the instructions in MBB can safely
     177             : /// be speculated. The terminators are not considered.
     178             : ///
     179             : /// If instructions use any values that are defined in the head basic block,
     180             : /// the defining instructions are added to InsertAfter.
     181             : ///
     182             : /// Any clobbered regunits are added to ClobberedRegUnits.
     183             : ///
     184         238 : bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
     185             :   // Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to
     186             :   // get right.
     187         238 :   if (!MBB->livein_empty()) {
     188             :     DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n");
     189             :     return false;
     190             :   }
     191             : 
     192         238 :   unsigned InstrCount = 0;
     193             : 
     194             :   // Check all instructions, except the terminators. It is assumed that
     195             :   // terminators never have side effects or define any used register values.
     196         238 :   for (MachineBasicBlock::iterator I = MBB->begin(),
     197         839 :        E = MBB->getFirstTerminator(); I != E; ++I) {
     198         936 :     if (I->isDebugValue())
     199           0 :       continue;
     200             : 
     201         936 :     if (++InstrCount > BlockInstrLimit && !Stress) {
     202             :       DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has more than "
     203             :                    << BlockInstrLimit << " instructions.\n");
     204         105 :       return false;
     205             :     }
     206             : 
     207             :     // There shouldn't normally be any phis in a single-predecessor block.
     208         936 :     if (I->isPHI()) {
     209             :       DEBUG(dbgs() << "Can't hoist: " << *I);
     210             :       return false;
     211             :     }
     212             : 
     213             :     // Don't speculate loads. Note that it may be possible and desirable to
     214             :     // speculate GOT or constant pool loads that are guaranteed not to trap,
     215             :     // but we don't support that for now.
     216         468 :     if (I->mayLoad()) {
     217             :       DEBUG(dbgs() << "Won't speculate load: " << *I);
     218             :       return false;
     219             :     }
     220             : 
     221             :     // We never speculate stores, so an AA pointer isn't necessary.
     222         402 :     bool DontMoveAcrossStore = true;
     223         402 :     if (!I->isSafeToMove(nullptr, DontMoveAcrossStore)) {
     224             :       DEBUG(dbgs() << "Can't speculate: " << *I);
     225             :       return false;
     226             :     }
     227             : 
     228             :     // Check for any dependencies on Head instructions.
     229        1962 :     for (const MachineOperand &MO : I->operands()) {
     230        1236 :       if (MO.isRegMask()) {
     231             :         DEBUG(dbgs() << "Won't speculate regmask: " << *I);
     232             :         return false;
     233             :       }
     234        1236 :       if (!MO.isReg())
     235         353 :         continue;
     236         883 :       unsigned Reg = MO.getReg();
     237             : 
     238             :       // Remember clobbered regunits.
     239        1283 :       if (MO.isDef() && TargetRegisterInfo::isPhysicalRegister(Reg))
     240         306 :         for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
     241         336 :           ClobberedRegUnits.set(*Units);
     242             : 
     243         967 :       if (!MO.readsReg() || !TargetRegisterInfo::isVirtualRegister(Reg))
     244         484 :         continue;
     245         399 :       MachineInstr *DefMI = MRI->getVRegDef(Reg);
     246        1026 :       if (!DefMI || DefMI->getParent() != Head)
     247         228 :         continue;
     248         171 :       if (InsertAfter.insert(DefMI).second)
     249             :         DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI);
     250         171 :       if (DefMI->isTerminator()) {
     251             :         DEBUG(dbgs() << "Can't insert instructions below terminator.\n");
     252             :         return false;
     253             :       }
     254             :     }
     255             :   }
     256         133 :   return true;
     257             : }
     258             : 
     259             : 
     260             : /// Find an insertion point in Head for the speculated instructions. The
     261             : /// insertion point must be:
     262             : ///
     263             : /// 1. Before any terminators.
     264             : /// 2. After any instructions in InsertAfter.
     265             : /// 3. Not have any clobbered regunits live.
     266             : ///
     267             : /// This function sets InsertionPoint and returns true when successful, it
     268             : /// returns false if no valid insertion point could be found.
     269             : ///
     270          81 : bool SSAIfConv::findInsertionPoint() {
     271             :   // Keep track of live regunits before the current position.
     272             :   // Only track RegUnits that are also in ClobberedRegUnits.
     273         162 :   LiveRegUnits.clear();
     274         162 :   SmallVector<unsigned, 8> Reads;
     275          81 :   MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
     276         162 :   MachineBasicBlock::iterator I = Head->end();
     277         162 :   MachineBasicBlock::iterator B = Head->begin();
     278         170 :   while (I != B) {
     279         170 :     --I;
     280             :     // Some of the conditional code depends in I.
     281         340 :     if (InsertAfter.count(&*I)) {
     282             :       DEBUG(dbgs() << "Can't insert code after " << *I);
     283             :       return false;
     284             :     }
     285             : 
     286             :     // Update live regunits.
     287         697 :     for (const MachineOperand &MO : I->operands()) {
     288             :       // We're ignoring regmask operands. That is conservatively correct.
     289         357 :       if (!MO.isReg())
     290         513 :         continue;
     291         126 :       unsigned Reg = MO.getReg();
     292         252 :       if (!TargetRegisterInfo::isPhysicalRegister(Reg))
     293          51 :         continue;
     294             :       // I clobbers Reg, so it isn't live before I.
     295          75 :       if (MO.isDef())
     296          45 :         for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
     297          34 :           LiveRegUnits.erase(*Units);
     298             :       // Unless I reads Reg.
     299             :       if (MO.readsReg())
     300          60 :         Reads.push_back(Reg);
     301             :     }
     302             :     // Anything read by I is live before I.
     303         290 :     while (!Reads.empty())
     304         251 :       for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
     305             :            ++Units)
     306         213 :         if (ClobberedRegUnits.test(*Units))
     307          17 :           LiveRegUnits.insert(*Units);
     308             : 
     309             :     // We can't insert before a terminator.
     310         423 :     if (I != FirstTerm && I->isTerminator())
     311          75 :       continue;
     312             : 
     313             :     // Some of the clobbered registers are live before I, not a valid insertion
     314             :     // point.
     315         204 :     if (!LiveRegUnits.empty()) {
     316             :       DEBUG({
     317             :         dbgs() << "Would clobber";
     318             :         for (SparseSet<unsigned>::const_iterator
     319             :              i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i)
     320             :           dbgs() << ' ' << PrintRegUnit(*i, TRI);
     321             :         dbgs() << " live before " << *I;
     322             :       });
     323          14 :       continue;
     324             :     }
     325             : 
     326             :     // This is a valid insertion point.
     327          81 :     InsertionPoint = I;
     328             :     DEBUG(dbgs() << "Can insert before " << *I);
     329          81 :     return true;
     330             :   }
     331             :   DEBUG(dbgs() << "No legal insertion point found.\n");
     332             :   return false;
     333             : }
     334             : 
     335             : 
     336             : 
     337             : /// canConvertIf - analyze the sub-cfg rooted in MBB, and return true if it is
     338             : /// a potential candidate for if-conversion. Fill out the internal state.
     339             : ///
     340       34345 : bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) {
     341       34345 :   Head = MBB;
     342       34345 :   TBB = FBB = Tail = nullptr;
     343             : 
     344       68690 :   if (Head->succ_size() != 2)
     345             :     return false;
     346       10046 :   MachineBasicBlock *Succ0 = Head->succ_begin()[0];
     347       10046 :   MachineBasicBlock *Succ1 = Head->succ_begin()[1];
     348             : 
     349             :   // Canonicalize so Succ0 has MBB as its single predecessor.
     350       10046 :   if (Succ0->pred_size() != 1)
     351             :     std::swap(Succ0, Succ1);
     352             : 
     353       14496 :   if (Succ0->pred_size() != 1 || Succ0->succ_size() != 1)
     354             :     return false;
     355             : 
     356        3998 :   Tail = Succ0->succ_begin()[0];
     357             : 
     358             :   // This is not a triangle.
     359        1999 :   if (Tail != Succ1) {
     360             :     // Check for a diamond. We won't deal with any critical edges.
     361        1242 :     if (Succ1->pred_size() != 1 || Succ1->succ_size() != 1 ||
     362         240 :         Succ1->succ_begin()[0] != Tail)
     363             :       return false;
     364             :     DEBUG(dbgs() << "\nDiamond: BB#" << Head->getNumber()
     365             :                  << " -> BB#" << Succ0->getNumber()
     366             :                  << "/BB#" << Succ1->getNumber()
     367             :                  << " -> BB#" << Tail->getNumber() << '\n');
     368             : 
     369             :     // Live-in physregs are tricky to get right when speculating code.
     370         182 :     if (!Tail->livein_empty()) {
     371             :       DEBUG(dbgs() << "Tail has live-ins.\n");
     372             :       return false;
     373             :     }
     374             :   } else {
     375             :     DEBUG(dbgs() << "\nTriangle: BB#" << Head->getNumber()
     376             :                  << " -> BB#" << Succ0->getNumber()
     377             :                  << " -> BB#" << Tail->getNumber() << '\n');
     378             :   }
     379             : 
     380             :   // This is a triangle or a diamond.
     381             :   // If Tail doesn't have any phis, there must be side effects.
     382        4894 :   if (Tail->empty() || !Tail->front().isPHI()) {
     383             :     DEBUG(dbgs() << "No phis in tail.\n");
     384             :     return false;
     385             :   }
     386             : 
     387             :   // The branch we're looking to eliminate must be analyzable.
     388        2234 :   Cond.clear();
     389        1117 :   if (TII->analyzeBranch(*Head, TBB, FBB, Cond)) {
     390             :     DEBUG(dbgs() << "Branch not analyzable.\n");
     391             :     return false;
     392             :   }
     393             : 
     394             :   // This is weird, probably some sort of degenerate CFG.
     395        1112 :   if (!TBB) {
     396             :     DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch.\n");
     397             :     return false;
     398             :   }
     399             : 
     400             :   // AnalyzeBranch doesn't set FBB on a fall-through branch.
     401             :   // Make sure it is always set.
     402        1112 :   FBB = TBB == Succ0 ? Succ1 : Succ0;
     403             : 
     404             :   // Any phis in the tail block must be convertible to selects.
     405        2224 :   PHIs.clear();
     406        1112 :   MachineBasicBlock *TPred = getTPred();
     407        1112 :   MachineBasicBlock *FPred = getFPred();
     408        3336 :   for (MachineBasicBlock::iterator I = Tail->begin(), E = Tail->end();
     409        2629 :        I != E && I->isPHI(); ++I) {
     410        3387 :     PHIs.push_back(&*I);
     411        2258 :     PHIInfo &PI = PHIs.back();
     412             :     // Find PHI operands corresponding to TPred and FPred.
     413        3463 :     for (unsigned i = 1; i != PI.PHI->getNumOperands(); i += 2) {
     414        4668 :       if (PI.PHI->getOperand(i+1).getMBB() == TPred)
     415        2258 :         PI.TReg = PI.PHI->getOperand(i).getReg();
     416        2334 :       if (PI.PHI->getOperand(i+1).getMBB() == FPred)
     417        2258 :         PI.FReg = PI.PHI->getOperand(i).getReg();
     418             :     }
     419             :     assert(TargetRegisterInfo::isVirtualRegister(PI.TReg) && "Bad PHI");
     420             :     assert(TargetRegisterInfo::isVirtualRegister(PI.FReg) && "Bad PHI");
     421             : 
     422             :     // Get target information.
     423        3387 :     if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,
     424        1129 :                               PI.CondCycles, PI.TCycles, PI.FCycles)) {
     425             :       DEBUG(dbgs() << "Can't convert: " << *PI.PHI);
     426         926 :       return false;
     427             :     }
     428             :   }
     429             : 
     430             :   // Check that the conditional instructions can be speculated.
     431         186 :   InsertAfter.clear();
     432         372 :   ClobberedRegUnits.reset();
     433         186 :   if (TBB != Tail && !canSpeculateInstrs(TBB))
     434             :     return false;
     435         166 :   if (FBB != Tail && !canSpeculateInstrs(FBB))
     436             :     return false;
     437             : 
     438             :   // Try to find a valid insertion point for the speculated instructions in the
     439             :   // head basic block.
     440          81 :   if (!findInsertionPoint())
     441             :     return false;
     442             : 
     443             :   if (isTriangle())
     444             :     ++NumTrianglesSeen;
     445             :   else
     446             :     ++NumDiamondsSeen;
     447             :   return true;
     448             : }
     449             : 
     450             : /// replacePHIInstrs - Completely replace PHI instructions with selects.
     451             : /// This is possible when the only Tail predecessors are the if-converted
     452             : /// blocks.
     453          66 : void SSAIfConv::replacePHIInstrs() {
     454             :   assert(Tail->pred_size() == 2 && "Cannot replace PHIs");
     455          66 :   MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
     456             :   assert(FirstTerm != Head->end() && "No terminators");
     457         198 :   DebugLoc HeadDL = FirstTerm->getDebugLoc();
     458             : 
     459             :   // Convert all PHIs to select instructions inserted before FirstTerm.
     460         201 :   for (unsigned i = 0, e = PHIs.size(); i != e; ++i) {
     461         138 :     PHIInfo &PI = PHIs[i];
     462             :     DEBUG(dbgs() << "If-converting " << *PI.PHI);
     463          69 :     unsigned DstReg = PI.PHI->getOperand(0).getReg();
     464         138 :     TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
     465             :     DEBUG(dbgs() << "          --> " << *std::prev(FirstTerm));
     466          69 :     PI.PHI->eraseFromParent();
     467          69 :     PI.PHI = nullptr;
     468             :   }
     469          66 : }
     470             : 
     471             : /// rewritePHIOperands - When there are additional Tail predecessors, insert
     472             : /// select instructions in Head and rewrite PHI operands to use the selects.
     473             : /// Keep the PHI instructions in Tail to handle the other predecessors.
     474           6 : void SSAIfConv::rewritePHIOperands() {
     475           6 :   MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
     476             :   assert(FirstTerm != Head->end() && "No terminators");
     477          18 :   DebugLoc HeadDL = FirstTerm->getDebugLoc();
     478             : 
     479             :   // Convert all PHIs to select instructions inserted before FirstTerm.
     480          23 :   for (unsigned i = 0, e = PHIs.size(); i != e; ++i) {
     481          22 :     PHIInfo &PI = PHIs[i];
     482          11 :     unsigned DstReg = 0;
     483             : 
     484             :     DEBUG(dbgs() << "If-converting " << *PI.PHI);
     485          11 :     if (PI.TReg == PI.FReg) {
     486             :       // We do not need the select instruction if both incoming values are
     487             :       // equal.
     488             :       DstReg = PI.TReg;
     489             :     } else {
     490           7 :       unsigned PHIDst = PI.PHI->getOperand(0).getReg();
     491          14 :       DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
     492          21 :       TII->insertSelect(*Head, FirstTerm, HeadDL,
     493           7 :                          DstReg, Cond, PI.TReg, PI.FReg);
     494             :       DEBUG(dbgs() << "          --> " << *std::prev(FirstTerm));
     495             :     }
     496             : 
     497             :     // Rewrite PHI operands TPred -> (DstReg, Head), remove FPred.
     498          47 :     for (unsigned i = PI.PHI->getNumOperands(); i != 1; i -= 2) {
     499          72 :       MachineBasicBlock *MBB = PI.PHI->getOperand(i-1).getMBB();
     500          36 :       if (MBB == getTPred()) {
     501          22 :         PI.PHI->getOperand(i-1).setMBB(Head);
     502          22 :         PI.PHI->getOperand(i-2).setReg(DstReg);
     503          25 :       } else if (MBB == getFPred()) {
     504          11 :         PI.PHI->RemoveOperand(i-1);
     505          11 :         PI.PHI->RemoveOperand(i-2);
     506             :       }
     507             :     }
     508             :     DEBUG(dbgs() << "          --> " << *PI.PHI);
     509             :   }
     510           6 : }
     511             : 
     512             : /// convertIf - Execute the if conversion after canConvertIf has determined the
     513             : /// feasibility.
     514             : ///
     515             : /// Any basic blocks erased will be added to RemovedBlocks.
     516             : ///
     517          72 : void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks) {
     518             :   assert(Head && Tail && TBB && FBB && "Call canConvertIf first.");
     519             : 
     520             :   // Update statistics.
     521          72 :   if (isTriangle())
     522             :     ++NumTrianglesConv;
     523             :   else
     524             :     ++NumDiamondsConv;
     525             : 
     526             :   // Move all instructions into Head, except for the terminators.
     527          72 :   if (TBB != Tail)
     528          16 :     Head->splice(InsertionPoint, TBB, TBB->begin(), TBB->getFirstTerminator());
     529          72 :   if (FBB != Tail)
     530         142 :     Head->splice(InsertionPoint, FBB, FBB->begin(), FBB->getFirstTerminator());
     531             : 
     532             :   // Are there extra Tail predecessors?
     533         144 :   bool ExtraPreds = Tail->pred_size() != 2;
     534          72 :   if (ExtraPreds)
     535           6 :     rewritePHIOperands();
     536             :   else
     537          66 :     replacePHIInstrs();
     538             : 
     539             :   // Fix up the CFG, temporarily leave Head without any successors.
     540          72 :   Head->removeSuccessor(TBB);
     541          72 :   Head->removeSuccessor(FBB, true);
     542          72 :   if (TBB != Tail)
     543           8 :     TBB->removeSuccessor(Tail, true);
     544          72 :   if (FBB != Tail)
     545          71 :     FBB->removeSuccessor(Tail, true);
     546             : 
     547             :   // Fix up Head's terminators.
     548             :   // It should become a single branch or a fallthrough.
     549         288 :   DebugLoc HeadDL = Head->getFirstTerminator()->getDebugLoc();
     550          72 :   TII->removeBranch(*Head);
     551             : 
     552             :   // Erase the now empty conditional blocks. It is likely that Head can fall
     553             :   // through to Tail, and we can join the two blocks.
     554          72 :   if (TBB != Tail) {
     555           8 :     RemovedBlocks.push_back(TBB);
     556           8 :     TBB->eraseFromParent();
     557             :   }
     558          72 :   if (FBB != Tail) {
     559          71 :     RemovedBlocks.push_back(FBB);
     560          71 :     FBB->eraseFromParent();
     561             :   }
     562             : 
     563             :   assert(Head->succ_empty() && "Additional head successors?");
     564          72 :   if (!ExtraPreds && Head->isLayoutSuccessor(Tail)) {
     565             :     // Splice Tail onto the end of Head.
     566             :     DEBUG(dbgs() << "Joining tail BB#" << Tail->getNumber()
     567             :                  << " into head BB#" << Head->getNumber() << '\n');
     568         330 :     Head->splice(Head->end(), Tail,
     569         132 :                      Tail->begin(), Tail->end());
     570          66 :     Head->transferSuccessorsAndUpdatePHIs(Tail);
     571          66 :     RemovedBlocks.push_back(Tail);
     572          66 :     Tail->eraseFromParent();
     573             :   } else {
     574             :     // We need a branch to Tail, let code placement work it out later.
     575             :     DEBUG(dbgs() << "Converting to unconditional branch.\n");
     576          12 :     SmallVector<MachineOperand, 0> EmptyCond;
     577          12 :     TII->insertBranch(*Head, Tail, nullptr, EmptyCond, HeadDL);
     578          12 :     Head->addSuccessor(Tail);
     579             :   }
     580             :   DEBUG(dbgs() << *Head);
     581          72 : }
     582             : 
     583             : 
     584             : //===----------------------------------------------------------------------===//
     585             : //                           EarlyIfConverter Pass
     586             : //===----------------------------------------------------------------------===//
     587             : 
     588             : namespace {
     589        9043 : class EarlyIfConverter : public MachineFunctionPass {
     590             :   const TargetInstrInfo *TII;
     591             :   const TargetRegisterInfo *TRI;
     592             :   MCSchedModel SchedModel;
     593             :   MachineRegisterInfo *MRI;
     594             :   MachineDominatorTree *DomTree;
     595             :   MachineLoopInfo *Loops;
     596             :   MachineTraceMetrics *Traces;
     597             :   MachineTraceMetrics::Ensemble *MinInstr;
     598             :   SSAIfConv IfConv;
     599             : 
     600             : public:
     601             :   static char ID;
     602       18178 :   EarlyIfConverter() : MachineFunctionPass(ID) {}
     603             :   void getAnalysisUsage(AnalysisUsage &AU) const override;
     604             :   bool runOnMachineFunction(MachineFunction &MF) override;
     605        9085 :   StringRef getPassName() const override { return "Early If-Conversion"; }
     606             : 
     607             : private:
     608             :   bool tryConvertIf(MachineBasicBlock*);
     609             :   void updateDomTree(ArrayRef<MachineBasicBlock*> Removed);
     610             :   void updateLoops(ArrayRef<MachineBasicBlock*> Removed);
     611             :   void invalidateTraces();
     612             :   bool shouldConvertIf();
     613             : };
     614             : } // end anonymous namespace
     615             : 
     616             : char EarlyIfConverter::ID = 0;
     617             : char &llvm::EarlyIfConverterID = EarlyIfConverter::ID;
     618             : 
     619       20212 : INITIALIZE_PASS_BEGIN(EarlyIfConverter, DEBUG_TYPE,
     620             :                       "Early If Converter", false, false)
     621       20212 : INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
     622       20212 : INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
     623       20212 : INITIALIZE_PASS_DEPENDENCY(MachineTraceMetrics)
     624      151199 : INITIALIZE_PASS_END(EarlyIfConverter, DEBUG_TYPE,
     625             :                     "Early If Converter", false, false)
     626             : 
     627        9065 : void EarlyIfConverter::getAnalysisUsage(AnalysisUsage &AU) const {
     628        9065 :   AU.addRequired<MachineBranchProbabilityInfo>();
     629        9065 :   AU.addRequired<MachineDominatorTree>();
     630        9065 :   AU.addPreserved<MachineDominatorTree>();
     631        9065 :   AU.addRequired<MachineLoopInfo>();
     632        9065 :   AU.addPreserved<MachineLoopInfo>();
     633        9065 :   AU.addRequired<MachineTraceMetrics>();
     634        9065 :   AU.addPreserved<MachineTraceMetrics>();
     635        9065 :   MachineFunctionPass::getAnalysisUsage(AU);
     636        9065 : }
     637             : 
     638             : /// Update the dominator tree after if-conversion erased some blocks.
     639          72 : void EarlyIfConverter::updateDomTree(ArrayRef<MachineBasicBlock*> Removed) {
     640             :   // convertIf can remove TBB, FBB, and Tail can be merged into Head.
     641             :   // TBB and FBB should not dominate any blocks.
     642             :   // Tail children should be transferred to Head.
     643          72 :   MachineDomTreeNode *HeadNode = DomTree->getNode(IfConv.Head);
     644         217 :   for (unsigned i = 0, e = Removed.size(); i != e; ++i) {
     645         290 :     MachineDomTreeNode *Node = DomTree->getNode(Removed[i]);
     646             :     assert(Node != HeadNode && "Cannot erase the head node");
     647         150 :     while (Node->getNumChildren()) {
     648             :       assert(Node->getBlock() == IfConv.Tail && "Unexpected children");
     649          10 :       DomTree->changeImmediateDominator(Node->getChildren().back(), HeadNode);
     650             :     }
     651         290 :     DomTree->eraseNode(Removed[i]);
     652             :   }
     653          72 : }
     654             : 
     655             : /// Update LoopInfo after if-conversion.
     656          72 : void EarlyIfConverter::updateLoops(ArrayRef<MachineBasicBlock*> Removed) {
     657          72 :   if (!Loops)
     658             :     return;
     659             :   // If-conversion doesn't change loop structure, and it doesn't mess with back
     660             :   // edges, so updating LoopInfo is simply removing the dead blocks.
     661         217 :   for (unsigned i = 0, e = Removed.size(); i != e; ++i)
     662         435 :     Loops->removeBlock(Removed[i]);
     663             : }
     664             : 
     665             : /// Invalidate MachineTraceMetrics before if-conversion.
     666          72 : void EarlyIfConverter::invalidateTraces() {
     667          72 :   Traces->verifyAnalysis();
     668          72 :   Traces->invalidate(IfConv.Head);
     669          72 :   Traces->invalidate(IfConv.Tail);
     670          72 :   Traces->invalidate(IfConv.TBB);
     671          72 :   Traces->invalidate(IfConv.FBB);
     672          72 :   Traces->verifyAnalysis();
     673          72 : }
     674             : 
     675             : // Adjust cycles with downward saturation.
     676             : static unsigned adjCycles(unsigned Cyc, int Delta) {
     677         149 :   if (Delta < 0 && Cyc + Delta > Cyc)
     678             :     return 0;
     679         149 :   return Cyc + Delta;
     680             : }
     681             : 
     682             : /// Apply cost model and heuristics to the if-conversion in IfConv.
     683             : /// Return true if the conversion is a good idea.
     684             : ///
     685          81 : bool EarlyIfConverter::shouldConvertIf() {
     686             :   // Stress testing mode disables all cost considerations.
     687          81 :   if (Stress)
     688             :     return true;
     689             : 
     690          51 :   if (!MinInstr)
     691          51 :     MinInstr = Traces->getEnsemble(MachineTraceMetrics::TS_MinInstrCount);
     692             : 
     693         102 :   MachineTraceMetrics::Trace TBBTrace = MinInstr->getTrace(IfConv.getTPred());
     694         102 :   MachineTraceMetrics::Trace FBBTrace = MinInstr->getTrace(IfConv.getFPred());
     695             :   DEBUG(dbgs() << "TBB: " << TBBTrace << "FBB: " << FBBTrace);
     696         153 :   unsigned MinCrit = std::min(TBBTrace.getCriticalPath(),
     697         204 :                               FBBTrace.getCriticalPath());
     698             : 
     699             :   // Set a somewhat arbitrary limit on the critical path extension we accept.
     700          51 :   unsigned CritLimit = SchedModel.MispredictPenalty/2;
     701             : 
     702             :   // If-conversion only makes sense when there is unexploited ILP. Compute the
     703             :   // maximum-ILP resource length of the trace after if-conversion. Compare it
     704             :   // to the shortest critical path.
     705          51 :   SmallVector<const MachineBasicBlock*, 1> ExtraBlocks;
     706          51 :   if (IfConv.TBB != IfConv.Tail)
     707           8 :     ExtraBlocks.push_back(IfConv.TBB);
     708         153 :   unsigned ResLength = FBBTrace.getResourceLength(ExtraBlocks);
     709             :   DEBUG(dbgs() << "Resource length " << ResLength
     710             :                << ", minimal critical path " << MinCrit << '\n');
     711          51 :   if (ResLength > MinCrit + CritLimit) {
     712             :     DEBUG(dbgs() << "Not enough available ILP.\n");
     713             :     return false;
     714             :   }
     715             : 
     716             :   // Assume that the depth of the first head terminator will also be the depth
     717             :   // of the select instruction inserted, as determined by the flag dependency.
     718             :   // TBB / FBB data dependencies may delay the select even more.
     719          44 :   MachineTraceMetrics::Trace HeadTrace = MinInstr->getTrace(IfConv.Head);
     720             :   unsigned BranchDepth =
     721         132 :       HeadTrace.getInstrCycles(*IfConv.Head->getFirstTerminator()).Depth;
     722             :   DEBUG(dbgs() << "Branch depth: " << BranchDepth << '\n');
     723             : 
     724             :   // Look at all the tail phis, and compute the critical path extension caused
     725             :   // by inserting select instructions.
     726          44 :   MachineTraceMetrics::Trace TailTrace = MinInstr->getTrace(IfConv.Tail);
     727         136 :   for (unsigned i = 0, e = IfConv.PHIs.size(); i != e; ++i) {
     728         100 :     SSAIfConv::PHIInfo &PI = IfConv.PHIs[i];
     729          50 :     unsigned Slack = TailTrace.getInstrSlack(*PI.PHI);
     730         100 :     unsigned MaxDepth = Slack + TailTrace.getInstrCycles(*PI.PHI).Depth;
     731             :     DEBUG(dbgs() << "Slack " << Slack << ":\t" << *PI.PHI);
     732             : 
     733             :     // The condition is pulled into the critical path.
     734         100 :     unsigned CondDepth = adjCycles(BranchDepth, PI.CondCycles);
     735          50 :     if (CondDepth > MaxDepth) {
     736          41 :       unsigned Extra = CondDepth - MaxDepth;
     737             :       DEBUG(dbgs() << "Condition adds " << Extra << " cycles.\n");
     738          41 :       if (Extra > CritLimit) {
     739             :         DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
     740             :         return false;
     741             :       }
     742             :     }
     743             : 
     744             :     // The TBB value is pulled into the critical path.
     745         100 :     unsigned TDepth = adjCycles(TBBTrace.getPHIDepth(*PI.PHI), PI.TCycles);
     746          50 :     if (TDepth > MaxDepth) {
     747          47 :       unsigned Extra = TDepth - MaxDepth;
     748             :       DEBUG(dbgs() << "TBB data adds " << Extra << " cycles.\n");
     749          47 :       if (Extra > CritLimit) {
     750             :         DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
     751             :         return false;
     752             :       }
     753             :     }
     754             : 
     755             :     // The FBB value is pulled into the critical path.
     756          98 :     unsigned FDepth = adjCycles(FBBTrace.getPHIDepth(*PI.PHI), PI.FCycles);
     757          49 :     if (FDepth > MaxDepth) {
     758          41 :       unsigned Extra = FDepth - MaxDepth;
     759             :       DEBUG(dbgs() << "FBB data adds " << Extra << " cycles.\n");
     760          41 :       if (Extra > CritLimit) {
     761             :         DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
     762             :         return false;
     763             :       }
     764             :     }
     765             :   }
     766             :   return true;
     767             : }
     768             : 
     769             : /// Attempt repeated if-conversion on MBB, return true if successful.
     770             : ///
     771       34273 : bool EarlyIfConverter::tryConvertIf(MachineBasicBlock *MBB) {
     772       34273 :   bool Changed = false;
     773       34417 :   while (IfConv.canConvertIf(MBB) && shouldConvertIf()) {
     774             :     // If-convert MBB and update analyses.
     775          72 :     invalidateTraces();
     776         144 :     SmallVector<MachineBasicBlock*, 4> RemovedBlocks;
     777          72 :     IfConv.convertIf(RemovedBlocks);
     778          72 :     Changed = true;
     779          72 :     updateDomTree(RemovedBlocks);
     780          72 :     updateLoops(RemovedBlocks);
     781             :   }
     782       34273 :   return Changed;
     783             : }
     784             : 
     785       93236 : bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) {
     786             :   DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n"
     787             :                << "********** Function: " << MF.getName() << '\n');
     788       93236 :   if (skipFunction(*MF.getFunction()))
     789             :     return false;
     790             : 
     791             :   // Only run if conversion if the target wants it.
     792       93190 :   const TargetSubtargetInfo &STI = MF.getSubtarget();
     793       93190 :   if (!STI.enableEarlyIfConversion())
     794             :     return false;
     795             : 
     796       24350 :   TII = STI.getInstrInfo();
     797       24350 :   TRI = STI.getRegisterInfo();
     798       24350 :   SchedModel = STI.getSchedModel();
     799       24350 :   MRI = &MF.getRegInfo();
     800       24350 :   DomTree = &getAnalysis<MachineDominatorTree>();
     801       24350 :   Loops = getAnalysisIfAvailable<MachineLoopInfo>();
     802       24350 :   Traces = &getAnalysis<MachineTraceMetrics>();
     803       24350 :   MinInstr = nullptr;
     804             : 
     805       24350 :   bool Changed = false;
     806       24350 :   IfConv.runOnMachineFunction(MF);
     807             : 
     808             :   // Visit blocks in dominator tree post-order. The post-order enables nested
     809             :   // if-conversion in a single pass. The tryConvertIf() function may erase
     810             :   // blocks, but only blocks dominated by the head block. This makes it safe to
     811             :   // update the dominator tree while the post-order iterator is still active.
     812      190296 :   for (auto DomNode : post_order(DomTree))
     813       34273 :     if (tryConvertIf(DomNode->getBlock()))
     814          72 :       Changed = true;
     815             : 
     816       24350 :   return Changed;
     817      216918 : }

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