LCOV - code coverage report
Current view: top level - lib/CodeGen - ExpandPostRAPseudos.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 73 77 94.8 %
Date: 2017-09-14 15:23:50 Functions: 8 9 88.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
      11             : // instructions after register allocation.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "llvm/CodeGen/MachineFunctionPass.h"
      16             : #include "llvm/CodeGen/MachineInstr.h"
      17             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      18             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      19             : #include "llvm/CodeGen/Passes.h"
      20             : #include "llvm/Support/Debug.h"
      21             : #include "llvm/Support/raw_ostream.h"
      22             : #include "llvm/Target/TargetInstrInfo.h"
      23             : #include "llvm/Target/TargetRegisterInfo.h"
      24             : #include "llvm/Target/TargetSubtargetInfo.h"
      25             : 
      26             : using namespace llvm;
      27             : 
      28             : #define DEBUG_TYPE "postrapseudos"
      29             : 
      30             : namespace {
      31       16823 : struct ExpandPostRA : public MachineFunctionPass {
      32             : private:
      33             :   const TargetRegisterInfo *TRI;
      34             :   const TargetInstrInfo *TII;
      35             : 
      36             : public:
      37             :   static char ID; // Pass identification, replacement for typeid
      38       16926 :   ExpandPostRA() : MachineFunctionPass(ID) {}
      39             : 
      40       16855 :   void getAnalysisUsage(AnalysisUsage &AU) const override {
      41       16855 :     AU.setPreservesCFG();
      42       33710 :     AU.addPreservedID(MachineLoopInfoID);
      43       33710 :     AU.addPreservedID(MachineDominatorsID);
      44       16855 :     MachineFunctionPass::getAnalysisUsage(AU);
      45       16855 :   }
      46             : 
      47             :   /// runOnMachineFunction - pass entry point
      48             :   bool runOnMachineFunction(MachineFunction&) override;
      49             : 
      50             : private:
      51             :   bool LowerSubregToReg(MachineInstr *MI);
      52             :   bool LowerCopy(MachineInstr *MI);
      53             : 
      54             :   void TransferImplicitOperands(MachineInstr *MI);
      55             : };
      56             : } // end anonymous namespace
      57             : 
      58             : char ExpandPostRA::ID = 0;
      59             : char &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID;
      60             : 
      61      151199 : INITIALIZE_PASS(ExpandPostRA, DEBUG_TYPE,
      62             :                 "Post-RA pseudo instruction expansion pass", false, false)
      63             : 
      64             : /// TransferImplicitOperands - MI is a pseudo-instruction, and the lowered
      65             : /// replacement instructions immediately precede it.  Copy any implicit
      66             : /// operands from MI to the replacement instruction.
      67       31375 : void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) {
      68       31375 :   MachineBasicBlock::iterator CopyMI = MI;
      69       31375 :   --CopyMI;
      70             : 
      71       63405 :   for (const MachineOperand &MO : MI->implicit_operands())
      72       32030 :     if (MO.isReg())
      73       32030 :       CopyMI->addOperand(MO);
      74       31375 : }
      75             : 
      76         164 : bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
      77         164 :   MachineBasicBlock *MBB = MI->getParent();
      78             :   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
      79             :          MI->getOperand(1).isImm() &&
      80             :          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
      81             :           MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
      82             : 
      83         164 :   unsigned DstReg  = MI->getOperand(0).getReg();
      84         164 :   unsigned InsReg  = MI->getOperand(2).getReg();
      85             :   assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
      86         164 :   unsigned SubIdx  = MI->getOperand(3).getImm();
      87             : 
      88             :   assert(SubIdx != 0 && "Invalid index for insert_subreg");
      89         164 :   unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
      90             : 
      91             :   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
      92             :          "Insert destination must be in a physical register");
      93             :   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
      94             :          "Inserted value must be in a physical register");
      95             : 
      96             :   DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
      97             : 
      98         164 :   if (MI->allDefsAreDead()) {
      99           0 :     MI->setDesc(TII->get(TargetOpcode::KILL));
     100             :     DEBUG(dbgs() << "subreg: replaced by: " << *MI);
     101             :     return true;
     102             :   }
     103             : 
     104         164 :   if (DstSubReg == InsReg) {
     105             :     // No need to insert an identity copy instruction.
     106             :     // Watch out for case like this:
     107             :     // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
     108             :     // We must leave %RAX live.
     109          17 :     if (DstReg != InsReg) {
     110          51 :       MI->setDesc(TII->get(TargetOpcode::KILL));
     111          17 :       MI->RemoveOperand(3);     // SubIdx
     112          17 :       MI->RemoveOperand(1);     // Imm
     113             :       DEBUG(dbgs() << "subreg: replace by: " << *MI);
     114             :       return true;
     115             :     }
     116             :     DEBUG(dbgs() << "subreg: eliminated!");
     117             :   } else {
     118         588 :     TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
     119         294 :                      MI->getOperand(2).isKill());
     120             : 
     121             :     // Implicitly define DstReg for subsequent uses.
     122         147 :     MachineBasicBlock::iterator CopyMI = MI;
     123         147 :     --CopyMI;
     124         147 :     CopyMI->addRegisterDefined(DstReg);
     125             :     DEBUG(dbgs() << "subreg: " << *CopyMI);
     126             :   }
     127             : 
     128             :   DEBUG(dbgs() << '\n');
     129         147 :   MBB->erase(MI);
     130             :   return true;
     131             : }
     132             : 
     133      169121 : bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
     134             : 
     135      169121 :   if (MI->allDefsAreDead()) {
     136             :     DEBUG(dbgs() << "dead copy: " << *MI);
     137         948 :     MI->setDesc(TII->get(TargetOpcode::KILL));
     138             :     DEBUG(dbgs() << "replaced by: " << *MI);
     139             :     return true;
     140             :   }
     141             : 
     142      168805 :   MachineOperand &DstMO = MI->getOperand(0);
     143      337610 :   MachineOperand &SrcMO = MI->getOperand(1);
     144             : 
     145      168805 :   bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg());
     146      337610 :   if (IdentityCopy || SrcMO.isUndef()) {
     147             :     DEBUG(dbgs() << (IdentityCopy ? "identity copy: " : "undef copy:    ") << *MI);
     148             :     // No need to insert an identity copy instruction, but replace with a KILL
     149             :     // if liveness is changed.
     150           1 :     if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
     151             :       // We must make sure the super-register gets killed. Replace the
     152             :       // instruction with KILL.
     153           3 :       MI->setDesc(TII->get(TargetOpcode::KILL));
     154             :       DEBUG(dbgs() << "replaced by:   " << *MI);
     155             :       return true;
     156             :     }
     157             :     // Vanilla identity copy.
     158           0 :     MI->eraseFromParent();
     159             :     return true;
     160             :   }
     161             : 
     162             :   DEBUG(dbgs() << "real copy:   " << *MI);
     163      675216 :   TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
     164      337608 :                    DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
     165             : 
     166      168804 :   if (MI->getNumOperands() > 2)
     167       31375 :     TransferImplicitOperands(MI);
     168             :   DEBUG({
     169             :     MachineBasicBlock::iterator dMI = MI;
     170             :     dbgs() << "replaced by: " << *(--dMI);
     171             :   });
     172      168804 :   MI->eraseFromParent();
     173             :   return true;
     174             : }
     175             : 
     176             : /// runOnMachineFunction - Reduce subregister inserts and extracts to register
     177             : /// copies.
     178             : ///
     179      142732 : bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
     180             :   DEBUG(dbgs() << "Machine Function\n"
     181             :                << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
     182             :                << "********** Function: " << MF.getName() << '\n');
     183      142732 :   TRI = MF.getSubtarget().getRegisterInfo();
     184      142732 :   TII = MF.getSubtarget().getInstrInfo();
     185             : 
     186      142732 :   bool MadeChange = false;
     187             : 
     188      285464 :   for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
     189      430345 :        mbbi != mbbe; ++mbbi) {
     190     1150452 :     for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
     191     3280673 :          mi != me;) {
     192     2993060 :       MachineInstr &MI = *mi;
     193             :       // Advance iterator here because MI may be erased.
     194     2993060 :       ++mi;
     195             : 
     196             :       // Only expand pseudos.
     197     2993060 :       if (!MI.isPseudo())
     198     2158497 :         continue;
     199             : 
     200             :       // Give targets a chance to expand even standard pseudos.
     201      940942 :       if (TII->expandPostRAPseudo(MI)) {
     202      106379 :         MadeChange = true;
     203      106379 :         continue;
     204             :       }
     205             : 
     206             :       // Expand standard pseudos.
     207      741010 :       switch (MI.getOpcode()) {
     208         164 :       case TargetOpcode::SUBREG_TO_REG:
     209         164 :         MadeChange |= LowerSubregToReg(&MI);
     210         164 :         break;
     211      169121 :       case TargetOpcode::COPY:
     212      169121 :         MadeChange |= LowerCopy(&MI);
     213      169121 :         break;
     214       12826 :       case TargetOpcode::DBG_VALUE:
     215       12826 :         continue;
     216           0 :       case TargetOpcode::INSERT_SUBREG:
     217             :       case TargetOpcode::EXTRACT_SUBREG:
     218           0 :         llvm_unreachable("Sub-register pseudos should have been eliminated.");
     219             :       }
     220             :     }
     221             :   }
     222             : 
     223      142732 :   return MadeChange;
     224             : }

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