LCOV - code coverage report
Current view: top level - lib/CodeGen/GlobalISel - InstructionSelect.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 62 70 88.6 %
Date: 2018-07-13 00:08:38 Functions: 6 6 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file
      10             : /// This file implements the InstructionSelect class.
      11             : //===----------------------------------------------------------------------===//
      12             : 
      13             : #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
      14             : #include "llvm/ADT/PostOrderIterator.h"
      15             : #include "llvm/ADT/Twine.h"
      16             : #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
      17             : #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
      18             : #include "llvm/CodeGen/GlobalISel/Utils.h"
      19             : #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
      20             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      21             : #include "llvm/CodeGen/TargetLowering.h"
      22             : #include "llvm/CodeGen/TargetPassConfig.h"
      23             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      24             : #include "llvm/Config/config.h"
      25             : #include "llvm/IR/Constants.h"
      26             : #include "llvm/IR/Function.h"
      27             : #include "llvm/Support/CommandLine.h"
      28             : #include "llvm/Support/Debug.h"
      29             : #include "llvm/Support/TargetRegistry.h"
      30             : 
      31             : #define DEBUG_TYPE "instruction-select"
      32             : 
      33             : using namespace llvm;
      34             : 
      35             : #ifdef LLVM_GISEL_COV_PREFIX
      36             : static cl::opt<std::string>
      37             :     CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
      38             :                    cl::desc("Record GlobalISel rule coverage files of this "
      39             :                             "prefix if instrumentation was generated"));
      40             : #else
      41       99743 : static const std::string CoveragePrefix = "";
      42             : #endif
      43             : 
      44             : char InstructionSelect::ID = 0;
      45       73521 : INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,
      46             :                       "Select target instructions out of generic instructions",
      47             :                       false, false)
      48       73521 : INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
      49     1128632 : INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE,
      50             :                     "Select target instructions out of generic instructions",
      51             :                     false, false)
      52             : 
      53         373 : InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) {
      54         373 :   initializeInstructionSelectPass(*PassRegistry::getPassRegistry());
      55         373 : }
      56             : 
      57         337 : void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
      58             :   AU.addRequired<TargetPassConfig>();
      59         337 :   MachineFunctionPass::getAnalysisUsage(AU);
      60         337 : }
      61             : 
      62        1817 : bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
      63             :   // If the ISel pipeline failed, do not bother running that pass.
      64        1817 :   if (MF.getProperties().hasProperty(
      65             :           MachineFunctionProperties::Property::FailedISel))
      66             :     return false;
      67             : 
      68             :   LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
      69             : 
      70        1705 :   const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
      71        1705 :   const InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
      72        1705 :   CodeGenCoverage CoverageInfo;
      73             :   assert(ISel && "Cannot work without InstructionSelector");
      74             : 
      75             :   // An optimization remark emitter. Used to report failures.
      76             :   MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
      77             : 
      78             :   // FIXME: There are many other MF/MFI fields we need to initialize.
      79             : 
      80        1705 :   MachineRegisterInfo &MRI = MF.getRegInfo();
      81             : #ifndef NDEBUG
      82             :   // Check that our input is fully legal: we require the function to have the
      83             :   // Legalized property, so it should be.
      84             :   // FIXME: This should be in the MachineVerifier, as the RegBankSelected
      85             :   // property check already is.
      86             :   if (!DisableGISelLegalityCheck)
      87             :     if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
      88             :       reportGISelFailure(MF, TPC, MORE, "gisel-select",
      89             :                          "instruction is not legal", *MI);
      90             :       return false;
      91             :     }
      92             : #endif
      93             :   // FIXME: We could introduce new blocks and will need to fix the outer loop.
      94             :   // Until then, keep track of the number of blocks to assert that we don't.
      95             :   const size_t NumBlocks = MF.size();
      96             : 
      97        8685 :   for (MachineBasicBlock *MBB : post_order(&MF)) {
      98        1798 :     if (MBB->empty())
      99          21 :       continue;
     100             : 
     101             :     // Select instructions in reverse block order. We permit erasing so have
     102             :     // to resort to manually iterating and recognizing the begin (rend) case.
     103             :     bool ReachedBegin = false;
     104        1777 :     for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
     105       12163 :          !ReachedBegin;) {
     106             : #ifndef NDEBUG
     107             :       // Keep track of the insertion range for debug printing.
     108             :       const auto AfterIt = std::next(MII);
     109             : #endif
     110             :       // Select this instruction.
     111             :       MachineInstr &MI = *MII;
     112             : 
     113             :       // And have our iterator point to the next instruction, if there is one.
     114       10399 :       if (MII == Begin)
     115             :         ReachedBegin = true;
     116             :       else
     117             :         --MII;
     118             : 
     119             :       LLVM_DEBUG(dbgs() << "Selecting: \n  " << MI);
     120             : 
     121             :       // We could have folded this instruction away already, making it dead.
     122             :       // If so, erase it.
     123       11133 :       if (isTriviallyDead(MI, MRI)) {
     124             :         LLVM_DEBUG(dbgs() << "Is dead; erasing.\n");
     125         734 :         MI.eraseFromParentAndMarkDBGValuesForRemoval();
     126         734 :         continue;
     127             :       }
     128             : 
     129        9665 :       if (!ISel->select(MI, CoverageInfo)) {
     130             :         // FIXME: It would be nice to dump all inserted instructions.  It's
     131             :         // not obvious how, esp. considering select() can insert after MI.
     132          12 :         reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
     133          11 :         return false;
     134             :       }
     135             : 
     136             :       // Dump the range of instructions that MI expanded into.
     137             :       LLVM_DEBUG({
     138             :         auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
     139             :         dbgs() << "Into:\n";
     140             :         for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
     141             :           dbgs() << "  " << InsertedMI;
     142             :         dbgs() << '\n';
     143             :       });
     144             :     }
     145             :   }
     146             : 
     147        1692 :   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
     148             : 
     149        3475 :   for (MachineBasicBlock &MBB : MF) {
     150        1783 :     if (MBB.empty())
     151          21 :       continue;
     152             : 
     153             :     // Try to find redundant copies b/w vregs of the same register class.
     154             :     bool ReachedBegin = false;
     155       13848 :     for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
     156             :       // Select this instruction.
     157             :       MachineInstr &MI = *MII;
     158             : 
     159             :       // And have our iterator point to the next instruction, if there is one.
     160       10324 :       if (MII == Begin)
     161             :         ReachedBegin = true;
     162             :       else
     163             :         --MII;
     164       20648 :       if (MI.getOpcode() != TargetOpcode::COPY)
     165        5023 :         continue;
     166        5301 :       unsigned SrcReg = MI.getOperand(1).getReg();
     167        5301 :       unsigned DstReg = MI.getOperand(0).getReg();
     168        8082 :       if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
     169             :           TargetRegisterInfo::isVirtualRegister(DstReg)) {
     170             :         auto SrcRC = MRI.getRegClass(SrcReg);
     171             :         auto DstRC = MRI.getRegClass(DstReg);
     172        1062 :         if (SrcRC == DstRC) {
     173         276 :           MRI.replaceRegWith(DstReg, SrcReg);
     174         276 :           MI.eraseFromParentAndMarkDBGValuesForRemoval();
     175             :         }
     176             :       }
     177             :     }
     178             :   }
     179             : 
     180             :   // Now that selection is complete, there are no more generic vregs.  Verify
     181             :   // that the size of the now-constrained vreg is unchanged and that it has a
     182             :   // register class.
     183       16656 :   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
     184             :     unsigned VReg = TargetRegisterInfo::index2VirtReg(I);
     185             : 
     186             :     MachineInstr *MI = nullptr;
     187        7482 :     if (!MRI.def_empty(VReg))
     188       11960 :       MI = &*MRI.def_instr_begin(VReg);
     189        1502 :     else if (!MRI.use_empty(VReg))
     190           0 :       MI = &*MRI.use_instr_begin(VReg);
     191        5980 :     if (!MI)
     192        1502 :       continue;
     193             : 
     194             :     const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
     195        5980 :     if (!RC) {
     196           0 :       reportGISelFailure(MF, TPC, MORE, "gisel-select",
     197             :                          "VReg has no regclass after selection", *MI);
     198           0 :       return false;
     199             :     }
     200             : 
     201        5980 :     const LLT Ty = MRI.getType(VReg);
     202       11690 :     if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
     203           0 :       reportGISelFailure(
     204             :           MF, TPC, MORE, "gisel-select",
     205             :           "VReg's low-level type and register class have different sizes", *MI);
     206           0 :       return false;
     207             :     }
     208             :   }
     209             : 
     210        1692 :   if (MF.size() != NumBlocks) {
     211             :     MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
     212           0 :                                       MF.getFunction().getSubprogram(),
     213           0 :                                       /*MBB=*/nullptr);
     214             :     R << "inserting blocks is not supported yet";
     215           0 :     reportGISelFailure(MF, TPC, MORE, R);
     216             :     return false;
     217             :   }
     218             : 
     219        1692 :   auto &TLI = *MF.getSubtarget().getTargetLowering();
     220        1692 :   TLI.finalizeLowering(MF);
     221             : 
     222             :   LLVM_DEBUG({
     223             :     dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
     224             :     for (auto RuleID : CoverageInfo.covered())
     225             :       dbgs() << " id" << RuleID;
     226             :     dbgs() << "\n\n";
     227             :   });
     228        3384 :   CoverageInfo.emit(CoveragePrefix,
     229        1692 :                     MF.getSubtarget()
     230        1692 :                         .getTargetLowering()
     231        1692 :                         ->getTargetMachine()
     232        1692 :                         .getTarget()
     233             :                         .getBackendName());
     234             : 
     235             :   // If we successfully selected the function nothing is going to use the vreg
     236             :   // types after us (otherwise MIRPrinter would need them). Make sure the types
     237             :   // disappear.
     238        1692 :   MRI.clearVirtRegTypes();
     239             : 
     240             :   // FIXME: Should we accurately track changes?
     241        1692 :   return true;
     242      199486 : }

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