LCOV - code coverage report
Current view: top level - lib/CodeGen/GlobalISel - InstructionSelector.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 33 33 100.0 %
Date: 2017-09-14 15:23:50 Functions: 5 5 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file
      10             : /// This file implements the InstructionSelector class.
      11             : //===----------------------------------------------------------------------===//
      12             : 
      13             : #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
      14             : #include "llvm/CodeGen/GlobalISel/Utils.h"
      15             : #include "llvm/CodeGen/MachineBasicBlock.h"
      16             : #include "llvm/CodeGen/MachineFunction.h"
      17             : #include "llvm/CodeGen/MachineInstr.h"
      18             : #include "llvm/CodeGen/MachineOperand.h"
      19             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      20             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      21             : #include "llvm/MC/MCInstrDesc.h"
      22             : #include "llvm/IR/Constants.h"
      23             : #include "llvm/Target/TargetInstrInfo.h"
      24             : #include "llvm/Support/Debug.h"
      25             : #include "llvm/Support/raw_ostream.h"
      26             : #include "llvm/Target/TargetRegisterInfo.h"
      27             : #include <cassert>
      28             : 
      29             : #define DEBUG_TYPE "instructionselector"
      30             : 
      31             : using namespace llvm;
      32             : 
      33       13721 : InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)
      34       82326 :     : Renderers(MaxRenderers, nullptr), MIs() {}
      35             : 
      36             : InstructionSelector::InstructionSelector() = default;
      37             : 
      38          25 : bool InstructionSelector::constrainOperandRegToRegClass(
      39             :     MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
      40             :     const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
      41             :     const RegisterBankInfo &RBI) const {
      42          25 :   MachineBasicBlock &MBB = *I.getParent();
      43          25 :   MachineFunction &MF = *MBB.getParent();
      44          25 :   MachineRegisterInfo &MRI = MF.getRegInfo();
      45             : 
      46             :   return
      47          50 :       constrainRegToClass(MRI, TII, RBI, I, I.getOperand(OpIdx).getReg(), RC);
      48             : }
      49             : 
      50        1986 : bool InstructionSelector::constrainSelectedInstRegOperands(
      51             :     MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
      52             :     const RegisterBankInfo &RBI) const {
      53        1986 :   MachineBasicBlock &MBB = *I.getParent();
      54        1986 :   MachineFunction &MF = *MBB.getParent();
      55        1986 :   MachineRegisterInfo &MRI = MF.getRegInfo();
      56             : 
      57        9895 :   for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
      58       15818 :     MachineOperand &MO = I.getOperand(OpI);
      59             : 
      60             :     // There's nothing to be done on non-register operands.
      61        7909 :     if (!MO.isReg())
      62        2394 :       continue;
      63             : 
      64             :     DEBUG(dbgs() << "Converting operand: " << MO << '\n');
      65             :     assert(MO.isReg() && "Unsupported non-reg operand");
      66             : 
      67        5515 :     unsigned Reg = MO.getReg();
      68             :     // Physical registers don't need to be constrained.
      69        5515 :     if (TRI.isPhysicalRegister(Reg))
      70         142 :       continue;
      71             : 
      72             :     // Register operands with a value of 0 (e.g. predicate operands) don't need
      73             :     // to be constrained.
      74        5373 :     if (Reg == 0)
      75        1408 :       continue;
      76             : 
      77             :     // If the operand is a vreg, we should constrain its regclass, and only
      78             :     // insert COPYs if that's impossible.
      79             :     // constrainOperandRegClass does that for us.
      80        3965 :     MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
      81             :                                        Reg, OpI));
      82             : 
      83             :     // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
      84             :     // done.
      85        3965 :     if (MO.isUse()) {
      86        2597 :       int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
      87         230 :       if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
      88         122 :         I.tieOperands(DefIdx, OpI);
      89             :     }
      90             :   }
      91        1986 :   return true;
      92             : }
      93             : 
      94          74 : bool InstructionSelector::isOperandImmEqual(
      95             :     const MachineOperand &MO, int64_t Value,
      96             :     const MachineRegisterInfo &MRI) const {
      97          74 :   if (MO.isReg() && MO.getReg())
      98         142 :     if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
      99          12 :       return *VRegVal == Value;
     100             :   return false;
     101             : }
     102             : 
     103          11 : bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI) const {
     104          22 :   return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
     105          33 :          MI.implicit_operands().begin() == MI.implicit_operands().end();
     106             : }

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