LCOV - code coverage report
Current view: top level - lib/CodeGen/GlobalISel - RegisterBank.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 8 36 22.2 %
Date: 2017-09-14 15:23:50 Functions: 2 6 33.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file
      10             : /// This file implements the RegisterBank class.
      11             : //===----------------------------------------------------------------------===//
      12             : 
      13             : #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
      14             : #include "llvm/Target/TargetRegisterInfo.h"
      15             : 
      16             : #define DEBUG_TYPE "registerbank"
      17             : 
      18             : using namespace llvm;
      19             : 
      20             : const unsigned RegisterBank::InvalidID = UINT_MAX;
      21             : 
      22      650754 : RegisterBank::RegisterBank(
      23             :     unsigned ID, const char *Name, unsigned Size,
      24      650754 :     const uint32_t *CoveredClasses, unsigned NumRegClasses)
      25     1301508 :     : ID(ID), Name(Name), Size(Size) {
      26      650754 :   ContainedRegClasses.resize(NumRegClasses);
      27     1301508 :   ContainedRegClasses.setBitsInMask(CoveredClasses);
      28      650754 : }
      29             : 
      30           0 : bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
      31             :   assert(isValid() && "Invalid register bank");
      32           0 :   for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
      33           0 :     const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
      34             : 
      35           0 :     if (!covers(RC))
      36             :       continue;
      37             :     // Verify that the register bank covers all the sub classes of the
      38             :     // classes it covers.
      39             : 
      40             :     // Use a different (slow in that case) method than
      41             :     // RegisterBankInfo to find the subclasses of RC, to make sure
      42             :     // both agree on the covers.
      43             :     for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
      44             :       const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
      45             : 
      46             :       if (!RC.hasSubClassEq(&SubRC))
      47             :         continue;
      48             : 
      49             :       // Verify that the Size of the register bank is big enough to cover
      50             :       // all the register classes it covers.
      51             :       assert(getSize() >= TRI.getRegSizeInBits(SubRC) &&
      52             :              "Size is not big enough for all the subclasses!");
      53             :       assert(covers(SubRC) && "Not all subclasses are covered");
      54             :     }
      55             :   }
      56           0 :   return true;
      57             : }
      58             : 
      59        3769 : bool RegisterBank::covers(const TargetRegisterClass &RC) const {
      60             :   assert(isValid() && "RB hasn't been initialized yet");
      61       11307 :   return ContainedRegClasses.test(RC.getID());
      62             : }
      63             : 
      64           0 : bool RegisterBank::isValid() const {
      65           0 :   return ID != InvalidID && Name != nullptr && Size != 0 &&
      66             :          // A register bank that does not cover anything is useless.
      67           0 :          !ContainedRegClasses.empty();
      68             : }
      69             : 
      70           0 : bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
      71             :   // There must be only one instance of a given register bank alive
      72             :   // for the whole compilation.
      73             :   // The RegisterBankInfo is supposed to enforce that.
      74             :   assert((OtherRB.getID() != getID() || &OtherRB == this) &&
      75             :          "ID does not uniquely identify a RegisterBank");
      76           0 :   return &OtherRB == this;
      77             : }
      78             : 
      79             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
      80             : LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const {
      81             :   print(dbgs(), /* IsForDebug */ true, TRI);
      82             : }
      83             : #endif
      84             : 
      85           0 : void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
      86             :                          const TargetRegisterInfo *TRI) const {
      87           0 :   OS << getName();
      88           0 :   if (!IsForDebug)
      89             :     return;
      90           0 :   OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
      91           0 :      << "isValid:" << isValid() << '\n'
      92           0 :      << "Number of Covered register classes: " << ContainedRegClasses.count()
      93           0 :      << '\n';
      94             :   // Print all the subclasses if we can.
      95             :   // This register classes may not be properly initialized yet.
      96           0 :   if (!TRI || ContainedRegClasses.empty())
      97             :     return;
      98             :   assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
      99             :          "TRI does not match the initialization process?");
     100           0 :   bool IsFirst = true;
     101           0 :   OS << "Covered register classes:\n";
     102           0 :   for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
     103           0 :     const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
     104             : 
     105           0 :     if (!covers(RC))
     106           0 :       continue;
     107             : 
     108           0 :     if (!IsFirst)
     109           0 :       OS << ", ";
     110           0 :     OS << TRI->getRegClassName(&RC);
     111           0 :     IsFirst = false;
     112             :   }
     113             : }

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