LCOV - code coverage report
Current view: top level - lib/CodeGen/GlobalISel - Utils.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 82 83 98.8 %
Date: 2018-06-17 00:07:59 Functions: 10 10 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file This file implements the utility functions used by the GlobalISel
      10             : /// pipeline.
      11             : //===----------------------------------------------------------------------===//
      12             : 
      13             : #include "llvm/CodeGen/GlobalISel/Utils.h"
      14             : #include "llvm/ADT/APFloat.h"
      15             : #include "llvm/ADT/Twine.h"
      16             : #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
      17             : #include "llvm/CodeGen/MachineInstr.h"
      18             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      19             : #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
      20             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      21             : #include "llvm/CodeGen/TargetInstrInfo.h"
      22             : #include "llvm/CodeGen/TargetPassConfig.h"
      23             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      24             : #include "llvm/IR/Constants.h"
      25             : 
      26             : #define DEBUG_TYPE "globalisel-utils"
      27             : 
      28             : using namespace llvm;
      29             : 
      30        6173 : unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
      31             :                                    const TargetInstrInfo &TII,
      32             :                                    const RegisterBankInfo &RBI,
      33             :                                    MachineInstr &InsertPt, unsigned Reg,
      34             :                                    const TargetRegisterClass &RegClass) {
      35        6173 :   if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) {
      36          21 :     unsigned NewReg = MRI.createVirtualRegister(&RegClass);
      37          42 :     BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
      38          21 :             TII.get(TargetOpcode::COPY), NewReg)
      39          21 :         .addReg(Reg);
      40          21 :     return NewReg;
      41             :   }
      42             : 
      43             :   return Reg;
      44             : }
      45             : 
      46        5923 : unsigned llvm::constrainOperandRegClass(
      47             :     const MachineFunction &MF, const TargetRegisterInfo &TRI,
      48             :     MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
      49             :     const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
      50             :     const MachineOperand &RegMO, unsigned OpIdx) {
      51        5923 :   unsigned Reg = RegMO.getReg();
      52             :   // Assume physical registers are properly constrained.
      53             :   assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
      54             :          "PhysReg not implemented");
      55             : 
      56        5923 :   const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
      57             :   // Some of the target independent instructions, like COPY, may not impose any
      58             :   // register class constraints on some of their operands: If it's a use, we can
      59             :   // skip constraining as the instruction defining the register would constrain
      60             :   // it.
      61             : 
      62             :   // We can't constrain unallocatable register classes, because we can't create
      63             :   // virtual registers for these classes, so we need to let targets handled this
      64             :   // case.
      65       11828 :   if (RegClass && !RegClass->isAllocatable())
      66          20 :     RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
      67             : 
      68        5923 :   if (!RegClass) {
      69             :     assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
      70             :            "Register class constraint is required unless either the "
      71             :            "instruction is target independent or the operand is a use");
      72             :     // FIXME: Just bailing out like this here could be not enough, unless we
      73             :     // expect the users of this function to do the right thing for PHIs and
      74             :     // COPY:
      75             :     //   v1 = COPY v0
      76             :     //   v2 = COPY v1
      77             :     // v1 here may end up not being constrained at all. Please notice that to
      78             :     // reproduce the issue we likely need a destination pattern of a selection
      79             :     // rule producing such extra copies, not just an input GMIR with them as
      80             :     // every existing target using selectImpl handles copies before calling it
      81             :     // and they never reach this function.
      82             :     return Reg;
      83             :   }
      84        5897 :   return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass);
      85             : }
      86             : 
      87        2928 : bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
      88             :                                             const TargetInstrInfo &TII,
      89             :                                             const TargetRegisterInfo &TRI,
      90             :                                             const RegisterBankInfo &RBI) {
      91             :   assert(!isPreISelGenericOpcode(I.getOpcode()) &&
      92             :          "A selected instruction is expected");
      93        2928 :   MachineBasicBlock &MBB = *I.getParent();
      94        2928 :   MachineFunction &MF = *MBB.getParent();
      95        2928 :   MachineRegisterInfo &MRI = MF.getRegInfo();
      96             : 
      97       13991 :   for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
      98       11063 :     MachineOperand &MO = I.getOperand(OpI);
      99             : 
     100             :     // There's nothing to be done on non-register operands.
     101       11063 :     if (!MO.isReg())
     102        3265 :       continue;
     103             : 
     104             :     LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
     105             :     assert(MO.isReg() && "Unsupported non-reg operand");
     106             : 
     107        7798 :     unsigned Reg = MO.getReg();
     108             :     // Physical registers don't need to be constrained.
     109        7798 :     if (TRI.isPhysicalRegister(Reg))
     110         171 :       continue;
     111             : 
     112             :     // Register operands with a value of 0 (e.g. predicate operands) don't need
     113             :     // to be constrained.
     114        7627 :     if (Reg == 0)
     115        1713 :       continue;
     116             : 
     117             :     // If the operand is a vreg, we should constrain its regclass, and only
     118             :     // insert COPYs if that's impossible.
     119             :     // constrainOperandRegClass does that for us.
     120        5914 :     MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
     121             :                                        MO, OpI));
     122             : 
     123             :     // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
     124             :     // done.
     125        5914 :     if (MO.isUse()) {
     126        3516 :       int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
     127         410 :       if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
     128         144 :         I.tieOperands(DefIdx, OpI);
     129             :     }
     130             :   }
     131        2928 :   return true;
     132             : }
     133             : 
     134       16795 : bool llvm::isTriviallyDead(const MachineInstr &MI,
     135             :                            const MachineRegisterInfo &MRI) {
     136             :   // If we can move an instruction, we can remove it.  Otherwise, it has
     137             :   // a side-effect of some sort.
     138       16795 :   bool SawStore = false;
     139       16795 :   if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
     140             :     return false;
     141             : 
     142             :   // Instructions without side-effects are dead iff they only define dead vregs.
     143       18351 :   for (auto &MO : MI.operands()) {
     144       30394 :     if (!MO.isReg() || !MO.isDef())
     145        1180 :       continue;
     146             : 
     147       14285 :     unsigned Reg = MO.getReg();
     148       26884 :     if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
     149             :         !MRI.use_nodbg_empty(Reg))
     150             :       return false;
     151             :   }
     152             :   return true;
     153             : }
     154             : 
     155          42 : void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
     156             :                               MachineOptimizationRemarkEmitter &MORE,
     157             :                               MachineOptimizationRemarkMissed &R) {
     158             :   MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
     159             : 
     160             :   // Print the function name explicitly if we don't have a debug location (which
     161             :   // makes the diagnostic less useful) or if we're going to emit a raw error.
     162          42 :   if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
     163         126 :     R << (" (in function: " + MF.getName() + ")").str();
     164             : 
     165          42 :   if (TPC.isGlobalISelAbortEnabled())
     166           2 :     report_fatal_error(R.getMsg());
     167             :   else
     168          40 :     MORE.emit(R);
     169          40 : }
     170             : 
     171          42 : void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
     172             :                               MachineOptimizationRemarkEmitter &MORE,
     173             :                               const char *PassName, StringRef Msg,
     174             :                               const MachineInstr &MI) {
     175             :   MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
     176         126 :                                     MI.getDebugLoc(), MI.getParent());
     177             :   R << Msg;
     178             :   // Printing MI is expensive;  only do it if expensive remarks are enabled.
     179         100 :   if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
     180          48 :     R << ": " << ore::MNV("Inst", MI);
     181          42 :   reportGISelFailure(MF, TPC, MORE, R);
     182          40 : }
     183             : 
     184         485 : Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
     185             :                                            const MachineRegisterInfo &MRI) {
     186         485 :   MachineInstr *MI = MRI.getVRegDef(VReg);
     187         970 :   if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
     188             :     return None;
     189             : 
     190         528 :   if (MI->getOperand(1).isImm())
     191           5 :     return MI->getOperand(1).getImm();
     192             : 
     193         518 :   if (MI->getOperand(1).isCImm() &&
     194         259 :       MI->getOperand(1).getCImm()->getBitWidth() <= 64)
     195             :     return MI->getOperand(1).getCImm()->getSExtValue();
     196             : 
     197             :   return None;
     198             : }
     199             : 
     200           3 : const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
     201             :                                        const MachineRegisterInfo &MRI) {
     202           3 :   MachineInstr *MI = MRI.getVRegDef(VReg);
     203           6 :   if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
     204             :     return nullptr;
     205           3 :   return MI->getOperand(1).getFPImm();
     206             : }
     207             : 
     208        1494 : llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, unsigned Reg,
     209             :                                        const MachineRegisterInfo &MRI) {
     210        1494 :   auto *DefMI = MRI.getVRegDef(Reg);
     211        1494 :   auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
     212        1494 :   if (!DstTy.isValid())
     213             :     return nullptr;
     214        3021 :   while (DefMI->getOpcode() == TargetOpcode::COPY) {
     215         141 :     unsigned SrcReg = DefMI->getOperand(1).getReg();
     216             :     auto SrcTy = MRI.getType(SrcReg);
     217         141 :     if (!SrcTy.isValid() || SrcTy != DstTy)
     218             :       break;
     219          11 :     DefMI = MRI.getVRegDef(SrcReg);
     220             :   }
     221        2988 :   return DefMI->getOpcode() == Opcode ? DefMI : nullptr;
     222             : }
     223             : 
     224           3 : APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
     225           3 :   if (Size == 32)
     226           1 :     return APFloat(float(Val));
     227           2 :   if (Size == 64)
     228           1 :     return APFloat(Val);
     229           1 :   if (Size != 16)
     230           0 :     llvm_unreachable("Unsupported FPConstant size");
     231             :   bool Ignored;
     232           1 :   APFloat APF(Val);
     233           1 :   APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
     234             :   return APF;
     235             : }

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