LCOV - code coverage report
Current view: top level - lib/CodeGen/GlobalISel - Utils.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 33 44 75.0 %
Date: 2017-09-14 15:23:50 Functions: 6 7 85.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file This file implements the utility functions used by the GlobalISel
      10             : /// pipeline.
      11             : //===----------------------------------------------------------------------===//
      12             : 
      13             : #include "llvm/CodeGen/GlobalISel/Utils.h"
      14             : #include "llvm/ADT/Twine.h"
      15             : #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
      16             : #include "llvm/CodeGen/MachineInstr.h"
      17             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      18             : #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
      19             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      20             : #include "llvm/CodeGen/TargetPassConfig.h"
      21             : #include "llvm/IR/Constants.h"
      22             : #include "llvm/Target/TargetInstrInfo.h"
      23             : #include "llvm/Target/TargetRegisterInfo.h"
      24             : 
      25             : #define DEBUG_TYPE "globalisel-utils"
      26             : 
      27             : using namespace llvm;
      28             : 
      29        3998 : unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
      30             :                                    const TargetInstrInfo &TII,
      31             :                                    const RegisterBankInfo &RBI,
      32             :                                    MachineInstr &InsertPt, unsigned Reg,
      33             :                                    const TargetRegisterClass &RegClass) {
      34        3998 :   if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) {
      35           0 :     unsigned NewReg = MRI.createVirtualRegister(&RegClass);
      36           0 :     BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
      37           0 :             TII.get(TargetOpcode::COPY), NewReg)
      38           0 :         .addReg(Reg);
      39           0 :     return NewReg;
      40             :   }
      41             : 
      42             :   return Reg;
      43             : }
      44             : 
      45             : 
      46        3973 : unsigned llvm::constrainOperandRegClass(
      47             :     const MachineFunction &MF, const TargetRegisterInfo &TRI,
      48             :     MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
      49             :     const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
      50             :     unsigned Reg, unsigned OpIdx) {
      51             :   // Assume physical registers are properly constrained.
      52             :   assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
      53             :          "PhysReg not implemented");
      54             : 
      55        3973 :   const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
      56        3973 :   return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass);
      57             : }
      58             : 
      59        6969 : bool llvm::isTriviallyDead(const MachineInstr &MI,
      60             :                            const MachineRegisterInfo &MRI) {
      61             :   // If we can move an instruction, we can remove it.  Otherwise, it has
      62             :   // a side-effect of some sort.
      63        6969 :   bool SawStore = false;
      64        6969 :   if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
      65             :     return false;
      66             : 
      67             :   // Instructions without side-effects are dead iff they only define dead vregs.
      68        6564 :   for (auto &MO : MI.operands()) {
      69       11956 :     if (!MO.isReg() || !MO.isDef())
      70         641 :       continue;
      71             : 
      72        5505 :     unsigned Reg = MO.getReg();
      73        9620 :     if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
      74        4115 :         !MRI.use_nodbg_empty(Reg))
      75             :       return false;
      76             :   }
      77             :   return true;
      78             : }
      79             : 
      80          21 : void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
      81             :                               MachineOptimizationRemarkEmitter &MORE,
      82             :                               MachineOptimizationRemarkMissed &R) {
      83          42 :   MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
      84             : 
      85             :   // Print the function name explicitly if we don't have a debug location (which
      86             :   // makes the diagnostic less useful) or if we're going to emit a raw error.
      87          63 :   if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
      88         126 :     R << (" (in function: " + MF.getName() + ")").str();
      89             : 
      90          21 :   if (TPC.isGlobalISelAbortEnabled())
      91           0 :     report_fatal_error(R.getMsg());
      92             :   else
      93          21 :     MORE.emit(R);
      94          21 : }
      95             : 
      96          21 : void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
      97             :                               MachineOptimizationRemarkEmitter &MORE,
      98             :                               const char *PassName, StringRef Msg,
      99             :                               const MachineInstr &MI) {
     100             :   MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
     101          84 :                                     MI.getDebugLoc(), MI.getParent());
     102          84 :   R << Msg << ": " << ore::MNV("Inst", MI);
     103          21 :   reportGISelFailure(MF, TPC, MORE, R);
     104          21 : }
     105             : 
     106         178 : Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
     107             :                                            const MachineRegisterInfo &MRI) {
     108         178 :   MachineInstr *MI = MRI.getVRegDef(VReg);
     109         356 :   if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
     110             :     return None;
     111             : 
     112         160 :   if (MI->getOperand(1).isImm())
     113           0 :     return MI->getOperand(1).getImm();
     114             : 
     115         160 :   if (MI->getOperand(1).isCImm() &&
     116         160 :       MI->getOperand(1).getCImm()->getBitWidth() <= 64)
     117         240 :     return MI->getOperand(1).getCImm()->getSExtValue();
     118             : 
     119             :   return None;
     120             : }
     121             : 
     122           0 : const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
     123             :                                        const MachineRegisterInfo &MRI) {
     124           0 :   MachineInstr *MI = MRI.getVRegDef(VReg);
     125           0 :   if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
     126             :     return nullptr;
     127           0 :   return MI->getOperand(1).getFPImm();
     128             : }

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