LCOV - code coverage report
Current view: top level - lib/CodeGen/GlobalISel - Utils.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 63 72 87.5 %
Date: 2018-02-21 06:32:55 Functions: 8 9 88.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file This file implements the utility functions used by the GlobalISel
      10             : /// pipeline.
      11             : //===----------------------------------------------------------------------===//
      12             : 
      13             : #include "llvm/CodeGen/GlobalISel/Utils.h"
      14             : #include "llvm/ADT/Twine.h"
      15             : #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
      16             : #include "llvm/CodeGen/MachineInstr.h"
      17             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      18             : #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
      19             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      20             : #include "llvm/CodeGen/TargetInstrInfo.h"
      21             : #include "llvm/CodeGen/TargetPassConfig.h"
      22             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      23             : #include "llvm/IR/Constants.h"
      24             : 
      25             : #define DEBUG_TYPE "globalisel-utils"
      26             : 
      27             : using namespace llvm;
      28             : 
      29        5175 : unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
      30             :                                    const TargetInstrInfo &TII,
      31             :                                    const RegisterBankInfo &RBI,
      32             :                                    MachineInstr &InsertPt, unsigned Reg,
      33             :                                    const TargetRegisterClass &RegClass) {
      34        5175 :   if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) {
      35           0 :     unsigned NewReg = MRI.createVirtualRegister(&RegClass);
      36           0 :     BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
      37           0 :             TII.get(TargetOpcode::COPY), NewReg)
      38           0 :         .addReg(Reg);
      39           0 :     return NewReg;
      40             :   }
      41             : 
      42             :   return Reg;
      43             : }
      44             : 
      45             : 
      46        5045 : unsigned llvm::constrainOperandRegClass(
      47             :     const MachineFunction &MF, const TargetRegisterInfo &TRI,
      48             :     MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
      49             :     const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
      50             :     unsigned Reg, unsigned OpIdx) {
      51             :   // Assume physical registers are properly constrained.
      52             :   assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
      53             :          "PhysReg not implemented");
      54             : 
      55        5045 :   const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
      56             :   // Some of the target independent instructions, like COPY, may not impose any
      57             :   // register class constraints on some of their operands:
      58        5045 :   if (!RegClass) {
      59             :     assert(!isTargetSpecificOpcode(II.getOpcode()) &&
      60             :            "Only target independent instructions are allowed to have operands "
      61             :            "with no register class constraints");
      62             :     // FIXME: Just bailing out like this here could be not enough, unless we
      63             :     // expect the users of this function to do the right thing for PHIs and
      64             :     // COPY:
      65             :     //   v1 = COPY v0
      66             :     //   v2 = COPY v1
      67             :     // v1 here may end up not being constrained at all. Please notice that to
      68             :     // reproduce the issue we likely need a destination pattern of a selection
      69             :     // rule producing such extra copies, not just an input GMIR with them as
      70             :     // every existing target using selectImpl handles copies before calling it
      71             :     // and they never reach this function.
      72             :     return Reg;
      73             :   }
      74        5031 :   return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass);
      75             : }
      76             : 
      77        2537 : bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
      78             :                                             const TargetInstrInfo &TII,
      79             :                                             const TargetRegisterInfo &TRI,
      80             :                                             const RegisterBankInfo &RBI) {
      81             :   assert(!isPreISelGenericOpcode(I.getOpcode()) &&
      82             :          "A selected instruction is expected");
      83        2537 :   MachineBasicBlock &MBB = *I.getParent();
      84        2537 :   MachineFunction &MF = *MBB.getParent();
      85        2537 :   MachineRegisterInfo &MRI = MF.getRegInfo();
      86             : 
      87       12450 :   for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
      88        9913 :     MachineOperand &MO = I.getOperand(OpI);
      89             : 
      90             :     // There's nothing to be done on non-register operands.
      91        9913 :     if (!MO.isReg())
      92        3003 :       continue;
      93             : 
      94             :     DEBUG(dbgs() << "Converting operand: " << MO << '\n');
      95             :     assert(MO.isReg() && "Unsupported non-reg operand");
      96             : 
      97        6910 :     unsigned Reg = MO.getReg();
      98             :     // Physical registers don't need to be constrained.
      99        6910 :     if (TRI.isPhysicalRegister(Reg))
     100         171 :       continue;
     101             : 
     102             :     // Register operands with a value of 0 (e.g. predicate operands) don't need
     103             :     // to be constrained.
     104        6739 :     if (Reg == 0)
     105        1703 :       continue;
     106             : 
     107             :     // If the operand is a vreg, we should constrain its regclass, and only
     108             :     // insert COPYs if that's impossible.
     109             :     // constrainOperandRegClass does that for us.
     110        5036 :     MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
     111             :                                        Reg, OpI));
     112             : 
     113             :     // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
     114             :     // done.
     115        5036 :     if (MO.isUse()) {
     116        2977 :       int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
     117         276 :       if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
     118         143 :         I.tieOperands(DefIdx, OpI);
     119             :     }
     120             :   }
     121        2537 :   return true;
     122             : }
     123             : 
     124       14742 : bool llvm::isTriviallyDead(const MachineInstr &MI,
     125             :                            const MachineRegisterInfo &MRI) {
     126             :   // If we can move an instruction, we can remove it.  Otherwise, it has
     127             :   // a side-effect of some sort.
     128       14742 :   bool SawStore = false;
     129       14742 :   if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
     130             :     return false;
     131             : 
     132             :   // Instructions without side-effects are dead iff they only define dead vregs.
     133       15851 :   for (auto &MO : MI.operands()) {
     134       26594 :     if (!MO.isReg() || !MO.isDef())
     135         956 :       continue;
     136             : 
     137       12580 :     unsigned Reg = MO.getReg();
     138       23596 :     if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
     139             :         !MRI.use_nodbg_empty(Reg))
     140             :       return false;
     141             :   }
     142             :   return true;
     143             : }
     144             : 
     145          43 : void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
     146             :                               MachineOptimizationRemarkEmitter &MORE,
     147             :                               MachineOptimizationRemarkMissed &R) {
     148             :   MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
     149             : 
     150             :   // Print the function name explicitly if we don't have a debug location (which
     151             :   // makes the diagnostic less useful) or if we're going to emit a raw error.
     152          43 :   if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
     153         129 :     R << (" (in function: " + MF.getName() + ")").str();
     154             : 
     155          43 :   if (TPC.isGlobalISelAbortEnabled())
     156           1 :     report_fatal_error(R.getMsg());
     157             :   else
     158          42 :     MORE.emit(R);
     159          42 : }
     160             : 
     161          43 : void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
     162             :                               MachineOptimizationRemarkEmitter &MORE,
     163             :                               const char *PassName, StringRef Msg,
     164             :                               const MachineInstr &MI) {
     165             :   MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
     166         129 :                                     MI.getDebugLoc(), MI.getParent());
     167             :   R << Msg;
     168             :   // Printing MI is expensive;  only do it if expensive remarks are enabled.
     169          43 :   if (MORE.allowExtraAnalysis(PassName))
     170          48 :     R << ": " << ore::MNV("Inst", MI);
     171          43 :   reportGISelFailure(MF, TPC, MORE, R);
     172          42 : }
     173             : 
     174         374 : Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
     175             :                                            const MachineRegisterInfo &MRI) {
     176         374 :   MachineInstr *MI = MRI.getVRegDef(VReg);
     177         748 :   if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
     178             :     return None;
     179             : 
     180         416 :   if (MI->getOperand(1).isImm())
     181           5 :     return MI->getOperand(1).getImm();
     182             : 
     183         406 :   if (MI->getOperand(1).isCImm() &&
     184         203 :       MI->getOperand(1).getCImm()->getBitWidth() <= 64)
     185             :     return MI->getOperand(1).getCImm()->getSExtValue();
     186             : 
     187             :   return None;
     188             : }
     189             : 
     190           0 : const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
     191             :                                        const MachineRegisterInfo &MRI) {
     192           0 :   MachineInstr *MI = MRI.getVRegDef(VReg);
     193           0 :   if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
     194             :     return nullptr;
     195           0 :   return MI->getOperand(1).getFPImm();
     196             : }
     197             : 
     198        1094 : llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, unsigned Reg,
     199             :                                        const MachineRegisterInfo &MRI) {
     200        1094 :   auto *DefMI = MRI.getVRegDef(Reg);
     201        1094 :   auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
     202        1094 :   if (!DstTy.isValid())
     203             :     return nullptr;
     204        2203 :   while (DefMI->getOpcode() == TargetOpcode::COPY) {
     205          83 :     unsigned SrcReg = DefMI->getOperand(1).getReg();
     206          83 :     auto SrcTy = MRI.getType(SrcReg);
     207          83 :     if (!SrcTy.isValid() || SrcTy != DstTy)
     208             :       break;
     209           5 :     DefMI = MRI.getVRegDef(SrcReg);
     210             :   }
     211        2188 :   return DefMI->getOpcode() == Opcode ? DefMI : nullptr;
     212             : }

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