LCOV - code coverage report
Current view: top level - lib/CodeGen - InlineSpiller.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 546 566 96.5 %
Date: 2017-09-14 15:23:50 Functions: 31 33 93.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- InlineSpiller.cpp - Insert spills and restores inline --------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // The inline spiller modifies the machine function directly instead of
      11             : // inserting spills and restores in VirtRegMap.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "LiveRangeCalc.h"
      16             : #include "Spiller.h"
      17             : #include "SplitKit.h"
      18             : #include "llvm/ADT/ArrayRef.h"
      19             : #include "llvm/ADT/DenseMap.h"
      20             : #include "llvm/ADT/MapVector.h"
      21             : #include "llvm/ADT/None.h"
      22             : #include "llvm/ADT/STLExtras.h"
      23             : #include "llvm/ADT/SetVector.h"
      24             : #include "llvm/ADT/SmallPtrSet.h"
      25             : #include "llvm/ADT/SmallVector.h"
      26             : #include "llvm/ADT/Statistic.h"
      27             : #include "llvm/Analysis/AliasAnalysis.h"
      28             : #include "llvm/CodeGen/LiveInterval.h"
      29             : #include "llvm/CodeGen/LiveIntervalAnalysis.h"
      30             : #include "llvm/CodeGen/LiveRangeEdit.h"
      31             : #include "llvm/CodeGen/LiveStackAnalysis.h"
      32             : #include "llvm/CodeGen/MachineBasicBlock.h"
      33             : #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
      34             : #include "llvm/CodeGen/MachineDominators.h"
      35             : #include "llvm/CodeGen/MachineFunction.h"
      36             : #include "llvm/CodeGen/MachineFunctionPass.h"
      37             : #include "llvm/CodeGen/MachineInstr.h"
      38             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      39             : #include "llvm/CodeGen/MachineInstrBundle.h"
      40             : #include "llvm/CodeGen/MachineLoopInfo.h"
      41             : #include "llvm/CodeGen/MachineOperand.h"
      42             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      43             : #include "llvm/CodeGen/SlotIndexes.h"
      44             : #include "llvm/CodeGen/VirtRegMap.h"
      45             : #include "llvm/Support/BlockFrequency.h"
      46             : #include "llvm/Support/BranchProbability.h"
      47             : #include "llvm/Support/CommandLine.h"
      48             : #include "llvm/Support/Compiler.h"
      49             : #include "llvm/Support/Debug.h"
      50             : #include "llvm/Support/ErrorHandling.h"
      51             : #include "llvm/Support/raw_ostream.h"
      52             : #include "llvm/Target/TargetInstrInfo.h"
      53             : #include "llvm/Target/TargetOpcodes.h"
      54             : #include "llvm/Target/TargetRegisterInfo.h"
      55             : #include "llvm/Target/TargetSubtargetInfo.h"
      56             : #include <cassert>
      57             : #include <iterator>
      58             : #include <tuple>
      59             : #include <utility>
      60             : #include <vector>
      61             : 
      62             : using namespace llvm;
      63             : 
      64             : #define DEBUG_TYPE "regalloc"
      65             : 
      66             : STATISTIC(NumSpilledRanges,   "Number of spilled live ranges");
      67             : STATISTIC(NumSnippets,        "Number of spilled snippets");
      68             : STATISTIC(NumSpills,          "Number of spills inserted");
      69             : STATISTIC(NumSpillsRemoved,   "Number of spills removed");
      70             : STATISTIC(NumReloads,         "Number of reloads inserted");
      71             : STATISTIC(NumReloadsRemoved,  "Number of reloads removed");
      72             : STATISTIC(NumFolded,          "Number of folded stack accesses");
      73             : STATISTIC(NumFoldedLoads,     "Number of folded loads");
      74             : STATISTIC(NumRemats,          "Number of rematerialized defs for spilling");
      75             : 
      76       72306 : static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
      77      144612 :                                      cl::desc("Disable inline spill hoisting"));
      78             : 
      79             : namespace {
      80             : 
      81      674155 : class HoistSpillHelper : private LiveRangeEdit::Delegate {
      82             :   MachineFunction &MF;
      83             :   LiveIntervals &LIS;
      84             :   LiveStacks &LSS;
      85             :   AliasAnalysis *AA;
      86             :   MachineDominatorTree &MDT;
      87             :   MachineLoopInfo &Loops;
      88             :   VirtRegMap &VRM;
      89             :   MachineRegisterInfo &MRI;
      90             :   const TargetInstrInfo &TII;
      91             :   const TargetRegisterInfo &TRI;
      92             :   const MachineBlockFrequencyInfo &MBFI;
      93             : 
      94             :   InsertPointAnalysis IPA;
      95             : 
      96             :   // Map from StackSlot to its original register.
      97             :   DenseMap<int, unsigned> StackSlotToReg;
      98             : 
      99             :   // Map from pair of (StackSlot and Original VNI) to a set of spills which
     100             :   // have the same stackslot and have equal values defined by Original VNI.
     101             :   // These spills are mergeable and are hoist candiates.
     102             :   using MergeableSpillsMap =
     103             :       MapVector<std::pair<int, VNInfo *>, SmallPtrSet<MachineInstr *, 16>>;
     104             :   MergeableSpillsMap MergeableSpills;
     105             : 
     106             :   /// This is the map from original register to a set containing all its
     107             :   /// siblings. To hoist a spill to another BB, we need to find out a live
     108             :   /// sibling there and use it as the source of the new spill.
     109             :   DenseMap<unsigned, SmallSetVector<unsigned, 16>> Virt2SiblingsMap;
     110             : 
     111             :   bool isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI, MachineBasicBlock &BB,
     112             :                      unsigned &LiveReg);
     113             : 
     114             :   void rmRedundantSpills(
     115             :       SmallPtrSet<MachineInstr *, 16> &Spills,
     116             :       SmallVectorImpl<MachineInstr *> &SpillsToRm,
     117             :       DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
     118             : 
     119             :   void getVisitOrders(
     120             :       MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
     121             :       SmallVectorImpl<MachineDomTreeNode *> &Orders,
     122             :       SmallVectorImpl<MachineInstr *> &SpillsToRm,
     123             :       DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
     124             :       DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
     125             : 
     126             :   void runHoistSpills(unsigned OrigReg, VNInfo &OrigVNI,
     127             :                       SmallPtrSet<MachineInstr *, 16> &Spills,
     128             :                       SmallVectorImpl<MachineInstr *> &SpillsToRm,
     129             :                       DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns);
     130             : 
     131             : public:
     132      134834 :   HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf,
     133             :                    VirtRegMap &vrm)
     134      269668 :       : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
     135      134834 :         LSS(pass.getAnalysis<LiveStacks>()),
     136      269668 :         AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()),
     137      134834 :         MDT(pass.getAnalysis<MachineDominatorTree>()),
     138      134834 :         Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm),
     139      269668 :         MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
     140      134834 :         TRI(*mf.getSubtarget().getRegisterInfo()),
     141      134834 :         MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()),
     142     1887676 :         IPA(LIS, mf.getNumBlockIDs()) {}
     143             : 
     144             :   void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
     145             :                             unsigned Original);
     146             :   bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
     147             :   void hoistAllSpills();
     148             :   void LRE_DidCloneVirtReg(unsigned, unsigned) override;
     149             : };
     150             : 
     151             : class InlineSpiller : public Spiller {
     152             :   MachineFunction &MF;
     153             :   LiveIntervals &LIS;
     154             :   LiveStacks &LSS;
     155             :   AliasAnalysis *AA;
     156             :   MachineDominatorTree &MDT;
     157             :   MachineLoopInfo &Loops;
     158             :   VirtRegMap &VRM;
     159             :   MachineRegisterInfo &MRI;
     160             :   const TargetInstrInfo &TII;
     161             :   const TargetRegisterInfo &TRI;
     162             :   const MachineBlockFrequencyInfo &MBFI;
     163             : 
     164             :   // Variables that are valid during spill(), but used by multiple methods.
     165             :   LiveRangeEdit *Edit;
     166             :   LiveInterval *StackInt;
     167             :   int StackSlot;
     168             :   unsigned Original;
     169             : 
     170             :   // All registers to spill to StackSlot, including the main register.
     171             :   SmallVector<unsigned, 8> RegsToSpill;
     172             : 
     173             :   // All COPY instructions to/from snippets.
     174             :   // They are ignored since both operands refer to the same stack slot.
     175             :   SmallPtrSet<MachineInstr*, 8> SnippetCopies;
     176             : 
     177             :   // Values that failed to remat at some point.
     178             :   SmallPtrSet<VNInfo*, 8> UsedValues;
     179             : 
     180             :   // Dead defs generated during spilling.
     181             :   SmallVector<MachineInstr*, 8> DeadDefs;
     182             : 
     183             :   // Object records spills information and does the hoisting.
     184             :   HoistSpillHelper HSpiller;
     185             : 
     186      808986 :   ~InlineSpiller() override = default;
     187             : 
     188             : public:
     189      134834 :   InlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
     190      269668 :       : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
     191      134834 :         LSS(pass.getAnalysis<LiveStacks>()),
     192      269668 :         AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()),
     193      134834 :         MDT(pass.getAnalysis<MachineDominatorTree>()),
     194      134834 :         Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm),
     195      269668 :         MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
     196      134834 :         TRI(*mf.getSubtarget().getRegisterInfo()),
     197      134834 :         MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()),
     198     1887676 :         HSpiller(pass, mf, vrm) {}
     199             : 
     200             :   void spill(LiveRangeEdit &) override;
     201             :   void postOptimization() override;
     202             : 
     203             : private:
     204             :   bool isSnippet(const LiveInterval &SnipLI);
     205             :   void collectRegsToSpill();
     206             : 
     207       71868 :   bool isRegToSpill(unsigned Reg) { return is_contained(RegsToSpill, Reg); }
     208             : 
     209             :   bool isSibling(unsigned Reg);
     210             :   bool hoistSpillInsideBB(LiveInterval &SpillLI, MachineInstr &CopyMI);
     211             :   void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
     212             : 
     213             :   void markValueUsed(LiveInterval*, VNInfo*);
     214             :   bool reMaterializeFor(LiveInterval &, MachineInstr &MI);
     215             :   void reMaterializeAll();
     216             : 
     217             :   bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
     218             :   bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>>,
     219             :                          MachineInstr *LoadMI = nullptr);
     220             :   void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI);
     221             :   void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI);
     222             : 
     223             :   void spillAroundUses(unsigned Reg);
     224             :   void spillAll();
     225             : };
     226             : 
     227             : } // end anonymous namespace
     228             : 
     229             : Spiller::~Spiller() = default;
     230             : 
     231           0 : void Spiller::anchor() {}
     232             : 
     233      134834 : Spiller *llvm::createInlineSpiller(MachineFunctionPass &pass,
     234             :                                    MachineFunction &mf,
     235             :                                    VirtRegMap &vrm) {
     236      134834 :   return new InlineSpiller(pass, mf, vrm);
     237             : }
     238             : 
     239             : //===----------------------------------------------------------------------===//
     240             : //                                Snippets
     241             : //===----------------------------------------------------------------------===//
     242             : 
     243             : // When spilling a virtual register, we also spill any snippets it is connected
     244             : // to. The snippets are small live ranges that only have a single real use,
     245             : // leftovers from live range splitting. Spilling them enables memory operand
     246             : // folding or tightens the live range around the single use.
     247             : //
     248             : // This minimizes register pressure and maximizes the store-to-load distance for
     249             : // spill slots which can be important in tight loops.
     250             : 
     251             : /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
     252             : /// otherwise return 0.
     253             : static unsigned isFullCopyOf(const MachineInstr &MI, unsigned Reg) {
     254       96958 :   if (!MI.isFullCopy())
     255             :     return 0;
     256       96958 :   if (MI.getOperand(0).getReg() == Reg)
     257       31708 :     return MI.getOperand(1).getReg();
     258       65250 :   if (MI.getOperand(1).getReg() == Reg)
     259       25869 :     return MI.getOperand(0).getReg();
     260             :   return 0;
     261             : }
     262             : 
     263             : /// isSnippet - Identify if a live interval is a snippet that should be spilled.
     264             : /// It is assumed that SnipLI is a virtual register with the same original as
     265             : /// Edit->getReg().
     266       30809 : bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
     267       61618 :   unsigned Reg = Edit->getReg();
     268             : 
     269             :   // A snippet is a tiny live range with only a single instruction using it
     270             :   // besides copies to/from Reg or spills/fills. We accept:
     271             :   //
     272             :   //   %snip = COPY %Reg / FILL fi#
     273             :   //   %snip = USE %snip
     274             :   //   %Reg = COPY %snip / SPILL %snip, fi#
     275             :   //
     276       61618 :   if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
     277             :     return false;
     278             : 
     279       12662 :   MachineInstr *UseMI = nullptr;
     280             : 
     281             :   // Check that all uses satisfy our criteria.
     282             :   for (MachineRegisterInfo::reg_instr_nodbg_iterator
     283       12662 :        RI = MRI.reg_instr_nodbg_begin(SnipLI.reg),
     284       45676 :        E = MRI.reg_instr_nodbg_end(); RI != E; ) {
     285       94131 :     MachineInstr &MI = *RI++;
     286             : 
     287             :     // Allow copies to/from Reg.
     288        6266 :     if (isFullCopyOf(MI, Reg))
     289       13397 :       continue;
     290             : 
     291             :     // Allow stack slot loads.
     292             :     int FI;
     293       25520 :     if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
     294         409 :       continue;
     295             : 
     296             :     // Allow stack slot stores.
     297       25909 :     if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
     298         456 :       continue;
     299             : 
     300             :     // Allow a single additional instruction.
     301       24246 :     if (UseMI && &MI != UseMI)
     302       11025 :       return false;
     303       13221 :     UseMI = &MI;
     304             :   }
     305             :   return true;
     306             : }
     307             : 
     308             : /// collectRegsToSpill - Collect live range snippets that only have a single
     309             : /// real use.
     310       29403 : void InlineSpiller::collectRegsToSpill() {
     311       58806 :   unsigned Reg = Edit->getReg();
     312             : 
     313             :   // Main register always spills.
     314       29403 :   RegsToSpill.assign(1, Reg);
     315       29403 :   SnippetCopies.clear();
     316             : 
     317             :   // Snippets all have the same original, so there can't be any for an original
     318             :   // register.
     319       29403 :   if (Original == Reg)
     320       12142 :     return;
     321             : 
     322             :   for (MachineRegisterInfo::reg_instr_iterator
     323       97590 :        RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) {
     324      189204 :     MachineInstr &MI = *RI++;
     325      126136 :     unsigned SnipReg = isFullCopyOf(MI, Reg);
     326      126136 :     if (!isSibling(SnipReg))
     327       93722 :       continue;
     328       30809 :     LiveInterval &SnipLI = LIS.getInterval(SnipReg);
     329       59981 :     if (!isSnippet(SnipLI))
     330       29172 :       continue;
     331        1637 :     SnippetCopies.insert(&MI);
     332        3274 :     if (isRegToSpill(SnipReg))
     333          32 :       continue;
     334        1605 :     RegsToSpill.push_back(SnipReg);
     335             :     DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
     336        1605 :     ++NumSnippets;
     337             :   }
     338             : }
     339             : 
     340             : bool InlineSpiller::isSibling(unsigned Reg) {
     341      162111 :   return TargetRegisterInfo::isVirtualRegister(Reg) &&
     342      109320 :            VRM.getOriginal(Reg) == Original;
     343             : }
     344             : 
     345             : /// It is beneficial to spill to earlier place in the same BB in case
     346             : /// as follows:
     347             : /// There is an alternative def earlier in the same MBB.
     348             : /// Hoist the spill as far as possible in SpillMBB. This can ease
     349             : /// register pressure:
     350             : ///
     351             : ///   x = def
     352             : ///   y = use x
     353             : ///   s = copy x
     354             : ///
     355             : /// Hoisting the spill of s to immediately after the def removes the
     356             : /// interference between x and y:
     357             : ///
     358             : ///   x = def
     359             : ///   spill x
     360             : ///   y = use x<kill>
     361             : ///
     362             : /// This hoist only helps when the copy kills its source.
     363             : ///
     364        7792 : bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
     365             :                                        MachineInstr &CopyMI) {
     366       15584 :   SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
     367             : #ifndef NDEBUG
     368             :   VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
     369             :   assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
     370             : #endif
     371             : 
     372        7792 :   unsigned SrcReg = CopyMI.getOperand(1).getReg();
     373        7792 :   LiveInterval &SrcLI = LIS.getInterval(SrcReg);
     374       15584 :   VNInfo *SrcVNI = SrcLI.getVNInfoAt(Idx);
     375        7792 :   LiveQueryResult SrcQ = SrcLI.Query(Idx);
     376       15584 :   MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(SrcVNI->def);
     377        7792 :   if (DefMBB != CopyMI.getParent() || !SrcQ.isKill())
     378             :     return false;
     379             : 
     380             :   // Conservatively extend the stack slot range to the range of the original
     381             :   // value. We may be able to do better with stack slot coloring by being more
     382             :   // careful here.
     383             :   assert(StackInt && "No stack slot assigned yet.");
     384        3555 :   LiveInterval &OrigLI = LIS.getInterval(Original);
     385        7110 :   VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
     386        7110 :   StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
     387             :   DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
     388             :                << *StackInt << '\n');
     389             : 
     390             :   // We are going to spill SrcVNI immediately after its def, so clear out
     391             :   // any later spills of the same value.
     392        3555 :   eliminateRedundantSpills(SrcLI, SrcVNI);
     393             : 
     394        7110 :   MachineBasicBlock *MBB = LIS.getMBBFromIndex(SrcVNI->def);
     395        3555 :   MachineBasicBlock::iterator MII;
     396        3555 :   if (SrcVNI->isPHIDef())
     397         305 :     MII = MBB->SkipPHIsLabelsAndDebug(MBB->begin());
     398             :   else {
     399        6500 :     MachineInstr *DefMI = LIS.getInstructionFromIndex(SrcVNI->def);
     400             :     assert(DefMI && "Defining instruction disappeared");
     401        3250 :     MII = DefMI;
     402             :     ++MII;
     403             :   }
     404             :   // Insert spill without kill flag immediately after def.
     405        7110 :   TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
     406        3555 :                           MRI.getRegClass(SrcReg), &TRI);
     407        3555 :   --MII; // Point to store instruction.
     408       10665 :   LIS.InsertMachineInstrInMaps(*MII);
     409             :   DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII);
     410             : 
     411        7110 :   HSpiller.addToMergeableSpills(*MII, StackSlot, Original);
     412        3555 :   ++NumSpills;
     413             :   return true;
     414             : }
     415             : 
     416             : /// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
     417             : /// redundant spills of this value in SLI.reg and sibling copies.
     418       12479 : void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
     419             :   assert(VNI && "Missing value");
     420       24958 :   SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
     421       24958 :   WorkList.push_back(std::make_pair(&SLI, VNI));
     422             :   assert(StackInt && "No stack slot assigned yet.");
     423             : 
     424             :   do {
     425             :     LiveInterval *LI;
     426       52743 :     std::tie(LI, VNI) = WorkList.pop_back_val();
     427       17581 :     unsigned Reg = LI->reg;
     428             :     DEBUG(dbgs() << "Checking redundant spills for "
     429             :                  << VNI->id << '@' << VNI->def << " in " << *LI << '\n');
     430             : 
     431             :     // Regs to spill are taken care of.
     432       17581 :     if (isRegToSpill(Reg))
     433        3556 :       continue;
     434             : 
     435             :     // Add all of VNI's live range to StackInt.
     436       28050 :     StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
     437             :     DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
     438             : 
     439             :     // Find all spills and copies of VNI.
     440             :     for (MachineRegisterInfo::use_instr_nodbg_iterator
     441       28050 :          UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
     442       87716 :          UI != E; ) {
     443      221073 :       MachineInstr &MI = *UI++;
     444       73691 :       if (!MI.isCopy() && !MI.mayStore())
     445       85519 :         continue;
     446      110188 :       SlotIndex Idx = LIS.getInstructionIndex(MI);
     447      110188 :       if (LI->getVNInfoAt(Idx) != VNI)
     448       36831 :         continue;
     449             : 
     450             :       // Follow sibling copies down the dominator tree.
     451       11494 :       if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
     452       16596 :         if (isSibling(DstReg)) {
     453        5102 :            LiveInterval &DstLI = LIS.getInterval(DstReg);
     454       15306 :            VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
     455             :            assert(DstVNI && "Missing defined value");
     456             :            assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
     457       10204 :            WorkList.push_back(std::make_pair(&DstLI, DstVNI));
     458             :         }
     459       11494 :         continue;
     460             :       }
     461             : 
     462             :       // Erase spills.
     463             :       int FI;
     464        6769 :       if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
     465             :         DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI);
     466             :         // eliminateDeadDefs won't normally remove stores, so switch opcode.
     467         834 :         MI.setDesc(TII.get(TargetOpcode::KILL));
     468         278 :         DeadDefs.push_back(&MI);
     469         278 :         ++NumSpillsRemoved;
     470         278 :         if (HSpiller.rmFromMergeableSpills(MI, StackSlot))
     471             :           --NumSpills;
     472             :       }
     473             :     }
     474       17581 :   } while (!WorkList.empty());
     475       12479 : }
     476             : 
     477             : //===----------------------------------------------------------------------===//
     478             : //                            Rematerialization
     479             : //===----------------------------------------------------------------------===//
     480             : 
     481             : /// markValueUsed - Remember that VNI failed to rematerialize, so its defining
     482             : /// instruction cannot be eliminated. See through snippet copies
     483        1237 : void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
     484        2474 :   SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
     485        2474 :   WorkList.push_back(std::make_pair(LI, VNI));
     486             :   do {
     487       10266 :     std::tie(LI, VNI) = WorkList.pop_back_val();
     488        3422 :     if (!UsedValues.insert(VNI).second)
     489         558 :       continue;
     490             : 
     491        5728 :     if (VNI->isPHIDef()) {
     492        1956 :       MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
     493        3958 :       for (MachineBasicBlock *P : MBB->predecessors()) {
     494        4004 :         VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(P));
     495        2002 :         if (PVNI)
     496        4004 :           WorkList.push_back(std::make_pair(LI, PVNI));
     497             :       }
     498         978 :       continue;
     499             :     }
     500             : 
     501             :     // Follow snippet copies.
     502        3772 :     MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
     503        1886 :     if (!SnippetCopies.count(MI))
     504        1703 :       continue;
     505         183 :     LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
     506             :     assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
     507         549 :     VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
     508             :     assert(SnipVNI && "Snippet undefined before copy");
     509         366 :     WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
     510        3422 :   } while (!WorkList.empty());
     511        1237 : }
     512             : 
     513             : /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
     514       49375 : bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
     515             :   // Analyze instruction
     516       98750 :   SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops;
     517             :   MIBundleOperands::VirtRegInfo RI =
     518       49375 :       MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
     519             : 
     520       49375 :   if (!RI.Reads)
     521             :     return false;
     522             : 
     523       94590 :   SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
     524       94590 :   VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
     525             : 
     526       31530 :   if (!ParentVNI) {
     527             :     DEBUG(dbgs() << "\tadding <undef> flags: ");
     528           0 :     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     529           0 :       MachineOperand &MO = MI.getOperand(i);
     530           0 :       if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
     531             :         MO.setIsUndef();
     532             :     }
     533             :     DEBUG(dbgs() << UseIdx << '\t' << MI);
     534             :     return true;
     535             :   }
     536             : 
     537       31530 :   if (SnippetCopies.count(&MI))
     538             :     return false;
     539             : 
     540       30719 :   LiveInterval &OrigLI = LIS.getInterval(Original);
     541       61438 :   VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx);
     542       30719 :   LiveRangeEdit::Remat RM(ParentVNI);
     543       61438 :   RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def);
     544             : 
     545       30719 :   if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx, false)) {
     546        1055 :     markValueUsed(&VirtReg, ParentVNI);
     547             :     DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI);
     548        1055 :     return false;
     549             :   }
     550             : 
     551             :   // If the instruction also writes VirtReg.reg, it had better not require the
     552             :   // same register for uses and defs.
     553       29664 :   if (RI.Tied) {
     554         182 :     markValueUsed(&VirtReg, ParentVNI);
     555             :     DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI);
     556         182 :     return false;
     557             :   }
     558             : 
     559             :   // Before rematerializing into a register for a single instruction, try to
     560             :   // fold a load into the instruction. That avoids allocating a new register.
     561       64245 :   if (RM.OrigMI->canFoldAsLoad() &&
     562       40044 :       foldMemoryOperand(Ops, RM.OrigMI)) {
     563        3880 :     Edit->markRematerialized(RM.ParentVNI);
     564        1940 :     ++NumFoldedLoads;
     565        1940 :     return true;
     566             :   }
     567             : 
     568             :   // Allocate a new register for the remat.
     569       27542 :   unsigned NewVReg = Edit->createFrom(Original);
     570             : 
     571             :   // Finally we can rematerialize OrigMI before MI.
     572             :   SlotIndex DefIdx =
     573       55084 :       Edit->rematerializeAt(*MI.getParent(), MI, NewVReg, RM, TRI);
     574             : 
     575             :   // We take the DebugLoc from MI, since OrigMI may be attributed to a
     576             :   // different source location.
     577       55084 :   auto *NewMI = LIS.getInstructionFromIndex(DefIdx);
     578      110168 :   NewMI->setDebugLoc(MI.getDebugLoc());
     579             : 
     580             :   (void)DefIdx;
     581             :   DEBUG(dbgs() << "\tremat:  " << DefIdx << '\t'
     582             :                << *LIS.getInstructionFromIndex(DefIdx));
     583             : 
     584             :   // Replace operands
     585      110178 :   for (const auto &OpPair : Ops) {
     586       55104 :     MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
     587       55104 :     if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
     588       27552 :       MO.setReg(NewVReg);
     589             :       MO.setIsKill();
     590             :     }
     591             :   }
     592             :   DEBUG(dbgs() << "\t        " << UseIdx << '\t' << MI << '\n');
     593             : 
     594             :   ++NumRemats;
     595             :   return true;
     596             : }
     597             : 
     598             : /// reMaterializeAll - Try to rematerialize as many uses as possible,
     599             : /// and trim the live ranges after.
     600       29403 : void InlineSpiller::reMaterializeAll() {
     601       29403 :   if (!Edit->anyRematerializable(AA))
     602             :     return;
     603             : 
     604       15334 :   UsedValues.clear();
     605             : 
     606             :   // Try to remat before all uses of snippets.
     607       15334 :   bool anyRemat = false;
     608       62136 :   for (unsigned Reg : RegsToSpill) {
     609       16134 :     LiveInterval &LI = LIS.getInterval(Reg);
     610             :     for (MachineRegisterInfo::reg_bundle_iterator
     611       48402 :            RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
     612       65509 :          RegI != E; ) {
     613      148125 :       MachineInstr &MI = *RegI++;
     614             : 
     615             :       // Debug values are not allowed to affect codegen.
     616       49375 :       if (MI.isDebugValue())
     617           0 :         continue;
     618             : 
     619       49375 :       anyRemat |= reMaterializeFor(LI, MI);
     620             :     }
     621             :   }
     622       15334 :   if (!anyRemat)
     623             :     return;
     624             : 
     625             :   // Remove any values that were completely rematted.
     626       59032 :   for (unsigned Reg : RegsToSpill) {
     627       15247 :     LiveInterval &LI = LIS.getInterval(Reg);
     628       62975 :     for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
     629       32481 :          I != E; ++I) {
     630       17234 :       VNInfo *VNI = *I;
     631       34468 :       if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
     632        2278 :         continue;
     633       32190 :       MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
     634       16095 :       MI->addRegisterDead(Reg, &TRI);
     635       16095 :       if (!MI->allDefsAreDead())
     636           0 :         continue;
     637             :       DEBUG(dbgs() << "All defs dead: " << *MI);
     638       16095 :       DeadDefs.push_back(MI);
     639             :     }
     640             :   }
     641             : 
     642             :   // Eliminate dead code after remat. Note that some snippet copies may be
     643             :   // deleted here.
     644       14595 :   if (DeadDefs.empty())
     645             :     return;
     646             :   DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
     647       29098 :   Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
     648             : 
     649             :   // LiveRangeEdit::eliminateDeadDef is used to remove dead define instructions
     650             :   // after rematerialization.  To remove a VNI for a vreg from its LiveInterval,
     651             :   // LiveIntervals::removeVRegDefAt is used. However, after non-PHI VNIs are all
     652             :   // removed, PHI VNI are still left in the LiveInterval.
     653             :   // So to get rid of unused reg, we need to check whether it has non-dbg
     654             :   // reference instead of whether it has non-empty interval.
     655       14549 :   unsigned ResultPos = 0;
     656       58816 :   for (unsigned Reg : RegsToSpill) {
     657       45506 :     if (MRI.reg_nodbg_empty(Reg)) {
     658       15168 :       Edit->eraseVirtReg(Reg);
     659       15168 :       continue;
     660             :     }
     661             : 
     662             :     assert(LIS.hasInterval(Reg) &&
     663             :            (!LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) &&
     664             :            "Empty and not used live-range?!");
     665             : 
     666           2 :     RegsToSpill[ResultPos++] = Reg;
     667             :   }
     668       43647 :   RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());
     669             :   DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n");
     670             : }
     671             : 
     672             : //===----------------------------------------------------------------------===//
     673             : //                                 Spilling
     674             : //===----------------------------------------------------------------------===//
     675             : 
     676             : /// If MI is a load or store of StackSlot, it can be removed.
     677       49756 : bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
     678       49756 :   int FI = 0;
     679       49756 :   unsigned InstrReg = TII.isLoadFromStackSlot(*MI, FI);
     680       49756 :   bool IsLoad = InstrReg;
     681       49756 :   if (!IsLoad)
     682       48748 :     InstrReg = TII.isStoreToStackSlot(*MI, FI);
     683             : 
     684             :   // We have a stack access. Is it the right register and slot?
     685       49756 :   if (InstrReg != Reg || FI != StackSlot)
     686             :     return false;
     687             : 
     688        1002 :   if (!IsLoad)
     689         529 :     HSpiller.rmFromMergeableSpills(*MI, StackSlot);
     690             : 
     691             :   DEBUG(dbgs() << "Coalescing stack access: " << *MI);
     692        2004 :   LIS.RemoveMachineInstrFromMaps(*MI);
     693        1002 :   MI->eraseFromParent();
     694             : 
     695             :   if (IsLoad) {
     696             :     ++NumReloadsRemoved;
     697             :     --NumReloads;
     698             :   } else {
     699             :     ++NumSpillsRemoved;
     700             :     --NumSpills;
     701             :   }
     702             : 
     703        1002 :   return true;
     704             : }
     705             : 
     706             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     707             : LLVM_DUMP_METHOD
     708             : // Dump the range of instructions from B to E with their slot indexes.
     709             : static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
     710             :                                                MachineBasicBlock::iterator E,
     711             :                                                LiveIntervals const &LIS,
     712             :                                                const char *const header,
     713             :                                                unsigned VReg =0) {
     714             :   char NextLine = '\n';
     715             :   char SlotIndent = '\t';
     716             : 
     717             :   if (std::next(B) == E) {
     718             :     NextLine = ' ';
     719             :     SlotIndent = ' ';
     720             :   }
     721             : 
     722             :   dbgs() << '\t' << header << ": " << NextLine;
     723             : 
     724             :   for (MachineBasicBlock::iterator I = B; I != E; ++I) {
     725             :     SlotIndex Idx = LIS.getInstructionIndex(*I).getRegSlot();
     726             : 
     727             :     // If a register was passed in and this instruction has it as a
     728             :     // destination that is marked as an early clobber, print the
     729             :     // early-clobber slot index.
     730             :     if (VReg) {
     731             :       MachineOperand *MO = I->findRegisterDefOperand(VReg);
     732             :       if (MO && MO->isEarlyClobber())
     733             :         Idx = Idx.getRegSlot(true);
     734             :     }
     735             : 
     736             :     dbgs() << SlotIndent << Idx << '\t' << *I;
     737             :   }
     738             : }
     739             : #endif
     740             : 
     741             : /// foldMemoryOperand - Try folding stack slot references in Ops into their
     742             : /// instructions.
     743             : ///
     744             : /// @param Ops    Operand indices from analyzeVirtReg().
     745             : /// @param LoadMI Load instruction to use instead of stack slot when non-null.
     746             : /// @return       True on success.
     747       50480 : bool InlineSpiller::
     748             : foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
     749             :                   MachineInstr *LoadMI) {
     750       50480 :   if (Ops.empty())
     751             :     return false;
     752             :   // Don't attempt folding in bundles.
     753       50480 :   MachineInstr *MI = Ops.front().first;
     754      100954 :   if (Ops.back().first != MI || MI->isBundled())
     755             :     return false;
     756             : 
     757       50474 :   bool WasCopy = MI->isCopy();
     758       50474 :   unsigned ImpReg = 0;
     759             : 
     760             :   // Spill subregs if the target allows it.
     761             :   // We always want to spill subregs for stackmap/patchpoint pseudos.
     762       56918 :   bool SpillSubRegs = TII.isSubregFoldable() ||
     763       12888 :                       MI->getOpcode() == TargetOpcode::STATEPOINT ||
     764       63326 :                       MI->getOpcode() == TargetOpcode::PATCHPOINT ||
     765       56882 :                       MI->getOpcode() == TargetOpcode::STACKMAP;
     766             : 
     767             :   // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
     768             :   // operands.
     769       50474 :   SmallVector<unsigned, 8> FoldOps;
     770      151910 :   for (const auto &OpPair : Ops) {
     771       51044 :     unsigned Idx = OpPair.second;
     772             :     assert(MI == OpPair.first && "Instruction conflict during operand folding");
     773      102088 :     MachineOperand &MO = MI->getOperand(Idx);
     774       51051 :     if (MO.isImplicit()) {
     775           7 :       ImpReg = MO.getReg();
     776           7 :       continue;
     777             :     }
     778             : 
     779       57454 :     if (!SpillSubRegs && MO.getSubReg())
     780          82 :       return false;
     781             :     // We cannot fold a load instruction into a def.
     782       56243 :     if (LoadMI && MO.isDef())
     783             :       return false;
     784             :     // Tied use operands should not be passed to foldMemoryOperand.
     785       50955 :     if (!MI->isRegTiedToDefOperand(Idx))
     786       50453 :       FoldOps.push_back(Idx);
     787             :   }
     788             : 
     789             :   // If we only have implicit uses, we won't be able to fold that.
     790             :   // Moreover, TargetInstrInfo::foldMemoryOperand will assert if we try!
     791       50392 :   if (FoldOps.empty())
     792             :     return false;
     793             : 
     794       50385 :   MachineInstrSpan MIS(MI);
     795             : 
     796             :   MachineInstr *FoldMI =
     797      151155 :       LoadMI ? TII.foldMemoryOperand(*MI, FoldOps, *LoadMI, &LIS)
     798      140593 :              : TII.foldMemoryOperand(*MI, FoldOps, StackSlot, &LIS);
     799       50385 :   if (!FoldMI)
     800             :     return false;
     801             : 
     802             :   // Remove LIS for any dead defs in the original MI not in FoldMI.
     803      118810 :   for (MIBundleOperands MO(*MI); MO.isValid(); ++MO) {
     804      165008 :     if (!MO->isReg())
     805       83493 :       continue;
     806       81312 :     unsigned Reg = MO->getReg();
     807      246237 :     if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) ||
     808       39812 :         MRI.isReserved(Reg)) {
     809       63825 :       continue;
     810             :     }
     811             :     // Skip non-Defs, including undef uses and internal reads.
     812       42858 :     if (MO->isUse())
     813        7884 :       continue;
     814             :     MIBundleOperands::PhysRegInfo RI =
     815        9603 :         MIBundleOperands(*FoldMI).analyzePhysReg(Reg, &TRI);
     816        9603 :     if (RI.FullyDefined)
     817        9400 :       continue;
     818             :     // FoldMI does not define this physreg. Remove the LI segment.
     819             :     assert(MO->isDead() && "Cannot fold physreg def");
     820         609 :     SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
     821         203 :     LIS.removePhysRegDefAt(Reg, Idx);
     822             :   }
     823             : 
     824             :   int FI;
     825       36306 :   if (TII.isStoreToStackSlot(*MI, FI) &&
     826           2 :       HSpiller.rmFromMergeableSpills(*MI, FI))
     827             :     --NumSpills;
     828       72612 :   LIS.ReplaceMachineInstrInMaps(*MI, *FoldMI);
     829       36306 :   MI->eraseFromParent();
     830             : 
     831             :   // Insert any new instructions other than FoldMI into the LIS maps.
     832             :   assert(!MIS.empty() && "Unexpected empty span of instructions!");
     833      145224 :   for (MachineInstr &MI : MIS)
     834       36306 :     if (&MI != FoldMI)
     835           0 :       LIS.InsertMachineInstrInMaps(MI);
     836             : 
     837             :   // TII.foldMemoryOperand may have left some implicit operands on the
     838             :   // instruction.  Strip them.
     839       36306 :   if (ImpReg)
     840           0 :     for (unsigned i = FoldMI->getNumOperands(); i; --i) {
     841           0 :       MachineOperand &MO = FoldMI->getOperand(i - 1);
     842           0 :       if (!MO.isReg() || !MO.isImplicit())
     843             :         break;
     844           0 :       if (MO.getReg() == ImpReg)
     845           0 :         FoldMI->RemoveOperand(i - 1);
     846             :     }
     847             : 
     848             :   DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,
     849             :                                            "folded"));
     850             : 
     851       36306 :   if (!WasCopy)
     852             :     ++NumFolded;
     853       29247 :   else if (Ops.front().second == 0) {
     854       11687 :     ++NumSpills;
     855       11687 :     HSpiller.addToMergeableSpills(*FoldMI, StackSlot, Original);
     856             :   } else
     857             :     ++NumReloads;
     858             :   return true;
     859             : }
     860             : 
     861        6652 : void InlineSpiller::insertReload(unsigned NewVReg,
     862             :                                  SlotIndex Idx,
     863             :                                  MachineBasicBlock::iterator MI) {
     864        6652 :   MachineBasicBlock &MBB = *MI->getParent();
     865             : 
     866        6652 :   MachineInstrSpan MIS(MI);
     867       13304 :   TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
     868        6652 :                            MRI.getRegClass(NewVReg), &TRI);
     869             : 
     870        6652 :   LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
     871             : 
     872             :   DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",
     873             :                                            NewVReg));
     874        6652 :   ++NumReloads;
     875        6652 : }
     876             : 
     877             : /// Check if \p Def fully defines a VReg with an undefined value.
     878             : /// If that's the case, that means the value of VReg is actually
     879             : /// not relevant.
     880             : static bool isFullUndefDef(const MachineInstr &Def) {
     881        4485 :   if (!Def.isImplicitDef())
     882             :     return false;
     883             :   assert(Def.getNumOperands() == 1 &&
     884             :          "Implicit def with more than one definition");
     885             :   // We can say that the VReg defined by Def is undef, only if it is
     886             :   // fully defined by Def. Otherwise, some of the lanes may not be
     887             :   // undef and the value of the VReg matters.
     888          24 :   return !Def.getOperand(0).getSubReg();
     889             : }
     890             : 
     891             : /// insertSpill - Insert a spill of NewVReg after MI.
     892        4485 : void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
     893             :                                  MachineBasicBlock::iterator MI) {
     894        4485 :   MachineBasicBlock &MBB = *MI->getParent();
     895             : 
     896        4485 :   MachineInstrSpan MIS(MI);
     897        4485 :   bool IsRealSpill = true;
     898        4497 :   if (isFullUndefDef(*MI)) {
     899             :     // Don't spill undef value.
     900             :     // Anything works for undef, in particular keeping the memory
     901             :     // uninitialized is a viable option and it saves code size and
     902             :     // run time.
     903          72 :     BuildMI(MBB, std::next(MI), MI->getDebugLoc(), TII.get(TargetOpcode::KILL))
     904          12 :         .addReg(NewVReg, getKillRegState(isKill));
     905          12 :     IsRealSpill = false;
     906             :   } else
     907       13419 :     TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot,
     908        4473 :                             MRI.getRegClass(NewVReg), &TRI);
     909             : 
     910        8970 :   LIS.InsertMachineInstrRangeInMaps(std::next(MI), MIS.end());
     911             : 
     912             :   DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,
     913             :                                            "spill"));
     914        4485 :   ++NumSpills;
     915        4485 :   if (IsRealSpill)
     916       13419 :     HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original);
     917        4485 : }
     918             : 
     919             : /// spillAroundUses - insert spill code around each use of Reg.
     920       15840 : void InlineSpiller::spillAroundUses(unsigned Reg) {
     921             :   DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
     922       15840 :   LiveInterval &OldLI = LIS.getInterval(Reg);
     923             : 
     924             :   // Iterate over instructions using Reg.
     925             :   for (MachineRegisterInfo::reg_bundle_iterator
     926       47520 :        RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
     927       67614 :        RegI != E; ) {
     928      155322 :     MachineInstr *MI = &*(RegI++);
     929             : 
     930             :     // Debug values are not allowed to affect codegen.
     931      103548 :     if (MI->isDebugValue()) {
     932             :       // Modify DBG_VALUE now that the value is in a spill slot.
     933           0 :       MachineBasicBlock *MBB = MI->getParent();
     934             :       DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI);
     935           0 :       buildDbgValueForSpill(*MBB, MI, *MI, StackSlot);
     936           0 :       MBB->erase(MI);
     937       40941 :       continue;
     938             :     }
     939             : 
     940             :     // Ignore copies to/from snippets. We'll delete them.
     941       51774 :     if (SnippetCopies.count(MI))
     942        2018 :       continue;
     943             : 
     944             :     // Stack slot accesses may coalesce away.
     945       49756 :     if (coalesceStackAccess(MI, Reg))
     946        1002 :       continue;
     947             : 
     948             :     // Analyze instruction.
     949       59587 :     SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
     950             :     MIBundleOperands::VirtRegInfo RI =
     951       97508 :         MIBundleOperands(*MI).analyzeVirtReg(Reg, &Ops);
     952             : 
     953             :     // Find the slot index where this instruction reads and writes OldLI.
     954             :     // This is usually the def slot, except for tied early clobbers.
     955      146262 :     SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
     956      126398 :     if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
     957       28890 :       if (SlotIndex::isSameInstr(Idx, VNI->def))
     958          12 :         Idx = VNI->def;
     959             : 
     960             :     // Check for a sibling copy.
     961       81643 :     unsigned SibReg = isFullCopyOf(*MI, Reg);
     962       49605 :     if (SibReg && isSibling(SibReg)) {
     963             :       // This may actually be a copy between snippets.
     964       16716 :       if (isRegToSpill(SibReg)) {
     965             :         DEBUG(dbgs() << "Found new snippet copy: " << *MI);
     966           0 :         SnippetCopies.insert(MI);
     967           0 :         continue;
     968             :       }
     969       16716 :       if (RI.Writes) {
     970       11347 :         if (hoistSpillInsideBB(OldLI, *MI)) {
     971             :           // This COPY is now dead, the value is already in the stack slot.
     972        7110 :           MI->getOperand(0).setIsDead();
     973        3555 :           DeadDefs.push_back(MI);
     974        3555 :           continue;
     975             :         }
     976             :       } else {
     977             :         // This is a reload for a sib-reg copy. Drop spills downstream.
     978        8924 :         LiveInterval &SibLI = LIS.getInterval(SibReg);
     979       17848 :         eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
     980             :         // The COPY will fold to a reload below.
     981             :       }
     982             :     }
     983             : 
     984             :     // Attempt to fold memory ops.
     985       45199 :     if (foldMemoryOperand(Ops))
     986       34366 :       continue;
     987             : 
     988             :     // Create a new virtual register for spill/fill.
     989             :     // FIXME: Infer regclass from instruction alone.
     990       10833 :     unsigned NewVReg = Edit->createFrom(Reg);
     991             : 
     992       10833 :     if (RI.Reads)
     993       13304 :       insertReload(NewVReg, Idx, MI);
     994             : 
     995             :     // Rewrite instruction operands.
     996       10833 :     bool hasLiveDef = false;
     997       43680 :     for (const auto &OpPair : Ops) {
     998       22362 :       MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
     999       11181 :       MO.setReg(NewVReg);
    1000       11181 :       if (MO.isUse()) {
    1001        6685 :         if (!OpPair.first->isRegTiedToDefOperand(OpPair.second))
    1002             :           MO.setIsKill();
    1003             :       } else {
    1004        4496 :         if (!MO.isDead())
    1005        4488 :           hasLiveDef = true;
    1006             :       }
    1007             :     }
    1008             :     DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n');
    1009             : 
    1010             :     // FIXME: Use a second vreg if instruction has no tied ops.
    1011       10833 :     if (RI.Writes)
    1012        4493 :       if (hasLiveDef)
    1013        8970 :         insertSpill(NewVReg, true, MI);
    1014             :   }
    1015       15840 : }
    1016             : 
    1017             : /// spillAll - Spill all registers remaining after rematerialization.
    1018       14855 : void InlineSpiller::spillAll() {
    1019             :   // Update LiveStacks now that we are committed to spilling.
    1020       14855 :   if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
    1021       12819 :     StackSlot = VRM.assignVirt2StackSlot(Original);
    1022       25638 :     StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
    1023       38457 :     StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator());
    1024             :   } else
    1025        4072 :     StackInt = &LSS.getInterval(StackSlot);
    1026             : 
    1027       29710 :   if (Original != Edit->getReg())
    1028       18044 :     VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
    1029             : 
    1030             :   assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
    1031       60405 :   for (unsigned Reg : RegsToSpill)
    1032       31680 :     StackInt->MergeSegmentsInAsValue(LIS.getInterval(Reg),
    1033             :                                      StackInt->getValNumInfo(0));
    1034             :   DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
    1035             : 
    1036             :   // Spill around uses of all RegsToSpill.
    1037       60405 :   for (unsigned Reg : RegsToSpill)
    1038       15840 :     spillAroundUses(Reg);
    1039             : 
    1040             :   // Hoisted spills may cause dead code.
    1041       14855 :   if (!DeadDefs.empty()) {
    1042             :     DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
    1043        7238 :     Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
    1044             :   }
    1045             : 
    1046             :   // Finally delete the SnippetCopies.
    1047       60405 :   for (unsigned Reg : RegsToSpill) {
    1048        1009 :     for (MachineRegisterInfo::reg_instr_iterator
    1049       15840 :          RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end();
    1050       16849 :          RI != E; ) {
    1051        3027 :       MachineInstr &MI = *(RI++);
    1052             :       assert(SnippetCopies.count(&MI) && "Remaining use wasn't a snippet copy");
    1053             :       // FIXME: Do this with a LiveRangeEdit callback.
    1054        2018 :       LIS.RemoveMachineInstrFromMaps(MI);
    1055        1009 :       MI.eraseFromParent();
    1056             :     }
    1057             :   }
    1058             : 
    1059             :   // Delete all spilled registers.
    1060       60405 :   for (unsigned Reg : RegsToSpill)
    1061       15840 :     Edit->eraseVirtReg(Reg);
    1062       14855 : }
    1063             : 
    1064       29403 : void InlineSpiller::spill(LiveRangeEdit &edit) {
    1065       29403 :   ++NumSpilledRanges;
    1066       29403 :   Edit = &edit;
    1067             :   assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
    1068             :          && "Trying to spill a stack slot.");
    1069             :   // Share a stack slot among all descendants of Original.
    1070       88209 :   Original = VRM.getOriginal(edit.getReg());
    1071       58806 :   StackSlot = VRM.getStackSlot(Original);
    1072       29403 :   StackInt = nullptr;
    1073             : 
    1074             :   DEBUG(dbgs() << "Inline spilling "
    1075             :                << TRI.getRegClassName(MRI.getRegClass(edit.getReg()))
    1076             :                << ':' << edit.getParent()
    1077             :                << "\nFrom original " << PrintReg(Original) << '\n');
    1078             :   assert(edit.getParent().isSpillable() &&
    1079             :          "Attempting to spill already spilled value.");
    1080             :   assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
    1081             : 
    1082       29403 :   collectRegsToSpill();
    1083       29403 :   reMaterializeAll();
    1084             : 
    1085             :   // Remat may handle everything.
    1086       29403 :   if (!RegsToSpill.empty())
    1087       14855 :     spillAll();
    1088             : 
    1089       29403 :   Edit->calculateRegClassAndHint(MF, Loops, MBFI);
    1090       29403 : }
    1091             : 
    1092             : /// Optimizations after all the reg selections and spills are done.
    1093      134831 : void InlineSpiller::postOptimization() { HSpiller.hoistAllSpills(); }
    1094             : 
    1095             : /// When a spill is inserted, add the spill to MergeableSpills map.
    1096       19715 : void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot,
    1097             :                                             unsigned Original) {
    1098       39430 :   StackSlotToReg[StackSlot] = Original;
    1099       39430 :   SlotIndex Idx = LIS.getInstructionIndex(Spill);
    1100       59145 :   VNInfo *OrigVNI = LIS.getInterval(Original).getVNInfoAt(Idx.getRegSlot());
    1101       39430 :   std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
    1102       19715 :   MergeableSpills[MIdx].insert(&Spill);
    1103       19715 : }
    1104             : 
    1105             : /// When a spill is removed, remove the spill from MergeableSpills map.
    1106             : /// Return true if the spill is removed successfully.
    1107         809 : bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill,
    1108             :                                              int StackSlot) {
    1109        1618 :   int Original = StackSlotToReg[StackSlot];
    1110         809 :   if (!Original)
    1111             :     return false;
    1112        1618 :   SlotIndex Idx = LIS.getInstructionIndex(Spill);
    1113        2427 :   VNInfo *OrigVNI = LIS.getInterval(Original).getVNInfoAt(Idx.getRegSlot());
    1114        1618 :   std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
    1115        1618 :   return MergeableSpills[MIdx].erase(&Spill);
    1116             : }
    1117             : 
    1118             : /// Check BB to see if it is a possible target BB to place a hoisted spill,
    1119             : /// i.e., there should be a living sibling of OrigReg at the insert point.
    1120        4875 : bool HoistSpillHelper::isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI,
    1121             :                                      MachineBasicBlock &BB, unsigned &LiveReg) {
    1122        4875 :   SlotIndex Idx;
    1123        4875 :   LiveInterval &OrigLI = LIS.getInterval(OrigReg);
    1124        4875 :   MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, BB);
    1125        9750 :   if (MI != BB.end())
    1126       14124 :     Idx = LIS.getInstructionIndex(*MI);
    1127             :   else
    1128         334 :     Idx = LIS.getMBBEndIdx(&BB).getPrevSlot();
    1129        9750 :   SmallSetVector<unsigned, 16> &Siblings = Virt2SiblingsMap[OrigReg];
    1130             :   assert((LIS.getInterval(OrigReg)).getVNInfoAt(Idx) == &OrigVNI &&
    1131             :          "Unexpected VNI");
    1132             : 
    1133       17428 :   for (auto const SibReg : Siblings) {
    1134        7597 :     LiveInterval &LI = LIS.getInterval(SibReg);
    1135       12391 :     VNInfo *VNI = LI.getVNInfoAt(Idx);
    1136        4794 :     if (VNI) {
    1137        4794 :       LiveReg = SibReg;
    1138             :       return true;
    1139             :     }
    1140             :   }
    1141             :   return false;
    1142             : }
    1143             : 
    1144             : /// Remove redundant spills in the same BB. Save those redundant spills in
    1145             : /// SpillsToRm, and save the spill to keep and its BB in SpillBBToSpill map.
    1146       17719 : void HoistSpillHelper::rmRedundantSpills(
    1147             :     SmallPtrSet<MachineInstr *, 16> &Spills,
    1148             :     SmallVectorImpl<MachineInstr *> &SpillsToRm,
    1149             :     DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
    1150             :   // For each spill saw, check SpillBBToSpill[] and see if its BB already has
    1151             :   // another spill inside. If a BB contains more than one spill, only keep the
    1152             :   // earlier spill with smaller SlotIndex.
    1153       36565 :   for (const auto CurrentSpill : Spills) {
    1154       18846 :     MachineBasicBlock *Block = CurrentSpill->getParent();
    1155       37692 :     MachineDomTreeNode *Node = MDT.getBase().getNode(Block);
    1156       18846 :     MachineInstr *PrevSpill = SpillBBToSpill[Node];
    1157       18846 :     if (PrevSpill) {
    1158         680 :       SlotIndex PIdx = LIS.getInstructionIndex(*PrevSpill);
    1159         680 :       SlotIndex CIdx = LIS.getInstructionIndex(*CurrentSpill);
    1160         340 :       MachineInstr *SpillToRm = (CIdx > PIdx) ? CurrentSpill : PrevSpill;
    1161         340 :       MachineInstr *SpillToKeep = (CIdx > PIdx) ? PrevSpill : CurrentSpill;
    1162         340 :       SpillsToRm.push_back(SpillToRm);
    1163        1020 :       SpillBBToSpill[MDT.getBase().getNode(Block)] = SpillToKeep;
    1164             :     } else {
    1165       55518 :       SpillBBToSpill[MDT.getBase().getNode(Block)] = CurrentSpill;
    1166             :     }
    1167             :   }
    1168       53497 :   for (const auto SpillToRm : SpillsToRm)
    1169         680 :     Spills.erase(SpillToRm);
    1170       17719 : }
    1171             : 
    1172             : /// Starting from \p Root find a top-down traversal order of the dominator
    1173             : /// tree to visit all basic blocks containing the elements of \p Spills.
    1174             : /// Redundant spills will be found and put into \p SpillsToRm at the same
    1175             : /// time. \p SpillBBToSpill will be populated as part of the process and
    1176             : /// maps a basic block to the first store occurring in the basic block.
    1177             : /// \post SpillsToRm.union(Spills\@post) == Spills\@pre
    1178       17719 : void HoistSpillHelper::getVisitOrders(
    1179             :     MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
    1180             :     SmallVectorImpl<MachineDomTreeNode *> &Orders,
    1181             :     SmallVectorImpl<MachineInstr *> &SpillsToRm,
    1182             :     DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
    1183             :     DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
    1184             :   // The set contains all the possible BB nodes to which we may hoist
    1185             :   // original spills.
    1186       35438 :   SmallPtrSet<MachineDomTreeNode *, 8> WorkSet;
    1187             :   // Save the BB nodes on the path from the first BB node containing
    1188             :   // non-redundant spill to the Root node.
    1189       35438 :   SmallPtrSet<MachineDomTreeNode *, 8> NodesOnPath;
    1190             :   // All the spills to be hoisted must originate from a single def instruction
    1191             :   // to the OrigReg. It means the def instruction should dominate all the spills
    1192             :   // to be hoisted. We choose the BB where the def instruction is located as
    1193             :   // the Root.
    1194       17719 :   MachineDomTreeNode *RootIDomNode = MDT[Root]->getIDom();
    1195             :   // For every node on the dominator tree with spill, walk up on the dominator
    1196             :   // tree towards the Root node until it is reached. If there is other node
    1197             :   // containing spill in the middle of the path, the previous spill saw will
    1198             :   // be redundant and the node containing it will be removed. All the nodes on
    1199             :   // the path starting from the first node with non-redundant spill to the Root
    1200             :   // node will be added to the WorkSet, which will contain all the possible
    1201             :   // locations where spills may be hoisted to after the loop below is done.
    1202       36225 :   for (const auto Spill : Spills) {
    1203       18506 :     MachineBasicBlock *Block = Spill->getParent();
    1204       18506 :     MachineDomTreeNode *Node = MDT[Block];
    1205       18506 :     MachineInstr *SpillToRm = nullptr;
    1206       44567 :     while (Node != RootIDomNode) {
    1207             :       // If Node dominates Block, and it already contains a spill, the spill in
    1208             :       // Block will be redundant.
    1209       35190 :       if (Node != MDT[Block] && SpillBBToSpill[Node]) {
    1210         452 :         SpillToRm = SpillBBToSpill[MDT[Block]];
    1211             :         break;
    1212             :         /// If we see the Node already in WorkSet, the path from the Node to
    1213             :         /// the Root node must already be traversed by another spill.
    1214             :         /// Then no need to repeat.
    1215       26622 :       } else if (WorkSet.count(Node)) {
    1216             :         break;
    1217             :       } else {
    1218       26061 :         NodesOnPath.insert(Node);
    1219             :       }
    1220       26061 :       Node = Node->getIDom();
    1221             :     }
    1222       18506 :     if (SpillToRm) {
    1223         226 :       SpillsToRm.push_back(SpillToRm);
    1224             :     } else {
    1225             :       // Add a BB containing the original spills to SpillsToKeep -- i.e.,
    1226             :       // set the initial status before hoisting start. The value of BBs
    1227             :       // containing original spills is set to 0, in order to descriminate
    1228             :       // with BBs containing hoisted spills which will be inserted to
    1229             :       // SpillsToKeep later during hoisting.
    1230       36560 :       SpillsToKeep[MDT[Block]] = 0;
    1231       18280 :       WorkSet.insert(NodesOnPath.begin(), NodesOnPath.end());
    1232             :     }
    1233       18506 :     NodesOnPath.clear();
    1234             :   }
    1235             : 
    1236             :   // Sort the nodes in WorkSet in top-down order and save the nodes
    1237             :   // in Orders. Orders will be used for hoisting in runHoistSpills.
    1238       17719 :   unsigned idx = 0;
    1239       35438 :   Orders.push_back(MDT.getBase().getNode(Root));
    1240             :   do {
    1241       46310 :     MachineDomTreeNode *Node = Orders[idx++];
    1242       23155 :     const std::vector<MachineDomTreeNode *> &Children = Node->getChildren();
    1243       23155 :     unsigned NumChildren = Children.size();
    1244       46986 :     for (unsigned i = 0; i != NumChildren; ++i) {
    1245       47662 :       MachineDomTreeNode *Child = Children[i];
    1246       23831 :       if (WorkSet.count(Child))
    1247        5436 :         Orders.push_back(Child);
    1248             :     }
    1249       46310 :   } while (idx != Orders.size());
    1250             :   assert(Orders.size() == WorkSet.size() &&
    1251             :          "Orders have different size with WorkSet");
    1252             : 
    1253             : #ifndef NDEBUG
    1254             :   DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n");
    1255             :   SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
    1256             :   for (; RIt != Orders.rend(); RIt++)
    1257             :     DEBUG(dbgs() << "BB" << (*RIt)->getBlock()->getNumber() << ",");
    1258             :   DEBUG(dbgs() << "\n");
    1259             : #endif
    1260       17719 : }
    1261             : 
    1262             : /// Try to hoist spills according to BB hotness. The spills to removed will
    1263             : /// be saved in \p SpillsToRm. The spills to be inserted will be saved in
    1264             : /// \p SpillsToIns.
    1265       17719 : void HoistSpillHelper::runHoistSpills(
    1266             :     unsigned OrigReg, VNInfo &OrigVNI, SmallPtrSet<MachineInstr *, 16> &Spills,
    1267             :     SmallVectorImpl<MachineInstr *> &SpillsToRm,
    1268             :     DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns) {
    1269             :   // Visit order of dominator tree nodes.
    1270       35438 :   SmallVector<MachineDomTreeNode *, 32> Orders;
    1271             :   // SpillsToKeep contains all the nodes where spills are to be inserted
    1272             :   // during hoisting. If the spill to be inserted is an original spill
    1273             :   // (not a hoisted one), the value of the map entry is 0. If the spill
    1274             :   // is a hoisted spill, the value of the map entry is the VReg to be used
    1275             :   // as the source of the spill.
    1276       35438 :   DenseMap<MachineDomTreeNode *, unsigned> SpillsToKeep;
    1277             :   // Map from BB to the first spill inside of it.
    1278       35438 :   DenseMap<MachineDomTreeNode *, MachineInstr *> SpillBBToSpill;
    1279             : 
    1280       17719 :   rmRedundantSpills(Spills, SpillsToRm, SpillBBToSpill);
    1281             : 
    1282       35438 :   MachineBasicBlock *Root = LIS.getMBBFromIndex(OrigVNI.def);
    1283       17719 :   getVisitOrders(Root, Spills, Orders, SpillsToRm, SpillsToKeep,
    1284             :                  SpillBBToSpill);
    1285             : 
    1286             :   // SpillsInSubTreeMap keeps the map from a dom tree node to a pair of
    1287             :   // nodes set and the cost of all the spills inside those nodes.
    1288             :   // The nodes set are the locations where spills are to be inserted
    1289             :   // in the subtree of current node.
    1290             :   using NodesCostPair =
    1291             :       std::pair<SmallPtrSet<MachineDomTreeNode *, 16>, BlockFrequency>;
    1292       35438 :   DenseMap<MachineDomTreeNode *, NodesCostPair> SpillsInSubTreeMap;
    1293             : 
    1294             :   // Iterate Orders set in reverse order, which will be a bottom-up order
    1295             :   // in the dominator tree. Once we visit a dom tree node, we know its
    1296             :   // children have already been visited and the spill locations in the
    1297             :   // subtrees of all the children have been determined.
    1298       17719 :   SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
    1299      168932 :   for (; RIt != Orders.rend(); RIt++) {
    1300       23155 :     MachineBasicBlock *Block = (*RIt)->getBlock();
    1301             : 
    1302             :     // If Block contains an original spill, simply continue.
    1303      124305 :     if (SpillsToKeep.find(*RIt) != SpillsToKeep.end() && !SpillsToKeep[*RIt]) {
    1304       54840 :       SpillsInSubTreeMap[*RIt].first.insert(*RIt);
    1305             :       // SpillsInSubTreeMap[*RIt].second contains the cost of spill.
    1306       54840 :       SpillsInSubTreeMap[*RIt].second = MBFI.getBlockFreq(Block);
    1307       18361 :       continue;
    1308             :     }
    1309             : 
    1310             :     // Collect spills in subtree of current node (*RIt) to
    1311             :     // SpillsInSubTreeMap[*RIt].first.
    1312        4875 :     const std::vector<MachineDomTreeNode *> &Children = (*RIt)->getChildren();
    1313        4875 :     unsigned NumChildren = Children.size();
    1314       16636 :     for (unsigned i = 0; i != NumChildren; ++i) {
    1315       23522 :       MachineDomTreeNode *Child = Children[i];
    1316       23522 :       if (SpillsInSubTreeMap.find(Child) == SpillsInSubTreeMap.end())
    1317        6325 :         continue;
    1318             :       // The stmt "SpillsInSubTree = SpillsInSubTreeMap[*RIt].first" below
    1319             :       // should be placed before getting the begin and end iterators of
    1320             :       // SpillsInSubTreeMap[Child].first, or else the iterators may be
    1321             :       // invalidated when SpillsInSubTreeMap[*RIt] is seen the first time
    1322             :       // and the map grows and then the original buckets in the map are moved.
    1323             :       SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree =
    1324       10872 :           SpillsInSubTreeMap[*RIt].first;
    1325       10872 :       BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second;
    1326        5436 :       SubTreeCost += SpillsInSubTreeMap[Child].second;
    1327        5436 :       auto BI = SpillsInSubTreeMap[Child].first.begin();
    1328        5436 :       auto EI = SpillsInSubTreeMap[Child].first.end();
    1329        5436 :       SpillsInSubTree.insert(BI, EI);
    1330        5436 :       SpillsInSubTreeMap.erase(Child);
    1331             :     }
    1332             : 
    1333             :     SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree =
    1334        9750 :           SpillsInSubTreeMap[*RIt].first;
    1335        9750 :     BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second;
    1336             :     // No spills in subtree, simply continue.
    1337        9750 :     if (SpillsInSubTree.empty())
    1338             :       continue;
    1339             : 
    1340             :     // Check whether Block is a possible candidate to insert spill.
    1341        4875 :     unsigned LiveReg = 0;
    1342        4875 :     if (!isSpillCandBB(OrigReg, OrigVNI, *Block, LiveReg))
    1343             :       continue;
    1344             : 
    1345             :     // If there are multiple spills that could be merged, bias a little
    1346             :     // to hoist the spill.
    1347        4794 :     BranchProbability MarginProb = (SpillsInSubTree.size() > 1)
    1348             :                                        ? BranchProbability(9, 10)
    1349        4794 :                                        : BranchProbability(1, 1);
    1350        9588 :     if (SubTreeCost > MBFI.getBlockFreq(Block) * MarginProb) {
    1351             :       // Hoist: Move spills to current Block.
    1352        1577 :       for (const auto SpillBB : SpillsInSubTree) {
    1353             :         // When SpillBB is a BB contains original spill, insert the spill
    1354             :         // to SpillsToRm.
    1355        2994 :         if (SpillsToKeep.find(SpillBB) != SpillsToKeep.end() &&
    1356         998 :             !SpillsToKeep[SpillBB]) {
    1357         883 :           MachineInstr *SpillToRm = SpillBBToSpill[SpillBB];
    1358         883 :           SpillsToRm.push_back(SpillToRm);
    1359             :         }
    1360             :         // SpillBB will not contain spill anymore, remove it from SpillsToKeep.
    1361         998 :         SpillsToKeep.erase(SpillBB);
    1362             :       }
    1363             :       // Current Block is the BB containing the new hoisted spill. Add it to
    1364             :       // SpillsToKeep. LiveReg is the source of the new spill.
    1365        1158 :       SpillsToKeep[*RIt] = LiveReg;
    1366             :       DEBUG({
    1367             :         dbgs() << "spills in BB: ";
    1368             :         for (const auto Rspill : SpillsInSubTree)
    1369             :           dbgs() << Rspill->getBlock()->getNumber() << " ";
    1370             :         dbgs() << "were promoted to BB" << (*RIt)->getBlock()->getNumber()
    1371             :                << "\n";
    1372             :       });
    1373         579 :       SpillsInSubTree.clear();
    1374        1158 :       SpillsInSubTree.insert(*RIt);
    1375         579 :       SubTreeCost = MBFI.getBlockFreq(Block);
    1376             :     }
    1377             :   }
    1378             :   // For spills in SpillsToKeep with LiveReg set (i.e., not original spill),
    1379             :   // save them to SpillsToIns.
    1380       71018 :   for (const auto Ent : SpillsToKeep) {
    1381       17861 :     if (Ent.second)
    1382         928 :       SpillsToIns[Ent.first->getBlock()] = Ent.second;
    1383             :   }
    1384       17719 : }
    1385             : 
    1386             : /// For spills with equal values, remove redundant spills and hoist those left
    1387             : /// to less hot spots.
    1388             : ///
    1389             : /// Spills with equal values will be collected into the same set in
    1390             : /// MergeableSpills when spill is inserted. These equal spills are originated
    1391             : /// from the same defining instruction and are dominated by the instruction.
    1392             : /// Before hoisting all the equal spills, redundant spills inside in the same
    1393             : /// BB are first marked to be deleted. Then starting from the spills left, walk
    1394             : /// up on the dominator tree towards the Root node where the define instruction
    1395             : /// is located, mark the dominated spills to be deleted along the way and
    1396             : /// collect the BB nodes on the path from non-dominated spills to the define
    1397             : /// instruction into a WorkSet. The nodes in WorkSet are the candidate places
    1398             : /// where we are considering to hoist the spills. We iterate the WorkSet in
    1399             : /// bottom-up order, and for each node, we will decide whether to hoist spills
    1400             : /// inside its subtree to that node. In this way, we can get benefit locally
    1401             : /// even if hoisting all the equal spills to one cold place is impossible.
    1402      134831 : void HoistSpillHelper::hoistAllSpills() {
    1403      269662 :   SmallVector<unsigned, 4> NewVRegs;
    1404      404493 :   LiveRangeEdit Edit(nullptr, NewVRegs, MF, LIS, &VRM, this);
    1405             : 
    1406             :   // Save the mapping between stackslot and its original reg.
    1407      269662 :   DenseMap<int, unsigned> SlotToOrigReg;
    1408     2704253 :   for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
    1409     2434591 :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
    1410     4869182 :     int Slot = VRM.getStackSlot(Reg);
    1411     2434591 :     if (Slot != VirtRegMap::NO_STACK_SLOT)
    1412       65343 :       SlotToOrigReg[Slot] = VRM.getOriginal(Reg);
    1413     4869182 :     unsigned Original = VRM.getPreSplitReg(Reg);
    1414     4869182 :     if (!MRI.def_empty(Reg))
    1415     2362792 :       Virt2SiblingsMap[Original].insert(Reg);
    1416             :   }
    1417             : 
    1418             :   // Each entry in MergeableSpills contains a spill set with equal values.
    1419      557087 :   for (auto &Ent : MergeableSpills) {
    1420       17763 :     int Slot = Ent.first.first;
    1421       17763 :     unsigned OrigReg = SlotToOrigReg[Slot];
    1422       17763 :     LiveInterval &OrigLI = LIS.getInterval(OrigReg);
    1423       17763 :     VNInfo *OrigVNI = Ent.first.second;
    1424       17763 :     SmallPtrSet<MachineInstr *, 16> &EqValSpills = Ent.second;
    1425       35526 :     if (Ent.second.empty())
    1426          44 :       continue;
    1427             : 
    1428             :     DEBUG({
    1429             :       dbgs() << "\nFor Slot" << Slot << " and VN" << OrigVNI->id << ":\n"
    1430             :              << "Equal spills in BB: ";
    1431             :       for (const auto spill : EqValSpills)
    1432             :         dbgs() << spill->getParent()->getNumber() << " ";
    1433             :       dbgs() << "\n";
    1434             :     });
    1435             : 
    1436             :     // SpillsToRm is the spill set to be removed from EqValSpills.
    1437       35438 :     SmallVector<MachineInstr *, 16> SpillsToRm;
    1438             :     // SpillsToIns is the spill set to be newly inserted after hoisting.
    1439       35438 :     DenseMap<MachineBasicBlock *, unsigned> SpillsToIns;
    1440             : 
    1441       17719 :     runHoistSpills(OrigReg, *OrigVNI, EqValSpills, SpillsToRm, SpillsToIns);
    1442             : 
    1443             :     DEBUG({
    1444             :       dbgs() << "Finally inserted spills in BB: ";
    1445             :       for (const auto Ispill : SpillsToIns)
    1446             :         dbgs() << Ispill.first->getNumber() << " ";
    1447             :       dbgs() << "\nFinally removed spills in BB: ";
    1448             :       for (const auto Rspill : SpillsToRm)
    1449             :         dbgs() << Rspill->getParent()->getNumber() << " ";
    1450             :       dbgs() << "\n";
    1451             :     });
    1452             : 
    1453             :     // Stack live range update.
    1454       35438 :     LiveInterval &StackIntvl = LSS.getInterval(Slot);
    1455       17719 :     if (!SpillsToIns.empty() || !SpillsToRm.empty())
    1456        1382 :       StackIntvl.MergeValueInAsValue(OrigLI, OrigVNI,
    1457             :                                      StackIntvl.getValNumInfo(0));
    1458             : 
    1459             :     // Insert hoisted spills.
    1460       53621 :     for (auto const Insert : SpillsToIns) {
    1461         464 :       MachineBasicBlock *BB = Insert.first;
    1462         464 :       unsigned LiveReg = Insert.second;
    1463         464 :       MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, *BB);
    1464         928 :       TII.storeRegToStackSlot(*BB, MI, LiveReg, false, Slot,
    1465         464 :                               MRI.getRegClass(LiveReg), &TRI);
    1466         928 :       LIS.InsertMachineInstrRangeInMaps(std::prev(MI), MI);
    1467         464 :       ++NumSpills;
    1468             :     }
    1469             : 
    1470             :     // Remove redundant spills or change them to dead instructions.
    1471       17719 :     NumSpills -= SpillsToRm.size();
    1472       19168 :     for (auto const RMEnt : SpillsToRm) {
    1473        4347 :       RMEnt->setDesc(TII.get(TargetOpcode::KILL));
    1474        1449 :       for (unsigned i = RMEnt->getNumOperands(); i; --i) {
    1475       16508 :         MachineOperand &MO = RMEnt->getOperand(i - 1);
    1476       12379 :         if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())
    1477          29 :           RMEnt->RemoveOperand(i - 1);
    1478             :       }
    1479             :     }
    1480       35438 :     Edit.eliminateDeadDefs(SpillsToRm, None, AA);
    1481             :   }
    1482      134831 : }
    1483             : 
    1484             : /// For VirtReg clone, the \p New register should have the same physreg or
    1485             : /// stackslot as the \p old register.
    1486          44 : void HoistSpillHelper::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
    1487          88 :   if (VRM.hasPhys(Old))
    1488          88 :     VRM.assignVirt2Phys(New, VRM.getPhys(Old));
    1489           0 :   else if (VRM.getStackSlot(Old) != VirtRegMap::NO_STACK_SLOT)
    1490           0 :     VRM.assignVirt2StackSlot(New, VRM.getStackSlot(Old));
    1491             :   else
    1492           0 :     llvm_unreachable("VReg should be assigned either physreg or stackslot");
    1493      216962 : }

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