LCOV - code coverage report
Current view: top level - lib/CodeGen - InterferenceCache.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 139 140 99.3 %
Date: 2017-09-14 15:23:50 Functions: 8 8 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- InterferenceCache.cpp - Caching per-block interference ---------*--===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // InterferenceCache remembers per-block interference in LiveIntervalUnions.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "InterferenceCache.h"
      15             : #include "llvm/CodeGen/LiveIntervalAnalysis.h"
      16             : #include "llvm/Support/ErrorHandling.h"
      17             : #include "llvm/Target/TargetRegisterInfo.h"
      18             : 
      19             : using namespace llvm;
      20             : 
      21             : #define DEBUG_TYPE "regalloc"
      22             : 
      23             : // Static member used for null interference cursors.
      24             : const InterferenceCache::BlockInterference
      25             :     InterferenceCache::Cursor::NoInterference;
      26             : 
      27             : // Initializes PhysRegEntries (instead of a SmallVector, PhysRegEntries is a
      28             : // buffer of size NumPhysRegs to speed up alloc/clear for targets with large
      29             : // reg files). Calloced memory is used for good form, and quites tools like
      30             : // Valgrind too, but zero initialized memory is not required by the algorithm:
      31             : // this is because PhysRegEntries works like a SparseSet and its entries are
      32             : // only valid when there is a corresponding CacheEntries assignment. There is
      33             : // also support for when pass managers are reused for targets with different
      34             : // numbers of PhysRegs: in this case PhysRegEntries is freed and reinitialized.
      35      134612 : void InterferenceCache::reinitPhysRegEntries() {
      36      134612 :   if (PhysRegEntriesCount == TRI->getNumRegs()) return;
      37       14879 :   free(PhysRegEntries);
      38       14879 :   PhysRegEntriesCount = TRI->getNumRegs();
      39       14879 :   PhysRegEntries = (unsigned char*)
      40       14879 :     calloc(PhysRegEntriesCount, sizeof(unsigned char));
      41             : }
      42             : 
      43      134612 : void InterferenceCache::init(MachineFunction *mf,
      44             :                              LiveIntervalUnion *liuarray,
      45             :                              SlotIndexes *indexes,
      46             :                              LiveIntervals *lis,
      47             :                              const TargetRegisterInfo *tri) {
      48      134612 :   MF = mf;
      49      134612 :   LIUArray = liuarray;
      50      134612 :   TRI = tri;
      51      134612 :   reinitPhysRegEntries();
      52     4442196 :   for (unsigned i = 0; i != CacheEntries; ++i)
      53     8615168 :     Entries[i].clear(mf, indexes, lis);
      54      134612 : }
      55             : 
      56      306036 : InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
      57      306036 :   unsigned E = PhysRegEntries[PhysReg];
      58      306036 :   if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
      59      242726 :     if (!Entries[E].valid(LIUArray, TRI))
      60       31016 :       Entries[E].revalidate(LIUArray, TRI);
      61             :     return &Entries[E];
      62             :   }
      63             :   // No valid entry exists, pick the next round-robin entry.
      64       63310 :   E = RoundRobin;
      65       63310 :   if (++RoundRobin == CacheEntries)
      66        1830 :     RoundRobin = 0;
      67      279726 :   for (unsigned i = 0; i != CacheEntries; ++i) {
      68             :     // Skip entries that are in use.
      69      279726 :     if (Entries[E].hasRefs()) {
      70      108208 :       if (++E == CacheEntries)
      71        3248 :         E = 0;
      72             :       continue;
      73             :     }
      74       63310 :     Entries[E].reset(PhysReg, LIUArray, TRI, MF);
      75       63310 :     PhysRegEntries[PhysReg] = E;
      76       63310 :     return &Entries[E];
      77             :   }
      78           0 :   llvm_unreachable("Ran out of interference cache entries.");
      79             : }
      80             : 
      81             : /// revalidate - LIU contents have changed, update tags.
      82       31016 : void InterferenceCache::Entry::revalidate(LiveIntervalUnion *LIUArray,
      83             :                                           const TargetRegisterInfo *TRI) {
      84             :   // Invalidate all block entries.
      85       31016 :   ++Tag;
      86             :   // Invalidate all iterators.
      87       31016 :   PrevPos = SlotIndex();
      88       31016 :   unsigned i = 0;
      89      145518 :   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
      90       83486 :     RegUnits[i].VirtTag = LIUArray[*Units].getTag();
      91       31016 : }
      92             : 
      93       63310 : void InterferenceCache::Entry::reset(unsigned physReg,
      94             :                                      LiveIntervalUnion *LIUArray,
      95             :                                      const TargetRegisterInfo *TRI,
      96             :                                      const MachineFunction *MF) {
      97             :   assert(!hasRefs() && "Cannot reset cache entry with references");
      98             :   // LIU's changed, invalidate cache.
      99       63310 :   ++Tag;
     100       63310 :   PhysReg = physReg;
     101      126620 :   Blocks.resize(MF->getNumBlockIDs());
     102             : 
     103             :   // Reset iterators.
     104       63310 :   PrevPos = SlotIndex();
     105       63310 :   RegUnits.clear();
     106      200963 :   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
     107      297372 :     RegUnits.push_back(LIUArray[*Units]);
     108      148686 :     RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
     109             :   }
     110       63310 : }
     111             : 
     112      242726 : bool InterferenceCache::Entry::valid(LiveIntervalUnion *LIUArray,
     113             :                                      const TargetRegisterInfo *TRI) {
     114      485452 :   unsigned i = 0, e = RegUnits.size();
     115     1016988 :   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) {
     116      296784 :     if (i == e)
     117             :       return false;
     118      593568 :     if (LIUArray[*Units].changedSince(RegUnits[i].VirtTag))
     119             :       return false;
     120             :   }
     121      211710 :   return i == e;
     122             : }
     123             : 
     124      973002 : void InterferenceCache::Entry::update(unsigned MBBNum) {
     125     1946004 :   SlotIndex Start, Stop;
     126     3892008 :   std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
     127             : 
     128             :   // Use advanceTo only when possible.
     129     1946004 :   if (PrevPos != Start) {
     130     2214666 :     if (!PrevPos.isValid() || Start < PrevPos) {
     131     1525596 :       for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
     132      694164 :         RegUnitInfo &RUI = RegUnits[i];
     133      347082 :         RUI.VirtI.find(Start);
     134      347082 :         RUI.FixedI = RUI.Fixed->find(Start);
     135             :       }
     136             :     } else {
     137     2771912 :       for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
     138     1294352 :         RegUnitInfo &RUI = RegUnits[i];
     139      647176 :         RUI.VirtI.advanceTo(Start);
     140     1294352 :         if (RUI.FixedI != RUI.Fixed->end())
     141      312600 :           RUI.FixedI = RUI.Fixed->advanceTo(RUI.FixedI, Start);
     142             :       }
     143             :     }
     144      769664 :     PrevPos = Start;
     145             :   }
     146             : 
     147             :   MachineFunction::const_iterator MFI =
     148     3892008 :       MF->getBlockNumbered(MBBNum)->getIterator();
     149     1946004 :   BlockInterference *BI = &Blocks[MBBNum];
     150      973002 :   ArrayRef<SlotIndex> RegMaskSlots;
     151      973002 :   ArrayRef<const uint32_t*> RegMaskBits;
     152             :   for (;;) {
     153     1599044 :     BI->Tag = Tag;
     154     1599044 :     BI->First = BI->Last = SlotIndex();
     155             : 
     156             :     // Check for first interference from virtregs.
     157     5178684 :     for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
     158     3961192 :       LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
     159     3961192 :       if (!I.valid())
     160      521395 :         continue;
     161     2918402 :       SlotIndex StartI = I.start();
     162     1459201 :       if (StartI >= Stop)
     163      855881 :         continue;
     164     1358307 :       if (!BI->First.isValid() || StartI < BI->First)
     165      455608 :         BI->First = StartI;
     166             :     }
     167             : 
     168             :     // Same thing for fixed interference.
     169     5178684 :     for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
     170     3961192 :       LiveInterval::const_iterator I = RegUnits[i].FixedI;
     171     5941788 :       LiveInterval::const_iterator E = RegUnits[i].Fixed->end();
     172     1980596 :       if (I == E)
     173     1300025 :         continue;
     174      680571 :       SlotIndex StartI = I->start;
     175      680571 :       if (StartI >= Stop)
     176      371548 :         continue;
     177      618046 :       if (!BI->First.isValid() || StartI < BI->First)
     178      117662 :         BI->First = StartI;
     179             :     }
     180             : 
     181             :     // Also check for register mask interference.
     182     3198088 :     RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
     183     3198088 :     RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
     184     3198088 :     SlotIndex Limit = BI->First.isValid() ? BI->First : Stop;
     185     2078688 :     for (unsigned i = 0, e = RegMaskSlots.size();
     186     4474914 :          i != e && RegMaskSlots[i] < Limit; ++i)
     187     2602584 :       if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) {
     188             :         // Register mask i clobbers PhysReg before the LIU interference.
     189      387884 :         BI->First = RegMaskSlots[i];
     190      387884 :         break;
     191             :       }
     192             : 
     193     1599044 :     PrevPos = Stop;
     194     3198088 :     if (BI->First.isValid())
     195             :       break;
     196             : 
     197             :     // No interference in this block? Go ahead and precompute the next block.
     198     2133564 :     if (++MFI == MF->end())
     199       85146 :       return;
     200      696041 :     MBBNum = MFI->getNumber();
     201     1392082 :     BI = &Blocks[MBBNum];
     202      696041 :     if (BI->Tag == Tag)
     203             :       return;
     204     2504168 :     std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
     205      626042 :   }
     206             : 
     207             :   // Check for last interference in block.
     208     5020140 :   for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
     209     2356572 :     LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
     210     4516579 :     if (!I.valid() || I.start() >= Stop)
     211      574966 :       continue;
     212      603320 :     I.advanceTo(Stop);
     213     2299778 :     bool Backup = !I.valid() || I.start() >= Stop;
     214             :     if (Backup)
     215             :       --I;
     216     1206640 :     SlotIndex StopI = I.stop();
     217     1358307 :     if (!BI->Last.isValid() || StopI > BI->Last)
     218      453930 :       BI->Last = StopI;
     219      603320 :     if (Backup)
     220             :       ++I;
     221             :   }
     222             : 
     223             :   // Fixed interference.
     224     2953998 :   for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
     225     2356572 :     LiveInterval::iterator &I = RegUnits[i].FixedI;
     226     2356572 :     LiveRange *LR = RegUnits[i].Fixed;
     227     3799711 :     if (I == LR->end() || I->start >= Stop)
     228      869263 :       continue;
     229      309023 :     I = LR->advanceTo(I, Stop);
     230     1205924 :     bool Backup = I == LR->end() || I->start >= Stop;
     231             :     if (Backup)
     232      309023 :       --I;
     233      309023 :     SlotIndex StopI = I->end;
     234      837184 :     if (!BI->Last.isValid() || StopI > BI->Last)
     235      153352 :       BI->Last = StopI;
     236      309023 :     if (Backup)
     237      309023 :       ++I;
     238             :   }
     239             : 
     240             :   // Also check for register mask interference.
     241     1775712 :   SlotIndex Limit = BI->Last.isValid() ? BI->Last : Start;
     242      887856 :   for (unsigned i = RegMaskSlots.size();
     243     3283647 :        i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i)
     244     1685754 :     if (MachineOperand::clobbersPhysReg(RegMaskBits[i-1], PhysReg)) {
     245             :       // Register mask i-1 clobbers PhysReg after the LIU interference.
     246             :       // Model the regmask clobber as a dead def.
     247     1001580 :       BI->Last = RegMaskSlots[i-1].getDeadSlot();
     248      500790 :       break;
     249             :     }
     250      144612 : }

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