Line data Source code
1 : //===- LiveRangeShrink.cpp - Move instructions to shrink live range -------===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : ///===---------------------------------------------------------------------===//
9 : ///
10 : /// \file
11 : /// This pass moves instructions close to the definition of its operands to
12 : /// shrink live range of the def instruction. The code motion is limited within
13 : /// the basic block. The moved instruction should have 1 def, and more than one
14 : /// uses, all of which are the only use of the def.
15 : ///
16 : ///===---------------------------------------------------------------------===//
17 :
18 : #include "llvm/ADT/DenseMap.h"
19 : #include "llvm/ADT/Statistic.h"
20 : #include "llvm/ADT/iterator_range.h"
21 : #include "llvm/CodeGen/MachineBasicBlock.h"
22 : #include "llvm/CodeGen/MachineFunction.h"
23 : #include "llvm/CodeGen/MachineFunctionPass.h"
24 : #include "llvm/CodeGen/MachineInstr.h"
25 : #include "llvm/CodeGen/MachineOperand.h"
26 : #include "llvm/CodeGen/MachineRegisterInfo.h"
27 : #include "llvm/CodeGen/TargetRegisterInfo.h"
28 : #include "llvm/Pass.h"
29 : #include "llvm/Support/Debug.h"
30 : #include "llvm/Support/raw_ostream.h"
31 : #include <iterator>
32 : #include <utility>
33 :
34 : using namespace llvm;
35 :
36 : #define DEBUG_TYPE "lrshrink"
37 :
38 : STATISTIC(NumInstrsHoistedToShrinkLiveRange,
39 : "Number of insructions hoisted to shrink live range.");
40 :
41 : namespace {
42 :
43 : class LiveRangeShrink : public MachineFunctionPass {
44 : public:
45 : static char ID;
46 :
47 8389 : LiveRangeShrink() : MachineFunctionPass(ID) {
48 8389 : initializeLiveRangeShrinkPass(*PassRegistry::getPassRegistry());
49 8389 : }
50 :
51 8349 : void getAnalysisUsage(AnalysisUsage &AU) const override {
52 8349 : AU.setPreservesCFG();
53 8349 : MachineFunctionPass::getAnalysisUsage(AU);
54 8349 : }
55 :
56 8367 : StringRef getPassName() const override { return "Live Range Shrink"; }
57 :
58 : bool runOnMachineFunction(MachineFunction &MF) override;
59 : };
60 :
61 : } // end anonymous namespace
62 :
63 : char LiveRangeShrink::ID = 0;
64 :
65 : char &llvm::LiveRangeShrinkID = LiveRangeShrink::ID;
66 :
67 93536 : INITIALIZE_PASS(LiveRangeShrink, "lrshrink", "Live Range Shrink Pass", false,
68 : false)
69 :
70 : using InstOrderMap = DenseMap<MachineInstr *, unsigned>;
71 :
72 : /// Returns \p New if it's dominated by \p Old, otherwise return \p Old.
73 : /// \p M maintains a map from instruction to its dominating order that satisfies
74 : /// M[A] > M[B] guarantees that A is dominated by B.
75 : /// If \p New is not in \p M, return \p Old. Otherwise if \p Old is null, return
76 : /// \p New.
77 374863 : static MachineInstr *FindDominatedInstruction(MachineInstr &New,
78 : MachineInstr *Old,
79 : const InstOrderMap &M) {
80 374863 : auto NewIter = M.find(&New);
81 374863 : if (NewIter == M.end())
82 : return Old;
83 363650 : if (Old == nullptr)
84 : return &New;
85 73429 : unsigned OrderOld = M.find(Old)->second;
86 73429 : unsigned OrderNew = NewIter->second;
87 73429 : if (OrderOld != OrderNew)
88 112346 : return OrderOld < OrderNew ? &New : Old;
89 : // OrderOld == OrderNew, we need to iterate down from Old to see if it
90 : // can reach New, if yes, New is dominated by Old.
91 310 : for (MachineInstr *I = Old->getNextNode(); M.find(I)->second == OrderNew;
92 : I = I->getNextNode())
93 57 : if (I == &New)
94 : return &New;
95 : return Old;
96 : }
97 :
98 : /// Builds Instruction to its dominating order number map \p M by traversing
99 : /// from instruction \p Start.
100 352620 : static void BuildInstOrderMap(MachineBasicBlock::iterator Start,
101 : InstOrderMap &M) {
102 352620 : M.clear();
103 : unsigned i = 0;
104 3700618 : for (MachineInstr &I : make_range(Start, Start->getParent()->end()))
105 3347998 : M[&I] = i++;
106 352620 : }
107 :
108 111638 : bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
109 111638 : if (skipFunction(MF.getFunction()))
110 : return false;
111 :
112 111504 : MachineRegisterInfo &MRI = MF.getRegInfo();
113 :
114 : LLVM_DEBUG(dbgs() << "**** Analysing " << MF.getName() << '\n');
115 :
116 : InstOrderMap IOM;
117 : // Map from register to instruction order (value of IOM) where the
118 : // register is used last. When moving instructions up, we need to
119 : // make sure all its defs (including dead def) will not cross its
120 : // last use when moving up.
121 : DenseMap<unsigned, std::pair<unsigned, MachineInstr *>> UseMap;
122 :
123 458703 : for (MachineBasicBlock &MBB : MF) {
124 347199 : if (MBB.empty())
125 2835 : continue;
126 344364 : bool SawStore = false;
127 344364 : BuildInstOrderMap(MBB.begin(), IOM);
128 344364 : UseMap.clear();
129 :
130 3623452 : for (MachineBasicBlock::iterator Next = MBB.begin(); Next != MBB.end();) {
131 : MachineInstr &MI = *Next;
132 : ++Next;
133 : if (MI.isPHI() || MI.isDebugInstr())
134 1590114 : continue;
135 3080810 : if (MI.mayStore())
136 638268 : SawStore = true;
137 :
138 3080809 : unsigned CurrentOrder = IOM[&MI];
139 : unsigned Barrier = 0;
140 : MachineInstr *BarrierMI = nullptr;
141 16359467 : for (const MachineOperand &MO : MI.operands()) {
142 13278657 : if (!MO.isReg() || MO.isDebug())
143 : continue;
144 9092187 : if (MO.isUse())
145 5978745 : UseMap[MO.getReg()] = std::make_pair(CurrentOrder, &MI);
146 3742414 : else if (MO.isDead() && UseMap.count(MO.getReg()))
147 : // Barrier is the last instruction where MO get used. MI should not
148 : // be moved above Barrier.
149 417822 : if (Barrier < UseMap[MO.getReg()].first) {
150 225976 : Barrier = UseMap[MO.getReg()].first;
151 225976 : BarrierMI = UseMap[MO.getReg()].second;
152 : }
153 : }
154 :
155 3080810 : if (!MI.isSafeToMove(nullptr, SawStore)) {
156 : // If MI has side effects, it should become a barrier for code motion.
157 : // IOM is rebuild from the next instruction to prevent later
158 : // instructions from being moved before this MI.
159 1352405 : if (MI.hasUnmodeledSideEffects() && Next != MBB.end()) {
160 8256 : BuildInstOrderMap(Next, IOM);
161 8256 : SawStore = false;
162 : }
163 1352405 : continue;
164 : }
165 :
166 : const MachineOperand *DefMO = nullptr;
167 1728405 : MachineInstr *Insert = nullptr;
168 :
169 : // Number of live-ranges that will be shortened. We do not count
170 : // live-ranges that are defined by a COPY as it could be coalesced later.
171 : unsigned NumEligibleUse = 0;
172 :
173 5525315 : for (const MachineOperand &MO : MI.operands()) {
174 5125692 : if (!MO.isReg() || MO.isDead() || MO.isDebug())
175 : continue;
176 3272658 : unsigned Reg = MO.getReg();
177 : // Do not move the instruction if it def/uses a physical register,
178 : // unless it is a constant physical register or a noreg.
179 3272658 : if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
180 1240745 : if (!Reg || MRI.isConstantPhysReg(Reg))
181 409993 : continue;
182 830752 : Insert = nullptr;
183 830752 : break;
184 : }
185 2031913 : if (MO.isDef()) {
186 : // Do not move if there is more than one def.
187 1159358 : if (DefMO) {
188 338 : Insert = nullptr;
189 338 : break;
190 : }
191 : DefMO = &MO;
192 872555 : } else if (MRI.hasOneNonDBGUse(Reg) && MRI.hasOneDef(Reg) && DefMO &&
193 521693 : MRI.getRegClass(DefMO->getReg()) ==
194 521693 : MRI.getRegClass(MO.getReg())) {
195 : // The heuristic does not handle different register classes yet
196 : // (registers of different sizes, looser/tighter constraints). This
197 : // is because it needs more accurate model to handle register
198 : // pressure correctly.
199 374863 : MachineInstr &DefInstr = *MRI.def_instr_begin(Reg);
200 374863 : if (!DefInstr.isCopy())
201 255173 : NumEligibleUse++;
202 374863 : Insert = FindDominatedInstruction(DefInstr, Insert, IOM);
203 : } else {
204 497692 : Insert = nullptr;
205 497692 : break;
206 : }
207 : }
208 :
209 : // If Barrier equals IOM[I], traverse forward to find if BarrierMI is
210 : // after Insert, if yes, then we should not hoist.
211 1909038 : for (MachineInstr *I = Insert; I && IOM[I] == Barrier;
212 17258 : I = I->getNextNode())
213 17781 : if (I == BarrierMI) {
214 523 : Insert = nullptr;
215 523 : break;
216 : }
217 : // Move the instruction when # of shrunk live range > 1.
218 1769688 : if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) {
219 41141 : MachineBasicBlock::iterator I = std::next(Insert->getIterator());
220 : // Skip all the PHI and debug instructions.
221 41317 : while (I != MBB.end() && (I->isPHI() || I->isDebugInstr()))
222 176 : I = std::next(I);
223 41141 : if (I == MI.getIterator())
224 : continue;
225 :
226 : // Update the dominator order to be the same as the insertion point.
227 : // We do this to maintain a non-decreasing order without need to update
228 : // all instruction orders after the insertion point.
229 1710 : unsigned NewOrder = IOM[&*I];
230 1710 : IOM[&MI] = NewOrder;
231 : NumInstrsHoistedToShrinkLiveRange++;
232 :
233 : // Find MI's debug value following MI.
234 : MachineBasicBlock::iterator EndIter = std::next(MI.getIterator());
235 3420 : if (MI.getOperand(0).isReg())
236 1714 : for (; EndIter != MBB.end() && EndIter->isDebugValue() &&
237 1718 : EndIter->getOperand(0).isReg() &&
238 4 : EndIter->getOperand(0).getReg() == MI.getOperand(0).getReg();
239 : ++EndIter, ++Next)
240 4 : IOM[&*EndIter] = NewOrder;
241 : MBB.splice(I, &MBB, MI.getIterator(), EndIter);
242 : }
243 : }
244 : }
245 : return false;
246 : }
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