LCOV - code coverage report
Current view: top level - lib/CodeGen - LiveVariables.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 312 335 93.1 %
Date: 2018-06-17 00:07:59 Functions: 25 25 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the LiveVariable analysis pass.  For each machine
      11             : // instruction in the function, this pass calculates the set of registers that
      12             : // are immediately dead after the instruction (i.e., the instruction calculates
      13             : // the value, but it is never used) and the set of registers that are used by
      14             : // the instruction, but are never used after the instruction (i.e., they are
      15             : // killed).
      16             : //
      17             : // This class computes live variables using a sparse implementation based on
      18             : // the machine code SSA form.  This class computes live variable information for
      19             : // each virtual and _register allocatable_ physical register in a function.  It
      20             : // uses the dominance properties of SSA form to efficiently compute live
      21             : // variables for virtual registers, and assumes that physical registers are only
      22             : // live within a single basic block (allowing it to do a single local analysis
      23             : // to resolve physical register lifetimes in each basic block).  If a physical
      24             : // register is not register allocatable, it is not tracked.  This is useful for
      25             : // things like the stack pointer and condition codes.
      26             : //
      27             : //===----------------------------------------------------------------------===//
      28             : 
      29             : #include "llvm/CodeGen/LiveVariables.h"
      30             : #include "llvm/ADT/DepthFirstIterator.h"
      31             : #include "llvm/ADT/STLExtras.h"
      32             : #include "llvm/ADT/SmallPtrSet.h"
      33             : #include "llvm/ADT/SmallSet.h"
      34             : #include "llvm/CodeGen/MachineInstr.h"
      35             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      36             : #include "llvm/CodeGen/Passes.h"
      37             : #include "llvm/Config/llvm-config.h"
      38             : #include "llvm/Support/Debug.h"
      39             : #include "llvm/Support/ErrorHandling.h"
      40             : #include "llvm/Support/raw_ostream.h"
      41             : #include <algorithm>
      42             : using namespace llvm;
      43             : 
      44             : char LiveVariables::ID = 0;
      45             : char &llvm::LiveVariablesID = LiveVariables::ID;
      46       26770 : INITIALIZE_PASS_BEGIN(LiveVariables, "livevars",
      47             :                 "Live Variable Analysis", false, false)
      48       26770 : INITIALIZE_PASS_DEPENDENCY(UnreachableMachineBlockElim)
      49      242058 : INITIALIZE_PASS_END(LiveVariables, "livevars",
      50             :                 "Live Variable Analysis", false, false)
      51             : 
      52             : 
      53       20048 : void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
      54       20048 :   AU.addRequiredID(UnreachableMachineBlockElimID);
      55             :   AU.setPreservesAll();
      56       20048 :   MachineFunctionPass::getAnalysisUsage(AU);
      57       20048 : }
      58             : 
      59             : MachineInstr *
      60      468085 : LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
      61      950511 :   for (unsigned i = 0, e = Kills.size(); i != e; ++i)
      62      933714 :     if (Kills[i]->getParent() == MBB)
      63             :       return Kills[i];
      64             :   return nullptr;
      65             : }
      66             : 
      67             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
      68             : LLVM_DUMP_METHOD void LiveVariables::VarInfo::dump() const {
      69             :   dbgs() << "  Alive in blocks: ";
      70             :   for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
      71             :            E = AliveBlocks.end(); I != E; ++I)
      72             :     dbgs() << *I << ", ";
      73             :   dbgs() << "\n  Killed by:";
      74             :   if (Kills.empty())
      75             :     dbgs() << " No instructions.\n";
      76             :   else {
      77             :     for (unsigned i = 0, e = Kills.size(); i != e; ++i)
      78             :       dbgs() << "\n    #" << i << ": " << *Kills[i];
      79             :     dbgs() << "\n";
      80             :   }
      81             : }
      82             : #endif
      83             : 
      84             : /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
      85     6729075 : LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
      86             :   assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
      87             :          "getVarInfo: not a virtual register!");
      88     6729075 :   VirtRegInfo.grow(RegIdx);
      89     6729075 :   return VirtRegInfo[RegIdx];
      90             : }
      91             : 
      92     1853420 : void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
      93             :                                             MachineBasicBlock *DefBlock,
      94             :                                             MachineBasicBlock *MBB,
      95             :                                     std::vector<MachineBasicBlock*> &WorkList) {
      96     1853420 :   unsigned BBNum = MBB->getNumber();
      97             : 
      98             :   // Check to see if this basic block is one of the killing blocks.  If so,
      99             :   // remove it.
     100     8419374 :   for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
     101     9897032 :     if (VRInfo.Kills[i]->getParent() == MBB) {
     102      235982 :       VRInfo.Kills.erase(VRInfo.Kills.begin()+i);  // Erase entry
     103      235982 :       break;
     104             :     }
     105             : 
     106     1853420 :   if (MBB == DefBlock) return;  // Terminate recursion
     107             : 
     108     1624664 :   if (VRInfo.AliveBlocks.test(BBNum))
     109             :     return;  // We already know the block is live
     110             : 
     111             :   // Mark the variable known alive in this bb
     112      937909 :   VRInfo.AliveBlocks.set(BBNum);
     113             : 
     114             :   assert(MBB != &MF->front() && "Can't find reaching def for virtreg");
     115      937909 :   WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());
     116             : }
     117             : 
     118      624096 : void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
     119             :                                             MachineBasicBlock *DefBlock,
     120             :                                             MachineBasicBlock *MBB) {
     121             :   std::vector<MachineBasicBlock*> WorkList;
     122      624096 :   MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
     123             : 
     124     3082744 :   while (!WorkList.empty()) {
     125     1229324 :     MachineBasicBlock *Pred = WorkList.back();
     126             :     WorkList.pop_back();
     127     1229324 :     MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
     128             :   }
     129      624096 : }
     130             : 
     131     2927837 : void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
     132             :                                      MachineInstr &MI) {
     133             :   assert(MRI->getVRegDef(reg) && "Register use before def!");
     134             : 
     135     2927837 :   unsigned BBNum = MBB->getNumber();
     136             : 
     137     2927837 :   VarInfo& VRInfo = getVarInfo(reg);
     138             : 
     139             :   // Check to see if this basic block is already a kill block.
     140     2927837 :   if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
     141             :     // Yes, this register is killed in this basic block already. Increase the
     142             :     // live range by updating the kill instruction.
     143     2529482 :     VRInfo.Kills.back() = &MI;
     144     2529482 :     return;
     145             :   }
     146             : 
     147             : #ifndef NDEBUG
     148             :   for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
     149             :     assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
     150             : #endif
     151             : 
     152             :   // This situation can occur:
     153             :   //
     154             :   //     ,------.
     155             :   //     |      |
     156             :   //     |      v
     157             :   //     |   t2 = phi ... t1 ...
     158             :   //     |      |
     159             :   //     |      v
     160             :   //     |   t1 = ...
     161             :   //     |  ... = ... t1 ...
     162             :   //     |      |
     163             :   //     `------'
     164             :   //
     165             :   // where there is a use in a PHI node that's a predecessor to the defining
     166             :   // block. We don't want to mark all predecessors as having the value "alive"
     167             :   // in this case.
     168      398355 :   if (MBB == MRI->getVRegDef(reg)->getParent()) return;
     169             : 
     170             :   // Add a new kill entry for this basic block. If this virtual register is
     171             :   // already marked as alive in this basic block, that means it is alive in at
     172             :   // least one of the successor blocks, it's not a kill.
     173      398355 :   if (!VRInfo.AliveBlocks.test(BBNum))
     174      334282 :     VRInfo.Kills.push_back(&MI);
     175             : 
     176             :   // Update all dominating blocks to mark them as "known live".
     177             :   for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
     178      942012 :          E = MBB->pred_end(); PI != E; ++PI)
     179      543657 :     MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
     180             : }
     181             : 
     182     1989718 : void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) {
     183     1989718 :   VarInfo &VRInfo = getVarInfo(Reg);
     184             : 
     185     1989718 :   if (VRInfo.AliveBlocks.empty())
     186             :     // If vr is not alive in any block, then defaults to dead.
     187     3979436 :     VRInfo.Kills.push_back(&MI);
     188     1989718 : }
     189             : 
     190             : /// FindLastPartialDef - Return the last partial def of the specified register.
     191             : /// Also returns the sub-registers that're defined by the instruction.
     192      331296 : MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
     193             :                                             SmallSet<unsigned,4> &PartDefRegs) {
     194      331296 :   unsigned LastDefReg = 0;
     195             :   unsigned LastDefDist = 0;
     196             :   MachineInstr *LastDef = nullptr;
     197     1187035 :   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
     198             :     unsigned SubReg = *SubRegs;
     199     1048886 :     MachineInstr *Def = PhysRegDef[SubReg];
     200      524443 :     if (!Def)
     201      524428 :       continue;
     202          30 :     unsigned Dist = DistanceMap[Def];
     203          15 :     if (Dist > LastDefDist) {
     204           3 :       LastDefReg  = SubReg;
     205           3 :       LastDef     = Def;
     206             :       LastDefDist = Dist;
     207             :     }
     208             :   }
     209             : 
     210      331296 :   if (!LastDef)
     211             :     return nullptr;
     212             : 
     213           3 :   PartDefRegs.insert(LastDefReg);
     214          12 :   for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
     215           9 :     MachineOperand &MO = LastDef->getOperand(i);
     216          18 :     if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
     217           3 :       continue;
     218             :     unsigned DefReg = MO.getReg();
     219          12 :     if (TRI->isSubRegister(Reg, DefReg)) {
     220           3 :       for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
     221          18 :            SubRegs.isValid(); ++SubRegs)
     222          15 :         PartDefRegs.insert(*SubRegs);
     223             :     }
     224             :   }
     225             :   return LastDef;
     226             : }
     227             : 
     228             : /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
     229             : /// implicit defs to a machine instruction if there was an earlier def of its
     230             : /// super-register.
     231      951668 : void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) {
     232     1903336 :   MachineInstr *LastDef = PhysRegDef[Reg];
     233             :   // If there was a previous use or a "full" def all is well.
     234     1283896 :   if (!LastDef && !PhysRegUse[Reg]) {
     235             :     // Otherwise, the last sub-register def implicitly defines this register.
     236             :     // e.g.
     237             :     // AH =
     238             :     // AL = ... implicit-def EAX, implicit killed AH
     239             :     //    = AH
     240             :     // ...
     241             :     //    = EAX
     242             :     // All of the sub-registers must have been defined before the use of Reg!
     243      331296 :     SmallSet<unsigned, 4> PartDefRegs;
     244      331296 :     MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
     245             :     // If LastPartialDef is NULL, it must be using a livein register.
     246      331296 :     if (LastPartialDef) {
     247           3 :       LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
     248             :                                                            true/*IsImp*/));
     249           6 :       PhysRegDef[Reg] = LastPartialDef;
     250           3 :       SmallSet<unsigned, 8> Processed;
     251          21 :       for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
     252          15 :         unsigned SubReg = *SubRegs;
     253          15 :         if (Processed.count(SubReg))
     254          15 :           continue;
     255          15 :         if (PartDefRegs.count(SubReg))
     256          15 :           continue;
     257             :         // This part of Reg was defined before the last partial def. It's killed
     258             :         // here.
     259           0 :         LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
     260             :                                                              false/*IsDef*/,
     261             :                                                              true/*IsImp*/));
     262           0 :         PhysRegDef[SubReg] = LastPartialDef;
     263           0 :         for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
     264           0 :           Processed.insert(*SS);
     265             :       }
     266             :     }
     267     2477298 :   } else if (LastDef && !PhysRegUse[Reg] &&
     268             :              !LastDef->findRegisterDefOperand(Reg))
     269             :     // Last def defines the super register, add an implicit def of reg.
     270         217 :     LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
     271             :                                                   true/*IsImp*/));
     272             : 
     273             :   // Remember this use.
     274      951668 :   for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
     275     3719707 :        SubRegs.isValid(); ++SubRegs)
     276     5536078 :     PhysRegUse[*SubRegs] = &MI;
     277      951668 : }
     278             : 
     279             : /// FindLastRefOrPartRef - Return the last reference or partial reference of
     280             : /// the specified register.
     281         362 : MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
     282         724 :   MachineInstr *LastDef = PhysRegDef[Reg];
     283         724 :   MachineInstr *LastUse = PhysRegUse[Reg];
     284         362 :   if (!LastDef && !LastUse)
     285             :     return nullptr;
     286             : 
     287         362 :   MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
     288         724 :   unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
     289             :   unsigned LastPartDefDist = 0;
     290         952 :   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
     291             :     unsigned SubReg = *SubRegs;
     292         456 :     MachineInstr *Def = PhysRegDef[SubReg];
     293         228 :     if (Def && Def != LastDef) {
     294             :       // There was a def of this sub-register in between. This is a partial
     295             :       // def, keep track of the last one.
     296          84 :       unsigned Dist = DistanceMap[Def];
     297          84 :       if (Dist > LastPartDefDist)
     298             :         LastPartDefDist = Dist;
     299         288 :     } else if (MachineInstr *Use = PhysRegUse[SubReg]) {
     300         144 :       unsigned Dist = DistanceMap[Use];
     301         144 :       if (Dist > LastRefOrPartRefDist) {
     302             :         LastRefOrPartRefDist = Dist;
     303           0 :         LastRefOrPartRef = Use;
     304             :       }
     305             :     }
     306             :   }
     307             : 
     308         362 :   return LastRefOrPartRef;
     309             : }
     310             : 
     311     8585560 : bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
     312    17171120 :   MachineInstr *LastDef = PhysRegDef[Reg];
     313    17171120 :   MachineInstr *LastUse = PhysRegUse[Reg];
     314     8585560 :   if (!LastDef && !LastUse)
     315             :     return false;
     316             : 
     317     7711518 :   MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
     318    15423036 :   unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
     319             :   // The whole register is used.
     320             :   // AL =
     321             :   // AH =
     322             :   //
     323             :   //    = AX
     324             :   //    = AL, implicit killed AX
     325             :   // AX =
     326             :   //
     327             :   // Or whole register is defined, but not used at all.
     328             :   // dead AX =
     329             :   // ...
     330             :   // AX =
     331             :   //
     332             :   // Or whole register is defined, but only partly used.
     333             :   // dead AX = implicit-def AL
     334             :   //    = killed AL
     335             :   // AX =
     336             :   MachineInstr *LastPartDef = nullptr;
     337             :   unsigned LastPartDefDist = 0;
     338     7711518 :   SmallSet<unsigned, 8> PartUses;
     339    26168320 :   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
     340             :     unsigned SubReg = *SubRegs;
     341    21490568 :     MachineInstr *Def = PhysRegDef[SubReg];
     342    10745284 :     if (Def && Def != LastDef) {
     343             :       // There was a def of this sub-register in between. This is a partial
     344             :       // def, keep track of the last one.
     345       72810 :       unsigned Dist = DistanceMap[Def];
     346       72810 :       if (Dist > LastPartDefDist) {
     347             :         LastPartDefDist = Dist;
     348       25231 :         LastPartDef = Def;
     349             :       }
     350       72810 :       continue;
     351             :     }
     352    21344948 :     if (MachineInstr *Use = PhysRegUse[SubReg]) {
     353    38985869 :       for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true); SS.isValid();
     354             :            ++SS)
     355    18100827 :         PartUses.insert(*SS);
     356    10442521 :       unsigned Dist = DistanceMap[Use];
     357    10442521 :       if (Dist > LastRefOrPartRefDist) {
     358             :         LastRefOrPartRefDist = Dist;
     359         362 :         LastRefOrPartRef = Use;
     360             :       }
     361             :     }
     362             :   }
     363             : 
     364    15423036 :   if (!PhysRegUse[Reg]) {
     365             :     // Partial uses. Mark register def dead and add implicit def of
     366             :     // sub-registers which are used.
     367             :     // dead EAX  = op  implicit-def AL
     368             :     // That is, EAX def is dead but AL def extends pass it.
     369     1853742 :     PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
     370     2087919 :     for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
     371      234177 :       unsigned SubReg = *SubRegs;
     372      234177 :       if (!PartUses.count(SubReg))
     373      233815 :         continue;
     374             :       bool NeedDef = true;
     375        1086 :       if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
     376             :         MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
     377         362 :         if (MO) {
     378             :           NeedDef = false;
     379             :           assert(!MO->isDead());
     380             :         }
     381             :       }
     382             :       if (NeedDef)
     383           0 :         PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
     384           0 :                                                  true/*IsDef*/, true/*IsImp*/));
     385         362 :       MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
     386         362 :       if (LastSubRef)
     387         362 :         LastSubRef->addRegisterKilled(SubReg, TRI, true);
     388             :       else {
     389           0 :         LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
     390           0 :         for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true);
     391           0 :              SS.isValid(); ++SS)
     392           0 :           PhysRegUse[*SS] = LastRefOrPartRef;
     393             :       }
     394         952 :       for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
     395         228 :         PartUses.erase(*SS);
     396             :     }
     397    13569294 :   } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
     398           0 :     if (LastPartDef)
     399             :       // The last partial def kills the register.
     400           0 :       LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
     401             :                                                 true/*IsImp*/, true/*IsKill*/));
     402             :     else {
     403             :       MachineOperand *MO =
     404           0 :         LastRefOrPartRef->findRegisterDefOperand(Reg, false, TRI);
     405           0 :       bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
     406             :       // If the last reference is the last def, then it's not used at all.
     407             :       // That is, unless we are currently processing the last reference itself.
     408           0 :       LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
     409           0 :       if (NeedEC) {
     410             :         // If we are adding a subreg def and the superreg def is marked early
     411             :         // clobber, add an early clobber marker to the subreg def.
     412           0 :         MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
     413           0 :         if (MO)
     414             :           MO->setIsEarlyClobber();
     415             :       }
     416             :     }
     417             :   } else
     418     6784647 :     LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
     419             :   return true;
     420             : }
     421             : 
     422      156688 : void LiveVariables::HandleRegMask(const MachineOperand &MO) {
     423             :   // Call HandlePhysRegKill() for all live registers clobbered by Mask.
     424             :   // Clobbered registers are always dead, sp there is no need to use
     425             :   // HandlePhysRegDef().
     426    43277442 :   for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
     427             :     // Skip dead regs.
     428   127630412 :     if (!PhysRegDef[Reg] && !PhysRegUse[Reg])
     429    41176903 :       continue;
     430             :     // Skip mask-preserved regs.
     431     1943851 :     if (!MO.clobbersPhysReg(Reg))
     432      331887 :       continue;
     433             :     // Kill the largest clobbered super-register.
     434             :     // This avoids needless implicit operands.
     435             :     unsigned Super = Reg;
     436     6150788 :     for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
     437     9096928 :       if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR))
     438             :         Super = *SR;
     439     1611964 :     HandlePhysRegKill(Super, nullptr);
     440             :   }
     441      156688 : }
     442             : 
     443     3938804 : void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
     444             :                                      SmallVectorImpl<unsigned> &Defs) {
     445             :   // What parts of the register are previously defined?
     446     3938804 :   SmallSet<unsigned, 32> Live;
     447     9523265 :   if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
     448     6129524 :     for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
     449     9157189 :          SubRegs.isValid(); ++SubRegs)
     450     6092427 :       Live.insert(*SubRegs);
     451             :   } else {
     452     4238036 :     for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
     453     1615910 :       unsigned SubReg = *SubRegs;
     454             :       // If a register isn't itself defined, but all parts that make up of it
     455             :       // are defined, then consider it also defined.
     456             :       // e.g.
     457             :       // AL =
     458             :       // AH =
     459             :       //    = AX
     460     1615910 :       if (Live.count(SubReg))
     461        3076 :         continue;
     462     4837482 :       if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
     463        4051 :         for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true);
     464       11226 :              SS.isValid(); ++SS)
     465        7175 :           Live.insert(*SS);
     466             :       }
     467             :     }
     468             :   }
     469             : 
     470             :   // Start from the largest piece, find the last time any part of the register
     471             :   // is referenced.
     472     3938804 :   HandlePhysRegKill(Reg, MI);
     473             :   // Only some of the sub-registers are used.
     474    12521183 :   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
     475     4643575 :     unsigned SubReg = *SubRegs;
     476     4643575 :     if (!Live.count(SubReg))
     477             :       // Skip if this sub-register isn't defined.
     478     1608783 :       continue;
     479     3034792 :     HandlePhysRegKill(SubReg, MI);
     480             :   }
     481             : 
     482     3938804 :   if (MI)
     483     1229637 :     Defs.push_back(Reg);  // Remember this def.
     484     3938804 : }
     485             : 
     486     3959721 : void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,
     487             :                                       SmallVectorImpl<unsigned> &Defs) {
     488     6418995 :   while (!Defs.empty()) {
     489     1229637 :     unsigned Reg = Defs.back();
     490             :     Defs.pop_back();
     491     1229637 :     for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
     492     3820325 :          SubRegs.isValid(); ++SubRegs) {
     493             :       unsigned SubReg = *SubRegs;
     494     5181376 :       PhysRegDef[SubReg] = &MI;
     495     5181376 :       PhysRegUse[SubReg]  = nullptr;
     496             :     }
     497             :   }
     498     3959721 : }
     499             : 
     500     3959721 : void LiveVariables::runOnInstr(MachineInstr &MI,
     501             :                                SmallVectorImpl<unsigned> &Defs) {
     502             :   assert(!MI.isDebugInstr());
     503             :   // Process all of the operands of the instruction...
     504     3959721 :   unsigned NumOperandsToProcess = MI.getNumOperands();
     505             : 
     506             :   // Unless it is a PHI node.  In this case, ONLY process the DEF, not any
     507             :   // of the uses.  They will be handled in other basic blocks.
     508             :   if (MI.isPHI())
     509             :     NumOperandsToProcess = 1;
     510             : 
     511             :   // Clear kill and dead markers. LV will recompute them.
     512             :   SmallVector<unsigned, 4> UseRegs;
     513             :   SmallVector<unsigned, 4> DefRegs;
     514             :   SmallVector<unsigned, 1> RegMasks;
     515    20432429 :   for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
     516    16472708 :     MachineOperand &MO = MI.getOperand(i);
     517    16629396 :     if (MO.isRegMask()) {
     518      156688 :       RegMasks.push_back(i);
     519     7056594 :       continue;
     520             :     }
     521    23059238 :     if (!MO.isReg() || MO.getReg() == 0)
     522     6743218 :       continue;
     523     9572802 :     unsigned MOReg = MO.getReg();
     524     9572802 :     if (MO.isUse()) {
     525     7898904 :       if (!(TargetRegisterInfo::isPhysicalRegister(MOReg) &&
     526     2466902 :             MRI->isReserved(MOReg)))
     527             :         MO.setIsKill(false);
     528             :       if (MO.readsReg())
     529     5393003 :         UseRegs.push_back(MOReg);
     530             :     } else {
     531             :       assert(MO.isDef());
     532             :       // FIXME: We should not remove any dead flags. However the MIPS RDDSP
     533             :       // instruction needs it at the moment: http://llvm.org/PR27116.
     534     6291882 :       if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
     535     2151082 :           !MRI->isReserved(MOReg))
     536             :         MO.setIsDead(false);
     537     4140800 :       DefRegs.push_back(MOReg);
     538             :     }
     539             :   }
     540             : 
     541     3959721 :   MachineBasicBlock *MBB = MI.getParent();
     542             :   // Process all uses.
     543     9352724 :   for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
     544    10786006 :     unsigned MOReg = UseRegs[i];
     545     5393003 :     if (TargetRegisterInfo::isVirtualRegister(MOReg))
     546     2927837 :       HandleVirtRegUse(MOReg, MBB, MI);
     547     4930332 :     else if (!MRI->isReserved(MOReg))
     548      951668 :       HandlePhysRegUse(MOReg, MI);
     549             :   }
     550             : 
     551             :   // Process all masked registers. (Call clobbers).
     552     4116409 :   for (unsigned i = 0, e = RegMasks.size(); i != e; ++i)
     553      470064 :     HandleRegMask(MI.getOperand(RegMasks[i]));
     554             : 
     555             :   // Process all defs.
     556     8100521 :   for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
     557     8281600 :     unsigned MOReg = DefRegs[i];
     558     4140800 :     if (TargetRegisterInfo::isVirtualRegister(MOReg))
     559     1989718 :       HandleVirtRegDef(MOReg, MI);
     560     4302164 :     else if (!MRI->isReserved(MOReg))
     561     1229637 :       HandlePhysRegDef(MOReg, &MI, Defs);
     562             :   }
     563     3959721 :   UpdatePhysRegDefs(MI, Defs);
     564     3959721 : }
     565             : 
     566      352619 : void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
     567             :   // Mark live-in registers as live-in.
     568             :   SmallVector<unsigned, 4> Defs;
     569      708086 :   for (const auto &LI : MBB->liveins()) {
     570             :     assert(TargetRegisterInfo::isPhysicalRegister(LI.PhysReg) &&
     571             :            "Cannot have a live-in virtual register!");
     572      355467 :     HandlePhysRegDef(LI.PhysReg, nullptr, Defs);
     573             :   }
     574             : 
     575             :   // Loop over all of the instructions, processing them.
     576      352619 :   DistanceMap.clear();
     577             :   unsigned Dist = 0;
     578     4698744 :   for (MachineInstr &MI : *MBB) {
     579       33785 :     if (MI.isDebugInstr())
     580       33785 :       continue;
     581     7919442 :     DistanceMap.insert(std::make_pair(&MI, Dist++));
     582             : 
     583     3959721 :     runOnInstr(MI, Defs);
     584             :   }
     585             : 
     586             :   // Handle any virtual assignments from PHI nodes which might be at the
     587             :   // bottom of this basic block.  We check all of our successor blocks to see
     588             :   // if they have PHI nodes, and if so, we simulate an assignment at the end
     589             :   // of the current block.
     590      705238 :   if (!PHIVarInfo[MBB->getNumber()].empty()) {
     591             :     SmallVectorImpl<unsigned> &VarInfoVec = PHIVarInfo[MBB->getNumber()];
     592             : 
     593       80439 :     for (SmallVectorImpl<unsigned>::iterator I = VarInfoVec.begin(),
     594      139014 :            E = VarInfoVec.end(); I != E; ++I)
     595             :       // Mark it alive only in the block we are representing.
     596       80439 :       MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
     597             :                               MBB);
     598             :   }
     599             : 
     600             :   // MachineCSE may CSE instructions which write to non-allocatable physical
     601             :   // registers across MBBs. Remember if any reserved register is liveout.
     602      352619 :   SmallSet<unsigned, 4> LiveOuts;
     603             :   for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
     604      580612 :          SE = MBB->succ_end(); SI != SE; ++SI) {
     605      227993 :     MachineBasicBlock *SuccMBB = *SI;
     606      227993 :     if (SuccMBB->isEHPad())
     607       28221 :       continue;
     608      200291 :     for (const auto &LI : SuccMBB->liveins()) {
     609        1038 :       if (!TRI->isInAllocatableClass(LI.PhysReg))
     610             :         // Ignore other live-ins, e.g. those that are live into landing pads.
     611         509 :         LiveOuts.insert(LI.PhysReg);
     612             :     }
     613             :   }
     614             : 
     615             :   // Loop over PhysRegDef / PhysRegUse, killing any registers that are
     616             :   // available at the end of the basic block.
     617   172338564 :   for (unsigned i = 0; i != NumRegs; ++i)
     618   514281115 :     if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(i))
     619     2353700 :       HandlePhysRegDef(i, nullptr, Defs);
     620      352619 : }
     621             : 
     622      189029 : bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
     623      189029 :   MF = &mf;
     624      189029 :   MRI = &mf.getRegInfo();
     625      189029 :   TRI = MF->getSubtarget().getRegisterInfo();
     626             : 
     627      189029 :   const unsigned NumRegs = TRI->getNumRegs();
     628      378058 :   PhysRegDef.assign(NumRegs, nullptr);
     629      378058 :   PhysRegUse.assign(NumRegs, nullptr);
     630      378058 :   PHIVarInfo.resize(MF->getNumBlockIDs());
     631             :   PHIJoins.clear();
     632             : 
     633             :   // FIXME: LiveIntervals will be updated to remove its dependence on
     634             :   // LiveVariables to improve compilation time and eliminate bizarre pass
     635             :   // dependencies. Until then, we can't change much in -O0.
     636      378058 :   if (!MRI->isSSA())
     637           0 :     report_fatal_error("regalloc=... not currently supported with -O0");
     638             : 
     639      189029 :   analyzePHINodes(mf);
     640             : 
     641             :   // Calculate live variable information in depth first order on the CFG of the
     642             :   // function.  This guarantees that we will see the definition of a virtual
     643             :   // register before its uses due to dominance properties of SSA (except for PHI
     644             :   // nodes, which are treated as a special case).
     645      378058 :   MachineBasicBlock *Entry = &MF->front();
     646             :   df_iterator_default_set<MachineBasicBlock*,16> Visited;
     647             : 
     648     1272325 :   for (MachineBasicBlock *MBB : depth_first_ext(Entry, Visited)) {
     649      352619 :     runOnBlock(MBB, NumRegs);
     650             : 
     651      705238 :     PhysRegDef.assign(NumRegs, nullptr);
     652      705238 :     PhysRegUse.assign(NumRegs, nullptr);
     653             :   }
     654             : 
     655             :   // Convert and transfer the dead / killed information we have gathered into
     656             :   // VirtRegInfo onto MI's.
     657     2771773 :   for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
     658             :     const unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
     659     7086365 :     for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
     660     5762631 :       if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
     661       23978 :         VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
     662             :       else
     663     3817776 :         VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
     664             :   }
     665             : 
     666             :   // Check to make sure there are no unreachable blocks in the MC CFG for the
     667             :   // function.  If so, it is due to a bug in the instruction selector or some
     668             :   // other part of the code generator if this happens.
     669             : #ifndef NDEBUG
     670             :   for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
     671             :     assert(Visited.count(&*i) != 0 && "unreachable basic block found");
     672             : #endif
     673             : 
     674             :   PhysRegDef.clear();
     675             :   PhysRegUse.clear();
     676      189029 :   PHIVarInfo.clear();
     677             : 
     678      189029 :   return false;
     679             : }
     680             : 
     681             : /// replaceKillInstruction - Update register kill info by replacing a kill
     682             : /// instruction with a new one.
     683      113705 : void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr &OldMI,
     684             :                                            MachineInstr &NewMI) {
     685      113705 :   VarInfo &VI = getVarInfo(Reg);
     686             :   std::replace(VI.Kills.begin(), VI.Kills.end(), &OldMI, &NewMI);
     687      113705 : }
     688             : 
     689             : /// removeVirtualRegistersKilled - Remove all killed info for the specified
     690             : /// instruction.
     691       36892 : void LiveVariables::removeVirtualRegistersKilled(MachineInstr &MI) {
     692      234584 :   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     693      197692 :     MachineOperand &MO = MI.getOperand(i);
     694      314984 :     if (MO.isReg() && MO.isKill()) {
     695             :       MO.setIsKill(false);
     696           0 :       unsigned Reg = MO.getReg();
     697           0 :       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
     698           0 :         bool removed = getVarInfo(Reg).removeKill(MI);
     699             :         assert(removed && "kill not in register's VarInfo?");
     700             :         (void)removed;
     701             :       }
     702             :     }
     703             :   }
     704       36892 : }
     705             : 
     706             : /// analyzePHINodes - Gather information about the PHI nodes in here. In
     707             : /// particular, we want to map the variable information of a virtual register
     708             : /// which is used in a PHI node. We map that to the BB the vreg is coming from.
     709             : ///
     710      189029 : void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
     711      541648 :   for (const auto &MBB : Fn)
     712      742913 :     for (const auto &BBI : MBB) {
     713             :       if (!BBI.isPHI())
     714             :         break;
     715      119736 :       for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
     716       82061 :         if (BBI.getOperand(i).readsReg())
     717      160878 :           PHIVarInfo[BBI.getOperand(i + 1).getMBB()->getNumber()]
     718       80439 :             .push_back(BBI.getOperand(i).getReg());
     719             :     }
     720      189029 : }
     721             : 
     722        2999 : bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
     723             :                                       unsigned Reg,
     724             :                                       MachineRegisterInfo &MRI) {
     725        2999 :   unsigned Num = MBB.getNumber();
     726             : 
     727             :   // Reg is live-through.
     728        2999 :   if (AliveBlocks.test(Num))
     729             :     return true;
     730             : 
     731             :   // Registers defined in MBB cannot be live in.
     732        2187 :   const MachineInstr *Def = MRI.getVRegDef(Reg);
     733        2187 :   if (Def && Def->getParent() == &MBB)
     734             :     return false;
     735             : 
     736             :  // Reg was not defined in MBB, was it killed here?
     737        2185 :   return findKill(&MBB);
     738             : }
     739             : 
     740       85632 : bool LiveVariables::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) {
     741       85632 :   LiveVariables::VarInfo &VI = getVarInfo(Reg);
     742             : 
     743             :   SmallPtrSet<const MachineBasicBlock *, 8> Kills;
     744      180813 :   for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
     745       19098 :     Kills.insert(VI.Kills[i]->getParent());
     746             : 
     747             :   // Loop over all of the successors of the basic block, checking to see if
     748             :   // the value is either live in the block, or if it is killed in the block.
     749      192803 :   for (const MachineBasicBlock *SuccMBB : MBB.successors()) {
     750             :     // Is it alive in this successor?
     751      113967 :     unsigned SuccIdx = SuccMBB->getNumber();
     752      113967 :     if (VI.AliveBlocks.test(SuccIdx))
     753             :       return true;
     754             :     // Or is it live because there is a use in a successor that kills it?
     755      109570 :     if (Kills.count(SuccMBB))
     756             :       return true;
     757             :   }
     758             : 
     759             :   return false;
     760             : }
     761             : 
     762             : /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
     763             : /// variables that are live out of DomBB will be marked as passing live through
     764             : /// BB.
     765        2035 : void LiveVariables::addNewBlock(MachineBasicBlock *BB,
     766             :                                 MachineBasicBlock *DomBB,
     767             :                                 MachineBasicBlock *SuccBB) {
     768        2035 :   const unsigned NumNew = BB->getNumber();
     769             : 
     770             :   DenseSet<unsigned> Defs, Kills;
     771             : 
     772        2035 :   MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end();
     773        5253 :   for (; BBI != BBE && BBI->isPHI(); ++BBI) {
     774             :     // Record the def of the PHI node.
     775        6436 :     Defs.insert(BBI->getOperand(0).getReg());
     776             : 
     777             :     // All registers used by PHI nodes in SuccBB must be live through BB.
     778       16411 :     for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
     779       26386 :       if (BBI->getOperand(i+1).getMBB() == BB)
     780        3224 :         getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
     781             :   }
     782             : 
     783             :   // Record all vreg defs and kills of all instructions in SuccBB.
     784       17120 :   for (; BBI != BBE; ++BBI) {
     785       73502 :     for (MachineInstr::mop_iterator I = BBI->operands_begin(),
     786       88587 :          E = BBI->operands_end(); I != E; ++I) {
     787       98298 :       if (I->isReg() && TargetRegisterInfo::isVirtualRegister(I->getReg())) {
     788       18466 :         if (I->isDef())
     789       11394 :           Defs.insert(I->getReg());
     790       12769 :         else if (I->isKill())
     791       14804 :           Kills.insert(I->getReg());
     792             :       }
     793             :     }
     794             :   }
     795             : 
     796             :   // Update info for all live variables
     797      787546 :   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
     798      391738 :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
     799             : 
     800             :     // If the Defs is defined in the successor it can't be live in BB.
     801        8915 :     if (Defs.count(Reg))
     802        8915 :       continue;
     803             : 
     804             :     // If the register is either killed in or live through SuccBB it's also live
     805             :     // through BB.
     806      382823 :     VarInfo &VI = getVarInfo(Reg);
     807      381659 :     if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))
     808        9657 :       VI.AliveBlocks.set(NumNew);
     809             :   }
     810        2035 : }

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