LCOV - code coverage report
Current view: top level - lib/CodeGen/MIRParser - MIParser.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 2 2 100.0 %
Date: 2018-07-13 00:08:38 Functions: 1 1 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- MIParser.h - Machine Instructions Parser -----------------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file declares the function that parses the machine instructions.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
      15             : #define LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
      16             : 
      17             : #include "llvm/ADT/DenseMap.h"
      18             : #include "llvm/ADT/StringMap.h"
      19             : #include "llvm/Support/Allocator.h"
      20             : 
      21             : namespace llvm {
      22             : 
      23             : class MachineBasicBlock;
      24             : class MachineFunction;
      25             : class MDNode;
      26             : class RegisterBank;
      27             : struct SlotMapping;
      28             : class SMDiagnostic;
      29             : class SourceMgr;
      30             : class StringRef;
      31             : class TargetRegisterClass;
      32             : 
      33       14602 : struct VRegInfo {
      34             :   enum uint8_t {
      35             :     UNKNOWN, NORMAL, GENERIC, REGBANK
      36             :   } Kind = UNKNOWN;
      37             :   bool Explicit = false; ///< VReg was explicitly specified in the .mir file.
      38             :   union {
      39             :     const TargetRegisterClass *RC;
      40             :     const RegisterBank *RegBank;
      41             :   } D;
      42             :   unsigned VReg;
      43             :   unsigned PreferredReg = 0;
      44             : };
      45             : 
      46             : using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
      47             : using Name2RegBankMap = StringMap<const RegisterBank *>;
      48             : 
      49       11964 : struct PerFunctionMIParsingState {
      50             :   BumpPtrAllocator Allocator;
      51             :   MachineFunction &MF;
      52             :   SourceMgr *SM;
      53             :   const SlotMapping &IRSlots;
      54             :   const Name2RegClassMap &Names2RegClasses;
      55             :   const Name2RegBankMap &Names2RegBanks;
      56             : 
      57             :   DenseMap<unsigned, MachineBasicBlock *> MBBSlots;
      58             :   DenseMap<unsigned, VRegInfo*> VRegInfos;
      59             :   StringMap<VRegInfo*> VRegInfosNamed;
      60             :   DenseMap<unsigned, int> FixedStackObjectSlots;
      61             :   DenseMap<unsigned, int> StackObjectSlots;
      62             :   DenseMap<unsigned, unsigned> ConstantPoolSlots;
      63             :   DenseMap<unsigned, unsigned> JumpTableSlots;
      64             : 
      65             :   PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM,
      66             :                             const SlotMapping &IRSlots,
      67             :                             const Name2RegClassMap &Names2RegClasses,
      68             :                             const Name2RegBankMap &Names2RegBanks);
      69             : 
      70             :   VRegInfo &getVRegInfo(unsigned VReg);
      71             :   VRegInfo &getVRegInfoNamed(StringRef RegName);
      72             : };
      73             : 
      74             : /// Parse the machine basic block definitions, and skip the machine
      75             : /// instructions.
      76             : ///
      77             : /// This function runs the first parsing pass on the machine function's body.
      78             : /// It parses only the machine basic block definitions and creates the machine
      79             : /// basic blocks in the given machine function.
      80             : ///
      81             : /// The machine instructions aren't parsed during the first pass because all
      82             : /// the machine basic blocks aren't defined yet - this makes it impossible to
      83             : /// resolve the machine basic block references.
      84             : ///
      85             : /// Return true if an error occurred.
      86             : bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS,
      87             :                                        StringRef Src, SMDiagnostic &Error);
      88             : 
      89             : /// Parse the machine instructions.
      90             : ///
      91             : /// This function runs the second parsing pass on the machine function's body.
      92             : /// It skips the machine basic block definitions and parses only the machine
      93             : /// instructions and basic block attributes like liveins and successors.
      94             : ///
      95             : /// The second parsing pass assumes that the first parsing pass already ran
      96             : /// on the given source string.
      97             : ///
      98             : /// Return true if an error occurred.
      99             : bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src,
     100             :                               SMDiagnostic &Error);
     101             : 
     102             : bool parseMBBReference(PerFunctionMIParsingState &PFS,
     103             :                        MachineBasicBlock *&MBB, StringRef Src,
     104             :                        SMDiagnostic &Error);
     105             : 
     106             : bool parseRegisterReference(PerFunctionMIParsingState &PFS,
     107             :                             unsigned &Reg, StringRef Src,
     108             :                             SMDiagnostic &Error);
     109             : 
     110             : bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,
     111             :                                  StringRef Src, SMDiagnostic &Error);
     112             : 
     113             : bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,
     114             :                                    VRegInfo *&Info, StringRef Src,
     115             :                                    SMDiagnostic &Error);
     116             : 
     117             : bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI,
     118             :                                StringRef Src, SMDiagnostic &Error);
     119             : 
     120             : bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src,
     121             :                  SMDiagnostic &Error);
     122             : 
     123             : } // end namespace llvm
     124             : 
     125             : #endif // LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H

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