LCOV - code coverage report
Current view: top level - lib/CodeGen - MachineInstr.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 613 694 88.3 %
Date: 2018-02-18 16:14:26 Functions: 74 74 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // Methods common to all machine instructions.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "llvm/CodeGen/MachineInstr.h"
      15             : #include "llvm/ADT/APFloat.h"
      16             : #include "llvm/ADT/ArrayRef.h"
      17             : #include "llvm/ADT/FoldingSet.h"
      18             : #include "llvm/ADT/Hashing.h"
      19             : #include "llvm/ADT/None.h"
      20             : #include "llvm/ADT/STLExtras.h"
      21             : #include "llvm/ADT/SmallBitVector.h"
      22             : #include "llvm/ADT/SmallString.h"
      23             : #include "llvm/ADT/SmallVector.h"
      24             : #include "llvm/Analysis/AliasAnalysis.h"
      25             : #include "llvm/Analysis/Loads.h"
      26             : #include "llvm/Analysis/MemoryLocation.h"
      27             : #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
      28             : #include "llvm/CodeGen/MachineBasicBlock.h"
      29             : #include "llvm/CodeGen/MachineFunction.h"
      30             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      31             : #include "llvm/CodeGen/MachineInstrBundle.h"
      32             : #include "llvm/CodeGen/MachineMemOperand.h"
      33             : #include "llvm/CodeGen/MachineModuleInfo.h"
      34             : #include "llvm/CodeGen/MachineOperand.h"
      35             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      36             : #include "llvm/CodeGen/PseudoSourceValue.h"
      37             : #include "llvm/CodeGen/TargetInstrInfo.h"
      38             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      39             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      40             : #include "llvm/IR/Constants.h"
      41             : #include "llvm/IR/DebugInfoMetadata.h"
      42             : #include "llvm/IR/DebugLoc.h"
      43             : #include "llvm/IR/DerivedTypes.h"
      44             : #include "llvm/IR/Function.h"
      45             : #include "llvm/IR/InlineAsm.h"
      46             : #include "llvm/IR/InstrTypes.h"
      47             : #include "llvm/IR/Intrinsics.h"
      48             : #include "llvm/IR/LLVMContext.h"
      49             : #include "llvm/IR/Metadata.h"
      50             : #include "llvm/IR/Module.h"
      51             : #include "llvm/IR/ModuleSlotTracker.h"
      52             : #include "llvm/IR/Type.h"
      53             : #include "llvm/IR/Value.h"
      54             : #include "llvm/MC/MCInstrDesc.h"
      55             : #include "llvm/MC/MCRegisterInfo.h"
      56             : #include "llvm/MC/MCSymbol.h"
      57             : #include "llvm/Support/Casting.h"
      58             : #include "llvm/Support/CommandLine.h"
      59             : #include "llvm/Support/Compiler.h"
      60             : #include "llvm/Support/Debug.h"
      61             : #include "llvm/Support/ErrorHandling.h"
      62             : #include "llvm/Support/LowLevelTypeImpl.h"
      63             : #include "llvm/Support/MathExtras.h"
      64             : #include "llvm/Support/raw_ostream.h"
      65             : #include "llvm/Target/TargetIntrinsicInfo.h"
      66             : #include "llvm/Target/TargetMachine.h"
      67             : #include <algorithm>
      68             : #include <cassert>
      69             : #include <cstddef>
      70             : #include <cstdint>
      71             : #include <cstring>
      72             : #include <iterator>
      73             : #include <utility>
      74             : 
      75             : using namespace llvm;
      76             : 
      77             : static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
      78       52680 :   if (const MachineBasicBlock *MBB = MI.getParent())
      79       52678 :     if (const MachineFunction *MF = MBB->getParent())
      80             :       return MF;
      81             :   return nullptr;
      82             : }
      83             : 
      84             : // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
      85             : // it.
      86       52609 : static void tryToGetTargetInfo(const MachineInstr &MI,
      87             :                                const TargetRegisterInfo *&TRI,
      88             :                                const MachineRegisterInfo *&MRI,
      89             :                                const TargetIntrinsicInfo *&IntrinsicInfo,
      90             :                                const TargetInstrInfo *&TII) {
      91             : 
      92             :   if (const MachineFunction *MF = getMFIfAvailable(MI)) {
      93       52608 :     TRI = MF->getSubtarget().getRegisterInfo();
      94       52608 :     MRI = &MF->getRegInfo();
      95       52608 :     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
      96       52608 :     TII = MF->getSubtarget().getInstrInfo();
      97             :   }
      98       52609 : }
      99             : 
     100     8137574 : void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
     101     8137574 :   if (MCID->ImplicitDefs)
     102     6444258 :     for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
     103             :            ++ImpDefs)
     104     5049402 :       addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
     105     8137574 :   if (MCID->ImplicitUses)
     106     6584860 :     for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
     107             :            ++ImpUses)
     108     4932528 :       addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
     109     8137574 : }
     110             : 
     111             : /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
     112             : /// implicit operands. It reserves space for the number of operands specified by
     113             : /// the MCInstrDesc.
     114     8080046 : MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
     115     8080046 :                            DebugLoc dl, bool NoImp)
     116    16160092 :     : MCID(&tid), debugLoc(std::move(dl)) {
     117             :   assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
     118             : 
     119             :   // Reserve space for the expected number of operands.
     120    24240138 :   if (unsigned NumOps = MCID->getNumOperands() +
     121     8080046 :     MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
     122    15562686 :     CapOperands = OperandCapacity::get(NumOps);
     123     7781343 :     Operands = MF.allocateOperandArray(CapOperands);
     124             :   }
     125             : 
     126     8080046 :   if (!NoImp)
     127     8035452 :     addImplicitDefUseOperands(MF);
     128     8080046 : }
     129             : 
     130             : /// MachineInstr ctor - Copies MachineInstr arg exactly
     131             : ///
     132      151784 : MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
     133      303568 :     : MCID(&MI.getDesc()), NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
     134      607136 :       debugLoc(MI.getDebugLoc()) {
     135             :   assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
     136             : 
     137      303568 :   CapOperands = OperandCapacity::get(MI.getNumOperands());
     138      151784 :   Operands = MF.allocateOperandArray(CapOperands);
     139             : 
     140             :   // Copy operands.
     141      969606 :   for (const MachineOperand &MO : MI.operands())
     142      408911 :     addOperand(MF, MO);
     143             : 
     144             :   // Copy all the sensible flags.
     145      151784 :   setFlags(MI.Flags);
     146      151784 : }
     147             : 
     148             : /// getRegInfo - If this instruction is embedded into a MachineFunction,
     149             : /// return the MachineRegisterInfo object for the current function, otherwise
     150             : /// return null.
     151    31577893 : MachineRegisterInfo *MachineInstr::getRegInfo() {
     152    31577893 :   if (MachineBasicBlock *MBB = getParent())
     153    12849653 :     return &MBB->getParent()->getRegInfo();
     154             :   return nullptr;
     155             : }
     156             : 
     157             : /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
     158             : /// this instruction from their respective use lists.  This requires that the
     159             : /// operands already be on their use lists.
     160     4082736 : void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
     161    29420122 :   for (MachineOperand &MO : operands())
     162    12668693 :     if (MO.isReg())
     163     9471818 :       MRI.removeRegOperandFromUseList(&MO);
     164     4082736 : }
     165             : 
     166             : /// AddRegOperandsToUseLists - Add all of the register operands in
     167             : /// this instruction from their respective use lists.  This requires that the
     168             : /// operands not be on their use lists yet.
     169     8234906 : void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
     170    45741248 :   for (MachineOperand &MO : operands())
     171    18753171 :     if (MO.isReg())
     172    12360337 :       MRI.addRegOperandToUseList(&MO);
     173     8234906 : }
     174             : 
     175     1167213 : void MachineInstr::addOperand(const MachineOperand &Op) {
     176             :   MachineBasicBlock *MBB = getParent();
     177             :   assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
     178             :   MachineFunction *MF = MBB->getParent();
     179             :   assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
     180     1167213 :   addOperand(*MF, Op);
     181     1167213 : }
     182             : 
     183             : /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
     184             : /// ranges. If MRI is non-null also update use-def chains.
     185     7293558 : static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
     186             :                          unsigned NumOps, MachineRegisterInfo *MRI) {
     187     7293558 :   if (MRI)
     188     2909875 :     return MRI->moveOperands(Dst, Src, NumOps);
     189             : 
     190             :   // MachineOperand is a trivially copyable type so we can just use memmove.
     191     4383683 :   std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
     192             : }
     193             : 
     194             : /// addOperand - Add the specified operand to the instruction.  If it is an
     195             : /// implicit operand, it is added to the end of the operand list.  If it is
     196             : /// an explicit operand it is added at the end of the explicit operand list
     197             : /// (before the first implicit operand).
     198    30961816 : void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
     199             :   assert(MCID && "Cannot add operands before providing an instr descriptor");
     200             : 
     201             :   // Check if we're adding one of our existing operands.
     202    30961816 :   if (&Op >= Operands && &Op < Operands + NumOperands) {
     203             :     // This is unusual: MI->addOperand(MI->getOperand(i)).
     204             :     // If adding Op requires reallocating or moving existing operands around,
     205             :     // the Op reference could go stale. Support it by copying Op.
     206         556 :     MachineOperand CopyOp(Op);
     207         556 :     return addOperand(MF, CopyOp);
     208             :   }
     209             : 
     210             :   // Find the insert location for the new operand.  Implicit registers go at
     211             :   // the end, everything else goes before the implicit regs.
     212             :   //
     213             :   // FIXME: Allow mixed explicit and implicit operands on inline asm.
     214             :   // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
     215             :   // implicit-defs, but they must not be moved around.  See the FIXME in
     216             :   // InstrEmitter.cpp.
     217             :   unsigned OpNo = getNumOperands();
     218    52353211 :   bool isImpReg = Op.isReg() && Op.isImplicit();
     219    23877680 :   if (!isImpReg && !isInlineAsm()) {
     220    87383097 :     while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
     221             :       --OpNo;
     222             :       assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
     223             :     }
     224             :   }
     225             : 
     226             : #ifndef NDEBUG
     227             :   bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
     228             :   // OpNo now points as the desired insertion point.  Unless this is a variadic
     229             :   // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
     230             :   // RegMask operands go between the explicit and implicit operands.
     231             :   assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
     232             :           OpNo < MCID->getNumOperands() || isMetaDataOp) &&
     233             :          "Trying to add an operand to a machine instr that is already done!");
     234             : #endif
     235             : 
     236    30961260 :   MachineRegisterInfo *MRI = getRegInfo();
     237             : 
     238             :   // Determine if the Operands array needs to be reallocated.
     239             :   // Save the old capacity and operand array.
     240    30961261 :   OperandCapacity OldCap = CapOperands;
     241    30961261 :   MachineOperand *OldOperands = Operands;
     242    61695257 :   if (!OldOperands || OldCap.getSize() == getNumOperands()) {
     243     3251783 :     CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
     244     1739524 :     Operands = MF.allocateOperandArray(CapOperands);
     245             :     // Move the operands before the insertion point.
     246     1739524 :     if (OpNo)
     247     1511081 :       moveOperands(Operands, OldOperands, OpNo, MRI);
     248             :   }
     249             : 
     250             :   // Move the operands following the insertion point.
     251    30961260 :   if (OpNo != NumOperands)
     252     5678484 :     moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
     253             :                  MRI);
     254    30961260 :   ++NumOperands;
     255             : 
     256             :   // Deallocate the old operand array.
     257    30961260 :   if (OldOperands != Operands && OldOperands)
     258             :     MF.deallocateOperandArray(OldCap, OldOperands);
     259             : 
     260             :   // Copy Op into place. It still needs to be inserted into the MRI use lists.
     261    30961260 :   MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
     262    30961260 :   NewMO->ParentMI = this;
     263             : 
     264             :   // When adding a register operand, tell MRI about it.
     265    30961260 :   if (NewMO->isReg()) {
     266             :     // Ensure isOnRegUseList() returns false, regardless of Op's status.
     267    21391950 :     NewMO->Contents.Reg.Prev = nullptr;
     268             :     // Ignore existing ties. This is not a property that can be copied.
     269    21391950 :     NewMO->TiedTo = 0;
     270             :     // Add the new operand to MRI, but only for instructions in an MBB.
     271    21391950 :     if (MRI)
     272     9046694 :       MRI->addRegOperandToUseList(NewMO);
     273             :     // The MCID operand information isn't accurate until we start adding
     274             :     // explicit operands. The implicit operands are added first, then the
     275             :     // explicits are inserted before them.
     276    21391951 :     if (!isImpReg) {
     277             :       // Tie uses to defs as indicated in MCInstrDesc.
     278    14308370 :       if (NewMO->isUse()) {
     279     9499944 :         int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
     280             :         if (DefIdx != -1)
     281      533247 :           tieOperands(DefIdx, OpNo);
     282             :       }
     283             :       // If the register operand is flagged as early, mark the operand as such.
     284    14308370 :       if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
     285             :         NewMO->setIsEarlyClobber(true);
     286             :     }
     287             :   }
     288             : }
     289             : 
     290             : /// RemoveOperand - Erase an operand  from an instruction, leaving it with one
     291             : /// fewer operand than it started with.
     292             : ///
     293      616632 : void MachineInstr::RemoveOperand(unsigned OpNo) {
     294             :   assert(OpNo < getNumOperands() && "Invalid operand number");
     295      616632 :   untieRegOperand(OpNo);
     296             : 
     297             : #ifndef NDEBUG
     298             :   // Moving tied operands would break the ties.
     299             :   for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
     300             :     if (Operands[i].isReg())
     301             :       assert(!Operands[i].isTied() && "Cannot move tied operands");
     302             : #endif
     303             : 
     304      616632 :   MachineRegisterInfo *MRI = getRegInfo();
     305     1233264 :   if (MRI && Operands[OpNo].isReg())
     306      564119 :     MRI->removeRegOperandFromUseList(Operands + OpNo);
     307             : 
     308             :   // Don't call the MachineOperand destructor. A lot of this code depends on
     309             :   // MachineOperand having a trivial destructor anyway, and adding a call here
     310             :   // wouldn't make it 'destructor-correct'.
     311             : 
     312      616632 :   if (unsigned N = NumOperands - 1 - OpNo)
     313      103993 :     moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
     314      616632 :   --NumOperands;
     315      616632 : }
     316             : 
     317             : /// addMemOperand - Add a MachineMemOperand to the machine instruction.
     318             : /// This function should be used only occasionally. The setMemRefs function
     319             : /// is the primary method for setting up a MachineInstr's MemRefs list.
     320      328101 : void MachineInstr::addMemOperand(MachineFunction &MF,
     321             :                                  MachineMemOperand *MO) {
     322      328101 :   mmo_iterator OldMemRefs = MemRefs;
     323      328101 :   unsigned OldNumMemRefs = NumMemRefs;
     324             : 
     325      328101 :   unsigned NewNum = NumMemRefs + 1;
     326      328101 :   mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
     327             : 
     328      328101 :   std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
     329      328101 :   NewMemRefs[NewNum - 1] = MO;
     330      328101 :   setMemRefs(NewMemRefs, NewMemRefs + NewNum);
     331      328101 : }
     332             : 
     333             : /// Check to see if the MMOs pointed to by the two MemRefs arrays are
     334             : /// identical.
     335       18386 : static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) {
     336             :   auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end();
     337             :   auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end();
     338       18386 :   if ((E1 - I1) != (E2 - I2))
     339             :     return false;
     340       50393 :   for (; I1 != E1; ++I1, ++I2) {
     341       43022 :     if (**I1 != **I2)
     342             :       return false;
     343             :   }
     344             :   return true;
     345             : }
     346             : 
     347             : std::pair<MachineInstr::mmo_iterator, unsigned>
     348       19102 : MachineInstr::mergeMemRefsWith(const MachineInstr& Other) {
     349             : 
     350             :   // If either of the incoming memrefs are empty, we must be conservative and
     351             :   // treat this as if we've exhausted our space for memrefs and dropped them.
     352       19102 :   if (memoperands_empty() || Other.memoperands_empty())
     353         716 :     return std::make_pair(nullptr, 0);
     354             : 
     355             :   // If both instructions have identical memrefs, we don't need to merge them.
     356             :   // Since many instructions have a single memref, and we tend to merge things
     357             :   // like pairs of loads from the same location, this catches a large number of
     358             :   // cases in practice.
     359       18386 :   if (hasIdenticalMMOs(*this, Other))
     360       12102 :     return std::make_pair(MemRefs, NumMemRefs);
     361             : 
     362             :   // TODO: consider uniquing elements within the operand lists to reduce
     363             :   // space usage and fall back to conservative information less often.
     364        6284 :   size_t CombinedNumMemRefs = NumMemRefs + Other.NumMemRefs;
     365             : 
     366             :   // If we don't have enough room to store this many memrefs, be conservative
     367             :   // and drop them.  Otherwise, we'd fail asserts when trying to add them to
     368             :   // the new instruction.
     369        6284 :   if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs))
     370           0 :     return std::make_pair(nullptr, 0);
     371             : 
     372             :   MachineFunction *MF = getMF();
     373        6284 :   mmo_iterator MemBegin = MF->allocateMemRefsArray(CombinedNumMemRefs);
     374             :   mmo_iterator MemEnd = std::copy(memoperands_begin(), memoperands_end(),
     375             :                                   MemBegin);
     376             :   MemEnd = std::copy(Other.memoperands_begin(), Other.memoperands_end(),
     377             :                      MemEnd);
     378             :   assert(MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs &&
     379             :          "missing memrefs");
     380             : 
     381        6284 :   return std::make_pair(MemBegin, CombinedNumMemRefs);
     382             : }
     383             : 
     384      218523 : bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
     385             :   assert(!isBundledWithPred() && "Must be called on bundle header");
     386      218523 :   for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
     387      399691 :     if (MII->getDesc().getFlags() & Mask) {
     388       73544 :       if (Type == AnyInBundle)
     389             :         return true;
     390             :     } else {
     391      331604 :       if (Type == AllInBundle && !MII->isBundle())
     392             :         return false;
     393             :     }
     394             :     // This was the last instruction in the bundle.
     395      320777 :     if (!MII->isBundledWithSucc())
     396      139609 :       return Type == AllInBundle;
     397             :   }
     398             : }
     399             : 
     400     6768599 : bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
     401             :                                  MICheckType Check) const {
     402             :   // If opcodes or number of operands are not the same then the two
     403             :   // instructions are obviously not identical.
     404     6768599 :   if (Other.getOpcode() != getOpcode() ||
     405             :       Other.getNumOperands() != getNumOperands())
     406             :     return false;
     407             : 
     408     5087393 :   if (isBundle()) {
     409             :     // We have passed the test above that both instructions have the same
     410             :     // opcode, so we know that both instructions are bundles here. Let's compare
     411             :     // MIs inside the bundle.
     412             :     assert(Other.isBundle() && "Expected that both instructions are bundles.");
     413           1 :     MachineBasicBlock::const_instr_iterator I1 = getIterator();
     414           1 :     MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
     415             :     // Loop until we analysed the last intruction inside at least one of the
     416             :     // bundles.
     417           3 :     while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
     418             :       ++I1;
     419             :       ++I2;
     420           2 :       if (!I1->isIdenticalTo(*I2, Check))
     421             :         return false;
     422             :     }
     423             :     // If we've reached the end of just one of the two bundles, but not both,
     424             :     // the instructions are not identical.
     425           2 :     if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
     426             :       return false;
     427             :   }
     428             : 
     429             :   // Check operands to make sure they match.
     430    47882203 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     431             :     const MachineOperand &MO = getOperand(i);
     432             :     const MachineOperand &OMO = Other.getOperand(i);
     433    29677633 :     if (!MO.isReg()) {
     434     7925414 :       if (!MO.isIdenticalTo(OMO))
     435             :         return false;
     436     6798509 :       continue;
     437             :     }
     438             : 
     439             :     // Clients may or may not want to ignore defs when testing for equality.
     440             :     // For example, machine CSE pass only cares about finding common
     441             :     // subexpressions, so it's safe to ignore virtual register defs.
     442    14953710 :     if (MO.isDef()) {
     443     6803762 :       if (Check == IgnoreDefs)
     444           0 :         continue;
     445     6803762 :       else if (Check == IgnoreVRegDefs) {
     446     8333302 :         if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()) ||
     447             :             !TargetRegisterInfo::isVirtualRegister(OMO.getReg()))
     448     3228393 :           if (!MO.isIdenticalTo(OMO))
     449             :             return false;
     450             :       } else {
     451     1023033 :         if (!MO.isIdenticalTo(OMO))
     452             :           return false;
     453     1023376 :         if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
     454             :           return false;
     455             :       }
     456             :     } else {
     457     8149948 :       if (!MO.isIdenticalTo(OMO))
     458             :         return false;
     459     7816369 :       if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
     460             :         return false;
     461             :     }
     462             :   }
     463             :   // If DebugLoc does not match then two dbg.values are not identical.
     464     3605674 :   if (isDebugValue())
     465        3422 :     if (getDebugLoc() && Other.getDebugLoc() &&
     466             :         getDebugLoc() != Other.getDebugLoc())
     467             :       return false;
     468             :   return true;
     469             : }
     470             : 
     471    17794931 : const MachineFunction *MachineInstr::getMF() const {
     472    17794931 :   return getParent()->getParent();
     473             : }
     474             : 
     475        1403 : MachineInstr *MachineInstr::removeFromParent() {
     476             :   assert(getParent() && "Not embedded in a basic block!");
     477        1403 :   return getParent()->remove(this);
     478             : }
     479             : 
     480           8 : MachineInstr *MachineInstr::removeFromBundle() {
     481             :   assert(getParent() && "Not embedded in a basic block!");
     482           8 :   return getParent()->remove_instr(this);
     483             : }
     484             : 
     485     2224771 : void MachineInstr::eraseFromParent() {
     486             :   assert(getParent() && "Not embedded in a basic block!");
     487             :   getParent()->erase(this);
     488     2224771 : }
     489             : 
     490      173459 : void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
     491             :   assert(getParent() && "Not embedded in a basic block!");
     492             :   MachineBasicBlock *MBB = getParent();
     493             :   MachineFunction *MF = MBB->getParent();
     494             :   assert(MF && "Not embedded in a function!");
     495             : 
     496             :   MachineInstr *MI = (MachineInstr *)this;
     497             :   MachineRegisterInfo &MRI = MF->getRegInfo();
     498             : 
     499      968547 :   for (const MachineOperand &MO : MI->operands()) {
     500      740193 :     if (!MO.isReg() || !MO.isDef())
     501      220596 :       continue;
     502             :     unsigned Reg = MO.getReg();
     503      176948 :     if (!TargetRegisterInfo::isVirtualRegister(Reg))
     504        3306 :       continue;
     505      173642 :     MRI.markUsesInDebugValueAsUndef(Reg);
     506             :   }
     507      173459 :   MI->eraseFromParent();
     508      173459 : }
     509             : 
     510      608492 : void MachineInstr::eraseFromBundle() {
     511             :   assert(getParent() && "Not embedded in a basic block!");
     512             :   getParent()->erase_instr(this);
     513      608493 : }
     514             : 
     515             : /// getNumExplicitOperands - Returns the number of non-implicit operands.
     516             : ///
     517    14691045 : unsigned MachineInstr::getNumExplicitOperands() const {
     518    14691045 :   unsigned NumOperands = MCID->getNumOperands();
     519    14691045 :   if (!MCID->isVariadic())
     520             :     return NumOperands;
     521             : 
     522        7641 :   for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
     523             :     const MachineOperand &MO = getOperand(i);
     524        4854 :     if (!MO.isReg() || !MO.isImplicit())
     525        3330 :       NumOperands++;
     526             :   }
     527             :   return NumOperands;
     528             : }
     529             : 
     530       47183 : void MachineInstr::bundleWithPred() {
     531             :   assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
     532             :   setFlag(BundledPred);
     533       47183 :   MachineBasicBlock::instr_iterator Pred = getIterator();
     534             :   --Pred;
     535             :   assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
     536             :   Pred->setFlag(BundledSucc);
     537       47183 : }
     538             : 
     539       19463 : void MachineInstr::bundleWithSucc() {
     540             :   assert(!isBundledWithSucc() && "MI is already bundled with its successor");
     541             :   setFlag(BundledSucc);
     542       19463 :   MachineBasicBlock::instr_iterator Succ = getIterator();
     543             :   ++Succ;
     544             :   assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
     545             :   Succ->setFlag(BundledPred);
     546       19463 : }
     547             : 
     548       38991 : void MachineInstr::unbundleFromPred() {
     549             :   assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
     550             :   clearFlag(BundledPred);
     551       38991 :   MachineBasicBlock::instr_iterator Pred = getIterator();
     552             :   --Pred;
     553             :   assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
     554             :   Pred->clearFlag(BundledSucc);
     555       38991 : }
     556             : 
     557           6 : void MachineInstr::unbundleFromSucc() {
     558             :   assert(isBundledWithSucc() && "MI isn't bundled with its successor");
     559             :   clearFlag(BundledSucc);
     560           6 :   MachineBasicBlock::instr_iterator Succ = getIterator();
     561             :   ++Succ;
     562             :   assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
     563             :   Succ->clearFlag(BundledPred);
     564           6 : }
     565             : 
     566     4981240 : bool MachineInstr::isStackAligningInlineAsm() const {
     567     4981240 :   if (isInlineAsm()) {
     568       11849 :     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
     569       11849 :     if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
     570             :       return true;
     571             :   }
     572             :   return false;
     573             : }
     574             : 
     575       15034 : InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
     576             :   assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
     577       15034 :   unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
     578       15034 :   return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
     579             : }
     580             : 
     581         147 : int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
     582             :                                        unsigned *GroupNo) const {
     583             :   assert(isInlineAsm() && "Expected an inline asm instruction");
     584             :   assert(OpIdx < getNumOperands() && "OpIdx out of range");
     585             : 
     586             :   // Ignore queries about the initial operands.
     587         147 :   if (OpIdx < InlineAsm::MIOp_FirstOperand)
     588             :     return -1;
     589             : 
     590             :   unsigned Group = 0;
     591             :   unsigned NumOps;
     592         465 :   for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
     593             :        i += NumOps) {
     594             :     const MachineOperand &FlagMO = getOperand(i);
     595             :     // If we reach the implicit register operands, stop looking.
     596         306 :     if (!FlagMO.isImm())
     597             :       return -1;
     598         612 :     NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
     599         306 :     if (i + NumOps > OpIdx) {
     600         147 :       if (GroupNo)
     601           0 :         *GroupNo = Group;
     602         147 :       return i;
     603             :     }
     604         159 :     ++Group;
     605             :   }
     606             :   return -1;
     607             : }
     608             : 
     609      264500 : const DILocalVariable *MachineInstr::getDebugVariable() const {
     610             :   assert(isDebugValue() && "not a DBG_VALUE");
     611      264500 :   return cast<DILocalVariable>(getOperand(2).getMetadata());
     612             : }
     613             : 
     614      178113 : const DIExpression *MachineInstr::getDebugExpression() const {
     615             :   assert(isDebugValue() && "not a DBG_VALUE");
     616      178113 :   return cast<DIExpression>(getOperand(3).getMetadata());
     617             : }
     618             : 
     619             : const TargetRegisterClass*
     620       54640 : MachineInstr::getRegClassConstraint(unsigned OpIdx,
     621             :                                     const TargetInstrInfo *TII,
     622             :                                     const TargetRegisterInfo *TRI) const {
     623             :   assert(getParent() && "Can't have an MBB reference here!");
     624             :   assert(getMF() && "Can't have an MF reference here!");
     625       54640 :   const MachineFunction &MF = *getMF();
     626             : 
     627             :   // Most opcodes have fixed constraints in their MCInstrDesc.
     628       54640 :   if (!isInlineAsm())
     629       54493 :     return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
     630             : 
     631         147 :   if (!getOperand(OpIdx).isReg())
     632             :     return nullptr;
     633             : 
     634             :   // For tied uses on inline asm, get the constraint from the def.
     635             :   unsigned DefIdx;
     636         147 :   if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
     637           1 :     OpIdx = DefIdx;
     638             : 
     639             :   // Inline asm stores register class constraints in the flag word.
     640         147 :   int FlagIdx = findInlineAsmFlagIdx(OpIdx);
     641         147 :   if (FlagIdx < 0)
     642             :     return nullptr;
     643             : 
     644         294 :   unsigned Flag = getOperand(FlagIdx).getImm();
     645             :   unsigned RCID;
     646          15 :   if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
     647           2 :        InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
     648         147 :        InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
     649             :       InlineAsm::hasRegClassConstraint(Flag, RCID))
     650         147 :     return TRI->getRegClass(RCID);
     651             : 
     652             :   // Assume that all registers in a memory operand are pointers.
     653           0 :   if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
     654           0 :     return TRI->getPointerRegClass(MF);
     655             : 
     656             :   return nullptr;
     657             : }
     658             : 
     659          45 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
     660             :     unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
     661             :     const TargetRegisterInfo *TRI, bool ExploreBundle) const {
     662             :   // Check every operands inside the bundle if we have
     663             :   // been asked to.
     664          45 :   if (ExploreBundle)
     665         325 :     for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
     666             :          ++OpndIt)
     667         280 :       CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
     668             :           OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
     669             :   else
     670             :     // Otherwise, just check the current operands.
     671           0 :     for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
     672           0 :       CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
     673          45 :   return CurRC;
     674             : }
     675             : 
     676         280 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
     677             :     unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
     678             :     const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
     679             :   assert(CurRC && "Invalid initial register class");
     680             :   // Check if Reg is constrained by some of its use/def from MI.
     681             :   const MachineOperand &MO = getOperand(OpIdx);
     682         280 :   if (!MO.isReg() || MO.getReg() != Reg)
     683             :     return CurRC;
     684             :   // If yes, accumulate the constraints through the operand.
     685          47 :   return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
     686             : }
     687             : 
     688       48482 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
     689             :     unsigned OpIdx, const TargetRegisterClass *CurRC,
     690             :     const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
     691       48482 :   const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
     692             :   const MachineOperand &MO = getOperand(OpIdx);
     693             :   assert(MO.isReg() &&
     694             :          "Cannot get register constraints for non-register operand");
     695             :   assert(CurRC && "Invalid initial register class");
     696       48482 :   if (unsigned SubIdx = MO.getSubReg()) {
     697       20110 :     if (OpRC)
     698       17315 :       CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
     699             :     else
     700        2795 :       CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
     701       28372 :   } else if (OpRC)
     702       19066 :     CurRC = TRI->getCommonSubClass(CurRC, OpRC);
     703       48482 :   return CurRC;
     704             : }
     705             : 
     706             : /// Return the number of instructions inside the MI bundle, not counting the
     707             : /// header instruction.
     708        1147 : unsigned MachineInstr::getBundleSize() const {
     709        1147 :   MachineBasicBlock::const_instr_iterator I = getIterator();
     710             :   unsigned Size = 0;
     711        4022 :   while (I->isBundledWithSucc()) {
     712        2875 :     ++Size;
     713             :     ++I;
     714             :   }
     715        1147 :   return Size;
     716             : }
     717             : 
     718             : /// Returns true if the MachineInstr has an implicit-use operand of exactly
     719             : /// the given register (not considering sub/super-registers).
     720     5551334 : bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const {
     721    56857392 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     722             :     const MachineOperand &MO = getOperand(i);
     723    65146438 :     if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
     724             :       return true;
     725             :   }
     726             :   return false;
     727             : }
     728             : 
     729             : /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
     730             : /// the specific register or -1 if it is not found. It further tightens
     731             : /// the search criteria to a use that kills the register if isKill is true.
     732     1915124 : int MachineInstr::findRegisterUseOperandIdx(
     733             :     unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
     734    21374858 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     735             :     const MachineOperand &MO = getOperand(i);
     736    16923927 :     if (!MO.isReg() || !MO.isUse())
     737     7190079 :       continue;
     738             :     unsigned MOReg = MO.getReg();
     739     3329579 :     if (!MOReg)
     740      465495 :       continue;
     741     4237363 :     if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
     742      466616 :                          TargetRegisterInfo::isPhysicalRegister(Reg) &&
     743      466616 :                          TRI->isSubRegister(MOReg, Reg)))
     744     1149395 :       if (!isKill || MO.isKill())
     745      789791 :         return i;
     746             :   }
     747             :   return -1;
     748             : }
     749             : 
     750             : /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
     751             : /// indicating if this instruction reads or writes Reg. This also considers
     752             : /// partial defines.
     753             : std::pair<bool,bool>
     754    20944362 : MachineInstr::readsWritesVirtualRegister(unsigned Reg,
     755             :                                          SmallVectorImpl<unsigned> *Ops) const {
     756             :   bool PartDef = false; // Partial redefine.
     757             :   bool FullDef = false; // Full define.
     758             :   bool Use = false;
     759             : 
     760    74792474 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     761             :     const MachineOperand &MO = getOperand(i);
     762    53848112 :     if (!MO.isReg() || MO.getReg() != Reg)
     763    32554877 :       continue;
     764    21293235 :     if (Ops)
     765      952420 :       Ops->push_back(i);
     766    21293235 :     if (MO.isUse())
     767    18866466 :       Use |= !MO.isUndef();
     768     2670423 :     else if (MO.getSubReg() && !MO.isUndef())
     769             :       // A partial def undef doesn't count as reading the register.
     770             :       PartDef = true;
     771             :     else
     772             :       FullDef = true;
     773             :   }
     774             :   // A partial redefine uses Reg unless there is also a full define.
     775    41888724 :   return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
     776             : }
     777             : 
     778             : /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
     779             : /// the specified register or -1 if it is not found. If isDead is true, defs
     780             : /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
     781             : /// also checks if there is a def of a super-register.
     782             : int
     783     8592540 : MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
     784             :                                         const TargetRegisterInfo *TRI) const {
     785             :   bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
     786    77076332 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     787             :     const MachineOperand &MO = getOperand(i);
     788             :     // Accept regmask operands when Overlap is set.
     789             :     // Ignore them when looking for a specific def operand (Overlap == false).
     790    55247187 :     if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
     791        1470 :       return i;
     792    89164491 :     if (!MO.isReg() || !MO.isDef())
     793    27427515 :       continue;
     794             :     unsigned MOReg = MO.getReg();
     795     9345453 :     bool Found = (MOReg == Reg);
     796    18145625 :     if (!Found && TRI && isPhys &&
     797             :         TargetRegisterInfo::isPhysicalRegister(MOReg)) {
     798     2812070 :       if (Overlap)
     799     2373397 :         Found = TRI->regsOverlap(MOReg, Reg);
     800             :       else
     801      438673 :         Found = TRI->isSubRegister(MOReg, Reg);
     802             :     }
     803    10635842 :     if (Found && (!isDead || MO.isDead()))
     804     2531072 :       return i;
     805             :   }
     806             :   return -1;
     807             : }
     808             : 
     809             : /// findFirstPredOperandIdx() - Find the index of the first operand in the
     810             : /// operand list that is used to represent the predicate. It returns -1 if
     811             : /// none is found.
     812     1101586 : int MachineInstr::findFirstPredOperandIdx() const {
     813             :   // Don't call MCID.findFirstPredOperandIdx() because this variant
     814             :   // is sometimes called on an instruction that's not yet complete, and
     815             :   // so the number of operands is less than the MCID indicates. In
     816             :   // particular, the PTX target does this.
     817             :   const MCInstrDesc &MCID = getDesc();
     818     1101586 :   if (MCID.isPredicable()) {
     819     6184012 :     for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
     820     3557628 :       if (MCID.OpInfo[i].isPredicate())
     821      963652 :         return i;
     822             :   }
     823             : 
     824             :   return -1;
     825             : }
     826             : 
     827             : // MachineOperand::TiedTo is 4 bits wide.
     828             : const unsigned TiedMax = 15;
     829             : 
     830             : /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
     831             : ///
     832             : /// Use and def operands can be tied together, indicated by a non-zero TiedTo
     833             : /// field. TiedTo can have these values:
     834             : ///
     835             : /// 0:              Operand is not tied to anything.
     836             : /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
     837             : /// TiedMax:        Tied to an operand >= TiedMax-1.
     838             : ///
     839             : /// The tied def must be one of the first TiedMax operands on a normal
     840             : /// instruction. INLINEASM instructions allow more tied defs.
     841             : ///
     842      534433 : void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
     843             :   MachineOperand &DefMO = getOperand(DefIdx);
     844             :   MachineOperand &UseMO = getOperand(UseIdx);
     845             :   assert(DefMO.isDef() && "DefIdx must be a def operand");
     846             :   assert(UseMO.isUse() && "UseIdx must be a use operand");
     847             :   assert(!DefMO.isTied() && "Def is already tied to another use");
     848             :   assert(!UseMO.isTied() && "Use is already tied to another def");
     849             : 
     850      534433 :   if (DefIdx < TiedMax)
     851      534350 :     UseMO.TiedTo = DefIdx + 1;
     852             :   else {
     853             :     // Inline asm can use the group descriptors to find tied operands, but on
     854             :     // normal instruction, the tied def must be within the first TiedMax
     855             :     // operands.
     856             :     assert(isInlineAsm() && "DefIdx out of range");
     857          83 :     UseMO.TiedTo = TiedMax;
     858             :   }
     859             : 
     860             :   // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
     861     1068866 :   DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
     862      534433 : }
     863             : 
     864             : /// Given the index of a tied register operand, find the operand it is tied to.
     865             : /// Defs are tied to uses and vice versa. Returns the index of the tied operand
     866             : /// which must exist.
     867     3965652 : unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
     868             :   const MachineOperand &MO = getOperand(OpIdx);
     869             :   assert(MO.isTied() && "Operand isn't tied");
     870             : 
     871             :   // Normally TiedTo is in range.
     872     3965652 :   if (MO.TiedTo < TiedMax)
     873     3950215 :     return MO.TiedTo - 1;
     874             : 
     875             :   // Uses on normal instructions can be out of range.
     876       15437 :   if (!isInlineAsm()) {
     877             :     // Normal tied defs must be in the 0..TiedMax-1 range.
     878           0 :     if (MO.isUse())
     879             :       return TiedMax - 1;
     880             :     // MO is a def. Search for the tied use.
     881           0 :     for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
     882             :       const MachineOperand &UseMO = getOperand(i);
     883           0 :       if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
     884             :         return i;
     885             :     }
     886           0 :     llvm_unreachable("Can't find tied use");
     887             :   }
     888             : 
     889             :   // Now deal with inline asm by parsing the operand group descriptor flags.
     890             :   // Find the beginning of each operand group.
     891             :   SmallVector<unsigned, 8> GroupIdx;
     892             :   unsigned OpIdxGroup = ~0u;
     893             :   unsigned NumOps;
     894     1377898 :   for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
     895     1362461 :        i += NumOps) {
     896             :     const MachineOperand &FlagMO = getOperand(i);
     897             :     assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
     898     1377898 :     unsigned CurGroup = GroupIdx.size();
     899     1377898 :     GroupIdx.push_back(i);
     900     2755796 :     NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
     901             :     // OpIdx belongs to this operand group.
     902     1377898 :     if (OpIdx > i && OpIdx < i + NumOps)
     903             :       OpIdxGroup = CurGroup;
     904             :     unsigned TiedGroup;
     905     1377898 :     if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
     906             :       continue;
     907             :     // Operands in this group are tied to operands in TiedGroup which must be
     908             :     // earlier. Find the number of operands between the two groups.
     909      961982 :     unsigned Delta = i - GroupIdx[TiedGroup];
     910             : 
     911             :     // OpIdx is a use tied to TiedGroup.
     912      480991 :     if (OpIdxGroup == CurGroup)
     913        8245 :       return OpIdx - Delta;
     914             : 
     915             :     // OpIdx is a def tied to this use group.
     916      472746 :     if (OpIdxGroup == TiedGroup)
     917        7192 :       return OpIdx + Delta;
     918             :   }
     919           0 :   llvm_unreachable("Invalid tied operand on inline asm");
     920             : }
     921             : 
     922             : /// clearKillInfo - Clears kill flags on all operands.
     923             : ///
     924       18012 : void MachineInstr::clearKillInfo() {
     925      126004 :   for (MachineOperand &MO : operands()) {
     926       95280 :     if (MO.isReg() && MO.isUse())
     927             :       MO.setIsKill(false);
     928             :   }
     929       18012 : }
     930             : 
     931      149720 : void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
     932             :                                       unsigned SubIdx,
     933             :                                       const TargetRegisterInfo &RegInfo,
     934             :                                       bool ClearIsRenamable) {
     935      149720 :   if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
     936       85878 :     if (SubIdx)
     937           0 :       ToReg = RegInfo.getSubReg(ToReg, SubIdx);
     938      444274 :     for (MachineOperand &MO : operands()) {
     939      179198 :       if (!MO.isReg() || MO.getReg() != FromReg)
     940       93320 :         continue;
     941       85878 :       MO.substPhysReg(ToReg, RegInfo);
     942       85878 :       if (ClearIsRenamable)
     943          81 :         MO.setIsRenamable(false);
     944             :     }
     945             :   } else {
     946             :     assert(!ClearIsRenamable && "IsRenamable invalid for virtual registers");
     947      550668 :     for (MachineOperand &MO : operands()) {
     948      422984 :       if (!MO.isReg() || MO.getReg() != FromReg)
     949      179571 :         continue;
     950       63842 :       MO.substVirtReg(ToReg, SubIdx, RegInfo);
     951             :     }
     952             :   }
     953      149720 : }
     954             : 
     955             : /// isSafeToMove - Return true if it is safe to move this instruction. If
     956             : /// SawStore is set to true, it means that there is a store (or call) between
     957             : /// the instruction's location and its intended destination.
     958    15933153 : bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
     959             :   // Ignore stuff that we obviously can't move.
     960             :   //
     961             :   // Treat volatile loads as stores. This is not strictly necessary for
     962             :   // volatiles, but it is required for atomic loads. It is not allowed to move
     963             :   // a load across an atomic load with Ordering > Monotonic.
     964    42033044 :   if (mayStore() || isCall() || isPHI() ||
     965    13875629 :       (mayLoad() && hasOrderedMemoryRef())) {
     966     3379357 :     SawStore = true;
     967     3379357 :     return false;
     968             :   }
     969             : 
     970    35228394 :   if (isPosition() || isDebugValue() || isTerminator() ||
     971    10946613 :       hasUnmodeledSideEffects())
     972             :     return false;
     973             : 
     974             :   // See if this instruction does a load.  If so, we have to guarantee that the
     975             :   // loaded value doesn't change between the load and the its intended
     976             :   // destination. The check for isInvariantLoad gives the targe the chance to
     977             :   // classify the load as always returning a constant, e.g. a constant pool
     978             :   // load.
     979    10872252 :   if (mayLoad() && !isDereferenceableInvariantLoad(AA))
     980             :     // Otherwise, this is a real load.  If there is a store between the load and
     981             :     // end of block, we can't move it.
     982      875630 :     return !SawStore;
     983             : 
     984             :   return true;
     985             : }
     986             : 
     987     3180865 : bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
     988             :                             bool UseTBAA) {
     989             :   const MachineFunction *MF = getMF();
     990     3180865 :   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
     991             :   const MachineFrameInfo &MFI = MF->getFrameInfo();
     992             : 
     993             :   // If neither instruction stores to memory, they can't alias in any
     994             :   // meaningful way, even if they read from the same address.
     995     3180865 :   if (!mayStore() && !Other.mayStore())
     996             :     return false;
     997             : 
     998             :   // Let the target decide if memory accesses cannot possibly overlap.
     999     3180865 :   if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
    1000             :     return false;
    1001             : 
    1002             :   // FIXME: Need to handle multiple memory operands to support all targets.
    1003     3136500 :   if (!hasOneMemOperand() || !Other.hasOneMemOperand())
    1004             :     return true;
    1005             : 
    1006     2142834 :   MachineMemOperand *MMOa = *memoperands_begin();
    1007     2142834 :   MachineMemOperand *MMOb = *Other.memoperands_begin();
    1008             : 
    1009             :   // The following interface to AA is fashioned after DAGCombiner::isAlias
    1010             :   // and operates with MachineMemOperand offset with some important
    1011             :   // assumptions:
    1012             :   //   - LLVM fundamentally assumes flat address spaces.
    1013             :   //   - MachineOperand offset can *only* result from legalization and
    1014             :   //     cannot affect queries other than the trivial case of overlap
    1015             :   //     checking.
    1016             :   //   - These offsets never wrap and never step outside
    1017             :   //     of allocated objects.
    1018             :   //   - There should never be any negative offsets here.
    1019             :   //
    1020             :   // FIXME: Modify API to hide this math from "user"
    1021             :   // Even before we go to AA we can reason locally about some
    1022             :   // memory objects. It can save compile time, and possibly catch some
    1023             :   // corner cases not currently covered.
    1024             : 
    1025     2142834 :   int64_t OffsetA = MMOa->getOffset();
    1026     2142834 :   int64_t OffsetB = MMOb->getOffset();
    1027             : 
    1028     2142834 :   int64_t MinOffset = std::min(OffsetA, OffsetB);
    1029     2142834 :   int64_t WidthA = MMOa->getSize();
    1030     2142834 :   int64_t WidthB = MMOb->getSize();
    1031             :   const Value *ValA = MMOa->getValue();
    1032             :   const Value *ValB = MMOb->getValue();
    1033     2142834 :   bool SameVal = (ValA && ValB && (ValA == ValB));
    1034             :   if (!SameVal) {
    1035             :     const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
    1036             :     const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
    1037     1665341 :     if (PSVa && ValB && !PSVa->mayAlias(&MFI))
    1038             :       return false;
    1039     1652683 :     if (PSVb && ValA && !PSVb->mayAlias(&MFI))
    1040             :       return false;
    1041     1641189 :     if (PSVa && PSVb && (PSVa == PSVb))
    1042             :       SameVal = true;
    1043             :   }
    1044             : 
    1045     1097238 :   if (SameVal) {
    1046     1498937 :     int64_t MaxOffset = std::max(OffsetA, OffsetB);
    1047     1498937 :     int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
    1048     1498937 :     return (MinOffset + LowWidth > MaxOffset);
    1049             :   }
    1050             : 
    1051      619745 :   if (!AA)
    1052             :     return true;
    1053             : 
    1054       21308 :   if (!ValA || !ValB)
    1055             :     return true;
    1056             : 
    1057             :   assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
    1058             :   assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
    1059             : 
    1060        9361 :   int64_t Overlapa = WidthA + OffsetA - MinOffset;
    1061        9361 :   int64_t Overlapb = WidthB + OffsetB - MinOffset;
    1062             : 
    1063             :   AliasResult AAResult = AA->alias(
    1064       18722 :       MemoryLocation(ValA, Overlapa,
    1065        9361 :                      UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
    1066       18722 :       MemoryLocation(ValB, Overlapb,
    1067       18722 :                      UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
    1068             : 
    1069        9361 :   return (AAResult != NoAlias);
    1070             : }
    1071             : 
    1072             : /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
    1073             : /// or volatile memory reference, or if the information describing the memory
    1074             : /// reference is not available. Return false if it is known to have no ordered
    1075             : /// memory references.
    1076     6994956 : bool MachineInstr::hasOrderedMemoryRef() const {
    1077             :   // An instruction known never to access memory won't have a volatile access.
    1078    11745231 :   if (!mayStore() &&
    1079     7191483 :       !mayLoad() &&
    1080     9434876 :       !isCall() &&
    1081     2439921 :       !hasUnmodeledSideEffects())
    1082             :     return false;
    1083             : 
    1084             :   // Otherwise, if the instruction has no memory reference information,
    1085             :   // conservatively assume it wasn't preserved.
    1086     4560710 :   if (memoperands_empty())
    1087             :     return true;
    1088             : 
    1089             :   // Check if any of our memory operands are ordered.
    1090             :   return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
    1091             :     return !MMO->isUnordered();
    1092             :   });
    1093             : }
    1094             : 
    1095             : /// isDereferenceableInvariantLoad - Return true if this instruction will never
    1096             : /// trap and is loading from a location whose value is invariant across a run of
    1097             : /// this function.
    1098     2475534 : bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
    1099             :   // If the instruction doesn't load at all, it isn't an invariant load.
    1100     2475534 :   if (!mayLoad())
    1101             :     return false;
    1102             : 
    1103             :   // If the instruction has lost its memoperands, conservatively assume that
    1104             :   // it may not be an invariant load.
    1105     2155684 :   if (memoperands_empty())
    1106             :     return false;
    1107             : 
    1108             :   const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
    1109             : 
    1110     3296860 :   for (MachineMemOperand *MMO : memoperands()) {
    1111     2135684 :     if (MMO->isVolatile()) return false;
    1112     2100518 :     if (MMO->isStore()) return false;
    1113     2325020 :     if (MMO->isInvariant() && MMO->isDereferenceable())
    1114      251715 :       continue;
    1115             : 
    1116             :     // A load from a constant PseudoSourceValue is invariant.
    1117      413616 :     if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
    1118      413616 :       if (PSV->isConstant(&MFI))
    1119      321245 :         continue;
    1120             : 
    1121     1407148 :     if (const Value *V = MMO->getValue()) {
    1122             :       // If we have an AliasAnalysis, ask it whether the memory is constant.
    1123     2176061 :       if (AA &&
    1124      781566 :           AA->pointsToConstantMemory(
    1125     1379161 :               MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
    1126        7667 :         continue;
    1127             :     }
    1128             : 
    1129             :     // Otherwise assume conservatively.
    1130             :     return false;
    1131             :   }
    1132             : 
    1133             :   // Everything checks out.
    1134             :   return true;
    1135             : }
    1136             : 
    1137             : /// isConstantValuePHI - If the specified instruction is a PHI that always
    1138             : /// merges together the same virtual register, return the register, otherwise
    1139             : /// return 0.
    1140          23 : unsigned MachineInstr::isConstantValuePHI() const {
    1141             :   if (!isPHI())
    1142             :     return 0;
    1143             :   assert(getNumOperands() >= 3 &&
    1144             :          "It's illegal to have a PHI without source operands");
    1145             : 
    1146             :   unsigned Reg = getOperand(1).getReg();
    1147          23 :   for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
    1148          23 :     if (getOperand(i).getReg() != Reg)
    1149             :       return 0;
    1150             :   return Reg;
    1151             : }
    1152             : 
    1153    29522287 : bool MachineInstr::hasUnmodeledSideEffects() const {
    1154    29522287 :   if (hasProperty(MCID::UnmodeledSideEffects))
    1155             :     return true;
    1156    29288028 :   if (isInlineAsm()) {
    1157       28081 :     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    1158       28081 :     if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
    1159             :       return true;
    1160             :   }
    1161             : 
    1162             :   return false;
    1163             : }
    1164             : 
    1165     3932412 : bool MachineInstr::isLoadFoldBarrier() const {
    1166     7262902 :   return mayStore() || isCall() || hasUnmodeledSideEffects();
    1167             : }
    1168             : 
    1169             : /// allDefsAreDead - Return true if all the defs of this instruction are dead.
    1170             : ///
    1171      952549 : bool MachineInstr::allDefsAreDead() const {
    1172     1305779 :   for (const MachineOperand &MO : operands()) {
    1173     2048232 :     if (!MO.isReg() || MO.isUse())
    1174       95998 :       continue;
    1175      959392 :     if (!MO.isDead())
    1176             :       return false;
    1177             :   }
    1178             :   return true;
    1179             : }
    1180             : 
    1181             : /// copyImplicitOps - Copy implicit register operands from specified
    1182             : /// instruction to this instruction.
    1183       11917 : void MachineInstr::copyImplicitOps(MachineFunction &MF,
    1184             :                                    const MachineInstr &MI) {
    1185       16365 :   for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
    1186       28282 :        i != e; ++i) {
    1187             :     const MachineOperand &MO = MI.getOperand(i);
    1188       30704 :     if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
    1189       16365 :       addOperand(MF, MO);
    1190             :   }
    1191       11917 : }
    1192             : 
    1193       80831 : bool MachineInstr::hasComplexRegisterTies() const {
    1194             :   const MCInstrDesc &MCID = getDesc();
    1195      578781 :   for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
    1196             :     const auto &Operand = getOperand(I);
    1197      407853 :     if (!Operand.isReg() || Operand.isDef())
    1198             :       // Ignore the defined registers as MCID marks only the uses as tied.
    1199      161546 :       continue;
    1200             :     int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
    1201       87436 :     int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
    1202       87436 :     if (ExpectedTiedIdx != TiedIdx)
    1203             :       return true;
    1204             :   }
    1205             :   return false;
    1206             : }
    1207             : 
    1208      248965 : LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
    1209             :                                  const MachineRegisterInfo &MRI) const {
    1210             :   const MachineOperand &Op = getOperand(OpIdx);
    1211      248965 :   if (!Op.isReg())
    1212       90093 :     return LLT{};
    1213             : 
    1214      158872 :   if (isVariadic() || OpIdx >= getNumExplicitOperands())
    1215       63163 :     return MRI.getType(Op.getReg());
    1216             : 
    1217       95709 :   auto &OpInfo = getDesc().OpInfo[OpIdx];
    1218       95709 :   if (!OpInfo.isGenericType())
    1219       87600 :     return MRI.getType(Op.getReg());
    1220             : 
    1221        8109 :   if (PrintedTypes[OpInfo.getGenericTypeIndex()])
    1222        2126 :     return LLT{};
    1223             : 
    1224        5983 :   PrintedTypes.set(OpInfo.getGenericTypeIndex());
    1225        5983 :   return MRI.getType(Op.getReg());
    1226             : }
    1227             : 
    1228             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
    1229             : LLVM_DUMP_METHOD void MachineInstr::dump() const {
    1230             :   dbgs() << "  ";
    1231             :   print(dbgs());
    1232             : }
    1233             : #endif
    1234             : 
    1235          71 : void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
    1236             :                          bool SkipDebugLoc, const TargetInstrInfo *TII) const {
    1237             :   const Module *M = nullptr;
    1238             :   const Function *F = nullptr;
    1239             :   if (const MachineFunction *MF = getMFIfAvailable(*this)) {
    1240             :     F = &MF->getFunction();
    1241             :     M = F->getParent();
    1242             :   }
    1243             : 
    1244         142 :   ModuleSlotTracker MST(M);
    1245          71 :   if (F)
    1246          70 :     MST.incorporateFunction(*F);
    1247          71 :   print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, TII);
    1248          71 : }
    1249             : 
    1250       52609 : void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
    1251             :                          bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
    1252             :                          const TargetInstrInfo *TII) const {
    1253             :   // We can be a bit tidier if we know the MachineFunction.
    1254             :   const MachineFunction *MF = nullptr;
    1255       52609 :   const TargetRegisterInfo *TRI = nullptr;
    1256       52609 :   const MachineRegisterInfo *MRI = nullptr;
    1257       52609 :   const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
    1258       52609 :   tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
    1259             : 
    1260             :   if (isCFIInstruction())
    1261             :     assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
    1262             : 
    1263       52585 :   SmallBitVector PrintedTypes(8);
    1264       52609 :   bool ShouldPrintRegisterTies = hasComplexRegisterTies();
    1265      163031 :   auto getTiedOperandIdx = [&](unsigned OpIdx) {
    1266      163031 :     if (!ShouldPrintRegisterTies)
    1267             :       return 0U;
    1268           0 :     const MachineOperand &MO = getOperand(OpIdx);
    1269           0 :     if (MO.isReg() && MO.isTied() && !MO.isDef())
    1270           0 :       return findTiedOperandIdx(OpIdx);
    1271             :     return 0U;
    1272       52609 :   };
    1273             :   unsigned StartOp = 0;
    1274             :   unsigned e = getNumOperands();
    1275             : 
    1276             :   // Print explicitly defined operands on the left of an assignment syntax.
    1277      100069 :   while (StartOp < e) {
    1278             :     const MachineOperand &MO = getOperand(StartOp);
    1279      140765 :     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
    1280             :       break;
    1281             : 
    1282       23730 :     if (StartOp != 0)
    1283         520 :       OS << ", ";
    1284             : 
    1285       23730 :     LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
    1286       23730 :     unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
    1287       23730 :     MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
    1288             :              ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
    1289       23730 :     ++StartOp;
    1290             :   }
    1291             : 
    1292       52609 :   if (StartOp != 0)
    1293       23210 :     OS << " = ";
    1294             : 
    1295       52609 :   if (getFlag(MachineInstr::FrameSetup))
    1296        1053 :     OS << "frame-setup ";
    1297       51556 :   else if (getFlag(MachineInstr::FrameDestroy))
    1298         252 :     OS << "frame-destroy ";
    1299             : 
    1300             :   // Print the opcode name.
    1301       52609 :   if (TII)
    1302       52608 :     OS << TII->getName(getOpcode());
    1303             :   else
    1304           1 :     OS << "UNKNOWN";
    1305             : 
    1306       52609 :   if (SkipOpers)
    1307          24 :     return;
    1308             : 
    1309             :   // Print the rest of the operands.
    1310             :   bool FirstOp = true;
    1311             :   unsigned AsmDescOp = ~0u;
    1312             :   unsigned AsmOpCount = 0;
    1313             : 
    1314       52609 :   if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
    1315             :     // Print asm string.
    1316           0 :     OS << " ";
    1317             :     const unsigned OpIdx = InlineAsm::MIOp_AsmString;
    1318           0 :     LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
    1319           0 :     unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
    1320           0 :     getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
    1321             :                             ShouldPrintRegisterTies, TiedOperandIdx, TRI,
    1322             :                             IntrinsicInfo);
    1323             : 
    1324             :     // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
    1325           0 :     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    1326           0 :     if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
    1327           0 :       OS << " [sideeffect]";
    1328           0 :     if (ExtraInfo & InlineAsm::Extra_MayLoad)
    1329           0 :       OS << " [mayload]";
    1330           0 :     if (ExtraInfo & InlineAsm::Extra_MayStore)
    1331           0 :       OS << " [maystore]";
    1332           0 :     if (ExtraInfo & InlineAsm::Extra_IsConvergent)
    1333           0 :       OS << " [isconvergent]";
    1334           0 :     if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
    1335           0 :       OS << " [alignstack]";
    1336           0 :     if (getInlineAsmDialect() == InlineAsm::AD_ATT)
    1337           0 :       OS << " [attdialect]";
    1338           0 :     if (getInlineAsmDialect() == InlineAsm::AD_Intel)
    1339           0 :       OS << " [inteldialect]";
    1340             : 
    1341             :     StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
    1342             :     FirstOp = false;
    1343             :   }
    1344             : 
    1345      331251 :   for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
    1346             :     const MachineOperand &MO = getOperand(i);
    1347             : 
    1348      139321 :     if (FirstOp) FirstOp = false; else OS << ",";
    1349      139321 :     OS << " ";
    1350             : 
    1351      139401 :     if (isDebugValue() && MO.isMetadata()) {
    1352             :       // Pretty print DBG_VALUE instructions.
    1353             :       auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
    1354          20 :       if (DIV && !DIV->getName().empty())
    1355          40 :         OS << "!\"" << DIV->getName() << '\"';
    1356             :       else {
    1357          40 :         LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
    1358          20 :         unsigned TiedOperandIdx = getTiedOperandIdx(i);
    1359          20 :         MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
    1360             :                  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
    1361             :       }
    1362      139281 :     } else if (i == AsmDescOp && MO.isImm()) {
    1363             :       // Pretty print the inline asm operand descriptor.
    1364           0 :       OS << '$' << AsmOpCount++;
    1365           0 :       unsigned Flag = MO.getImm();
    1366           0 :       switch (InlineAsm::getKind(Flag)) {
    1367           0 :       case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
    1368           0 :       case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
    1369           0 :       case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
    1370           0 :       case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
    1371           0 :       case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
    1372           0 :       case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
    1373           0 :       default: OS << ":[??" << InlineAsm::getKind(Flag); break;
    1374             :       }
    1375             : 
    1376             :       unsigned RCID = 0;
    1377           0 :       if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
    1378             :           InlineAsm::hasRegClassConstraint(Flag, RCID)) {
    1379           0 :         if (TRI) {
    1380           0 :           OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
    1381             :         } else
    1382           0 :           OS << ":RC" << RCID;
    1383             :       }
    1384             : 
    1385           0 :       if (InlineAsm::isMemKind(Flag)) {
    1386             :         unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
    1387           0 :         switch (MCID) {
    1388           0 :         case InlineAsm::Constraint_es: OS << ":es"; break;
    1389           0 :         case InlineAsm::Constraint_i:  OS << ":i"; break;
    1390           0 :         case InlineAsm::Constraint_m:  OS << ":m"; break;
    1391           0 :         case InlineAsm::Constraint_o:  OS << ":o"; break;
    1392           0 :         case InlineAsm::Constraint_v:  OS << ":v"; break;
    1393           0 :         case InlineAsm::Constraint_Q:  OS << ":Q"; break;
    1394           0 :         case InlineAsm::Constraint_R:  OS << ":R"; break;
    1395           0 :         case InlineAsm::Constraint_S:  OS << ":S"; break;
    1396           0 :         case InlineAsm::Constraint_T:  OS << ":T"; break;
    1397           0 :         case InlineAsm::Constraint_Um: OS << ":Um"; break;
    1398           0 :         case InlineAsm::Constraint_Un: OS << ":Un"; break;
    1399           0 :         case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
    1400           0 :         case InlineAsm::Constraint_Us: OS << ":Us"; break;
    1401           0 :         case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
    1402           0 :         case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
    1403           0 :         case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
    1404           0 :         case InlineAsm::Constraint_X:  OS << ":X"; break;
    1405           0 :         case InlineAsm::Constraint_Z:  OS << ":Z"; break;
    1406           0 :         case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
    1407           0 :         case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
    1408           0 :         default: OS << ":?"; break;
    1409             :         }
    1410             :       }
    1411             : 
    1412             :       unsigned TiedTo = 0;
    1413             :       if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
    1414           0 :         OS << " tiedto:$" << TiedTo;
    1415             : 
    1416             :       OS << ']';
    1417             : 
    1418             :       // Compute the index of the next operand descriptor.
    1419           0 :       AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
    1420             :     } else {
    1421      278562 :       LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
    1422      139281 :       unsigned TiedOperandIdx = getTiedOperandIdx(i);
    1423      139281 :       if (MO.isImm() && isOperandSubregIdx(i))
    1424         610 :         MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
    1425             :       else
    1426      138671 :         MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
    1427             :                  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
    1428             :     }
    1429             :   }
    1430             : 
    1431       52609 :   if (!SkipDebugLoc) {
    1432       52585 :     if (const DebugLoc &DL = getDebugLoc()) {
    1433          31 :       if (!FirstOp)
    1434             :         OS << ',';
    1435          31 :       OS << " debug-location ";
    1436          31 :       DL->printAsOperand(OS, MST);
    1437             :     }
    1438             :   }
    1439             : 
    1440             :   bool HaveSemi = false;
    1441       52609 :   if (!memoperands_empty()) {
    1442             :     if (!HaveSemi) {
    1443        1872 :       OS << ";";
    1444             :       HaveSemi = true;
    1445             :     }
    1446             : 
    1447        1872 :     OS << " mem:";
    1448             :     for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
    1449        4248 :          i != e; ++i) {
    1450        2376 :       (*i)->print(OS, MST);
    1451        2376 :       if (std::next(i) != e)
    1452         504 :         OS << " ";
    1453             :     }
    1454             :   }
    1455             : 
    1456       52609 :   if (SkipDebugLoc)
    1457             :     return;
    1458             : 
    1459             :   // Print debug location information.
    1460       52605 :   if (isDebugValue() && getOperand(e - 2).isMetadata()) {
    1461          20 :     if (!HaveSemi)
    1462          20 :       OS << ";";
    1463             :     auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
    1464          20 :     OS << " line no:" <<  DV->getLine();
    1465          20 :     if (auto *InlinedAt = debugLoc->getInlinedAt()) {
    1466           0 :       DebugLoc InlinedAtDL(InlinedAt);
    1467             :       if (InlinedAtDL && MF) {
    1468             :         OS << " inlined @[ ";
    1469             :         InlinedAtDL.print(OS);
    1470             :         OS << " ]";
    1471             :       }
    1472             :     }
    1473             :     if (isIndirectDebugValue())
    1474           0 :       OS << " indirect";
    1475             :   }
    1476             : }
    1477             : 
    1478     9836192 : bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
    1479             :                                      const TargetRegisterInfo *RegInfo,
    1480             :                                      bool AddIfNotFound) {
    1481             :   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
    1482    16101795 :   bool hasAliases = isPhysReg &&
    1483    16101795 :     MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
    1484             :   bool Found = false;
    1485             :   SmallVector<unsigned,4> DeadOps;
    1486    51273946 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    1487             :     MachineOperand &MO = getOperand(i);
    1488   107521539 :     if (!MO.isReg() || !MO.isUse() || MO.isUndef())
    1489    18897876 :       continue;
    1490             : 
    1491             :     // DEBUG_VALUE nodes do not contribute to code generation and should
    1492             :     // always be ignored. Failure to do so may result in trying to modify
    1493             :     // KILL flags on DEBUG_VALUE nodes.
    1494    27338354 :     if (MO.isDebug())
    1495           0 :       continue;
    1496             : 
    1497             :     unsigned Reg = MO.getReg();
    1498    27338354 :     if (!Reg)
    1499     1315881 :       continue;
    1500             : 
    1501    26022473 :     if (Reg == IncomingReg) {
    1502     6182851 :       if (!Found) {
    1503     6119104 :         if (MO.isKill())
    1504             :           // The register is already marked kill.
    1505     4798476 :           return true;
    1506     4507647 :         if (isPhysReg && isRegTiedToDefOperand(i))
    1507             :           // Two-address uses of physregs must not be marked kill.
    1508             :           return true;
    1509             :         MO.setIsKill();
    1510             :         Found = true;
    1511             :       }
    1512    44612483 :     } else if (hasAliases && MO.isKill() &&
    1513             :                TargetRegisterInfo::isPhysicalRegister(Reg)) {
    1514             :       // A super-register kill already exists.
    1515     7645969 :       if (RegInfo->isSuperRegister(IncomingReg, Reg))
    1516             :         return true;
    1517     4458951 :       if (RegInfo->isSubRegister(IncomingReg, Reg))
    1518      474162 :         DeadOps.push_back(i);
    1519             :     }
    1520             :   }
    1521             : 
    1522             :   // Trim unneeded kill operands.
    1523     5511878 :   while (!DeadOps.empty()) {
    1524      474162 :     unsigned OpIdx = DeadOps.back();
    1525      474162 :     if (getOperand(OpIdx).isImplicit())
    1526      430951 :       RemoveOperand(OpIdx);
    1527             :     else
    1528             :       getOperand(OpIdx).setIsKill(false);
    1529             :     DeadOps.pop_back();
    1530             :   }
    1531             : 
    1532             :   // If not found, this means an alias of one of the operands is killed. Add a
    1533             :   // new implicit operand if required.
    1534     5037716 :   if (!Found && AddIfNotFound) {
    1535      498393 :     addOperand(MachineOperand::CreateReg(IncomingReg,
    1536             :                                          false /*IsDef*/,
    1537             :                                          true  /*IsImp*/,
    1538             :                                          true  /*IsKill*/));
    1539      498393 :     return true;
    1540             :   }
    1541             :   return Found;
    1542             : }
    1543             : 
    1544      150036 : void MachineInstr::clearRegisterKills(unsigned Reg,
    1545             :                                       const TargetRegisterInfo *RegInfo) {
    1546      150036 :   if (!TargetRegisterInfo::isPhysicalRegister(Reg))
    1547             :     RegInfo = nullptr;
    1548     1640598 :   for (MachineOperand &MO : operands()) {
    1549     1484590 :     if (!MO.isReg() || !MO.isUse() || !MO.isKill())
    1550      714371 :       continue;
    1551             :     unsigned OpReg = MO.getReg();
    1552       30910 :     if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
    1553             :       MO.setIsKill(false);
    1554             :   }
    1555      150036 : }
    1556             : 
    1557     1098084 : bool MachineInstr::addRegisterDead(unsigned Reg,
    1558             :                                    const TargetRegisterInfo *RegInfo,
    1559             :                                    bool AddIfNotFound) {
    1560             :   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
    1561     2093512 :   bool hasAliases = isPhysReg &&
    1562     2093512 :     MCRegAliasIterator(Reg, RegInfo, false).isValid();
    1563             :   bool Found = false;
    1564             :   SmallVector<unsigned,4> DeadOps;
    1565    13101952 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    1566             :     MachineOperand &MO = getOperand(i);
    1567    19517021 :     if (!MO.isReg() || !MO.isDef())
    1568     6808048 :       continue;
    1569             :     unsigned MOReg = MO.getReg();
    1570     5307549 :     if (!MOReg)
    1571           0 :       continue;
    1572             : 
    1573     5307549 :     if (MOReg == Reg) {
    1574             :       MO.setIsDead();
    1575             :       Found = true;
    1576     8829039 :     } else if (hasAliases && MO.isDead() &&
    1577             :                TargetRegisterInfo::isPhysicalRegister(MOReg)) {
    1578             :       // There exists a super-register that's marked dead.
    1579     1518936 :       if (RegInfo->isSuperRegister(Reg, MOReg))
    1580      111729 :         return true;
    1581     1407207 :       if (RegInfo->isSubRegister(Reg, MOReg))
    1582       24181 :         DeadOps.push_back(i);
    1583             :     }
    1584             :   }
    1585             : 
    1586             :   // Trim unneeded dead operands.
    1587     1010536 :   while (!DeadOps.empty()) {
    1588       24181 :     unsigned OpIdx = DeadOps.back();
    1589       24181 :     if (getOperand(OpIdx).isImplicit())
    1590       24111 :       RemoveOperand(OpIdx);
    1591             :     else
    1592             :       getOperand(OpIdx).setIsDead(false);
    1593             :     DeadOps.pop_back();
    1594             :   }
    1595             : 
    1596             :   // If not found, this means an alias of one of the operands is dead. Add a
    1597             :   // new implicit operand if required.
    1598      986355 :   if (Found || !AddIfNotFound)
    1599             :     return Found;
    1600             : 
    1601       24148 :   addOperand(MachineOperand::CreateReg(Reg,
    1602             :                                        true  /*IsDef*/,
    1603             :                                        true  /*IsImp*/,
    1604             :                                        false /*IsKill*/,
    1605             :                                        true  /*IsDead*/));
    1606       24148 :   return true;
    1607             : }
    1608             : 
    1609       50029 : void MachineInstr::clearRegisterDeads(unsigned Reg) {
    1610      564511 :   for (MachineOperand &MO : operands()) {
    1611      417644 :     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
    1612      207312 :       continue;
    1613             :     MO.setIsDead(false);
    1614             :   }
    1615       50029 : }
    1616             : 
    1617      438126 : void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
    1618     4081980 :   for (MachineOperand &MO : operands()) {
    1619     3520530 :     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
    1620     1743878 :       continue;
    1621             :     MO.setIsUndef(IsUndef);
    1622             :   }
    1623      438126 : }
    1624             : 
    1625      566528 : void MachineInstr::addRegisterDefined(unsigned Reg,
    1626             :                                       const TargetRegisterInfo *RegInfo) {
    1627      566528 :   if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
    1628             :     MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
    1629          59 :     if (MO)
    1630             :       return;
    1631             :   } else {
    1632           0 :     for (const MachineOperand &MO : operands()) {
    1633           0 :       if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
    1634             :           MO.getSubReg() == 0)
    1635             :         return;
    1636             :     }
    1637             :   }
    1638      566469 :   addOperand(MachineOperand::CreateReg(Reg,
    1639             :                                        true  /*IsDef*/,
    1640             :                                        true  /*IsImp*/));
    1641             : }
    1642             : 
    1643     1098895 : void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
    1644             :                                          const TargetRegisterInfo &TRI) {
    1645             :   bool HasRegMask = false;
    1646    14900221 :   for (MachineOperand &MO : operands()) {
    1647     6900663 :     if (MO.isRegMask()) {
    1648             :       HasRegMask = true;
    1649     5513500 :       continue;
    1650             :     }
    1651    11267172 :     if (!MO.isReg() || !MO.isDef()) continue;
    1652     1817454 :     unsigned Reg = MO.getReg();
    1653     1817454 :     if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
    1654             :     // If there are no uses, including partial uses, the def is dead.
    1655     1656653 :     if (llvm::none_of(UsedRegs,
    1656      302654 :                       [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
    1657             :       MO.setIsDead();
    1658             :   }
    1659             : 
    1660             :   // This is a call with a register mask operand.
    1661             :   // Mask clobbers are always dead, so add defs for the non-dead defines.
    1662     1098895 :   if (HasRegMask)
    1663      491119 :     for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
    1664      760609 :          I != E; ++I)
    1665      491119 :       addRegisterDefined(*I, &TRI);
    1666     1098895 : }
    1667             : 
    1668             : unsigned
    1669     5808097 : MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
    1670             :   // Build up a buffer of hash code components.
    1671             :   SmallVector<size_t, 8> HashComponents;
    1672     5808097 :   HashComponents.reserve(MI->getNumOperands() + 1);
    1673    11616194 :   HashComponents.push_back(MI->getOpcode());
    1674    71700064 :   for (const MachineOperand &MO : MI->operands()) {
    1675    58362960 :     if (MO.isReg() && MO.isDef() &&
    1676             :         TargetRegisterInfo::isVirtualRegister(MO.getReg()))
    1677     4602004 :       continue;  // Skip virtual register defs.
    1678             : 
    1679    50879862 :     HashComponents.push_back(hash_value(MO));
    1680             :   }
    1681    11616194 :   return hash_combine_range(HashComponents.begin(), HashComponents.end());
    1682             : }
    1683             : 
    1684         110 : void MachineInstr::emitError(StringRef Msg) const {
    1685             :   // Find the source location cookie.
    1686             :   unsigned LocCookie = 0;
    1687             :   const MDNode *LocMD = nullptr;
    1688        2576 :   for (unsigned i = getNumOperands(); i != 0; --i) {
    1689        2490 :     if (getOperand(i-1).isMetadata() &&
    1690        2490 :         (LocMD = getOperand(i-1).getMetadata()) &&
    1691             :         LocMD->getNumOperands() != 0) {
    1692             :       if (const ConstantInt *CI =
    1693             :               mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
    1694          12 :         LocCookie = CI->getZExtValue();
    1695          12 :         break;
    1696             :       }
    1697             :     }
    1698             :   }
    1699             : 
    1700         110 :   if (const MachineBasicBlock *MBB = getParent())
    1701         110 :     if (const MachineFunction *MF = MBB->getParent())
    1702         110 :       return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
    1703           0 :   report_fatal_error(Msg);
    1704             : }
    1705             : 
    1706       40227 : MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
    1707             :                                   const MCInstrDesc &MCID, bool IsIndirect,
    1708             :                                   unsigned Reg, const MDNode *Variable,
    1709             :                                   const MDNode *Expr) {
    1710             :   assert(isa<DILocalVariable>(Variable) && "not a variable");
    1711             :   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
    1712             :   assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
    1713             :          "Expected inlined-at fields to agree");
    1714       40227 :   if (IsIndirect)
    1715       20328 :     return BuildMI(MF, DL, MCID)
    1716       10164 :         .addReg(Reg, RegState::Debug)
    1717             :         .addImm(0U)
    1718             :         .addMetadata(Variable)
    1719       10164 :         .addMetadata(Expr);
    1720             :   else
    1721       60126 :     return BuildMI(MF, DL, MCID)
    1722       30063 :         .addReg(Reg, RegState::Debug)
    1723       30063 :         .addReg(0U, RegState::Debug)
    1724             :         .addMetadata(Variable)
    1725       30063 :         .addMetadata(Expr);
    1726             : }
    1727             : 
    1728       37264 : MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
    1729             :                                   MachineBasicBlock::iterator I,
    1730             :                                   const DebugLoc &DL, const MCInstrDesc &MCID,
    1731             :                                   bool IsIndirect, unsigned Reg,
    1732             :                                   const MDNode *Variable, const MDNode *Expr) {
    1733             :   assert(isa<DILocalVariable>(Variable) && "not a variable");
    1734             :   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
    1735             :   MachineFunction &MF = *BB.getParent();
    1736       37264 :   MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
    1737             :   BB.insert(I, MI);
    1738       37264 :   return MachineInstrBuilder(MF, MI);
    1739             : }
    1740             : 
    1741             : /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
    1742             : /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
    1743         142 : static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
    1744             :   assert(MI.getOperand(0).isReg() && "can't spill non-register");
    1745             :   assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
    1746             :          "Expected inlined-at fields to agree");
    1747             : 
    1748         142 :   const DIExpression *Expr = MI.getDebugExpression();
    1749             :   if (MI.isIndirectDebugValue()) {
    1750             :     assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
    1751         119 :     Expr = DIExpression::prepend(Expr, DIExpression::WithDeref);
    1752             :   }
    1753         142 :   return Expr;
    1754             : }
    1755             : 
    1756         125 : MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
    1757             :                                           MachineBasicBlock::iterator I,
    1758             :                                           const MachineInstr &Orig,
    1759             :                                           int FrameIndex) {
    1760         125 :   const DIExpression *Expr = computeExprForSpill(Orig);
    1761         125 :   return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
    1762             :       .addFrameIndex(FrameIndex)
    1763             :       .addImm(0U)
    1764         125 :       .addMetadata(Orig.getDebugVariable())
    1765         125 :       .addMetadata(Expr);
    1766             : }
    1767             : 
    1768          17 : void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
    1769          17 :   const DIExpression *Expr = computeExprForSpill(Orig);
    1770          17 :   Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
    1771          17 :   Orig.getOperand(1).ChangeToImmediate(0U);
    1772             :   Orig.getOperand(3).setMetadata(Expr);
    1773          17 : }

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