Line data Source code
1 : //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // Methods common to all machine instructions.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #include "llvm/CodeGen/MachineInstr.h"
15 : #include "llvm/ADT/APFloat.h"
16 : #include "llvm/ADT/ArrayRef.h"
17 : #include "llvm/ADT/FoldingSet.h"
18 : #include "llvm/ADT/Hashing.h"
19 : #include "llvm/ADT/None.h"
20 : #include "llvm/ADT/STLExtras.h"
21 : #include "llvm/ADT/SmallBitVector.h"
22 : #include "llvm/ADT/SmallString.h"
23 : #include "llvm/ADT/SmallVector.h"
24 : #include "llvm/Analysis/AliasAnalysis.h"
25 : #include "llvm/Analysis/Loads.h"
26 : #include "llvm/Analysis/MemoryLocation.h"
27 : #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
28 : #include "llvm/CodeGen/MachineBasicBlock.h"
29 : #include "llvm/CodeGen/MachineFunction.h"
30 : #include "llvm/CodeGen/MachineInstrBuilder.h"
31 : #include "llvm/CodeGen/MachineInstrBundle.h"
32 : #include "llvm/CodeGen/MachineMemOperand.h"
33 : #include "llvm/CodeGen/MachineModuleInfo.h"
34 : #include "llvm/CodeGen/MachineOperand.h"
35 : #include "llvm/CodeGen/MachineRegisterInfo.h"
36 : #include "llvm/CodeGen/PseudoSourceValue.h"
37 : #include "llvm/CodeGen/TargetInstrInfo.h"
38 : #include "llvm/CodeGen/TargetRegisterInfo.h"
39 : #include "llvm/CodeGen/TargetSubtargetInfo.h"
40 : #include "llvm/Config/llvm-config.h"
41 : #include "llvm/IR/Constants.h"
42 : #include "llvm/IR/DebugInfoMetadata.h"
43 : #include "llvm/IR/DebugLoc.h"
44 : #include "llvm/IR/DerivedTypes.h"
45 : #include "llvm/IR/Function.h"
46 : #include "llvm/IR/InlineAsm.h"
47 : #include "llvm/IR/InstrTypes.h"
48 : #include "llvm/IR/Intrinsics.h"
49 : #include "llvm/IR/LLVMContext.h"
50 : #include "llvm/IR/Metadata.h"
51 : #include "llvm/IR/Module.h"
52 : #include "llvm/IR/ModuleSlotTracker.h"
53 : #include "llvm/IR/Type.h"
54 : #include "llvm/IR/Value.h"
55 : #include "llvm/IR/Operator.h"
56 : #include "llvm/MC/MCInstrDesc.h"
57 : #include "llvm/MC/MCRegisterInfo.h"
58 : #include "llvm/MC/MCSymbol.h"
59 : #include "llvm/Support/Casting.h"
60 : #include "llvm/Support/CommandLine.h"
61 : #include "llvm/Support/Compiler.h"
62 : #include "llvm/Support/Debug.h"
63 : #include "llvm/Support/ErrorHandling.h"
64 : #include "llvm/Support/LowLevelTypeImpl.h"
65 : #include "llvm/Support/MathExtras.h"
66 : #include "llvm/Support/raw_ostream.h"
67 : #include "llvm/Target/TargetIntrinsicInfo.h"
68 : #include "llvm/Target/TargetMachine.h"
69 : #include <algorithm>
70 : #include <cassert>
71 : #include <cstddef>
72 : #include <cstdint>
73 : #include <cstring>
74 : #include <iterator>
75 : #include <utility>
76 :
77 : using namespace llvm;
78 :
79 : static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
80 64310 : if (const MachineBasicBlock *MBB = MI.getParent())
81 64308 : if (const MachineFunction *MF = MBB->getParent())
82 : return MF;
83 : return nullptr;
84 : }
85 :
86 : // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
87 : // it.
88 61546 : static void tryToGetTargetInfo(const MachineInstr &MI,
89 : const TargetRegisterInfo *&TRI,
90 : const MachineRegisterInfo *&MRI,
91 : const TargetIntrinsicInfo *&IntrinsicInfo,
92 : const TargetInstrInfo *&TII) {
93 :
94 : if (const MachineFunction *MF = getMFIfAvailable(MI)) {
95 61545 : TRI = MF->getSubtarget().getRegisterInfo();
96 61545 : MRI = &MF->getRegInfo();
97 61545 : IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
98 61545 : TII = MF->getSubtarget().getInstrInfo();
99 : }
100 61546 : }
101 :
102 52011199 : void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
103 52011199 : if (MCID->ImplicitDefs)
104 24428989 : for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
105 : ++ImpDefs)
106 33265654 : addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
107 52011199 : if (MCID->ImplicitUses)
108 23382209 : for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
109 : ++ImpUses)
110 29928366 : addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
111 52011199 : }
112 :
113 : /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
114 : /// implicit operands. It reserves space for the number of operands specified by
115 : /// the MCInstrDesc.
116 52472967 : MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
117 52472967 : DebugLoc dl, bool NoImp)
118 104945934 : : MCID(&tid), debugLoc(std::move(dl)) {
119 : assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
120 :
121 : // Reserve space for the expected number of operands.
122 52472967 : if (unsigned NumOps = MCID->getNumOperands() +
123 69057239 : MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
124 98279515 : CapOperands = OperandCapacity::get(NumOps);
125 51619916 : Operands = MF.allocateOperandArray(CapOperands);
126 : }
127 :
128 52472967 : if (!NoImp)
129 51903032 : addImplicitDefUseOperands(MF);
130 52472967 : }
131 :
132 : /// MachineInstr ctor - Copies MachineInstr arg exactly
133 : ///
134 109227 : MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
135 218454 : : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) {
136 : assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
137 :
138 218134 : CapOperands = OperandCapacity::get(MI.getNumOperands());
139 109227 : Operands = MF.allocateOperandArray(CapOperands);
140 :
141 : // Copy operands.
142 420579 : for (const MachineOperand &MO : MI.operands())
143 311352 : addOperand(MF, MO);
144 :
145 : // Copy all the sensible flags.
146 109227 : setFlags(MI.Flags);
147 109227 : }
148 :
149 : /// getRegInfo - If this instruction is embedded into a MachineFunction,
150 : /// return the MachineRegisterInfo object for the current function, otherwise
151 : /// return null.
152 230989395 : MachineRegisterInfo *MachineInstr::getRegInfo() {
153 230989395 : if (MachineBasicBlock *MBB = getParent())
154 143083783 : return &MBB->getParent()->getRegInfo();
155 : return nullptr;
156 : }
157 :
158 : /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
159 : /// this instruction from their respective use lists. This requires that the
160 : /// operands already be on their use lists.
161 19629835 : void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
162 89074038 : for (MachineOperand &MO : operands())
163 69444203 : if (MO.isReg())
164 52311620 : MRI.removeRegOperandFromUseList(&MO);
165 19629835 : }
166 :
167 : /// AddRegOperandsToUseLists - Add all of the register operands in
168 : /// this instruction from their respective use lists. This requires that the
169 : /// operands not be on their use lists yet.
170 54115192 : void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
171 148333873 : for (MachineOperand &MO : operands())
172 94218681 : if (MO.isReg())
173 62153076 : MRI.addRegOperandToUseList(&MO);
174 54115192 : }
175 :
176 4356648 : void MachineInstr::addOperand(const MachineOperand &Op) {
177 4356648 : MachineBasicBlock *MBB = getParent();
178 : assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
179 4356648 : MachineFunction *MF = MBB->getParent();
180 : assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
181 4356648 : addOperand(*MF, Op);
182 4356648 : }
183 :
184 : /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
185 : /// ranges. If MRI is non-null also update use-def chains.
186 33659982 : static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
187 : unsigned NumOps, MachineRegisterInfo *MRI) {
188 33659982 : if (MRI)
189 20018878 : return MRI->moveOperands(Dst, Src, NumOps);
190 :
191 : // MachineOperand is a trivially copyable type so we can just use memmove.
192 13641104 : std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
193 : }
194 :
195 : /// addOperand - Add the specified operand to the instruction. If it is an
196 : /// implicit operand, it is added to the end of the operand list. If it is
197 : /// an explicit operand it is added at the end of the explicit operand list
198 : /// (before the first implicit operand).
199 230204231 : void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
200 : assert(MCID && "Cannot add operands before providing an instr descriptor");
201 :
202 : // Check if we're adding one of our existing operands.
203 230204231 : if (&Op >= Operands && &Op < Operands + NumOperands) {
204 : // This is unusual: MI->addOperand(MI->getOperand(i)).
205 : // If adding Op requires reallocating or moving existing operands around,
206 : // the Op reference could go stale. Support it by copying Op.
207 617 : MachineOperand CopyOp(Op);
208 617 : return addOperand(MF, CopyOp);
209 : }
210 :
211 : // Find the insert location for the new operand. Implicit registers go at
212 : // the end, everything else goes before the implicit regs.
213 : //
214 : // FIXME: Allow mixed explicit and implicit operands on inline asm.
215 : // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
216 : // implicit-defs, but they must not be moved around. See the FIXME in
217 : // InstrEmitter.cpp.
218 230203614 : unsigned OpNo = getNumOperands();
219 230203614 : bool isImpReg = Op.isReg() && Op.isImplicit();
220 188858111 : if (!isImpReg && !isInlineAsm()) {
221 266910726 : while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
222 : --OpNo;
223 : assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
224 : }
225 : }
226 :
227 : #ifndef NDEBUG
228 : bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
229 : // OpNo now points as the desired insertion point. Unless this is a variadic
230 : // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
231 : // RegMask operands go between the explicit and implicit operands.
232 : assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
233 : OpNo < MCID->getNumOperands() || isMetaDataOp) &&
234 : "Trying to add an operand to a machine instr that is already done!");
235 : #endif
236 :
237 230203614 : MachineRegisterInfo *MRI = getRegInfo();
238 :
239 : // Determine if the Operands array needs to be reallocated.
240 : // Save the old capacity and operand array.
241 230203613 : OperandCapacity OldCap = CapOperands;
242 230203613 : MachineOperand *OldOperands = Operands;
243 230203613 : if (!OldOperands || OldCap.getSize() == getNumOperands()) {
244 7292287 : CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
245 7292287 : Operands = MF.allocateOperandArray(CapOperands);
246 : // Move the operands before the insertion point.
247 7292287 : if (OpNo)
248 6631566 : moveOperands(Operands, OldOperands, OpNo, MRI);
249 : }
250 :
251 : // Move the operands following the insertion point.
252 230203613 : if (OpNo != NumOperands)
253 26904042 : moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
254 : MRI);
255 230203614 : ++NumOperands;
256 :
257 : // Deallocate the old operand array.
258 230203614 : if (OldOperands != Operands && OldOperands)
259 : MF.deallocateOperandArray(OldCap, OldOperands);
260 :
261 : // Copy Op into place. It still needs to be inserted into the MRI use lists.
262 230203614 : MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
263 230203614 : NewMO->ParentMI = this;
264 :
265 : // When adding a register operand, tell MRI about it.
266 230203614 : if (NewMO->isReg()) {
267 : // Ensure isOnRegUseList() returns false, regardless of Op's status.
268 143598650 : NewMO->Contents.Reg.Prev = nullptr;
269 : // Ignore existing ties. This is not a property that can be copied.
270 143598650 : NewMO->TiedTo = 0;
271 : // Add the new operand to MRI, but only for instructions in an MBB.
272 143598650 : if (MRI)
273 84608957 : MRI->addRegOperandToUseList(NewMO);
274 : // The MCID operand information isn't accurate until we start adding
275 : // explicit operands. The implicit operands are added first, then the
276 : // explicits are inserted before them.
277 143598650 : if (!isImpReg) {
278 : // Tie uses to defs as indicated in MCInstrDesc.
279 102253145 : if (NewMO->isUse()) {
280 73207836 : int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
281 : if (DefIdx != -1)
282 2205584 : tieOperands(DefIdx, OpNo);
283 : }
284 : // If the register operand is flagged as early, mark the operand as such.
285 102253145 : if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
286 : NewMO->setIsEarlyClobber(true);
287 : }
288 : }
289 : }
290 :
291 : /// RemoveOperand - Erase an operand from an instruction, leaving it with one
292 : /// fewer operand than it started with.
293 : ///
294 785782 : void MachineInstr::RemoveOperand(unsigned OpNo) {
295 : assert(OpNo < getNumOperands() && "Invalid operand number");
296 785782 : untieRegOperand(OpNo);
297 :
298 : #ifndef NDEBUG
299 : // Moving tied operands would break the ties.
300 : for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
301 : if (Operands[i].isReg())
302 : assert(!Operands[i].isTied() && "Cannot move tied operands");
303 : #endif
304 :
305 785782 : MachineRegisterInfo *MRI = getRegInfo();
306 785782 : if (MRI && Operands[OpNo].isReg())
307 732587 : MRI->removeRegOperandFromUseList(Operands + OpNo);
308 :
309 : // Don't call the MachineOperand destructor. A lot of this code depends on
310 : // MachineOperand having a trivial destructor anyway, and adding a call here
311 : // wouldn't make it 'destructor-correct'.
312 :
313 785782 : if (unsigned N = NumOperands - 1 - OpNo)
314 124374 : moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
315 785782 : --NumOperands;
316 785782 : }
317 :
318 6487004 : void MachineInstr::dropMemRefs(MachineFunction &MF) {
319 6487004 : if (memoperands_empty())
320 : return;
321 :
322 : // See if we can just drop all of our extra info.
323 574 : if (!getPreInstrSymbol() && !getPostInstrSymbol()) {
324 : Info.clear();
325 574 : return;
326 : }
327 0 : if (!getPostInstrSymbol()) {
328 : Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
329 0 : return;
330 : }
331 0 : if (!getPreInstrSymbol()) {
332 : Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
333 0 : return;
334 : }
335 :
336 : // Otherwise allocate a fresh extra info with just these symbols.
337 0 : Info.set<EIIK_OutOfLine>(
338 0 : MF.createMIExtraInfo({}, getPreInstrSymbol(), getPostInstrSymbol()));
339 : }
340 :
341 24874379 : void MachineInstr::setMemRefs(MachineFunction &MF,
342 : ArrayRef<MachineMemOperand *> MMOs) {
343 24874379 : if (MMOs.empty()) {
344 6484825 : dropMemRefs(MF);
345 6484825 : return;
346 : }
347 :
348 : // Try to store a single MMO inline.
349 18389554 : if (MMOs.size() == 1 && !getPreInstrSymbol() && !getPostInstrSymbol()) {
350 18020992 : Info.set<EIIK_MMO>(MMOs[0]);
351 18020992 : return;
352 : }
353 :
354 : // Otherwise create an extra info struct with all of our info.
355 368562 : Info.set<EIIK_OutOfLine>(
356 : MF.createMIExtraInfo(MMOs, getPreInstrSymbol(), getPostInstrSymbol()));
357 : }
358 :
359 13359675 : void MachineInstr::addMemOperand(MachineFunction &MF,
360 : MachineMemOperand *MO) {
361 : SmallVector<MachineMemOperand *, 2> MMOs;
362 13359675 : MMOs.append(memoperands_begin(), memoperands_end());
363 13359675 : MMOs.push_back(MO);
364 13359675 : setMemRefs(MF, MMOs);
365 13359675 : }
366 :
367 11880 : void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
368 11880 : if (this == &MI)
369 : // Nothing to do for a self-clone!
370 : return;
371 :
372 : assert(&MF == MI.getMF() &&
373 : "Invalid machine functions when cloning memory refrences!");
374 : // See if we can just steal the extra info already allocated for the
375 : // instruction. We can do this whenever the pre- and post-instruction symbols
376 : // are the same (including null).
377 11880 : if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
378 11880 : getPostInstrSymbol() == MI.getPostInstrSymbol()) {
379 11880 : Info = MI.Info;
380 11880 : return;
381 : }
382 :
383 : // Otherwise, fall back on a copy-based clone.
384 0 : setMemRefs(MF, MI.memoperands());
385 : }
386 :
387 : /// Check to see if the MMOs pointed to by the two MemRefs arrays are
388 : /// identical.
389 42427 : static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
390 : ArrayRef<MachineMemOperand *> RHS) {
391 42427 : if (LHS.size() != RHS.size())
392 : return false;
393 :
394 : auto LHSPointees = make_pointee_range(LHS);
395 : auto RHSPointees = make_pointee_range(RHS);
396 : return std::equal(LHSPointees.begin(), LHSPointees.end(),
397 : RHSPointees.begin());
398 : }
399 :
400 44411 : void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
401 : ArrayRef<const MachineInstr *> MIs) {
402 : // Try handling easy numbers of MIs with simpler mechanisms.
403 44411 : if (MIs.empty()) {
404 0 : dropMemRefs(MF);
405 1984 : return;
406 : }
407 44411 : if (MIs.size() == 1) {
408 0 : cloneMemRefs(MF, *MIs[0]);
409 0 : return;
410 : }
411 : // Because an empty memoperands list provides *no* information and must be
412 : // handled conservatively (assuming the instruction can do anything), the only
413 : // way to merge with it is to drop all other memoperands.
414 44411 : if (MIs[0]->memoperands_empty()) {
415 1984 : dropMemRefs(MF);
416 1984 : return;
417 : }
418 :
419 : // Handle the general case.
420 : SmallVector<MachineMemOperand *, 2> MergedMMOs;
421 : // Start with the first instruction.
422 : assert(&MF == MIs[0]->getMF() &&
423 : "Invalid machine functions when cloning memory references!");
424 42427 : MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
425 : // Now walk all the other instructions and accumulate any different MMOs.
426 84854 : for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
427 : assert(&MF == MI.getMF() &&
428 : "Invalid machine functions when cloning memory references!");
429 :
430 : // Skip MIs with identical operands to the first. This is a somewhat
431 : // arbitrary hack but will catch common cases without being quadratic.
432 : // TODO: We could fully implement merge semantics here if needed.
433 42427 : if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
434 : continue;
435 :
436 : // Because an empty memoperands list provides *no* information and must be
437 : // handled conservatively (assuming the instruction can do anything), the
438 : // only way to merge with it is to drop all other memoperands.
439 5943 : if (MI.memoperands_empty()) {
440 0 : dropMemRefs(MF);
441 : return;
442 : }
443 :
444 : // Otherwise accumulate these into our temporary buffer of the merged state.
445 5943 : MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
446 : }
447 :
448 42427 : setMemRefs(MF, MergedMMOs);
449 : }
450 :
451 4 : void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
452 4 : MCSymbol *OldSymbol = getPreInstrSymbol();
453 4 : if (OldSymbol == Symbol)
454 : return;
455 4 : if (OldSymbol && !Symbol) {
456 : // We're removing a symbol rather than adding one. Try to clean up any
457 : // extra info carried around.
458 0 : if (Info.is<EIIK_PreInstrSymbol>()) {
459 : Info.clear();
460 0 : return;
461 : }
462 :
463 0 : if (memoperands_empty()) {
464 : assert(getPostInstrSymbol() &&
465 : "Should never have only a single symbol allocated out-of-line!");
466 0 : Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
467 0 : return;
468 : }
469 :
470 : // Otherwise fallback on the generic update.
471 4 : } else if (!Info || Info.is<EIIK_PreInstrSymbol>()) {
472 : // If we don't have any other extra info, we can store this inline.
473 : Info.set<EIIK_PreInstrSymbol>(Symbol);
474 4 : return;
475 : }
476 :
477 : // Otherwise, allocate a full new set of extra info.
478 : // FIXME: Maybe we should make the symbols in the extra info mutable?
479 0 : Info.set<EIIK_OutOfLine>(
480 : MF.createMIExtraInfo(memoperands(), Symbol, getPostInstrSymbol()));
481 : }
482 :
483 57 : void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
484 57 : MCSymbol *OldSymbol = getPostInstrSymbol();
485 57 : if (OldSymbol == Symbol)
486 : return;
487 57 : if (OldSymbol && !Symbol) {
488 : // We're removing a symbol rather than adding one. Try to clean up any
489 : // extra info carried around.
490 0 : if (Info.is<EIIK_PostInstrSymbol>()) {
491 : Info.clear();
492 0 : return;
493 : }
494 :
495 0 : if (memoperands_empty()) {
496 : assert(getPreInstrSymbol() &&
497 : "Should never have only a single symbol allocated out-of-line!");
498 0 : Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
499 0 : return;
500 : }
501 :
502 : // Otherwise fallback on the generic update.
503 57 : } else if (!Info || Info.is<EIIK_PostInstrSymbol>()) {
504 : // If we don't have any other extra info, we can store this inline.
505 : Info.set<EIIK_PostInstrSymbol>(Symbol);
506 55 : return;
507 : }
508 :
509 : // Otherwise, allocate a full new set of extra info.
510 : // FIXME: Maybe we should make the symbols in the extra info mutable?
511 2 : Info.set<EIIK_OutOfLine>(
512 : MF.createMIExtraInfo(memoperands(), getPreInstrSymbol(), Symbol));
513 : }
514 :
515 1140 : uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
516 : // For now, the just return the union of the flags. If the flags get more
517 : // complicated over time, we might need more logic here.
518 1140 : return getFlags() | Other.getFlags();
519 : }
520 :
521 510 : void MachineInstr::copyIRFlags(const Instruction &I) {
522 : // Copy the wrapping flags.
523 : if (const OverflowingBinaryOperator *OB =
524 : dyn_cast<OverflowingBinaryOperator>(&I)) {
525 250 : if (OB->hasNoSignedWrap())
526 : setFlag(MachineInstr::MIFlag::NoSWrap);
527 250 : if (OB->hasNoUnsignedWrap())
528 : setFlag(MachineInstr::MIFlag::NoUWrap);
529 : }
530 :
531 : // Copy the exact flag.
532 : if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
533 73 : if (PE->isExact())
534 : setFlag(MachineInstr::MIFlag::IsExact);
535 :
536 : // Copy the fast-math flags.
537 : if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
538 : const FastMathFlags Flags = FP->getFastMathFlags();
539 112 : if (Flags.noNaNs())
540 : setFlag(MachineInstr::MIFlag::FmNoNans);
541 112 : if (Flags.noInfs())
542 : setFlag(MachineInstr::MIFlag::FmNoInfs);
543 112 : if (Flags.noSignedZeros())
544 : setFlag(MachineInstr::MIFlag::FmNsz);
545 112 : if (Flags.allowReciprocal())
546 : setFlag(MachineInstr::MIFlag::FmArcp);
547 112 : if (Flags.allowContract())
548 : setFlag(MachineInstr::MIFlag::FmContract);
549 112 : if (Flags.approxFunc())
550 : setFlag(MachineInstr::MIFlag::FmAfn);
551 112 : if (Flags.allowReassoc())
552 : setFlag(MachineInstr::MIFlag::FmReassoc);
553 : }
554 510 : }
555 :
556 187061 : bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
557 : assert(!isBundledWithPred() && "Must be called on bundle header");
558 187061 : for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
559 359105 : if (MII->getDesc().getFlags() & Mask) {
560 67707 : if (Type == AnyInBundle)
561 : return true;
562 : } else {
563 291398 : if (Type == AllInBundle && !MII->isBundle())
564 : return false;
565 : }
566 : // This was the last instruction in the bundle.
567 286186 : if (!MII->isBundledWithSucc())
568 114142 : return Type == AllInBundle;
569 : }
570 : }
571 :
572 10495068 : bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
573 : MICheckType Check) const {
574 : // If opcodes or number of operands are not the same then the two
575 : // instructions are obviously not identical.
576 31485204 : if (Other.getOpcode() != getOpcode() ||
577 8758842 : Other.getNumOperands() != getNumOperands())
578 : return false;
579 :
580 8735460 : if (isBundle()) {
581 : // We have passed the test above that both instructions have the same
582 : // opcode, so we know that both instructions are bundles here. Let's compare
583 : // MIs inside the bundle.
584 : assert(Other.isBundle() && "Expected that both instructions are bundles.");
585 1 : MachineBasicBlock::const_instr_iterator I1 = getIterator();
586 1 : MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
587 : // Loop until we analysed the last intruction inside at least one of the
588 : // bundles.
589 3 : while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
590 : ++I1;
591 : ++I2;
592 2 : if (!I1->isIdenticalTo(*I2, Check))
593 : return false;
594 : }
595 : // If we've reached the end of just one of the two bundles, but not both,
596 : // the instructions are not identical.
597 1 : if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
598 : return false;
599 : }
600 :
601 : // Check operands to make sure they match.
602 44409021 : for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
603 38287596 : const MachineOperand &MO = getOperand(i);
604 38287596 : const MachineOperand &OMO = Other.getOperand(i);
605 38287596 : if (!MO.isReg()) {
606 13250139 : if (!MO.isIdenticalTo(OMO))
607 : return false;
608 : continue;
609 : }
610 :
611 : // Clients may or may not want to ignore defs when testing for equality.
612 : // For example, machine CSE pass only cares about finding common
613 : // subexpressions, so it's safe to ignore virtual register defs.
614 25037457 : if (MO.isDef()) {
615 9676791 : if (Check == IgnoreDefs)
616 : continue;
617 9676791 : else if (Check == IgnoreVRegDefs) {
618 9113130 : if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()) ||
619 2423497 : !TargetRegisterInfo::isVirtualRegister(OMO.getReg()))
620 2133526 : if (!MO.isIdenticalTo(OMO))
621 : return false;
622 : } else {
623 5120226 : if (!MO.isIdenticalTo(OMO))
624 : return false;
625 5118620 : if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
626 : return false;
627 : }
628 : } else {
629 15360666 : if (!MO.isIdenticalTo(OMO))
630 : return false;
631 14811529 : if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
632 : return false;
633 : }
634 : }
635 : // If DebugLoc does not match then two debug instructions are not identical.
636 : if (isDebugInstr())
637 23647 : if (getDebugLoc() && Other.getDebugLoc() &&
638 : getDebugLoc() != Other.getDebugLoc())
639 0 : return false;
640 : return true;
641 : }
642 :
643 34631142 : const MachineFunction *MachineInstr::getMF() const {
644 34631142 : return getParent()->getParent();
645 : }
646 :
647 11473 : MachineInstr *MachineInstr::removeFromParent() {
648 : assert(getParent() && "Not embedded in a basic block!");
649 11473 : return getParent()->remove(this);
650 : }
651 :
652 98 : MachineInstr *MachineInstr::removeFromBundle() {
653 : assert(getParent() && "Not embedded in a basic block!");
654 98 : return getParent()->remove_instr(this);
655 : }
656 :
657 4541485 : void MachineInstr::eraseFromParent() {
658 : assert(getParent() && "Not embedded in a basic block!");
659 4541485 : getParent()->erase(this);
660 : }
661 :
662 245676 : void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
663 : assert(getParent() && "Not embedded in a basic block!");
664 245676 : MachineBasicBlock *MBB = getParent();
665 245676 : MachineFunction *MF = MBB->getParent();
666 : assert(MF && "Not embedded in a function!");
667 :
668 : MachineInstr *MI = (MachineInstr *)this;
669 245676 : MachineRegisterInfo &MRI = MF->getRegInfo();
670 :
671 799375 : for (const MachineOperand &MO : MI->operands()) {
672 553699 : if (!MO.isReg() || !MO.isDef())
673 : continue;
674 248793 : unsigned Reg = MO.getReg();
675 248793 : if (!TargetRegisterInfo::isVirtualRegister(Reg))
676 : continue;
677 245860 : MRI.markUsesInDebugValueAsUndef(Reg);
678 : }
679 245676 : MI->eraseFromParent();
680 245676 : }
681 :
682 615236 : void MachineInstr::eraseFromBundle() {
683 : assert(getParent() && "Not embedded in a basic block!");
684 615236 : getParent()->erase_instr(this);
685 615236 : }
686 :
687 17691216 : unsigned MachineInstr::getNumExplicitOperands() const {
688 17691216 : unsigned NumOperands = MCID->getNumOperands();
689 35382432 : if (!MCID->isVariadic())
690 : return NumOperands;
691 :
692 13081 : for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
693 11536 : const MachineOperand &MO = getOperand(I);
694 : // The operands must always be in the following order:
695 : // - explicit reg defs,
696 : // - other explicit operands (reg uses, immediates, etc.),
697 : // - implicit reg defs
698 : // - implicit reg uses
699 11536 : if (MO.isReg() && MO.isImplicit())
700 : break;
701 10489 : ++NumOperands;
702 : }
703 : return NumOperands;
704 : }
705 :
706 3185515 : unsigned MachineInstr::getNumExplicitDefs() const {
707 3185515 : unsigned NumDefs = MCID->getNumDefs();
708 6371030 : if (!MCID->isVariadic())
709 : return NumDefs;
710 :
711 460241 : for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
712 460241 : const MachineOperand &MO = getOperand(I);
713 460241 : if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
714 : break;
715 995 : ++NumDefs;
716 : }
717 : return NumDefs;
718 : }
719 :
720 55563 : void MachineInstr::bundleWithPred() {
721 : assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
722 : setFlag(BundledPred);
723 55563 : MachineBasicBlock::instr_iterator Pred = getIterator();
724 : --Pred;
725 : assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
726 : Pred->setFlag(BundledSucc);
727 55563 : }
728 :
729 24387 : void MachineInstr::bundleWithSucc() {
730 : assert(!isBundledWithSucc() && "MI is already bundled with its successor");
731 : setFlag(BundledSucc);
732 24387 : MachineBasicBlock::instr_iterator Succ = getIterator();
733 : ++Succ;
734 : assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
735 : Succ->setFlag(BundledPred);
736 24387 : }
737 :
738 40504 : void MachineInstr::unbundleFromPred() {
739 : assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
740 : clearFlag(BundledPred);
741 40504 : MachineBasicBlock::instr_iterator Pred = getIterator();
742 : --Pred;
743 : assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
744 : Pred->clearFlag(BundledSucc);
745 40504 : }
746 :
747 118 : void MachineInstr::unbundleFromSucc() {
748 : assert(isBundledWithSucc() && "MI isn't bundled with its successor");
749 : clearFlag(BundledSucc);
750 118 : MachineBasicBlock::instr_iterator Succ = getIterator();
751 : ++Succ;
752 : assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
753 : Succ->clearFlag(BundledPred);
754 118 : }
755 :
756 38944644 : bool MachineInstr::isStackAligningInlineAsm() const {
757 38944644 : if (isInlineAsm()) {
758 16680 : unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
759 16680 : if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
760 21 : return true;
761 : }
762 : return false;
763 : }
764 :
765 24254 : InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
766 : assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
767 24254 : unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
768 24254 : return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
769 : }
770 :
771 10620 : int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
772 : unsigned *GroupNo) const {
773 : assert(isInlineAsm() && "Expected an inline asm instruction");
774 : assert(OpIdx < getNumOperands() && "OpIdx out of range");
775 :
776 : // Ignore queries about the initial operands.
777 10620 : if (OpIdx < InlineAsm::MIOp_FirstOperand)
778 : return -1;
779 :
780 : unsigned Group = 0;
781 : unsigned NumOps;
782 289759 : for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
783 : i += NumOps) {
784 289759 : const MachineOperand &FlagMO = getOperand(i);
785 : // If we reach the implicit register operands, stop looking.
786 289759 : if (!FlagMO.isImm())
787 : return -1;
788 279425 : NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
789 279425 : if (i + NumOps > OpIdx) {
790 286 : if (GroupNo)
791 0 : *GroupNo = Group;
792 286 : return i;
793 : }
794 279139 : ++Group;
795 : }
796 : return -1;
797 : }
798 :
799 8 : const DILabel *MachineInstr::getDebugLabel() const {
800 : assert(isDebugLabel() && "not a DBG_LABEL");
801 8 : return cast<DILabel>(getOperand(0).getMetadata());
802 : }
803 :
804 1385764 : const DILocalVariable *MachineInstr::getDebugVariable() const {
805 : assert(isDebugValue() && "not a DBG_VALUE");
806 1385764 : return cast<DILocalVariable>(getOperand(2).getMetadata());
807 : }
808 :
809 803590 : const DIExpression *MachineInstr::getDebugExpression() const {
810 : assert(isDebugValue() && "not a DBG_VALUE");
811 803590 : return cast<DIExpression>(getOperand(3).getMetadata());
812 : }
813 :
814 : const TargetRegisterClass*
815 113597 : MachineInstr::getRegClassConstraint(unsigned OpIdx,
816 : const TargetInstrInfo *TII,
817 : const TargetRegisterInfo *TRI) const {
818 : assert(getParent() && "Can't have an MBB reference here!");
819 : assert(getMF() && "Can't have an MF reference here!");
820 113597 : const MachineFunction &MF = *getMF();
821 :
822 : // Most opcodes have fixed constraints in their MCInstrDesc.
823 113597 : if (!isInlineAsm())
824 113348 : return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
825 :
826 498 : if (!getOperand(OpIdx).isReg())
827 : return nullptr;
828 :
829 : // For tied uses on inline asm, get the constraint from the def.
830 : unsigned DefIdx;
831 249 : if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
832 1 : OpIdx = DefIdx;
833 :
834 : // Inline asm stores register class constraints in the flag word.
835 249 : int FlagIdx = findInlineAsmFlagIdx(OpIdx);
836 249 : if (FlagIdx < 0)
837 : return nullptr;
838 :
839 498 : unsigned Flag = getOperand(FlagIdx).getImm();
840 : unsigned RCID;
841 18 : if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
842 5 : InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
843 249 : InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
844 : InlineAsm::hasRegClassConstraint(Flag, RCID))
845 492 : return TRI->getRegClass(RCID);
846 :
847 : // Assume that all registers in a memory operand are pointers.
848 3 : if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
849 3 : return TRI->getPointerRegClass(MF);
850 :
851 : return nullptr;
852 : }
853 :
854 45 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
855 : unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
856 : const TargetRegisterInfo *TRI, bool ExploreBundle) const {
857 : // Check every operands inside the bundle if we have
858 : // been asked to.
859 45 : if (ExploreBundle)
860 320 : for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
861 : ++OpndIt)
862 550 : CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
863 : OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
864 : else
865 : // Otherwise, just check the current operands.
866 0 : for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
867 0 : CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
868 45 : return CurRC;
869 : }
870 :
871 275 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
872 : unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
873 : const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
874 : assert(CurRC && "Invalid initial register class");
875 : // Check if Reg is constrained by some of its use/def from MI.
876 275 : const MachineOperand &MO = getOperand(OpIdx);
877 275 : if (!MO.isReg() || MO.getReg() != Reg)
878 : return CurRC;
879 : // If yes, accumulate the constraints through the operand.
880 47 : return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
881 : }
882 :
883 43155 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
884 : unsigned OpIdx, const TargetRegisterClass *CurRC,
885 : const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
886 43155 : const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
887 43155 : const MachineOperand &MO = getOperand(OpIdx);
888 : assert(MO.isReg() &&
889 : "Cannot get register constraints for non-register operand");
890 : assert(CurRC && "Invalid initial register class");
891 43155 : if (unsigned SubIdx = MO.getSubReg()) {
892 10758 : if (OpRC)
893 7459 : CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
894 : else
895 3299 : CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
896 32397 : } else if (OpRC)
897 23117 : CurRC = TRI->getCommonSubClass(CurRC, OpRC);
898 43155 : return CurRC;
899 : }
900 :
901 : /// Return the number of instructions inside the MI bundle, not counting the
902 : /// header instruction.
903 1566 : unsigned MachineInstr::getBundleSize() const {
904 1566 : MachineBasicBlock::const_instr_iterator I = getIterator();
905 : unsigned Size = 0;
906 5424 : while (I->isBundledWithSucc()) {
907 3858 : ++Size;
908 : ++I;
909 : }
910 1566 : return Size;
911 : }
912 :
913 : /// Returns true if the MachineInstr has an implicit-use operand of exactly
914 : /// the given register (not considering sub/super-registers).
915 6457550 : bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const {
916 36281657 : for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
917 36281655 : const MachineOperand &MO = getOperand(i);
918 36281655 : if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
919 : return true;
920 : }
921 : return false;
922 : }
923 :
924 : /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
925 : /// the specific register or -1 if it is not found. It further tightens
926 : /// the search criteria to a use that kills the register if isKill is true.
927 2546742 : int MachineInstr::findRegisterUseOperandIdx(
928 : unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
929 14818418 : for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
930 13314673 : const MachineOperand &MO = getOperand(i);
931 13314673 : if (!MO.isReg() || !MO.isUse())
932 : continue;
933 4586734 : unsigned MOReg = MO.getReg();
934 4586734 : if (!MOReg)
935 : continue;
936 3561823 : if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
937 463133 : TargetRegisterInfo::isPhysicalRegister(Reg) &&
938 463133 : TRI->isSubRegister(MOReg, Reg)))
939 1127666 : if (!isKill || MO.isKill())
940 1042997 : return i;
941 : }
942 : return -1;
943 : }
944 :
945 : /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
946 : /// indicating if this instruction reads or writes Reg. This also considers
947 : /// partial defines.
948 : std::pair<bool,bool>
949 6099203 : MachineInstr::readsWritesVirtualRegister(unsigned Reg,
950 : SmallVectorImpl<unsigned> *Ops) const {
951 : bool PartDef = false; // Partial redefine.
952 : bool FullDef = false; // Full define.
953 : bool Use = false;
954 :
955 32857060 : for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
956 26757857 : const MachineOperand &MO = getOperand(i);
957 26757857 : if (!MO.isReg() || MO.getReg() != Reg)
958 : continue;
959 6535387 : if (Ops)
960 1338217 : Ops->push_back(i);
961 6535387 : if (MO.isUse())
962 3767136 : Use |= !MO.isUndef();
963 2768251 : else if (MO.getSubReg() && !MO.isUndef())
964 : // A partial def undef doesn't count as reading the register.
965 : PartDef = true;
966 : else
967 : FullDef = true;
968 : }
969 : // A partial redefine uses Reg unless there is also a full define.
970 6099203 : return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
971 : }
972 :
973 : /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
974 : /// the specified register or -1 if it is not found. If isDead is true, defs
975 : /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
976 : /// also checks if there is a def of a super-register.
977 : int
978 12132877 : MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
979 : const TargetRegisterInfo *TRI) const {
980 : bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
981 69105300 : for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
982 59148441 : const MachineOperand &MO = getOperand(i);
983 : // Accept regmask operands when Overlap is set.
984 : // Ignore them when looking for a specific def operand (Overlap == false).
985 59148441 : if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
986 1875 : return i;
987 59146566 : if (!MO.isReg() || !MO.isDef())
988 : continue;
989 11609297 : unsigned MOReg = MO.getReg();
990 11609297 : bool Found = (MOReg == Reg);
991 11609297 : if (!Found && TRI && isPhys &&
992 : TargetRegisterInfo::isPhysicalRegister(MOReg)) {
993 4653504 : if (Overlap)
994 2493773 : Found = TRI->regsOverlap(MOReg, Reg);
995 : else
996 2159731 : Found = TRI->isSubRegister(MOReg, Reg);
997 : }
998 11609297 : if (Found && (!isDead || MO.isDead()))
999 2174143 : return i;
1000 : }
1001 : return -1;
1002 : }
1003 :
1004 : /// findFirstPredOperandIdx() - Find the index of the first operand in the
1005 : /// operand list that is used to represent the predicate. It returns -1 if
1006 : /// none is found.
1007 1206892 : int MachineInstr::findFirstPredOperandIdx() const {
1008 : // Don't call MCID.findFirstPredOperandIdx() because this variant
1009 : // is sometimes called on an instruction that's not yet complete, and
1010 : // so the number of operands is less than the MCID indicates. In
1011 : // particular, the PTX target does this.
1012 1206892 : const MCInstrDesc &MCID = getDesc();
1013 2413784 : if (MCID.isPredicable()) {
1014 3782173 : for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1015 3747579 : if (MCID.OpInfo[i].isPredicate())
1016 1056069 : return i;
1017 : }
1018 :
1019 : return -1;
1020 : }
1021 :
1022 : // MachineOperand::TiedTo is 4 bits wide.
1023 : const unsigned TiedMax = 15;
1024 :
1025 : /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1026 : ///
1027 : /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1028 : /// field. TiedTo can have these values:
1029 : ///
1030 : /// 0: Operand is not tied to anything.
1031 : /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1032 : /// TiedMax: Tied to an operand >= TiedMax-1.
1033 : ///
1034 : /// The tied def must be one of the first TiedMax operands on a normal
1035 : /// instruction. INLINEASM instructions allow more tied defs.
1036 : ///
1037 2207077 : void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1038 2207077 : MachineOperand &DefMO = getOperand(DefIdx);
1039 : MachineOperand &UseMO = getOperand(UseIdx);
1040 : assert(DefMO.isDef() && "DefIdx must be a def operand");
1041 : assert(UseMO.isUse() && "UseIdx must be a use operand");
1042 : assert(!DefMO.isTied() && "Def is already tied to another use");
1043 : assert(!UseMO.isTied() && "Use is already tied to another def");
1044 :
1045 2207077 : if (DefIdx < TiedMax)
1046 2206994 : UseMO.TiedTo = DefIdx + 1;
1047 : else {
1048 : // Inline asm can use the group descriptors to find tied operands, but on
1049 : // normal instruction, the tied def must be within the first TiedMax
1050 : // operands.
1051 : assert(isInlineAsm() && "DefIdx out of range");
1052 83 : UseMO.TiedTo = TiedMax;
1053 : }
1054 :
1055 : // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1056 2207077 : DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1057 2207077 : }
1058 :
1059 : /// Given the index of a tied register operand, find the operand it is tied to.
1060 : /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1061 : /// which must exist.
1062 5879341 : unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1063 5879341 : const MachineOperand &MO = getOperand(OpIdx);
1064 : assert(MO.isTied() && "Operand isn't tied");
1065 :
1066 : // Normally TiedTo is in range.
1067 5879341 : if (MO.TiedTo < TiedMax)
1068 5862796 : return MO.TiedTo - 1;
1069 :
1070 : // Uses on normal instructions can be out of range.
1071 16545 : if (!isInlineAsm()) {
1072 : // Normal tied defs must be in the 0..TiedMax-1 range.
1073 0 : if (MO.isUse())
1074 : return TiedMax - 1;
1075 : // MO is a def. Search for the tied use.
1076 0 : for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1077 : const MachineOperand &UseMO = getOperand(i);
1078 0 : if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1079 0 : return i;
1080 : }
1081 0 : llvm_unreachable("Can't find tied use");
1082 : }
1083 :
1084 : // Now deal with inline asm by parsing the operand group descriptor flags.
1085 : // Find the beginning of each operand group.
1086 : SmallVector<unsigned, 8> GroupIdx;
1087 : unsigned OpIdxGroup = ~0u;
1088 : unsigned NumOps;
1089 1477964 : for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1090 1461419 : i += NumOps) {
1091 1477964 : const MachineOperand &FlagMO = getOperand(i);
1092 : assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1093 1477964 : unsigned CurGroup = GroupIdx.size();
1094 1477964 : GroupIdx.push_back(i);
1095 1477964 : NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1096 : // OpIdx belongs to this operand group.
1097 1477964 : if (OpIdx > i && OpIdx < i + NumOps)
1098 : OpIdxGroup = CurGroup;
1099 : unsigned TiedGroup;
1100 1477964 : if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1101 : continue;
1102 : // Operands in this group are tied to operands in TiedGroup which must be
1103 : // earlier. Find the number of operands between the two groups.
1104 515969 : unsigned Delta = i - GroupIdx[TiedGroup];
1105 :
1106 : // OpIdx is a use tied to TiedGroup.
1107 515969 : if (OpIdxGroup == CurGroup)
1108 8869 : return OpIdx - Delta;
1109 :
1110 : // OpIdx is a def tied to this use group.
1111 507100 : if (OpIdxGroup == TiedGroup)
1112 7676 : return OpIdx + Delta;
1113 : }
1114 0 : llvm_unreachable("Invalid tied operand on inline asm");
1115 : }
1116 :
1117 : /// clearKillInfo - Clears kill flags on all operands.
1118 : ///
1119 34329 : void MachineInstr::clearKillInfo() {
1120 144854 : for (MachineOperand &MO : operands()) {
1121 110525 : if (MO.isReg() && MO.isUse())
1122 : MO.setIsKill(false);
1123 : }
1124 34329 : }
1125 :
1126 104395 : void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
1127 : unsigned SubIdx,
1128 : const TargetRegisterInfo &RegInfo) {
1129 104395 : if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1130 35596 : if (SubIdx)
1131 0 : ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1132 114678 : for (MachineOperand &MO : operands()) {
1133 79082 : if (!MO.isReg() || MO.getReg() != FromReg)
1134 : continue;
1135 35596 : MO.substPhysReg(ToReg, RegInfo);
1136 : }
1137 : } else {
1138 303224 : for (MachineOperand &MO : operands()) {
1139 234425 : if (!MO.isReg() || MO.getReg() != FromReg)
1140 : continue;
1141 68799 : MO.substVirtReg(ToReg, SubIdx, RegInfo);
1142 : }
1143 : }
1144 104395 : }
1145 :
1146 : /// isSafeToMove - Return true if it is safe to move this instruction. If
1147 : /// SawStore is set to true, it means that there is a store (or call) between
1148 : /// the instruction's location and its intended destination.
1149 20045037 : bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1150 : // Ignore stuff that we obviously can't move.
1151 : //
1152 : // Treat volatile loads as stores. This is not strictly necessary for
1153 : // volatiles, but it is required for atomic loads. It is not allowed to move
1154 : // a load across an atomic load with Ordering > Monotonic.
1155 52940730 : if (mayStore() || isCall() || isPHI() ||
1156 17711191 : (mayLoad() && hasOrderedMemoryRef())) {
1157 4146932 : SawStore = true;
1158 4146932 : return false;
1159 : }
1160 :
1161 28305177 : if (isPosition() || isDebugInstr() || isTerminator() ||
1162 13306889 : hasUnmodeledSideEffects())
1163 2691269 : return false;
1164 :
1165 : // See if this instruction does a load. If so, we have to guarantee that the
1166 : // loaded value doesn't change between the load and the its intended
1167 : // destination. The check for isInvariantLoad gives the targe the chance to
1168 : // classify the load as always returning a constant, e.g. a constant pool
1169 : // load.
1170 13206836 : if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1171 : // Otherwise, this is a real load. If there is a store between the load and
1172 : // end of block, we can't move it.
1173 1272604 : return !SawStore;
1174 :
1175 : return true;
1176 : }
1177 :
1178 4135861 : bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
1179 : bool UseTBAA) {
1180 : const MachineFunction *MF = getMF();
1181 4135861 : const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1182 4135861 : const MachineFrameInfo &MFI = MF->getFrameInfo();
1183 :
1184 : // If neither instruction stores to memory, they can't alias in any
1185 : // meaningful way, even if they read from the same address.
1186 4135861 : if (!mayStore() && !Other.mayStore())
1187 : return false;
1188 :
1189 : // Let the target decide if memory accesses cannot possibly overlap.
1190 4135861 : if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
1191 : return false;
1192 :
1193 : // FIXME: Need to handle multiple memory operands to support all targets.
1194 6449804 : if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1195 1750919 : return true;
1196 :
1197 2326958 : MachineMemOperand *MMOa = *memoperands_begin();
1198 2326958 : MachineMemOperand *MMOb = *Other.memoperands_begin();
1199 :
1200 : // The following interface to AA is fashioned after DAGCombiner::isAlias
1201 : // and operates with MachineMemOperand offset with some important
1202 : // assumptions:
1203 : // - LLVM fundamentally assumes flat address spaces.
1204 : // - MachineOperand offset can *only* result from legalization and
1205 : // cannot affect queries other than the trivial case of overlap
1206 : // checking.
1207 : // - These offsets never wrap and never step outside
1208 : // of allocated objects.
1209 : // - There should never be any negative offsets here.
1210 : //
1211 : // FIXME: Modify API to hide this math from "user"
1212 : // Even before we go to AA we can reason locally about some
1213 : // memory objects. It can save compile time, and possibly catch some
1214 : // corner cases not currently covered.
1215 :
1216 2326958 : int64_t OffsetA = MMOa->getOffset();
1217 2326958 : int64_t OffsetB = MMOb->getOffset();
1218 2326958 : int64_t MinOffset = std::min(OffsetA, OffsetB);
1219 :
1220 2326958 : uint64_t WidthA = MMOa->getSize();
1221 2326958 : uint64_t WidthB = MMOb->getSize();
1222 : bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1223 : bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1224 :
1225 : const Value *ValA = MMOa->getValue();
1226 : const Value *ValB = MMOb->getValue();
1227 2326958 : bool SameVal = (ValA && ValB && (ValA == ValB));
1228 : if (!SameVal) {
1229 : const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1230 : const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1231 1794407 : if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1232 : return false;
1233 1779635 : if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1234 : return false;
1235 1768482 : if (PSVa && PSVb && (PSVa == PSVb))
1236 : SameVal = true;
1237 : }
1238 :
1239 1253985 : if (SameVal) {
1240 1579599 : if (!KnownWidthA || !KnownWidthB)
1241 : return true;
1242 1579557 : int64_t MaxOffset = std::max(OffsetA, OffsetB);
1243 1579557 : int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1244 1579557 : return (MinOffset + LowWidth > MaxOffset);
1245 : }
1246 :
1247 721434 : if (!AA)
1248 : return true;
1249 :
1250 30199 : if (!ValA || !ValB)
1251 : return true;
1252 :
1253 : assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1254 : assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1255 :
1256 17802 : int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
1257 : : MemoryLocation::UnknownSize;
1258 17802 : int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
1259 : : MemoryLocation::UnknownSize;
1260 :
1261 17802 : AliasResult AAResult = AA->alias(
1262 17802 : MemoryLocation(ValA, OverlapA,
1263 17802 : UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1264 17802 : MemoryLocation(ValB, OverlapB,
1265 17802 : UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1266 :
1267 17802 : return (AAResult != NoAlias);
1268 : }
1269 :
1270 : /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1271 : /// or volatile memory reference, or if the information describing the memory
1272 : /// reference is not available. Return false if it is known to have no ordered
1273 : /// memory references.
1274 8076955 : bool MachineInstr::hasOrderedMemoryRef() const {
1275 : // An instruction known never to access memory won't have a volatile access.
1276 13530416 : if (!mayStore() &&
1277 8012079 : !mayLoad() &&
1278 10633835 : !isCall() &&
1279 2556880 : !hasUnmodeledSideEffects())
1280 : return false;
1281 :
1282 : // Otherwise, if the instruction has no memory reference information,
1283 : // conservatively assume it wasn't preserved.
1284 5526456 : if (memoperands_empty())
1285 : return true;
1286 :
1287 : // Check if any of our memory operands are ordered.
1288 5460890 : return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1289 0 : return !MMO->isUnordered();
1290 : });
1291 : }
1292 :
1293 : /// isDereferenceableInvariantLoad - Return true if this instruction will never
1294 : /// trap and is loading from a location whose value is invariant across a run of
1295 : /// this function.
1296 3160774 : bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
1297 : // If the instruction doesn't load at all, it isn't an invariant load.
1298 3160774 : if (!mayLoad())
1299 : return false;
1300 :
1301 : // If the instruction has lost its memoperands, conservatively assume that
1302 : // it may not be an invariant load.
1303 2827975 : if (memoperands_empty())
1304 : return false;
1305 :
1306 2804372 : const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1307 :
1308 3432722 : for (MachineMemOperand *MMO : memoperands()) {
1309 5608900 : if (MMO->isVolatile()) return false;
1310 2758982 : if (MMO->isStore()) return false;
1311 2716563 : if (MMO->isInvariant() && MMO->isDereferenceable())
1312 : continue;
1313 :
1314 : // A load from a constant PseudoSourceValue is invariant.
1315 513935 : if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1316 513935 : if (PSV->isConstant(&MFI))
1317 : continue;
1318 :
1319 2002984 : if (const Value *V = MMO->getValue()) {
1320 : // If we have an AliasAnalysis, ask it whether the memory is constant.
1321 3095820 : if (AA &&
1322 1110338 : AA->pointsToConstantMemory(
1323 3086369 : MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1324 9451 : continue;
1325 : }
1326 :
1327 : // Otherwise assume conservatively.
1328 : return false;
1329 : }
1330 :
1331 : // Everything checks out.
1332 : return true;
1333 : }
1334 :
1335 : /// isConstantValuePHI - If the specified instruction is a PHI that always
1336 : /// merges together the same virtual register, return the register, otherwise
1337 : /// return 0.
1338 31 : unsigned MachineInstr::isConstantValuePHI() const {
1339 : if (!isPHI())
1340 : return 0;
1341 : assert(getNumOperands() >= 3 &&
1342 : "It's illegal to have a PHI without source operands");
1343 :
1344 31 : unsigned Reg = getOperand(1).getReg();
1345 31 : for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1346 31 : if (getOperand(i).getReg() != Reg)
1347 : return 0;
1348 : return Reg;
1349 : }
1350 :
1351 33456063 : bool MachineInstr::hasUnmodeledSideEffects() const {
1352 33456063 : if (hasProperty(MCID::UnmodeledSideEffects))
1353 : return true;
1354 33150929 : if (isInlineAsm()) {
1355 38663 : unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1356 38663 : if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1357 30202 : return true;
1358 : }
1359 :
1360 : return false;
1361 : }
1362 :
1363 4215890 : bool MachineInstr::isLoadFoldBarrier() const {
1364 7701578 : return mayStore() || isCall() || hasUnmodeledSideEffects();
1365 : }
1366 :
1367 : /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1368 : ///
1369 2682865 : bool MachineInstr::allDefsAreDead() const {
1370 2818132 : for (const MachineOperand &MO : operands()) {
1371 2762052 : if (!MO.isReg() || MO.isUse())
1372 : continue;
1373 2691617 : if (!MO.isDead())
1374 : return false;
1375 : }
1376 : return true;
1377 : }
1378 :
1379 : /// copyImplicitOps - Copy implicit register operands from specified
1380 : /// instruction to this instruction.
1381 15971 : void MachineInstr::copyImplicitOps(MachineFunction &MF,
1382 : const MachineInstr &MI) {
1383 59154 : for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1384 43183 : i != e; ++i) {
1385 27212 : const MachineOperand &MO = MI.getOperand(i);
1386 27212 : if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1387 27212 : addOperand(MF, MO);
1388 : }
1389 15971 : }
1390 :
1391 42391 : bool MachineInstr::hasComplexRegisterTies() const {
1392 42391 : const MCInstrDesc &MCID = getDesc();
1393 168989 : for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1394 126608 : const auto &Operand = getOperand(I);
1395 126608 : if (!Operand.isReg() || Operand.isDef())
1396 : // Ignore the defined registers as MCID marks only the uses as tied.
1397 : continue;
1398 59032 : int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1399 59032 : int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1400 59032 : if (ExpectedTiedIdx != TiedIdx)
1401 : return true;
1402 : }
1403 : return false;
1404 : }
1405 :
1406 321310 : LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1407 : const MachineRegisterInfo &MRI) const {
1408 321310 : const MachineOperand &Op = getOperand(OpIdx);
1409 321310 : if (!Op.isReg())
1410 110724 : return LLT{};
1411 :
1412 210586 : if (isVariadic() || OpIdx >= getNumExplicitOperands())
1413 82213 : return MRI.getType(Op.getReg());
1414 :
1415 128373 : auto &OpInfo = getDesc().OpInfo[OpIdx];
1416 256746 : if (!OpInfo.isGenericType())
1417 115380 : return MRI.getType(Op.getReg());
1418 :
1419 12993 : if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1420 3144 : return LLT{};
1421 :
1422 9849 : LLT TypeToPrint = MRI.getType(Op.getReg());
1423 : // Don't mark the type index printed if it wasn't actually printed: maybe
1424 : // another operand with the same type index has an actual type attached:
1425 9849 : if (TypeToPrint.isValid())
1426 9829 : PrintedTypes.set(OpInfo.getGenericTypeIndex());
1427 9849 : return TypeToPrint;
1428 : }
1429 :
1430 : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1431 : LLVM_DUMP_METHOD void MachineInstr::dump() const {
1432 : dbgs() << " ";
1433 : print(dbgs());
1434 : }
1435 : #endif
1436 :
1437 134 : void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1438 : bool SkipDebugLoc, bool AddNewLine,
1439 : const TargetInstrInfo *TII) const {
1440 : const Module *M = nullptr;
1441 : const Function *F = nullptr;
1442 : if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1443 133 : F = &MF->getFunction();
1444 133 : M = F->getParent();
1445 133 : if (!TII)
1446 133 : TII = MF->getSubtarget().getInstrInfo();
1447 : }
1448 :
1449 268 : ModuleSlotTracker MST(M);
1450 134 : if (F)
1451 133 : MST.incorporateFunction(*F);
1452 134 : print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, TII);
1453 134 : }
1454 :
1455 61546 : void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1456 : bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1457 : bool AddNewLine, const TargetInstrInfo *TII) const {
1458 : // We can be a bit tidier if we know the MachineFunction.
1459 : const MachineFunction *MF = nullptr;
1460 61546 : const TargetRegisterInfo *TRI = nullptr;
1461 61546 : const MachineRegisterInfo *MRI = nullptr;
1462 61546 : const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1463 61546 : tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1464 :
1465 : if (isCFIInstruction())
1466 : assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1467 :
1468 61522 : SmallBitVector PrintedTypes(8);
1469 61546 : bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1470 : auto getTiedOperandIdx = [&](unsigned OpIdx) {
1471 : if (!ShouldPrintRegisterTies)
1472 : return 0U;
1473 : const MachineOperand &MO = getOperand(OpIdx);
1474 : if (MO.isReg() && MO.isTied() && !MO.isDef())
1475 : return findTiedOperandIdx(OpIdx);
1476 : return 0U;
1477 61546 : };
1478 : unsigned StartOp = 0;
1479 61546 : unsigned e = getNumOperands();
1480 :
1481 : // Print explicitly defined operands on the left of an assignment syntax.
1482 89854 : while (StartOp < e) {
1483 89474 : const MachineOperand &MO = getOperand(StartOp);
1484 89474 : if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1485 : break;
1486 :
1487 28308 : if (StartOp != 0)
1488 594 : OS << ", ";
1489 :
1490 28308 : LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1491 28308 : unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1492 28308 : MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
1493 : ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1494 28308 : ++StartOp;
1495 : }
1496 :
1497 61546 : if (StartOp != 0)
1498 27714 : OS << " = ";
1499 :
1500 61546 : if (getFlag(MachineInstr::FrameSetup))
1501 1165 : OS << "frame-setup ";
1502 61546 : if (getFlag(MachineInstr::FrameDestroy))
1503 280 : OS << "frame-destroy ";
1504 61546 : if (getFlag(MachineInstr::FmNoNans))
1505 0 : OS << "nnan ";
1506 61546 : if (getFlag(MachineInstr::FmNoInfs))
1507 0 : OS << "ninf ";
1508 61546 : if (getFlag(MachineInstr::FmNsz))
1509 0 : OS << "nsz ";
1510 61546 : if (getFlag(MachineInstr::FmArcp))
1511 0 : OS << "arcp ";
1512 61546 : if (getFlag(MachineInstr::FmContract))
1513 0 : OS << "contract ";
1514 61546 : if (getFlag(MachineInstr::FmAfn))
1515 0 : OS << "afn ";
1516 61546 : if (getFlag(MachineInstr::FmReassoc))
1517 0 : OS << "reassoc ";
1518 61546 : if (getFlag(MachineInstr::NoUWrap))
1519 2 : OS << "nuw ";
1520 61546 : if (getFlag(MachineInstr::NoSWrap))
1521 142 : OS << "nsw ";
1522 61546 : if (getFlag(MachineInstr::IsExact))
1523 0 : OS << "exact ";
1524 :
1525 : // Print the opcode name.
1526 61546 : if (TII)
1527 184635 : OS << TII->getName(getOpcode());
1528 : else
1529 1 : OS << "UNKNOWN";
1530 :
1531 61546 : if (SkipOpers)
1532 24 : return;
1533 :
1534 : // Print the rest of the operands.
1535 : bool FirstOp = true;
1536 : unsigned AsmDescOp = ~0u;
1537 : unsigned AsmOpCount = 0;
1538 :
1539 61546 : if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1540 : // Print asm string.
1541 0 : OS << " ";
1542 : const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1543 0 : LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1544 0 : unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1545 0 : getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1546 : ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1547 : IntrinsicInfo);
1548 :
1549 : // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1550 0 : unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1551 0 : if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1552 0 : OS << " [sideeffect]";
1553 0 : if (ExtraInfo & InlineAsm::Extra_MayLoad)
1554 0 : OS << " [mayload]";
1555 0 : if (ExtraInfo & InlineAsm::Extra_MayStore)
1556 0 : OS << " [maystore]";
1557 0 : if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1558 0 : OS << " [isconvergent]";
1559 0 : if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1560 0 : OS << " [alignstack]";
1561 0 : if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1562 0 : OS << " [attdialect]";
1563 0 : if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1564 0 : OS << " [inteldialect]";
1565 :
1566 : StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1567 : FirstOp = false;
1568 : }
1569 :
1570 228947 : for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1571 167401 : const MachineOperand &MO = getOperand(i);
1572 :
1573 167401 : if (FirstOp) FirstOp = false; else OS << ",";
1574 167401 : OS << " ";
1575 :
1576 167401 : if (isDebugValue() && MO.isMetadata()) {
1577 : // Pretty print DBG_VALUE instructions.
1578 2024 : auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1579 1012 : if (DIV && !DIV->getName().empty())
1580 2024 : OS << "!\"" << DIV->getName() << '\"';
1581 : else {
1582 1012 : LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1583 1012 : unsigned TiedOperandIdx = getTiedOperandIdx(i);
1584 1012 : MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1585 : ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1586 : }
1587 165377 : } else if (isDebugLabel() && MO.isMetadata()) {
1588 : // Pretty print DBG_LABEL instructions.
1589 0 : auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1590 0 : if (DIL && !DIL->getName().empty())
1591 0 : OS << "\"" << DIL->getName() << '\"';
1592 : else {
1593 0 : LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1594 0 : unsigned TiedOperandIdx = getTiedOperandIdx(i);
1595 0 : MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1596 : ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1597 : }
1598 165377 : } else if (i == AsmDescOp && MO.isImm()) {
1599 : // Pretty print the inline asm operand descriptor.
1600 0 : OS << '$' << AsmOpCount++;
1601 0 : unsigned Flag = MO.getImm();
1602 0 : switch (InlineAsm::getKind(Flag)) {
1603 0 : case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1604 0 : case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1605 0 : case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1606 0 : case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1607 0 : case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1608 0 : case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1609 0 : default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1610 : }
1611 :
1612 : unsigned RCID = 0;
1613 0 : if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1614 : InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1615 0 : if (TRI) {
1616 0 : OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1617 : } else
1618 0 : OS << ":RC" << RCID;
1619 : }
1620 :
1621 0 : if (InlineAsm::isMemKind(Flag)) {
1622 : unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1623 0 : switch (MCID) {
1624 0 : case InlineAsm::Constraint_es: OS << ":es"; break;
1625 0 : case InlineAsm::Constraint_i: OS << ":i"; break;
1626 0 : case InlineAsm::Constraint_m: OS << ":m"; break;
1627 0 : case InlineAsm::Constraint_o: OS << ":o"; break;
1628 0 : case InlineAsm::Constraint_v: OS << ":v"; break;
1629 0 : case InlineAsm::Constraint_Q: OS << ":Q"; break;
1630 0 : case InlineAsm::Constraint_R: OS << ":R"; break;
1631 0 : case InlineAsm::Constraint_S: OS << ":S"; break;
1632 0 : case InlineAsm::Constraint_T: OS << ":T"; break;
1633 0 : case InlineAsm::Constraint_Um: OS << ":Um"; break;
1634 0 : case InlineAsm::Constraint_Un: OS << ":Un"; break;
1635 0 : case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1636 0 : case InlineAsm::Constraint_Us: OS << ":Us"; break;
1637 0 : case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1638 0 : case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1639 0 : case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1640 0 : case InlineAsm::Constraint_X: OS << ":X"; break;
1641 0 : case InlineAsm::Constraint_Z: OS << ":Z"; break;
1642 0 : case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1643 0 : case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1644 0 : default: OS << ":?"; break;
1645 : }
1646 : }
1647 :
1648 : unsigned TiedTo = 0;
1649 : if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1650 0 : OS << " tiedto:$" << TiedTo;
1651 :
1652 : OS << ']';
1653 :
1654 : // Compute the index of the next operand descriptor.
1655 0 : AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1656 : } else {
1657 165377 : LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1658 165377 : unsigned TiedOperandIdx = getTiedOperandIdx(i);
1659 165377 : if (MO.isImm() && isOperandSubregIdx(i))
1660 631 : MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1661 : else
1662 164746 : MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1663 : ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1664 : }
1665 : }
1666 :
1667 : // Print any optional symbols attached to this instruction as-if they were
1668 : // operands.
1669 61546 : if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1670 0 : if (!FirstOp) {
1671 : FirstOp = false;
1672 : OS << ',';
1673 : }
1674 0 : OS << " pre-instr-symbol ";
1675 0 : MachineOperand::printSymbol(OS, *PreInstrSymbol);
1676 : }
1677 61546 : if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1678 0 : if (!FirstOp) {
1679 : FirstOp = false;
1680 : OS << ',';
1681 : }
1682 0 : OS << " post-instr-symbol ";
1683 0 : MachineOperand::printSymbol(OS, *PostInstrSymbol);
1684 : }
1685 :
1686 61546 : if (!SkipDebugLoc) {
1687 61522 : if (const DebugLoc &DL = getDebugLoc()) {
1688 4098 : if (!FirstOp)
1689 : OS << ',';
1690 4098 : OS << " debug-location ";
1691 4098 : DL->printAsOperand(OS, MST);
1692 : }
1693 : }
1694 :
1695 61546 : if (!memoperands_empty()) {
1696 : SmallVector<StringRef, 0> SSNs;
1697 : const LLVMContext *Context = nullptr;
1698 5260 : std::unique_ptr<LLVMContext> CtxPtr;
1699 : const MachineFrameInfo *MFI = nullptr;
1700 : if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1701 2630 : MFI = &MF->getFrameInfo();
1702 2630 : Context = &MF->getFunction().getContext();
1703 : } else {
1704 0 : CtxPtr = llvm::make_unique<LLVMContext>();
1705 : Context = CtxPtr.get();
1706 : }
1707 :
1708 2630 : OS << " :: ";
1709 : bool NeedComma = false;
1710 5820 : for (const MachineMemOperand *Op : memoperands()) {
1711 3190 : if (NeedComma)
1712 560 : OS << ", ";
1713 3190 : Op->print(OS, MST, SSNs, *Context, MFI, TII);
1714 : NeedComma = true;
1715 : }
1716 : }
1717 :
1718 61546 : if (SkipDebugLoc)
1719 : return;
1720 :
1721 : bool HaveSemi = false;
1722 :
1723 : // Print debug location information.
1724 61522 : if (const DebugLoc &DL = getDebugLoc()) {
1725 : if (!HaveSemi) {
1726 : OS << ';';
1727 : HaveSemi = true;
1728 : }
1729 : OS << ' ';
1730 4098 : DL.print(OS);
1731 : }
1732 :
1733 : // Print extra comments for DEBUG_VALUE.
1734 61522 : if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1735 1012 : if (!HaveSemi) {
1736 0 : OS << ";";
1737 : HaveSemi = true;
1738 : }
1739 1012 : auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1740 1012 : OS << " line no:" << DV->getLine();
1741 : if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1742 0 : DebugLoc InlinedAtDL(InlinedAt);
1743 : if (InlinedAtDL && MF) {
1744 : OS << " inlined @[ ";
1745 : InlinedAtDL.print(OS);
1746 : OS << " ]";
1747 : }
1748 : }
1749 : if (isIndirectDebugValue())
1750 0 : OS << " indirect";
1751 : }
1752 : // TODO: DBG_LABEL
1753 :
1754 61522 : if (AddNewLine)
1755 : OS << '\n';
1756 : }
1757 :
1758 11185132 : bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1759 : const TargetRegisterInfo *RegInfo,
1760 : bool AddIfNotFound) {
1761 : bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1762 18202707 : bool hasAliases = isPhysReg &&
1763 18202707 : MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1764 : bool Found = false;
1765 : SmallVector<unsigned,4> DeadOps;
1766 53432363 : for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1767 47337532 : MachineOperand &MO = getOperand(i);
1768 47337532 : if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1769 : continue;
1770 :
1771 : // DEBUG_VALUE nodes do not contribute to code generation and should
1772 : // always be ignored. Failure to do so may result in trying to modify
1773 : // KILL flags on DEBUG_VALUE nodes.
1774 27318630 : if (MO.isDebug())
1775 : continue;
1776 :
1777 27318630 : unsigned Reg = MO.getReg();
1778 27318630 : if (!Reg)
1779 : continue;
1780 :
1781 25180822 : if (Reg == IncomingReg) {
1782 6221680 : if (!Found) {
1783 6152627 : if (MO.isKill())
1784 : // The register is already marked kill.
1785 5090301 : return true;
1786 5142244 : if (isPhysReg && isRegTiedToDefOperand(i))
1787 : // Two-address uses of physregs must not be marked kill.
1788 : return true;
1789 : MO.setIsKill();
1790 : Found = true;
1791 : }
1792 18959142 : } else if (hasAliases && MO.isKill() &&
1793 : TargetRegisterInfo::isPhysicalRegister(Reg)) {
1794 : // A super-register kill already exists.
1795 7657503 : if (RegInfo->isSuperRegister(IncomingReg, Reg))
1796 : return true;
1797 3577585 : if (RegInfo->isSubRegister(IncomingReg, Reg))
1798 934913 : DeadOps.push_back(i);
1799 : }
1800 : }
1801 :
1802 : // Trim unneeded kill operands.
1803 7029744 : while (!DeadOps.empty()) {
1804 934913 : unsigned OpIdx = DeadOps.back();
1805 1869826 : if (getOperand(OpIdx).isImplicit() &&
1806 317 : (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1807 557153 : RemoveOperand(OpIdx);
1808 : else
1809 377760 : getOperand(OpIdx).setIsKill(false);
1810 : DeadOps.pop_back();
1811 : }
1812 :
1813 : // If not found, this means an alias of one of the operands is killed. Add a
1814 : // new implicit operand if required.
1815 6094831 : if (!Found && AddIfNotFound) {
1816 939316 : addOperand(MachineOperand::CreateReg(IncomingReg,
1817 : false /*IsDef*/,
1818 : true /*IsImp*/,
1819 : true /*IsKill*/));
1820 939316 : return true;
1821 : }
1822 : return Found;
1823 : }
1824 :
1825 345720 : void MachineInstr::clearRegisterKills(unsigned Reg,
1826 : const TargetRegisterInfo *RegInfo) {
1827 345720 : if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1828 : RegInfo = nullptr;
1829 1886647 : for (MachineOperand &MO : operands()) {
1830 1540927 : if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1831 : continue;
1832 88236 : unsigned OpReg = MO.getReg();
1833 88236 : if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1834 : MO.setIsKill(false);
1835 : }
1836 345720 : }
1837 :
1838 1133777 : bool MachineInstr::addRegisterDead(unsigned Reg,
1839 : const TargetRegisterInfo *RegInfo,
1840 : bool AddIfNotFound) {
1841 : bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1842 2165707 : bool hasAliases = isPhysReg &&
1843 2165707 : MCRegAliasIterator(Reg, RegInfo, false).isValid();
1844 : bool Found = false;
1845 : SmallVector<unsigned,4> DeadOps;
1846 13707527 : for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1847 12739617 : MachineOperand &MO = getOperand(i);
1848 12739617 : if (!MO.isReg() || !MO.isDef())
1849 : continue;
1850 5406248 : unsigned MOReg = MO.getReg();
1851 5406248 : if (!MOReg)
1852 : continue;
1853 :
1854 5406248 : if (MOReg == Reg) {
1855 : MO.setIsDead();
1856 : Found = true;
1857 4469120 : } else if (hasAliases && MO.isDead() &&
1858 : TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1859 : // There exists a super-register that's marked dead.
1860 1741889 : if (RegInfo->isSuperRegister(Reg, MOReg))
1861 165867 : return true;
1862 1576022 : if (RegInfo->isSubRegister(Reg, MOReg))
1863 30873 : DeadOps.push_back(i);
1864 : }
1865 : }
1866 :
1867 : // Trim unneeded dead operands.
1868 998783 : while (!DeadOps.empty()) {
1869 30873 : unsigned OpIdx = DeadOps.back();
1870 61746 : if (getOperand(OpIdx).isImplicit() &&
1871 10054 : (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1872 30728 : RemoveOperand(OpIdx);
1873 : else
1874 145 : getOperand(OpIdx).setIsDead(false);
1875 : DeadOps.pop_back();
1876 : }
1877 :
1878 : // If not found, this means an alias of one of the operands is dead. Add a
1879 : // new implicit operand if required.
1880 967910 : if (Found || !AddIfNotFound)
1881 : return Found;
1882 :
1883 30836 : addOperand(MachineOperand::CreateReg(Reg,
1884 : true /*IsDef*/,
1885 : true /*IsImp*/,
1886 : false /*IsKill*/,
1887 : true /*IsDead*/));
1888 30836 : return true;
1889 : }
1890 :
1891 34638 : void MachineInstr::clearRegisterDeads(unsigned Reg) {
1892 178289 : for (MachineOperand &MO : operands()) {
1893 143651 : if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1894 : continue;
1895 : MO.setIsDead(false);
1896 : }
1897 34638 : }
1898 :
1899 493606 : void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
1900 2529714 : for (MachineOperand &MO : operands()) {
1901 2036108 : if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1902 : continue;
1903 : MO.setIsUndef(IsUndef);
1904 : }
1905 493606 : }
1906 :
1907 2936571 : void MachineInstr::addRegisterDefined(unsigned Reg,
1908 : const TargetRegisterInfo *RegInfo) {
1909 2936571 : if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1910 : MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1911 65 : if (MO)
1912 : return;
1913 : } else {
1914 0 : for (const MachineOperand &MO : operands()) {
1915 0 : if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1916 : MO.getSubReg() == 0)
1917 : return;
1918 : }
1919 : }
1920 2936506 : addOperand(MachineOperand::CreateReg(Reg,
1921 : true /*IsDef*/,
1922 : true /*IsImp*/));
1923 : }
1924 :
1925 5066782 : void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1926 : const TargetRegisterInfo &TRI) {
1927 : bool HasRegMask = false;
1928 37352432 : for (MachineOperand &MO : operands()) {
1929 32285650 : if (MO.isRegMask()) {
1930 : HasRegMask = true;
1931 25415611 : continue;
1932 : }
1933 30117792 : if (!MO.isReg() || !MO.isDef()) continue;
1934 7332185 : unsigned Reg = MO.getReg();
1935 7332185 : if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1936 : // If there are no uses, including partial uses, the def is dead.
1937 6870039 : if (llvm::none_of(UsedRegs,
1938 0 : [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1939 : MO.setIsDead();
1940 : }
1941 :
1942 : // This is a call with a register mask operand.
1943 : // Mask clobbers are always dead, so add defs for the non-dead defines.
1944 5066782 : if (HasRegMask)
1945 2705265 : for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1946 4873123 : I != E; ++I)
1947 2705265 : addRegisterDefined(*I, &TRI);
1948 5066782 : }
1949 :
1950 : unsigned
1951 5923100 : MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1952 : // Build up a buffer of hash code components.
1953 : SmallVector<size_t, 8> HashComponents;
1954 5923100 : HashComponents.reserve(MI->getNumOperands() + 1);
1955 11846200 : HashComponents.push_back(MI->getOpcode());
1956 35491641 : for (const MachineOperand &MO : MI->operands()) {
1957 29568540 : if (MO.isReg() && MO.isDef() &&
1958 8138973 : TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1959 : continue; // Skip virtual register defs.
1960 :
1961 24482089 : HashComponents.push_back(hash_value(MO));
1962 : }
1963 5923102 : return hash_combine_range(HashComponents.begin(), HashComponents.end());
1964 : }
1965 :
1966 109 : void MachineInstr::emitError(StringRef Msg) const {
1967 : // Find the source location cookie.
1968 : unsigned LocCookie = 0;
1969 : const MDNode *LocMD = nullptr;
1970 2545 : for (unsigned i = getNumOperands(); i != 0; --i) {
1971 2448 : if (getOperand(i-1).isMetadata() &&
1972 2448 : (LocMD = getOperand(i-1).getMetadata()) &&
1973 12 : LocMD->getNumOperands() != 0) {
1974 : if (const ConstantInt *CI =
1975 : mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1976 12 : LocCookie = CI->getZExtValue();
1977 12 : break;
1978 : }
1979 : }
1980 : }
1981 :
1982 109 : if (const MachineBasicBlock *MBB = getParent())
1983 109 : if (const MachineFunction *MF = MBB->getParent())
1984 218 : return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1985 0 : report_fatal_error(Msg);
1986 : }
1987 :
1988 332633 : MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
1989 : const MCInstrDesc &MCID, bool IsIndirect,
1990 : unsigned Reg, const MDNode *Variable,
1991 : const MDNode *Expr) {
1992 : assert(isa<DILocalVariable>(Variable) && "not a variable");
1993 : assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
1994 : assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
1995 : "Expected inlined-at fields to agree");
1996 332633 : auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
1997 332633 : if (IsIndirect)
1998 : MIB.addImm(0U);
1999 : else
2000 302025 : MIB.addReg(0U, RegState::Debug);
2001 332633 : return MIB.addMetadata(Variable).addMetadata(Expr);
2002 : }
2003 :
2004 143464 : MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2005 : const MCInstrDesc &MCID, bool IsIndirect,
2006 : MachineOperand &MO, const MDNode *Variable,
2007 : const MDNode *Expr) {
2008 : assert(isa<DILocalVariable>(Variable) && "not a variable");
2009 : assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2010 : assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2011 : "Expected inlined-at fields to agree");
2012 143464 : if (MO.isReg())
2013 128613 : return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2014 :
2015 14851 : auto MIB = BuildMI(MF, DL, MCID).add(MO);
2016 14851 : if (IsIndirect)
2017 : MIB.addImm(0U);
2018 : else
2019 12638 : MIB.addReg(0U, RegState::Debug);
2020 14851 : return MIB.addMetadata(Variable).addMetadata(Expr);
2021 : }
2022 :
2023 201958 : MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2024 : MachineBasicBlock::iterator I,
2025 : const DebugLoc &DL, const MCInstrDesc &MCID,
2026 : bool IsIndirect, unsigned Reg,
2027 : const MDNode *Variable, const MDNode *Expr) {
2028 201958 : MachineFunction &MF = *BB.getParent();
2029 201958 : MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2030 : BB.insert(I, MI);
2031 201958 : return MachineInstrBuilder(MF, MI);
2032 : }
2033 :
2034 119859 : MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2035 : MachineBasicBlock::iterator I,
2036 : const DebugLoc &DL, const MCInstrDesc &MCID,
2037 : bool IsIndirect, MachineOperand &MO,
2038 : const MDNode *Variable, const MDNode *Expr) {
2039 119859 : MachineFunction &MF = *BB.getParent();
2040 119859 : MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2041 : BB.insert(I, MI);
2042 119859 : return MachineInstrBuilder(MF, *MI);
2043 : }
2044 :
2045 : /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2046 : /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2047 44 : static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
2048 : assert(MI.getOperand(0).isReg() && "can't spill non-register");
2049 : assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2050 : "Expected inlined-at fields to agree");
2051 :
2052 44 : const DIExpression *Expr = MI.getDebugExpression();
2053 : if (MI.isIndirectDebugValue()) {
2054 : assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
2055 24 : Expr = DIExpression::prepend(Expr, DIExpression::WithDeref);
2056 : }
2057 44 : return Expr;
2058 : }
2059 :
2060 42 : MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2061 : MachineBasicBlock::iterator I,
2062 : const MachineInstr &Orig,
2063 : int FrameIndex) {
2064 42 : const DIExpression *Expr = computeExprForSpill(Orig);
2065 84 : return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2066 : .addFrameIndex(FrameIndex)
2067 : .addImm(0U)
2068 42 : .addMetadata(Orig.getDebugVariable())
2069 42 : .addMetadata(Expr);
2070 : }
2071 :
2072 2 : void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
2073 2 : const DIExpression *Expr = computeExprForSpill(Orig);
2074 2 : Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
2075 4 : Orig.getOperand(1).ChangeToImmediate(0U);
2076 2 : Orig.getOperand(3).setMetadata(Expr);
2077 2 : }
2078 :
2079 144840 : void MachineInstr::collectDebugValues(
2080 : SmallVectorImpl<MachineInstr *> &DbgValues) {
2081 : MachineInstr &MI = *this;
2082 289680 : if (!MI.getOperand(0).isReg())
2083 : return;
2084 :
2085 : MachineBasicBlock::iterator DI = MI; ++DI;
2086 144838 : for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2087 156631 : DI != DE; ++DI) {
2088 156246 : if (!DI->isDebugValue())
2089 : return;
2090 23586 : if (DI->getOperand(0).isReg() &&
2091 11076 : DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2092 7142 : DbgValues.push_back(&*DI);
2093 : }
2094 : }
2095 :
2096 81881 : void MachineInstr::changeDebugValuesDefReg(unsigned Reg) {
2097 : // Collect matching debug values.
2098 : SmallVector<MachineInstr *, 2> DbgValues;
2099 81881 : collectDebugValues(DbgValues);
2100 :
2101 : // Propagate Reg to debug value instructions.
2102 81893 : for (auto *DBI : DbgValues)
2103 12 : DBI->getOperand(0).setReg(Reg);
2104 81881 : }
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