LCOV - code coverage report
Current view: top level - lib/CodeGen - MachineInstr.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1075 1267 84.8 %
Date: 2017-09-14 15:23:50 Functions: 94 98 95.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // Methods common to all machine instructions.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "llvm/CodeGen/MachineInstr.h"
      15             : #include "llvm/ADT/APFloat.h"
      16             : #include "llvm/ADT/ArrayRef.h"
      17             : #include "llvm/ADT/FoldingSet.h"
      18             : #include "llvm/ADT/Hashing.h"
      19             : #include "llvm/ADT/None.h"
      20             : #include "llvm/ADT/STLExtras.h"
      21             : #include "llvm/ADT/SmallString.h"
      22             : #include "llvm/ADT/SmallVector.h"
      23             : #include "llvm/Analysis/AliasAnalysis.h"
      24             : #include "llvm/Analysis/Loads.h"
      25             : #include "llvm/Analysis/MemoryLocation.h"
      26             : #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
      27             : #include "llvm/CodeGen/MachineBasicBlock.h"
      28             : #include "llvm/CodeGen/MachineFunction.h"
      29             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      30             : #include "llvm/CodeGen/MachineInstrBundle.h"
      31             : #include "llvm/CodeGen/MachineMemOperand.h"
      32             : #include "llvm/CodeGen/MachineModuleInfo.h"
      33             : #include "llvm/CodeGen/MachineOperand.h"
      34             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      35             : #include "llvm/CodeGen/PseudoSourceValue.h"
      36             : #include "llvm/IR/Constants.h"
      37             : #include "llvm/IR/DebugInfoMetadata.h"
      38             : #include "llvm/IR/DebugLoc.h"
      39             : #include "llvm/IR/DerivedTypes.h"
      40             : #include "llvm/IR/Function.h"
      41             : #include "llvm/IR/InlineAsm.h"
      42             : #include "llvm/IR/InstrTypes.h"
      43             : #include "llvm/IR/Intrinsics.h"
      44             : #include "llvm/IR/LLVMContext.h"
      45             : #include "llvm/IR/Metadata.h"
      46             : #include "llvm/IR/Module.h"
      47             : #include "llvm/IR/ModuleSlotTracker.h"
      48             : #include "llvm/IR/Type.h"
      49             : #include "llvm/IR/Value.h"
      50             : #include "llvm/MC/MCInstrDesc.h"
      51             : #include "llvm/MC/MCRegisterInfo.h"
      52             : #include "llvm/MC/MCSymbol.h"
      53             : #include "llvm/Support/Casting.h"
      54             : #include "llvm/Support/CommandLine.h"
      55             : #include "llvm/Support/Compiler.h"
      56             : #include "llvm/Support/Debug.h"
      57             : #include "llvm/Support/ErrorHandling.h"
      58             : #include "llvm/Support/LowLevelTypeImpl.h"
      59             : #include "llvm/Support/MathExtras.h"
      60             : #include "llvm/Support/raw_ostream.h"
      61             : #include "llvm/Target/TargetInstrInfo.h"
      62             : #include "llvm/Target/TargetIntrinsicInfo.h"
      63             : #include "llvm/Target/TargetMachine.h"
      64             : #include "llvm/Target/TargetRegisterInfo.h"
      65             : #include "llvm/Target/TargetSubtargetInfo.h"
      66             : #include <algorithm>
      67             : #include <cassert>
      68             : #include <cstddef>
      69             : #include <cstdint>
      70             : #include <cstring>
      71             : #include <iterator>
      72             : #include <utility>
      73             : 
      74             : using namespace llvm;
      75             : 
      76       72306 : static cl::opt<int> PrintRegMaskNumRegs(
      77             :     "print-regmask-num-regs",
      78      216918 :     cl::desc("Number of registers to limit to when "
      79             :              "printing regmask operands in IR dumps. "
      80             :              "unlimited = -1"),
      81      289224 :     cl::init(32), cl::Hidden);
      82             : 
      83             : //===----------------------------------------------------------------------===//
      84             : // MachineOperand Implementation
      85             : //===----------------------------------------------------------------------===//
      86             : 
      87     7424265 : void MachineOperand::setReg(unsigned Reg) {
      88     7424265 :   if (getReg() == Reg) return; // No change.
      89             : 
      90             :   // Otherwise, we have to change the register.  If this operand is embedded
      91             :   // into a machine function, we need to update the old and new register's
      92             :   // use/def lists.
      93     6972021 :   if (MachineInstr *MI = getParent())
      94     6962584 :     if (MachineBasicBlock *MBB = MI->getParent())
      95     6952246 :       if (MachineFunction *MF = MBB->getParent()) {
      96     6952246 :         MachineRegisterInfo &MRI = MF->getRegInfo();
      97     6952246 :         MRI.removeRegOperandFromUseList(this);
      98     6952246 :         SmallContents.RegNo = Reg;
      99     6952246 :         MRI.addRegOperandToUseList(this);
     100     6952246 :         return;
     101             :       }
     102             : 
     103             :   // Otherwise, just change the register, no problem.  :)
     104       19775 :   SmallContents.RegNo = Reg;
     105             : }
     106             : 
     107      965475 : void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
     108             :                                   const TargetRegisterInfo &TRI) {
     109             :   assert(TargetRegisterInfo::isVirtualRegister(Reg));
     110     1300481 :   if (SubIdx && getSubReg())
     111       33244 :     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
     112      965475 :   setReg(Reg);
     113      965475 :   if (SubIdx)
     114             :     setSubReg(SubIdx);
     115      965475 : }
     116             : 
     117      174199 : void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
     118             :   assert(TargetRegisterInfo::isPhysicalRegister(Reg));
     119      174199 :   if (getSubReg()) {
     120        9476 :     Reg = TRI.getSubReg(Reg, getSubReg());
     121             :     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
     122             :     // That won't happen in legal code.
     123        9476 :     setSubReg(0);
     124        9476 :     if (isDef())
     125             :       setIsUndef(false);
     126             :   }
     127      174199 :   setReg(Reg);
     128      174199 : }
     129             : 
     130             : /// Change a def to a use, or a use to a def.
     131       12140 : void MachineOperand::setIsDef(bool Val) {
     132             :   assert(isReg() && "Wrong MachineOperand accessor");
     133             :   assert((!Val || !isDebug()) && "Marking a debug operation as def");
     134       12140 :   if (IsDef == Val)
     135             :     return;
     136             :   // MRI may keep uses and defs in different list positions.
     137         496 :   if (MachineInstr *MI = getParent())
     138         482 :     if (MachineBasicBlock *MBB = MI->getParent())
     139         482 :       if (MachineFunction *MF = MBB->getParent()) {
     140         482 :         MachineRegisterInfo &MRI = MF->getRegInfo();
     141         482 :         MRI.removeRegOperandFromUseList(this);
     142         482 :         IsDef = Val;
     143         482 :         MRI.addRegOperandToUseList(this);
     144         482 :         return;
     145             :       }
     146          14 :   IsDef = Val;
     147             : }
     148             : 
     149             : // If this operand is currently a register operand, and if this is in a
     150             : // function, deregister the operand from the register's use/def list.
     151      272248 : void MachineOperand::removeRegFromUses() {
     152      272248 :   if (!isReg() || !isOnRegUseList())
     153             :     return;
     154             : 
     155       68103 :   if (MachineInstr *MI = getParent()) {
     156       68103 :     if (MachineBasicBlock *MBB = MI->getParent()) {
     157       68103 :       if (MachineFunction *MF = MBB->getParent())
     158       68103 :         MF->getRegInfo().removeRegOperandFromUseList(this);
     159             :     }
     160             :   }
     161             : }
     162             : 
     163             : /// ChangeToImmediate - Replace this operand with a new immediate operand of
     164             : /// the specified value.  If an operand is known to be an immediate already,
     165             : /// the setImm method should be used.
     166      272168 : void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
     167             :   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
     168             : 
     169      272168 :   removeRegFromUses();
     170             : 
     171      272168 :   OpKind = MO_Immediate;
     172      272168 :   Contents.ImmVal = ImmVal;
     173      272168 : }
     174             : 
     175           0 : void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
     176             :   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
     177             : 
     178           0 :   removeRegFromUses();
     179             : 
     180           0 :   OpKind = MO_FPImmediate;
     181           0 :   Contents.CFP = FPImm;
     182           0 : }
     183             : 
     184           0 : void MachineOperand::ChangeToES(const char *SymName, unsigned char TargetFlags) {
     185             :   assert((!isReg() || !isTied()) &&
     186             :          "Cannot change a tied operand into an external symbol");
     187             : 
     188           0 :   removeRegFromUses();
     189             : 
     190           0 :   OpKind = MO_ExternalSymbol;
     191           0 :   Contents.OffsetedInfo.Val.SymbolName = SymName;
     192           0 :   setOffset(0); // Offset is always 0.
     193           0 :   setTargetFlags(TargetFlags);
     194           0 : }
     195             : 
     196           0 : void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
     197             :   assert((!isReg() || !isTied()) &&
     198             :          "Cannot change a tied operand into an MCSymbol");
     199             : 
     200           0 :   removeRegFromUses();
     201             : 
     202           0 :   OpKind = MO_MCSymbol;
     203           0 :   Contents.Sym = Sym;
     204           0 : }
     205             : 
     206          79 : void MachineOperand::ChangeToFrameIndex(int Idx) {
     207             :   assert((!isReg() || !isTied()) &&
     208             :          "Cannot change a tied operand into a FrameIndex");
     209             : 
     210          79 :   removeRegFromUses();
     211             : 
     212          79 :   OpKind = MO_FrameIndex;
     213         158 :   setIndex(Idx);
     214          79 : }
     215             : 
     216           1 : void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
     217             :                                          unsigned char TargetFlags) {
     218             :   assert((!isReg() || !isTied()) &&
     219             :          "Cannot change a tied operand into a FrameIndex");
     220             : 
     221           1 :   removeRegFromUses();
     222             : 
     223           1 :   OpKind = MO_TargetIndex;
     224           2 :   setIndex(Idx);
     225           2 :   setOffset(Offset);
     226           2 :   setTargetFlags(TargetFlags);
     227           1 : }
     228             : 
     229             : /// ChangeToRegister - Replace this operand with a new register operand of
     230             : /// the specified value.  If an operand is known to be an register already,
     231             : /// the setReg method should be used.
     232      271996 : void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
     233             :                                       bool isKill, bool isDead, bool isUndef,
     234             :                                       bool isDebug) {
     235      271996 :   MachineRegisterInfo *RegInfo = nullptr;
     236      271996 :   if (MachineInstr *MI = getParent())
     237      271996 :     if (MachineBasicBlock *MBB = MI->getParent())
     238      271995 :       if (MachineFunction *MF = MBB->getParent())
     239      271995 :         RegInfo = &MF->getRegInfo();
     240             :   // If this operand is already a register operand, remove it from the
     241             :   // register's use/def lists.
     242      271996 :   bool WasReg = isReg();
     243      271996 :   if (RegInfo && WasReg)
     244       37271 :     RegInfo->removeRegOperandFromUseList(this);
     245             : 
     246             :   // Change this to a register and set the reg#.
     247      271996 :   OpKind = MO_Register;
     248      271996 :   SmallContents.RegNo = Reg;
     249      271996 :   SubReg_TargetFlags = 0;
     250      271996 :   IsDef = isDef;
     251      271996 :   IsImp = isImp;
     252      271996 :   IsKill = isKill;
     253      271996 :   IsDead = isDead;
     254      271996 :   IsUndef = isUndef;
     255      271996 :   IsInternalRead = false;
     256      271996 :   IsEarlyClobber = false;
     257      271996 :   IsDebug = isDebug;
     258             :   // Ensure isOnRegUseList() returns false.
     259      271996 :   Contents.Reg.Prev = nullptr;
     260             :   // Preserve the tie when the operand was already a register.
     261      271996 :   if (!WasReg)
     262      234725 :     TiedTo = 0;
     263             : 
     264             :   // If this operand is embedded in a function, add the operand to the
     265             :   // register's use/def list.
     266      271996 :   if (RegInfo)
     267      271995 :     RegInfo->addRegOperandToUseList(this);
     268      271996 : }
     269             : 
     270             : /// isIdenticalTo - Return true if this operand is identical to the specified
     271             : /// operand. Note that this should stay in sync with the hash_value overload
     272             : /// below.
     273    15356272 : bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
     274    45850603 :   if (getType() != Other.getType() ||
     275    30276118 :       getTargetFlags() != Other.getTargetFlags())
     276             :     return false;
     277             : 
     278    15127461 :   switch (getType()) {
     279     7673464 :   case MachineOperand::MO_Register:
     280    29958265 :     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
     281    14856282 :            getSubReg() == Other.getSubReg();
     282     5778872 :   case MachineOperand::MO_Immediate:
     283     5778872 :     return getImm() == Other.getImm();
     284           0 :   case MachineOperand::MO_CImmediate:
     285           0 :     return getCImm() == Other.getCImm();
     286          82 :   case MachineOperand::MO_FPImmediate:
     287          82 :     return getFPImm() == Other.getFPImm();
     288        8062 :   case MachineOperand::MO_MachineBasicBlock:
     289        8062 :     return getMBB() == Other.getMBB();
     290      211223 :   case MachineOperand::MO_FrameIndex:
     291      211223 :     return getIndex() == Other.getIndex();
     292       20880 :   case MachineOperand::MO_ConstantPoolIndex:
     293             :   case MachineOperand::MO_TargetIndex:
     294       59528 :     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
     295         146 :   case MachineOperand::MO_JumpTableIndex:
     296         146 :     return getIndex() == Other.getIndex();
     297      934048 :   case MachineOperand::MO_GlobalAddress:
     298     2299578 :     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
     299        4510 :   case MachineOperand::MO_ExternalSymbol:
     300        8967 :     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
     301        8914 :            getOffset() == Other.getOffset();
     302         121 :   case MachineOperand::MO_BlockAddress:
     303         242 :     return getBlockAddress() == Other.getBlockAddress() &&
     304         242 :            getOffset() == Other.getOffset();
     305      195408 :   case MachineOperand::MO_RegisterMask:
     306             :   case MachineOperand::MO_RegisterLiveOut: {
     307             :     // Shallow compare of the two RegMasks
     308      195408 :     const uint32_t *RegMask = getRegMask();
     309      195408 :     const uint32_t *OtherRegMask = Other.getRegMask();
     310      195408 :     if (RegMask == OtherRegMask)
     311             :       return true;
     312             : 
     313             :     // Calculate the size of the RegMask
     314           0 :     const MachineFunction *MF = getParent()->getParent()->getParent();
     315           0 :     const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     316           0 :     unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
     317             : 
     318             :     // Deep compare of the two RegMasks
     319           0 :     return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
     320             :   }
     321      268317 :   case MachineOperand::MO_MCSymbol:
     322      268317 :     return getMCSymbol() == Other.getMCSymbol();
     323       30684 :   case MachineOperand::MO_CFIIndex:
     324       30684 :     return getCFIIndex() == Other.getCFIIndex();
     325        1644 :   case MachineOperand::MO_Metadata:
     326        1644 :     return getMetadata() == Other.getMetadata();
     327           0 :   case MachineOperand::MO_IntrinsicID:
     328           0 :     return getIntrinsicID() == Other.getIntrinsicID();
     329           0 :   case MachineOperand::MO_Predicate:
     330           0 :     return getPredicate() == Other.getPredicate();
     331             :   }
     332           0 :   llvm_unreachable("Invalid machine operand type");
     333             : }
     334             : 
     335             : // Note: this must stay exactly in sync with isIdenticalTo above.
     336    23327855 : hash_code llvm::hash_value(const MachineOperand &MO) {
     337    23327855 :   switch (MO.getType()) {
     338    13131670 :   case MachineOperand::MO_Register:
     339             :     // Register operands don't have target flags.
     340    26263340 :     return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
     341     9147347 :   case MachineOperand::MO_Immediate:
     342    18294694 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
     343           0 :   case MachineOperand::MO_CImmediate:
     344           0 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
     345         219 :   case MachineOperand::MO_FPImmediate:
     346         438 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
     347       84590 :   case MachineOperand::MO_MachineBasicBlock:
     348      169180 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
     349      251682 :   case MachineOperand::MO_FrameIndex:
     350      503364 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
     351       56551 :   case MachineOperand::MO_ConstantPoolIndex:
     352             :   case MachineOperand::MO_TargetIndex:
     353      169653 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
     354      226204 :                         MO.getOffset());
     355         441 :   case MachineOperand::MO_JumpTableIndex:
     356         882 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
     357       13038 :   case MachineOperand::MO_ExternalSymbol:
     358       52152 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
     359       39114 :                         MO.getSymbolName());
     360      641827 :   case MachineOperand::MO_GlobalAddress:
     361     1925481 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
     362     2567308 :                         MO.getOffset());
     363         340 :   case MachineOperand::MO_BlockAddress:
     364         680 :     return hash_combine(MO.getType(), MO.getTargetFlags(),
     365        1360 :                         MO.getBlockAddress(), MO.getOffset());
     366           2 :   case MachineOperand::MO_RegisterMask:
     367             :   case MachineOperand::MO_RegisterLiveOut:
     368           4 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
     369           0 :   case MachineOperand::MO_Metadata:
     370           0 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
     371         148 :   case MachineOperand::MO_MCSymbol:
     372         296 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
     373           0 :   case MachineOperand::MO_CFIIndex:
     374           0 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
     375           0 :   case MachineOperand::MO_IntrinsicID:
     376           0 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
     377           0 :   case MachineOperand::MO_Predicate:
     378           0 :     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
     379             :   }
     380           0 :   llvm_unreachable("Invalid machine operand type");
     381             : }
     382             : 
     383           3 : void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
     384             :                            const TargetIntrinsicInfo *IntrinsicInfo) const {
     385           6 :   ModuleSlotTracker DummyMST(nullptr);
     386           3 :   print(OS, DummyMST, TRI, IntrinsicInfo);
     387           3 : }
     388             : 
     389      142314 : void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
     390             :                            const TargetRegisterInfo *TRI,
     391             :                            const TargetIntrinsicInfo *IntrinsicInfo) const {
     392      142314 :   switch (getType()) {
     393       81643 :   case MachineOperand::MO_Register:
     394      244929 :     OS << PrintReg(getReg(), TRI, getSubReg());
     395             : 
     396      214804 :     if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
     397      119668 :         isInternalRead() || isEarlyClobber() || isTied()) {
     398       69580 :       OS << '<';
     399       69580 :       bool NeedComma = false;
     400       69580 :       if (isDef()) {
     401             :         if (NeedComma) OS << ',';
     402       40870 :         if (isEarlyClobber())
     403         469 :           OS << "earlyclobber,";
     404       40870 :         if (isImplicit())
     405       20048 :           OS << "imp-";
     406       40870 :         OS << "def";
     407       40870 :         NeedComma = true;
     408             :         // <def,read-undef> only makes sense when getSubReg() is set.
     409             :         // Don't clutter the output otherwise.
     410       40958 :         if (isUndef() && getSubReg())
     411          88 :           OS << ",read-undef";
     412       28710 :       } else if (isImplicit()) {
     413       22377 :         OS << "imp-use";
     414       22377 :         NeedComma = true;
     415             :       }
     416             : 
     417       69580 :       if (isKill()) {
     418        7368 :         if (NeedComma) OS << ',';
     419        7368 :         OS << "kill";
     420        7368 :         NeedComma = true;
     421             :       }
     422       69580 :       if (isDead()) {
     423       14248 :         if (NeedComma) OS << ',';
     424       14248 :         OS << "dead";
     425       14248 :         NeedComma = true;
     426             :       }
     427       69900 :       if (isUndef() && isUse()) {
     428         232 :         if (NeedComma) OS << ',';
     429         232 :         OS << "undef";
     430         232 :         NeedComma = true;
     431             :       }
     432       69580 :       if (isInternalRead()) {
     433           6 :         if (NeedComma) OS << ',';
     434           6 :         OS << "internal";
     435           6 :         NeedComma = true;
     436             :       }
     437       69580 :       if (isTied()) {
     438        1302 :         if (NeedComma) OS << ',';
     439        1302 :         OS << "tied";
     440        1302 :         if (TiedTo != 15)
     441        1302 :           OS << unsigned(TiedTo - 1);
     442             :       }
     443             :       OS << '>';
     444             :     }
     445             :     break;
     446       37695 :   case MachineOperand::MO_Immediate:
     447       37695 :     OS << getImm();
     448       37695 :     break;
     449           3 :   case MachineOperand::MO_CImmediate:
     450           6 :     getCImm()->getValue().print(OS, false);
     451           3 :     break;
     452           3 :   case MachineOperand::MO_FPImmediate:
     453           6 :     if (getFPImm()->getType()->isFloatTy()) {
     454           0 :       OS << getFPImm()->getValueAPF().convertToFloat();
     455           6 :     } else if (getFPImm()->getType()->isHalfTy()) {
     456           0 :       APFloat APF = getFPImm()->getValueAPF();
     457             :       bool Unused;
     458           0 :       APF.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &Unused);
     459           0 :       OS << "half " << APF.convertToFloat();
     460           6 :     } else if (getFPImm()->getType()->isFP128Ty()) {
     461           6 :       APFloat APF = getFPImm()->getValueAPF();
     462           4 :       SmallString<16> Str;
     463           4 :       getFPImm()->getValueAPF().toString(Str);
     464           4 :       OS << "quad " << Str;
     465           2 :     } else if (getFPImm()->getType()->isX86_FP80Ty()) {
     466           3 :       APFloat APF = getFPImm()->getValueAPF();
     467           1 :       OS << "x86_fp80 0xK";
     468           2 :       APInt API = APF.bitcastToAPInt();
     469           3 :       OS << format_hex_no_prefix(API.getHiBits(16).getZExtValue(), 4,
     470           1 :                                  /*Upper=*/true);
     471           3 :       OS << format_hex_no_prefix(API.getLoBits(64).getZExtValue(), 16,
     472           1 :                                  /*Upper=*/true);
     473             :     } else {
     474           0 :       OS << getFPImm()->getValueAPF().convertToDouble();
     475             :     }
     476             :     break;
     477        8696 :   case MachineOperand::MO_MachineBasicBlock:
     478       17392 :     OS << "<BB#" << getMBB()->getNumber() << ">";
     479        8696 :     break;
     480          81 :   case MachineOperand::MO_FrameIndex:
     481         162 :     OS << "<fi#" << getIndex() << '>';
     482             :     break;
     483           2 :   case MachineOperand::MO_ConstantPoolIndex:
     484           4 :     OS << "<cp#" << getIndex();
     485           4 :     if (getOffset()) OS << "+" << getOffset();
     486             :     OS << '>';
     487             :     break;
     488           0 :   case MachineOperand::MO_TargetIndex:
     489           0 :     OS << "<ti#" << getIndex();
     490           0 :     if (getOffset()) OS << "+" << getOffset();
     491             :     OS << '>';
     492             :     break;
     493        2057 :   case MachineOperand::MO_JumpTableIndex:
     494        4114 :     OS << "<jt#" << getIndex() << '>';
     495             :     break;
     496        5679 :   case MachineOperand::MO_GlobalAddress:
     497        5679 :     OS << "<ga:";
     498        5679 :     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
     499       11358 :     if (getOffset()) OS << "+" << getOffset();
     500             :     OS << '>';
     501             :     break;
     502          20 :   case MachineOperand::MO_ExternalSymbol:
     503          20 :     OS << "<es:" << getSymbolName();
     504          40 :     if (getOffset()) OS << "+" << getOffset();
     505             :     OS << '>';
     506             :     break;
     507           0 :   case MachineOperand::MO_BlockAddress:
     508           0 :     OS << '<';
     509           0 :     getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
     510           0 :     if (getOffset()) OS << "+" << getOffset();
     511             :     OS << '>';
     512             :     break;
     513        5674 :   case MachineOperand::MO_RegisterMask: {
     514        5674 :     unsigned NumRegsInMask = 0;
     515        5674 :     unsigned NumRegsEmitted = 0;
     516        5674 :     OS << "<regmask";
     517     2732606 :     for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
     518     2726932 :       unsigned MaskWord = i / 32;
     519     2726932 :       unsigned MaskBit = i % 32;
     520     2726932 :       if (getRegMask()[MaskWord] & (1 << MaskBit)) {
     521     1080812 :         if (PrintRegMaskNumRegs < 0 ||
     522      540406 :             NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
     523      560445 :           OS << " " << PrintReg(i, TRI);
     524      186815 :           NumRegsEmitted++;
     525             :         }
     526      540406 :         NumRegsInMask++;
     527             :       }
     528             :     }
     529        5674 :     if (NumRegsEmitted != NumRegsInMask)
     530       11262 :       OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
     531        5674 :     OS << ">";
     532        5674 :     break;
     533             :   }
     534           0 :   case MachineOperand::MO_RegisterLiveOut:
     535           0 :     OS << "<regliveout>";
     536           0 :     break;
     537          20 :   case MachineOperand::MO_Metadata:
     538          20 :     OS << '<';
     539          20 :     getMetadata()->printAsOperand(OS, MST);
     540             :     OS << '>';
     541             :     break;
     542           2 :   case MachineOperand::MO_MCSymbol:
     543           4 :     OS << "<MCSym=" << *getMCSymbol() << '>';
     544             :     break;
     545         738 :   case MachineOperand::MO_CFIIndex:
     546         738 :     OS << "<call frame instruction>";
     547         738 :     break;
     548           0 :   case MachineOperand::MO_IntrinsicID: {
     549           0 :     Intrinsic::ID ID = getIntrinsicID();
     550           0 :     if (ID < Intrinsic::num_intrinsics)
     551           0 :       OS << "<intrinsic:@" << Intrinsic::getName(ID, None) << '>';
     552           0 :     else if (IntrinsicInfo)
     553           0 :       OS << "<intrinsic:@" << IntrinsicInfo->getName(ID) << '>';
     554             :     else
     555           0 :       OS << "<intrinsic:" << ID << '>';
     556             :     break;
     557             :   }
     558           1 :   case MachineOperand::MO_Predicate: {
     559           1 :     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
     560           2 :     OS << '<' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred")
     561           1 :        << CmpInst::getPredicateName(Pred) << '>';
     562             :     break;
     563             :   }
     564             :   }
     565       60671 :   if (unsigned TF = getTargetFlags())
     566        4106 :     OS << "[TF=" << TF << ']';
     567      142314 : }
     568             : 
     569             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     570             : LLVM_DUMP_METHOD void MachineOperand::dump() const {
     571             :   dbgs() << *this << '\n';
     572             : }
     573             : #endif
     574             : 
     575             : //===----------------------------------------------------------------------===//
     576             : // MachineMemOperand Implementation
     577             : //===----------------------------------------------------------------------===//
     578             : 
     579             : /// getAddrSpace - Return the LLVM IR address space number that this pointer
     580             : /// points into.
     581    13231231 : unsigned MachinePointerInfo::getAddrSpace() const {
     582    39372895 :   if (V.isNull() || V.is<const PseudoSourceValue*>()) return 0;
     583    40712772 :   return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
     584             : }
     585             : 
     586             : /// isDereferenceable - Return true if V is always dereferenceable for 
     587             : /// Offset + Size byte.
     588        2056 : bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
     589             :                                            const DataLayout &DL) const {
     590        4112 :   if (!V.is<const Value*>())
     591             :     return false;
     592             : 
     593        4112 :   const Value *BasePtr = V.get<const Value*>();
     594        2056 :   if (BasePtr == nullptr)
     595             :     return false;
     596             : 
     597             :   return isDereferenceableAndAlignedPointer(
     598        5144 :       BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
     599             : }
     600             : 
     601             : /// getConstantPool - Return a MachinePointerInfo record that refers to the
     602             : /// constant pool.
     603       20632 : MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
     604       41264 :   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
     605             : }
     606             : 
     607             : /// getFixedStack - Return a MachinePointerInfo record that refers to the
     608             : /// the specified FrameIndex.
     609      133399 : MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
     610             :                                                      int FI, int64_t Offset) {
     611      266798 :   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
     612             : }
     613             : 
     614         191 : MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
     615         382 :   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
     616             : }
     617             : 
     618       12649 : MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
     619       25298 :   return MachinePointerInfo(MF.getPSVManager().getGOT());
     620             : }
     621             : 
     622      144538 : MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
     623             :                                                 int64_t Offset,
     624             :                                                 uint8_t ID) {
     625      433614 :   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset,ID);
     626             : }
     627             : 
     628     1458092 : MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
     629             :                                      uint64_t s, unsigned int a,
     630             :                                      const AAMDNodes &AAInfo,
     631             :                                      const MDNode *Ranges,
     632             :                                      SyncScope::ID SSID,
     633             :                                      AtomicOrdering Ordering,
     634     1458092 :                                      AtomicOrdering FailureOrdering)
     635     1458092 :     : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
     636     2916184 :       AAInfo(AAInfo), Ranges(Ranges) {
     637             :   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
     638             :           isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
     639             :          "invalid pointer value");
     640             :   assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
     641             :   assert((isLoad() || isStore()) && "Not a load/store!");
     642             : 
     643     1458092 :   AtomicInfo.SSID = static_cast<unsigned>(SSID);
     644             :   assert(getSyncScopeID() == SSID && "Value truncated");
     645     1458092 :   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
     646             :   assert(getOrdering() == Ordering && "Value truncated");
     647     1458092 :   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
     648             :   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
     649     1458092 : }
     650             : 
     651             : /// Profile - Gather unique data for the object.
     652             : ///
     653           0 : void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
     654           0 :   ID.AddInteger(getOffset());
     655           0 :   ID.AddInteger(Size);
     656           0 :   ID.AddPointer(getOpaqueValue());
     657           0 :   ID.AddInteger(getFlags());
     658           0 :   ID.AddInteger(getBaseAlignment());
     659           0 : }
     660             : 
     661       24063 : void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
     662             :   // The Value and Offset may differ due to CSE. But the flags and size
     663             :   // should be the same.
     664             :   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
     665             :   assert(MMO->getSize() == getSize() && "Size mismatch!");
     666             : 
     667       72189 :   if (MMO->getBaseAlignment() >= getBaseAlignment()) {
     668             :     // Update the alignment value.
     669       48096 :     BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
     670             :     // Also update the base and offset, because the new alignment may
     671             :     // not be applicable with the old ones.
     672       24048 :     PtrInfo = MMO->PtrInfo;
     673             :   }
     674       24063 : }
     675             : 
     676             : /// getAlignment - Return the minimum known alignment in bytes of the
     677             : /// actual memory reference.
     678    11065204 : uint64_t MachineMemOperand::getAlignment() const {
     679    33195612 :   return MinAlign(getBaseAlignment(), getOffset());
     680             : }
     681             : 
     682           3 : void MachineMemOperand::print(raw_ostream &OS) const {
     683           6 :   ModuleSlotTracker DummyMST(nullptr);
     684           3 :   print(OS, DummyMST);
     685           3 : }
     686        2123 : void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
     687             :   assert((isLoad() || isStore()) &&
     688             :          "SV has to be a load, store or both.");
     689             : 
     690        4246 :   if (isVolatile())
     691          10 :     OS << "Volatile ";
     692             : 
     693        4246 :   if (isLoad())
     694        1572 :     OS << "LD";
     695        4246 :   if (isStore())
     696         551 :     OS << "ST";
     697        2123 :   OS << getSize();
     698             : 
     699             :   // Print the address information.
     700        2123 :   OS << "[";
     701         118 :   if (const Value *V = getValue())
     702         118 :     V->printAsOperand(OS, /*PrintType=*/false, MST);
     703        2005 :   else if (const PseudoSourceValue *PSV = getPseudoValue())
     704        2005 :     PSV->printCustom(OS);
     705             :   else
     706           0 :     OS << "<unknown>";
     707             : 
     708        2123 :   unsigned AS = getAddrSpace();
     709        2123 :   if (AS != 0)
     710           4 :     OS << "(addrspace=" << AS << ')';
     711             : 
     712             :   // If the alignment of the memory reference itself differs from the alignment
     713             :   // of the base pointer, print the base alignment explicitly, next to the base
     714             :   // pointer.
     715        4246 :   if (getBaseAlignment() != getAlignment())
     716           0 :     OS << "(align=" << getBaseAlignment() << ")";
     717             : 
     718        2123 :   if (getOffset() != 0)
     719          10 :     OS << "+" << getOffset();
     720        2123 :   OS << "]";
     721             : 
     722             :   // Print the alignment of the reference.
     723        6369 :   if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
     724          22 :     OS << "(align=" << getAlignment() << ")";
     725             : 
     726             :   // Print TBAA info.
     727        2123 :   if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
     728           0 :     OS << "(tbaa=";
     729           0 :     if (TBAAInfo->getNumOperands() > 0)
     730           0 :       TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
     731             :     else
     732           0 :       OS << "<unknown>";
     733           0 :     OS << ")";
     734             :   }
     735             : 
     736             :   // Print AA scope info.
     737        2123 :   if (const MDNode *ScopeInfo = getAAInfo().Scope) {
     738           0 :     OS << "(alias.scope=";
     739           0 :     if (ScopeInfo->getNumOperands() > 0)
     740           0 :       for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
     741           0 :         ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
     742           0 :         if (i != ie-1)
     743           0 :           OS << ",";
     744             :       }
     745             :     else
     746           0 :       OS << "<unknown>";
     747           0 :     OS << ")";
     748             :   }
     749             : 
     750             :   // Print AA noalias scope info.
     751        2123 :   if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
     752           0 :     OS << "(noalias=";
     753           0 :     if (NoAliasInfo->getNumOperands() > 0)
     754           0 :       for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
     755           0 :         NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
     756           0 :         if (i != ie-1)
     757           0 :           OS << ",";
     758             :       }
     759             :     else
     760           0 :       OS << "<unknown>";
     761           0 :     OS << ")";
     762             :   }
     763             : 
     764        4246 :   if (isNonTemporal())
     765           0 :     OS << "(nontemporal)";
     766        4246 :   if (isDereferenceable())
     767          25 :     OS << "(dereferenceable)";
     768        4246 :   if (isInvariant())
     769           6 :     OS << "(invariant)";
     770        4246 :   if (getFlags() & MOTargetFlag1)
     771           0 :     OS << "(flag1)";
     772        4246 :   if (getFlags() & MOTargetFlag2)
     773           0 :     OS << "(flag2)";
     774        4246 :   if (getFlags() & MOTargetFlag3)
     775           0 :     OS << "(flag3)";
     776        2123 : }
     777             : 
     778             : //===----------------------------------------------------------------------===//
     779             : // MachineInstr Implementation
     780             : //===----------------------------------------------------------------------===//
     781             : 
     782     6404228 : void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
     783     6404228 :   if (MCID->ImplicitDefs)
     784     3998100 :     for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
     785             :            ++ImpDefs)
     786     2944644 :       addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
     787     6404228 :   if (MCID->ImplicitUses)
     788     3918170 :     for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
     789             :            ++ImpUses)
     790     2638468 :       addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
     791     6404228 : }
     792             : 
     793             : /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
     794             : /// implicit operands. It reserves space for the number of operands specified by
     795             : /// the MCInstrDesc.
     796     6315503 : MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
     797     6315503 :                            DebugLoc dl, bool NoImp)
     798    25262012 :     : MCID(&tid), debugLoc(std::move(dl)) {
     799             :   assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
     800             : 
     801             :   // Reserve space for the expected number of operands.
     802    18946509 :   if (unsigned NumOps = MCID->getNumOperands() +
     803    25262012 :     MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
     804    12204524 :     CapOperands = OperandCapacity::get(NumOps);
     805     6102262 :     Operands = MF.allocateOperandArray(CapOperands);
     806             :   }
     807             : 
     808     6315503 :   if (!NoImp)
     809     6287321 :     addImplicitDefUseOperands(MF);
     810     6315503 : }
     811             : 
     812             : /// MachineInstr ctor - Copies MachineInstr arg exactly
     813             : ///
     814      139910 : MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
     815      419730 :     : MCID(&MI.getDesc()), NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
     816      979370 :       debugLoc(MI.getDebugLoc()) {
     817             :   assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
     818             : 
     819      279820 :   CapOperands = OperandCapacity::get(MI.getNumOperands());
     820      139910 :   Operands = MF.allocateOperandArray(CapOperands);
     821             : 
     822             :   // Copy operands.
     823      518231 :   for (const MachineOperand &MO : MI.operands())
     824      378321 :     addOperand(MF, MO);
     825             : 
     826             :   // Copy all the sensible flags.
     827      279820 :   setFlags(MI.Flags);
     828      139910 : }
     829             : 
     830             : /// getRegInfo - If this instruction is embedded into a MachineFunction,
     831             : /// return the MachineRegisterInfo object for the current function, otherwise
     832             : /// return null.
     833    23824875 : MachineRegisterInfo *MachineInstr::getRegInfo() {
     834    23824875 :   if (MachineBasicBlock *MBB = getParent())
     835     8523518 :     return &MBB->getParent()->getRegInfo();
     836             :   return nullptr;
     837             : }
     838             : 
     839             : /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
     840             : /// this instruction from their respective use lists.  This requires that the
     841             : /// operands already be on their use lists.
     842     3317779 : void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
     843    12669449 :   for (MachineOperand &MO : operands())
     844     9351670 :     if (MO.isReg())
     845     6725326 :       MRI.removeRegOperandFromUseList(&MO);
     846     3317779 : }
     847             : 
     848             : /// AddRegOperandsToUseLists - Add all of the register operands in
     849             : /// this instruction from their respective use lists.  This requires that the
     850             : /// operands not be on their use lists yet.
     851     6456525 : void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
     852    21777660 :   for (MachineOperand &MO : operands())
     853    15321135 :     if (MO.isReg())
     854     9512161 :       MRI.addRegOperandToUseList(&MO);
     855     6456525 : }
     856             : 
     857      791403 : void MachineInstr::addOperand(const MachineOperand &Op) {
     858      791403 :   MachineBasicBlock *MBB = getParent();
     859             :   assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
     860      791403 :   MachineFunction *MF = MBB->getParent();
     861             :   assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
     862      791403 :   addOperand(*MF, Op);
     863      791404 : }
     864             : 
     865             : /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
     866             : /// ranges. If MRI is non-null also update use-def chains.
     867     6017911 : static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
     868             :                          unsigned NumOps, MachineRegisterInfo *MRI) {
     869     6017911 :   if (MRI)
     870     1919359 :     return MRI->moveOperands(Dst, Src, NumOps);
     871             : 
     872             :   // MachineOperand is a trivially copyable type so we can just use memmove.
     873     4098552 :   std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
     874             : }
     875             : 
     876             : /// addOperand - Add the specified operand to the instruction.  If it is an
     877             : /// implicit operand, it is added to the end of the operand list.  If it is
     878             : /// an explicit operand it is added at the end of the explicit operand list
     879             : /// (before the first implicit operand).
     880    23272364 : void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
     881             :   assert(MCID && "Cannot add operands before providing an instr descriptor");
     882             : 
     883             :   // Check if we're adding one of our existing operands.
     884    23272364 :   if (&Op >= Operands && &Op < Operands + NumOperands) {
     885             :     // This is unusual: MI->addOperand(MI->getOperand(i)).
     886             :     // If adding Op requires reallocating or moving existing operands around,
     887             :     // the Op reference could go stale. Support it by copying Op.
     888         300 :     MachineOperand CopyOp(Op);
     889         300 :     return addOperand(MF, CopyOp);
     890             :   }
     891             : 
     892             :   // Find the insert location for the new operand.  Implicit registers go at
     893             :   // the end, everything else goes before the implicit regs.
     894             :   //
     895             :   // FIXME: Allow mixed explicit and implicit operands on inline asm.
     896             :   // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
     897             :   // implicit-defs, but they must not be moved around.  See the FIXME in
     898             :   // InstrEmitter.cpp.
     899    23272064 :   unsigned OpNo = getNumOperands();
     900    39039795 :   bool isImpReg = Op.isReg() && Op.isImplicit();
     901    18964818 :   if (!isImpReg && !isInlineAsm()) {
     902    61943942 :     while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
     903             :       --OpNo;
     904             :       assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
     905             :     }
     906             :   }
     907             : 
     908             : #ifndef NDEBUG
     909             :   bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
     910             :   // OpNo now points as the desired insertion point.  Unless this is a variadic
     911             :   // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
     912             :   // RegMask operands go between the explicit and implicit operands.
     913             :   assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
     914             :           OpNo < MCID->getNumOperands() || isMetaDataOp) &&
     915             :          "Trying to add an operand to a machine instr that is already done!");
     916             : #endif
     917             : 
     918    23272064 :   MachineRegisterInfo *MRI = getRegInfo();
     919             : 
     920             :   // Determine if the Operands array needs to be reallocated.
     921             :   // Save the old capacity and operand array.
     922    23272064 :   OperandCapacity OldCap = CapOperands;
     923    23272064 :   MachineOperand *OldOperands = Operands;
     924    46381132 :   if (!OldOperands || OldCap.getSize() == getNumOperands()) {
     925     3053156 :     CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
     926     1526578 :     Operands = MF.allocateOperandArray(CapOperands);
     927             :     // Move the operands before the insertion point.
     928     1526578 :     if (OpNo)
     929     1362409 :       moveOperands(Operands, OldOperands, OpNo, MRI);
     930             :   }
     931             : 
     932             :   // Move the operands following the insertion point.
     933    23272064 :   if (OpNo != NumOperands)
     934     4562366 :     moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
     935             :                  MRI);
     936    23272064 :   ++NumOperands;
     937             : 
     938             :   // Deallocate the old operand array.
     939    23272064 :   if (OldOperands != Operands && OldOperands)
     940             :     MF.deallocateOperandArray(OldCap, OldOperands);
     941             : 
     942             :   // Copy Op into place. It still needs to be inserted into the MRI use lists.
     943    23272064 :   MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
     944    23272064 :   NewMO->ParentMI = this;
     945             : 
     946             :   // When adding a register operand, tell MRI about it.
     947    23272064 :   if (NewMO->isReg()) {
     948             :     // Ensure isOnRegUseList() returns false, regardless of Op's status.
     949    15767731 :     NewMO->Contents.Reg.Prev = nullptr;
     950             :     // Ignore existing ties. This is not a property that can be copied.
     951    15767731 :     NewMO->TiedTo = 0;
     952             :     // Add the new operand to MRI, but only for instructions in an MBB.
     953    15767731 :     if (MRI)
     954     6267583 :       MRI->addRegOperandToUseList(NewMO);
     955             :     // The MCID operand information isn't accurate until we start adding
     956             :     // explicit operands. The implicit operands are added first, then the
     957             :     // explicits are inserted before them.
     958    15767731 :     if (!isImpReg) {
     959             :       // Tie uses to defs as indicated in MCInstrDesc.
     960    11460485 :       if (NewMO->isUse()) {
     961     8077653 :         int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
     962             :         if (DefIdx != -1)
     963      427047 :           tieOperands(DefIdx, OpNo);
     964             :       }
     965             :       // If the register operand is flagged as early, mark the operand as such.
     966    11465522 :       if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
     967             :         NewMO->setIsEarlyClobber(true);
     968             :     }
     969             :   }
     970             : }
     971             : 
     972             : /// RemoveOperand - Erase an operand  from an instruction, leaving it with one
     973             : /// fewer operand than it started with.
     974             : ///
     975      552811 : void MachineInstr::RemoveOperand(unsigned OpNo) {
     976             :   assert(OpNo < getNumOperands() && "Invalid operand number");
     977      552811 :   untieRegOperand(OpNo);
     978             : 
     979             : #ifndef NDEBUG
     980             :   // Moving tied operands would break the ties.
     981             :   for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
     982             :     if (Operands[i].isReg())
     983             :       assert(!Operands[i].isTied() && "Cannot move tied operands");
     984             : #endif
     985             : 
     986      552811 :   MachineRegisterInfo *MRI = getRegInfo();
     987     1105622 :   if (MRI && Operands[OpNo].isReg())
     988      508133 :     MRI->removeRegOperandFromUseList(Operands + OpNo);
     989             : 
     990             :   // Don't call the MachineOperand destructor. A lot of this code depends on
     991             :   // MachineOperand having a trivial destructor anyway, and adding a call here
     992             :   // wouldn't make it 'destructor-correct'.
     993             : 
     994      552811 :   if (unsigned N = NumOperands - 1 - OpNo)
     995       93136 :     moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
     996      552811 :   --NumOperands;
     997      552811 : }
     998             : 
     999             : /// addMemOperand - Add a MachineMemOperand to the machine instruction.
    1000             : /// This function should be used only occasionally. The setMemRefs function
    1001             : /// is the primary method for setting up a MachineInstr's MemRefs list.
    1002       98797 : void MachineInstr::addMemOperand(MachineFunction &MF,
    1003             :                                  MachineMemOperand *MO) {
    1004       98797 :   mmo_iterator OldMemRefs = MemRefs;
    1005       98797 :   unsigned OldNumMemRefs = NumMemRefs;
    1006             : 
    1007       98797 :   unsigned NewNum = NumMemRefs + 1;
    1008       98797 :   mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
    1009             : 
    1010      197594 :   std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
    1011       98797 :   NewMemRefs[NewNum - 1] = MO;
    1012      197594 :   setMemRefs(NewMemRefs, NewMemRefs + NewNum);
    1013       98797 : }
    1014             : 
    1015             : /// Check to see if the MMOs pointed to by the two MemRefs arrays are
    1016             : /// identical.
    1017       16833 : static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) {
    1018       33666 :   auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end();
    1019       33666 :   auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end();
    1020       16833 :   if ((E1 - I1) != (E2 - I2))
    1021             :     return false;
    1022       46844 :   for (; I1 != E1; ++I1, ++I2) {
    1023       39216 :     if (**I1 != **I2)
    1024             :       return false;
    1025             :   }
    1026             :   return true;
    1027             : }
    1028             : 
    1029             : std::pair<MachineInstr::mmo_iterator, unsigned>
    1030       17484 : MachineInstr::mergeMemRefsWith(const MachineInstr& Other) {
    1031             : 
    1032             :   // If either of the incoming memrefs are empty, we must be conservative and
    1033             :   // treat this as if we've exhausted our space for memrefs and dropped them.
    1034       17484 :   if (memoperands_empty() || Other.memoperands_empty())
    1035        1302 :     return std::make_pair(nullptr, 0);
    1036             : 
    1037             :   // If both instructions have identical memrefs, we don't need to merge them.
    1038             :   // Since many instructions have a single memref, and we tend to merge things
    1039             :   // like pairs of loads from the same location, this catches a large number of
    1040             :   // cases in practice.
    1041       16833 :   if (hasIdenticalMMOs(*this, Other))
    1042       34380 :     return std::make_pair(MemRefs, NumMemRefs);
    1043             : 
    1044             :   // TODO: consider uniquing elements within the operand lists to reduce
    1045             :   // space usage and fall back to conservative information less often.
    1046        5373 :   size_t CombinedNumMemRefs = NumMemRefs + Other.NumMemRefs;
    1047             : 
    1048             :   // If we don't have enough room to store this many memrefs, be conservative
    1049             :   // and drop them.  Otherwise, we'd fail asserts when trying to add them to
    1050             :   // the new instruction.
    1051        5373 :   if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs))
    1052           0 :     return std::make_pair(nullptr, 0);
    1053             : 
    1054        5373 :   MachineFunction *MF = getParent()->getParent();
    1055        5373 :   mmo_iterator MemBegin = MF->allocateMemRefsArray(CombinedNumMemRefs);
    1056       10746 :   mmo_iterator MemEnd = std::copy(memoperands_begin(), memoperands_end(),
    1057        5373 :                                   MemBegin);
    1058       16119 :   MemEnd = std::copy(Other.memoperands_begin(), Other.memoperands_end(),
    1059             :                      MemEnd);
    1060             :   assert(MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs &&
    1061             :          "missing memrefs");
    1062             : 
    1063       16119 :   return std::make_pair(MemBegin, CombinedNumMemRefs);
    1064             : }
    1065             : 
    1066      204122 : bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
    1067             :   assert(!isBundledWithPred() && "Must be called on bundle header");
    1068      408244 :   for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
    1069      367895 :     if (MII->getDesc().getFlags() & Mask) {
    1070       66832 :       if (Type == AnyInBundle)
    1071             :         return true;
    1072             :     } else {
    1073      311049 :       if (Type == AllInBundle && !MII->isBundle())
    1074             :         return false;
    1075             :     }
    1076             :     // This was the last instruction in the bundle.
    1077      592272 :     if (!MII->isBundledWithSucc())
    1078      132363 :       return Type == AllInBundle;
    1079             :   }
    1080             : }
    1081             : 
    1082     6381974 : bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
    1083             :                                  MICheckType Check) const {
    1084             :   // If opcodes or number of operands are not the same then the two
    1085             :   // instructions are obviously not identical.
    1086    23900441 :   if (Other.getOpcode() != getOpcode() ||
    1087     4754519 :       Other.getNumOperands() != getNumOperands())
    1088             :     return false;
    1089             : 
    1090     4745132 :   if (isBundle()) {
    1091             :     // We have passed the test above that both instructions have the same
    1092             :     // opcode, so we know that both instructions are bundles here. Let's compare
    1093             :     // MIs inside the bundle.
    1094             :     assert(Other.isBundle() && "Expected that both instructions are bundles.");
    1095           0 :     MachineBasicBlock::const_instr_iterator I1 = getIterator();
    1096           0 :     MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
    1097             :     // Loop until we analysed the last intruction inside at least one of the
    1098             :     // bundles.
    1099           0 :     while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
    1100           0 :       ++I1;
    1101           0 :       ++I2;
    1102           0 :       if (!I1->isIdenticalTo(*I2, Check))
    1103             :         return false;
    1104             :     }
    1105             :     // If we've reached the end of just one of the two bundles, but not both,
    1106             :     // the instructions are not identical.
    1107           0 :     if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
    1108             :       return false;
    1109             :   }
    1110             : 
    1111             :   // Check operands to make sure they match.
    1112    23172432 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    1113    39355498 :     const MachineOperand &MO = getOperand(i);
    1114    39355498 :     const MachineOperand &OMO = Other.getOperand(i);
    1115    26279503 :     if (!MO.isReg()) {
    1116     7514482 :       if (!MO.isIdenticalTo(OMO))
    1117             :         return false;
    1118     6601754 :       continue;
    1119             :     }
    1120             : 
    1121             :     // Clients may or may not want to ignore defs when testing for equality.
    1122             :     // For example, machine CSE pass only cares about finding common
    1123             :     // subexpressions, so it's safe to ignore virtual register defs.
    1124    12163267 :     if (MO.isDef()) {
    1125     5437353 :       if (Check == IgnoreDefs)
    1126           0 :         continue;
    1127     5437353 :       else if (Check == IgnoreVRegDefs) {
    1128    11646745 :         if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
    1129     4837146 :             TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
    1130     2195704 :           if (MO.getReg() != OMO.getReg())
    1131             :             return false;
    1132             :       } else {
    1133      823267 :         if (!MO.isIdenticalTo(OMO))
    1134             :           return false;
    1135      824775 :         if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
    1136             :           return false;
    1137             :       }
    1138             :     } else {
    1139     6725914 :       if (!MO.isIdenticalTo(OMO))
    1140             :         return false;
    1141     6425386 :       if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
    1142             :         return false;
    1143             :     }
    1144             :   }
    1145             :   // If DebugLoc does not match then two dbg.values are not identical.
    1146     3494683 :   if (isDebugValue())
    1147        3192 :     if (getDebugLoc() && Other.getDebugLoc() &&
    1148        1596 :         getDebugLoc() != Other.getDebugLoc())
    1149             :       return false;
    1150             :   return true;
    1151             : }
    1152             : 
    1153         985 : MachineInstr *MachineInstr::removeFromParent() {
    1154             :   assert(getParent() && "Not embedded in a basic block!");
    1155        1970 :   return getParent()->remove(this);
    1156             : }
    1157             : 
    1158           7 : MachineInstr *MachineInstr::removeFromBundle() {
    1159             :   assert(getParent() && "Not embedded in a basic block!");
    1160           7 :   return getParent()->remove_instr(this);
    1161             : }
    1162             : 
    1163     2046159 : void MachineInstr::eraseFromParent() {
    1164             :   assert(getParent() && "Not embedded in a basic block!");
    1165     4092318 :   getParent()->erase(this);
    1166     2046159 : }
    1167             : 
    1168      157130 : void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
    1169             :   assert(getParent() && "Not embedded in a basic block!");
    1170      157130 :   MachineBasicBlock *MBB = getParent();
    1171      157130 :   MachineFunction *MF = MBB->getParent();
    1172             :   assert(MF && "Not embedded in a function!");
    1173             : 
    1174      157130 :   MachineInstr *MI = (MachineInstr *)this;
    1175      157130 :   MachineRegisterInfo &MRI = MF->getRegInfo();
    1176             : 
    1177      524191 :   for (const MachineOperand &MO : MI->operands()) {
    1178      679788 :     if (!MO.isReg() || !MO.isDef())
    1179      209317 :       continue;
    1180      157744 :     unsigned Reg = MO.getReg();
    1181      157744 :     if (!TargetRegisterInfo::isVirtualRegister(Reg))
    1182         702 :       continue;
    1183      157042 :     MRI.markUsesInDebugValueAsUndef(Reg);
    1184             :   }
    1185      157130 :   MI->eraseFromParent();
    1186      157130 : }
    1187             : 
    1188      544316 : void MachineInstr::eraseFromBundle() {
    1189             :   assert(getParent() && "Not embedded in a basic block!");
    1190     1088632 :   getParent()->erase_instr(this);
    1191      544316 : }
    1192             : 
    1193             : /// getNumExplicitOperands - Returns the number of non-implicit operands.
    1194             : ///
    1195    13151772 : unsigned MachineInstr::getNumExplicitOperands() const {
    1196    26303544 :   unsigned NumOperands = MCID->getNumOperands();
    1197    26303544 :   if (!MCID->isVariadic())
    1198             :     return NumOperands;
    1199             : 
    1200        3959 :   for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
    1201        6186 :     const MachineOperand &MO = getOperand(i);
    1202        4456 :     if (!MO.isReg() || !MO.isImplicit())
    1203        3089 :       NumOperands++;
    1204             :   }
    1205             :   return NumOperands;
    1206             : }
    1207             : 
    1208       45225 : void MachineInstr::bundleWithPred() {
    1209             :   assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
    1210       90450 :   setFlag(BundledPred);
    1211       90450 :   MachineBasicBlock::instr_iterator Pred = getIterator();
    1212       45225 :   --Pred;
    1213             :   assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
    1214       90450 :   Pred->setFlag(BundledSucc);
    1215       45225 : }
    1216             : 
    1217       18293 : void MachineInstr::bundleWithSucc() {
    1218             :   assert(!isBundledWithSucc() && "MI is already bundled with its successor");
    1219       36586 :   setFlag(BundledSucc);
    1220       36586 :   MachineBasicBlock::instr_iterator Succ = getIterator();
    1221       18293 :   ++Succ;
    1222             :   assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
    1223       36586 :   Succ->setFlag(BundledPred);
    1224       18293 : }
    1225             : 
    1226       38318 : void MachineInstr::unbundleFromPred() {
    1227             :   assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
    1228       76636 :   clearFlag(BundledPred);
    1229       76636 :   MachineBasicBlock::instr_iterator Pred = getIterator();
    1230       38318 :   --Pred;
    1231             :   assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
    1232       76636 :   Pred->clearFlag(BundledSucc);
    1233       38318 : }
    1234             : 
    1235           6 : void MachineInstr::unbundleFromSucc() {
    1236             :   assert(isBundledWithSucc() && "MI isn't bundled with its successor");
    1237          12 :   clearFlag(BundledSucc);
    1238          12 :   MachineBasicBlock::instr_iterator Succ = getIterator();
    1239           6 :   ++Succ;
    1240             :   assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
    1241          12 :   Succ->clearFlag(BundledPred);
    1242           6 : }
    1243             : 
    1244     3901621 : bool MachineInstr::isStackAligningInlineAsm() const {
    1245     3901621 :   if (isInlineAsm()) {
    1246        8741 :     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    1247        8741 :     if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
    1248             :       return true;
    1249             :   }
    1250             :   return false;
    1251             : }
    1252             : 
    1253        8894 : InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
    1254             :   assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
    1255        8894 :   unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    1256        8894 :   return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
    1257             : }
    1258             : 
    1259          34 : int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
    1260             :                                        unsigned *GroupNo) const {
    1261             :   assert(isInlineAsm() && "Expected an inline asm instruction");
    1262             :   assert(OpIdx < getNumOperands() && "OpIdx out of range");
    1263             : 
    1264             :   // Ignore queries about the initial operands.
    1265          34 :   if (OpIdx < InlineAsm::MIOp_FirstOperand)
    1266             :     return -1;
    1267             : 
    1268          34 :   unsigned Group = 0;
    1269             :   unsigned NumOps;
    1270          64 :   for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
    1271          30 :        i += NumOps) {
    1272         128 :     const MachineOperand &FlagMO = getOperand(i);
    1273             :     // If we reach the implicit register operands, stop looking.
    1274          64 :     if (!FlagMO.isImm())
    1275             :       return -1;
    1276         128 :     NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
    1277          64 :     if (i + NumOps > OpIdx) {
    1278          34 :       if (GroupNo)
    1279           0 :         *GroupNo = Group;
    1280          34 :       return i;
    1281             :     }
    1282          30 :     ++Group;
    1283             :   }
    1284             :   return -1;
    1285             : }
    1286             : 
    1287      185694 : const DILocalVariable *MachineInstr::getDebugVariable() const {
    1288             :   assert(isDebugValue() && "not a DBG_VALUE");
    1289      371388 :   return cast<DILocalVariable>(getOperand(2).getMetadata());
    1290             : }
    1291             : 
    1292      127415 : const DIExpression *MachineInstr::getDebugExpression() const {
    1293             :   assert(isDebugValue() && "not a DBG_VALUE");
    1294      254830 :   return cast<DIExpression>(getOperand(3).getMetadata());
    1295             : }
    1296             : 
    1297             : const TargetRegisterClass*
    1298       52470 : MachineInstr::getRegClassConstraint(unsigned OpIdx,
    1299             :                                     const TargetInstrInfo *TII,
    1300             :                                     const TargetRegisterInfo *TRI) const {
    1301             :   assert(getParent() && "Can't have an MBB reference here!");
    1302             :   assert(getParent()->getParent() && "Can't have an MF reference here!");
    1303       52470 :   const MachineFunction &MF = *getParent()->getParent();
    1304             : 
    1305             :   // Most opcodes have fixed constraints in their MCInstrDesc.
    1306       52470 :   if (!isInlineAsm())
    1307       52436 :     return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
    1308             : 
    1309         102 :   if (!getOperand(OpIdx).isReg())
    1310             :     return nullptr;
    1311             : 
    1312             :   // For tied uses on inline asm, get the constraint from the def.
    1313             :   unsigned DefIdx;
    1314          68 :   if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
    1315           1 :     OpIdx = DefIdx;
    1316             : 
    1317             :   // Inline asm stores register class constraints in the flag word.
    1318          34 :   int FlagIdx = findInlineAsmFlagIdx(OpIdx);
    1319          34 :   if (FlagIdx < 0)
    1320             :     return nullptr;
    1321             : 
    1322          68 :   unsigned Flag = getOperand(FlagIdx).getImm();
    1323             :   unsigned RCID;
    1324          43 :   if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
    1325          11 :        InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
    1326          36 :        InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
    1327          34 :       InlineAsm::hasRegClassConstraint(Flag, RCID))
    1328          68 :     return TRI->getRegClass(RCID);
    1329             : 
    1330             :   // Assume that all registers in a memory operand are pointers.
    1331           0 :   if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
    1332           0 :     return TRI->getPointerRegClass(MF);
    1333             : 
    1334             :   return nullptr;
    1335             : }
    1336             : 
    1337          41 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
    1338             :     unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
    1339             :     const TargetRegisterInfo *TRI, bool ExploreBundle) const {
    1340             :   // Check every operands inside the bundle if we have
    1341             :   // been asked to.
    1342          41 :   if (ExploreBundle)
    1343         209 :     for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
    1344             :          ++OpndIt)
    1345         336 :       CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
    1346             :           OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
    1347             :   else
    1348             :     // Otherwise, just check the current operands.
    1349           0 :     for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
    1350           0 :       CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
    1351          41 :   return CurRC;
    1352             : }
    1353             : 
    1354         168 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
    1355             :     unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
    1356             :     const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
    1357             :   assert(CurRC && "Invalid initial register class");
    1358             :   // Check if Reg is constrained by some of its use/def from MI.
    1359         336 :   const MachineOperand &MO = getOperand(OpIdx);
    1360         168 :   if (!MO.isReg() || MO.getReg() != Reg)
    1361             :     return CurRC;
    1362             :   // If yes, accumulate the constraints through the operand.
    1363          43 :   return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
    1364             : }
    1365             : 
    1366       48560 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
    1367             :     unsigned OpIdx, const TargetRegisterClass *CurRC,
    1368             :     const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
    1369       48560 :   const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
    1370       97120 :   const MachineOperand &MO = getOperand(OpIdx);
    1371             :   assert(MO.isReg() &&
    1372             :          "Cannot get register constraints for non-register operand");
    1373             :   assert(CurRC && "Invalid initial register class");
    1374       48560 :   if (unsigned SubIdx = MO.getSubReg()) {
    1375       18504 :     if (OpRC)
    1376       16910 :       CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
    1377             :     else
    1378        1594 :       CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
    1379       30056 :   } else if (OpRC)
    1380       19356 :     CurRC = TRI->getCommonSubClass(CurRC, OpRC);
    1381       48560 :   return CurRC;
    1382             : }
    1383             : 
    1384             : /// Return the number of instructions inside the MI bundle, not counting the
    1385             : /// header instruction.
    1386        1101 : unsigned MachineInstr::getBundleSize() const {
    1387        2202 :   MachineBasicBlock::const_instr_iterator I = getIterator();
    1388        1101 :   unsigned Size = 0;
    1389        7742 :   while (I->isBundledWithSucc()) {
    1390        2770 :     ++Size;
    1391             :     ++I;
    1392             :   }
    1393        1101 :   return Size;
    1394             : }
    1395             : 
    1396             : /// Returns true if the MachineInstr has an implicit-use operand of exactly
    1397             : /// the given register (not considering sub/super-registers).
    1398     4959248 : bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const {
    1399    27955484 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    1400    55910968 :     const MachineOperand &MO = getOperand(i);
    1401    58650339 :     if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
    1402             :       return true;
    1403             :   }
    1404             :   return false;
    1405             : }
    1406             : 
    1407             : /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
    1408             : /// the specific register or -1 if it is not found. It further tightens
    1409             : /// the search criteria to a use that kills the register if isKill is true.
    1410     3147974 : int MachineInstr::findRegisterUseOperandIdx(
    1411             :     unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
    1412    17410326 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    1413    29984100 :     const MachineOperand &MO = getOperand(i);
    1414    25010754 :     if (!MO.isReg() || !MO.isUse())
    1415     9401324 :       continue;
    1416     5590726 :     unsigned MOReg = MO.getReg();
    1417     5590726 :     if (!MOReg)
    1418      459914 :       continue;
    1419     6267882 :     if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
    1420      766964 :                          TargetRegisterInfo::isPhysicalRegister(Reg) &&
    1421      743328 :                          TRI->isSubRegister(MOReg, Reg)))
    1422     1052512 :       if (!isKill || MO.isKill())
    1423      729698 :         return i;
    1424             :   }
    1425             :   return -1;
    1426             : }
    1427             : 
    1428             : /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
    1429             : /// indicating if this instruction reads or writes Reg. This also considers
    1430             : /// partial defines.
    1431             : std::pair<bool,bool>
    1432    18107185 : MachineInstr::readsWritesVirtualRegister(unsigned Reg,
    1433             :                                          SmallVectorImpl<unsigned> *Ops) const {
    1434    18107185 :   bool PartDef = false; // Partial redefine.
    1435    18107185 :   bool FullDef = false; // Full define.
    1436    18107185 :   bool Use = false;
    1437             : 
    1438    65592801 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    1439    94971232 :     const MachineOperand &MO = getOperand(i);
    1440    47485616 :     if (!MO.isReg() || MO.getReg() != Reg)
    1441    29074034 :       continue;
    1442    18411582 :     if (Ops)
    1443      892098 :       Ops->push_back(i);
    1444    18411582 :     if (MO.isUse())
    1445    16150260 :       Use |= !MO.isUndef();
    1446     2494779 :     else if (MO.getSubReg() && !MO.isUndef())
    1447             :       // A partial <def,undef> doesn't count as reading the register.
    1448             :       PartDef = true;
    1449             :     else
    1450             :       FullDef = true;
    1451             :   }
    1452             :   // A partial redefine uses Reg unless there is also a full define.
    1453    36214370 :   return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
    1454             : }
    1455             : 
    1456             : /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
    1457             : /// the specified register or -1 if it is not found. If isDead is true, defs
    1458             : /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
    1459             : /// also checks if there is a def of a super-register.
    1460             : int
    1461     8924030 : MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
    1462             :                                         const TargetRegisterInfo *TRI) const {
    1463     8924030 :   bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
    1464    43022969 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    1465    73238522 :     const MachineOperand &MO = getOperand(i);
    1466             :     // Accept regmask operands when Overlap is set.
    1467             :     // Ignore them when looking for a specific def operand (Overlap == false).
    1468    52848457 :     if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
    1469         689 :       return i;
    1470    88457367 :     if (!MO.isReg() || !MO.isDef())
    1471    26651595 :       continue;
    1472     9966977 :     unsigned MOReg = MO.getReg();
    1473     9966977 :     bool Found = (MOReg == Reg);
    1474    16946791 :     if (!Found && TRI && isPhys &&
    1475     3249473 :         TargetRegisterInfo::isPhysicalRegister(MOReg)) {
    1476     2049224 :       if (Overlap)
    1477     1912993 :         Found = TRI->regsOverlap(MOReg, Reg);
    1478             :       else
    1479      272462 :         Found = TRI->isSubRegister(MOReg, Reg);
    1480             :     }
    1481    11308629 :     if (Found && (!isDead || MO.isDead()))
    1482     2519633 :       return i;
    1483             :   }
    1484             :   return -1;
    1485             : }
    1486             : 
    1487             : /// findFirstPredOperandIdx() - Find the index of the first operand in the
    1488             : /// operand list that is used to represent the predicate. It returns -1 if
    1489             : /// none is found.
    1490     1014788 : int MachineInstr::findFirstPredOperandIdx() const {
    1491             :   // Don't call MCID.findFirstPredOperandIdx() because this variant
    1492             :   // is sometimes called on an instruction that's not yet complete, and
    1493             :   // so the number of operands is less than the MCID indicates. In
    1494             :   // particular, the PTX target does this.
    1495     1014788 :   const MCInstrDesc &MCID = getDesc();
    1496     1014788 :   if (MCID.isPredicable()) {
    1497     3405236 :     for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
    1498     3374846 :       if (MCID.OpInfo[i].isPredicate())
    1499      895919 :         return i;
    1500             :   }
    1501             : 
    1502             :   return -1;
    1503             : }
    1504             : 
    1505             : // MachineOperand::TiedTo is 4 bits wide.
    1506             : const unsigned TiedMax = 15;
    1507             : 
    1508             : /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
    1509             : ///
    1510             : /// Use and def operands can be tied together, indicated by a non-zero TiedTo
    1511             : /// field. TiedTo can have these values:
    1512             : ///
    1513             : /// 0:              Operand is not tied to anything.
    1514             : /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
    1515             : /// TiedMax:        Tied to an operand >= TiedMax-1.
    1516             : ///
    1517             : /// The tied def must be one of the first TiedMax operands on a normal
    1518             : /// instruction. INLINEASM instructions allow more tied defs.
    1519             : ///
    1520      427919 : void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
    1521      855838 :   MachineOperand &DefMO = getOperand(DefIdx);
    1522      855838 :   MachineOperand &UseMO = getOperand(UseIdx);
    1523             :   assert(DefMO.isDef() && "DefIdx must be a def operand");
    1524             :   assert(UseMO.isUse() && "UseIdx must be a use operand");
    1525             :   assert(!DefMO.isTied() && "Def is already tied to another use");
    1526             :   assert(!UseMO.isTied() && "Use is already tied to another def");
    1527             : 
    1528      427919 :   if (DefIdx < TiedMax)
    1529      427896 :     UseMO.TiedTo = DefIdx + 1;
    1530             :   else {
    1531             :     // Inline asm can use the group descriptors to find tied operands, but on
    1532             :     // normal instruction, the tied def must be within the first TiedMax
    1533             :     // operands.
    1534             :     assert(isInlineAsm() && "DefIdx out of range");
    1535          23 :     UseMO.TiedTo = TiedMax;
    1536             :   }
    1537             : 
    1538             :   // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
    1539      855838 :   DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
    1540      427919 : }
    1541             : 
    1542             : /// Given the index of a tied register operand, find the operand it is tied to.
    1543             : /// Defs are tied to uses and vice versa. Returns the index of the tied operand
    1544             : /// which must exist.
    1545     3459759 : unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
    1546     6919518 :   const MachineOperand &MO = getOperand(OpIdx);
    1547             :   assert(MO.isTied() && "Operand isn't tied");
    1548             : 
    1549             :   // Normally TiedTo is in range.
    1550     3459759 :   if (MO.TiedTo < TiedMax)
    1551     3457232 :     return MO.TiedTo - 1;
    1552             : 
    1553             :   // Uses on normal instructions can be out of range.
    1554        2527 :   if (!isInlineAsm()) {
    1555             :     // Normal tied defs must be in the 0..TiedMax-1 range.
    1556           0 :     if (MO.isUse())
    1557             :       return TiedMax - 1;
    1558             :     // MO is a def. Search for the tied use.
    1559           0 :     for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
    1560           0 :       const MachineOperand &UseMO = getOperand(i);
    1561           0 :       if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
    1562             :         return i;
    1563             :     }
    1564           0 :     llvm_unreachable("Can't find tied use");
    1565             :   }
    1566             : 
    1567             :   // Now deal with inline asm by parsing the operand group descriptor flags.
    1568             :   // Find the beginning of each operand group.
    1569        2527 :   SmallVector<unsigned, 8> GroupIdx;
    1570        2527 :   unsigned OpIdxGroup = ~0u;
    1571             :   unsigned NumOps;
    1572       77825 :   for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
    1573       75298 :        i += NumOps) {
    1574      155650 :     const MachineOperand &FlagMO = getOperand(i);
    1575             :     assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
    1576       77825 :     unsigned CurGroup = GroupIdx.size();
    1577       77825 :     GroupIdx.push_back(i);
    1578      155650 :     NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
    1579             :     // OpIdx belongs to this operand group.
    1580       77825 :     if (OpIdx > i && OpIdx < i + NumOps)
    1581        2527 :       OpIdxGroup = CurGroup;
    1582             :     unsigned TiedGroup;
    1583      155650 :     if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
    1584       48619 :       continue;
    1585             :     // Operands in this group are tied to operands in TiedGroup which must be
    1586             :     // earlier. Find the number of operands between the two groups.
    1587       58412 :     unsigned Delta = i - GroupIdx[TiedGroup];
    1588             : 
    1589             :     // OpIdx is a use tied to TiedGroup.
    1590       29206 :     if (OpIdxGroup == CurGroup)
    1591        3710 :       return OpIdx - Delta;
    1592             : 
    1593             :     // OpIdx is a def tied to this use group.
    1594       28023 :     if (OpIdxGroup == TiedGroup)
    1595        1344 :       return OpIdx + Delta;
    1596             :   }
    1597           0 :   llvm_unreachable("Invalid tied operand on inline asm");
    1598             : }
    1599             : 
    1600             : /// clearKillInfo - Clears kill flags on all operands.
    1601             : ///
    1602       14928 : void MachineInstr::clearKillInfo() {
    1603       60691 :   for (MachineOperand &MO : operands()) {
    1604       76289 :     if (MO.isReg() && MO.isUse())
    1605             :       MO.setIsKill(false);
    1606             :   }
    1607       14928 : }
    1608             : 
    1609      141862 : void MachineInstr::substituteRegister(unsigned FromReg,
    1610             :                                       unsigned ToReg,
    1611             :                                       unsigned SubIdx,
    1612             :                                       const TargetRegisterInfo &RegInfo) {
    1613      141862 :   if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
    1614       79803 :     if (SubIdx)
    1615           0 :       ToReg = RegInfo.getSubReg(ToReg, SubIdx);
    1616      246716 :     for (MachineOperand &MO : operands()) {
    1617      166913 :       if (!MO.isReg() || MO.getReg() != FromReg)
    1618       87110 :         continue;
    1619       79803 :       MO.substPhysReg(ToReg, RegInfo);
    1620             :     }
    1621             :   } else {
    1622      297009 :     for (MachineOperand &MO : operands()) {
    1623      407841 :       if (!MO.isReg() || MO.getReg() != FromReg)
    1624      172891 :         continue;
    1625       62059 :       MO.substVirtReg(ToReg, SubIdx, RegInfo);
    1626             :     }
    1627             :   }
    1628      141862 : }
    1629             : 
    1630             : /// isSafeToMove - Return true if it is safe to move this instruction. If
    1631             : /// SawStore is set to true, it means that there is a store (or call) between
    1632             : /// the instruction's location and its intended destination.
    1633    15049549 : bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
    1634             :   // Ignore stuff that we obviously can't move.
    1635             :   //
    1636             :   // Treat volatile loads as stores. This is not strictly necessary for
    1637             :   // volatiles, but it is required for atomic loads. It is not allowed to move
    1638             :   // a load across an atomic load with Ordering > Monotonic.
    1639    39683539 :   if (mayStore() || isCall() ||
    1640    13146287 :       (mayLoad() && hasOrderedMemoryRef())) {
    1641     3142816 :     SawStore = true;
    1642     3142816 :     return false;
    1643             :   }
    1644             : 
    1645    44994357 :   if (isPosition() || isDebugValue() || isTerminator() ||
    1646    10434395 :       hasUnmodeledSideEffects())
    1647             :     return false;
    1648             : 
    1649             :   // See if this instruction does a load.  If so, we have to guarantee that the
    1650             :   // loaded value doesn't change between the load and the its intended
    1651             :   // destination. The check for isInvariantLoad gives the targe the chance to
    1652             :   // classify the load as always returning a constant, e.g. a constant pool
    1653             :   // load.
    1654    10234564 :   if (mayLoad() && !isDereferenceableInvariantLoad(AA))
    1655             :     // Otherwise, this is a real load.  If there is a store between the load and
    1656             :     // end of block, we can't move it.
    1657      836429 :     return !SawStore;
    1658             : 
    1659             :   return true;
    1660             : }
    1661             : 
    1662     4054445 : bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
    1663             :                             bool UseTBAA) {
    1664     4054445 :   const MachineFunction *MF = getParent()->getParent();
    1665     4054445 :   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
    1666     4054445 :   const MachineFrameInfo &MFI = MF->getFrameInfo();
    1667             : 
    1668             :   // If neither instruction stores to memory, they can't alias in any
    1669             :   // meaningful way, even if they read from the same address.
    1670     4054445 :   if (!mayStore() && !Other.mayStore())
    1671             :     return false;
    1672             : 
    1673             :   // Let the target decide if memory accesses cannot possibly overlap.
    1674     4054445 :   if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
    1675             :     return false;
    1676             : 
    1677             :   // FIXME: Need to handle multiple memory operands to support all targets.
    1678     3530550 :   if (!hasOneMemOperand() || !Other.hasOneMemOperand())
    1679             :     return true;
    1680             : 
    1681     2560521 :   MachineMemOperand *MMOa = *memoperands_begin();
    1682     2560521 :   MachineMemOperand *MMOb = *Other.memoperands_begin();
    1683             : 
    1684             :   // The following interface to AA is fashioned after DAGCombiner::isAlias
    1685             :   // and operates with MachineMemOperand offset with some important
    1686             :   // assumptions:
    1687             :   //   - LLVM fundamentally assumes flat address spaces.
    1688             :   //   - MachineOperand offset can *only* result from legalization and
    1689             :   //     cannot affect queries other than the trivial case of overlap
    1690             :   //     checking.
    1691             :   //   - These offsets never wrap and never step outside
    1692             :   //     of allocated objects.
    1693             :   //   - There should never be any negative offsets here.
    1694             :   //
    1695             :   // FIXME: Modify API to hide this math from "user"
    1696             :   // Even before we go to AA we can reason locally about some
    1697             :   // memory objects. It can save compile time, and possibly catch some
    1698             :   // corner cases not currently covered.
    1699             : 
    1700     2560521 :   int64_t OffsetA = MMOa->getOffset();
    1701     2560521 :   int64_t OffsetB = MMOb->getOffset();
    1702             : 
    1703     2560521 :   int64_t MinOffset = std::min(OffsetA, OffsetB);
    1704     2560521 :   int64_t WidthA = MMOa->getSize();
    1705     2560521 :   int64_t WidthB = MMOb->getSize();
    1706     2560521 :   const Value *ValA = MMOa->getValue();
    1707     2560521 :   const Value *ValB = MMOb->getValue();
    1708     2560521 :   bool SameVal = (ValA && ValB && (ValA == ValB));
    1709             :   if (!SameVal) {
    1710     2114151 :     const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
    1711     2114151 :     const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
    1712     2114151 :     if (PSVa && ValB && !PSVa->mayAlias(&MFI))
    1713             :       return false;
    1714     2101666 :     if (PSVb && ValA && !PSVb->mayAlias(&MFI))
    1715             :       return false;
    1716     2090755 :     if (PSVa && PSVb && (PSVa == PSVb))
    1717             :       SameVal = true;
    1718             :   }
    1719             : 
    1720     1453829 :   if (SameVal) {
    1721     1529666 :     int64_t MaxOffset = std::max(OffsetA, OffsetB);
    1722     1529666 :     int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
    1723     1529666 :     return (MinOffset + LowWidth > MaxOffset);
    1724             :   }
    1725             : 
    1726     1007459 :   if (!AA)
    1727             :     return true;
    1728             : 
    1729       14139 :   if (!ValA || !ValB)
    1730             :     return true;
    1731             : 
    1732             :   assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
    1733             :   assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
    1734             : 
    1735        3550 :   int64_t Overlapa = WidthA + OffsetA - MinOffset;
    1736        3550 :   int64_t Overlapb = WidthB + OffsetB - MinOffset;
    1737             : 
    1738             :   AliasResult AAResult = AA->alias(
    1739       10650 :       MemoryLocation(ValA, Overlapa,
    1740        3550 :                      UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
    1741       10650 :       MemoryLocation(ValB, Overlapb,
    1742        7100 :                      UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
    1743             : 
    1744        3550 :   return (AAResult != NoAlias);
    1745             : }
    1746             : 
    1747             : /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
    1748             : /// or volatile memory reference, or if the information describing the memory
    1749             : /// reference is not available. Return false if it is known to have no ordered
    1750             : /// memory references.
    1751     8363987 : bool MachineInstr::hasOrderedMemoryRef() const {
    1752             :   // An instruction known never to access memory won't have a volatile access.
    1753    13385455 :   if (!mayStore() &&
    1754     7273835 :       !mayLoad() &&
    1755    12867498 :       !isCall() &&
    1756     2251144 :       !hasUnmodeledSideEffects())
    1757             :     return false;
    1758             : 
    1759             :   // Otherwise, if the instruction has no memory reference information,
    1760             :   // conservatively assume it wasn't preserved.
    1761     6121875 :   if (memoperands_empty())
    1762             :     return true;
    1763             : 
    1764             :   // Check if any of our memory operands are ordered.
    1765     6074611 :   return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
    1766     6416212 :     return !MMO->isUnordered();
    1767    12149222 :   });
    1768             : }
    1769             : 
    1770             : /// isDereferenceableInvariantLoad - Return true if this instruction will never
    1771             : /// trap and is loading from a location whose value is invariant across a run of
    1772             : /// this function.
    1773     2320437 : bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
    1774             :   // If the instruction doesn't load at all, it isn't an invariant load.
    1775     2320437 :   if (!mayLoad())
    1776             :     return false;
    1777             : 
    1778             :   // If the instruction has lost its memoperands, conservatively assume that
    1779             :   // it may not be an invariant load.
    1780     2022635 :   if (memoperands_empty())
    1781             :     return false;
    1782             : 
    1783     2005952 :   const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
    1784             : 
    1785     2533606 :   for (MachineMemOperand *MMO : memoperands()) {
    1786     4012056 :     if (MMO->isVolatile()) return false;
    1787     3950034 :     if (MMO->isStore()) return false;
    1788     4130759 :     if (MMO->isInvariant() && MMO->isDereferenceable())
    1789      234132 :       continue;
    1790             : 
    1791             :     // A load from a constant PseudoSourceValue is invariant.
    1792      397429 :     if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
    1793      397429 :       if (PSV->isConstant(&MFI))
    1794      286776 :         continue;
    1795             : 
    1796     1316483 :     if (const Value *V = MMO->getValue()) {
    1797             :       // If we have an AliasAnalysis, ask it whether the memory is constant.
    1798     2040189 :       if (AA &&
    1799      734133 :           AA->pointsToConstantMemory(
    1800     2760830 :               MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
    1801        6746 :         continue;
    1802             :     }
    1803             : 
    1804             :     // Otherwise assume conservatively.
    1805             :     return false;
    1806             :   }
    1807             : 
    1808             :   // Everything checks out.
    1809             :   return true;
    1810             : }
    1811             : 
    1812             : /// isConstantValuePHI - If the specified instruction is a PHI that always
    1813             : /// merges together the same virtual register, return the register, otherwise
    1814             : /// return 0.
    1815          23 : unsigned MachineInstr::isConstantValuePHI() const {
    1816             :   if (!isPHI())
    1817             :     return 0;
    1818             :   assert(getNumOperands() >= 3 &&
    1819             :          "It's illegal to have a PHI without source operands");
    1820             : 
    1821          23 :   unsigned Reg = getOperand(1).getReg();
    1822          23 :   for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
    1823          46 :     if (getOperand(i).getReg() != Reg)
    1824             :       return 0;
    1825             :   return Reg;
    1826             : }
    1827             : 
    1828    29661882 : bool MachineInstr::hasUnmodeledSideEffects() const {
    1829    29661882 :   if (hasProperty(MCID::UnmodeledSideEffects))
    1830             :     return true;
    1831    29153380 :   if (isInlineAsm()) {
    1832       17472 :     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    1833       17472 :     if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
    1834             :       return true;
    1835             :   }
    1836             : 
    1837             :   return false;
    1838             : }
    1839             : 
    1840     3723056 : bool MachineInstr::isLoadFoldBarrier() const {
    1841     6863674 :   return mayStore() || isCall() || hasUnmodeledSideEffects();
    1842             : }
    1843             : 
    1844             : /// allDefsAreDead - Return true if all the defs of this instruction are dead.
    1845             : ///
    1846      852582 : bool MachineInstr::allDefsAreDead() const {
    1847     1019395 :   for (const MachineOperand &MO : operands()) {
    1848     1840770 :     if (!MO.isReg() || MO.isUse())
    1849       90780 :       continue;
    1850      858995 :     if (!MO.isDead())
    1851             :       return false;
    1852             :   }
    1853             :   return true;
    1854             : }
    1855             : 
    1856             : /// copyImplicitOps - Copy implicit register operands from specified
    1857             : /// instruction to this instruction.
    1858       10738 : void MachineInstr::copyImplicitOps(MachineFunction &MF,
    1859             :                                    const MachineInstr &MI) {
    1860       34624 :   for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
    1861       23886 :        i != e; ++i) {
    1862       26296 :     const MachineOperand &MO = MI.getOperand(i);
    1863       24471 :     if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
    1864       13148 :       addOperand(MF, MO);
    1865             :   }
    1866       10738 : }
    1867             : 
    1868             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
    1869             : LLVM_DUMP_METHOD void MachineInstr::dump() const {
    1870             :   dbgs() << "  ";
    1871             :   print(dbgs());
    1872             : }
    1873             : #endif
    1874             : 
    1875          28 : void MachineInstr::print(raw_ostream &OS, bool SkipOpers, bool SkipDebugLoc,
    1876             :                          const TargetInstrInfo *TII) const {
    1877          28 :   const Module *M = nullptr;
    1878          28 :   if (const MachineBasicBlock *MBB = getParent())
    1879          28 :     if (const MachineFunction *MF = MBB->getParent())
    1880          28 :       M = MF->getFunction()->getParent();
    1881             : 
    1882          56 :   ModuleSlotTracker MST(M);
    1883          28 :   print(OS, MST, SkipOpers, SkipDebugLoc, TII);
    1884          28 : }
    1885             : 
    1886       46100 : void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
    1887             :                          bool SkipOpers, bool SkipDebugLoc,
    1888             :                          const TargetInstrInfo *TII) const {
    1889             :   // We can be a bit tidier if we know the MachineFunction.
    1890       46100 :   const MachineFunction *MF = nullptr;
    1891       46100 :   const TargetRegisterInfo *TRI = nullptr;
    1892       46100 :   const MachineRegisterInfo *MRI = nullptr;
    1893       46100 :   const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
    1894             : 
    1895       46100 :   if (const MachineBasicBlock *MBB = getParent()) {
    1896       46100 :     MF = MBB->getParent();
    1897       46100 :     if (MF) {
    1898       46100 :       MRI = &MF->getRegInfo();
    1899       46100 :       TRI = MF->getSubtarget().getRegisterInfo();
    1900       46100 :       if (!TII)
    1901       46100 :         TII = MF->getSubtarget().getInstrInfo();
    1902       46100 :       IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
    1903             :     }
    1904             :   }
    1905             : 
    1906             :   // Save a list of virtual registers.
    1907       92173 :   SmallVector<unsigned, 8> VirtRegs;
    1908             : 
    1909             :   // Print explicitly defined operands on the left of an assignment syntax.
    1910       46100 :   unsigned StartOp = 0, e = getNumOperands();
    1911      256848 :   for (; StartOp < e && getOperand(StartOp).isReg() &&
    1912      159950 :          getOperand(StartOp).isDef() &&
    1913       41612 :          !getOperand(StartOp).isImplicit();
    1914             :        ++StartOp) {
    1915       21269 :     if (StartOp != 0) OS << ", ";
    1916       41588 :     getOperand(StartOp).print(OS, MST, TRI, IntrinsicInfo);
    1917       41588 :     unsigned Reg = getOperand(StartOp).getReg();
    1918       41588 :     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    1919        8246 :       VirtRegs.push_back(Reg);
    1920        8246 :       LLT Ty = MRI ? MRI->getType(Reg) : LLT{};
    1921        8246 :       if (Ty.isValid())
    1922          68 :         OS << '(' << Ty << ')';
    1923             :     }
    1924             :   }
    1925             : 
    1926       46100 :   if (StartOp != 0)
    1927       20319 :     OS << " = ";
    1928             : 
    1929             :   // Print the opcode name.
    1930       46100 :   if (TII)
    1931      138300 :     OS << TII->getName(getOpcode());
    1932             :   else
    1933           0 :     OS << "UNKNOWN";
    1934             : 
    1935       46100 :   if (SkipOpers)
    1936          27 :     return;
    1937             : 
    1938             :   // Print the rest of the operands.
    1939       46094 :   bool FirstOp = true;
    1940       46094 :   unsigned AsmDescOp = ~0u;
    1941       46094 :   unsigned AsmOpCount = 0;
    1942             : 
    1943       46094 :   if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
    1944             :     // Print asm string.
    1945           0 :     OS << " ";
    1946           0 :     getOperand(InlineAsm::MIOp_AsmString).print(OS, MST, TRI);
    1947             : 
    1948             :     // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
    1949           0 :     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    1950           0 :     if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
    1951           0 :       OS << " [sideeffect]";
    1952           0 :     if (ExtraInfo & InlineAsm::Extra_MayLoad)
    1953           0 :       OS << " [mayload]";
    1954           0 :     if (ExtraInfo & InlineAsm::Extra_MayStore)
    1955           0 :       OS << " [maystore]";
    1956           0 :     if (ExtraInfo & InlineAsm::Extra_IsConvergent)
    1957           0 :       OS << " [isconvergent]";
    1958           0 :     if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
    1959           0 :       OS << " [alignstack]";
    1960           0 :     if (getInlineAsmDialect() == InlineAsm::AD_ATT)
    1961           0 :       OS << " [attdialect]";
    1962           0 :     if (getInlineAsmDialect() == InlineAsm::AD_Intel)
    1963           0 :       OS << " [inteldialect]";
    1964             : 
    1965             :     StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
    1966             :     FirstOp = false;
    1967             :   }
    1968             : 
    1969      168182 :   for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
    1970      244176 :     const MachineOperand &MO = getOperand(i);
    1971             : 
    1972      182934 :     if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
    1973        8734 :       VirtRegs.push_back(MO.getReg());
    1974             : 
    1975      122088 :     if (FirstOp) FirstOp = false; else OS << ",";
    1976      122088 :     OS << " ";
    1977      122088 :     if (i < getDesc().NumOperands) {
    1978       73568 :       const MCOperandInfo &MCOI = getDesc().OpInfo[i];
    1979       73568 :       if (MCOI.isPredicate())
    1980         792 :         OS << "pred:";
    1981       73568 :       if (MCOI.isOptionalDef())
    1982          63 :         OS << "opt:";
    1983             :     }
    1984      122168 :     if (isDebugValue() && MO.isMetadata()) {
    1985             :       // Pretty print DBG_VALUE instructions.
    1986          60 :       auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
    1987          40 :       if (DIV && !DIV->getName().empty())
    1988          40 :         OS << "!\"" << DIV->getName() << '\"';
    1989             :       else
    1990          20 :         MO.print(OS, MST, TRI);
    1991      366132 :     } else if (TRI && (isInsertSubreg() || isRegSequence() ||
    1992      246292 :                        (isSubregToReg() && i == 3)) && MO.isImm()) {
    1993        1102 :       OS << TRI->getSubRegIndexName(MO.getImm());
    1994      121497 :     } else if (i == AsmDescOp && MO.isImm()) {
    1995             :       // Pretty print the inline asm operand descriptor.
    1996           0 :       OS << '$' << AsmOpCount++;
    1997           0 :       unsigned Flag = MO.getImm();
    1998           0 :       switch (InlineAsm::getKind(Flag)) {
    1999           0 :       case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
    2000           0 :       case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
    2001           0 :       case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
    2002           0 :       case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
    2003           0 :       case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
    2004           0 :       case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
    2005           0 :       default: OS << ":[??" << InlineAsm::getKind(Flag); break;
    2006             :       }
    2007             : 
    2008           0 :       unsigned RCID = 0;
    2009           0 :       if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
    2010           0 :           InlineAsm::hasRegClassConstraint(Flag, RCID)) {
    2011           0 :         if (TRI) {
    2012           0 :           OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
    2013             :         } else
    2014           0 :           OS << ":RC" << RCID;
    2015             :       }
    2016             : 
    2017           0 :       if (InlineAsm::isMemKind(Flag)) {
    2018           0 :         unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
    2019           0 :         switch (MCID) {
    2020           0 :         case InlineAsm::Constraint_es: OS << ":es"; break;
    2021           0 :         case InlineAsm::Constraint_i:  OS << ":i"; break;
    2022           0 :         case InlineAsm::Constraint_m:  OS << ":m"; break;
    2023           0 :         case InlineAsm::Constraint_o:  OS << ":o"; break;
    2024           0 :         case InlineAsm::Constraint_v:  OS << ":v"; break;
    2025           0 :         case InlineAsm::Constraint_Q:  OS << ":Q"; break;
    2026           0 :         case InlineAsm::Constraint_R:  OS << ":R"; break;
    2027           0 :         case InlineAsm::Constraint_S:  OS << ":S"; break;
    2028           0 :         case InlineAsm::Constraint_T:  OS << ":T"; break;
    2029           0 :         case InlineAsm::Constraint_Um: OS << ":Um"; break;
    2030           0 :         case InlineAsm::Constraint_Un: OS << ":Un"; break;
    2031           0 :         case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
    2032           0 :         case InlineAsm::Constraint_Us: OS << ":Us"; break;
    2033           0 :         case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
    2034           0 :         case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
    2035           0 :         case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
    2036           0 :         case InlineAsm::Constraint_X:  OS << ":X"; break;
    2037           0 :         case InlineAsm::Constraint_Z:  OS << ":Z"; break;
    2038           0 :         case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
    2039           0 :         case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
    2040           0 :         default: OS << ":?"; break;
    2041             :         }
    2042             :       }
    2043             : 
    2044           0 :       unsigned TiedTo = 0;
    2045           0 :       if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
    2046           0 :         OS << " tiedto:$" << TiedTo;
    2047             : 
    2048           0 :       OS << ']';
    2049             : 
    2050             :       // Compute the index of the next operand descriptor.
    2051           0 :       AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
    2052             :     } else
    2053      121497 :       MO.print(OS, MST, TRI);
    2054             :   }
    2055             : 
    2056       46094 :   bool HaveSemi = false;
    2057       46094 :   const unsigned PrintableFlags = FrameSetup | FrameDestroy;
    2058       46094 :   if (Flags & PrintableFlags) {
    2059             :     if (!HaveSemi) {
    2060        1215 :       OS << ";";
    2061        1215 :       HaveSemi = true;
    2062             :     }
    2063        1215 :     OS << " flags: ";
    2064             : 
    2065        1215 :     if (Flags & FrameSetup)
    2066         981 :       OS << "FrameSetup";
    2067             : 
    2068        1215 :     if (Flags & FrameDestroy)
    2069         234 :       OS << "FrameDestroy";
    2070             :   }
    2071             : 
    2072       46094 :   if (!memoperands_empty()) {
    2073        1652 :     if (!HaveSemi) {
    2074        1184 :       OS << ";";
    2075        1184 :       HaveSemi = true;
    2076             :     }
    2077             : 
    2078        1652 :     OS << " mem:";
    2079        3304 :     for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
    2080        3772 :          i != e; ++i) {
    2081        2120 :       (*i)->print(OS, MST);
    2082        2120 :       if (std::next(i) != e)
    2083         468 :         OS << " ";
    2084             :     }
    2085             :   }
    2086             : 
    2087             :   // Print the regclass of any virtual registers encountered.
    2088       46094 :   if (MRI && !VirtRegs.empty()) {
    2089       13462 :     if (!HaveSemi) {
    2090       12779 :       OS << ";";
    2091       12779 :       HaveSemi = true;
    2092             :     }
    2093       58054 :     for (unsigned i = 0; i != VirtRegs.size(); ++i) {
    2094       46695 :       const RegClassOrRegBank &RC = MRI->getRegClassOrRegBank(VirtRegs[i]);
    2095       15565 :       if (!RC)
    2096          50 :         continue;
    2097             :       // Generic virtual registers do not have register classes.
    2098       15515 :       if (RC.is<const RegisterBank *>())
    2099          10 :         OS << " " << RC.get<const RegisterBank *>()->getName();
    2100             :       else
    2101       15510 :         OS << " "
    2102       31020 :            << TRI->getRegClassName(RC.get<const TargetRegisterClass *>());
    2103       62060 :       OS << ':' << PrintReg(VirtRegs[i]);
    2104       34598 :       for (unsigned j = i+1; j != VirtRegs.size();) {
    2105       16429 :         if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) {
    2106        2157 :           ++j;
    2107        2157 :           continue;
    2108             :         }
    2109        4233 :         if (VirtRegs[i] != VirtRegs[j])
    2110        5588 :           OS << "," << PrintReg(VirtRegs[j]);
    2111        1411 :         VirtRegs.erase(VirtRegs.begin()+j);
    2112             :       }
    2113             :     }
    2114             :   }
    2115             : 
    2116             :   // Print debug location information.
    2117       46134 :   if (isDebugValue() && getOperand(e - 2).isMetadata()) {
    2118          20 :     if (!HaveSemi)
    2119          20 :       OS << ";";
    2120          60 :     auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
    2121          40 :     OS << " line no:" <<  DV->getLine();
    2122          40 :     if (auto *InlinedAt = debugLoc->getInlinedAt()) {
    2123           0 :       DebugLoc InlinedAtDL(InlinedAt);
    2124           0 :       if (InlinedAtDL && MF) {
    2125           0 :         OS << " inlined @[ ";
    2126           0 :         InlinedAtDL.print(OS);
    2127           0 :         OS << " ]";
    2128             :       }
    2129             :     }
    2130           0 :     if (isIndirectDebugValue())
    2131           0 :       OS << " indirect";
    2132       46074 :   } else if (SkipDebugLoc) {
    2133             :     return;
    2134       92106 :   } else if (debugLoc && MF) {
    2135          10 :     if (!HaveSemi)
    2136          10 :       OS << ";";
    2137          10 :     OS << " dbg:";
    2138          10 :     debugLoc.print(OS);
    2139             :   }
    2140             : 
    2141       46073 :   OS << '\n';
    2142             : }
    2143             : 
    2144     9146747 : bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
    2145             :                                      const TargetRegisterInfo *RegInfo,
    2146             :                                      bool AddIfNotFound) {
    2147     9146747 :   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
    2148    14977110 :   bool hasAliases = isPhysReg &&
    2149    20807473 :     MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
    2150     9146746 :   bool Found = false;
    2151    18293492 :   SmallVector<unsigned,4> DeadOps;
    2152    43889631 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    2153    78515740 :     MachineOperand &MO = getOperand(i);
    2154    88977795 :     if (!MO.isReg() || !MO.isUse() || MO.isUndef())
    2155    17168151 :       continue;
    2156             : 
    2157             :     // DEBUG_VALUE nodes do not contribute to code generation and should
    2158             :     // always be ignored. Failure to do so may result in trying to modify
    2159             :     // KILL flags on DEBUG_VALUE nodes.
    2160    22089719 :     if (MO.isDebug())
    2161           0 :       continue;
    2162             : 
    2163    22089719 :     unsigned Reg = MO.getReg();
    2164    22089719 :     if (!Reg)
    2165     1205565 :       continue;
    2166             : 
    2167    20884154 :     if (Reg == IncomingReg) {
    2168     5770642 :       if (!Found) {
    2169     5725079 :         if (MO.isKill())
    2170             :           // The register is already marked kill.
    2171     4514985 :           return true;
    2172     4177085 :         if (isPhysReg && isRegTiedToDefOperand(i))
    2173             :           // Two-address uses of physregs must not be marked kill.
    2174             :           return true;
    2175     4177084 :         MO.setIsKill();
    2176     4177084 :         Found = true;
    2177             :       }
    2178    34960670 :     } else if (hasAliases && MO.isKill() &&
    2179     7203180 :                TargetRegisterInfo::isPhysicalRegister(Reg)) {
    2180             :       // A super-register kill already exists.
    2181     7203180 :       if (RegInfo->isSuperRegister(IncomingReg, Reg))
    2182             :         return true;
    2183     8472380 :       if (RegInfo->isSubRegister(IncomingReg, Reg))
    2184      405674 :         DeadOps.push_back(i);
    2185             :     }
    2186             :   }
    2187             : 
    2188             :   // Trim unneeded kill operands.
    2189     5037435 :   while (!DeadOps.empty()) {
    2190      811348 :     unsigned OpIdx = DeadOps.back();
    2191     1217022 :     if (getOperand(OpIdx).isImplicit())
    2192      371175 :       RemoveOperand(OpIdx);
    2193             :     else
    2194       34499 :       getOperand(OpIdx).setIsKill(false);
    2195             :     DeadOps.pop_back();
    2196             :   }
    2197             : 
    2198             :   // If not found, this means an alias of one of the operands is killed. Add a
    2199             :   // new implicit operand if required.
    2200     4631761 :   if (!Found && AddIfNotFound) {
    2201      428949 :     addOperand(MachineOperand::CreateReg(IncomingReg,
    2202             :                                          false /*IsDef*/,
    2203             :                                          true  /*IsImp*/,
    2204             :                                          true  /*IsKill*/));
    2205      428949 :     return true;
    2206             :   }
    2207             :   return Found;
    2208             : }
    2209             : 
    2210      145088 : void MachineInstr::clearRegisterKills(unsigned Reg,
    2211             :                                       const TargetRegisterInfo *RegInfo) {
    2212      145088 :   if (!TargetRegisterInfo::isPhysicalRegister(Reg))
    2213      110524 :     RegInfo = nullptr;
    2214      863519 :   for (MachineOperand &MO : operands()) {
    2215     1436598 :     if (!MO.isReg() || !MO.isUse() || !MO.isKill())
    2216      679065 :       continue;
    2217       39366 :     unsigned OpReg = MO.getReg();
    2218       39366 :     if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
    2219             :       MO.setIsKill(false);
    2220             :   }
    2221      145088 : }
    2222             : 
    2223     1049699 : bool MachineInstr::addRegisterDead(unsigned Reg,
    2224             :                                    const TargetRegisterInfo *RegInfo,
    2225             :                                    bool AddIfNotFound) {
    2226     1049699 :   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
    2227     2017337 :   bool hasAliases = isPhysReg &&
    2228     2984975 :     MCRegAliasIterator(Reg, RegInfo, false).isValid();
    2229     1049699 :   bool Found = false;
    2230     2099398 :   SmallVector<unsigned,4> DeadOps;
    2231    11074327 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    2232    20279264 :     MachineOperand &MO = getOperand(i);
    2233    15908965 :     if (!MO.isReg() || !MO.isDef())
    2234     5799111 :       continue;
    2235     4340521 :     unsigned MOReg = MO.getReg();
    2236     4340521 :     if (!MOReg)
    2237           0 :       continue;
    2238             : 
    2239     4340521 :     if (MOReg == Reg) {
    2240      912333 :       MO.setIsDead();
    2241      912333 :       Found = true;
    2242     7442318 :     } else if (hasAliases && MO.isDead() &&
    2243     1380840 :                TargetRegisterInfo::isPhysicalRegister(MOReg)) {
    2244             :       // There exists a super-register that's marked dead.
    2245     1379897 :       if (RegInfo->isSuperRegister(Reg, MOReg))
    2246      115004 :         return true;
    2247     2529786 :       if (RegInfo->isSubRegister(Reg, MOReg))
    2248       22419 :         DeadOps.push_back(i);
    2249             :     }
    2250             :   }
    2251             : 
    2252             :   // Trim unneeded dead operands.
    2253      957114 :   while (!DeadOps.empty()) {
    2254       44838 :     unsigned OpIdx = DeadOps.back();
    2255       67257 :     if (getOperand(OpIdx).isImplicit())
    2256       22364 :       RemoveOperand(OpIdx);
    2257             :     else
    2258          55 :       getOperand(OpIdx).setIsDead(false);
    2259             :     DeadOps.pop_back();
    2260             :   }
    2261             : 
    2262             :   // If not found, this means an alias of one of the operands is dead. Add a
    2263             :   // new implicit operand if required.
    2264      934695 :   if (Found || !AddIfNotFound)
    2265             :     return Found;
    2266             : 
    2267       22386 :   addOperand(MachineOperand::CreateReg(Reg,
    2268             :                                        true  /*IsDef*/,
    2269             :                                        true  /*IsImp*/,
    2270             :                                        false /*IsKill*/,
    2271             :                                        true  /*IsDead*/));
    2272       22386 :   return true;
    2273             : }
    2274             : 
    2275       49213 : void MachineInstr::clearRegisterDeads(unsigned Reg) {
    2276      302446 :   for (MachineOperand &MO : operands()) {
    2277      410955 :     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
    2278      204106 :       continue;
    2279             :     MO.setIsDead(false);
    2280             :   }
    2281       49213 : }
    2282             : 
    2283      383849 : void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
    2284     1942056 :   for (MachineOperand &MO : operands()) {
    2285     2994084 :     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
    2286     1482815 :       continue;
    2287       75392 :     MO.setIsUndef(IsUndef);
    2288             :   }
    2289      383849 : }
    2290             : 
    2291      274841 : void MachineInstr::addRegisterDefined(unsigned Reg,
    2292             :                                       const TargetRegisterInfo *RegInfo) {
    2293      274841 :   if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
    2294          59 :     MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
    2295          59 :     if (MO)
    2296             :       return;
    2297             :   } else {
    2298           0 :     for (const MachineOperand &MO : operands()) {
    2299           0 :       if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
    2300           0 :           MO.getSubReg() == 0)
    2301             :         return;
    2302             :     }
    2303             :   }
    2304      274782 :   addOperand(MachineOperand::CreateReg(Reg,
    2305             :                                        true  /*IsDef*/,
    2306             :                                        true  /*IsImp*/));
    2307             : }
    2308             : 
    2309      943308 : void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
    2310             :                                          const TargetRegisterInfo &TRI) {
    2311      943308 :   bool HasRegMask = false;
    2312     6025682 :   for (MachineOperand &MO : operands()) {
    2313     5269500 :     if (MO.isRegMask()) {
    2314      187126 :       HasRegMask = true;
    2315     4146417 :       continue;
    2316             :     }
    2317     8027026 :     if (!MO.isReg() || !MO.isDef()) continue;
    2318     1275729 :     unsigned Reg = MO.getReg();
    2319     2551458 :     if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
    2320             :     // If there are no uses, including partial uses, the def is dead.
    2321     2246166 :     if (llvm::none_of(UsedRegs,
    2322      228990 :                       [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
    2323             :       MO.setIsDead();
    2324             :   }
    2325             : 
    2326             :   // This is a call with a register mask operand.
    2327             :   // Mask clobbers are always dead, so add defs for the non-dead defines.
    2328      943308 :   if (HasRegMask)
    2329      588310 :     for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
    2330      401184 :          I != E; ++I)
    2331      214058 :       addRegisterDefined(*I, &TRI);
    2332      943308 : }
    2333             : 
    2334             : unsigned
    2335     5546298 : MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
    2336             :   // Build up a buffer of hash code components.
    2337    11092596 :   SmallVector<size_t, 8> HashComponents;
    2338     5546298 :   HashComponents.reserve(MI->getNumOperands() + 1);
    2339    11092596 :   HashComponents.push_back(MI->getOpcode());
    2340    37792871 :   for (const MachineOperand &MO : MI->operands()) {
    2341    50626452 :     if (MO.isReg() && MO.isDef() &&
    2342    14309142 :         TargetRegisterInfo::isVirtualRegister(MO.getReg()))
    2343     4310436 :       continue;  // Skip virtual register defs.
    2344             : 
    2345    44779678 :     HashComponents.push_back(hash_value(MO));
    2346             :   }
    2347    22185192 :   return hash_combine_range(HashComponents.begin(), HashComponents.end());
    2348             : }
    2349             : 
    2350         108 : void MachineInstr::emitError(StringRef Msg) const {
    2351             :   // Find the source location cookie.
    2352         108 :   unsigned LocCookie = 0;
    2353         108 :   const MDNode *LocMD = nullptr;
    2354         108 :   for (unsigned i = getNumOperands(); i != 0; --i) {
    2355        7290 :     if (getOperand(i-1).isMetadata() &&
    2356        2438 :         (LocMD = getOperand(i-1).getMetadata()) &&
    2357             :         LocMD->getNumOperands() != 0) {
    2358             :       if (const ConstantInt *CI =
    2359          24 :               mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
    2360          12 :         LocCookie = CI->getZExtValue();
    2361          12 :         break;
    2362             :       }
    2363             :     }
    2364             :   }
    2365             : 
    2366         108 :   if (const MachineBasicBlock *MBB = getParent())
    2367         108 :     if (const MachineFunction *MF = MBB->getParent())
    2368         216 :       return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
    2369           0 :   report_fatal_error(Msg);
    2370             : }
    2371             : 
    2372       37921 : MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
    2373             :                                   const MCInstrDesc &MCID, bool IsIndirect,
    2374             :                                   unsigned Reg, const MDNode *Variable,
    2375             :                                   const MDNode *Expr) {
    2376             :   assert(isa<DILocalVariable>(Variable) && "not a variable");
    2377             :   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
    2378             :   assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
    2379             :          "Expected inlined-at fields to agree");
    2380       37921 :   if (IsIndirect)
    2381       13392 :     return BuildMI(MF, DL, MCID)
    2382        6696 :         .addReg(Reg, RegState::Debug)
    2383        6696 :         .addImm(0U)
    2384        6696 :         .addMetadata(Variable)
    2385        6696 :         .addMetadata(Expr);
    2386             :   else
    2387       62450 :     return BuildMI(MF, DL, MCID)
    2388       31225 :         .addReg(Reg, RegState::Debug)
    2389       31225 :         .addReg(0U, RegState::Debug)
    2390       31225 :         .addMetadata(Variable)
    2391       31225 :         .addMetadata(Expr);
    2392             : }
    2393             : 
    2394       36841 : MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
    2395             :                                   MachineBasicBlock::iterator I,
    2396             :                                   const DebugLoc &DL, const MCInstrDesc &MCID,
    2397             :                                   bool IsIndirect, unsigned Reg,
    2398             :                                   const MDNode *Variable, const MDNode *Expr) {
    2399             :   assert(isa<DILocalVariable>(Variable) && "not a variable");
    2400             :   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
    2401       36841 :   MachineFunction &MF = *BB.getParent();
    2402       36841 :   MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
    2403       36841 :   BB.insert(I, MI);
    2404       36841 :   return MachineInstrBuilder(MF, MI);
    2405             : }
    2406             : 
    2407          43 : MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
    2408             :                                           MachineBasicBlock::iterator I,
    2409             :                                           const MachineInstr &Orig,
    2410             :                                           int FrameIndex) {
    2411          43 :   const MDNode *Var = Orig.getDebugVariable();
    2412          86 :   const auto *Expr = cast_or_null<DIExpression>(Orig.getDebugExpression());
    2413          43 :   bool IsIndirect = Orig.isIndirectDebugValue();
    2414             :   if (IsIndirect)
    2415             :     assert(Orig.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
    2416         129 :   DebugLoc DL = Orig.getDebugLoc();
    2417             :   assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
    2418             :          "Expected inlined-at fields to agree");
    2419             :   // If the DBG_VALUE already was a memory location, add an extra
    2420             :   // DW_OP_deref. Otherwise just turning this from a register into a
    2421             :   // memory/indirect location is sufficient.
    2422          43 :   if (IsIndirect)
    2423          21 :     Expr = DIExpression::prepend(Expr, DIExpression::WithDeref);
    2424          86 :   return BuildMI(BB, I, DL, Orig.getDesc())
    2425          43 :       .addFrameIndex(FrameIndex)
    2426          43 :       .addImm(0U)
    2427          43 :       .addMetadata(Var)
    2428          86 :       .addMetadata(Expr);
    2429      216918 : }

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