LCOV - code coverage report
Current view: top level - lib/CodeGen - MachineInstr.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 691 787 87.8 %
Date: 2018-06-17 00:07:59 Functions: 76 77 98.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // Methods common to all machine instructions.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "llvm/CodeGen/MachineInstr.h"
      15             : #include "llvm/ADT/APFloat.h"
      16             : #include "llvm/ADT/ArrayRef.h"
      17             : #include "llvm/ADT/FoldingSet.h"
      18             : #include "llvm/ADT/Hashing.h"
      19             : #include "llvm/ADT/None.h"
      20             : #include "llvm/ADT/STLExtras.h"
      21             : #include "llvm/ADT/SmallBitVector.h"
      22             : #include "llvm/ADT/SmallString.h"
      23             : #include "llvm/ADT/SmallVector.h"
      24             : #include "llvm/Analysis/AliasAnalysis.h"
      25             : #include "llvm/Analysis/Loads.h"
      26             : #include "llvm/Analysis/MemoryLocation.h"
      27             : #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
      28             : #include "llvm/CodeGen/MachineBasicBlock.h"
      29             : #include "llvm/CodeGen/MachineFunction.h"
      30             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      31             : #include "llvm/CodeGen/MachineInstrBundle.h"
      32             : #include "llvm/CodeGen/MachineMemOperand.h"
      33             : #include "llvm/CodeGen/MachineModuleInfo.h"
      34             : #include "llvm/CodeGen/MachineOperand.h"
      35             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      36             : #include "llvm/CodeGen/PseudoSourceValue.h"
      37             : #include "llvm/CodeGen/TargetInstrInfo.h"
      38             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      39             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      40             : #include "llvm/Config/llvm-config.h"
      41             : #include "llvm/IR/Constants.h"
      42             : #include "llvm/IR/DebugInfoMetadata.h"
      43             : #include "llvm/IR/DebugLoc.h"
      44             : #include "llvm/IR/DerivedTypes.h"
      45             : #include "llvm/IR/Function.h"
      46             : #include "llvm/IR/InlineAsm.h"
      47             : #include "llvm/IR/InstrTypes.h"
      48             : #include "llvm/IR/Intrinsics.h"
      49             : #include "llvm/IR/LLVMContext.h"
      50             : #include "llvm/IR/Metadata.h"
      51             : #include "llvm/IR/Module.h"
      52             : #include "llvm/IR/ModuleSlotTracker.h"
      53             : #include "llvm/IR/Type.h"
      54             : #include "llvm/IR/Value.h"
      55             : #include "llvm/MC/MCInstrDesc.h"
      56             : #include "llvm/MC/MCRegisterInfo.h"
      57             : #include "llvm/MC/MCSymbol.h"
      58             : #include "llvm/Support/Casting.h"
      59             : #include "llvm/Support/CommandLine.h"
      60             : #include "llvm/Support/Compiler.h"
      61             : #include "llvm/Support/Debug.h"
      62             : #include "llvm/Support/ErrorHandling.h"
      63             : #include "llvm/Support/LowLevelTypeImpl.h"
      64             : #include "llvm/Support/MathExtras.h"
      65             : #include "llvm/Support/raw_ostream.h"
      66             : #include "llvm/Target/TargetIntrinsicInfo.h"
      67             : #include "llvm/Target/TargetMachine.h"
      68             : #include <algorithm>
      69             : #include <cassert>
      70             : #include <cstddef>
      71             : #include <cstdint>
      72             : #include <cstring>
      73             : #include <iterator>
      74             : #include <utility>
      75             : 
      76             : using namespace llvm;
      77             : 
      78             : static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
      79       56752 :   if (const MachineBasicBlock *MBB = MI.getParent())
      80       56750 :     if (const MachineFunction *MF = MBB->getParent())
      81             :       return MF;
      82             :   return nullptr;
      83             : }
      84             : 
      85             : // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
      86             : // it.
      87       54709 : static void tryToGetTargetInfo(const MachineInstr &MI,
      88             :                                const TargetRegisterInfo *&TRI,
      89             :                                const MachineRegisterInfo *&MRI,
      90             :                                const TargetIntrinsicInfo *&IntrinsicInfo,
      91             :                                const TargetInstrInfo *&TII) {
      92             : 
      93             :   if (const MachineFunction *MF = getMFIfAvailable(MI)) {
      94       54708 :     TRI = MF->getSubtarget().getRegisterInfo();
      95       54708 :     MRI = &MF->getRegInfo();
      96       54708 :     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
      97       54708 :     TII = MF->getSubtarget().getInstrInfo();
      98             :   }
      99       54709 : }
     100             : 
     101     8163686 : void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
     102     8163686 :   if (MCID->ImplicitDefs)
     103     5897408 :     for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
     104             :            ++ImpDefs)
     105     4615424 :       addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
     106     8163686 :   if (MCID->ImplicitUses)
     107     6034953 :     for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
     108             :            ++ImpUses)
     109     4503796 :       addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
     110     8163686 : }
     111             : 
     112             : /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
     113             : /// implicit operands. It reserves space for the number of operands specified by
     114             : /// the MCInstrDesc.
     115     8105267 : MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
     116     8105267 :                            DebugLoc dl, bool NoImp)
     117    16210534 :     : MCID(&tid), debugLoc(std::move(dl)) {
     118             :   assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
     119             : 
     120             :   // Reserve space for the expected number of operands.
     121    24315801 :   if (unsigned NumOps = MCID->getNumOperands() +
     122    24315801 :     MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
     123    15510564 :     CapOperands = OperandCapacity::get(NumOps);
     124     7755282 :     Operands = MF.allocateOperandArray(CapOperands);
     125             :   }
     126             : 
     127     8105267 :   if (!NoImp)
     128     8054318 :     addImplicitDefUseOperands(MF);
     129     8105267 : }
     130             : 
     131             : /// MachineInstr ctor - Copies MachineInstr arg exactly
     132             : ///
     133       98048 : MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
     134      294144 :     : MCID(&MI.getDesc()), NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
     135      392192 :       debugLoc(MI.getDebugLoc()) {
     136             :   assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
     137             : 
     138      196096 :   CapOperands = OperandCapacity::get(MI.getNumOperands());
     139       98048 :   Operands = MF.allocateOperandArray(CapOperands);
     140             : 
     141             :   // Copy operands.
     142      704716 :   for (const MachineOperand &MO : MI.operands())
     143      303334 :     addOperand(MF, MO);
     144             : 
     145             :   // Copy all the sensible flags.
     146       98048 :   setFlags(MI.Flags);
     147       98048 : }
     148             : 
     149             : /// getRegInfo - If this instruction is embedded into a MachineFunction,
     150             : /// return the MachineRegisterInfo object for the current function, otherwise
     151             : /// return null.
     152    31032972 : MachineRegisterInfo *MachineInstr::getRegInfo() {
     153    31032972 :   if (MachineBasicBlock *MBB = getParent())
     154    13270464 :     return &MBB->getParent()->getRegInfo();
     155             :   return nullptr;
     156             : }
     157             : 
     158             : /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
     159             : /// this instruction from their respective use lists.  This requires that the
     160             : /// operands already be on their use lists.
     161     4110680 : void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
     162    28486954 :   for (MachineOperand &MO : operands())
     163    12188137 :     if (MO.isReg())
     164     9212611 :       MRI.removeRegOperandFromUseList(&MO);
     165     4110680 : }
     166             : 
     167             : /// AddRegOperandsToUseLists - Add all of the register operands in
     168             : /// this instruction from their respective use lists.  This requires that the
     169             : /// operands not be on their use lists yet.
     170     8237642 : void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
     171    44052384 :   for (MachineOperand &MO : operands())
     172    17907371 :     if (MO.isReg())
     173    11835287 :       MRI.addRegOperandToUseList(&MO);
     174     8237642 : }
     175             : 
     176     1175167 : void MachineInstr::addOperand(const MachineOperand &Op) {
     177     1175167 :   MachineBasicBlock *MBB = getParent();
     178             :   assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
     179     1175167 :   MachineFunction *MF = MBB->getParent();
     180             :   assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
     181     1175167 :   addOperand(*MF, Op);
     182     1175167 : }
     183             : 
     184             : /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
     185             : /// ranges. If MRI is non-null also update use-def chains.
     186     7175831 : static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
     187             :                          unsigned NumOps, MachineRegisterInfo *MRI) {
     188     7175831 :   if (MRI)
     189     2913303 :     return MRI->moveOperands(Dst, Src, NumOps);
     190             : 
     191             :   // MachineOperand is a trivially copyable type so we can just use memmove.
     192     4262528 :   std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
     193             : }
     194             : 
     195             : /// addOperand - Add the specified operand to the instruction.  If it is an
     196             : /// implicit operand, it is added to the end of the operand list.  If it is
     197             : /// an explicit operand it is added at the end of the explicit operand list
     198             : /// (before the first implicit operand).
     199    30328327 : void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
     200             :   assert(MCID && "Cannot add operands before providing an instr descriptor");
     201             : 
     202             :   // Check if we're adding one of our existing operands.
     203    30328327 :   if (&Op >= Operands && &Op < Operands + NumOperands) {
     204             :     // This is unusual: MI->addOperand(MI->getOperand(i)).
     205             :     // If adding Op requires reallocating or moving existing operands around,
     206             :     // the Op reference could go stale. Support it by copying Op.
     207         576 :     MachineOperand CopyOp(Op);
     208         576 :     return addOperand(MF, CopyOp);
     209             :   }
     210             : 
     211             :   // Find the insert location for the new operand.  Implicit registers go at
     212             :   // the end, everything else goes before the implicit regs.
     213             :   //
     214             :   // FIXME: Allow mixed explicit and implicit operands on inline asm.
     215             :   // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
     216             :   // implicit-defs, but they must not be moved around.  See the FIXME in
     217             :   // InstrEmitter.cpp.
     218    30327751 :   unsigned OpNo = getNumOperands();
     219    51401895 :   bool isImpReg = Op.isReg() && Op.isImplicit();
     220    23715773 :   if (!isImpReg && !isInlineAsm()) {
     221    84019935 :     while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
     222             :       --OpNo;
     223             :       assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
     224             :     }
     225             :   }
     226             : 
     227             : #ifndef NDEBUG
     228             :   bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
     229             :   // OpNo now points as the desired insertion point.  Unless this is a variadic
     230             :   // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
     231             :   // RegMask operands go between the explicit and implicit operands.
     232             :   assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
     233             :           OpNo < MCID->getNumOperands() || isMetaDataOp) &&
     234             :          "Trying to add an operand to a machine instr that is already done!");
     235             : #endif
     236             : 
     237    30327751 :   MachineRegisterInfo *MRI = getRegInfo();
     238             : 
     239             :   // Determine if the Operands array needs to be reallocated.
     240             :   // Save the old capacity and operand array.
     241    30327751 :   OperandCapacity OldCap = CapOperands;
     242    30327751 :   MachineOperand *OldOperands = Operands;
     243    60382952 :   if (!OldOperands || OldCap.getSize() == getNumOperands()) {
     244     3455224 :     CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
     245     1863887 :     Operands = MF.allocateOperandArray(CapOperands);
     246             :     // Move the operands before the insertion point.
     247     1863887 :     if (OpNo)
     248     1590146 :       moveOperands(Operands, OldOperands, OpNo, MRI);
     249             :   }
     250             : 
     251             :   // Move the operands following the insertion point.
     252    30327751 :   if (OpNo != NumOperands)
     253     5471603 :     moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
     254             :                  MRI);
     255    30327751 :   ++NumOperands;
     256             : 
     257             :   // Deallocate the old operand array.
     258    30327751 :   if (OldOperands != Operands && OldOperands)
     259             :     MF.deallocateOperandArray(OldCap, OldOperands);
     260             : 
     261             :   // Copy Op into place. It still needs to be inserted into the MRI use lists.
     262    30327751 :   MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
     263    30327751 :   NewMO->ParentMI = this;
     264             : 
     265             :   // When adding a register operand, tell MRI about it.
     266    30327751 :   if (NewMO->isReg()) {
     267             :     // Ensure isOnRegUseList() returns false, regardless of Op's status.
     268    21074144 :     NewMO->Contents.Reg.Prev = nullptr;
     269             :     // Ignore existing ties. This is not a property that can be copied.
     270    21074144 :     NewMO->TiedTo = 0;
     271             :     // Add the new operand to MRI, but only for instructions in an MBB.
     272    21074144 :     if (MRI)
     273     9315565 :       MRI->addRegOperandToUseList(NewMO);
     274             :     // The MCID operand information isn't accurate until we start adding
     275             :     // explicit operands. The implicit operands are added first, then the
     276             :     // explicits are inserted before them.
     277    21074144 :     if (!isImpReg) {
     278             :       // Tie uses to defs as indicated in MCInstrDesc.
     279    14462166 :       if (NewMO->isUse()) {
     280     9573902 :         int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
     281             :         if (DefIdx != -1)
     282      525077 :           tieOperands(DefIdx, OpNo);
     283             :       }
     284             :       // If the register operand is flagged as early, mark the operand as such.
     285    14462166 :       if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
     286             :         NewMO->setIsEarlyClobber(true);
     287             :     }
     288             :   }
     289             : }
     290             : 
     291             : /// RemoveOperand - Erase an operand  from an instruction, leaving it with one
     292             : /// fewer operand than it started with.
     293             : ///
     294      705221 : void MachineInstr::RemoveOperand(unsigned OpNo) {
     295             :   assert(OpNo < getNumOperands() && "Invalid operand number");
     296      705221 :   untieRegOperand(OpNo);
     297             : 
     298             : #ifndef NDEBUG
     299             :   // Moving tied operands would break the ties.
     300             :   for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
     301             :     if (Operands[i].isReg())
     302             :       assert(!Operands[i].isTied() && "Cannot move tied operands");
     303             : #endif
     304             : 
     305      705221 :   MachineRegisterInfo *MRI = getRegInfo();
     306     1410442 :   if (MRI && Operands[OpNo].isReg())
     307      645591 :     MRI->removeRegOperandFromUseList(Operands + OpNo);
     308             : 
     309             :   // Don't call the MachineOperand destructor. A lot of this code depends on
     310             :   // MachineOperand having a trivial destructor anyway, and adding a call here
     311             :   // wouldn't make it 'destructor-correct'.
     312             : 
     313      705221 :   if (unsigned N = NumOperands - 1 - OpNo)
     314      114082 :     moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
     315      705221 :   --NumOperands;
     316      705221 : }
     317             : 
     318             : /// addMemOperand - Add a MachineMemOperand to the machine instruction.
     319             : /// This function should be used only occasionally. The setMemRefs function
     320             : /// is the primary method for setting up a MachineInstr's MemRefs list.
     321      348417 : void MachineInstr::addMemOperand(MachineFunction &MF,
     322             :                                  MachineMemOperand *MO) {
     323      348417 :   mmo_iterator OldMemRefs = MemRefs;
     324      348417 :   unsigned OldNumMemRefs = NumMemRefs;
     325             : 
     326      348417 :   unsigned NewNum = NumMemRefs + 1;
     327      348417 :   mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
     328             : 
     329      348417 :   std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
     330      348417 :   NewMemRefs[NewNum - 1] = MO;
     331      348417 :   setMemRefs(NewMemRefs, NewMemRefs + NewNum);
     332      348417 : }
     333             : 
     334             : /// Check to see if the MMOs pointed to by the two MemRefs arrays are
     335             : /// identical.
     336       18952 : static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) {
     337       18952 :   auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end();
     338       18952 :   auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end();
     339       18952 :   if ((E1 - I1) != (E2 - I2))
     340             :     return false;
     341       51269 :   for (; I1 != E1; ++I1, ++I2) {
     342       44010 :     if (**I1 != **I2)
     343             :       return false;
     344             :   }
     345             :   return true;
     346             : }
     347             : 
     348             : std::pair<MachineInstr::mmo_iterator, unsigned>
     349       20720 : MachineInstr::mergeMemRefsWith(const MachineInstr& Other) {
     350             : 
     351             :   // If either of the incoming memrefs are empty, we must be conservative and
     352             :   // treat this as if we've exhausted our space for memrefs and dropped them.
     353       20720 :   if (memoperands_empty() || Other.memoperands_empty())
     354        1768 :     return std::make_pair(nullptr, 0);
     355             : 
     356             :   // If both instructions have identical memrefs, we don't need to merge them.
     357             :   // Since many instructions have a single memref, and we tend to merge things
     358             :   // like pairs of loads from the same location, this catches a large number of
     359             :   // cases in practice.
     360       18952 :   if (hasIdenticalMMOs(*this, Other))
     361       24612 :     return std::make_pair(MemRefs, NumMemRefs);
     362             : 
     363             :   // TODO: consider uniquing elements within the operand lists to reduce
     364             :   // space usage and fall back to conservative information less often.
     365        6646 :   size_t CombinedNumMemRefs = NumMemRefs + Other.NumMemRefs;
     366             : 
     367             :   // If we don't have enough room to store this many memrefs, be conservative
     368             :   // and drop them.  Otherwise, we'd fail asserts when trying to add them to
     369             :   // the new instruction.
     370        6646 :   if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs))
     371           0 :     return std::make_pair(nullptr, 0);
     372             : 
     373             :   MachineFunction *MF = getMF();
     374        6646 :   mmo_iterator MemBegin = MF->allocateMemRefsArray(CombinedNumMemRefs);
     375        6646 :   mmo_iterator MemEnd = std::copy(memoperands_begin(), memoperands_end(),
     376             :                                   MemBegin);
     377        6646 :   MemEnd = std::copy(Other.memoperands_begin(), Other.memoperands_end(),
     378             :                      MemEnd);
     379             :   assert(MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs &&
     380             :          "missing memrefs");
     381             : 
     382        6646 :   return std::make_pair(MemBegin, CombinedNumMemRefs);
     383             : }
     384             : 
     385        1086 : uint8_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
     386             :   // For now, the just return the union of the flags. If the flags get more
     387             :   // complicated over time, we might need more logic here.
     388        3258 :   return getFlags() | Other.getFlags();
     389             : }
     390             : 
     391      224390 : bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
     392             :   assert(!isBundledWithPred() && "Must be called on bundle header");
     393      224390 :   for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
     394      420059 :     if (MII->getDesc().getFlags() & Mask) {
     395       76274 :       if (Type == AnyInBundle)
     396             :         return true;
     397             :     } else {
     398      348215 :       if (Type == AllInBundle && !MII->isBundle())
     399             :         return false;
     400             :     }
     401             :     // This was the last instruction in the bundle.
     402      339442 :     if (!MII->isBundledWithSucc())
     403      143773 :       return Type == AllInBundle;
     404             :   }
     405             : }
     406             : 
     407     6344464 : bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
     408             :                                  MICheckType Check) const {
     409             :   // If opcodes or number of operands are not the same then the two
     410             :   // instructions are obviously not identical.
     411    23739227 :   if (Other.getOpcode() != getOpcode() ||
     412     4705835 :       Other.getNumOperands() != getNumOperands())
     413             :     return false;
     414             : 
     415     4694836 :   if (isBundle()) {
     416             :     // We have passed the test above that both instructions have the same
     417             :     // opcode, so we know that both instructions are bundles here. Let's compare
     418             :     // MIs inside the bundle.
     419             :     assert(Other.isBundle() && "Expected that both instructions are bundles.");
     420           1 :     MachineBasicBlock::const_instr_iterator I1 = getIterator();
     421           1 :     MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
     422             :     // Loop until we analysed the last intruction inside at least one of the
     423             :     // bundles.
     424           5 :     while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
     425             :       ++I1;
     426             :       ++I2;
     427           2 :       if (!I1->isIdenticalTo(*I2, Check))
     428             :         return false;
     429             :     }
     430             :     // If we've reached the end of just one of the two bundles, but not both,
     431             :     // the instructions are not identical.
     432           2 :     if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
     433             :       return false;
     434             :   }
     435             : 
     436             :   // Check operands to make sure they match.
     437    24407259 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     438    20898137 :     const MachineOperand &MO = getOperand(i);
     439    20898137 :     const MachineOperand &OMO = Other.getOperand(i);
     440    27090814 :     if (!MO.isReg()) {
     441     6998793 :       if (!MO.isIdenticalTo(OMO))
     442             :         return false;
     443     6192677 :       continue;
     444             :     }
     445             : 
     446             :     // Clients may or may not want to ignore defs when testing for equality.
     447             :     // For example, machine CSE pass only cares about finding common
     448             :     // subexpressions, so it's safe to ignore virtual register defs.
     449    13899344 :     if (MO.isDef()) {
     450     6162531 :       if (Check == IgnoreDefs)
     451           0 :         continue;
     452     6162531 :       else if (Check == IgnoreVRegDefs) {
     453    12406262 :         if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()) ||
     454     2447536 :             !TargetRegisterInfo::isVirtualRegister(OMO.getReg()))
     455     2532059 :           if (!MO.isIdenticalTo(OMO))
     456             :             return false;
     457             :       } else {
     458     1183168 :         if (!MO.isIdenticalTo(OMO))
     459             :           return false;
     460     1183400 :         if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
     461             :           return false;
     462             :       }
     463             :     } else {
     464     7736813 :       if (!MO.isIdenticalTo(OMO))
     465             :         return false;
     466     7378123 :       if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
     467             :         return false;
     468             :     }
     469             :   }
     470             :   // If DebugLoc does not match then two debug instructions are not identical.
     471             :   if (isDebugInstr())
     472        4350 :     if (getDebugLoc() && Other.getDebugLoc() &&
     473             :         getDebugLoc() != Other.getDebugLoc())
     474             :       return false;
     475             :   return true;
     476             : }
     477             : 
     478    18080499 : const MachineFunction *MachineInstr::getMF() const {
     479    18080499 :   return getParent()->getParent();
     480             : }
     481             : 
     482        3505 : MachineInstr *MachineInstr::removeFromParent() {
     483             :   assert(getParent() && "Not embedded in a basic block!");
     484        7010 :   return getParent()->remove(this);
     485             : }
     486             : 
     487          81 : MachineInstr *MachineInstr::removeFromBundle() {
     488             :   assert(getParent() && "Not embedded in a basic block!");
     489          81 :   return getParent()->remove_instr(this);
     490             : }
     491             : 
     492     2267602 : void MachineInstr::eraseFromParent() {
     493             :   assert(getParent() && "Not embedded in a basic block!");
     494     2267602 :   getParent()->erase(this);
     495     2267602 : }
     496             : 
     497      183969 : void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
     498             :   assert(getParent() && "Not embedded in a basic block!");
     499      183969 :   MachineBasicBlock *MBB = getParent();
     500      183969 :   MachineFunction *MF = MBB->getParent();
     501             :   assert(MF && "Not embedded in a function!");
     502             : 
     503             :   MachineInstr *MI = (MachineInstr *)this;
     504      183969 :   MachineRegisterInfo &MRI = MF->getRegInfo();
     505             : 
     506      988313 :   for (const MachineOperand &MO : MI->operands()) {
     507      747655 :     if (!MO.isReg() || !MO.isDef())
     508      215253 :       continue;
     509      186919 :     unsigned Reg = MO.getReg();
     510      186919 :     if (!TargetRegisterInfo::isVirtualRegister(Reg))
     511        2778 :       continue;
     512      184141 :     MRI.markUsesInDebugValueAsUndef(Reg);
     513             :   }
     514      183969 :   MI->eraseFromParent();
     515      183969 : }
     516             : 
     517      629055 : void MachineInstr::eraseFromBundle() {
     518             :   assert(getParent() && "Not embedded in a basic block!");
     519      629055 :   getParent()->erase_instr(this);
     520      629055 : }
     521             : 
     522    16278435 : unsigned MachineInstr::getNumExplicitOperands() const {
     523    16278435 :   unsigned NumOperands = MCID->getNumOperands();
     524    32556870 :   if (!MCID->isVariadic())
     525             :     return NumOperands;
     526             : 
     527        7951 :   for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
     528        6877 :     const MachineOperand &MO = getOperand(I);
     529             :     // The operands must always be in the following order:
     530             :     // - explicit reg defs,
     531             :     // - other explicit operands (reg uses, immediates, etc.),
     532             :     // - implicit reg defs
     533             :     // - implicit reg uses
     534       10778 :     if (MO.isReg() && MO.isImplicit())
     535             :       break;
     536        6074 :     ++NumOperands;
     537             :   }
     538             :   return NumOperands;
     539             : }
     540             : 
     541     2417159 : unsigned MachineInstr::getNumExplicitDefs() const {
     542     2417159 :   unsigned NumDefs = MCID->getNumDefs();
     543     4834318 :   if (!MCID->isVariadic())
     544             :     return NumDefs;
     545             : 
     546      345715 :   for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
     547      345715 :     const MachineOperand &MO = getOperand(I);
     548      688442 :     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
     549             :       break;
     550        1012 :     ++NumDefs;
     551             :   }
     552             :   return NumDefs;
     553             : }
     554             : 
     555       54506 : void MachineInstr::bundleWithPred() {
     556             :   assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
     557             :   setFlag(BundledPred);
     558       54506 :   MachineBasicBlock::instr_iterator Pred = getIterator();
     559             :   --Pred;
     560             :   assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
     561             :   Pred->setFlag(BundledSucc);
     562       54506 : }
     563             : 
     564       24046 : void MachineInstr::bundleWithSucc() {
     565             :   assert(!isBundledWithSucc() && "MI is already bundled with its successor");
     566             :   setFlag(BundledSucc);
     567       24046 :   MachineBasicBlock::instr_iterator Succ = getIterator();
     568             :   ++Succ;
     569             :   assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
     570             :   Succ->setFlag(BundledPred);
     571       24046 : }
     572             : 
     573       39525 : void MachineInstr::unbundleFromPred() {
     574             :   assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
     575             :   clearFlag(BundledPred);
     576       39525 :   MachineBasicBlock::instr_iterator Pred = getIterator();
     577             :   --Pred;
     578             :   assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
     579             :   Pred->clearFlag(BundledSucc);
     580       39525 : }
     581             : 
     582         149 : void MachineInstr::unbundleFromSucc() {
     583             :   assert(isBundledWithSucc() && "MI isn't bundled with its successor");
     584             :   clearFlag(BundledSucc);
     585         149 :   MachineBasicBlock::instr_iterator Succ = getIterator();
     586             :   ++Succ;
     587             :   assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
     588             :   Succ->clearFlag(BundledPred);
     589         149 : }
     590             : 
     591     4998222 : bool MachineInstr::isStackAligningInlineAsm() const {
     592     4998222 :   if (isInlineAsm()) {
     593       16270 :     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
     594       16270 :     if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
     595             :       return true;
     596             :   }
     597             :   return false;
     598             : }
     599             : 
     600       23692 : InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
     601             :   assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
     602       23692 :   unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
     603       23692 :   return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
     604             : }
     605             : 
     606         276 : int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
     607             :                                        unsigned *GroupNo) const {
     608             :   assert(isInlineAsm() && "Expected an inline asm instruction");
     609             :   assert(OpIdx < getNumOperands() && "OpIdx out of range");
     610             : 
     611             :   // Ignore queries about the initial operands.
     612         276 :   if (OpIdx < InlineAsm::MIOp_FirstOperand)
     613             :     return -1;
     614             : 
     615             :   unsigned Group = 0;
     616             :   unsigned NumOps;
     617         588 :   for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
     618             :        i += NumOps) {
     619         588 :     const MachineOperand &FlagMO = getOperand(i);
     620             :     // If we reach the implicit register operands, stop looking.
     621         588 :     if (!FlagMO.isImm())
     622             :       return -1;
     623        1176 :     NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
     624         588 :     if (i + NumOps > OpIdx) {
     625         276 :       if (GroupNo)
     626           0 :         *GroupNo = Group;
     627         276 :       return i;
     628             :     }
     629         312 :     ++Group;
     630             :   }
     631             :   return -1;
     632             : }
     633             : 
     634           0 : const DILabel *MachineInstr::getDebugLabel() const {
     635             :   assert(isDebugLabel() && "not a DBG_LABEL");
     636           0 :   return cast<DILabel>(getOperand(0).getMetadata());
     637             : }
     638             : 
     639      324734 : const DILocalVariable *MachineInstr::getDebugVariable() const {
     640             :   assert(isDebugValue() && "not a DBG_VALUE");
     641      324734 :   return cast<DILocalVariable>(getOperand(2).getMetadata());
     642             : }
     643             : 
     644      218938 : const DIExpression *MachineInstr::getDebugExpression() const {
     645             :   assert(isDebugValue() && "not a DBG_VALUE");
     646      218938 :   return cast<DIExpression>(getOperand(3).getMetadata());
     647             : }
     648             : 
     649             : const TargetRegisterClass*
     650      119730 : MachineInstr::getRegClassConstraint(unsigned OpIdx,
     651             :                                     const TargetInstrInfo *TII,
     652             :                                     const TargetRegisterInfo *TRI) const {
     653             :   assert(getParent() && "Can't have an MBB reference here!");
     654             :   assert(getMF() && "Can't have an MF reference here!");
     655      119730 :   const MachineFunction &MF = *getMF();
     656             : 
     657             :   // Most opcodes have fixed constraints in their MCInstrDesc.
     658      119730 :   if (!isInlineAsm())
     659      119454 :     return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
     660             : 
     661         552 :   if (!getOperand(OpIdx).isReg())
     662             :     return nullptr;
     663             : 
     664             :   // For tied uses on inline asm, get the constraint from the def.
     665             :   unsigned DefIdx;
     666         276 :   if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
     667           1 :     OpIdx = DefIdx;
     668             : 
     669             :   // Inline asm stores register class constraints in the flag word.
     670         276 :   int FlagIdx = findInlineAsmFlagIdx(OpIdx);
     671         276 :   if (FlagIdx < 0)
     672             :     return nullptr;
     673             : 
     674         552 :   unsigned Flag = getOperand(FlagIdx).getImm();
     675             :   unsigned RCID;
     676          18 :   if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
     677           5 :        InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
     678         276 :        InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
     679             :       InlineAsm::hasRegClassConstraint(Flag, RCID))
     680         546 :     return TRI->getRegClass(RCID);
     681             : 
     682             :   // Assume that all registers in a memory operand are pointers.
     683           3 :   if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
     684           3 :     return TRI->getPointerRegClass(MF);
     685             : 
     686             :   return nullptr;
     687             : }
     688             : 
     689          50 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
     690             :     unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
     691             :     const TargetRegisterInfo *TRI, bool ExploreBundle) const {
     692             :   // Check every operands inside the bundle if we have
     693             :   // been asked to.
     694          50 :   if (ExploreBundle)
     695         349 :     for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
     696             :          ++OpndIt)
     697         598 :       CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
     698             :           OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
     699             :   else
     700             :     // Otherwise, just check the current operands.
     701           0 :     for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
     702           0 :       CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
     703          50 :   return CurRC;
     704             : }
     705             : 
     706         299 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
     707             :     unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
     708             :     const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
     709             :   assert(CurRC && "Invalid initial register class");
     710             :   // Check if Reg is constrained by some of its use/def from MI.
     711         299 :   const MachineOperand &MO = getOperand(OpIdx);
     712         299 :   if (!MO.isReg() || MO.getReg() != Reg)
     713             :     return CurRC;
     714             :   // If yes, accumulate the constraints through the operand.
     715          52 :   return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
     716             : }
     717             : 
     718       53373 : const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
     719             :     unsigned OpIdx, const TargetRegisterClass *CurRC,
     720             :     const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
     721       53373 :   const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
     722       53373 :   const MachineOperand &MO = getOperand(OpIdx);
     723             :   assert(MO.isReg() &&
     724             :          "Cannot get register constraints for non-register operand");
     725             :   assert(CurRC && "Invalid initial register class");
     726       53373 :   if (unsigned SubIdx = MO.getSubReg()) {
     727       22512 :     if (OpRC)
     728       19500 :       CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
     729             :     else
     730        3012 :       CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
     731       30861 :   } else if (OpRC)
     732       20902 :     CurRC = TRI->getCommonSubClass(CurRC, OpRC);
     733       53373 :   return CurRC;
     734             : }
     735             : 
     736             : /// Return the number of instructions inside the MI bundle, not counting the
     737             : /// header instruction.
     738        1227 : unsigned MachineInstr::getBundleSize() const {
     739        1227 :   MachineBasicBlock::const_instr_iterator I = getIterator();
     740             :   unsigned Size = 0;
     741        4286 :   while (I->isBundledWithSucc()) {
     742        3059 :     ++Size;
     743             :     ++I;
     744             :   }
     745        1227 :   return Size;
     746             : }
     747             : 
     748             : /// Returns true if the MachineInstr has an implicit-use operand of exactly
     749             : /// the given register (not considering sub/super-registers).
     750     5948294 : bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const {
     751    33521661 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     752    33521659 :     const MachineOperand &MO = getOperand(i);
     753    69976653 :     if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
     754             :       return true;
     755             :   }
     756             :   return false;
     757             : }
     758             : 
     759             : /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
     760             : /// the specific register or -1 if it is not found. It further tightens
     761             : /// the search criteria to a use that kills the register if isKill is true.
     762     2332890 : int MachineInstr::findRegisterUseOperandIdx(
     763             :     unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
     764    13442788 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     765    12014697 :     const MachineOperand &MO = getOperand(i);
     766    19592702 :     if (!MO.isReg() || !MO.isUse())
     767     7943652 :       continue;
     768     4071045 :     unsigned MOReg = MO.getReg();
     769     4071045 :     if (!MOReg)
     770      516473 :       continue;
     771     5035747 :     if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
     772      508764 :                          TargetRegisterInfo::isPhysicalRegister(Reg) &&
     773      508764 :                          TRI->isSubRegister(MOReg, Reg)))
     774     1365897 :       if (!isKill || MO.isKill())
     775      904799 :         return i;
     776             :   }
     777             :   return -1;
     778             : }
     779             : 
     780             : /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
     781             : /// indicating if this instruction reads or writes Reg. This also considers
     782             : /// partial defines.
     783             : std::pair<bool,bool>
     784     5587361 : MachineInstr::readsWritesVirtualRegister(unsigned Reg,
     785             :                                          SmallVectorImpl<unsigned> *Ops) const {
     786             :   bool PartDef = false; // Partial redefine.
     787             :   bool FullDef = false; // Full define.
     788             :   bool Use = false;
     789             : 
     790    29033082 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     791    23445721 :     const MachineOperand &MO = getOperand(i);
     792    23445721 :     if (!MO.isReg() || MO.getReg() != Reg)
     793    17473395 :       continue;
     794     5972326 :     if (Ops)
     795     1040525 :       Ops->push_back(i);
     796     5972326 :     if (MO.isUse())
     797     3485974 :       Use |= !MO.isUndef();
     798     2743615 :     else if (MO.getSubReg() && !MO.isUndef())
     799             :       // A partial def undef doesn't count as reading the register.
     800             :       PartDef = true;
     801             :     else
     802             :       FullDef = true;
     803             :   }
     804             :   // A partial redefine uses Reg unless there is also a full define.
     805    11174722 :   return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
     806             : }
     807             : 
     808             : /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
     809             : /// the specified register or -1 if it is not found. If isDead is true, defs
     810             : /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
     811             : /// also checks if there is a def of a super-register.
     812             : int
     813     8612962 : MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
     814             :                                         const TargetRegisterInfo *TRI) const {
     815             :   bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
     816    43756491 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     817    37329093 :     const MachineOperand &MO = getOperand(i);
     818             :     // Accept regmask operands when Overlap is set.
     819             :     // Ignore them when looking for a specific def operand (Overlap == false).
     820    55489897 :     if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
     821        1786 :       return i;
     822    90851993 :     if (!MO.isReg() || !MO.isDef())
     823    28036532 :       continue;
     824     9290775 :     unsigned MOReg = MO.getReg();
     825     9290775 :     bool Found = (MOReg == Reg);
     826    18216460 :     if (!Found && TRI && isPhys &&
     827             :         TargetRegisterInfo::isPhysicalRegister(MOReg)) {
     828     2774566 :       if (Overlap)
     829     2333980 :         Found = TRI->regsOverlap(MOReg, Reg);
     830             :       else
     831      440586 :         Found = TRI->isSubRegister(MOReg, Reg);
     832             :     }
     833    10557517 :     if (Found && (!isDead || MO.isDead()))
     834     2183778 :       return i;
     835             :   }
     836             :   return -1;
     837             : }
     838             : 
     839             : /// findFirstPredOperandIdx() - Find the index of the first operand in the
     840             : /// operand list that is used to represent the predicate. It returns -1 if
     841             : /// none is found.
     842     1144493 : int MachineInstr::findFirstPredOperandIdx() const {
     843             :   // Don't call MCID.findFirstPredOperandIdx() because this variant
     844             :   // is sometimes called on an instruction that's not yet complete, and
     845             :   // so the number of operands is less than the MCID indicates. In
     846             :   // particular, the PTX target does this.
     847     1144493 :   const MCInstrDesc &MCID = getDesc();
     848     2288986 :   if (MCID.isPredicable()) {
     849     3656332 :     for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
     850     3622225 :       if (MCID.OpInfo[i].isPredicate())
     851      998216 :         return i;
     852             :   }
     853             : 
     854             :   return -1;
     855             : }
     856             : 
     857             : // MachineOperand::TiedTo is 4 bits wide.
     858             : const unsigned TiedMax = 15;
     859             : 
     860             : /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
     861             : ///
     862             : /// Use and def operands can be tied together, indicated by a non-zero TiedTo
     863             : /// field. TiedTo can have these values:
     864             : ///
     865             : /// 0:              Operand is not tied to anything.
     866             : /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
     867             : /// TiedMax:        Tied to an operand >= TiedMax-1.
     868             : ///
     869             : /// The tied def must be one of the first TiedMax operands on a normal
     870             : /// instruction. INLINEASM instructions allow more tied defs.
     871             : ///
     872      526409 : void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
     873      526409 :   MachineOperand &DefMO = getOperand(DefIdx);
     874             :   MachineOperand &UseMO = getOperand(UseIdx);
     875             :   assert(DefMO.isDef() && "DefIdx must be a def operand");
     876             :   assert(UseMO.isUse() && "UseIdx must be a use operand");
     877             :   assert(!DefMO.isTied() && "Def is already tied to another use");
     878             :   assert(!UseMO.isTied() && "Use is already tied to another def");
     879             : 
     880      526409 :   if (DefIdx < TiedMax)
     881      526326 :     UseMO.TiedTo = DefIdx + 1;
     882             :   else {
     883             :     // Inline asm can use the group descriptors to find tied operands, but on
     884             :     // normal instruction, the tied def must be within the first TiedMax
     885             :     // operands.
     886             :     assert(isInlineAsm() && "DefIdx out of range");
     887          83 :     UseMO.TiedTo = TiedMax;
     888             :   }
     889             : 
     890             :   // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
     891     1052818 :   DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
     892      526409 : }
     893             : 
     894             : /// Given the index of a tied register operand, find the operand it is tied to.
     895             : /// Defs are tied to uses and vice versa. Returns the index of the tied operand
     896             : /// which must exist.
     897     4478105 : unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
     898     4478105 :   const MachineOperand &MO = getOperand(OpIdx);
     899             :   assert(MO.isTied() && "Operand isn't tied");
     900             : 
     901             :   // Normally TiedTo is in range.
     902     4478105 :   if (MO.TiedTo < TiedMax)
     903     4461560 :     return MO.TiedTo - 1;
     904             : 
     905             :   // Uses on normal instructions can be out of range.
     906       16545 :   if (!isInlineAsm()) {
     907             :     // Normal tied defs must be in the 0..TiedMax-1 range.
     908           0 :     if (MO.isUse())
     909             :       return TiedMax - 1;
     910             :     // MO is a def. Search for the tied use.
     911           0 :     for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
     912             :       const MachineOperand &UseMO = getOperand(i);
     913           0 :       if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
     914             :         return i;
     915             :     }
     916           0 :     llvm_unreachable("Can't find tied use");
     917             :   }
     918             : 
     919             :   // Now deal with inline asm by parsing the operand group descriptor flags.
     920             :   // Find the beginning of each operand group.
     921             :   SmallVector<unsigned, 8> GroupIdx;
     922             :   unsigned OpIdxGroup = ~0u;
     923             :   unsigned NumOps;
     924     1477964 :   for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
     925     1461419 :        i += NumOps) {
     926     1477964 :     const MachineOperand &FlagMO = getOperand(i);
     927             :     assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
     928     1477964 :     unsigned CurGroup = GroupIdx.size();
     929     1477964 :     GroupIdx.push_back(i);
     930     2955928 :     NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
     931             :     // OpIdx belongs to this operand group.
     932     1477964 :     if (OpIdx > i && OpIdx < i + NumOps)
     933             :       OpIdxGroup = CurGroup;
     934             :     unsigned TiedGroup;
     935     1477964 :     if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
     936             :       continue;
     937             :     // Operands in this group are tied to operands in TiedGroup which must be
     938             :     // earlier. Find the number of operands between the two groups.
     939     1031938 :     unsigned Delta = i - GroupIdx[TiedGroup];
     940             : 
     941             :     // OpIdx is a use tied to TiedGroup.
     942      515969 :     if (OpIdxGroup == CurGroup)
     943        8869 :       return OpIdx - Delta;
     944             : 
     945             :     // OpIdx is a def tied to this use group.
     946      507100 :     if (OpIdxGroup == TiedGroup)
     947        7676 :       return OpIdx + Delta;
     948             :   }
     949           0 :   llvm_unreachable("Invalid tied operand on inline asm");
     950             : }
     951             : 
     952             : /// clearKillInfo - Clears kill flags on all operands.
     953             : ///
     954       35160 : void MachineInstr::clearKillInfo() {
     955      260134 :   for (MachineOperand &MO : operands()) {
     956      196912 :     if (MO.isReg() && MO.isUse())
     957             :       MO.setIsKill(false);
     958             :   }
     959       35160 : }
     960             : 
     961       94118 : void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
     962             :                                       unsigned SubIdx,
     963             :                                       const TargetRegisterInfo &RegInfo) {
     964       94118 :   if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
     965       28677 :     if (SubIdx)
     966           0 :       ToReg = RegInfo.getSubReg(ToReg, SubIdx);
     967      158511 :     for (MachineOperand &MO : operands()) {
     968       64917 :       if (!MO.isReg() || MO.getReg() != FromReg)
     969       36240 :         continue;
     970       28677 :       MO.substPhysReg(ToReg, RegInfo);
     971             :     }
     972             :   } else {
     973      558133 :     for (MachineOperand &MO : operands()) {
     974      427251 :       if (!MO.isReg() || MO.getReg() != FromReg)
     975      180905 :         continue;
     976       65441 :       MO.substVirtReg(ToReg, SubIdx, RegInfo);
     977             :     }
     978             :   }
     979       94118 : }
     980             : 
     981             : /// isSafeToMove - Return true if it is safe to move this instruction. If
     982             : /// SawStore is set to true, it means that there is a store (or call) between
     983             : /// the instruction's location and its intended destination.
     984    15743294 : bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
     985             :   // Ignore stuff that we obviously can't move.
     986             :   //
     987             :   // Treat volatile loads as stores. This is not strictly necessary for
     988             :   // volatiles, but it is required for atomic loads. It is not allowed to move
     989             :   // a load across an atomic load with Ordering > Monotonic.
     990    41806152 :   if (mayStore() || isCall() || isPHI() ||
     991    13981803 :       (mayLoad() && hasOrderedMemoryRef())) {
     992     3166506 :     SawStore = true;
     993     3166506 :     return false;
     994             :   }
     995             : 
     996    22943659 :   if (isPosition() || isDebugInstr() || isTerminator() ||
     997    10840944 :       hasUnmodeledSideEffects())
     998             :     return false;
     999             : 
    1000             :   // See if this instruction does a load.  If so, we have to guarantee that the
    1001             :   // loaded value doesn't change between the load and the its intended
    1002             :   // destination. The check for isInvariantLoad gives the targe the chance to
    1003             :   // classify the load as always returning a constant, e.g. a constant pool
    1004             :   // load.
    1005    10755354 :   if (mayLoad() && !isDereferenceableInvariantLoad(AA))
    1006             :     // Otherwise, this is a real load.  If there is a store between the load and
    1007             :     // end of block, we can't move it.
    1008      914250 :     return !SawStore;
    1009             : 
    1010             :   return true;
    1011             : }
    1012             : 
    1013     3289772 : bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
    1014             :                             bool UseTBAA) {
    1015             :   const MachineFunction *MF = getMF();
    1016     3289772 :   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
    1017     3289772 :   const MachineFrameInfo &MFI = MF->getFrameInfo();
    1018             : 
    1019             :   // If neither instruction stores to memory, they can't alias in any
    1020             :   // meaningful way, even if they read from the same address.
    1021     3289772 :   if (!mayStore() && !Other.mayStore())
    1022             :     return false;
    1023             : 
    1024             :   // Let the target decide if memory accesses cannot possibly overlap.
    1025     3289772 :   if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
    1026             :     return false;
    1027             : 
    1028             :   // FIXME: Need to handle multiple memory operands to support all targets.
    1029     3234934 :   if (!hasOneMemOperand() || !Other.hasOneMemOperand())
    1030             :     return true;
    1031             : 
    1032     2198066 :   MachineMemOperand *MMOa = *memoperands_begin();
    1033     2198066 :   MachineMemOperand *MMOb = *Other.memoperands_begin();
    1034             : 
    1035             :   // The following interface to AA is fashioned after DAGCombiner::isAlias
    1036             :   // and operates with MachineMemOperand offset with some important
    1037             :   // assumptions:
    1038             :   //   - LLVM fundamentally assumes flat address spaces.
    1039             :   //   - MachineOperand offset can *only* result from legalization and
    1040             :   //     cannot affect queries other than the trivial case of overlap
    1041             :   //     checking.
    1042             :   //   - These offsets never wrap and never step outside
    1043             :   //     of allocated objects.
    1044             :   //   - There should never be any negative offsets here.
    1045             :   //
    1046             :   // FIXME: Modify API to hide this math from "user"
    1047             :   // Even before we go to AA we can reason locally about some
    1048             :   // memory objects. It can save compile time, and possibly catch some
    1049             :   // corner cases not currently covered.
    1050             : 
    1051     2198066 :   int64_t OffsetA = MMOa->getOffset();
    1052     2198066 :   int64_t OffsetB = MMOb->getOffset();
    1053             : 
    1054     2198066 :   int64_t MinOffset = std::min(OffsetA, OffsetB);
    1055     2198066 :   int64_t WidthA = MMOa->getSize();
    1056     2198066 :   int64_t WidthB = MMOb->getSize();
    1057             :   const Value *ValA = MMOa->getValue();
    1058             :   const Value *ValB = MMOb->getValue();
    1059     2198066 :   bool SameVal = (ValA && ValB && (ValA == ValB));
    1060             :   if (!SameVal) {
    1061             :     const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
    1062             :     const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
    1063     1713949 :     if (PSVa && ValB && !PSVa->mayAlias(&MFI))
    1064             :       return false;
    1065     1702268 :     if (PSVb && ValA && !PSVb->mayAlias(&MFI))
    1066             :       return false;
    1067     1690964 :     if (PSVa && PSVb && (PSVa == PSVb))
    1068             :       SameVal = true;
    1069             :   }
    1070             : 
    1071     1152969 :   if (SameVal) {
    1072     1506229 :     int64_t MaxOffset = std::max(OffsetA, OffsetB);
    1073     1506229 :     int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
    1074     1506229 :     return (MinOffset + LowWidth > MaxOffset);
    1075             :   }
    1076             : 
    1077      668852 :   if (!AA)
    1078             :     return true;
    1079             : 
    1080       30652 :   if (!ValA || !ValB)
    1081             :     return true;
    1082             : 
    1083             :   assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
    1084             :   assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
    1085             : 
    1086       18215 :   int64_t Overlapa = WidthA + OffsetA - MinOffset;
    1087       18215 :   int64_t Overlapb = WidthB + OffsetB - MinOffset;
    1088             : 
    1089             :   AliasResult AAResult = AA->alias(
    1090       36430 :       MemoryLocation(ValA, Overlapa,
    1091       18215 :                      UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
    1092       36430 :       MemoryLocation(ValB, Overlapb,
    1093       36430 :                      UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
    1094             : 
    1095       18215 :   return (AAResult != NoAlias);
    1096             : }
    1097             : 
    1098             : /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
    1099             : /// or volatile memory reference, or if the information describing the memory
    1100             : /// reference is not available. Return false if it is known to have no ordered
    1101             : /// memory references.
    1102     7274612 : bool MachineInstr::hasOrderedMemoryRef() const {
    1103             :   // An instruction known never to access memory won't have a volatile access.
    1104    12210700 :   if (!mayStore() &&
    1105     7432675 :       !mayLoad() &&
    1106     9769765 :       !isCall() &&
    1107     2495153 :       !hasUnmodeledSideEffects())
    1108             :     return false;
    1109             : 
    1110             :   // Otherwise, if the instruction has no memory reference information,
    1111             :   // conservatively assume it wasn't preserved.
    1112     4785389 :   if (memoperands_empty())
    1113             :     return true;
    1114             : 
    1115             :   // Check if any of our memory operands are ordered.
    1116             :   return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
    1117             :     return !MMO->isUnordered();
    1118             :   });
    1119             : }
    1120             : 
    1121             : /// isDereferenceableInvariantLoad - Return true if this instruction will never
    1122             : /// trap and is loading from a location whose value is invariant across a run of
    1123             : /// this function.
    1124     2603181 : bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
    1125             :   // If the instruction doesn't load at all, it isn't an invariant load.
    1126     2603181 :   if (!mayLoad())
    1127             :     return false;
    1128             : 
    1129             :   // If the instruction has lost its memoperands, conservatively assume that
    1130             :   // it may not be an invariant load.
    1131     2271251 :   if (memoperands_empty())
    1132             :     return false;
    1133             : 
    1134     2248823 :   const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
    1135             : 
    1136     3508375 :   for (MachineMemOperand *MMO : memoperands()) {
    1137     4497802 :     if (MMO->isVolatile()) return false;
    1138     2211987 :     if (MMO->isStore()) return false;
    1139     2441776 :     if (MMO->isInvariant() && MMO->isDereferenceable())
    1140      257558 :       continue;
    1141             : 
    1142             :     // A load from a constant PseudoSourceValue is invariant.
    1143      459472 :     if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
    1144      459472 :       if (PSV->isConstant(&MFI))
    1145      363754 :         continue;
    1146             : 
    1147     1466336 :     if (const Value *V = MMO->getValue()) {
    1148             :       // If we have an AliasAnalysis, ask it whether the memory is constant.
    1149     2265004 :       if (AA &&
    1150      807027 :           AA->pointsToConstantMemory(
    1151     2248076 :               MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
    1152        8464 :         continue;
    1153             :     }
    1154             : 
    1155             :     // Otherwise assume conservatively.
    1156             :     return false;
    1157             :   }
    1158             : 
    1159             :   // Everything checks out.
    1160             :   return true;
    1161             : }
    1162             : 
    1163             : /// isConstantValuePHI - If the specified instruction is a PHI that always
    1164             : /// merges together the same virtual register, return the register, otherwise
    1165             : /// return 0.
    1166          23 : unsigned MachineInstr::isConstantValuePHI() const {
    1167             :   if (!isPHI())
    1168             :     return 0;
    1169             :   assert(getNumOperands() >= 3 &&
    1170             :          "It's illegal to have a PHI without source operands");
    1171             : 
    1172          23 :   unsigned Reg = getOperand(1).getReg();
    1173          23 :   for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
    1174          23 :     if (getOperand(i).getReg() != Reg)
    1175             :       return 0;
    1176             :   return Reg;
    1177             : }
    1178             : 
    1179    29437013 : bool MachineInstr::hasUnmodeledSideEffects() const {
    1180    29437013 :   if (hasProperty(MCID::UnmodeledSideEffects))
    1181             :     return true;
    1182    29170233 :   if (isInlineAsm()) {
    1183       37452 :     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    1184       37452 :     if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
    1185             :       return true;
    1186             :   }
    1187             : 
    1188             :   return false;
    1189             : }
    1190             : 
    1191     3804134 : bool MachineInstr::isLoadFoldBarrier() const {
    1192     7055438 :   return mayStore() || isCall() || hasUnmodeledSideEffects();
    1193             : }
    1194             : 
    1195             : /// allDefsAreDead - Return true if all the defs of this instruction are dead.
    1196             : ///
    1197      996398 : bool MachineInstr::allDefsAreDead() const {
    1198     1260070 :   for (const MachineOperand &MO : operands()) {
    1199     2113660 :     if (!MO.isReg() || MO.isUse())
    1200       73104 :       continue;
    1201     1003644 :     if (!MO.isDead())
    1202             :       return false;
    1203             :   }
    1204             :   return true;
    1205             : }
    1206             : 
    1207             : /// copyImplicitOps - Copy implicit register operands from specified
    1208             : /// instruction to this instruction.
    1209       13407 : void MachineInstr::copyImplicitOps(MachineFunction &MF,
    1210             :                                    const MachineInstr &MI) {
    1211       43692 :   for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
    1212       30285 :        i != e; ++i) {
    1213       16878 :     const MachineOperand &MO = MI.getOperand(i);
    1214       31684 :     if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
    1215       16878 :       addOperand(MF, MO);
    1216             :   }
    1217       13407 : }
    1218             : 
    1219       90199 : bool MachineInstr::hasComplexRegisterTies() const {
    1220       90199 :   const MCInstrDesc &MCID = getDesc();
    1221      366848 :   for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
    1222      276656 :     const auto &Operand = getOperand(I);
    1223      454710 :     if (!Operand.isReg() || Operand.isDef())
    1224             :       // Ignore the defined registers as MCID marks only the uses as tied.
    1225      178143 :       continue;
    1226       98513 :     int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
    1227       98513 :     int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
    1228       98513 :     if (ExpectedTiedIdx != TiedIdx)
    1229             :       return true;
    1230             :   }
    1231             :   return false;
    1232             : }
    1233             : 
    1234      276639 : LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
    1235             :                                  const MachineRegisterInfo &MRI) const {
    1236      276639 :   const MachineOperand &Op = getOperand(OpIdx);
    1237      276639 :   if (!Op.isReg())
    1238       98584 :     return LLT{};
    1239             : 
    1240      178055 :   if (isVariadic() || OpIdx >= getNumExplicitOperands())
    1241       69335 :     return MRI.getType(Op.getReg());
    1242             : 
    1243      108720 :   auto &OpInfo = getDesc().OpInfo[OpIdx];
    1244      217440 :   if (!OpInfo.isGenericType())
    1245       98488 :     return MRI.getType(Op.getReg());
    1246             : 
    1247       10232 :   if (PrintedTypes[OpInfo.getGenericTypeIndex()])
    1248        2588 :     return LLT{};
    1249             : 
    1250        7644 :   LLT TypeToPrint = MRI.getType(Op.getReg());
    1251             :   // Don't mark the type index printed if it wasn't actually printed: maybe
    1252             :   // another operand with the same type index has an actual type attached:
    1253        7644 :   if (TypeToPrint.isValid())
    1254        7624 :     PrintedTypes.set(OpInfo.getGenericTypeIndex());
    1255        7644 :   return TypeToPrint;
    1256             : }
    1257             : 
    1258             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
    1259             : LLVM_DUMP_METHOD void MachineInstr::dump() const {
    1260             :   dbgs() << "  ";
    1261             :   print(dbgs());
    1262             : }
    1263             : #endif
    1264             : 
    1265         127 : void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
    1266             :                          bool SkipDebugLoc, bool AddNewLine,
    1267             :                          const TargetInstrInfo *TII) const {
    1268             :   const Module *M = nullptr;
    1269             :   const Function *F = nullptr;
    1270             :   if (const MachineFunction *MF = getMFIfAvailable(*this)) {
    1271         126 :     F = &MF->getFunction();
    1272         126 :     M = F->getParent();
    1273         126 :     if (!TII)
    1274         126 :       TII = MF->getSubtarget().getInstrInfo();
    1275             :   }
    1276             : 
    1277         254 :   ModuleSlotTracker MST(M);
    1278         127 :   if (F)
    1279         126 :     MST.incorporateFunction(*F);
    1280         127 :   print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, TII);
    1281         127 : }
    1282             : 
    1283       54709 : void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
    1284             :                          bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
    1285             :                          bool AddNewLine, const TargetInstrInfo *TII) const {
    1286             :   // We can be a bit tidier if we know the MachineFunction.
    1287             :   const MachineFunction *MF = nullptr;
    1288       54709 :   const TargetRegisterInfo *TRI = nullptr;
    1289       54709 :   const MachineRegisterInfo *MRI = nullptr;
    1290       54709 :   const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
    1291       54709 :   tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
    1292             : 
    1293             :   if (isCFIInstruction())
    1294             :     assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
    1295             : 
    1296       54685 :   SmallBitVector PrintedTypes(8);
    1297       54709 :   bool ShouldPrintRegisterTies = hasComplexRegisterTies();
    1298      169807 :   auto getTiedOperandIdx = [&](unsigned OpIdx) {
    1299      169807 :     if (!ShouldPrintRegisterTies)
    1300             :       return 0U;
    1301           0 :     const MachineOperand &MO = getOperand(OpIdx);
    1302           0 :     if (MO.isReg() && MO.isTied() && !MO.isDef())
    1303           0 :       return findTiedOperandIdx(OpIdx);
    1304             :     return 0U;
    1305       54709 :   };
    1306             :   unsigned StartOp = 0;
    1307       54709 :   unsigned e = getNumOperands();
    1308             : 
    1309             :   // Print explicitly defined operands on the left of an assignment syntax.
    1310      103653 :   while (StartOp < e) {
    1311       78851 :     const MachineOperand &MO = getOperand(StartOp);
    1312      145553 :     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
    1313             :       break;
    1314             : 
    1315       24472 :     if (StartOp != 0)
    1316         520 :       OS << ", ";
    1317             : 
    1318       24472 :     LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
    1319       24472 :     unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
    1320       24472 :     MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
    1321             :              ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
    1322       24472 :     ++StartOp;
    1323             :   }
    1324             : 
    1325       54709 :   if (StartOp != 0)
    1326       23952 :     OS << " = ";
    1327             : 
    1328       54709 :   if (getFlag(MachineInstr::FrameSetup))
    1329        1053 :     OS << "frame-setup ";
    1330       54709 :   if (getFlag(MachineInstr::FrameDestroy))
    1331         252 :     OS << "frame-destroy ";
    1332       54709 :   if (getFlag(MachineInstr::FmNoNans))
    1333           0 :     OS << "nnan ";
    1334       54709 :   if (getFlag(MachineInstr::FmNoInfs))
    1335           0 :     OS << "ninf ";
    1336       54709 :   if (getFlag(MachineInstr::FmNsz))
    1337           0 :     OS << "nsz ";
    1338       54709 :   if (getFlag(MachineInstr::FmArcp))
    1339           0 :     OS << "arcp ";
    1340       54709 :   if (getFlag(MachineInstr::FmContract))
    1341           0 :     OS << "contract ";
    1342       54709 :   if (getFlag(MachineInstr::FmAfn))
    1343           0 :     OS << "afn ";
    1344       54709 :   if (getFlag(MachineInstr::FmReassoc))
    1345           0 :     OS << "reassoc ";
    1346             : 
    1347             :   // Print the opcode name.
    1348       54709 :   if (TII)
    1349      164124 :     OS << TII->getName(getOpcode());
    1350             :   else
    1351           1 :     OS << "UNKNOWN";
    1352             : 
    1353       54709 :   if (SkipOpers)
    1354          24 :     return;
    1355             : 
    1356             :   // Print the rest of the operands.
    1357             :   bool FirstOp = true;
    1358             :   unsigned AsmDescOp = ~0u;
    1359             :   unsigned AsmOpCount = 0;
    1360             : 
    1361       54709 :   if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
    1362             :     // Print asm string.
    1363           0 :     OS << " ";
    1364             :     const unsigned OpIdx = InlineAsm::MIOp_AsmString;
    1365           0 :     LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
    1366           0 :     unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
    1367           0 :     getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
    1368             :                             ShouldPrintRegisterTies, TiedOperandIdx, TRI,
    1369             :                             IntrinsicInfo);
    1370             : 
    1371             :     // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
    1372           0 :     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    1373           0 :     if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
    1374           0 :       OS << " [sideeffect]";
    1375           0 :     if (ExtraInfo & InlineAsm::Extra_MayLoad)
    1376           0 :       OS << " [mayload]";
    1377           0 :     if (ExtraInfo & InlineAsm::Extra_MayStore)
    1378           0 :       OS << " [maystore]";
    1379           0 :     if (ExtraInfo & InlineAsm::Extra_IsConvergent)
    1380           0 :       OS << " [isconvergent]";
    1381           0 :     if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
    1382           0 :       OS << " [alignstack]";
    1383           0 :     if (getInlineAsmDialect() == InlineAsm::AD_ATT)
    1384           0 :       OS << " [attdialect]";
    1385           0 :     if (getInlineAsmDialect() == InlineAsm::AD_Intel)
    1386           0 :       OS << " [inteldialect]";
    1387             : 
    1388             :     StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
    1389             :     FirstOp = false;
    1390             :   }
    1391             : 
    1392      200064 :   for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
    1393      145355 :     const MachineOperand &MO = getOperand(i);
    1394             : 
    1395      145355 :     if (FirstOp) FirstOp = false; else OS << ",";
    1396      145355 :     OS << " ";
    1397             : 
    1398      145435 :     if (isDebugValue() && MO.isMetadata()) {
    1399             :       // Pretty print DBG_VALUE instructions.
    1400          40 :       auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
    1401          20 :       if (DIV && !DIV->getName().empty())
    1402          40 :         OS << "!\"" << DIV->getName() << '\"';
    1403             :       else {
    1404          40 :         LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
    1405          20 :         unsigned TiedOperandIdx = getTiedOperandIdx(i);
    1406          20 :         MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
    1407             :                  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
    1408             :       }
    1409      145315 :     } else if (isDebugLabel() && MO.isMetadata()) {
    1410             :       // Pretty print DBG_LABEL instructions.
    1411           0 :       auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
    1412           0 :       if (DIL && !DIL->getName().empty())
    1413           0 :         OS << "\"" << DIL->getName() << '\"';
    1414             :       else {
    1415           0 :         LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
    1416           0 :         unsigned TiedOperandIdx = getTiedOperandIdx(i);
    1417           0 :         MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
    1418             :                  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
    1419             :       }
    1420      145315 :     } else if (i == AsmDescOp && MO.isImm()) {
    1421             :       // Pretty print the inline asm operand descriptor.
    1422           0 :       OS << '$' << AsmOpCount++;
    1423           0 :       unsigned Flag = MO.getImm();
    1424           0 :       switch (InlineAsm::getKind(Flag)) {
    1425           0 :       case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
    1426           0 :       case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
    1427           0 :       case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
    1428           0 :       case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
    1429           0 :       case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
    1430           0 :       case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
    1431           0 :       default: OS << ":[??" << InlineAsm::getKind(Flag); break;
    1432             :       }
    1433             : 
    1434             :       unsigned RCID = 0;
    1435           0 :       if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
    1436             :           InlineAsm::hasRegClassConstraint(Flag, RCID)) {
    1437           0 :         if (TRI) {
    1438           0 :           OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
    1439             :         } else
    1440           0 :           OS << ":RC" << RCID;
    1441             :       }
    1442             : 
    1443           0 :       if (InlineAsm::isMemKind(Flag)) {
    1444             :         unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
    1445           0 :         switch (MCID) {
    1446           0 :         case InlineAsm::Constraint_es: OS << ":es"; break;
    1447           0 :         case InlineAsm::Constraint_i:  OS << ":i"; break;
    1448           0 :         case InlineAsm::Constraint_m:  OS << ":m"; break;
    1449           0 :         case InlineAsm::Constraint_o:  OS << ":o"; break;
    1450           0 :         case InlineAsm::Constraint_v:  OS << ":v"; break;
    1451           0 :         case InlineAsm::Constraint_Q:  OS << ":Q"; break;
    1452           0 :         case InlineAsm::Constraint_R:  OS << ":R"; break;
    1453           0 :         case InlineAsm::Constraint_S:  OS << ":S"; break;
    1454           0 :         case InlineAsm::Constraint_T:  OS << ":T"; break;
    1455           0 :         case InlineAsm::Constraint_Um: OS << ":Um"; break;
    1456           0 :         case InlineAsm::Constraint_Un: OS << ":Un"; break;
    1457           0 :         case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
    1458           0 :         case InlineAsm::Constraint_Us: OS << ":Us"; break;
    1459           0 :         case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
    1460           0 :         case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
    1461           0 :         case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
    1462           0 :         case InlineAsm::Constraint_X:  OS << ":X"; break;
    1463           0 :         case InlineAsm::Constraint_Z:  OS << ":Z"; break;
    1464           0 :         case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
    1465           0 :         case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
    1466           0 :         default: OS << ":?"; break;
    1467             :         }
    1468             :       }
    1469             : 
    1470             :       unsigned TiedTo = 0;
    1471             :       if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
    1472           0 :         OS << " tiedto:$" << TiedTo;
    1473             : 
    1474             :       OS << ']';
    1475             : 
    1476             :       // Compute the index of the next operand descriptor.
    1477           0 :       AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
    1478             :     } else {
    1479      290630 :       LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
    1480      145315 :       unsigned TiedOperandIdx = getTiedOperandIdx(i);
    1481      145315 :       if (MO.isImm() && isOperandSubregIdx(i))
    1482         627 :         MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
    1483             :       else
    1484      144688 :         MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
    1485             :                  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
    1486             :     }
    1487             :   }
    1488             : 
    1489       54709 :   if (!SkipDebugLoc) {
    1490       54685 :     if (const DebugLoc &DL = getDebugLoc()) {
    1491          31 :       if (!FirstOp)
    1492             :         OS << ',';
    1493          31 :       OS << " debug-location ";
    1494          31 :       DL->printAsOperand(OS, MST);
    1495             :     }
    1496             :   }
    1497             : 
    1498       54709 :   if (!memoperands_empty()) {
    1499             :     SmallVector<StringRef, 0> SSNs;
    1500             :     const LLVMContext *Context = nullptr;
    1501        3832 :     std::unique_ptr<LLVMContext> CtxPtr;
    1502             :     const MachineFrameInfo *MFI = nullptr;
    1503             :     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
    1504        1916 :       MFI = &MF->getFrameInfo();
    1505        1916 :       Context = &MF->getFunction().getContext();
    1506             :     } else {
    1507           0 :       CtxPtr = llvm::make_unique<LLVMContext>();
    1508             :       Context = CtxPtr.get();
    1509             :     }
    1510             : 
    1511        1916 :     OS << " :: ";
    1512             :     bool NeedComma = false;
    1513        6756 :     for (const MachineMemOperand *Op : memoperands()) {
    1514        2420 :       if (NeedComma)
    1515         504 :         OS << ", ";
    1516        2420 :       Op->print(OS, MST, SSNs, *Context, MFI, TII);
    1517             :       NeedComma = true;
    1518             :     }
    1519             :   }
    1520             : 
    1521       54709 :   if (SkipDebugLoc)
    1522             :     return;
    1523             : 
    1524             :   bool HaveSemi = false;
    1525             : 
    1526             :   // Print debug location information.
    1527       54685 :   if (const DebugLoc &DL = getDebugLoc()) {
    1528             :     if (!HaveSemi) {
    1529             :       OS << ';';
    1530             :       HaveSemi = true;
    1531             :     }
    1532             :     OS << ' ';
    1533          31 :     DL.print(OS);
    1534             :   }
    1535             : 
    1536             :   // Print extra comments for DEBUG_VALUE.
    1537       54705 :   if (isDebugValue() && getOperand(e - 2).isMetadata()) {
    1538          20 :     if (!HaveSemi) {
    1539           0 :       OS << ";";
    1540             :       HaveSemi = true;
    1541             :     }
    1542          40 :     auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
    1543          20 :     OS << " line no:" <<  DV->getLine();
    1544             :     if (auto *InlinedAt = debugLoc->getInlinedAt()) {
    1545           0 :       DebugLoc InlinedAtDL(InlinedAt);
    1546             :       if (InlinedAtDL && MF) {
    1547             :         OS << " inlined @[ ";
    1548             :         InlinedAtDL.print(OS);
    1549             :         OS << " ]";
    1550             :       }
    1551             :     }
    1552             :     if (isIndirectDebugValue())
    1553           0 :       OS << " indirect";
    1554             :   }
    1555             :   // TODO: DBG_LABEL
    1556             : 
    1557       54685 :   if (AddNewLine)
    1558             :     OS << '\n';
    1559             : }
    1560             : 
    1561    10641482 : bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
    1562             :                                      const TargetRegisterInfo *RegInfo,
    1563             :                                      bool AddIfNotFound) {
    1564             :   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
    1565    17510874 :   bool hasAliases = isPhysReg &&
    1566    17510874 :     MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
    1567             :   bool Found = false;
    1568             :   SmallVector<unsigned,4> DeadOps;
    1569    52989563 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    1570    47721372 :     MachineOperand &MO = getOperand(i);
    1571   110648369 :     if (!MO.isReg() || !MO.isUse() || MO.isUndef())
    1572    19820906 :       continue;
    1573             : 
    1574             :     // DEBUG_VALUE nodes do not contribute to code generation and should
    1575             :     // always be ignored. Failure to do so may result in trying to modify
    1576             :     // KILL flags on DEBUG_VALUE nodes.
    1577    27900466 :     if (MO.isDebug())
    1578           0 :       continue;
    1579             : 
    1580    27900466 :     unsigned Reg = MO.getReg();
    1581    27900466 :     if (!Reg)
    1582     1399084 :       continue;
    1583             : 
    1584    26501382 :     if (Reg == IncomingReg) {
    1585     6234567 :       if (!Found) {
    1586     6166259 :         if (MO.isKill())
    1587             :           // The register is already marked kill.
    1588     5373291 :           return true;
    1589     4686244 :         if (isPhysReg && isRegTiedToDefOperand(i))
    1590             :           // Two-address uses of physregs must not be marked kill.
    1591             :           return true;
    1592             :         MO.setIsKill();
    1593             :         Found = true;
    1594             :       }
    1595    45527918 :     } else if (hasAliases && MO.isKill() &&
    1596             :                TargetRegisterInfo::isPhysicalRegister(Reg)) {
    1597             :       // A super-register kill already exists.
    1598     7926703 :       if (RegInfo->isSuperRegister(IncomingReg, Reg))
    1599             :         return true;
    1600     4033428 :       if (RegInfo->isSubRegister(IncomingReg, Reg))
    1601      523732 :         DeadOps.push_back(i);
    1602             :     }
    1603             :   }
    1604             : 
    1605             :   // Trim unneeded kill operands.
    1606     5791923 :   while (!DeadOps.empty()) {
    1607      523732 :     unsigned OpIdx = DeadOps.back();
    1608     1047464 :     if (getOperand(OpIdx).isImplicit())
    1609      477476 :       RemoveOperand(OpIdx);
    1610             :     else
    1611             :       getOperand(OpIdx).setIsKill(false);
    1612             :     DeadOps.pop_back();
    1613             :   }
    1614             : 
    1615             :   // If not found, this means an alias of one of the operands is killed. Add a
    1616             :   // new implicit operand if required.
    1617     5268191 :   if (!Found && AddIfNotFound) {
    1618      549079 :     addOperand(MachineOperand::CreateReg(IncomingReg,
    1619             :                                          false /*IsDef*/,
    1620             :                                          true  /*IsImp*/,
    1621             :                                          true  /*IsKill*/));
    1622      549079 :     return true;
    1623             :   }
    1624             :   return Found;
    1625             : }
    1626             : 
    1627      210505 : void MachineInstr::clearRegisterKills(unsigned Reg,
    1628             :                                       const TargetRegisterInfo *RegInfo) {
    1629      210505 :   if (!TargetRegisterInfo::isPhysicalRegister(Reg))
    1630             :     RegInfo = nullptr;
    1631     2207661 :   for (MachineOperand &MO : operands()) {
    1632     2024895 :     if (!MO.isReg() || !MO.isUse() || !MO.isKill())
    1633      951880 :       continue;
    1634       46698 :     unsigned OpReg = MO.getReg();
    1635       46698 :     if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
    1636             :       MO.setIsKill(false);
    1637             :   }
    1638      210505 : }
    1639             : 
    1640     1012692 : bool MachineInstr::addRegisterDead(unsigned Reg,
    1641             :                                    const TargetRegisterInfo *RegInfo,
    1642             :                                    bool AddIfNotFound) {
    1643             :   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
    1644     1940035 :   bool hasAliases = isPhysReg &&
    1645     1940035 :     MCRegAliasIterator(Reg, RegInfo, false).isValid();
    1646             :   bool Found = false;
    1647             :   SmallVector<unsigned,4> DeadOps;
    1648    12551157 :   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
    1649    11672988 :     MachineOperand &MO = getOperand(i);
    1650    18827887 :     if (!MO.isReg() || !MO.isDef())
    1651     6503388 :       continue;
    1652     5169600 :     unsigned MOReg = MO.getReg();
    1653     5169600 :     if (!MOReg)
    1654           0 :       continue;
    1655             : 
    1656     5169600 :     if (MOReg == Reg) {
    1657             :       MO.setIsDead();
    1658             :       Found = true;
    1659     9049856 :     } else if (hasAliases && MO.isDead() &&
    1660             :                TargetRegisterInfo::isPhysicalRegister(MOReg)) {
    1661             :       // There exists a super-register that's marked dead.
    1662     1590928 :       if (RegInfo->isSuperRegister(Reg, MOReg))
    1663      134523 :         return true;
    1664     1456405 :       if (RegInfo->isSubRegister(Reg, MOReg))
    1665       25858 :         DeadOps.push_back(i);
    1666             :     }
    1667             :   }
    1668             : 
    1669             :   // Trim unneeded dead operands.
    1670      904027 :   while (!DeadOps.empty()) {
    1671       25858 :     unsigned OpIdx = DeadOps.back();
    1672       51716 :     if (getOperand(OpIdx).isImplicit())
    1673       25785 :       RemoveOperand(OpIdx);
    1674             :     else
    1675             :       getOperand(OpIdx).setIsDead(false);
    1676             :     DeadOps.pop_back();
    1677             :   }
    1678             : 
    1679             :   // If not found, this means an alias of one of the operands is dead. Add a
    1680             :   // new implicit operand if required.
    1681      878169 :   if (Found || !AddIfNotFound)
    1682             :     return Found;
    1683             : 
    1684       25825 :   addOperand(MachineOperand::CreateReg(Reg,
    1685             :                                        true  /*IsDef*/,
    1686             :                                        true  /*IsImp*/,
    1687             :                                        false /*IsKill*/,
    1688             :                                        true  /*IsDead*/));
    1689       25825 :   return true;
    1690             : }
    1691             : 
    1692       51941 : void MachineInstr::clearRegisterDeads(unsigned Reg) {
    1693      583869 :   for (MachineOperand &MO : operands()) {
    1694      431908 :     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
    1695      214124 :       continue;
    1696             :     MO.setIsDead(false);
    1697             :   }
    1698       51941 : }
    1699             : 
    1700      463930 : void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
    1701     4299298 :   for (MachineOperand &MO : operands()) {
    1702     3710409 :     if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
    1703     1835490 :       continue;
    1704             :     MO.setIsUndef(IsUndef);
    1705             :   }
    1706      463930 : }
    1707             : 
    1708      501058 : void MachineInstr::addRegisterDefined(unsigned Reg,
    1709             :                                       const TargetRegisterInfo *RegInfo) {
    1710      501058 :   if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
    1711             :     MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
    1712          60 :     if (MO)
    1713             :       return;
    1714             :   } else {
    1715           0 :     for (const MachineOperand &MO : operands()) {
    1716           0 :       if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
    1717             :           MO.getSubReg() == 0)
    1718             :         return;
    1719             :     }
    1720             :   }
    1721      500998 :   addOperand(MachineOperand::CreateReg(Reg,
    1722             :                                        true  /*IsDef*/,
    1723             :                                        true  /*IsImp*/));
    1724             : }
    1725             : 
    1726     1022171 : void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
    1727             :                                          const TargetRegisterInfo &TRI) {
    1728             :   bool HasRegMask = false;
    1729    13569385 :   for (MachineOperand &MO : operands()) {
    1730     6273607 :     if (MO.isRegMask()) {
    1731             :       HasRegMask = true;
    1732     5045151 :       continue;
    1733             :     }
    1734    10257340 :     if (!MO.isReg() || !MO.isDef()) continue;
    1735     1637262 :     unsigned Reg = MO.getReg();
    1736     1637262 :     if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
    1737             :     // If there are no uses, including partial uses, the def is dead.
    1738     1466251 :     if (llvm::none_of(UsedRegs,
    1739      323858 :                       [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
    1740             :       MO.setIsDead();
    1741             :   }
    1742             : 
    1743             :   // This is a call with a register mask operand.
    1744             :   // Mask clobbers are always dead, so add defs for the non-dead defines.
    1745     1022171 :   if (HasRegMask)
    1746      421349 :     for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
    1747      659144 :          I != E; ++I)
    1748      421349 :       addRegisterDefined(*I, &TRI);
    1749     1022171 : }
    1750             : 
    1751             : unsigned
    1752     5628243 : MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
    1753             :   // Build up a buffer of hash code components.
    1754             :   SmallVector<size_t, 8> HashComponents;
    1755     5628243 :   HashComponents.reserve(MI->getNumOperands() + 1);
    1756    11256486 :   HashComponents.push_back(MI->getOpcode());
    1757    67869826 :   for (const MachineOperand &MO : MI->operands()) {
    1758    55027069 :     if (MO.isReg() && MO.isDef() &&
    1759     7959557 :         TargetRegisterInfo::isVirtualRegister(MO.getReg()))
    1760     4640968 :       continue;  // Skip virtual register defs.
    1761             : 
    1762    47331404 :     HashComponents.push_back(hash_value(MO));
    1763             :   }
    1764    11256486 :   return hash_combine_range(HashComponents.begin(), HashComponents.end());
    1765             : }
    1766             : 
    1767         110 : void MachineInstr::emitError(StringRef Msg) const {
    1768             :   // Find the source location cookie.
    1769             :   unsigned LocCookie = 0;
    1770             :   const MDNode *LocMD = nullptr;
    1771         110 :   for (unsigned i = getNumOperands(); i != 0; --i) {
    1772        2490 :     if (getOperand(i-1).isMetadata() &&
    1773        2490 :         (LocMD = getOperand(i-1).getMetadata()) &&
    1774          12 :         LocMD->getNumOperands() != 0) {
    1775             :       if (const ConstantInt *CI =
    1776             :               mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
    1777          12 :         LocCookie = CI->getZExtValue();
    1778          12 :         break;
    1779             :       }
    1780             :     }
    1781             :   }
    1782             : 
    1783         110 :   if (const MachineBasicBlock *MBB = getParent())
    1784         110 :     if (const MachineFunction *MF = MBB->getParent())
    1785         220 :       return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
    1786           0 :   report_fatal_error(Msg);
    1787             : }
    1788             : 
    1789       48967 : MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
    1790             :                                   const MCInstrDesc &MCID, bool IsIndirect,
    1791             :                                   unsigned Reg, const MDNode *Variable,
    1792             :                                   const MDNode *Expr) {
    1793             :   assert(isa<DILocalVariable>(Variable) && "not a variable");
    1794             :   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
    1795             :   assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
    1796             :          "Expected inlined-at fields to agree");
    1797       48967 :   if (IsIndirect)
    1798       21778 :     return BuildMI(MF, DL, MCID)
    1799       10889 :         .addReg(Reg, RegState::Debug)
    1800             :         .addImm(0U)
    1801             :         .addMetadata(Variable)
    1802       10889 :         .addMetadata(Expr);
    1803             :   else
    1804       76156 :     return BuildMI(MF, DL, MCID)
    1805       38078 :         .addReg(Reg, RegState::Debug)
    1806       38078 :         .addReg(0U, RegState::Debug)
    1807             :         .addMetadata(Variable)
    1808       38078 :         .addMetadata(Expr);
    1809             : }
    1810             : 
    1811       44189 : MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
    1812             :                                   MachineBasicBlock::iterator I,
    1813             :                                   const DebugLoc &DL, const MCInstrDesc &MCID,
    1814             :                                   bool IsIndirect, unsigned Reg,
    1815             :                                   const MDNode *Variable, const MDNode *Expr) {
    1816             :   assert(isa<DILocalVariable>(Variable) && "not a variable");
    1817             :   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
    1818       44189 :   MachineFunction &MF = *BB.getParent();
    1819       44189 :   MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
    1820             :   BB.insert(I, MI);
    1821       44189 :   return MachineInstrBuilder(MF, MI);
    1822             : }
    1823             : 
    1824             : /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
    1825             : /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
    1826         180 : static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
    1827             :   assert(MI.getOperand(0).isReg() && "can't spill non-register");
    1828             :   assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
    1829             :          "Expected inlined-at fields to agree");
    1830             : 
    1831         180 :   const DIExpression *Expr = MI.getDebugExpression();
    1832             :   if (MI.isIndirectDebugValue()) {
    1833             :     assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
    1834         160 :     Expr = DIExpression::prepend(Expr, DIExpression::WithDeref);
    1835             :   }
    1836         180 :   return Expr;
    1837             : }
    1838             : 
    1839         178 : MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
    1840             :                                           MachineBasicBlock::iterator I,
    1841             :                                           const MachineInstr &Orig,
    1842             :                                           int FrameIndex) {
    1843         178 :   const DIExpression *Expr = computeExprForSpill(Orig);
    1844         356 :   return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
    1845             :       .addFrameIndex(FrameIndex)
    1846             :       .addImm(0U)
    1847         178 :       .addMetadata(Orig.getDebugVariable())
    1848         178 :       .addMetadata(Expr);
    1849             : }
    1850             : 
    1851           2 : void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
    1852           2 :   const DIExpression *Expr = computeExprForSpill(Orig);
    1853           2 :   Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
    1854           4 :   Orig.getOperand(1).ChangeToImmediate(0U);
    1855           2 :   Orig.getOperand(3).setMetadata(Expr);
    1856           2 : }

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