Line data Source code
1 : //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : /// \file Methods common to all machine operands.
11 : //
12 : //===----------------------------------------------------------------------===//
13 :
14 : #include "llvm/CodeGen/MachineOperand.h"
15 : #include "llvm/ADT/StringExtras.h"
16 : #include "llvm/Analysis/Loads.h"
17 : #include "llvm/Analysis/MemoryLocation.h"
18 : #include "llvm/CodeGen/MIRPrinter.h"
19 : #include "llvm/CodeGen/MachineFrameInfo.h"
20 : #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 : #include "llvm/CodeGen/MachineRegisterInfo.h"
22 : #include "llvm/CodeGen/TargetInstrInfo.h"
23 : #include "llvm/CodeGen/TargetRegisterInfo.h"
24 : #include "llvm/Config/llvm-config.h"
25 : #include "llvm/IR/Constants.h"
26 : #include "llvm/IR/IRPrintingPasses.h"
27 : #include "llvm/IR/ModuleSlotTracker.h"
28 : #include "llvm/Target/TargetIntrinsicInfo.h"
29 : #include "llvm/Target/TargetMachine.h"
30 :
31 : using namespace llvm;
32 :
33 : static cl::opt<int>
34 : PrintRegMaskNumRegs("print-regmask-num-regs",
35 : cl::desc("Number of registers to limit to when "
36 : "printing regmask operands in IR dumps. "
37 : "unlimited = -1"),
38 : cl::init(32), cl::Hidden);
39 :
40 : static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
41 242201 : if (const MachineInstr *MI = MO.getParent())
42 69975279 : if (const MachineBasicBlock *MBB = MI->getParent())
43 69959403 : if (const MachineFunction *MF = MBB->getParent())
44 : return MF;
45 : return nullptr;
46 : }
47 : static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
48 : return const_cast<MachineFunction *>(
49 : getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
50 : }
51 :
52 53218891 : void MachineOperand::setReg(unsigned Reg) {
53 53218891 : if (getReg() == Reg)
54 : return; // No change.
55 :
56 : // Clear the IsRenamable bit to keep it conservatively correct.
57 52503309 : IsRenamable = false;
58 :
59 : // Otherwise, we have to change the register. If this operand is embedded
60 : // into a machine function, we need to update the old and new register's
61 : // use/def lists.
62 : if (MachineFunction *MF = getMFIfAvailable(*this)) {
63 52427150 : MachineRegisterInfo &MRI = MF->getRegInfo();
64 52427150 : MRI.removeRegOperandFromUseList(this);
65 52427150 : SmallContents.RegNo = Reg;
66 52427150 : MRI.addRegOperandToUseList(this);
67 52427150 : return;
68 : }
69 :
70 : // Otherwise, just change the register, no problem. :)
71 76159 : SmallContents.RegNo = Reg;
72 : }
73 :
74 1413167 : void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
75 : const TargetRegisterInfo &TRI) {
76 : assert(TargetRegisterInfo::isVirtualRegister(Reg));
77 1413167 : if (SubIdx && getSubReg())
78 : SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
79 1413167 : setReg(Reg);
80 1413167 : if (SubIdx)
81 : setSubReg(SubIdx);
82 1413167 : }
83 :
84 194943 : void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
85 : assert(TargetRegisterInfo::isPhysicalRegister(Reg));
86 194943 : if (getSubReg()) {
87 7505 : Reg = TRI.getSubReg(Reg, getSubReg());
88 : // Note that getSubReg() may return 0 if the sub-register doesn't exist.
89 : // That won't happen in legal code.
90 : setSubReg(0);
91 7505 : if (isDef())
92 : setIsUndef(false);
93 : }
94 194943 : setReg(Reg);
95 194943 : }
96 :
97 : /// Change a def to a use, or a use to a def.
98 90144 : void MachineOperand::setIsDef(bool Val) {
99 : assert(isReg() && "Wrong MachineOperand accessor");
100 : assert((!Val || !isDebug()) && "Marking a debug operation as def");
101 90144 : if (IsDef == Val)
102 : return;
103 : assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
104 : // MRI may keep uses and defs in different list positions.
105 : if (MachineFunction *MF = getMFIfAvailable(*this)) {
106 532 : MachineRegisterInfo &MRI = MF->getRegInfo();
107 532 : MRI.removeRegOperandFromUseList(this);
108 532 : IsDef = Val;
109 532 : MRI.addRegOperandToUseList(this);
110 532 : return;
111 : }
112 112 : IsDef = Val;
113 : }
114 :
115 38065218 : bool MachineOperand::isRenamable() const {
116 : assert(isReg() && "Wrong MachineOperand accessor");
117 : assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
118 : "isRenamable should only be checked on physical registers");
119 38065218 : if (!IsRenamable)
120 : return false;
121 :
122 15666278 : const MachineInstr *MI = getParent();
123 15666278 : if (!MI)
124 : return true;
125 :
126 15666278 : if (isDef())
127 6330221 : return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
128 :
129 : assert(isUse() && "Reg is not def or use");
130 9336057 : return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
131 : }
132 :
133 39143244 : void MachineOperand::setIsRenamable(bool Val) {
134 : assert(isReg() && "Wrong MachineOperand accessor");
135 : assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
136 : "setIsRenamable should only be called on physical registers");
137 39143244 : IsRenamable = Val;
138 39143244 : }
139 :
140 : // If this operand is currently a register operand, and if this is in a
141 : // function, deregister the operand from the register's use/def list.
142 17304506 : void MachineOperand::removeRegFromUses() {
143 17304506 : if (!isReg() || !isOnRegUseList())
144 : return;
145 :
146 : if (MachineFunction *MF = getMFIfAvailable(*this))
147 101552 : MF->getRegInfo().removeRegOperandFromUseList(this);
148 : }
149 :
150 : /// ChangeToImmediate - Replace this operand with a new immediate operand of
151 : /// the specified value. If an operand is known to be an immediate already,
152 : /// the setImm method should be used.
153 17304357 : void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
154 : assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
155 :
156 17304357 : removeRegFromUses();
157 :
158 17304357 : OpKind = MO_Immediate;
159 17304357 : Contents.ImmVal = ImmVal;
160 17304357 : }
161 :
162 0 : void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
163 : assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
164 :
165 0 : removeRegFromUses();
166 :
167 0 : OpKind = MO_FPImmediate;
168 0 : Contents.CFP = FPImm;
169 0 : }
170 :
171 58 : void MachineOperand::ChangeToES(const char *SymName,
172 : unsigned char TargetFlags) {
173 : assert((!isReg() || !isTied()) &&
174 : "Cannot change a tied operand into an external symbol");
175 :
176 58 : removeRegFromUses();
177 :
178 58 : OpKind = MO_ExternalSymbol;
179 58 : Contents.OffsetedInfo.Val.SymbolName = SymName;
180 : setOffset(0); // Offset is always 0.
181 : setTargetFlags(TargetFlags);
182 58 : }
183 :
184 0 : void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
185 : assert((!isReg() || !isTied()) &&
186 : "Cannot change a tied operand into an MCSymbol");
187 :
188 0 : removeRegFromUses();
189 :
190 0 : OpKind = MO_MCSymbol;
191 0 : Contents.Sym = Sym;
192 0 : }
193 :
194 90 : void MachineOperand::ChangeToFrameIndex(int Idx) {
195 : assert((!isReg() || !isTied()) &&
196 : "Cannot change a tied operand into a FrameIndex");
197 :
198 90 : removeRegFromUses();
199 :
200 90 : OpKind = MO_FrameIndex;
201 : setIndex(Idx);
202 90 : }
203 :
204 1 : void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
205 : unsigned char TargetFlags) {
206 : assert((!isReg() || !isTied()) &&
207 : "Cannot change a tied operand into a FrameIndex");
208 :
209 1 : removeRegFromUses();
210 :
211 1 : OpKind = MO_TargetIndex;
212 1 : setIndex(Idx);
213 : setOffset(Offset);
214 : setTargetFlags(TargetFlags);
215 1 : }
216 :
217 : /// ChangeToRegister - Replace this operand with a new register operand of
218 : /// the specified value. If an operand is known to be an register already,
219 : /// the setReg method should be used.
220 17289547 : void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
221 : bool isKill, bool isDead, bool isUndef,
222 : bool isDebug) {
223 : MachineRegisterInfo *RegInfo = nullptr;
224 : if (MachineFunction *MF = getMFIfAvailable(*this))
225 17289546 : RegInfo = &MF->getRegInfo();
226 : // If this operand is already a register operand, remove it from the
227 : // register's use/def lists.
228 : bool WasReg = isReg();
229 17289547 : if (RegInfo && WasReg)
230 31685 : RegInfo->removeRegOperandFromUseList(this);
231 :
232 : // Change this to a register and set the reg#.
233 : assert(!(isDead && !isDef) && "Dead flag on non-def");
234 : assert(!(isKill && isDef) && "Kill flag on def");
235 17289547 : OpKind = MO_Register;
236 17289547 : SmallContents.RegNo = Reg;
237 17289547 : SubReg_TargetFlags = 0;
238 17289547 : IsDef = isDef;
239 17289547 : IsImp = isImp;
240 17289547 : IsDeadOrKill = isKill | isDead;
241 17289547 : IsRenamable = false;
242 17289547 : IsUndef = isUndef;
243 17289547 : IsInternalRead = false;
244 17289547 : IsEarlyClobber = false;
245 17289547 : IsDebug = isDebug;
246 : // Ensure isOnRegUseList() returns false.
247 17289547 : Contents.Reg.Prev = nullptr;
248 : // Preserve the tie when the operand was already a register.
249 17289547 : if (!WasReg)
250 17257862 : TiedTo = 0;
251 :
252 : // If this operand is embedded in a function, add the operand to the
253 : // register's use/def list.
254 17289547 : if (RegInfo)
255 17289546 : RegInfo->addRegOperandToUseList(this);
256 17289547 : }
257 :
258 : /// isIdenticalTo - Return true if this operand is identical to the specified
259 : /// operand. Note that this should stay in sync with the hash_value overload
260 : /// below.
261 36222809 : bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
262 72031327 : if (getType() != Other.getType() ||
263 : getTargetFlags() != Other.getTargetFlags())
264 : return false;
265 :
266 35631823 : switch (getType()) {
267 22584832 : case MachineOperand::MO_Register:
268 22584832 : return getReg() == Other.getReg() && isDef() == Other.isDef() &&
269 : getSubReg() == Other.getSubReg();
270 8063820 : case MachineOperand::MO_Immediate:
271 8063820 : return getImm() == Other.getImm();
272 5 : case MachineOperand::MO_CImmediate:
273 5 : return getCImm() == Other.getCImm();
274 317 : case MachineOperand::MO_FPImmediate:
275 317 : return getFPImm() == Other.getFPImm();
276 10350 : case MachineOperand::MO_MachineBasicBlock:
277 10350 : return getMBB() == Other.getMBB();
278 255221 : case MachineOperand::MO_FrameIndex:
279 255221 : return getIndex() == Other.getIndex();
280 29170 : case MachineOperand::MO_ConstantPoolIndex:
281 : case MachineOperand::MO_TargetIndex:
282 29170 : return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
283 266 : case MachineOperand::MO_JumpTableIndex:
284 266 : return getIndex() == Other.getIndex();
285 2455505 : case MachineOperand::MO_GlobalAddress:
286 2455505 : return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
287 4928 : case MachineOperand::MO_ExternalSymbol:
288 4928 : return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
289 9728 : getOffset() == Other.getOffset();
290 153 : case MachineOperand::MO_BlockAddress:
291 153 : return getBlockAddress() == Other.getBlockAddress() &&
292 280 : getOffset() == Other.getOffset();
293 1139076 : case MachineOperand::MO_RegisterMask:
294 : case MachineOperand::MO_RegisterLiveOut: {
295 : // Shallow compare of the two RegMasks
296 1139076 : const uint32_t *RegMask = getRegMask();
297 1139076 : const uint32_t *OtherRegMask = Other.getRegMask();
298 1139076 : if (RegMask == OtherRegMask)
299 : return true;
300 :
301 : if (const MachineFunction *MF = getMFIfAvailable(*this)) {
302 : // Calculate the size of the RegMask
303 0 : const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
304 0 : unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
305 :
306 : // Deep compare of the two RegMasks
307 0 : return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
308 : }
309 : // We don't know the size of the RegMask, so we can't deep compare the two
310 : // reg masks.
311 : return false;
312 : }
313 1032092 : case MachineOperand::MO_MCSymbol:
314 1032092 : return getMCSymbol() == Other.getMCSymbol();
315 6 : case MachineOperand::MO_CFIIndex:
316 6 : return getCFIIndex() == Other.getCFIIndex();
317 56082 : case MachineOperand::MO_Metadata:
318 56082 : return getMetadata() == Other.getMetadata();
319 0 : case MachineOperand::MO_IntrinsicID:
320 0 : return getIntrinsicID() == Other.getIntrinsicID();
321 0 : case MachineOperand::MO_Predicate:
322 0 : return getPredicate() == Other.getPredicate();
323 : }
324 0 : llvm_unreachable("Invalid machine operand type");
325 : }
326 :
327 : // Note: this must stay exactly in sync with isIdenticalTo above.
328 25197128 : hash_code llvm::hash_value(const MachineOperand &MO) {
329 25197128 : switch (MO.getType()) {
330 : case MachineOperand::MO_Register:
331 : // Register operands don't have target flags.
332 29960304 : return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
333 8838289 : case MachineOperand::MO_Immediate:
334 17676578 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
335 17 : case MachineOperand::MO_CImmediate:
336 34 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
337 727 : case MachineOperand::MO_FPImmediate:
338 1454 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
339 490443 : case MachineOperand::MO_MachineBasicBlock:
340 980886 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
341 325698 : case MachineOperand::MO_FrameIndex:
342 651396 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
343 80116 : case MachineOperand::MO_ConstantPoolIndex:
344 : case MachineOperand::MO_TargetIndex:
345 240348 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
346 240348 : MO.getOffset());
347 822 : case MachineOperand::MO_JumpTableIndex:
348 1644 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
349 14255 : case MachineOperand::MO_ExternalSymbol:
350 14255 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
351 28510 : MO.getSymbolName());
352 466049 : case MachineOperand::MO_GlobalAddress:
353 1398148 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
354 1398147 : MO.getOffset());
355 376 : case MachineOperand::MO_BlockAddress:
356 1128 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
357 1128 : MO.getOffset());
358 18 : case MachineOperand::MO_RegisterMask:
359 : case MachineOperand::MO_RegisterLiveOut:
360 36 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
361 0 : case MachineOperand::MO_Metadata:
362 0 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
363 166 : case MachineOperand::MO_MCSymbol:
364 332 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
365 0 : case MachineOperand::MO_CFIIndex:
366 0 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
367 0 : case MachineOperand::MO_IntrinsicID:
368 0 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
369 0 : case MachineOperand::MO_Predicate:
370 0 : return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
371 : }
372 0 : llvm_unreachable("Invalid machine operand type");
373 : }
374 :
375 : // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
376 : // it.
377 36 : static void tryToGetTargetInfo(const MachineOperand &MO,
378 : const TargetRegisterInfo *&TRI,
379 : const TargetIntrinsicInfo *&IntrinsicInfo) {
380 : if (const MachineFunction *MF = getMFIfAvailable(MO)) {
381 17 : TRI = MF->getSubtarget().getRegisterInfo();
382 17 : IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
383 : }
384 36 : }
385 :
386 2 : static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
387 2 : const auto *TII = MF.getSubtarget().getInstrInfo();
388 : assert(TII && "expected instruction info");
389 2 : auto Indices = TII->getSerializableTargetIndices();
390 : auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
391 0 : return I.first == Index;
392 : });
393 2 : if (Found != Indices.end())
394 2 : return Found->second;
395 : return nullptr;
396 : }
397 :
398 : static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
399 3021 : auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
400 5943 : for (const auto &I : Flags) {
401 5943 : if (I.first == TF) {
402 3021 : return I.second;
403 : }
404 : }
405 : return nullptr;
406 : }
407 :
408 796 : static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
409 : const TargetRegisterInfo *TRI) {
410 796 : if (!TRI) {
411 0 : OS << "%dwarfreg." << DwarfReg;
412 0 : return;
413 : }
414 :
415 796 : int Reg = TRI->getLLVMRegNum(DwarfReg, true);
416 796 : if (Reg == -1) {
417 0 : OS << "<badreg>";
418 0 : return;
419 : }
420 1592 : OS << printReg(Reg, TRI);
421 : }
422 :
423 21 : static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
424 : ModuleSlotTracker &MST) {
425 21 : OS << "%ir-block.";
426 21 : if (BB.hasName()) {
427 19 : printLLVMNameWithoutPrefix(OS, BB.getName());
428 : return;
429 : }
430 : Optional<int> Slot;
431 2 : if (const Function *F = BB.getParent()) {
432 2 : if (F == MST.getCurrentFunction()) {
433 1 : Slot = MST.getLocalSlot(&BB);
434 1 : } else if (const Module *M = F->getParent()) {
435 2 : ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
436 1 : CustomMST.incorporateFunction(*F);
437 1 : Slot = CustomMST.getLocalSlot(&BB);
438 : }
439 : }
440 2 : if (Slot)
441 2 : MachineOperand::printIRSlotNumber(OS, *Slot);
442 : else
443 0 : OS << "<unknown>";
444 : }
445 :
446 2607 : static void printIRValueReference(raw_ostream &OS, const Value &V,
447 : ModuleSlotTracker &MST) {
448 : if (isa<GlobalValue>(V)) {
449 180 : V.printAsOperand(OS, /*PrintType=*/false, MST);
450 180 : return;
451 : }
452 2427 : if (isa<Constant>(V)) {
453 : // Machine memory operands can load/store to/from constant value pointers.
454 : OS << '`';
455 642 : V.printAsOperand(OS, /*PrintType=*/true, MST);
456 : OS << '`';
457 642 : return;
458 : }
459 1785 : OS << "%ir.";
460 1785 : if (V.hasName()) {
461 1671 : printLLVMNameWithoutPrefix(OS, V.getName());
462 1671 : return;
463 : }
464 114 : MachineOperand::printIRSlotNumber(OS, MST.getLocalSlot(&V));
465 : }
466 :
467 6545 : static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
468 : SyncScope::ID SSID,
469 : SmallVectorImpl<StringRef> &SSNs) {
470 6545 : switch (SSID) {
471 : case SyncScope::System:
472 : break;
473 90 : default:
474 90 : if (SSNs.empty())
475 84 : Context.getSyncScopeNames(SSNs);
476 :
477 90 : OS << "syncscope(\"";
478 180 : printEscapedString(SSNs[SSID], OS);
479 90 : OS << "\") ";
480 90 : break;
481 : }
482 6545 : }
483 :
484 : static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
485 : unsigned TMMOFlag) {
486 23 : auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
487 44 : for (const auto &I : Flags) {
488 44 : if (I.first == TMMOFlag) {
489 23 : return I.second;
490 : }
491 : }
492 : return nullptr;
493 : }
494 :
495 2672 : static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
496 : const MachineFrameInfo *MFI) {
497 2672 : StringRef Name;
498 2672 : if (MFI) {
499 : IsFixed = MFI->isFixedObjectIndex(FrameIndex);
500 2672 : if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
501 610 : if (Alloca->hasName())
502 610 : Name = Alloca->getName();
503 2672 : if (IsFixed)
504 331 : FrameIndex -= MFI->getObjectIndexBegin();
505 : }
506 2672 : MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
507 2672 : }
508 :
509 1206 : void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
510 : const TargetRegisterInfo *TRI) {
511 1206 : OS << "%subreg.";
512 1206 : if (TRI)
513 2410 : OS << TRI->getSubRegIndexName(Index);
514 : else
515 1 : OS << Index;
516 1206 : }
517 :
518 319470 : void MachineOperand::printTargetFlags(raw_ostream &OS,
519 : const MachineOperand &Op) {
520 108865 : if (!Op.getTargetFlags())
521 318185 : return;
522 : const MachineFunction *MF = getMFIfAvailable(Op);
523 : if (!MF)
524 : return;
525 :
526 3181 : const auto *TII = MF->getSubtarget().getInstrInfo();
527 : assert(TII && "expected instruction info");
528 6362 : auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
529 3181 : OS << "target-flags(";
530 3181 : const bool HasDirectFlags = Flags.first;
531 : const bool HasBitmaskFlags = Flags.second;
532 3181 : if (!HasDirectFlags && !HasBitmaskFlags) {
533 138 : OS << "<unknown>) ";
534 138 : return;
535 : }
536 3043 : if (HasDirectFlags) {
537 3021 : if (const auto *Name = getTargetFlagName(TII, Flags.first))
538 3021 : OS << Name;
539 : else
540 0 : OS << "<unknown target flag>";
541 : }
542 3043 : if (!HasBitmaskFlags) {
543 1758 : OS << ") ";
544 1758 : return;
545 : }
546 : bool IsCommaNeeded = HasDirectFlags;
547 : unsigned BitMask = Flags.second;
548 1285 : auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
549 7713 : for (const auto &Mask : BitMasks) {
550 : // Check if the flag's bitmask has the bits of the current mask set.
551 6428 : if ((BitMask & Mask.first) == Mask.first) {
552 1286 : if (IsCommaNeeded)
553 1264 : OS << ", ";
554 : IsCommaNeeded = true;
555 1286 : OS << Mask.second;
556 : // Clear the bits which were serialized from the flag's bitmask.
557 1286 : BitMask &= ~(Mask.first);
558 : }
559 : }
560 1285 : if (BitMask) {
561 : // When the resulting flag's bitmask isn't zero, we know that we didn't
562 : // serialize all of the bit flags.
563 0 : if (IsCommaNeeded)
564 0 : OS << ", ";
565 0 : OS << "<unknown bitmask target flag>";
566 : }
567 1285 : OS << ") ";
568 : }
569 :
570 25 : void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
571 50 : OS << "<mcsymbol " << Sym << ">";
572 25 : }
573 :
574 3426 : void MachineOperand::printStackObjectReference(raw_ostream &OS,
575 : unsigned FrameIndex,
576 : bool IsFixed, StringRef Name) {
577 3426 : if (IsFixed) {
578 621 : OS << "%fixed-stack." << FrameIndex;
579 621 : return;
580 : }
581 :
582 2805 : OS << "%stack." << FrameIndex;
583 2805 : if (!Name.empty())
584 793 : OS << '.' << Name;
585 : }
586 :
587 15463 : void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
588 15463 : if (Offset == 0)
589 : return;
590 417 : if (Offset < 0) {
591 7 : OS << " - " << -Offset;
592 7 : return;
593 : }
594 410 : OS << " + " << Offset;
595 : }
596 :
597 116 : void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
598 116 : if (Slot == -1)
599 0 : OS << "<badref>";
600 : else
601 : OS << Slot;
602 116 : }
603 :
604 1211 : static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
605 : const TargetRegisterInfo *TRI) {
606 1211 : switch (CFI.getOperation()) {
607 3 : case MCCFIInstruction::OpSameValue:
608 3 : OS << "same_value ";
609 3 : if (MCSymbol *Label = CFI.getLabel())
610 0 : MachineOperand::printSymbol(OS, *Label);
611 3 : printCFIRegister(CFI.getRegister(), OS, TRI);
612 3 : break;
613 1 : case MCCFIInstruction::OpRememberState:
614 1 : OS << "remember_state ";
615 1 : if (MCSymbol *Label = CFI.getLabel())
616 0 : MachineOperand::printSymbol(OS, *Label);
617 : break;
618 1 : case MCCFIInstruction::OpRestoreState:
619 1 : OS << "restore_state ";
620 1 : if (MCSymbol *Label = CFI.getLabel())
621 0 : MachineOperand::printSymbol(OS, *Label);
622 : break;
623 772 : case MCCFIInstruction::OpOffset:
624 772 : OS << "offset ";
625 772 : if (MCSymbol *Label = CFI.getLabel())
626 0 : MachineOperand::printSymbol(OS, *Label);
627 772 : printCFIRegister(CFI.getRegister(), OS, TRI);
628 772 : OS << ", " << CFI.getOffset();
629 : break;
630 11 : case MCCFIInstruction::OpDefCfaRegister:
631 11 : OS << "def_cfa_register ";
632 11 : if (MCSymbol *Label = CFI.getLabel())
633 0 : MachineOperand::printSymbol(OS, *Label);
634 11 : printCFIRegister(CFI.getRegister(), OS, TRI);
635 11 : break;
636 396 : case MCCFIInstruction::OpDefCfaOffset:
637 396 : OS << "def_cfa_offset ";
638 396 : if (MCSymbol *Label = CFI.getLabel())
639 2 : MachineOperand::printSymbol(OS, *Label);
640 396 : OS << CFI.getOffset();
641 : break;
642 5 : case MCCFIInstruction::OpDefCfa:
643 5 : OS << "def_cfa ";
644 5 : if (MCSymbol *Label = CFI.getLabel())
645 0 : MachineOperand::printSymbol(OS, *Label);
646 5 : printCFIRegister(CFI.getRegister(), OS, TRI);
647 5 : OS << ", " << CFI.getOffset();
648 : break;
649 1 : case MCCFIInstruction::OpRelOffset:
650 1 : OS << "rel_offset ";
651 1 : if (MCSymbol *Label = CFI.getLabel())
652 0 : MachineOperand::printSymbol(OS, *Label);
653 1 : printCFIRegister(CFI.getRegister(), OS, TRI);
654 1 : OS << ", " << CFI.getOffset();
655 : break;
656 16 : case MCCFIInstruction::OpAdjustCfaOffset:
657 16 : OS << "adjust_cfa_offset ";
658 16 : if (MCSymbol *Label = CFI.getLabel())
659 0 : MachineOperand::printSymbol(OS, *Label);
660 16 : OS << CFI.getOffset();
661 : break;
662 1 : case MCCFIInstruction::OpRestore:
663 1 : OS << "restore ";
664 1 : if (MCSymbol *Label = CFI.getLabel())
665 0 : MachineOperand::printSymbol(OS, *Label);
666 1 : printCFIRegister(CFI.getRegister(), OS, TRI);
667 1 : break;
668 1 : case MCCFIInstruction::OpEscape: {
669 1 : OS << "escape ";
670 1 : if (MCSymbol *Label = CFI.getLabel())
671 0 : MachineOperand::printSymbol(OS, *Label);
672 1 : if (!CFI.getValues().empty()) {
673 1 : size_t e = CFI.getValues().size() - 1;
674 3 : for (size_t i = 0; i < e; ++i)
675 4 : OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
676 2 : OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
677 : }
678 : break;
679 : }
680 1 : case MCCFIInstruction::OpUndefined:
681 1 : OS << "undefined ";
682 1 : if (MCSymbol *Label = CFI.getLabel())
683 0 : MachineOperand::printSymbol(OS, *Label);
684 1 : printCFIRegister(CFI.getRegister(), OS, TRI);
685 1 : break;
686 1 : case MCCFIInstruction::OpRegister:
687 1 : OS << "register ";
688 1 : if (MCSymbol *Label = CFI.getLabel())
689 0 : MachineOperand::printSymbol(OS, *Label);
690 1 : printCFIRegister(CFI.getRegister(), OS, TRI);
691 1 : OS << ", ";
692 1 : printCFIRegister(CFI.getRegister2(), OS, TRI);
693 1 : break;
694 1 : case MCCFIInstruction::OpWindowSave:
695 1 : OS << "window_save ";
696 1 : if (MCSymbol *Label = CFI.getLabel())
697 0 : MachineOperand::printSymbol(OS, *Label);
698 : break;
699 0 : default:
700 : // TODO: Print the other CFI Operations.
701 0 : OS << "<unserializable cfi directive>";
702 0 : break;
703 : }
704 1211 : }
705 :
706 19 : void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
707 : const TargetIntrinsicInfo *IntrinsicInfo) const {
708 19 : print(OS, LLT{}, TRI, IntrinsicInfo);
709 19 : }
710 :
711 36 : void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
712 : const TargetRegisterInfo *TRI,
713 : const TargetIntrinsicInfo *IntrinsicInfo) const {
714 36 : tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
715 72 : ModuleSlotTracker DummyMST(nullptr);
716 36 : print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
717 : /*ShouldPrintRegisterTies=*/true,
718 : /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
719 36 : }
720 :
721 318896 : void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
722 : LLT TypeToPrint, bool PrintDef, bool IsStandalone,
723 : bool ShouldPrintRegisterTies,
724 : unsigned TiedOperandIdx,
725 : const TargetRegisterInfo *TRI,
726 : const TargetIntrinsicInfo *IntrinsicInfo) const {
727 318896 : printTargetFlags(OS, *this);
728 318896 : switch (getType()) {
729 210605 : case MachineOperand::MO_Register: {
730 210605 : unsigned Reg = getReg();
731 210605 : if (isImplicit())
732 114251 : OS << (isDef() ? "implicit-def " : "implicit ");
733 135754 : else if (PrintDef && isDef())
734 : // Print the 'def' flag only when the operand is defined after '='.
735 96 : OS << "def ";
736 210605 : if (isInternalRead())
737 24 : OS << "internal ";
738 210605 : if (isDead())
739 21924 : OS << "dead ";
740 210605 : if (isKill())
741 13660 : OS << "killed ";
742 210605 : if (isUndef())
743 1383 : OS << "undef ";
744 210605 : if (isEarlyClobber())
745 920 : OS << "early-clobber ";
746 210605 : if (isDebug())
747 2393 : OS << "debug-use ";
748 421210 : if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable())
749 7943 : OS << "renamable ";
750 :
751 : const MachineRegisterInfo *MRI = nullptr;
752 210605 : if (TargetRegisterInfo::isVirtualRegister(Reg)) {
753 : if (const MachineFunction *MF = getMFIfAvailable(*this)) {
754 67804 : MRI = &MF->getRegInfo();
755 : }
756 : }
757 :
758 421210 : OS << printReg(Reg, TRI, 0, MRI);
759 : // Print the sub register.
760 210605 : if (unsigned SubReg = getSubReg()) {
761 1433 : if (TRI)
762 2864 : OS << '.' << TRI->getSubRegIndexName(SubReg);
763 : else
764 1 : OS << ".subreg" << SubReg;
765 : }
766 : // Print the register class / bank.
767 210605 : if (TargetRegisterInfo::isVirtualRegister(Reg)) {
768 : if (const MachineFunction *MF = getMFIfAvailable(*this)) {
769 67804 : const MachineRegisterInfo &MRI = MF->getRegInfo();
770 88868 : if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
771 : OS << ':';
772 93798 : OS << printRegClassOrBank(Reg, MRI, TRI);
773 : }
774 : }
775 : }
776 : // Print ties.
777 210605 : if (ShouldPrintRegisterTies && isTied() && !isDef())
778 1608 : OS << "(tied-def " << TiedOperandIdx << ")";
779 : // Print types.
780 210605 : if (TypeToPrint.isValid())
781 : OS << '(' << TypeToPrint << ')';
782 : break;
783 : }
784 70982 : case MachineOperand::MO_Immediate:
785 70982 : OS << getImm();
786 70982 : break;
787 1090 : case MachineOperand::MO_CImmediate:
788 1090 : getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
789 1090 : break;
790 55 : case MachineOperand::MO_FPImmediate:
791 55 : getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
792 55 : break;
793 13465 : case MachineOperand::MO_MachineBasicBlock:
794 13465 : OS << printMBBReference(*getMBB());
795 13465 : break;
796 604 : case MachineOperand::MO_FrameIndex: {
797 604 : int FrameIndex = getIndex();
798 : bool IsFixed = false;
799 : const MachineFrameInfo *MFI = nullptr;
800 : if (const MachineFunction *MF = getMFIfAvailable(*this))
801 604 : MFI = &MF->getFrameInfo();
802 604 : printFrameIndex(OS, FrameIndex, IsFixed, MFI);
803 604 : break;
804 : }
805 96 : case MachineOperand::MO_ConstantPoolIndex:
806 96 : OS << "%const." << getIndex();
807 192 : printOperandOffset(OS, getOffset());
808 96 : break;
809 4 : case MachineOperand::MO_TargetIndex: {
810 4 : OS << "target-index(";
811 : const char *Name = "<unknown>";
812 : if (const MachineFunction *MF = getMFIfAvailable(*this))
813 2 : if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
814 : Name = TargetIndexName;
815 4 : OS << Name << ')';
816 8 : printOperandOffset(OS, getOffset());
817 4 : break;
818 : }
819 2458 : case MachineOperand::MO_JumpTableIndex:
820 2458 : OS << printJumpTableEntryReference(getIndex());
821 2458 : break;
822 8246 : case MachineOperand::MO_GlobalAddress:
823 8246 : getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
824 16492 : printOperandOffset(OS, getOffset());
825 8246 : break;
826 551 : case MachineOperand::MO_ExternalSymbol: {
827 551 : StringRef Name = getSymbolName();
828 : OS << '&';
829 551 : if (Name.empty()) {
830 12 : OS << "\"\"";
831 : } else {
832 539 : printLLVMNameWithoutPrefix(OS, Name);
833 : }
834 1102 : printOperandOffset(OS, getOffset());
835 : break;
836 : }
837 21 : case MachineOperand::MO_BlockAddress: {
838 21 : OS << "blockaddress(";
839 42 : getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
840 : MST);
841 21 : OS << ", ";
842 42 : printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
843 : OS << ')';
844 42 : MachineOperand::printOperandOffset(OS, getOffset());
845 21 : break;
846 : }
847 7057 : case MachineOperand::MO_RegisterMask: {
848 7057 : OS << "<regmask";
849 7057 : if (TRI) {
850 : unsigned NumRegsInMask = 0;
851 : unsigned NumRegsEmitted = 0;
852 4635754 : for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
853 4628698 : unsigned MaskWord = i / 32;
854 4628698 : unsigned MaskBit = i % 32;
855 4628698 : if (getRegMask()[MaskWord] & (1 << MaskBit)) {
856 673146 : if (PrintRegMaskNumRegs < 0 ||
857 673146 : NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
858 232701 : OS << " " << printReg(i, TRI);
859 232701 : NumRegsEmitted++;
860 : }
861 673146 : NumRegsInMask++;
862 : }
863 : }
864 7056 : if (NumRegsEmitted != NumRegsInMask)
865 7043 : OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
866 : } else {
867 1 : OS << " ...";
868 : }
869 7057 : OS << ">";
870 7057 : break;
871 : }
872 2 : case MachineOperand::MO_RegisterLiveOut: {
873 2 : const uint32_t *RegMask = getRegLiveOut();
874 2 : OS << "liveout(";
875 2 : if (!TRI) {
876 1 : OS << "<unknown>";
877 : } else {
878 : bool IsCommaNeeded = false;
879 278 : for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
880 277 : if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
881 4 : if (IsCommaNeeded)
882 3 : OS << ", ";
883 8 : OS << printReg(Reg, TRI);
884 : IsCommaNeeded = true;
885 : }
886 : }
887 : }
888 2 : OS << ")";
889 2 : break;
890 : }
891 2090 : case MachineOperand::MO_Metadata:
892 2090 : getMetadata()->printAsOperand(OS, MST);
893 2090 : break;
894 19 : case MachineOperand::MO_MCSymbol:
895 19 : printSymbol(OS, *getMCSymbol());
896 19 : break;
897 : case MachineOperand::MO_CFIIndex: {
898 : if (const MachineFunction *MF = getMFIfAvailable(*this))
899 2422 : printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
900 : else
901 1 : OS << "<cfi directive>";
902 : break;
903 : }
904 51 : case MachineOperand::MO_IntrinsicID: {
905 51 : Intrinsic::ID ID = getIntrinsicID();
906 51 : if (ID < Intrinsic::num_intrinsics)
907 100 : OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
908 1 : else if (IntrinsicInfo)
909 0 : OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
910 : else
911 1 : OS << "intrinsic(" << ID << ')';
912 : break;
913 : }
914 288 : case MachineOperand::MO_Predicate: {
915 288 : auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
916 418 : OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
917 288 : << CmpInst::getPredicateName(Pred) << ')';
918 : break;
919 : }
920 : }
921 318896 : }
922 :
923 : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
924 : LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
925 : #endif
926 :
927 : //===----------------------------------------------------------------------===//
928 : // MachineMemOperand Implementation
929 : //===----------------------------------------------------------------------===//
930 :
931 : /// getAddrSpace - Return the LLVM IR address space number that this pointer
932 : /// points into.
933 48227963 : unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
934 :
935 : /// isDereferenceable - Return true if V is always dereferenceable for
936 : /// Offset + Size byte.
937 110766 : bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
938 : const DataLayout &DL) const {
939 110766 : if (!V.is<const Value *>())
940 : return false;
941 :
942 : const Value *BasePtr = V.get<const Value *>();
943 110766 : if (BasePtr == nullptr)
944 : return false;
945 :
946 104658 : return isDereferenceableAndAlignedPointer(
947 209316 : BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
948 : }
949 :
950 : /// getConstantPool - Return a MachinePointerInfo record that refers to the
951 : /// constant pool.
952 36042 : MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
953 36042 : return MachinePointerInfo(MF.getPSVManager().getConstantPool());
954 : }
955 :
956 : /// getFixedStack - Return a MachinePointerInfo record that refers to the
957 : /// the specified FrameIndex.
958 3233408 : MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
959 : int FI, int64_t Offset) {
960 3233408 : return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
961 : }
962 :
963 3197 : MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
964 3197 : return MachinePointerInfo(MF.getPSVManager().getJumpTable());
965 : }
966 :
967 16300 : MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
968 16300 : return MachinePointerInfo(MF.getPSVManager().getGOT());
969 : }
970 :
971 173711 : MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
972 : int64_t Offset, uint8_t ID) {
973 173711 : return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
974 : }
975 :
976 1943 : MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
977 1943 : return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
978 : }
979 :
980 19487240 : MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
981 : uint64_t s, uint64_t a,
982 : const AAMDNodes &AAInfo,
983 : const MDNode *Ranges, SyncScope::ID SSID,
984 : AtomicOrdering Ordering,
985 19487240 : AtomicOrdering FailureOrdering)
986 38974480 : : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
987 19487240 : AAInfo(AAInfo), Ranges(Ranges) {
988 : assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
989 : isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
990 : "invalid pointer value");
991 : assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
992 : assert((isLoad() || isStore()) && "Not a load/store!");
993 :
994 19487240 : AtomicInfo.SSID = static_cast<unsigned>(SSID);
995 : assert(getSyncScopeID() == SSID && "Value truncated");
996 19487240 : AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
997 : assert(getOrdering() == Ordering && "Value truncated");
998 19487240 : AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
999 : assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1000 19487240 : }
1001 :
1002 : /// Profile - Gather unique data for the object.
1003 : ///
1004 0 : void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1005 0 : ID.AddInteger(getOffset());
1006 0 : ID.AddInteger(Size);
1007 0 : ID.AddPointer(getOpaqueValue());
1008 0 : ID.AddInteger(getFlags());
1009 0 : ID.AddInteger(getBaseAlignment());
1010 0 : }
1011 :
1012 167741 : void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1013 : // The Value and Offset may differ due to CSE. But the flags and size
1014 : // should be the same.
1015 : assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1016 : assert(MMO->getSize() == getSize() && "Size mismatch!");
1017 :
1018 503223 : if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1019 : // Update the alignment value.
1020 167727 : BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1021 : // Also update the base and offset, because the new alignment may
1022 : // not be applicable with the old ones.
1023 167727 : PtrInfo = MMO->PtrInfo;
1024 : }
1025 167741 : }
1026 :
1027 : /// getAlignment - Return the minimum known alignment in bytes of the
1028 : /// actual memory reference.
1029 41505627 : uint64_t MachineMemOperand::getAlignment() const {
1030 83011254 : return MinAlign(getBaseAlignment(), getOffset());
1031 : }
1032 :
1033 0 : void MachineMemOperand::print(raw_ostream &OS) const {
1034 0 : ModuleSlotTracker DummyMST(nullptr);
1035 0 : print(OS, DummyMST);
1036 0 : }
1037 :
1038 0 : void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
1039 : SmallVector<StringRef, 0> SSNs;
1040 0 : LLVMContext Ctx;
1041 0 : print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1042 0 : }
1043 :
1044 6545 : void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1045 : SmallVectorImpl<StringRef> &SSNs,
1046 : const LLVMContext &Context,
1047 : const MachineFrameInfo *MFI,
1048 : const TargetInstrInfo *TII) const {
1049 : OS << '(';
1050 13090 : if (isVolatile())
1051 338 : OS << "volatile ";
1052 13090 : if (isNonTemporal())
1053 134 : OS << "non-temporal ";
1054 13090 : if (isDereferenceable())
1055 745 : OS << "dereferenceable ";
1056 13090 : if (isInvariant())
1057 446 : OS << "invariant ";
1058 13090 : if (getFlags() & MachineMemOperand::MOTargetFlag1)
1059 2 : OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1060 2 : << "\" ";
1061 13090 : if (getFlags() & MachineMemOperand::MOTargetFlag2)
1062 21 : OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1063 21 : << "\" ";
1064 13090 : if (getFlags() & MachineMemOperand::MOTargetFlag3)
1065 0 : OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1066 0 : << "\" ";
1067 :
1068 : assert((isLoad() || isStore()) &&
1069 : "machine memory operand must be a load or store (or both)");
1070 13090 : if (isLoad())
1071 4122 : OS << "load ";
1072 13090 : if (isStore())
1073 2464 : OS << "store ";
1074 :
1075 6545 : printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1076 :
1077 6545 : if (getOrdering() != AtomicOrdering::NotAtomic)
1078 161 : OS << toIRString(getOrdering()) << ' ';
1079 6545 : if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1080 4 : OS << toIRString(getFailureOrdering()) << ' ';
1081 :
1082 6545 : if (getSize() == MemoryLocation::UnknownSize)
1083 2 : OS << "unknown-size";
1084 : else
1085 6543 : OS << getSize();
1086 :
1087 2989 : if (const Value *Val = getValue()) {
1088 6385 : OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1089 2607 : printIRValueReference(OS, *Val, MST);
1090 3556 : } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1091 8184 : OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1092 : assert(PVal && "Expected a pseudo source value");
1093 3556 : switch (PVal->kind()) {
1094 161 : case PseudoSourceValue::Stack:
1095 161 : OS << "stack";
1096 161 : break;
1097 25 : case PseudoSourceValue::GOT:
1098 25 : OS << "got";
1099 25 : break;
1100 1228 : case PseudoSourceValue::JumpTable:
1101 1228 : OS << "jump-table";
1102 1228 : break;
1103 59 : case PseudoSourceValue::ConstantPool:
1104 59 : OS << "constant-pool";
1105 59 : break;
1106 : case PseudoSourceValue::FixedStack: {
1107 2068 : int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1108 : bool IsFixed = true;
1109 2068 : printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1110 2068 : break;
1111 : }
1112 8 : case PseudoSourceValue::GlobalValueCallEntry:
1113 8 : OS << "call-entry ";
1114 8 : cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1115 : OS, /*PrintType=*/false, MST);
1116 8 : break;
1117 6 : case PseudoSourceValue::ExternalSymbolCallEntry:
1118 6 : OS << "call-entry &";
1119 12 : printLLVMNameWithoutPrefix(
1120 : OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1121 6 : break;
1122 1 : case PseudoSourceValue::TargetCustom:
1123 : // FIXME: This is not necessarily the correct MIR serialization format for
1124 : // a custom pseudo source value, but at least it allows
1125 : // -print-machineinstrs to work on a target with custom pseudo source
1126 : // values.
1127 1 : OS << "custom ";
1128 1 : PVal->printCustom(OS);
1129 1 : break;
1130 : }
1131 : }
1132 6545 : MachineOperand::printOperandOffset(OS, getOffset());
1133 13090 : if (getBaseAlignment() != getSize())
1134 931 : OS << ", align " << getBaseAlignment();
1135 : auto AAInfo = getAAInfo();
1136 6545 : if (AAInfo.TBAA) {
1137 791 : OS << ", !tbaa ";
1138 791 : AAInfo.TBAA->printAsOperand(OS, MST);
1139 : }
1140 6545 : if (AAInfo.Scope) {
1141 1 : OS << ", !alias.scope ";
1142 1 : AAInfo.Scope->printAsOperand(OS, MST);
1143 : }
1144 6545 : if (AAInfo.NoAlias) {
1145 1 : OS << ", !noalias ";
1146 1 : AAInfo.NoAlias->printAsOperand(OS, MST);
1147 : }
1148 6545 : if (getRanges()) {
1149 1 : OS << ", !range ";
1150 1 : getRanges()->printAsOperand(OS, MST);
1151 : }
1152 : // FIXME: Implement addrspace printing/parsing in MIR.
1153 : // For now, print this even though parsing it is not available in MIR.
1154 6545 : if (unsigned AS = getAddrSpace())
1155 695 : OS << ", addrspace " << AS;
1156 :
1157 : OS << ')';
1158 6545 : }
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