LCOV - code coverage report
Current view: top level - lib/CodeGen - MachineRegisterInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 249 257 96.9 %
Date: 2017-09-14 15:23:50 Functions: 37 40 92.5 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // Implementation of the MachineRegisterInfo class.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      15             : #include "llvm/ADT/iterator_range.h"
      16             : #include "llvm/CodeGen/LowLevelType.h"
      17             : #include "llvm/CodeGen/MachineBasicBlock.h"
      18             : #include "llvm/CodeGen/MachineFunction.h"
      19             : #include "llvm/CodeGen/MachineInstr.h"
      20             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      21             : #include "llvm/CodeGen/MachineOperand.h"
      22             : #include "llvm/IR/Attributes.h"
      23             : #include "llvm/IR/DebugLoc.h"
      24             : #include "llvm/IR/Function.h"
      25             : #include "llvm/MC/MCRegisterInfo.h"
      26             : #include "llvm/Support/Casting.h"
      27             : #include "llvm/Support/CommandLine.h"
      28             : #include "llvm/Support/Compiler.h"
      29             : #include "llvm/Support/ErrorHandling.h"
      30             : #include "llvm/Support/raw_ostream.h"
      31             : #include "llvm/Target/TargetInstrInfo.h"
      32             : #include "llvm/Target/TargetRegisterInfo.h"
      33             : #include "llvm/Target/TargetSubtargetInfo.h"
      34             : #include <cassert>
      35             : 
      36             : using namespace llvm;
      37             : 
      38       72306 : static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
      39      216918 :   cl::init(true), cl::desc("Enable subregister liveness tracking."));
      40             : 
      41             : // Pin the vtable to this file.
      42           0 : void MachineRegisterInfo::Delegate::anchor() {}
      43             : 
      44      145510 : MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
      45      165121 :     : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
      46       19611 :                                    EnableSubRegLiveness),
      47     1455100 :       IsUpdatedCSRsInitialized(false) {
      48      291020 :   unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
      49      291020 :   VRegInfo.reserve(256);
      50      291020 :   RegAllocHints.reserve(256);
      51      145510 :   UsedPhysRegMask.resize(NumRegs);
      52      291020 :   PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
      53      145510 : }
      54             : 
      55             : /// setRegClass - Set the register class of the specified virtual register.
      56             : ///
      57             : void
      58      413184 : MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
      59             :   assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
      60     1239552 :   VRegInfo[Reg].first = RC;
      61      413184 : }
      62             : 
      63        4939 : void MachineRegisterInfo::setRegBank(unsigned Reg,
      64             :                                      const RegisterBank &RegBank) {
      65       14817 :   VRegInfo[Reg].first = &RegBank;
      66        4939 : }
      67             : 
      68             : const TargetRegisterClass *
      69     2123130 : MachineRegisterInfo::constrainRegClass(unsigned Reg,
      70             :                                        const TargetRegisterClass *RC,
      71             :                                        unsigned MinNumRegs) {
      72     2123130 :   const TargetRegisterClass *OldRC = getRegClass(Reg);
      73     2123130 :   if (OldRC == RC)
      74             :     return RC;
      75             :   const TargetRegisterClass *NewRC =
      76      872404 :     getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
      77      436202 :   if (!NewRC || NewRC == OldRC)
      78             :     return NewRC;
      79      254644 :   if (NewRC->getNumRegs() < MinNumRegs)
      80             :     return nullptr;
      81      127286 :   setRegClass(Reg, NewRC);
      82      127286 :   return NewRC;
      83             : }
      84             : 
      85             : bool
      86      127902 : MachineRegisterInfo::recomputeRegClass(unsigned Reg) {
      87      127902 :   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
      88      127902 :   const TargetRegisterClass *OldRC = getRegClass(Reg);
      89             :   const TargetRegisterClass *NewRC =
      90      255804 :       getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF);
      91             : 
      92             :   // Stop early if there is no room to grow.
      93      127902 :   if (NewRC == OldRC)
      94             :     return false;
      95             : 
      96             :   // Accumulate constraints from all uses.
      97       78474 :   for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
      98             :     // Apply the effect of the given operand to NewRC.
      99       48517 :     MachineInstr *MI = MO.getParent();
     100       48517 :     unsigned OpNo = &MO - &MI->getOperand(0);
     101       97034 :     NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
     102             :                                             getTargetRegisterInfo());
     103       48517 :     if (!NewRC || NewRC == OldRC)
     104             :       return false;
     105             :   }
     106        5948 :   setRegClass(Reg, NewRC);
     107        5948 :   return true;
     108             : }
     109             : 
     110     2513586 : unsigned MachineRegisterInfo::createIncompleteVirtualRegister() {
     111     5027172 :   unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
     112     2513586 :   VRegInfo.grow(Reg);
     113     2513586 :   RegAllocHints.grow(Reg);
     114     2513586 :   return Reg;
     115             : }
     116             : 
     117             : /// createVirtualRegister - Create and return a new virtual register in the
     118             : /// function with the specified register class.
     119             : ///
     120             : unsigned
     121     2499988 : MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
     122             :   assert(RegClass && "Cannot create register without RegClass!");
     123             :   assert(RegClass->isAllocatable() &&
     124             :          "Virtual register RegClass must be allocatable.");
     125             : 
     126             :   // New virtual register number.
     127     2499988 :   unsigned Reg = createIncompleteVirtualRegister();
     128     7499964 :   VRegInfo[Reg].first = RegClass;
     129     2499988 :   if (TheDelegate)
     130      118065 :     TheDelegate->MRI_NoteNewVirtualRegister(Reg);
     131     2499988 :   return Reg;
     132             : }
     133             : 
     134      120816 : LLT MachineRegisterInfo::getType(unsigned VReg) const {
     135      241632 :   VRegToTypeMap::const_iterator TypeIt = getVRegToType().find(VReg);
     136      483264 :   return TypeIt != getVRegToType().end() ? TypeIt->second : LLT{};
     137             : }
     138             : 
     139        7196 : void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
     140             :   // Check that VReg doesn't have a class.
     141             :   assert((getRegClassOrRegBank(VReg).isNull() ||
     142             :          !getRegClassOrRegBank(VReg).is<const TargetRegisterClass *>()) &&
     143             :          "Can't set the size of a non-generic virtual register");
     144       14392 :   getVRegToType()[VReg] = Ty;
     145        7196 : }
     146             : 
     147             : unsigned
     148        6136 : MachineRegisterInfo::createGenericVirtualRegister(LLT Ty) {
     149             :   // New virtual register number.
     150        6136 :   unsigned Reg = createIncompleteVirtualRegister();
     151             :   // FIXME: Should we use a dummy register class?
     152       18408 :   VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
     153       12272 :   getVRegToType()[Reg] = Ty;
     154        6136 :   if (TheDelegate)
     155           0 :     TheDelegate->MRI_NoteNewVirtualRegister(Reg);
     156        6136 :   return Reg;
     157             : }
     158             : 
     159           0 : void MachineRegisterInfo::clearVirtRegTypes() {
     160           0 :   getVRegToType().clear();
     161           0 : }
     162             : 
     163             : /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
     164      194816 : void MachineRegisterInfo::clearVirtRegs() {
     165             : #ifndef NDEBUG
     166             :   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
     167             :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
     168             :     if (!VRegInfo[Reg].second)
     169             :       continue;
     170             :     verifyUseList(Reg);
     171             :     llvm_unreachable("Remaining virtual register operands");
     172             :   }
     173             : #endif
     174      389632 :   VRegInfo.clear();
     175     1088851 :   for (auto &I : LiveIns)
     176      309587 :     I.second = 0;
     177      194816 : }
     178             : 
     179           0 : void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
     180             : #ifndef NDEBUG
     181             :   bool Valid = true;
     182             :   for (MachineOperand &M : reg_operands(Reg)) {
     183             :     MachineOperand *MO = &M;
     184             :     MachineInstr *MI = MO->getParent();
     185             :     if (!MI) {
     186             :       errs() << PrintReg(Reg, getTargetRegisterInfo())
     187             :              << " use list MachineOperand " << MO
     188             :              << " has no parent instruction.\n";
     189             :       Valid = false;
     190             :       continue;
     191             :     }
     192             :     MachineOperand *MO0 = &MI->getOperand(0);
     193             :     unsigned NumOps = MI->getNumOperands();
     194             :     if (!(MO >= MO0 && MO < MO0+NumOps)) {
     195             :       errs() << PrintReg(Reg, getTargetRegisterInfo())
     196             :              << " use list MachineOperand " << MO
     197             :              << " doesn't belong to parent MI: " << *MI;
     198             :       Valid = false;
     199             :     }
     200             :     if (!MO->isReg()) {
     201             :       errs() << PrintReg(Reg, getTargetRegisterInfo())
     202             :              << " MachineOperand " << MO << ": " << *MO
     203             :              << " is not a register\n";
     204             :       Valid = false;
     205             :     }
     206             :     if (MO->getReg() != Reg) {
     207             :       errs() << PrintReg(Reg, getTargetRegisterInfo())
     208             :              << " use-list MachineOperand " << MO << ": "
     209             :              << *MO << " is the wrong register\n";
     210             :       Valid = false;
     211             :     }
     212             :   }
     213             :   assert(Valid && "Invalid use list");
     214             : #endif
     215           0 : }
     216             : 
     217     1128039 : void MachineRegisterInfo::verifyUseLists() const {
     218             : #ifndef NDEBUG
     219             :   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
     220             :     verifyUseList(TargetRegisterInfo::index2VirtReg(i));
     221             :   for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
     222             :     verifyUseList(i);
     223             : #endif
     224     1128039 : }
     225             : 
     226             : /// Add MO to the linked list of operands for its register.
     227    23004467 : void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
     228             :   assert(!MO->isOnRegUseList() && "Already on list");
     229    46008934 :   MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
     230    23004467 :   MachineOperand *const Head = HeadRef;
     231             : 
     232             :   // Head points to the first list element.
     233             :   // Next is NULL on the last list element.
     234             :   // Prev pointers are circular, so Head->Prev == Last.
     235             : 
     236             :   // Head is NULL for an empty list.
     237    23004467 :   if (!Head) {
     238     4070625 :     MO->Contents.Reg.Prev = MO;
     239     4070625 :     MO->Contents.Reg.Next = nullptr;
     240     4070625 :     HeadRef = MO;
     241     4070625 :     return;
     242             :   }
     243             :   assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
     244             : 
     245             :   // Insert MO between Last and Head in the circular Prev chain.
     246    18933842 :   MachineOperand *Last = Head->Contents.Reg.Prev;
     247             :   assert(Last && "Inconsistent use list");
     248             :   assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
     249    18933842 :   Head->Contents.Reg.Prev = MO;
     250    18933842 :   MO->Contents.Reg.Prev = Last;
     251             : 
     252             :   // Def operands always precede uses. This allows def_iterator to stop early.
     253             :   // Insert def operands at the front, and use operands at the back.
     254    18933842 :   if (MO->isDef()) {
     255             :     // Insert def at the front.
     256     5316870 :     MO->Contents.Reg.Next = Head;
     257     5316870 :     HeadRef = MO;
     258             :   } else {
     259             :     // Insert use at the end.
     260    13616972 :     MO->Contents.Reg.Next = nullptr;
     261    13616972 :     Last->Contents.Reg.Next = MO;
     262             :   }
     263             : }
     264             : 
     265             : /// Remove MO from its use-def list.
     266    14291560 : void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
     267             :   assert(MO->isOnRegUseList() && "Operand not on use list");
     268    28583120 :   MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
     269    14291560 :   MachineOperand *const Head = HeadRef;
     270             :   assert(Head && "List already empty");
     271             : 
     272             :   // Unlink this from the doubly linked list of operands.
     273    14291560 :   MachineOperand *Next = MO->Contents.Reg.Next;
     274    14291560 :   MachineOperand *Prev = MO->Contents.Reg.Prev;
     275             : 
     276             :   // Prev links are circular, next link is NULL instead of looping back to Head.
     277    14291560 :   if (MO == Head)
     278     7039907 :     HeadRef = Next;
     279             :   else
     280     7251653 :     Prev->Contents.Reg.Next = Next;
     281             : 
     282    14291560 :   (Next ? Next : Head)->Contents.Reg.Prev = Prev;
     283             : 
     284    14291560 :   MO->Contents.Reg.Prev = nullptr;
     285    14291560 :   MO->Contents.Reg.Next = nullptr;
     286    14291560 : }
     287             : 
     288             : /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
     289             : ///
     290             : /// The Dst range is assumed to be uninitialized memory. (Or it may contain
     291             : /// operands that won't be destroyed, which is OK because the MO destructor is
     292             : /// trivial anyway).
     293             : ///
     294             : /// The Src and Dst ranges may overlap.
     295     1919359 : void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
     296             :                                        MachineOperand *Src,
     297             :                                        unsigned NumOps) {
     298             :   assert(Src != Dst && NumOps && "Noop moveOperands");
     299             : 
     300             :   // Copy backwards if Dst is within the Src range.
     301     1919359 :   int Stride = 1;
     302     1919359 :   if (Dst >= Src && Dst < Src + NumOps) {
     303      213195 :     Stride = -1;
     304      213195 :     Dst += NumOps - 1;
     305      213195 :     Src += NumOps - 1;
     306             :   }
     307             : 
     308             :   // Copy one operand at a time.
     309             :   do {
     310     3610616 :     new (Dst) MachineOperand(*Src);
     311             : 
     312             :     // Dst takes Src's place in the use-def chain.
     313     3610616 :     if (Src->isReg()) {
     314     6391488 :       MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
     315     3195744 :       MachineOperand *Prev = Src->Contents.Reg.Prev;
     316     3195744 :       MachineOperand *Next = Src->Contents.Reg.Next;
     317             :       assert(Head && "List empty, but operand is chained");
     318             :       assert(Prev && "Operand was not on use-def list");
     319             : 
     320             :       // Prev links are circular, next link is NULL instead of looping back to
     321             :       // Head.
     322     3195744 :       if (Src == Head)
     323     1321198 :         Head = Dst;
     324             :       else
     325     1874546 :         Prev->Contents.Reg.Next = Dst;
     326             : 
     327             :       // Update Prev pointer. This also works when Src was pointing to itself
     328             :       // in a 1-element list. In that case Head == Dst.
     329     3195744 :       (Next ? Next : Head)->Contents.Reg.Prev = Dst;
     330             :     }
     331             : 
     332     3610616 :     Dst += Stride;
     333     3610616 :     Src += Stride;
     334     3610616 :   } while (--NumOps);
     335     1919359 : }
     336             : 
     337             : /// replaceRegWith - Replace all instances of FromReg with ToReg in the
     338             : /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
     339             : /// except that it also changes any definitions of the register as well.
     340             : /// If ToReg is a physical register we apply the sub register to obtain the
     341             : /// final/proper physical register.
     342      271097 : void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
     343             :   assert(FromReg != ToReg && "Cannot replace a reg with itself");
     344             : 
     345      542194 :   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
     346             :   
     347             :   // TODO: This could be more efficient by bulk changing the operands.
     348      800953 :   for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
     349      529856 :     MachineOperand &O = *I;
     350      529856 :     ++I;
     351      529856 :     if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
     352       28406 :       O.substPhysReg(ToReg, *TRI);
     353             :     } else {
     354      501450 :       O.setReg(ToReg);
     355             :     }
     356             :   }
     357      271097 : }
     358             : 
     359             : /// getVRegDef - Return the machine instr that defines the specified virtual
     360             : /// register or null if none is found.  This assumes that the code is in SSA
     361             : /// form, so there should only be one definition.
     362     5990387 : MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
     363             :   // Since we are in SSA form, we can use the first definition.
     364     5990387 :   def_instr_iterator I = def_instr_begin(Reg);
     365             :   assert((I.atEnd() || std::next(I) == def_instr_end()) &&
     366             :          "getVRegDef assumes a single definition or no definition");
     367    11962343 :   return !I.atEnd() ? &*I : nullptr;
     368             : }
     369             : 
     370             : /// getUniqueVRegDef - Return the unique machine instr that defines the
     371             : /// specified virtual register or null if none is found.  If there are
     372             : /// multiple definitions or no definition, return null.
     373      365314 : MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
     374      365314 :   if (def_empty(Reg)) return nullptr;
     375      364279 :   def_instr_iterator I = def_instr_begin(Reg);
     376      728558 :   if (std::next(I) != def_instr_end())
     377             :     return nullptr;
     378      364277 :   return &*I;
     379             : }
     380             : 
     381     3424319 : bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
     382     3424319 :   use_nodbg_iterator UI = use_nodbg_begin(RegNo);
     383     3424319 :   if (UI == use_nodbg_end())
     384             :     return false;
     385    10254570 :   return ++UI == use_nodbg_end();
     386             : }
     387             : 
     388             : /// clearKillFlags - Iterate over all the uses of the given register and
     389             : /// clear the kill flag from the MachineOperand. This function is used by
     390             : /// optimization passes which extend register lifetimes and need only
     391             : /// preserve conservative kill flag information.
     392     1404812 : void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
     393     9120559 :   for (MachineOperand &MO : use_operands(Reg))
     394     6310935 :     MO.setIsKill(false);
     395     1404812 : }
     396             : 
     397      120840 : bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
     398      502966 :   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
     399      144693 :     if (I->first == Reg || I->second == Reg)
     400             :       return true;
     401             :   return false;
     402             : }
     403             : 
     404             : /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
     405             : /// corresponding live-in physical register.
     406         936 : unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
     407        3826 :   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
     408        1944 :     if (I->second == VReg)
     409         926 :       return I->first;
     410             :   return 0;
     411             : }
     412             : 
     413             : /// getLiveInVirtReg - If PReg is a live-in physical register, return the
     414             : /// corresponding live-in physical register.
     415      266536 : unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
     416     1129334 :   for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
     417      365143 :     if (I->first == PReg)
     418       35417 :       return I->second;
     419             :   return 0;
     420             : }
     421             : 
     422             : /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
     423             : /// into the given entry block.
     424             : void
     425      142254 : MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
     426             :                                       const TargetRegisterInfo &TRI,
     427             :                                       const TargetInstrInfo &TII) {
     428             :   // Emit the copies into the top of the block.
     429      554303 :   for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
     430      539590 :     if (LiveIns[i].second) {
     431      539586 :       if (use_empty(LiveIns[i].second)) {
     432             :         // The livein has no uses. Drop it.
     433             :         //
     434             :         // It would be preferable to have isel avoid creating live-in
     435             :         // records for unused arguments in the first place, but it's
     436             :         // complicated by the debug info code for arguments.
     437      281745 :         LiveIns.erase(LiveIns.begin() + i);
     438       56349 :         --i; --e;
     439             :       } else {
     440             :         // Emit a copy.
     441     1067220 :         BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
     442      853776 :                 TII.get(TargetOpcode::COPY), LiveIns[i].second)
     443      426888 :           .addReg(LiveIns[i].first);
     444             : 
     445             :         // Add the register to the entry block live-in set.
     446      426888 :         EntryMBB->addLiveIn(LiveIns[i].first);
     447             :       }
     448             :     } else {
     449             :       // Add the register to the entry block live-in set.
     450           2 :       EntryMBB->addLiveIn(LiveIns[i].first);
     451             :     }
     452      142254 : }
     453             : 
     454    10860298 : LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const {
     455             :   // Lane masks are only defined for vregs.
     456             :   assert(TargetRegisterInfo::isVirtualRegister(Reg));
     457    10860298 :   const TargetRegisterClass &TRC = *getRegClass(Reg);
     458    10860298 :   return TRC.getLaneMask();
     459             : }
     460             : 
     461             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     462             : LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(unsigned Reg) const {
     463             :   for (MachineInstr &I : use_instructions(Reg))
     464             :     I.dump();
     465             : }
     466             : #endif
     467             : 
     468      286924 : void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
     469     1147696 :   ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
     470             :   assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
     471             :          "Invalid ReservedRegs vector from target");
     472      286924 : }
     473             : 
     474     6260711 : bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
     475             :   assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
     476             : 
     477    12521422 :   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
     478     6260711 :   if (TRI->isConstantPhysReg(PhysReg))
     479             :     return true;
     480             : 
     481             :   // Check if any overlapping register is modified, or allocatable so it may be
     482             :   // used later.
     483    12436049 :   for (MCRegAliasIterator AI(PhysReg, TRI, true);
     484    18617381 :        AI.isValid(); ++AI)
     485    31210241 :     if (!def_empty(*AI) || isAllocatable(*AI))
     486     5294258 :       return false;
     487      960459 :   return true;
     488             : }
     489             : 
     490             : /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
     491             : /// specified register as undefined which causes the DBG_VALUE to be
     492             : /// deleted during LiveDebugVariables analysis.
     493      160457 : void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const {
     494             :   // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
     495      160457 :   MachineRegisterInfo::use_instr_iterator nextI;
     496      320914 :   for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end();
     497      161860 :        I != E; I = nextI) {
     498        1403 :     nextI = std::next(I);  // I is invalidated by the setReg
     499        1403 :     MachineInstr *UseMI = &*I;
     500        1403 :     if (UseMI->isDebugValue())
     501          10 :       UseMI->getOperand(0).setReg(0U);
     502             :   }
     503      160457 : }
     504             : 
     505             : static const Function *getCalledFunction(const MachineInstr &MI) {
     506       33177 :   for (const MachineOperand &MO : MI.operands()) {
     507       30063 :     if (!MO.isGlobal())
     508             :       continue;
     509        2470 :     const Function *Func = dyn_cast<Function>(MO.getGlobal());
     510             :     if (Func != nullptr)
     511             :       return Func;
     512             :   }
     513             :   return nullptr;
     514             : }
     515             : 
     516       37134 : static bool isNoReturnDef(const MachineOperand &MO) {
     517             :   // Anything which is not a noreturn function is a real def.
     518       37134 :   const MachineInstr &MI = *MO.getParent();
     519       37134 :   if (!MI.isCall())
     520             :     return false;
     521        6269 :   const MachineBasicBlock &MBB = *MI.getParent();
     522        6269 :   if (!MBB.succ_empty())
     523             :     return false;
     524        5596 :   const MachineFunction &MF = *MBB.getParent();
     525             :   // We need to keep correct unwind information even if the function will
     526             :   // not return, since the runtime may need it.
     527       11192 :   if (MF.getFunction()->hasFnAttribute(Attribute::UWTable))
     528             :     return false;
     529        5558 :   const Function *Called = getCalledFunction(MI);
     530        8038 :   return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
     531          36 :            !Called->hasFnAttribute(Attribute::NoUnwind));
     532             : }
     533             : 
     534     1778784 : bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg,
     535             :                                             bool SkipNoReturnDef) const {
     536     3557568 :   if (UsedPhysRegMask.test(PhysReg))
     537             :     return true;
     538     3553118 :   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
     539    38507480 :   for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
     540    70057182 :     for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
     541       37134 :       if (!SkipNoReturnDef && isNoReturnDef(MO))
     542             :         continue;
     543       37108 :       return true;
     544             :     }
     545             :   }
     546     1739451 :   return false;
     547             : }
     548             : 
     549     5761878 : bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
     550    11523756 :   if (UsedPhysRegMask.test(PhysReg))
     551             :     return true;
     552    11473618 :   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
     553   290269122 :   for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
     554   139397752 :        ++AliasReg) {
     555   278981610 :     if (!reg_nodbg_empty(*AliasReg))
     556       93053 :       return true;
     557             :   }
     558     5643756 :   return false;
     559             : }
     560             : 
     561         579 : void MachineRegisterInfo::disableCalleeSavedRegister(unsigned Reg) {
     562             : 
     563        1158 :   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
     564             :   assert(Reg && (Reg < TRI->getNumRegs()) &&
     565             :          "Trying to disable an invalid register");
     566             : 
     567         579 :   if (!IsUpdatedCSRsInitialized) {
     568         132 :     const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
     569        1984 :     for (const MCPhysReg *I = CSR; *I; ++I)
     570        1852 :       UpdatedCSRs.push_back(*I);
     571             : 
     572             :     // Zero value represents the end of the register list
     573             :     // (no more registers should be pushed).
     574         132 :     UpdatedCSRs.push_back(0);
     575             : 
     576         132 :     IsUpdatedCSRsInitialized = true;
     577             :   }
     578             : 
     579             :   // Remove the register (and its aliases from the list).
     580        6754 :   for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
     581       13990 :     UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI),
     582        5596 :                       UpdatedCSRs.end());
     583         579 : }
     584             : 
     585     2005175 : const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
     586     2005175 :   if (IsUpdatedCSRsInitialized)
     587        2536 :     return UpdatedCSRs.data();
     588             : 
     589     4007814 :   return getTargetRegisterInfo()->getCalleeSavedRegs(MF);
     590             : }
     591             : 
     592          17 : void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
     593          17 :   if (IsUpdatedCSRsInitialized)
     594           0 :     UpdatedCSRs.clear();
     595             : 
     596         771 :   for (MCPhysReg Reg : CSRs)
     597         737 :     UpdatedCSRs.push_back(Reg);
     598             : 
     599             :   // Zero value represents the end of the register list
     600             :   // (no more registers should be pushed).
     601          17 :   UpdatedCSRs.push_back(0);
     602          17 :   IsUpdatedCSRsInitialized = true;
     603          17 : }
     604             : 
     605      706557 : bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
     606     1413114 :   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
     607     1958803 :   for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
     608      706557 :     bool IsRootReserved = true;
     609      706557 :     for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
     610     1021606 :          Super.isValid(); ++Super) {
     611     1721476 :       unsigned Reg = *Super;
     612      860738 :       if (!isReserved(Reg)) {
     613             :         IsRootReserved = false;
     614             :         break;
     615             :       }
     616             :     }
     617      706557 :     if (IsRootReserved)
     618             :       return true;
     619             :   }
     620      545689 :   return false;
     621      216918 : }

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