LCOV - code coverage report
Current view: top level - lib/CodeGen - MachineVerifier.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 794 1141 69.6 %
Date: 2018-09-23 13:06:45 Functions: 46 57 80.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // Pass to verify generated machine code. The following is checked:
      11             : //
      12             : // Operand counts: All explicit operands must be present.
      13             : //
      14             : // Register classes: All physical and virtual register operands must be
      15             : // compatible with the register class required by the instruction descriptor.
      16             : //
      17             : // Register live intervals: Registers must be defined only once, and must be
      18             : // defined before use.
      19             : //
      20             : // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
      21             : // command-line option -verify-machineinstrs, or by defining the environment
      22             : // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
      23             : // the verifier errors.
      24             : //===----------------------------------------------------------------------===//
      25             : 
      26             : #include "LiveRangeCalc.h"
      27             : #include "llvm/ADT/BitVector.h"
      28             : #include "llvm/ADT/DenseMap.h"
      29             : #include "llvm/ADT/DenseSet.h"
      30             : #include "llvm/ADT/DepthFirstIterator.h"
      31             : #include "llvm/ADT/STLExtras.h"
      32             : #include "llvm/ADT/SetOperations.h"
      33             : #include "llvm/ADT/SmallPtrSet.h"
      34             : #include "llvm/ADT/SmallVector.h"
      35             : #include "llvm/ADT/StringRef.h"
      36             : #include "llvm/ADT/Twine.h"
      37             : #include "llvm/Analysis/EHPersonalities.h"
      38             : #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
      39             : #include "llvm/CodeGen/LiveInterval.h"
      40             : #include "llvm/CodeGen/LiveIntervals.h"
      41             : #include "llvm/CodeGen/LiveStacks.h"
      42             : #include "llvm/CodeGen/LiveVariables.h"
      43             : #include "llvm/CodeGen/MachineBasicBlock.h"
      44             : #include "llvm/CodeGen/MachineFrameInfo.h"
      45             : #include "llvm/CodeGen/MachineFunction.h"
      46             : #include "llvm/CodeGen/MachineFunctionPass.h"
      47             : #include "llvm/CodeGen/MachineInstr.h"
      48             : #include "llvm/CodeGen/MachineInstrBundle.h"
      49             : #include "llvm/CodeGen/MachineMemOperand.h"
      50             : #include "llvm/CodeGen/MachineOperand.h"
      51             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      52             : #include "llvm/CodeGen/PseudoSourceValue.h"
      53             : #include "llvm/CodeGen/SlotIndexes.h"
      54             : #include "llvm/CodeGen/StackMaps.h"
      55             : #include "llvm/CodeGen/TargetInstrInfo.h"
      56             : #include "llvm/CodeGen/TargetOpcodes.h"
      57             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      58             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      59             : #include "llvm/IR/BasicBlock.h"
      60             : #include "llvm/IR/Function.h"
      61             : #include "llvm/IR/InlineAsm.h"
      62             : #include "llvm/IR/Instructions.h"
      63             : #include "llvm/MC/LaneBitmask.h"
      64             : #include "llvm/MC/MCAsmInfo.h"
      65             : #include "llvm/MC/MCInstrDesc.h"
      66             : #include "llvm/MC/MCRegisterInfo.h"
      67             : #include "llvm/MC/MCTargetOptions.h"
      68             : #include "llvm/Pass.h"
      69             : #include "llvm/Support/Casting.h"
      70             : #include "llvm/Support/ErrorHandling.h"
      71             : #include "llvm/Support/LowLevelTypeImpl.h"
      72             : #include "llvm/Support/MathExtras.h"
      73             : #include "llvm/Support/raw_ostream.h"
      74             : #include "llvm/Target/TargetMachine.h"
      75             : #include <algorithm>
      76             : #include <cassert>
      77             : #include <cstddef>
      78             : #include <cstdint>
      79             : #include <iterator>
      80             : #include <string>
      81             : #include <utility>
      82             : 
      83             : using namespace llvm;
      84             : 
      85             : namespace {
      86             : 
      87             :   struct MachineVerifier {
      88     1631460 :     MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
      89             : 
      90             :     unsigned verify(MachineFunction &MF);
      91             : 
      92             :     Pass *const PASS;
      93             :     const char *Banner;
      94             :     const MachineFunction *MF;
      95             :     const TargetMachine *TM;
      96             :     const TargetInstrInfo *TII;
      97             :     const TargetRegisterInfo *TRI;
      98             :     const MachineRegisterInfo *MRI;
      99             : 
     100             :     unsigned foundErrors;
     101             : 
     102             :     // Avoid querying the MachineFunctionProperties for each operand.
     103             :     bool isFunctionRegBankSelected;
     104             :     bool isFunctionSelected;
     105             : 
     106             :     using RegVector = SmallVector<unsigned, 16>;
     107             :     using RegMaskVector = SmallVector<const uint32_t *, 4>;
     108             :     using RegSet = DenseSet<unsigned>;
     109             :     using RegMap = DenseMap<unsigned, const MachineInstr *>;
     110             :     using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
     111             : 
     112             :     const MachineInstr *FirstTerminator;
     113             :     BlockSet FunctionBlocks;
     114             : 
     115             :     BitVector regsReserved;
     116             :     RegSet regsLive;
     117             :     RegVector regsDefined, regsDead, regsKilled;
     118             :     RegMaskVector regMasks;
     119             : 
     120             :     SlotIndex lastIndex;
     121             : 
     122             :     // Add Reg and any sub-registers to RV
     123           0 :     void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
     124           0 :       RV.push_back(Reg);
     125           0 :       if (TargetRegisterInfo::isPhysicalRegister(Reg))
     126           0 :         for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
     127           0 :           RV.push_back(*SubRegs);
     128           0 :     }
     129             : 
     130             :     struct BBInfo {
     131             :       // Is this MBB reachable from the MF entry point?
     132             :       bool reachable = false;
     133             : 
     134             :       // Vregs that must be live in because they are used without being
     135             :       // defined. Map value is the user.
     136             :       RegMap vregsLiveIn;
     137             : 
     138             :       // Regs killed in MBB. They may be defined again, and will then be in both
     139             :       // regsKilled and regsLiveOut.
     140             :       RegSet regsKilled;
     141             : 
     142             :       // Regs defined in MBB and live out. Note that vregs passing through may
     143             :       // be live out without being mentioned here.
     144             :       RegSet regsLiveOut;
     145             : 
     146             :       // Vregs that pass through MBB untouched. This set is disjoint from
     147             :       // regsKilled and regsLiveOut.
     148             :       RegSet vregsPassed;
     149             : 
     150             :       // Vregs that must pass through MBB because they are needed by a successor
     151             :       // block. This set is disjoint from regsLiveOut.
     152             :       RegSet vregsRequired;
     153             : 
     154             :       // Set versions of block's predecessor and successor lists.
     155             :       BlockSet Preds, Succs;
     156             : 
     157     2024712 :       BBInfo() = default;
     158             : 
     159             :       // Add register to vregsPassed if it belongs there. Return true if
     160             :       // anything changed.
     161    17466902 :       bool addPassed(unsigned Reg) {
     162    34933804 :         if (!TargetRegisterInfo::isVirtualRegister(Reg))
     163             :           return false;
     164             :         if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
     165      345972 :           return false;
     166             :         return vregsPassed.insert(Reg).second;
     167             :       }
     168             : 
     169             :       // Same for a full set.
     170      758984 :       bool addPassed(const RegSet &RS) {
     171             :         bool changed = false;
     172    18225886 :         for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
     173    17466902 :           if (addPassed(*I))
     174             :             changed = true;
     175      758984 :         return changed;
     176             :       }
     177             : 
     178             :       // Add register to vregsRequired if it belongs there. Return true if
     179             :       // anything changed.
     180     1148472 :       bool addRequired(unsigned Reg) {
     181     2296944 :         if (!TargetRegisterInfo::isVirtualRegister(Reg))
     182             :           return false;
     183             :         if (regsLiveOut.count(Reg))
     184      445037 :           return false;
     185             :         return vregsRequired.insert(Reg).second;
     186             :       }
     187             : 
     188             :       // Same for a full set.
     189      115837 :       bool addRequired(const RegSet &RS) {
     190             :         bool changed = false;
     191      908379 :         for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
     192      792542 :           if (addRequired(*I))
     193             :             changed = true;
     194      115837 :         return changed;
     195             :       }
     196             : 
     197             :       // Same for a full map.
     198      557057 :       bool addRequired(const RegMap &RM) {
     199             :         bool changed = false;
     200      912987 :         for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
     201      355930 :           if (addRequired(I->first))
     202             :             changed = true;
     203      557057 :         return changed;
     204             :       }
     205             : 
     206             :       // Live-out registers are either in regsLiveOut or vregsPassed.
     207      167473 :       bool isLiveOut(unsigned Reg) const {
     208      167473 :         return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
     209             :       }
     210             :     };
     211             : 
     212             :     // Extra register info per MBB.
     213             :     DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
     214             : 
     215             :     bool isReserved(unsigned Reg) {
     216    12609124 :       return Reg < regsReserved.size() && regsReserved.test(Reg);
     217             :     }
     218             : 
     219     1114323 :     bool isAllocatable(unsigned Reg) const {
     220     1114323 :       return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
     221     1114323 :         !regsReserved.test(Reg);
     222             :     }
     223             : 
     224             :     // Analysis information if available
     225             :     LiveVariables *LiveVars;
     226             :     LiveIntervals *LiveInts;
     227             :     LiveStacks *LiveStks;
     228             :     SlotIndexes *Indexes;
     229             : 
     230             :     void visitMachineFunctionBefore();
     231             :     void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
     232             :     void visitMachineBundleBefore(const MachineInstr *MI);
     233             :     void visitMachineInstrBefore(const MachineInstr *MI);
     234             :     void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
     235             :     void visitMachineInstrAfter(const MachineInstr *MI);
     236             :     void visitMachineBundleAfter(const MachineInstr *MI);
     237             :     void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
     238             :     void visitMachineFunctionAfter();
     239             : 
     240             :     void report(const char *msg, const MachineFunction *MF);
     241             :     void report(const char *msg, const MachineBasicBlock *MBB);
     242             :     void report(const char *msg, const MachineInstr *MI);
     243             :     void report(const char *msg, const MachineOperand *MO, unsigned MONum,
     244             :                 LLT MOVRegType = LLT{});
     245             : 
     246             :     void report_context(const LiveInterval &LI) const;
     247             :     void report_context(const LiveRange &LR, unsigned VRegUnit,
     248             :                         LaneBitmask LaneMask) const;
     249             :     void report_context(const LiveRange::Segment &S) const;
     250             :     void report_context(const VNInfo &VNI) const;
     251             :     void report_context(SlotIndex Pos) const;
     252             :     void report_context_liverange(const LiveRange &LR) const;
     253             :     void report_context_lanemask(LaneBitmask LaneMask) const;
     254             :     void report_context_vreg(unsigned VReg) const;
     255             :     void report_context_vreg_regunit(unsigned VRegOrUnit) const;
     256             : 
     257             :     void verifyInlineAsm(const MachineInstr *MI);
     258             : 
     259             :     void checkLiveness(const MachineOperand *MO, unsigned MONum);
     260             :     void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
     261             :                             SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
     262             :                             LaneBitmask LaneMask = LaneBitmask::getNone());
     263             :     void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
     264             :                             SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
     265             :                             bool SubRangeCheck = false,
     266             :                             LaneBitmask LaneMask = LaneBitmask::getNone());
     267             : 
     268             :     void markReachable(const MachineBasicBlock *MBB);
     269             :     void calcRegsPassed();
     270             :     void checkPHIOps(const MachineBasicBlock &MBB);
     271             : 
     272             :     void calcRegsRequired();
     273             :     void verifyLiveVariables();
     274             :     void verifyLiveIntervals();
     275             :     void verifyLiveInterval(const LiveInterval&);
     276             :     void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
     277             :                               LaneBitmask);
     278             :     void verifyLiveRangeSegment(const LiveRange&,
     279             :                                 const LiveRange::const_iterator I, unsigned,
     280             :                                 LaneBitmask);
     281             :     void verifyLiveRange(const LiveRange&, unsigned,
     282             :                          LaneBitmask LaneMask = LaneBitmask::getNone());
     283             : 
     284             :     void verifyStackFrame();
     285             : 
     286             :     void verifySlotIndexes() const;
     287             :     void verifyProperties(const MachineFunction &MF);
     288             :   };
     289             : 
     290             :   struct MachineVerifierPass : public MachineFunctionPass {
     291             :     static char ID; // Pass ID, replacement for typeid
     292             : 
     293             :     const std::string Banner;
     294             : 
     295      162930 :     MachineVerifierPass(std::string banner = std::string())
     296      162930 :       : MachineFunctionPass(ID), Banner(std::move(banner)) {
     297      162930 :         initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
     298      162930 :       }
     299             : 
     300      162930 :     void getAnalysisUsage(AnalysisUsage &AU) const override {
     301             :       AU.setPreservesAll();
     302      162930 :       MachineFunctionPass::getAnalysisUsage(AU);
     303      162930 :     }
     304             : 
     305     1626933 :     bool runOnMachineFunction(MachineFunction &MF) override {
     306     1626933 :       unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
     307     1626933 :       if (FoundErrors)
     308           3 :         report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
     309     1626930 :       return false;
     310             :     }
     311             :   };
     312             : 
     313             : } // end anonymous namespace
     314             : 
     315             : char MachineVerifierPass::ID = 0;
     316             : 
     317      249803 : INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
     318             :                 "Verify generated machine code", false, false)
     319             : 
     320      162929 : FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
     321      162929 :   return new MachineVerifierPass(Banner);
     322             : }
     323             : 
     324        4527 : bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
     325             :     const {
     326             :   MachineFunction &MF = const_cast<MachineFunction&>(*this);
     327        4527 :   unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
     328        4527 :   if (AbortOnErrors && FoundErrors)
     329          37 :     report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
     330        4490 :   return FoundErrors == 0;
     331             : }
     332             : 
     333           0 : void MachineVerifier::verifySlotIndexes() const {
     334             :   if (Indexes == nullptr)
     335           0 :     return;
     336             : 
     337             :   // Ensure the IdxMBB list is sorted by slot indexes.
     338             :   SlotIndex Last;
     339             :   for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
     340             :        E = Indexes->MBBIndexEnd(); I != E; ++I) {
     341             :     assert(!Last.isValid() || I->first > Last);
     342             :     Last = I->first;
     343             :   }
     344             : }
     345             : 
     346     1631460 : void MachineVerifier::verifyProperties(const MachineFunction &MF) {
     347             :   // If a pass has introduced virtual registers without clearing the
     348             :   // NoVRegs property (or set it without allocating the vregs)
     349             :   // then report an error.
     350             :   if (MF.getProperties().hasProperty(
     351     1631460 :           MachineFunctionProperties::Property::NoVRegs) &&
     352      819633 :       MRI->getNumVirtRegs())
     353           0 :     report("Function has NoVRegs property but there are VReg operands", &MF);
     354     1631460 : }
     355             : 
     356     1631460 : unsigned MachineVerifier::verify(MachineFunction &MF) {
     357     1631460 :   foundErrors = 0;
     358             : 
     359     1631460 :   this->MF = &MF;
     360     1631460 :   TM = &MF.getTarget();
     361     1631460 :   TII = MF.getSubtarget().getInstrInfo();
     362     1631460 :   TRI = MF.getSubtarget().getRegisterInfo();
     363     1631460 :   MRI = &MF.getRegInfo();
     364             : 
     365             :   const bool isFunctionFailedISel = MF.getProperties().hasProperty(
     366             :       MachineFunctionProperties::Property::FailedISel);
     367     1631460 :   isFunctionRegBankSelected =
     368     1631460 :       !isFunctionFailedISel &&
     369             :       MF.getProperties().hasProperty(
     370             :           MachineFunctionProperties::Property::RegBankSelected);
     371     1631460 :   isFunctionSelected = !isFunctionFailedISel &&
     372             :                        MF.getProperties().hasProperty(
     373             :                            MachineFunctionProperties::Property::Selected);
     374     1631460 :   LiveVars = nullptr;
     375     1631460 :   LiveInts = nullptr;
     376     1631460 :   LiveStks = nullptr;
     377     1631460 :   Indexes = nullptr;
     378     1631460 :   if (PASS) {
     379     1627115 :     LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
     380             :     // We don't want to verify LiveVariables if LiveIntervals is available.
     381     1627115 :     if (!LiveInts)
     382     1431760 :       LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
     383     1627115 :     LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
     384     1627115 :     Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
     385             :   }
     386             : 
     387             :   verifySlotIndexes();
     388             : 
     389     1631460 :   verifyProperties(MF);
     390             : 
     391     1631460 :   visitMachineFunctionBefore();
     392             :   for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
     393     3656172 :        MFI!=MFE; ++MFI) {
     394     2024712 :     visitMachineBasicBlockBefore(&*MFI);
     395             :     // Keep track of the current bundle header.
     396             :     const MachineInstr *CurBundle = nullptr;
     397             :     // Do we expect the next instruction to be part of the same bundle?
     398             :     bool InBundle = false;
     399             : 
     400             :     for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
     401    26401481 :            MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
     402    24376769 :       if (MBBI->getParent() != &*MFI) {
     403           0 :         report("Bad instruction parent pointer", &*MFI);
     404           0 :         errs() << "Instruction: " << *MBBI;
     405           0 :         continue;
     406             :       }
     407             : 
     408             :       // Check for consistent bundle flags.
     409    24376769 :       if (InBundle && !MBBI->isBundledWithPred())
     410           0 :         report("Missing BundledPred flag, "
     411             :                "BundledSucc was set on predecessor",
     412             :                &*MBBI);
     413    24376769 :       if (!InBundle && MBBI->isBundledWithPred())
     414           0 :         report("BundledPred flag is set, "
     415             :                "but BundledSucc not set on predecessor",
     416             :                &*MBBI);
     417             : 
     418             :       // Is this a bundle header?
     419    24376769 :       if (!MBBI->isInsideBundle()) {
     420    24347941 :         if (CurBundle)
     421    22339916 :           visitMachineBundleAfter(CurBundle);
     422             :         CurBundle = &*MBBI;
     423    24347941 :         visitMachineBundleBefore(CurBundle);
     424       28828 :       } else if (!CurBundle)
     425           0 :         report("No bundle header", &*MBBI);
     426    24376769 :       visitMachineInstrBefore(&*MBBI);
     427   121238367 :       for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
     428             :         const MachineInstr &MI = *MBBI;
     429    96861598 :         const MachineOperand &Op = MI.getOperand(I);
     430    96861598 :         if (Op.getParent() != &MI) {
     431             :           // Make sure to use correct addOperand / RemoveOperand / ChangeTo
     432             :           // functions when replacing operands of a MachineInstr.
     433           0 :           report("Instruction has operand with wrong parent set", &MI);
     434             :         }
     435             : 
     436    96861598 :         visitMachineOperand(&Op, I);
     437             :       }
     438             : 
     439             :       visitMachineInstrAfter(&*MBBI);
     440             : 
     441             :       // Was this the last bundled instruction?
     442             :       InBundle = MBBI->isBundledWithSucc();
     443             :     }
     444     2024712 :     if (CurBundle)
     445     2008025 :       visitMachineBundleAfter(CurBundle);
     446     2024712 :     if (InBundle)
     447           0 :       report("BundledSucc flag set on last instruction in block", &MFI->back());
     448     2024712 :     visitMachineBasicBlockAfter(&*MFI);
     449             :   }
     450     1631460 :   visitMachineFunctionAfter();
     451             : 
     452             :   // Clean up.
     453             :   regsLive.clear();
     454             :   regsDefined.clear();
     455             :   regsDead.clear();
     456             :   regsKilled.clear();
     457             :   regMasks.clear();
     458     1631460 :   MBBInfoMap.clear();
     459             : 
     460     1631460 :   return foundErrors;
     461             : }
     462             : 
     463          70 : void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
     464             :   assert(MF);
     465          70 :   errs() << '\n';
     466          70 :   if (!foundErrors++) {
     467          40 :     if (Banner)
     468           3 :       errs() << "# " << Banner << '\n';
     469          40 :     if (LiveInts != nullptr)
     470           2 :       LiveInts->print(errs());
     471             :     else
     472          38 :       MF->print(errs(), Indexes);
     473             :   }
     474          70 :   errs() << "*** Bad machine code: " << msg << " ***\n"
     475          70 :       << "- function:    " << MF->getName() << "\n";
     476          70 : }
     477             : 
     478          70 : void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
     479             :   assert(MBB);
     480          70 :   report(msg, MBB->getParent());
     481          70 :   errs() << "- basic block: " << printMBBReference(*MBB) << ' '
     482          70 :          << MBB->getName() << " (" << (const void *)MBB << ')';
     483          70 :   if (Indexes)
     484           5 :     errs() << " [" << Indexes->getMBBStartIdx(MBB)
     485           5 :         << ';' <<  Indexes->getMBBEndIdx(MBB) << ')';
     486          70 :   errs() << '\n';
     487          70 : }
     488             : 
     489          70 : void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
     490             :   assert(MI);
     491          70 :   report(msg, MI->getParent());
     492          70 :   errs() << "- instruction: ";
     493          70 :   if (Indexes && Indexes->hasIndex(*MI))
     494          10 :     errs() << Indexes->getInstructionIndex(*MI) << '\t';
     495          70 :   MI->print(errs(), /*SkipOpers=*/true);
     496          70 : }
     497             : 
     498          17 : void MachineVerifier::report(const char *msg, const MachineOperand *MO,
     499             :                              unsigned MONum, LLT MOVRegType) {
     500             :   assert(MO);
     501          17 :   report(msg, MO->getParent());
     502          34 :   errs() << "- operand " << MONum << ":   ";
     503          17 :   MO->print(errs(), MOVRegType, TRI);
     504          17 :   errs() << "\n";
     505          17 : }
     506             : 
     507           0 : void MachineVerifier::report_context(SlotIndex Pos) const {
     508           0 :   errs() << "- at:          " << Pos << '\n';
     509           0 : }
     510             : 
     511           0 : void MachineVerifier::report_context(const LiveInterval &LI) const {
     512           0 :   errs() << "- interval:    " << LI << '\n';
     513           0 : }
     514             : 
     515           0 : void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
     516             :                                      LaneBitmask LaneMask) const {
     517           0 :   report_context_liverange(LR);
     518           0 :   report_context_vreg_regunit(VRegUnit);
     519           0 :   if (LaneMask.any())
     520           0 :     report_context_lanemask(LaneMask);
     521           0 : }
     522             : 
     523           0 : void MachineVerifier::report_context(const LiveRange::Segment &S) const {
     524           0 :   errs() << "- segment:     " << S << '\n';
     525           0 : }
     526             : 
     527           0 : void MachineVerifier::report_context(const VNInfo &VNI) const {
     528           0 :   errs() << "- ValNo:       " << VNI.id << " (def " << VNI.def << ")\n";
     529           0 : }
     530             : 
     531           0 : void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
     532           0 :   errs() << "- liverange:   " << LR << '\n';
     533           0 : }
     534             : 
     535           0 : void MachineVerifier::report_context_vreg(unsigned VReg) const {
     536           0 :   errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
     537           0 : }
     538             : 
     539           5 : void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
     540           5 :   if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
     541           5 :     report_context_vreg(VRegOrUnit);
     542             :   } else {
     543           0 :     errs() << "- regunit:     " << printRegUnit(VRegOrUnit, TRI) << '\n';
     544             :   }
     545           5 : }
     546             : 
     547           0 : void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
     548           0 :   errs() << "- lanemask:    " << PrintLaneMask(LaneMask) << '\n';
     549           0 : }
     550             : 
     551     2188188 : void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
     552     2188188 :   BBInfo &MInfo = MBBInfoMap[MBB];
     553     2188188 :   if (!MInfo.reachable) {
     554     2023447 :     MInfo.reachable = true;
     555     2023447 :     for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
     556     2580195 :            SuE = MBB->succ_end(); SuI != SuE; ++SuI)
     557      556748 :       markReachable(*SuI);
     558             :   }
     559     2188188 : }
     560             : 
     561     1631460 : void MachineVerifier::visitMachineFunctionBefore() {
     562     1631460 :   lastIndex = SlotIndex();
     563     3262920 :   regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
     564     1631460 :                                            : TRI->getReservedRegs(*MF);
     565             : 
     566     3262920 :   if (!MF->empty())
     567     1631440 :     markReachable(&MF->front());
     568             : 
     569             :   // Build a set of the basic blocks in the function.
     570     1631460 :   FunctionBlocks.clear();
     571     3656172 :   for (const auto &MBB : *MF) {
     572     2024712 :     FunctionBlocks.insert(&MBB);
     573     2024712 :     BBInfo &MInfo = MBBInfoMap[&MBB];
     574             : 
     575     2024712 :     MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
     576     4049424 :     if (MInfo.Preds.size() != MBB.pred_size())
     577           0 :       report("MBB has duplicate entries in its predecessor list.", &MBB);
     578             : 
     579     2024712 :     MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
     580     4049424 :     if (MInfo.Succs.size() != MBB.succ_size())
     581           0 :       report("MBB has duplicate entries in its successor list.", &MBB);
     582             :   }
     583             : 
     584             :   // Check that the register use lists are sane.
     585     1631460 :   MRI->verifyUseLists();
     586             : 
     587     3262920 :   if (!MF->empty())
     588     1631440 :     verifyStackFrame();
     589     1631460 : }
     590             : 
     591             : // Does iterator point to a and b as the first two elements?
     592             : static bool matchPair(MachineBasicBlock::const_succ_iterator i,
     593             :                       const MachineBasicBlock *a, const MachineBasicBlock *b) {
     594      164452 :   if (*i == a)
     595       83555 :     return *++i == b;
     596       80897 :   if (*i == b)
     597       80897 :     return *++i == a;
     598             :   return false;
     599             : }
     600             : 
     601             : void
     602     2024712 : MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
     603     2024712 :   FirstTerminator = nullptr;
     604             : 
     605     2024712 :   if (!MF->getProperties().hasProperty(
     606     2024712 :       MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) {
     607             :     // If this block has allocatable physical registers live-in, check that
     608             :     // it is an entry block or landing pad.
     609     1853969 :     for (const auto &LI : MBB->liveins()) {
     610     1114323 :       if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
     611     2222570 :           MBB->getIterator() != MBB->getParent()->begin()) {
     612           0 :         report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
     613             :       }
     614             :     }
     615             :   }
     616             : 
     617             :   // Count the number of landing pad successors.
     618             :   SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
     619             :   for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
     620     2581769 :        E = MBB->succ_end(); I != E; ++I) {
     621      557057 :     if ((*I)->isEHPad())
     622        7914 :       LandingPadSuccs.insert(*I);
     623      557057 :     if (!FunctionBlocks.count(*I))
     624           0 :       report("MBB has successor that isn't part of the function.", MBB);
     625      557057 :     if (!MBBInfoMap[*I].Preds.count(MBB)) {
     626           0 :       report("Inconsistent CFG", MBB);
     627           0 :       errs() << "MBB is not in the predecessor list of the successor "
     628           0 :              << printMBBReference(*(*I)) << ".\n";
     629             :     }
     630             :   }
     631             : 
     632             :   // Check the predecessor list.
     633             :   for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
     634     2581769 :        E = MBB->pred_end(); I != E; ++I) {
     635      557057 :     if (!FunctionBlocks.count(*I))
     636           0 :       report("MBB has predecessor that isn't part of the function.", MBB);
     637      557057 :     if (!MBBInfoMap[*I].Succs.count(MBB)) {
     638           0 :       report("Inconsistent CFG", MBB);
     639           0 :       errs() << "MBB is not in the successor list of the predecessor "
     640           0 :              << printMBBReference(*(*I)) << ".\n";
     641             :     }
     642             :   }
     643             : 
     644     2024712 :   const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
     645     2024712 :   const BasicBlock *BB = MBB->getBasicBlock();
     646     2024712 :   const Function &F = MF->getFunction();
     647     2024712 :   if (LandingPadSuccs.size() > 1 &&
     648           0 :       !(AsmInfo &&
     649         273 :         AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
     650     2024712 :         BB && isa<SwitchInst>(BB->getTerminator())) &&
     651         273 :       !isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
     652           0 :     report("MBB has more than one landing pad successor", MBB);
     653             : 
     654             :   // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
     655     2024712 :   MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
     656             :   SmallVector<MachineOperand, 4> Cond;
     657     2024712 :   if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
     658     2024712 :                           Cond)) {
     659             :     // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
     660             :     // check whether its answers match up with reality.
     661      375247 :     if (!TBB && !FBB) {
     662             :       // Block falls through to its successor.
     663      166184 :       MachineFunction::const_iterator MBBI = MBB->getIterator();
     664             :       ++MBBI;
     665      332368 :       if (MBBI == MF->end()) {
     666             :         // It's possible that the block legitimately ends with a noreturn
     667             :         // call or an unreachable, in which case it won't actually fall
     668             :         // out the bottom of the function.
     669      266098 :       } else if (MBB->succ_size() == LandingPadSuccs.size()) {
     670             :         // It's possible that the block legitimately ends with a noreturn
     671             :         // call or an unreachable, in which case it won't actuall fall
     672             :         // out of the block.
     673      123453 :       } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
     674           0 :         report("MBB exits via unconditional fall-through but doesn't have "
     675             :                "exactly one CFG successor!", MBB);
     676      123453 :       } else if (!MBB->isSuccessor(&*MBBI)) {
     677           0 :         report("MBB exits via unconditional fall-through but its successor "
     678             :                "differs from its CFG successor!", MBB);
     679             :       }
     680      315699 :       if (!MBB->empty() && MBB->back().isBarrier() &&
     681          18 :           !TII->isPredicated(MBB->back())) {
     682           0 :         report("MBB exits via unconditional fall-through but ends with a "
     683             :                "barrier instruction!", MBB);
     684             :       }
     685      166184 :       if (!Cond.empty()) {
     686           0 :         report("MBB exits via unconditional fall-through but has a condition!",
     687             :                MBB);
     688             :       }
     689      209063 :     } else if (TBB && !FBB && Cond.empty()) {
     690             :       // Block unconditionally branches somewhere.
     691             :       // If the block has exactly one successor, that happens to be a
     692             :       // landingpad, accept it as valid control flow.
     693       88836 :       if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
     694           0 :           (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
     695           0 :            *MBB->succ_begin() != *LandingPadSuccs.begin())) {
     696           0 :         report("MBB exits via unconditional branch but doesn't have "
     697             :                "exactly one CFG successor!", MBB);
     698       44418 :       } else if (!MBB->isSuccessor(TBB)) {
     699           0 :         report("MBB exits via unconditional branch but the CFG "
     700             :                "successor doesn't match the actual successor!", MBB);
     701             :       }
     702       44418 :       if (MBB->empty()) {
     703           0 :         report("MBB exits via unconditional branch but doesn't contain "
     704             :                "any instructions!", MBB);
     705       44418 :       } else if (!MBB->back().isBarrier()) {
     706           0 :         report("MBB exits via unconditional branch but doesn't end with a "
     707             :                "barrier instruction!", MBB);
     708       44418 :       } else if (!MBB->back().isTerminator()) {
     709           0 :         report("MBB exits via unconditional branch but the branch isn't a "
     710             :                "terminator instruction!", MBB);
     711             :       }
     712      164645 :     } else if (TBB && !FBB && !Cond.empty()) {
     713             :       // Block conditionally branches somewhere, otherwise falls through.
     714       76873 :       MachineFunction::const_iterator MBBI = MBB->getIterator();
     715             :       ++MBBI;
     716      153746 :       if (MBBI == MF->end()) {
     717           0 :         report("MBB conditionally falls through out of function!", MBB);
     718       76873 :       } else if (MBB->succ_size() == 1) {
     719             :         // A conditional branch with only one successor is weird, but allowed.
     720          49 :         if (&*MBBI != TBB)
     721           0 :           report("MBB exits via conditional branch/fall-through but only has "
     722             :                  "one CFG successor!", MBB);
     723          49 :         else if (TBB != *MBB->succ_begin())
     724           0 :           report("MBB exits via conditional branch/fall-through but the CFG "
     725             :                  "successor don't match the actual successor!", MBB);
     726       76824 :       } else if (MBB->succ_size() != 2) {
     727           0 :         report("MBB exits via conditional branch/fall-through but doesn't have "
     728             :                "exactly two CFG successors!", MBB);
     729       76824 :       } else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
     730           0 :         report("MBB exits via conditional branch/fall-through but the CFG "
     731             :                "successors don't match the actual successors!", MBB);
     732             :       }
     733       76873 :       if (MBB->empty()) {
     734           0 :         report("MBB exits via conditional branch/fall-through but doesn't "
     735             :                "contain any instructions!", MBB);
     736       76873 :       } else if (MBB->back().isBarrier()) {
     737           0 :         report("MBB exits via conditional branch/fall-through but ends with a "
     738             :                "barrier instruction!", MBB);
     739       76873 :       } else if (!MBB->back().isTerminator()) {
     740           0 :         report("MBB exits via conditional branch/fall-through but the branch "
     741             :                "isn't a terminator instruction!", MBB);
     742             :       }
     743       87772 :     } else if (TBB && FBB) {
     744             :       // Block conditionally branches somewhere, otherwise branches
     745             :       // somewhere else.
     746       87772 :       if (MBB->succ_size() == 1) {
     747             :         // A conditional branch with only one successor is weird, but allowed.
     748         144 :         if (FBB != TBB)
     749           0 :           report("MBB exits via conditional branch/branch through but only has "
     750             :                  "one CFG successor!", MBB);
     751         144 :         else if (TBB != *MBB->succ_begin())
     752           0 :           report("MBB exits via conditional branch/branch through but the CFG "
     753             :                  "successor don't match the actual successor!", MBB);
     754       87628 :       } else if (MBB->succ_size() != 2) {
     755           0 :         report("MBB exits via conditional branch/branch but doesn't have "
     756             :                "exactly two CFG successors!", MBB);
     757       87628 :       } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
     758           0 :         report("MBB exits via conditional branch/branch but the CFG "
     759             :                "successors don't match the actual successors!", MBB);
     760             :       }
     761       87772 :       if (MBB->empty()) {
     762           0 :         report("MBB exits via conditional branch/branch but doesn't "
     763             :                "contain any instructions!", MBB);
     764       87772 :       } else if (!MBB->back().isBarrier()) {
     765           0 :         report("MBB exits via conditional branch/branch but doesn't end with a "
     766             :                "barrier instruction!", MBB);
     767       87772 :       } else if (!MBB->back().isTerminator()) {
     768           0 :         report("MBB exits via conditional branch/branch but the branch "
     769             :                "isn't a terminator instruction!", MBB);
     770             :       }
     771       87772 :       if (Cond.empty()) {
     772           0 :         report("MBB exits via conditinal branch/branch but there's no "
     773             :                "condition!", MBB);
     774             :       }
     775             :     } else {
     776           0 :       report("AnalyzeBranch returned invalid data!", MBB);
     777             :     }
     778             :   }
     779             : 
     780             :   regsLive.clear();
     781     4049424 :   if (MRI->tracksLiveness()) {
     782     5682077 :     for (const auto &LI : MBB->liveins()) {
     783     3688747 :       if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
     784           0 :         report("MBB live-in list contains non-physical register", MBB);
     785           0 :         continue;
     786             :       }
     787     3688747 :       for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
     788    11551948 :            SubRegs.isValid(); ++SubRegs)
     789     7863201 :         regsLive.insert(*SubRegs);
     790             :     }
     791             :   }
     792             : 
     793     2024712 :   const MachineFrameInfo &MFI = MF->getFrameInfo();
     794     2024712 :   BitVector PR = MFI.getPristineRegs(*MF);
     795    18328294 :   for (unsigned I : PR.set_bits()) {
     796    16303582 :     for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
     797    43369139 :          SubRegs.isValid(); ++SubRegs)
     798    27065557 :       regsLive.insert(*SubRegs);
     799             :   }
     800             : 
     801             :   regsKilled.clear();
     802             :   regsDefined.clear();
     803             : 
     804     2024712 :   if (Indexes)
     805      289032 :     lastIndex = Indexes->getMBBStartIdx(MBB);
     806     2024712 : }
     807             : 
     808             : // This function gets called for all bundle headers, including normal
     809             : // stand-alone unbundled instructions.
     810    24347941 : void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
     811    24347941 :   if (Indexes && Indexes->hasIndex(*MI)) {
     812     3223052 :     SlotIndex idx = Indexes->getInstructionIndex(*MI);
     813     3223052 :     if (!(idx > lastIndex)) {
     814           0 :       report("Instruction index out of order", MI);
     815           0 :       errs() << "Last instruction was at " << lastIndex << '\n';
     816             :     }
     817     3223052 :     lastIndex = idx;
     818             :   }
     819             : 
     820             :   // Ensure non-terminators don't follow terminators.
     821             :   // Ignore predicated terminators formed by if conversion.
     822             :   // FIXME: If conversion shouldn't need to violate this rule.
     823    24347941 :   if (MI->isTerminator() && !TII->isPredicated(*MI)) {
     824     1967877 :     if (!FirstTerminator)
     825     1869193 :       FirstTerminator = MI;
     826    22380064 :   } else if (FirstTerminator) {
     827           0 :     report("Non-terminator instruction after the first terminator", MI);
     828           0 :     errs() << "First terminator was:\t" << *FirstTerminator;
     829             :   }
     830    24347941 : }
     831             : 
     832             : // The operands on an INLINEASM instruction must follow a template.
     833             : // Verify that the flag operands make sense.
     834      121954 : void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
     835             :   // The first two operands on INLINEASM are the asm string and global flags.
     836      121954 :   if (MI->getNumOperands() < 2) {
     837           0 :     report("Too few operands on inline asm", MI);
     838           0 :     return;
     839             :   }
     840      243908 :   if (!MI->getOperand(0).isSymbol())
     841           0 :     report("Asm string must be an external symbol", MI);
     842      243908 :   if (!MI->getOperand(1).isImm())
     843           0 :     report("Asm flags must be an immediate", MI);
     844             :   // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
     845             :   // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
     846             :   // and Extra_IsConvergent = 32.
     847      121954 :   if (!isUInt<6>(MI->getOperand(1).getImm()))
     848           0 :     report("Unknown asm flags", &MI->getOperand(1), 1);
     849             : 
     850             :   static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
     851             : 
     852             :   unsigned OpNo = InlineAsm::MIOp_FirstOperand;
     853             :   unsigned NumOps;
     854      578508 :   for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
     855      457345 :     const MachineOperand &MO = MI->getOperand(OpNo);
     856             :     // There may be implicit ops after the fixed operands.
     857      457345 :     if (!MO.isImm())
     858             :       break;
     859      913108 :     NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
     860             :   }
     861             : 
     862      121954 :   if (OpNo > MI->getNumOperands())
     863           0 :     report("Missing operands in last group", MI);
     864             : 
     865             :   // An optional MDNode follows the groups.
     866      121954 :   if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
     867         434 :     ++OpNo;
     868             : 
     869             :   // All trailing operands must be implicit registers.
     870      122447 :   for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
     871         493 :     const MachineOperand &MO = MI->getOperand(OpNo);
     872         493 :     if (!MO.isReg() || !MO.isImplicit())
     873           0 :       report("Expected implicit register after groups", &MO, OpNo);
     874             :   }
     875             : }
     876             : 
     877    24376769 : void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     878    24376769 :   const MCInstrDesc &MCID = MI->getDesc();
     879    48753538 :   if (MI->getNumOperands() < MCID.getNumOperands()) {
     880          10 :     report("Too few operands", MI);
     881          10 :     errs() << MCID.getNumOperands() << " operands expected, but "
     882          10 :            << MI->getNumOperands() << " given.\n";
     883             :   }
     884             : 
     885      165704 :   if (MI->isPHI() && MF->getProperties().hasProperty(
     886             :                          MachineFunctionProperties::Property::NoPHIs))
     887           0 :     report("Found PHI instruction with NoPHIs property set", MI);
     888             : 
     889             :   // Check the tied operands.
     890    24376769 :   if (MI->isInlineAsm())
     891      121954 :     verifyInlineAsm(MI);
     892             : 
     893             :   // Check the MachineMemOperands for basic consistency.
     894     4822565 :   for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
     895             :                                   E = MI->memoperands_end();
     896    29199334 :        I != E; ++I) {
     897     9645130 :     if ((*I)->isLoad() && !MI->mayLoad())
     898           0 :       report("Missing mayLoad flag", MI);
     899     9645130 :     if ((*I)->isStore() && !MI->mayStore())
     900           0 :       report("Missing mayStore flag", MI);
     901             :   }
     902             : 
     903             :   // Debug values must not have a slot index.
     904             :   // Other instructions must have one, unless they are inside a bundle.
     905    24376769 :   if (LiveInts) {
     906     2793490 :     bool mapped = !LiveInts->isNotInMIMap(*MI);
     907             :     if (MI->isDebugInstr()) {
     908         129 :       if (mapped)
     909           0 :         report("Debug instruction has a slot index", MI);
     910     2793361 :     } else if (MI->isInsideBundle()) {
     911         223 :       if (mapped)
     912           0 :         report("Instruction inside bundle has a slot index", MI);
     913             :     } else {
     914     2793138 :       if (!mapped)
     915           0 :         report("Missing slot index", MI);
     916             :     }
     917             :   }
     918             : 
     919    48753538 :   if (isPreISelGenericOpcode(MCID.getOpcode())) {
     920       11693 :     if (isFunctionSelected)
     921           1 :       report("Unexpected generic instruction in a Selected function", MI);
     922             : 
     923             :     // Check types.
     924             :     SmallVector<LLT, 4> Types;
     925       51561 :     for (unsigned I = 0; I < MCID.getNumOperands(); ++I) {
     926       56350 :       if (!MCID.OpInfo[I].isGenericType())
     927             :         continue;
     928             :       // Generic instructions specify type equality constraints between some of
     929             :       // their operands. Make sure these are consistent.
     930       24618 :       size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
     931       49527 :       Types.resize(std::max(TypeIdx + 1, Types.size()));
     932             : 
     933       24618 :       const MachineOperand *MO = &MI->getOperand(I);
     934       24618 :       LLT OpTy = MRI->getType(MO->getReg());
     935             :       // Don't report a type mismatch if there is no actual mismatch, only a
     936             :       // type missing, to reduce noise:
     937       24618 :       if (OpTy.isValid()) {
     938             :         // Only the first valid type for a type index will be printed: don't
     939             :         // overwrite it later so it's always clear which type was expected:
     940       24613 :         if (!Types[TypeIdx].isValid())
     941       18472 :           Types[TypeIdx] = OpTy;
     942        6140 :         else if (Types[TypeIdx] != OpTy)
     943           1 :           report("Type mismatch in generic instruction", MO, I, OpTy);
     944             :       } else {
     945             :         // Generic instructions must have types attached to their operands.
     946           5 :         report("Generic instruction is missing a virtual register type", MO, I);
     947             :       }
     948             :     }
     949             : 
     950             :     // Generic opcodes must not have physical register operands.
     951       41512 :     for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
     952       29819 :       const MachineOperand *MO = &MI->getOperand(I);
     953       29819 :       if (MO->isReg() && TargetRegisterInfo::isPhysicalRegister(MO->getReg()))
     954           0 :         report("Generic instruction cannot have physical register", MO, I);
     955             :     }
     956             :   }
     957             : 
     958    24376769 :   StringRef ErrorInfo;
     959    24376769 :   if (!TII->verifyInstruction(*MI, ErrorInfo))
     960          25 :     report(ErrorInfo.data(), MI);
     961             : 
     962             :   // Verify properties of various specific instruction types
     963    48753538 :   switch(MI->getOpcode()) {
     964             :   default:
     965             :     break;
     966        1426 :   case TargetOpcode::G_LOAD:
     967             :   case TargetOpcode::G_STORE:
     968             :     // Generic loads and stores must have a single MachineMemOperand
     969             :     // describing that access.
     970        1426 :     if (!MI->hasOneMemOperand())
     971           0 :       report("Generic instruction accessing memory must have one mem operand",
     972             :              MI);
     973             :     break;
     974          77 :   case TargetOpcode::G_PHI: {
     975         154 :     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     976         154 :     if (!DstTy.isValid() ||
     977         154 :         !std::all_of(MI->operands_begin() + 1, MI->operands_end(),
     978             :                      [this, &DstTy](const MachineOperand &MO) {
     979             :                        if (!MO.isReg())
     980             :                          return true;
     981             :                        LLT Ty = MRI->getType(MO.getReg());
     982             :                        if (!Ty.isValid() || (Ty != DstTy))
     983             :                          return false;
     984             :                        return true;
     985             :                      }))
     986           1 :       report("Generic Instruction G_PHI has operands with incompatible/missing "
     987             :              "types",
     988             :              MI);
     989             :     break;
     990             :   }
     991        2734 :   case TargetOpcode::G_SEXT:
     992             :   case TargetOpcode::G_ZEXT:
     993             :   case TargetOpcode::G_ANYEXT:
     994             :   case TargetOpcode::G_TRUNC:
     995             :   case TargetOpcode::G_FPEXT:
     996             :   case TargetOpcode::G_FPTRUNC: {
     997             :     // Number of operands and presense of types is already checked (and
     998             :     // reported in case of any issues), so no need to report them again. As
     999             :     // we're trying to report as many issues as possible at once, however, the
    1000             :     // instructions aren't guaranteed to have the right number of operands or
    1001             :     // types attached to them at this point
    1002             :     assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
    1003        5468 :     if (MI->getNumOperands() < MCID.getNumOperands())
    1004             :       break;
    1005        2734 :     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
    1006        5468 :     LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
    1007        2734 :     if (!DstTy.isValid() || !SrcTy.isValid())
    1008             :       break;
    1009             : 
    1010        2734 :     LLT DstElTy = DstTy.isVector() ? DstTy.getElementType() : DstTy;
    1011        2734 :     LLT SrcElTy = SrcTy.isVector() ? SrcTy.getElementType() : SrcTy;
    1012        5466 :     if (DstElTy.isPointer() || SrcElTy.isPointer())
    1013           3 :       report("Generic extend/truncate can not operate on pointers", MI);
    1014             : 
    1015        5468 :     if (DstTy.isVector() != SrcTy.isVector()) {
    1016           2 :       report("Generic extend/truncate must be all-vector or all-scalar", MI);
    1017             :       // Generally we try to report as many issues as possible at once, but in
    1018             :       // this case it's not clear what should we be comparing the size of the
    1019             :       // scalar with: the size of the whole vector or its lane. Instead of
    1020             :       // making an arbitrary choice and emitting not so helpful message, let's
    1021             :       // avoid the extra noise and stop here.
    1022           2 :       break;
    1023             :     }
    1024        2852 :     if (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements())
    1025           2 :       report("Generic vector extend/truncate must preserve number of lanes",
    1026             :              MI);
    1027        2732 :     unsigned DstSize = DstElTy.getSizeInBits();
    1028        2732 :     unsigned SrcSize = SrcElTy.getSizeInBits();
    1029        2732 :     switch (MI->getOpcode()) {
    1030        1239 :     default:
    1031        1239 :       if (DstSize <= SrcSize)
    1032           2 :         report("Generic extend has destination type no larger than source", MI);
    1033             :       break;
    1034        1493 :     case TargetOpcode::G_TRUNC:
    1035             :     case TargetOpcode::G_FPTRUNC:
    1036        1493 :       if (DstSize >= SrcSize)
    1037           1 :         report("Generic truncate has destination type no smaller than source",
    1038             :                MI);
    1039             :       break;
    1040             :     }
    1041             :     break;
    1042             :   }
    1043     5722948 :   case TargetOpcode::COPY: {
    1044     5722948 :     if (foundErrors)
    1045             :       break;
    1046     5722912 :     const MachineOperand &DstOp = MI->getOperand(0);
    1047             :     const MachineOperand &SrcOp = MI->getOperand(1);
    1048     5722912 :     LLT DstTy = MRI->getType(DstOp.getReg());
    1049     9133615 :     LLT SrcTy = MRI->getType(SrcOp.getReg());
    1050     5722912 :     if (SrcTy.isValid() && DstTy.isValid()) {
    1051             :       // If both types are valid, check that the types are the same.
    1052         465 :       if (SrcTy != DstTy) {
    1053           1 :         report("Copy Instruction is illegal with mismatching types", MI);
    1054           3 :         errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
    1055             :       }
    1056             :     }
    1057     5722912 :     if (SrcTy.isValid() || DstTy.isValid()) {
    1058             :       // If one of them have valid types, let's just check they have the same
    1059             :       // size.
    1060       12197 :       unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
    1061       12197 :       unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);
    1062             :       assert(SrcSize && "Expecting size here");
    1063             :       assert(DstSize && "Expecting size here");
    1064       12197 :       if (SrcSize != DstSize)
    1065           2 :         if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
    1066           2 :           report("Copy Instruction is illegal with mismatching sizes", MI);
    1067           4 :           errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
    1068           2 :                  << "\n";
    1069             :         }
    1070             :     }
    1071             :     break;
    1072             :   }
    1073        2984 :   case TargetOpcode::STATEPOINT:
    1074        2984 :     if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
    1075        5968 :         !MI->getOperand(StatepointOpers::NBytesPos).isImm() ||
    1076             :         !MI->getOperand(StatepointOpers::NCallArgsPos).isImm())
    1077           0 :       report("meta operands to STATEPOINT not constant!", MI);
    1078             :     break;
    1079             : 
    1080             :     auto VerifyStackMapConstant = [&](unsigned Offset) {
    1081             :       if (!MI->getOperand(Offset).isImm() ||
    1082             :           MI->getOperand(Offset).getImm() != StackMaps::ConstantOp ||
    1083             :           !MI->getOperand(Offset + 1).isImm())
    1084             :         report("stack map constant to STATEPOINT not well formed!", MI);
    1085             :     };
    1086             :     const unsigned VarStart = StatepointOpers(MI).getVarIdx();
    1087             :     VerifyStackMapConstant(VarStart + StatepointOpers::CCOffset);
    1088             :     VerifyStackMapConstant(VarStart + StatepointOpers::FlagsOffset);
    1089             :     VerifyStackMapConstant(VarStart + StatepointOpers::NumDeoptOperandsOffset);
    1090             : 
    1091             :     // TODO: verify we have properly encoded deopt arguments
    1092             :   };
    1093    24376769 : }
    1094             : 
    1095             : void
    1096    96861598 : MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
    1097    96861598 :   const MachineInstr *MI = MO->getParent();
    1098    96861598 :   const MCInstrDesc &MCID = MI->getDesc();
    1099    96861598 :   unsigned NumDefs = MCID.getNumDefs();
    1100    96861598 :   if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
    1101          35 :     NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
    1102             : 
    1103             :   // The first MCID.NumDefs operands must be explicit register defines
    1104    96861598 :   if (MONum < NumDefs) {
    1105    19644265 :     const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
    1106    19644265 :     if (!MO->isReg())
    1107           0 :       report("Explicit definition must be a register", MO, MONum);
    1108    19644265 :     else if (!MO->isDef() && !MCOI.isOptionalDef())
    1109           0 :       report("Explicit definition marked as use", MO, MONum);
    1110    19644265 :     else if (MO->isImplicit())
    1111           0 :       report("Explicit definition marked as implicit", MO, MONum);
    1112   154434666 :   } else if (MONum < MCID.getNumOperands()) {
    1113    57722318 :     const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
    1114             :     // Don't check if it's the last operand in a variadic instruction. See,
    1115             :     // e.g., LDM_RET in the arm back end.
    1116    85642758 :     if (MO->isReg() &&
    1117     2016944 :         !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
    1118    26978365 :       if (MO->isDef() && !MCOI.isOptionalDef())
    1119           0 :         report("Explicit operand marked as def", MO, MONum);
    1120    26978365 :       if (MO->isImplicit())
    1121           0 :         report("Explicit operand marked as implicit", MO, MONum);
    1122             :     }
    1123             : 
    1124    57722318 :     int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
    1125             :     if (TiedTo != -1) {
    1126      666027 :       if (!MO->isReg())
    1127           0 :         report("Tied use must be a register", MO, MONum);
    1128      666027 :       else if (!MO->isTied())
    1129           0 :         report("Operand should be tied", MO, MONum);
    1130      666027 :       else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
    1131           0 :         report("Tied def doesn't match MCInstrDesc", MO, MONum);
    1132     1332054 :       else if (TargetRegisterInfo::isPhysicalRegister(MO->getReg())) {
    1133      385815 :         const MachineOperand &MOTied = MI->getOperand(TiedTo);
    1134      385815 :         if (!MOTied.isReg())
    1135           0 :           report("Tied counterpart must be a register", &MOTied, TiedTo);
    1136      771630 :         else if (TargetRegisterInfo::isPhysicalRegister(MOTied.getReg()) &&
    1137             :                  MO->getReg() != MOTied.getReg())
    1138           1 :           report("Tied physical registers must match.", &MOTied, TiedTo);
    1139             :       }
    1140    57056291 :     } else if (MO->isReg() && MO->isTied())
    1141           0 :       report("Explicit operand should not be tied", MO, MONum);
    1142             :   } else {
    1143             :     // ARM adds %reg0 operands to indicate predicates. We'll allow that.
    1144    21765644 :     if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
    1145           0 :       report("Extra explicit operand on non-variadic instruction", MO, MONum);
    1146             :   }
    1147             : 
    1148    96861598 :   switch (MO->getType()) {
    1149    63376057 :   case MachineOperand::MO_Register: {
    1150    63376057 :     const unsigned Reg = MO->getReg();
    1151    63376057 :     if (!Reg)
    1152     1745794 :       return;
    1153   123260530 :     if (MRI->tracksLiveness() && !MI->isDebugValue())
    1154    60803405 :       checkLiveness(MO, MONum);
    1155             : 
    1156             :     // Verify the consistency of tied operands.
    1157    61630265 :     if (MO->isTied()) {
    1158     1345448 :       unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
    1159     1345448 :       const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
    1160     1345448 :       if (!OtherMO.isReg())
    1161           0 :         report("Must be tied to a register", MO, MONum);
    1162     1345448 :       if (!OtherMO.isTied())
    1163           0 :         report("Missing tie flags on tied operand", MO, MONum);
    1164     1345448 :       if (MI->findTiedOperandIdx(OtherIdx) != MONum)
    1165           0 :         report("Inconsistent tie links", MO, MONum);
    1166     2690896 :       if (MONum < MCID.getNumDefs()) {
    1167     1334026 :         if (OtherIdx < MCID.getNumOperands()) {
    1168             :           if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
    1169           0 :             report("Explicit def tied to explicit use without tie constraint",
    1170             :                    MO, MONum);
    1171             :         } else {
    1172         986 :           if (!OtherMO.isImplicit())
    1173           0 :             report("Explicit def should be tied to implicit use", MO, MONum);
    1174             :         }
    1175             :       }
    1176             :     }
    1177             : 
    1178             :     // Verify two-address constraints after leaving SSA form.
    1179             :     unsigned DefIdx;
    1180    83107433 :     if (!MRI->isSSA() && MO->isUse() &&
    1181    83107433 :         MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
    1182      892890 :         Reg != MI->getOperand(DefIdx).getReg())
    1183           0 :       report("Two-address instruction operands must be identical", MO, MONum);
    1184             : 
    1185             :     // Check register classes.
    1186             :     unsigned SubIdx = MO->getSubReg();
    1187             : 
    1188    61630265 :     if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
    1189    35992364 :       if (SubIdx) {
    1190           0 :         report("Illegal subregister index for physical register", MO, MONum);
    1191           0 :         return;
    1192             :       }
    1193    71984728 :       if (MONum < MCID.getNumOperands()) {
    1194    22024533 :         if (const TargetRegisterClass *DRC =
    1195    22024533 :               TII->getRegClass(MCID, MONum, TRI, *MF)) {
    1196    18177771 :           if (!DRC->contains(Reg)) {
    1197           0 :             report("Illegal physical register for instruction", MO, MONum);
    1198           0 :             errs() << printReg(Reg, TRI) << " is not a "
    1199           0 :                    << TRI->getRegClassName(DRC) << " register.\n";
    1200             :           }
    1201             :         }
    1202             :       }
    1203    35992364 :       if (MO->isRenamable()) {
    1204    24342406 :         if (MRI->isReserved(Reg)) {
    1205           0 :           report("isRenamable set on reserved register", MO, MONum);
    1206           0 :           return;
    1207             :         }
    1208             :       }
    1209    35992364 :       if (MI->isDebugValue() && MO->isUse() && !MO->isDebug()) {
    1210           0 :         report("Use-reg is not IsDebug in a DBG_VALUE", MO, MONum);
    1211           0 :         return;
    1212             :       }
    1213             :     } else {
    1214             :       // Virtual register.
    1215    25637901 :       const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
    1216    25613227 :       if (!RC) {
    1217             :         // This is a generic virtual register.
    1218             : 
    1219             :         // If we're post-Select, we can't have gvregs anymore.
    1220       39343 :         if (isFunctionSelected) {
    1221           1 :           report("Generic virtual register invalid in a Selected function",
    1222             :                  MO, MONum);
    1223           2 :           return;
    1224             :         }
    1225             : 
    1226             :         // The gvreg must have a type and it must not have a SubIdx.
    1227       39342 :         LLT Ty = MRI->getType(Reg);
    1228       39342 :         if (!Ty.isValid()) {
    1229           0 :           report("Generic virtual register must have a valid type", MO,
    1230             :                  MONum);
    1231           0 :           return;
    1232             :         }
    1233             : 
    1234             :         const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
    1235             : 
    1236             :         // If we're post-RegBankSelect, the gvreg must have a bank.
    1237       39342 :         if (!RegBank && isFunctionRegBankSelected) {
    1238           1 :           report("Generic virtual register must have a bank in a "
    1239             :                  "RegBankSelected function",
    1240             :                  MO, MONum);
    1241           1 :           return;
    1242             :         }
    1243             : 
    1244             :         // Make sure the register fits into its register bank if any.
    1245       39341 :         if (RegBank && Ty.isValid() &&
    1246       18256 :             RegBank->getSize() < Ty.getSizeInBits()) {
    1247           0 :           report("Register bank is too small for virtual register", MO,
    1248             :                  MONum);
    1249           0 :           errs() << "Register bank " << RegBank->getName() << " too small("
    1250           0 :                  << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
    1251           0 :                  << "-bits\n";
    1252           0 :           return;
    1253             :         }
    1254       39341 :         if (SubIdx)  {
    1255           0 :           report("Generic virtual register does not subregister index", MO,
    1256             :                  MONum);
    1257           0 :           return;
    1258             :         }
    1259             : 
    1260             :         // If this is a target specific instruction and this operand
    1261             :         // has register class constraint, the virtual register must
    1262             :         // comply to it.
    1263       39341 :         if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
    1264       52233 :             MONum < MCID.getNumOperands() &&
    1265       12892 :             TII->getRegClass(MCID, MONum, TRI, *MF)) {
    1266           0 :           report("Virtual register does not match instruction constraint", MO,
    1267             :                  MONum);
    1268           0 :           errs() << "Expect register class "
    1269           0 :                  << TRI->getRegClassName(
    1270           0 :                         TII->getRegClass(MCID, MONum, TRI, *MF))
    1271           0 :                  << " but got nothing\n";
    1272           0 :           return;
    1273             :         }
    1274             : 
    1275       39341 :         break;
    1276             :       }
    1277    25598558 :       if (SubIdx) {
    1278             :         const TargetRegisterClass *SRC =
    1279     2995773 :           TRI->getSubClassWithSubReg(RC, SubIdx);
    1280     2995773 :         if (!SRC) {
    1281           0 :           report("Invalid subregister index for virtual register", MO, MONum);
    1282           0 :           errs() << "Register class " << TRI->getRegClassName(RC)
    1283           0 :               << " does not support subreg index " << SubIdx << "\n";
    1284           0 :           return;
    1285             :         }
    1286     2995773 :         if (RC != SRC) {
    1287           0 :           report("Invalid register class for subregister index", MO, MONum);
    1288           0 :           errs() << "Register class " << TRI->getRegClassName(RC)
    1289           0 :               << " does not fully support subreg index " << SubIdx << "\n";
    1290           0 :           return;
    1291             :         }
    1292             :       }
    1293    51197116 :       if (MONum < MCID.getNumOperands()) {
    1294    23759517 :         if (const TargetRegisterClass *DRC =
    1295    23759517 :               TII->getRegClass(MCID, MONum, TRI, *MF)) {
    1296    13780291 :           if (SubIdx) {
    1297             :             const TargetRegisterClass *SuperRC =
    1298      974367 :                 TRI->getLargestLegalSuperClass(RC, *MF);
    1299      974367 :             if (!SuperRC) {
    1300           0 :               report("No largest legal super class exists.", MO, MONum);
    1301           0 :               return;
    1302             :             }
    1303      974367 :             DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
    1304      974367 :             if (!DRC) {
    1305           0 :               report("No matching super-reg register class.", MO, MONum);
    1306           0 :               return;
    1307             :             }
    1308             :           }
    1309    13780291 :           if (!RC->hasSuperClassEq(DRC)) {
    1310           0 :             report("Illegal virtual register for instruction", MO, MONum);
    1311           0 :             errs() << "Expected a " << TRI->getRegClassName(DRC)
    1312           0 :                 << " register, but got a " << TRI->getRegClassName(RC)
    1313           0 :                 << " register\n";
    1314             :           }
    1315             :         }
    1316             :       }
    1317             :     }
    1318             :     break;
    1319             :   }
    1320             : 
    1321      215031 :   case MachineOperand::MO_RegisterMask:
    1322      215031 :     regMasks.push_back(MO->getRegMask());
    1323      215031 :     break;
    1324             : 
    1325             :   case MachineOperand::MO_MachineBasicBlock:
    1326      167487 :     if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
    1327           0 :       report("PHI operand is not in the CFG", MO, MONum);
    1328             :     break;
    1329             : 
    1330      417548 :   case MachineOperand::MO_FrameIndex:
    1331       36658 :     if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
    1332      425109 :         LiveInts && !LiveInts->isNotInMIMap(*MI)) {
    1333        4871 :       int FI = MO->getIndex();
    1334        4871 :       LiveInterval &LI = LiveStks->getInterval(FI);
    1335        4871 :       SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
    1336             : 
    1337        4871 :       bool stores = MI->mayStore();
    1338        4871 :       bool loads = MI->mayLoad();
    1339             :       // For a memory-to-memory move, we need to check if the frame
    1340             :       // index is used for storing or loading, by inspecting the
    1341             :       // memory operands.
    1342        4871 :       if (stores && loads) {
    1343          44 :         for (auto *MMO : MI->memoperands()) {
    1344             :           const PseudoSourceValue *PSV = MMO->getPseudoValue();
    1345          26 :           if (PSV == nullptr) continue;
    1346             :           const FixedStackPseudoSourceValue *Value =
    1347             :             dyn_cast<FixedStackPseudoSourceValue>(PSV);
    1348             :           if (Value == nullptr) continue;
    1349          26 :           if (Value->getFrameIndex() != FI) continue;
    1350             : 
    1351          46 :           if (MMO->isStore())
    1352             :             loads = false;
    1353             :           else
    1354             :             stores = false;
    1355             :           break;
    1356             :         }
    1357          23 :         if (loads == stores)
    1358           0 :           report("Missing fixed stack memoperand.", MI);
    1359             :       }
    1360        4871 :       if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
    1361           0 :         report("Instruction loads from dead spill slot", MO, MONum);
    1362           0 :         errs() << "Live stack: " << LI << '\n';
    1363             :       }
    1364        4871 :       if (stores && !LI.liveAt(Idx.getRegSlot())) {
    1365           0 :         report("Instruction stores to dead spill slot", MO, MONum);
    1366           0 :         errs() << "Live stack: " << LI << '\n';
    1367             :       }
    1368             :     }
    1369             :     break;
    1370             : 
    1371             :   default:
    1372             :     break;
    1373             :   }
    1374             : }
    1375             : 
    1376     4888353 : void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
    1377             :     unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
    1378             :     LaneBitmask LaneMask) {
    1379     4888353 :   LiveQueryResult LRQ = LR.Query(UseIdx);
    1380             :   // Check if we have a segment at the use, note however that we only need one
    1381             :   // live subregister range, the others may be dead.
    1382     4888353 :   if (!LRQ.valueIn() && LaneMask.none()) {
    1383           0 :     report("No live segment at use", MO, MONum);
    1384           0 :     report_context_liverange(LR);
    1385           0 :     report_context_vreg_regunit(VRegOrUnit);
    1386           0 :     report_context(UseIdx);
    1387             :   }
    1388     4888353 :   if (MO->isKill() && !LRQ.isKill()) {
    1389           0 :     report("Live range continues after kill flag", MO, MONum);
    1390           0 :     report_context_liverange(LR);
    1391           0 :     report_context_vreg_regunit(VRegOrUnit);
    1392           0 :     if (LaneMask.any())
    1393           0 :       report_context_lanemask(LaneMask);
    1394           0 :     report_context(UseIdx);
    1395             :   }
    1396     4888353 : }
    1397             : 
    1398     3134674 : void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
    1399             :     unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
    1400             :     bool SubRangeCheck, LaneBitmask LaneMask) {
    1401     3134674 :   if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
    1402             :     assert(VNI && "NULL valno is not allowed");
    1403     3134674 :     if (VNI->def != DefIdx) {
    1404           0 :       report("Inconsistent valno->def", MO, MONum);
    1405           0 :       report_context_liverange(LR);
    1406           0 :       report_context_vreg_regunit(VRegOrUnit);
    1407           0 :       if (LaneMask.any())
    1408           0 :         report_context_lanemask(LaneMask);
    1409           0 :       report_context(*VNI);
    1410           0 :       report_context(DefIdx);
    1411             :     }
    1412             :   } else {
    1413           0 :     report("No live segment at def", MO, MONum);
    1414           0 :     report_context_liverange(LR);
    1415           0 :     report_context_vreg_regunit(VRegOrUnit);
    1416           0 :     if (LaneMask.any())
    1417           0 :       report_context_lanemask(LaneMask);
    1418           0 :     report_context(DefIdx);
    1419             :   }
    1420             :   // Check that, if the dead def flag is present, LiveInts agree.
    1421     3134674 :   if (MO->isDead()) {
    1422       40595 :     LiveQueryResult LRQ = LR.Query(DefIdx);
    1423       40595 :     if (!LRQ.isDeadDef()) {
    1424             :       assert(TargetRegisterInfo::isVirtualRegister(VRegOrUnit) &&
    1425             :              "Expecting a virtual register.");
    1426             :       // A dead subreg def only tells us that the specific subreg is dead. There
    1427             :       // could be other non-dead defs of other subregs, or we could have other
    1428             :       // parts of the register being live through the instruction. So unless we
    1429             :       // are checking liveness for a subrange it is ok for the live range to
    1430             :       // continue, given that we have a dead def of a subregister.
    1431          13 :       if (SubRangeCheck || MO->getSubReg() == 0) {
    1432           5 :         report("Live range continues after dead def flag", MO, MONum);
    1433           5 :         report_context_liverange(LR);
    1434           5 :         report_context_vreg_regunit(VRegOrUnit);
    1435           5 :         if (LaneMask.any())
    1436           3 :           report_context_lanemask(LaneMask);
    1437             :       }
    1438             :     }
    1439             :   }
    1440     3134674 : }
    1441             : 
    1442    60803405 : void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
    1443    60803405 :   const MachineInstr *MI = MO->getParent();
    1444    60803405 :   const unsigned Reg = MO->getReg();
    1445             : 
    1446             :   // Both use and def operands can read a register.
    1447             :   if (MO->readsReg()) {
    1448    38495721 :     if (MO->isKill())
    1449     9639109 :       addRegWithSubRegs(regsKilled, Reg);
    1450             : 
    1451             :     // Check that LiveVars knows this kill.
    1452    38495721 :     if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
    1453             :         MO->isKill()) {
    1454         507 :       LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
    1455         507 :       if (!is_contained(VI.Kills, MI))
    1456           0 :         report("Kill missing from LiveVariables", MO, MONum);
    1457             :     }
    1458             : 
    1459             :     // Check LiveInts liveness and kill.
    1460    38495721 :     if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
    1461     4686233 :       SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
    1462             :       // Check the cached regunit intervals.
    1463     9372466 :       if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
    1464     1890270 :         for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
    1465     1462476 :           if (MRI->isReservedRegUnit(*Units))
    1466             :             continue;
    1467     1462408 :           if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
    1468      626710 :             checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
    1469             :         }
    1470             :       }
    1471             : 
    1472     9372466 :       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    1473     2841651 :         if (LiveInts->hasInterval(Reg)) {
    1474             :           // This is a virtual register interval.
    1475     2841651 :           const LiveInterval &LI = LiveInts->getInterval(Reg);
    1476     2841651 :           checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
    1477             : 
    1478     2841651 :           if (LI.hasSubRanges() && !MO->isDef()) {
    1479             :             unsigned SubRegIdx = MO->getSubReg();
    1480             :             LaneBitmask MOMask = SubRegIdx != 0
    1481      504174 :                                ? TRI->getSubRegIndexLaneMask(SubRegIdx)
    1482      789305 :                                : MRI->getMaxLaneMaskForVReg(Reg);
    1483             :             LaneBitmask LiveInMask;
    1484     3794673 :             for (const LiveInterval::SubRange &SR : LI.subranges()) {
    1485     3005368 :               if ((MOMask & SR.LaneMask).none())
    1486     1585376 :                 continue;
    1487     1419992 :               checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
    1488     1419992 :               LiveQueryResult LRQ = SR.Query(UseIdx);
    1489     1419992 :               if (LRQ.valueIn())
    1490             :                 LiveInMask |= SR.LaneMask;
    1491             :             }
    1492             :             // At least parts of the register has to be live at the use.
    1493      789305 :             if ((LiveInMask & MOMask).none()) {
    1494           0 :               report("No live subrange at use", MO, MONum);
    1495           0 :               report_context(LI);
    1496           0 :               report_context(UseIdx);
    1497             :             }
    1498             :           }
    1499             :         } else {
    1500           0 :           report("Virtual register has no live interval", MO, MONum);
    1501             :         }
    1502             :       }
    1503             :     }
    1504             : 
    1505             :     // Use of a dead register.
    1506             :     if (!regsLive.count(Reg)) {
    1507    22481874 :       if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
    1508             :         // Reserved registers may be used even when 'dead'.
    1509    10764542 :         bool Bad = !isReserved(Reg);
    1510             :         // We are fine if just any subregister has a defined value.
    1511    10764542 :         if (Bad) {
    1512     1902835 :           for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
    1513             :                ++SubRegs) {
    1514     1974802 :             if (regsLive.count(*SubRegs)) {
    1515             :               Bad = false;
    1516             :               break;
    1517             :             }
    1518             :           }
    1519             :         }
    1520             :         // If there is an additional implicit-use of a super register we stop
    1521             :         // here. By definition we are fine if the super register is not
    1522             :         // (completely) dead, if the complete super register is dead we will
    1523             :         // get a report for its operand.
    1524    10764542 :         if (Bad) {
    1525         143 :           for (const MachineOperand &MOP : MI->uses()) {
    1526          91 :             if (!MOP.isReg() || !MOP.isImplicit())
    1527             :               continue;
    1528             : 
    1529         132 :             if (!TargetRegisterInfo::isPhysicalRegister(MOP.getReg()))
    1530             :               continue;
    1531             : 
    1532         274 :             for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
    1533             :                  ++SubRegs) {
    1534         169 :               if (*SubRegs == Reg) {
    1535             :                 Bad = false;
    1536             :                 break;
    1537             :               }
    1538             :             }
    1539             :           }
    1540             :         }
    1541    10764542 :         if (Bad)
    1542           1 :           report("Using an undefined physical register", MO, MONum);
    1543      476395 :       } else if (MRI->def_empty(Reg)) {
    1544           0 :         report("Reading virtual register without a def", MO, MONum);
    1545             :       } else {
    1546      476395 :         BBInfo &MInfo = MBBInfoMap[MI->getParent()];
    1547             :         // We don't know which virtual registers are live in, so only complain
    1548             :         // if vreg was killed in this MBB. Otherwise keep track of vregs that
    1549             :         // must be live in. PHI instructions are handled separately.
    1550             :         if (MInfo.regsKilled.count(Reg))
    1551           0 :           report("Using a killed virtual register", MO, MONum);
    1552      476395 :         else if (!MI->isPHI())
    1553      308994 :           MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
    1554             :       }
    1555             :     }
    1556             :   }
    1557             : 
    1558    60803405 :   if (MO->isDef()) {
    1559             :     // Register defined.
    1560             :     // TODO: verify that earlyclobber ops are not used.
    1561    22540354 :     if (MO->isDead())
    1562     2002743 :       addRegWithSubRegs(regsDead, Reg);
    1563             :     else
    1564    20537611 :       addRegWithSubRegs(regsDefined, Reg);
    1565             : 
    1566             :     // Verify SSA form.
    1567    54236947 :     if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
    1568     9156239 :         std::next(MRI->def_begin(Reg)) != MRI->def_end())
    1569           0 :       report("Multiple virtual register defs in SSA form", MO, MONum);
    1570             : 
    1571             :     // Check LiveInts for a live segment, but only for virtual registers.
    1572    22540354 :     if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
    1573     2612769 :       SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
    1574             :       DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
    1575             : 
    1576     5225538 :       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    1577     2091646 :         if (LiveInts->hasInterval(Reg)) {
    1578     2091646 :           const LiveInterval &LI = LiveInts->getInterval(Reg);
    1579     2091646 :           checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
    1580             : 
    1581     2091646 :           if (LI.hasSubRanges()) {
    1582             :             unsigned SubRegIdx = MO->getSubReg();
    1583             :             LaneBitmask MOMask = SubRegIdx != 0
    1584      636547 :               ? TRI->getSubRegIndexLaneMask(SubRegIdx)
    1585      749104 :               : MRI->getMaxLaneMaskForVReg(Reg);
    1586     3358265 :             for (const LiveInterval::SubRange &SR : LI.subranges()) {
    1587     5218322 :               if ((SR.LaneMask & MOMask).none())
    1588             :                 continue;
    1589     1043028 :               checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
    1590             :             }
    1591             :           }
    1592             :         } else {
    1593           0 :           report("Virtual register has no Live interval", MO, MONum);
    1594             :         }
    1595             :       }
    1596             :     }
    1597             :   }
    1598    60803405 : }
    1599             : 
    1600           0 : void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {}
    1601             : 
    1602             : // This function gets called after visiting all instructions in a bundle. The
    1603             : // argument points to the bundle header.
    1604             : // Normal stand-alone instructions are also considered 'bundles', and this
    1605             : // function is called for all of them.
    1606    24347941 : void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
    1607    24347941 :   BBInfo &MInfo = MBBInfoMap[MI->getParent()];
    1608    24347941 :   set_union(MInfo.regsKilled, regsKilled);
    1609             :   set_subtract(regsLive, regsKilled); regsKilled.clear();
    1610             :   // Kill any masked registers.
    1611    24562972 :   while (!regMasks.empty()) {
    1612             :     const uint32_t *Mask = regMasks.pop_back_val();
    1613     5579096 :     for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
    1614    10728130 :       if (TargetRegisterInfo::isPhysicalRegister(*I) &&
    1615             :           MachineOperand::clobbersPhysReg(Mask, *I))
    1616     2018264 :         regsDead.push_back(*I);
    1617             :   }
    1618             :   set_subtract(regsLive, regsDead);   regsDead.clear();
    1619    24347941 :   set_union(regsLive, regsDefined);   regsDefined.clear();
    1620    24347941 : }
    1621             : 
    1622             : void
    1623     2024712 : MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
    1624     2024712 :   MBBInfoMap[MBB].regsLiveOut = regsLive;
    1625             :   regsLive.clear();
    1626             : 
    1627     2024712 :   if (Indexes) {
    1628      289032 :     SlotIndex stop = Indexes->getMBBEndIdx(MBB);
    1629      289032 :     if (!(stop > lastIndex)) {
    1630           0 :       report("Block ends before last instruction index", MBB);
    1631           0 :       errs() << "Block ends at " << stop
    1632           0 :           << " last instruction was at " << lastIndex << '\n';
    1633             :     }
    1634      289032 :     lastIndex = stop;
    1635             :   }
    1636     2024712 : }
    1637             : 
    1638             : // Calculate the largest possible vregsPassed sets. These are the registers that
    1639             : // can pass through an MBB live, but may not be live every time. It is assumed
    1640             : // that all vregsPassed sets are empty before the call.
    1641     1631460 : void MachineVerifier::calcRegsPassed() {
    1642             :   // First push live-out regs to successors' vregsPassed. Remember the MBBs that
    1643             :   // have any vregsPassed.
    1644             :   SmallPtrSet<const MachineBasicBlock*, 8> todo;
    1645     3656172 :   for (const auto &MBB : *MF) {
    1646     2024712 :     BBInfo &MInfo = MBBInfoMap[&MBB];
    1647     2024712 :     if (!MInfo.reachable)
    1648             :       continue;
    1649             :     for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
    1650     2580195 :            SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
    1651      556748 :       BBInfo &SInfo = MBBInfoMap[*SuI];
    1652      556748 :       if (SInfo.addPassed(MInfo.regsLiveOut))
    1653      188295 :         todo.insert(*SuI);
    1654             :     }
    1655             :   }
    1656             : 
    1657             :   // Iteratively push vregsPassed to successors. This will converge to the same
    1658             :   // final state regardless of DenseSet iteration order.
    1659     1858125 :   while (!todo.empty()) {
    1660      226665 :     const MachineBasicBlock *MBB = *todo.begin();
    1661             :     todo.erase(MBB);
    1662      226665 :     BBInfo &MInfo = MBBInfoMap[MBB];
    1663      226665 :     for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
    1664      452383 :            SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
    1665      225718 :       if (*SuI == MBB)
    1666             :         continue;
    1667      202236 :       BBInfo &SInfo = MBBInfoMap[*SuI];
    1668      202236 :       if (SInfo.addPassed(MInfo.vregsPassed))
    1669      136855 :         todo.insert(*SuI);
    1670             :     }
    1671             :   }
    1672     1631460 : }
    1673             : 
    1674             : // Calculate the set of virtual registers that must be passed through each basic
    1675             : // block in order to satisfy the requirements of successor blocks. This is very
    1676             : // similar to calcRegsPassed, only backwards.
    1677     1631460 : void MachineVerifier::calcRegsRequired() {
    1678             :   // First push live-in regs to predecessors' vregsRequired.
    1679             :   SmallPtrSet<const MachineBasicBlock*, 8> todo;
    1680     3656172 :   for (const auto &MBB : *MF) {
    1681     2024712 :     BBInfo &MInfo = MBBInfoMap[&MBB];
    1682             :     for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
    1683     2581769 :            PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
    1684      557057 :       BBInfo &PInfo = MBBInfoMap[*PrI];
    1685      557057 :       if (PInfo.addRequired(MInfo.vregsLiveIn))
    1686       68982 :         todo.insert(*PrI);
    1687             :     }
    1688             :   }
    1689             : 
    1690             :   // Iteratively push vregsRequired to predecessors. This will converge to the
    1691             :   // same final state regardless of DenseSet iteration order.
    1692     1724736 :   while (!todo.empty()) {
    1693       93276 :     const MachineBasicBlock *MBB = *todo.begin();
    1694             :     todo.erase(MBB);
    1695       93276 :     BBInfo &MInfo = MBBInfoMap[MBB];
    1696       93276 :     for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
    1697      226697 :            PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
    1698      133421 :       if (*PrI == MBB)
    1699             :         continue;
    1700      115837 :       BBInfo &SInfo = MBBInfoMap[*PrI];
    1701      115837 :       if (SInfo.addRequired(MInfo.vregsRequired))
    1702       44787 :         todo.insert(*PrI);
    1703             :     }
    1704             :   }
    1705     1631460 : }
    1706             : 
    1707             : // Check PHI instructions at the beginning of MBB. It is assumed that
    1708             : // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
    1709     2024712 : void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
    1710     2024712 :   BBInfo &MInfo = MBBInfoMap[&MBB];
    1711             : 
    1712             :   SmallPtrSet<const MachineBasicBlock*, 8> seen;
    1713     2107564 :   for (const MachineInstr &Phi : MBB) {
    1714             :     if (!Phi.isPHI())
    1715             :       break;
    1716       82852 :     seen.clear();
    1717             : 
    1718       82852 :     const MachineOperand &MODef = Phi.getOperand(0);
    1719       82852 :     if (!MODef.isReg() || !MODef.isDef()) {
    1720           0 :       report("Expected first PHI operand to be a register def", &MODef, 0);
    1721           0 :       continue;
    1722             :     }
    1723       82852 :     if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
    1724      165704 :         MODef.isEarlyClobber() || MODef.isDebug())
    1725           0 :       report("Unexpected flag on PHI operand", &MODef, 0);
    1726       82852 :     unsigned DefReg = MODef.getReg();
    1727       82852 :     if (!TargetRegisterInfo::isVirtualRegister(DefReg))
    1728           0 :       report("Expected first PHI operand to be a virtual register", &MODef, 0);
    1729             : 
    1730      250339 :     for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
    1731      167487 :       const MachineOperand &MO0 = Phi.getOperand(I);
    1732      167487 :       if (!MO0.isReg()) {
    1733           0 :         report("Expected PHI operand to be a register", &MO0, I);
    1734           0 :         continue;
    1735             :       }
    1736      167487 :       if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
    1737      334974 :           MO0.isDebug() || MO0.isTied())
    1738           0 :         report("Unexpected flag on PHI operand", &MO0, I);
    1739             : 
    1740      167487 :       const MachineOperand &MO1 = Phi.getOperand(I + 1);
    1741      167487 :       if (!MO1.isMBB()) {
    1742           0 :         report("Expected PHI operand to be a basic block", &MO1, I + 1);
    1743           0 :         continue;
    1744             :       }
    1745             : 
    1746      167487 :       const MachineBasicBlock &Pre = *MO1.getMBB();
    1747      167487 :       if (!Pre.isSuccessor(&MBB)) {
    1748           0 :         report("PHI input is not a predecessor block", &MO1, I + 1);
    1749           0 :         continue;
    1750             :       }
    1751             : 
    1752      167487 :       if (MInfo.reachable) {
    1753      167481 :         seen.insert(&Pre);
    1754      167481 :         BBInfo &PrInfo = MBBInfoMap[&Pre];
    1755      334954 :         if (!MO0.isUndef() && PrInfo.reachable &&
    1756      167473 :             !PrInfo.isLiveOut(MO0.getReg()))
    1757           2 :           report("PHI operand is not live-out from predecessor", &MO0, I);
    1758             :       }
    1759             :     }
    1760             : 
    1761             :     // Did we see all predecessors?
    1762       82852 :     if (MInfo.reachable) {
    1763      250223 :       for (MachineBasicBlock *Pred : MBB.predecessors()) {
    1764      167377 :         if (!seen.count(Pred)) {
    1765           0 :           report("Missing PHI operand", &Phi);
    1766           0 :           errs() << printMBBReference(*Pred)
    1767           0 :                  << " is a predecessor according to the CFG.\n";
    1768             :         }
    1769             :       }
    1770             :     }
    1771             :   }
    1772     2024712 : }
    1773             : 
    1774     1631460 : void MachineVerifier::visitMachineFunctionAfter() {
    1775     1631460 :   calcRegsPassed();
    1776             : 
    1777     3656172 :   for (const MachineBasicBlock &MBB : *MF)
    1778     2024712 :     checkPHIOps(MBB);
    1779             : 
    1780             :   // Now check liveness info if available
    1781     1631460 :   calcRegsRequired();
    1782             : 
    1783             :   // Check for killed virtual registers that should be live out.
    1784     3656172 :   for (const auto &MBB : *MF) {
    1785     2024712 :     BBInfo &MInfo = MBBInfoMap[&MBB];
    1786             :     for (RegSet::iterator
    1787     2407534 :          I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
    1788             :          ++I)
    1789             :       if (MInfo.regsKilled.count(*I)) {
    1790           0 :         report("Virtual register killed in block, but needed live out.", &MBB);
    1791           0 :         errs() << "Virtual register " << printReg(*I)
    1792           0 :                << " is used after the block.\n";
    1793             :       }
    1794             :   }
    1795             : 
    1796     3262920 :   if (!MF->empty()) {
    1797     1631440 :     BBInfo &MInfo = MBBInfoMap[&MF->front()];
    1798             :     for (RegSet::iterator
    1799     1631440 :          I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
    1800             :          ++I) {
    1801           0 :       report("Virtual register defs don't dominate all uses.", MF);
    1802           0 :       report_context_vreg(*I);
    1803             :     }
    1804             :   }
    1805             : 
    1806     1631460 :   if (LiveVars)
    1807         117 :     verifyLiveVariables();
    1808     1631460 :   if (LiveInts)
    1809      195355 :     verifyLiveIntervals();
    1810     1631460 : }
    1811             : 
    1812         117 : void MachineVerifier::verifyLiveVariables() {
    1813             :   assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
    1814         642 :   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
    1815         525 :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
    1816         525 :     LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
    1817        1224 :     for (const auto &MBB : *MF) {
    1818         699 :       BBInfo &MInfo = MBBInfoMap[&MBB];
    1819             : 
    1820             :       // Our vregsRequired should be identical to LiveVariables' AliveBlocks
    1821             :       if (MInfo.vregsRequired.count(Reg)) {
    1822           0 :         if (!VI.AliveBlocks.test(MBB.getNumber())) {
    1823           0 :           report("LiveVariables: Block missing from AliveBlocks", &MBB);
    1824           0 :           errs() << "Virtual register " << printReg(Reg)
    1825           0 :                  << " must be live through the block.\n";
    1826             :         }
    1827             :       } else {
    1828         699 :         if (VI.AliveBlocks.test(MBB.getNumber())) {
    1829           0 :           report("LiveVariables: Block should not be in AliveBlocks", &MBB);
    1830           0 :           errs() << "Virtual register " << printReg(Reg)
    1831           0 :                  << " is not needed live through the block.\n";
    1832             :         }
    1833             :       }
    1834             :     }
    1835             :   }
    1836         117 : }
    1837             : 
    1838      195355 : void MachineVerifier::verifyLiveIntervals() {
    1839             :   assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
    1840     4698833 :   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
    1841             :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
    1842             : 
    1843             :     // Spilling and splitting may leave unused registers around. Skip them.
    1844     4503478 :     if (MRI->reg_nodbg_empty(Reg))
    1845             :       continue;
    1846             : 
    1847     1600712 :     if (!LiveInts->hasInterval(Reg)) {
    1848           0 :       report("Missing live interval for virtual register", MF);
    1849           0 :       errs() << printReg(Reg, TRI) << " still has defs or uses\n";
    1850           0 :       continue;
    1851             :     }
    1852             : 
    1853     1600712 :     const LiveInterval &LI = LiveInts->getInterval(Reg);
    1854             :     assert(Reg == LI.reg && "Invalid reg to interval mapping");
    1855     1600712 :     verifyLiveInterval(LI);
    1856             :   }
    1857             : 
    1858             :   // Verify all the cached regunit intervals.
    1859    65361384 :   for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
    1860   130332058 :     if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
    1861      702943 :       verifyLiveRange(*LR, i);
    1862      195355 : }
    1863             : 
    1864     3889372 : void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
    1865             :                                            const VNInfo *VNI, unsigned Reg,
    1866             :                                            LaneBitmask LaneMask) {
    1867     3889372 :   if (VNI->isUnused())
    1868             :     return;
    1869             : 
    1870           0 :   const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
    1871             : 
    1872     3888589 :   if (!DefVNI) {
    1873           0 :     report("Value not live at VNInfo def and not marked unused", MF);
    1874           0 :     report_context(LR, Reg, LaneMask);
    1875           0 :     report_context(*VNI);
    1876           0 :     return;
    1877             :   }
    1878             : 
    1879     3888589 :   if (DefVNI != VNI) {
    1880           0 :     report("Live segment at def has different VNInfo", MF);
    1881           0 :     report_context(LR, Reg, LaneMask);
    1882           0 :     report_context(*VNI);
    1883           0 :     return;
    1884             :   }
    1885             : 
    1886     3888589 :   const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
    1887     3888589 :   if (!MBB) {
    1888           0 :     report("Invalid VNInfo definition index", MF);
    1889           0 :     report_context(LR, Reg, LaneMask);
    1890           0 :     report_context(*VNI);
    1891           0 :     return;
    1892             :   }
    1893             : 
    1894     3888589 :   if (VNI->isPHIDef()) {
    1895     1007534 :     if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
    1896           0 :       report("PHIDef VNInfo is not defined at MBB start", MBB);
    1897           0 :       report_context(LR, Reg, LaneMask);
    1898           0 :       report_context(*VNI);
    1899             :     }
    1900      503767 :     return;
    1901             :   }
    1902             : 
    1903             :   // Non-PHI def.
    1904             :   const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
    1905     3384822 :   if (!MI) {
    1906           0 :     report("No instruction at VNInfo def index", MBB);
    1907           0 :     report_context(LR, Reg, LaneMask);
    1908           0 :     report_context(*VNI);
    1909           0 :     return;
    1910             :   }
    1911             : 
    1912     3384822 :   if (Reg != 0) {
    1913             :     bool hasDef = false;
    1914             :     bool isEarlyClobber = false;
    1915    17178668 :     for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
    1916    13812183 :       if (!MOI->isReg() || !MOI->isDef())
    1917             :         continue;
    1918     4037757 :       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    1919     3561490 :         if (MOI->getReg() != Reg)
    1920             :           continue;
    1921             :       } else {
    1922     1365434 :         if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
    1923      412900 :             !TRI->hasRegUnit(MOI->getReg(), Reg))
    1924      243865 :           continue;
    1925             :       }
    1926     3367493 :       if (LaneMask.any() &&
    1927     2086314 :           (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
    1928             :         continue;
    1929             :       hasDef = true;
    1930     3367471 :       if (MOI->isEarlyClobber())
    1931             :         isEarlyClobber = true;
    1932             :     }
    1933             : 
    1934     3366485 :     if (!hasDef) {
    1935           0 :       report("Defining instruction does not modify register", MI);
    1936           0 :       report_context(LR, Reg, LaneMask);
    1937           0 :       report_context(*VNI);
    1938             :     }
    1939             : 
    1940             :     // Early clobber defs begin at USE slots, but other defs must begin at
    1941             :     // DEF slots.
    1942     3366485 :     if (isEarlyClobber) {
    1943       17421 :       if (!VNI->def.isEarlyClobber()) {
    1944           0 :         report("Early clobber def must be at an early-clobber slot", MBB);
    1945           0 :         report_context(LR, Reg, LaneMask);
    1946           0 :         report_context(*VNI);
    1947             :       }
    1948     3349064 :     } else if (!VNI->def.isRegister()) {
    1949           0 :       report("Non-PHI, non-early clobber def must be at a register slot", MBB);
    1950           0 :       report_context(LR, Reg, LaneMask);
    1951           0 :       report_context(*VNI);
    1952             :     }
    1953             :   }
    1954             : }
    1955             : 
    1956     3910510 : void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
    1957             :                                              const LiveRange::const_iterator I,
    1958             :                                              unsigned Reg, LaneBitmask LaneMask)
    1959             : {
    1960             :   const LiveRange::Segment &S = *I;
    1961     3910510 :   const VNInfo *VNI = S.valno;
    1962             :   assert(VNI && "Live segment has no valno");
    1963             : 
    1964     7821020 :   if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
    1965           0 :     report("Foreign valno in live segment", MF);
    1966           0 :     report_context(LR, Reg, LaneMask);
    1967           0 :     report_context(S);
    1968           0 :     report_context(*VNI);
    1969             :   }
    1970             : 
    1971     3910510 :   if (VNI->isUnused()) {
    1972           0 :     report("Live segment valno is marked unused", MF);
    1973           0 :     report_context(LR, Reg, LaneMask);
    1974           0 :     report_context(S);
    1975             :   }
    1976             : 
    1977     3910510 :   const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
    1978     3910510 :   if (!MBB) {
    1979           0 :     report("Bad start of live segment, no basic block", MF);
    1980           0 :     report_context(LR, Reg, LaneMask);
    1981           0 :     report_context(S);
    1982     3374138 :     return;
    1983             :   }
    1984     3910510 :   SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
    1985     3910510 :   if (S.start != MBBStartIdx && S.start != VNI->def) {
    1986           0 :     report("Live segment must begin at MBB entry or valno def", MBB);
    1987           0 :     report_context(LR, Reg, LaneMask);
    1988           0 :     report_context(S);
    1989             :   }
    1990             : 
    1991             :   const MachineBasicBlock *EndMBB =
    1992     7821020 :     LiveInts->getMBBFromIndex(S.end.getPrevSlot());
    1993     3910510 :   if (!EndMBB) {
    1994           0 :     report("Bad end of live segment, no basic block", MF);
    1995           0 :     report_context(LR, Reg, LaneMask);
    1996           0 :     report_context(S);
    1997           0 :     return;
    1998             :   }
    1999             : 
    2000             :   // No more checks for live-out segments.
    2001     7821020 :   if (S.end == LiveInts->getMBBEndIdx(EndMBB))
    2002             :     return;
    2003             : 
    2004             :   // RegUnit intervals are allowed dead phis.
    2005      724102 :   if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
    2006     4297274 :       S.start == VNI->def && S.end == VNI->def.getDeadSlot())
    2007             :     return;
    2008             : 
    2009             :   // The live segment is ending inside EndMBB
    2010             :   const MachineInstr *MI =
    2011             :     LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
    2012     3821828 :   if (!MI) {
    2013           0 :     report("Live segment doesn't end at a valid instruction", EndMBB);
    2014           0 :     report_context(LR, Reg, LaneMask);
    2015           0 :     report_context(S);
    2016           0 :     return;
    2017             :   }
    2018             : 
    2019             :   // The block slot must refer to a basic block boundary.
    2020     3821828 :   if (S.end.isBlock()) {
    2021           0 :     report("Live segment ends at B slot of an instruction", EndMBB);
    2022           0 :     report_context(LR, Reg, LaneMask);
    2023           0 :     report_context(S);
    2024             :   }
    2025             : 
    2026     3821828 :   if (S.end.isDead()) {
    2027             :     // Segment ends on the dead slot.
    2028             :     // That means there must be a dead def.
    2029      143255 :     if (!SlotIndex::isSameInstr(S.start, S.end)) {
    2030           0 :       report("Live segment ending at dead slot spans instructions", EndMBB);
    2031           0 :       report_context(LR, Reg, LaneMask);
    2032           0 :       report_context(S);
    2033             :     }
    2034             :   }
    2035             : 
    2036             :   // A live segment can only end at an early-clobber slot if it is being
    2037             :   // redefined by an early-clobber def.
    2038     3821828 :   if (S.end.isEarlyClobber()) {
    2039       10864 :     if (I+1 == LR.end() || (I+1)->start != S.end) {
    2040           0 :       report("Live segment ending at early clobber slot must be "
    2041             :              "redefined by an EC def in the same instruction", EndMBB);
    2042           0 :       report_context(LR, Reg, LaneMask);
    2043           0 :       report_context(S);
    2044             :     }
    2045             :   }
    2046             : 
    2047             :   // The following checks only apply to virtual registers. Physreg liveness
    2048             :   // is too weird to check.
    2049     3821828 :   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    2050             :     // A live segment can end with either a redefinition, a kill flag on a
    2051             :     // use, or a dead flag on a def.
    2052             :     bool hasRead = false;
    2053             :     bool hasSubRegDef = false;
    2054             :     bool hasDeadDef = false;
    2055    19807146 :     for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
    2056    16708025 :       if (!MOI->isReg() || MOI->getReg() != Reg)
    2057             :         continue;
    2058             :       unsigned Sub = MOI->getSubReg();
    2059      969859 :       LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
    2060     3228235 :                                  : LaneBitmask::getAll();
    2061     3228235 :       if (MOI->isDef()) {
    2062      535945 :         if (Sub != 0) {
    2063             :           hasSubRegDef = true;
    2064             :           // An operand %0:sub0 reads %0:sub1..n. Invert the lane
    2065             :           // mask for subregister defs. Read-undef defs will be handled by
    2066             :           // readsReg below.
    2067             :           SLM = ~SLM;
    2068             :         }
    2069      535945 :         if (MOI->isDead())
    2070             :           hasDeadDef = true;
    2071             :       }
    2072     3228235 :       if (LaneMask.any() && (LaneMask & SLM).none())
    2073             :         continue;
    2074             :       if (MOI->readsReg())
    2075             :         hasRead = true;
    2076             :     }
    2077     3099121 :     if (S.end.isDead()) {
    2078             :       // Make sure that the corresponding machine operand for a "dead" live
    2079             :       // range has the dead flag. We cannot perform this check for subregister
    2080             :       // liveranges as partially dead values are allowed.
    2081       46610 :       if (LaneMask.none() && !hasDeadDef) {
    2082           0 :         report("Instruction ending live segment on dead slot has no dead flag",
    2083             :                MI);
    2084           0 :         report_context(LR, Reg, LaneMask);
    2085           0 :         report_context(S);
    2086             :       }
    2087             :     } else {
    2088     3052511 :       if (!hasRead) {
    2089             :         // When tracking subregister liveness, the main range must start new
    2090             :         // values on partial register writes, even if there is no read.
    2091           2 :         if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
    2092             :             !hasSubRegDef) {
    2093           0 :           report("Instruction ending live segment doesn't read the register",
    2094             :                  MI);
    2095           0 :           report_context(LR, Reg, LaneMask);
    2096           0 :           report_context(S);
    2097             :         }
    2098             :       }
    2099             :     }
    2100             :   }
    2101             : 
    2102             :   // Now check all the basic blocks in this live segment.
    2103     3821828 :   MachineFunction::const_iterator MFI = MBB->getIterator();
    2104             :   // Is this live segment the beginning of a non-PHIDef VN?
    2105     3821828 :   if (S.start == VNI->def && !VNI->isPHIDef()) {
    2106             :     // Not live-in to any blocks.
    2107     3322297 :     if (MBB == EndMBB)
    2108             :       return;
    2109             :     // Skip this block.
    2110             :     ++MFI;
    2111             :   }
    2112             : 
    2113             :   SmallVector<SlotIndex, 4> Undefs;
    2114      536372 :   if (LaneMask.any()) {
    2115        9780 :     LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
    2116        9780 :     OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
    2117             :   }
    2118             : 
    2119             :   while (true) {
    2120             :     assert(LiveInts->isLiveInToMBB(LR, &*MFI));
    2121             :     // We don't know how to track physregs into a landing pad.
    2122      595384 :     if (!TargetRegisterInfo::isVirtualRegister(Reg) &&
    2123      472656 :         MFI->isEHPad()) {
    2124          71 :       if (&*MFI == EndMBB)
    2125             :         break;
    2126             :       ++MFI;
    2127           0 :       continue;
    2128             :     }
    2129             : 
    2130             :     // Is VNI a PHI-def in the current block?
    2131      595313 :     bool IsPHI = VNI->isPHIDef() &&
    2132      499195 :       VNI->def == LiveInts->getMBBStartIdx(&*MFI);
    2133             : 
    2134             :     // Check that VNI is live-out of all predecessors.
    2135             :     for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
    2136      779306 :          PE = MFI->pred_end(); PI != PE; ++PI) {
    2137      183993 :       SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
    2138      183993 :       const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
    2139             : 
    2140             :       // All predecessors must have a live-out value. However for a phi
    2141             :       // instruction with subregister intervals
    2142             :       // only one of the subregisters (not necessarily the current one) needs to
    2143             :       // be defined.
    2144      183993 :       if (!PVNI && (LaneMask.none() || !IsPHI)) {
    2145           0 :         if (LiveRangeCalc::isJointlyDominated(*PI, Undefs, *Indexes))
    2146             :           continue;
    2147           0 :         report("Register not marked live out of predecessor", *PI);
    2148           0 :         report_context(LR, Reg, LaneMask);
    2149           0 :         report_context(*VNI);
    2150           0 :         errs() << " live into " << printMBBReference(*MFI) << '@'
    2151           0 :                << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
    2152           0 :                << PEnd << '\n';
    2153           0 :         continue;
    2154             :       }
    2155             : 
    2156             :       // Only PHI-defs can take different predecessor values.
    2157      183993 :       if (!IsPHI && PVNI != VNI) {
    2158           0 :         report("Different value live out of predecessor", *PI);
    2159           0 :         report_context(LR, Reg, LaneMask);
    2160           0 :         errs() << "Valno #" << PVNI->id << " live out of "
    2161           0 :                << printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
    2162           0 :                << VNI->id << " live into " << printMBBReference(*MFI) << '@'
    2163           0 :                << LiveInts->getMBBStartIdx(&*MFI) << '\n';
    2164             :       }
    2165             :     }
    2166      595313 :     if (&*MFI == EndMBB)
    2167             :       break;
    2168             :     ++MFI;
    2169             :   }
    2170             : }
    2171             : 
    2172     3317523 : void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
    2173             :                                       LaneBitmask LaneMask) {
    2174     7206895 :   for (const VNInfo *VNI : LR.valnos)
    2175     3889372 :     verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
    2176             : 
    2177     7228033 :   for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
    2178     3910510 :     verifyLiveRangeSegment(LR, I, Reg, LaneMask);
    2179     3317523 : }
    2180             : 
    2181     1600712 : void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
    2182     1600712 :   unsigned Reg = LI.reg;
    2183             :   assert(TargetRegisterInfo::isVirtualRegister(Reg));
    2184     1600712 :   verifyLiveRange(LI, Reg);
    2185             : 
    2186             :   LaneBitmask Mask;
    2187     1600712 :   LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
    2188     2614580 :   for (const LiveInterval::SubRange &SR : LI.subranges()) {
    2189     1013868 :     if ((Mask & SR.LaneMask).any()) {
    2190           0 :       report("Lane masks of sub ranges overlap in live interval", MF);
    2191           0 :       report_context(LI);
    2192             :     }
    2193     3041604 :     if ((SR.LaneMask & ~MaxMask).any()) {
    2194           0 :       report("Subrange lanemask is invalid", MF);
    2195           0 :       report_context(LI);
    2196             :     }
    2197     1013868 :     if (SR.empty()) {
    2198           0 :       report("Subrange must not be empty", MF);
    2199           0 :       report_context(SR, LI.reg, SR.LaneMask);
    2200             :     }
    2201             :     Mask |= SR.LaneMask;
    2202     1013868 :     verifyLiveRange(SR, LI.reg, SR.LaneMask);
    2203     1013868 :     if (!LI.covers(SR)) {
    2204           0 :       report("A Subrange is not covered by the main range", MF);
    2205           0 :       report_context(LI);
    2206             :     }
    2207             :   }
    2208             : 
    2209             :   // Check the LI only has one connected component.
    2210     1600712 :   ConnectedVNInfoEqClasses ConEQ(*LiveInts);
    2211     1600712 :   unsigned NumComp = ConEQ.Classify(LI);
    2212     1600712 :   if (NumComp > 1) {
    2213           0 :     report("Multiple connected components in live interval", MF);
    2214           0 :     report_context(LI);
    2215           0 :     for (unsigned comp = 0; comp != NumComp; ++comp) {
    2216           0 :       errs() << comp << ": valnos";
    2217           0 :       for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
    2218           0 :            E = LI.vni_end(); I!=E; ++I)
    2219           0 :         if (comp == ConEQ.getEqClass(*I))
    2220           0 :           errs() << ' ' << (*I)->id;
    2221           0 :       errs() << '\n';
    2222             :     }
    2223             :   }
    2224     1600712 : }
    2225             : 
    2226             : namespace {
    2227             : 
    2228             :   // FrameSetup and FrameDestroy can have zero adjustment, so using a single
    2229             :   // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
    2230             :   // value is zero.
    2231             :   // We use a bool plus an integer to capture the stack state.
    2232             :   struct StackStateOfBB {
    2233             :     StackStateOfBB() = default;
    2234             :     StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
    2235             :       EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
    2236             :       ExitIsSetup(ExitSetup) {}
    2237             : 
    2238             :     // Can be negative, which means we are setting up a frame.
    2239             :     int EntryValue = 0;
    2240             :     int ExitValue = 0;
    2241             :     bool EntryIsSetup = false;
    2242             :     bool ExitIsSetup = false;
    2243             :   };
    2244             : 
    2245             : } // end anonymous namespace
    2246             : 
    2247             : /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
    2248             : /// by a FrameDestroy <n>, stack adjustments are identical on all
    2249             : /// CFG edges to a merge point, and frame is destroyed at end of a return block.
    2250     1631440 : void MachineVerifier::verifyStackFrame() {
    2251     1631440 :   unsigned FrameSetupOpcode   = TII->getCallFrameSetupOpcode();
    2252     1631440 :   unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
    2253     1631440 :   if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
    2254       30478 :     return;
    2255             : 
    2256     1600962 :   SmallVector<StackStateOfBB, 8> SPState;
    2257     3201924 :   SPState.resize(MF->getNumBlockIDs());
    2258             :   df_iterator_default_set<const MachineBasicBlock*> Reachable;
    2259             : 
    2260             :   // Visit the MBBs in DFS order.
    2261             :   for (df_ext_iterator<const MachineFunction *,
    2262             :                        df_iterator_default_set<const MachineBasicBlock *>>
    2263     1600962 :        DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
    2264     3593345 :        DFI != DFE; ++DFI) {
    2265     1992383 :     const MachineBasicBlock *MBB = *DFI;
    2266             : 
    2267             :     StackStateOfBB BBState;
    2268             :     // Check the exit state of the DFS stack predecessor.
    2269     1992383 :     if (DFI.getPathLength() >= 2) {
    2270      391421 :       const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
    2271             :       assert(Reachable.count(StackPred) &&
    2272             :              "DFS stack predecessor is already visited.\n");
    2273      391421 :       BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
    2274      391421 :       BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
    2275             :       BBState.ExitValue = BBState.EntryValue;
    2276             :       BBState.ExitIsSetup = BBState.EntryIsSetup;
    2277             :     }
    2278             : 
    2279             :     // Update stack state by checking contents of MBB.
    2280    25718320 :     for (const auto &I : *MBB) {
    2281    47451874 :       if (I.getOpcode() == FrameSetupOpcode) {
    2282      120431 :         if (BBState.ExitIsSetup)
    2283           1 :           report("FrameSetup is after another FrameSetup", &I);
    2284      240862 :         BBState.ExitValue -= TII->getFrameTotalSize(I);
    2285             :         BBState.ExitIsSetup = true;
    2286             :       }
    2287             : 
    2288    47451874 :       if (I.getOpcode() == FrameDestroyOpcode) {
    2289      120431 :         int Size = TII->getFrameTotalSize(I);
    2290      120431 :         if (!BBState.ExitIsSetup)
    2291           1 :           report("FrameDestroy is not after a FrameSetup", &I);
    2292      120431 :         int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
    2293             :                                                BBState.ExitValue;
    2294      120431 :         if (BBState.ExitIsSetup && AbsSPAdj != Size) {
    2295           1 :           report("FrameDestroy <n> is after FrameSetup <m>", &I);
    2296           2 :           errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
    2297           1 :               << AbsSPAdj << ">.\n";
    2298             :         }
    2299      120431 :         BBState.ExitValue += Size;
    2300             :         BBState.ExitIsSetup = false;
    2301             :       }
    2302             :     }
    2303     3984766 :     SPState[MBB->getNumber()] = BBState;
    2304             : 
    2305             :     // Make sure the exit state of any predecessor is consistent with the entry
    2306             :     // state.
    2307             :     for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
    2308     2548364 :          E = MBB->pred_end(); I != E; ++I) {
    2309      555981 :       if (Reachable.count(*I) &&
    2310      962270 :           (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
    2311      481135 :            SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
    2312           0 :         report("The exit stack state of a predecessor is inconsistent.", MBB);
    2313           0 :         errs() << "Predecessor " << printMBBReference(*(*I))
    2314           0 :                << " has exit state (" << SPState[(*I)->getNumber()].ExitValue
    2315           0 :                << ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while "
    2316           0 :                << printMBBReference(*MBB) << " has entry state ("
    2317           0 :                << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
    2318             :       }
    2319             :     }
    2320             : 
    2321             :     // Make sure the entry state of any successor is consistent with the exit
    2322             :     // state.
    2323             :     for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
    2324     2548296 :          E = MBB->succ_end(); I != E; ++I) {
    2325      555913 :       if (Reachable.count(*I) &&
    2326      242106 :           (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
    2327      121053 :            SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
    2328           0 :         report("The entry stack state of a successor is inconsistent.", MBB);
    2329           0 :         errs() << "Successor " << printMBBReference(*(*I))
    2330           0 :                << " has entry state (" << SPState[(*I)->getNumber()].EntryValue
    2331           0 :                << ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while "
    2332           0 :                << printMBBReference(*MBB) << " has exit state ("
    2333           0 :                << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
    2334             :       }
    2335             :     }
    2336             : 
    2337             :     // Make sure a basic block with return ends with zero stack adjustment.
    2338     3968448 :     if (!MBB->empty() && MBB->back().isReturn()) {
    2339     1618019 :       if (BBState.ExitIsSetup)
    2340           0 :         report("A return block ends with a FrameSetup.", MBB);
    2341     1618019 :       if (BBState.ExitValue)
    2342           0 :         report("A return block ends with a nonzero stack adjustment.", MBB);
    2343             :     }
    2344             :   }
    2345             : }

Generated by: LCOV version 1.13