LCOV - code coverage report
Current view: top level - lib/CodeGen - MachineVerifier.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 796 1152 69.1 %
Date: 2018-06-17 00:07:59 Functions: 52 61 85.2 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // Pass to verify generated machine code. The following is checked:
      11             : //
      12             : // Operand counts: All explicit operands must be present.
      13             : //
      14             : // Register classes: All physical and virtual register operands must be
      15             : // compatible with the register class required by the instruction descriptor.
      16             : //
      17             : // Register live intervals: Registers must be defined only once, and must be
      18             : // defined before use.
      19             : //
      20             : // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
      21             : // command-line option -verify-machineinstrs, or by defining the environment
      22             : // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
      23             : // the verifier errors.
      24             : //===----------------------------------------------------------------------===//
      25             : 
      26             : #include "llvm/ADT/BitVector.h"
      27             : #include "llvm/ADT/DenseMap.h"
      28             : #include "llvm/ADT/DenseSet.h"
      29             : #include "llvm/ADT/DepthFirstIterator.h"
      30             : #include "llvm/ADT/STLExtras.h"
      31             : #include "llvm/ADT/SetOperations.h"
      32             : #include "llvm/ADT/SmallPtrSet.h"
      33             : #include "llvm/ADT/SmallVector.h"
      34             : #include "llvm/ADT/StringRef.h"
      35             : #include "llvm/ADT/Twine.h"
      36             : #include "llvm/Analysis/EHPersonalities.h"
      37             : #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
      38             : #include "llvm/CodeGen/LiveInterval.h"
      39             : #include "llvm/CodeGen/LiveIntervals.h"
      40             : #include "llvm/CodeGen/LiveStacks.h"
      41             : #include "llvm/CodeGen/LiveVariables.h"
      42             : #include "llvm/CodeGen/MachineBasicBlock.h"
      43             : #include "llvm/CodeGen/MachineFrameInfo.h"
      44             : #include "llvm/CodeGen/MachineFunction.h"
      45             : #include "llvm/CodeGen/MachineFunctionPass.h"
      46             : #include "llvm/CodeGen/MachineInstr.h"
      47             : #include "llvm/CodeGen/MachineInstrBundle.h"
      48             : #include "llvm/CodeGen/MachineMemOperand.h"
      49             : #include "llvm/CodeGen/MachineOperand.h"
      50             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      51             : #include "llvm/CodeGen/PseudoSourceValue.h"
      52             : #include "llvm/CodeGen/SlotIndexes.h"
      53             : #include "llvm/CodeGen/StackMaps.h"
      54             : #include "llvm/CodeGen/TargetInstrInfo.h"
      55             : #include "llvm/CodeGen/TargetOpcodes.h"
      56             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      57             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      58             : #include "llvm/IR/BasicBlock.h"
      59             : #include "llvm/IR/Function.h"
      60             : #include "llvm/IR/InlineAsm.h"
      61             : #include "llvm/IR/Instructions.h"
      62             : #include "llvm/MC/LaneBitmask.h"
      63             : #include "llvm/MC/MCAsmInfo.h"
      64             : #include "llvm/MC/MCInstrDesc.h"
      65             : #include "llvm/MC/MCRegisterInfo.h"
      66             : #include "llvm/MC/MCTargetOptions.h"
      67             : #include "llvm/Pass.h"
      68             : #include "llvm/Support/Casting.h"
      69             : #include "llvm/Support/ErrorHandling.h"
      70             : #include "llvm/Support/LowLevelTypeImpl.h"
      71             : #include "llvm/Support/MathExtras.h"
      72             : #include "llvm/Support/raw_ostream.h"
      73             : #include "llvm/Target/TargetMachine.h"
      74             : #include <algorithm>
      75             : #include <cassert>
      76             : #include <cstddef>
      77             : #include <cstdint>
      78             : #include <iterator>
      79             : #include <string>
      80             : #include <utility>
      81             : 
      82             : using namespace llvm;
      83             : 
      84             : namespace {
      85             : 
      86     3003774 :   struct MachineVerifier {
      87     4505661 :     MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
      88             : 
      89             :     unsigned verify(MachineFunction &MF);
      90             : 
      91             :     Pass *const PASS;
      92             :     const char *Banner;
      93             :     const MachineFunction *MF;
      94             :     const TargetMachine *TM;
      95             :     const TargetInstrInfo *TII;
      96             :     const TargetRegisterInfo *TRI;
      97             :     const MachineRegisterInfo *MRI;
      98             : 
      99             :     unsigned foundErrors;
     100             : 
     101             :     // Avoid querying the MachineFunctionProperties for each operand.
     102             :     bool isFunctionRegBankSelected;
     103             :     bool isFunctionSelected;
     104             : 
     105             :     using RegVector = SmallVector<unsigned, 16>;
     106             :     using RegMaskVector = SmallVector<const uint32_t *, 4>;
     107             :     using RegSet = DenseSet<unsigned>;
     108             :     using RegMap = DenseMap<unsigned, const MachineInstr *>;
     109             :     using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
     110             : 
     111             :     const MachineInstr *FirstTerminator;
     112             :     BlockSet FunctionBlocks;
     113             : 
     114             :     BitVector regsReserved;
     115             :     RegSet regsLive;
     116             :     RegVector regsDefined, regsDead, regsKilled;
     117             :     RegMaskVector regMasks;
     118             : 
     119             :     SlotIndex lastIndex;
     120             : 
     121             :     // Add Reg and any sub-registers to RV
     122    29401544 :     void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
     123    29401544 :       RV.push_back(Reg);
     124    58803088 :       if (TargetRegisterInfo::isPhysicalRegister(Reg))
     125    45697688 :         for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
     126    13712020 :           RV.push_back(*SubRegs);
     127    29401544 :     }
     128             : 
     129     3784190 :     struct BBInfo {
     130             :       // Is this MBB reachable from the MF entry point?
     131             :       bool reachable = false;
     132             : 
     133             :       // Vregs that must be live in because they are used without being
     134             :       // defined. Map value is the user.
     135             :       RegMap vregsLiveIn;
     136             : 
     137             :       // Regs killed in MBB. They may be defined again, and will then be in both
     138             :       // regsKilled and regsLiveOut.
     139             :       RegSet regsKilled;
     140             : 
     141             :       // Regs defined in MBB and live out. Note that vregs passing through may
     142             :       // be live out without being mentioned here.
     143             :       RegSet regsLiveOut;
     144             : 
     145             :       // Vregs that pass through MBB untouched. This set is disjoint from
     146             :       // regsKilled and regsLiveOut.
     147             :       RegSet vregsPassed;
     148             : 
     149             :       // Vregs that must pass through MBB because they are needed by a successor
     150             :       // block. This set is disjoint from regsLiveOut.
     151             :       RegSet vregsRequired;
     152             : 
     153             :       // Set versions of block's predecessor and successor lists.
     154             :       BlockSet Preds, Succs;
     155             : 
     156     3753150 :       BBInfo() = default;
     157             : 
     158             :       // Add register to vregsPassed if it belongs there. Return true if
     159             :       // anything changed.
     160    16024853 :       bool addPassed(unsigned Reg) {
     161    32049706 :         if (!TargetRegisterInfo::isVirtualRegister(Reg))
     162             :           return false;
     163             :         if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
     164             :           return false;
     165             :         return vregsPassed.insert(Reg).second;
     166             :       }
     167             : 
     168             :       // Same for a full set.
     169      732214 :       bool addPassed(const RegSet &RS) {
     170             :         bool changed = false;
     171    16757067 :         for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
     172    16024853 :           if (addPassed(*I))
     173             :             changed = true;
     174      732214 :         return changed;
     175             :       }
     176             : 
     177             :       // Add register to vregsRequired if it belongs there. Return true if
     178             :       // anything changed.
     179     1142498 :       bool addRequired(unsigned Reg) {
     180     2284996 :         if (!TargetRegisterInfo::isVirtualRegister(Reg))
     181             :           return false;
     182             :         if (regsLiveOut.count(Reg))
     183             :           return false;
     184             :         return vregsRequired.insert(Reg).second;
     185             :       }
     186             : 
     187             :       // Same for a full set.
     188      112581 :       bool addRequired(const RegSet &RS) {
     189             :         bool changed = false;
     190      910555 :         for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
     191      797974 :           if (addRequired(*I))
     192             :             changed = true;
     193      112581 :         return changed;
     194             :       }
     195             : 
     196             :       // Same for a full map.
     197      532153 :       bool addRequired(const RegMap &RM) {
     198             :         bool changed = false;
     199     1408830 :         for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
     200      344524 :           if (addRequired(I->first))
     201             :             changed = true;
     202      532153 :         return changed;
     203             :       }
     204             : 
     205             :       // Live-out registers are either in regsLiveOut or vregsPassed.
     206      163048 :       bool isLiveOut(unsigned Reg) const {
     207      163048 :         return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
     208             :       }
     209             :     };
     210             : 
     211             :     // Extra register info per MBB.
     212             :     DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
     213             : 
     214             :     bool isReserved(unsigned Reg) {
     215    23495494 :       return Reg < regsReserved.size() && regsReserved.test(Reg);
     216             :     }
     217             : 
     218      913539 :     bool isAllocatable(unsigned Reg) const {
     219     2739430 :       return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
     220      913539 :         !regsReserved.test(Reg);
     221             :     }
     222             : 
     223             :     // Analysis information if available
     224             :     LiveVariables *LiveVars;
     225             :     LiveIntervals *LiveInts;
     226             :     LiveStacks *LiveStks;
     227             :     SlotIndexes *Indexes;
     228             : 
     229             :     void visitMachineFunctionBefore();
     230             :     void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
     231             :     void visitMachineBundleBefore(const MachineInstr *MI);
     232             :     void visitMachineInstrBefore(const MachineInstr *MI);
     233             :     void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
     234             :     void visitMachineInstrAfter(const MachineInstr *MI);
     235             :     void visitMachineBundleAfter(const MachineInstr *MI);
     236             :     void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
     237             :     void visitMachineFunctionAfter();
     238             : 
     239             :     void report(const char *msg, const MachineFunction *MF);
     240             :     void report(const char *msg, const MachineBasicBlock *MBB);
     241             :     void report(const char *msg, const MachineInstr *MI);
     242             :     void report(const char *msg, const MachineOperand *MO, unsigned MONum,
     243             :                 LLT MOVRegType = LLT{});
     244             : 
     245             :     void report_context(const LiveInterval &LI) const;
     246             :     void report_context(const LiveRange &LR, unsigned VRegUnit,
     247             :                         LaneBitmask LaneMask) const;
     248             :     void report_context(const LiveRange::Segment &S) const;
     249             :     void report_context(const VNInfo &VNI) const;
     250             :     void report_context(SlotIndex Pos) const;
     251             :     void report_context_liverange(const LiveRange &LR) const;
     252             :     void report_context_lanemask(LaneBitmask LaneMask) const;
     253             :     void report_context_vreg(unsigned VReg) const;
     254             :     void report_context_vreg_regunit(unsigned VRegOrRegUnit) const;
     255             : 
     256             :     void verifyInlineAsm(const MachineInstr *MI);
     257             : 
     258             :     void checkLiveness(const MachineOperand *MO, unsigned MONum);
     259             :     void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
     260             :                             SlotIndex UseIdx, const LiveRange &LR, unsigned Reg,
     261             :                             LaneBitmask LaneMask = LaneBitmask::getNone());
     262             :     void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
     263             :                             SlotIndex DefIdx, const LiveRange &LR, unsigned Reg,
     264             :                             LaneBitmask LaneMask = LaneBitmask::getNone());
     265             : 
     266             :     void markReachable(const MachineBasicBlock *MBB);
     267             :     void calcRegsPassed();
     268             :     void checkPHIOps(const MachineBasicBlock &MBB);
     269             : 
     270             :     void calcRegsRequired();
     271             :     void verifyLiveVariables();
     272             :     void verifyLiveIntervals();
     273             :     void verifyLiveInterval(const LiveInterval&);
     274             :     void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
     275             :                               LaneBitmask);
     276             :     void verifyLiveRangeSegment(const LiveRange&,
     277             :                                 const LiveRange::const_iterator I, unsigned,
     278             :                                 LaneBitmask);
     279             :     void verifyLiveRange(const LiveRange&, unsigned,
     280             :                          LaneBitmask LaneMask = LaneBitmask::getNone());
     281             : 
     282             :     void verifyStackFrame();
     283             : 
     284             :     void verifySlotIndexes() const;
     285             :     void verifyProperties(const MachineFunction &MF);
     286             :   };
     287             : 
     288      457674 :   struct MachineVerifierPass : public MachineFunctionPass {
     289             :     static char ID; // Pass ID, replacement for typeid
     290             : 
     291             :     const std::string Banner;
     292             : 
     293      152825 :     MachineVerifierPass(std::string banner = std::string())
     294      152825 :       : MachineFunctionPass(ID), Banner(std::move(banner)) {
     295      152825 :         initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
     296      152825 :       }
     297             : 
     298      152825 :     void getAnalysisUsage(AnalysisUsage &AU) const override {
     299             :       AU.setPreservesAll();
     300      152825 :       MachineFunctionPass::getAnalysisUsage(AU);
     301      152825 :     }
     302             : 
     303     1497858 :     bool runOnMachineFunction(MachineFunction &MF) override {
     304     1497858 :       unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
     305     1497858 :       if (FoundErrors)
     306           1 :         report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
     307     1497857 :       return false;
     308             :     }
     309             :   };
     310             : 
     311             : } // end anonymous namespace
     312             : 
     313             : char MachineVerifierPass::ID = 0;
     314             : 
     315      453762 : INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
     316             :                 "Verify generated machine code", false, false)
     317             : 
     318      152824 : FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
     319      305648 :   return new MachineVerifierPass(Banner);
     320             : }
     321             : 
     322        4029 : bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
     323             :     const {
     324             :   MachineFunction &MF = const_cast<MachineFunction&>(*this);
     325        4029 :   unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
     326        4029 :   if (AbortOnErrors && FoundErrors)
     327          36 :     report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
     328        3993 :   return FoundErrors == 0;
     329             : }
     330             : 
     331             : void MachineVerifier::verifySlotIndexes() const {
     332             :   if (Indexes == nullptr)
     333             :     return;
     334             : 
     335             :   // Ensure the IdxMBB list is sorted by slot indexes.
     336             :   SlotIndex Last;
     337             :   for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
     338             :        E = Indexes->MBBIndexEnd(); I != E; ++I) {
     339             :     assert(!Last.isValid() || I->first > Last);
     340             :     Last = I->first;
     341             :   }
     342             : }
     343             : 
     344     1501887 : void MachineVerifier::verifyProperties(const MachineFunction &MF) {
     345             :   // If a pass has introduced virtual registers without clearing the
     346             :   // NoVRegs property (or set it without allocating the vregs)
     347             :   // then report an error.
     348             :   if (MF.getProperties().hasProperty(
     349     2254938 :           MachineFunctionProperties::Property::NoVRegs) &&
     350      753051 :       MRI->getNumVirtRegs())
     351           0 :     report("Function has NoVRegs property but there are VReg operands", &MF);
     352     1501887 : }
     353             : 
     354     1501887 : unsigned MachineVerifier::verify(MachineFunction &MF) {
     355     1501887 :   foundErrors = 0;
     356             : 
     357     1501887 :   this->MF = &MF;
     358     1501887 :   TM = &MF.getTarget();
     359     1501887 :   TII = MF.getSubtarget().getInstrInfo();
     360     1501887 :   TRI = MF.getSubtarget().getRegisterInfo();
     361     1501887 :   MRI = &MF.getRegInfo();
     362             : 
     363             :   const bool isFunctionFailedISel = MF.getProperties().hasProperty(
     364             :       MachineFunctionProperties::Property::FailedISel);
     365     1501887 :   isFunctionRegBankSelected =
     366     3003726 :       !isFunctionFailedISel &&
     367             :       MF.getProperties().hasProperty(
     368             :           MachineFunctionProperties::Property::RegBankSelected);
     369     3003726 :   isFunctionSelected = !isFunctionFailedISel &&
     370             :                        MF.getProperties().hasProperty(
     371             :                            MachineFunctionProperties::Property::Selected);
     372     1501887 :   LiveVars = nullptr;
     373     1501887 :   LiveInts = nullptr;
     374     1501887 :   LiveStks = nullptr;
     375     1501887 :   Indexes = nullptr;
     376     1501887 :   if (PASS) {
     377     1498038 :     LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
     378             :     // We don't want to verify LiveVariables if LiveIntervals is available.
     379     1498038 :     if (!LiveInts)
     380     1317231 :       LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
     381     1498038 :     LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
     382     1498038 :     Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
     383             :   }
     384             : 
     385             :   verifySlotIndexes();
     386             : 
     387     1501887 :   verifyProperties(MF);
     388             : 
     389     1501887 :   visitMachineFunctionBefore();
     390             :   for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
     391     3378462 :        MFI!=MFE; ++MFI) {
     392     1876575 :     visitMachineBasicBlockBefore(&*MFI);
     393             :     // Keep track of the current bundle header.
     394             :     const MachineInstr *CurBundle = nullptr;
     395             :     // Do we expect the next instruction to be part of the same bundle?
     396             :     bool InBundle = false;
     397             : 
     398             :     for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
     399    24188335 :            MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
     400    22311760 :       if (MBBI->getParent() != &*MFI) {
     401           0 :         report("Bad instruction parent pointer", &*MFI);
     402           0 :         errs() << "Instruction: " << *MBBI;
     403           0 :         continue;
     404             :       }
     405             : 
     406             :       // Check for consistent bundle flags.
     407    22336345 :       if (InBundle && !MBBI->isBundledWithPred())
     408           0 :         report("Missing BundledPred flag, "
     409             :                "BundledSucc was set on predecessor",
     410             :                &*MBBI);
     411    44598935 :       if (!InBundle && MBBI->isBundledWithPred())
     412           0 :         report("BundledPred flag is set, "
     413             :                "but BundledSucc not set on predecessor",
     414             :                &*MBBI);
     415             : 
     416             :       // Is this a bundle header?
     417    22311760 :       if (!MBBI->isInsideBundle()) {
     418    22287175 :         if (CurBundle)
     419    20426731 :           visitMachineBundleAfter(CurBundle);
     420             :         CurBundle = &*MBBI;
     421    22287175 :         visitMachineBundleBefore(CurBundle);
     422       24585 :       } else if (!CurBundle)
     423           0 :         report("No bundle header", &*MBBI);
     424    22311760 :       visitMachineInstrBefore(&*MBBI);
     425   112847543 :       for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
     426             :         const MachineInstr &MI = *MBBI;
     427    90535783 :         const MachineOperand &Op = MI.getOperand(I);
     428    90535783 :         if (Op.getParent() != &MI) {
     429             :           // Make sure to use correct addOperand / RemoveOperand / ChangeTo
     430             :           // functions when replacing operands of a MachineInstr.
     431           0 :           report("Instruction has operand with wrong parent set", &MI);
     432             :         }
     433             : 
     434    90535783 :         visitMachineOperand(&Op, I);
     435             :       }
     436             : 
     437             :       visitMachineInstrAfter(&*MBBI);
     438             : 
     439             :       // Was this the last bundled instruction?
     440             :       InBundle = MBBI->isBundledWithSucc();
     441             :     }
     442     1876575 :     if (CurBundle)
     443     1860444 :       visitMachineBundleAfter(CurBundle);
     444     1876575 :     if (InBundle)
     445           0 :       report("BundledSucc flag set on last instruction in block", &MFI->back());
     446     1876575 :     visitMachineBasicBlockAfter(&*MFI);
     447             :   }
     448     1501887 :   visitMachineFunctionAfter();
     449             : 
     450             :   // Clean up.
     451             :   regsLive.clear();
     452             :   regsDefined.clear();
     453             :   regsDead.clear();
     454             :   regsKilled.clear();
     455             :   regMasks.clear();
     456     1501887 :   MBBInfoMap.clear();
     457             : 
     458     1501887 :   return foundErrors;
     459             : }
     460             : 
     461          64 : void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
     462             :   assert(MF);
     463          64 :   errs() << '\n';
     464          64 :   if (!foundErrors++) {
     465          37 :     if (Banner)
     466           1 :       errs() << "# " << Banner << '\n';
     467          37 :     if (LiveInts != nullptr)
     468           0 :       LiveInts->print(errs());
     469             :     else
     470          37 :       MF->print(errs(), Indexes);
     471             :   }
     472          64 :   errs() << "*** Bad machine code: " << msg << " ***\n"
     473          64 :       << "- function:    " << MF->getName() << "\n";
     474          64 : }
     475             : 
     476          64 : void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
     477             :   assert(MBB);
     478          64 :   report(msg, MBB->getParent());
     479         128 :   errs() << "- basic block: " << printMBBReference(*MBB) << ' '
     480          64 :          << MBB->getName() << " (" << (const void *)MBB << ')';
     481          64 :   if (Indexes)
     482           0 :     errs() << " [" << Indexes->getMBBStartIdx(MBB)
     483           0 :         << ';' <<  Indexes->getMBBEndIdx(MBB) << ')';
     484          64 :   errs() << '\n';
     485          64 : }
     486             : 
     487          64 : void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
     488             :   assert(MI);
     489          64 :   report(msg, MI->getParent());
     490          64 :   errs() << "- instruction: ";
     491          64 :   if (Indexes && Indexes->hasIndex(*MI))
     492           0 :     errs() << Indexes->getInstructionIndex(*MI) << '\t';
     493          64 :   MI->print(errs(), /*SkipOpers=*/true);
     494          64 : }
     495             : 
     496          11 : void MachineVerifier::report(const char *msg, const MachineOperand *MO,
     497             :                              unsigned MONum, LLT MOVRegType) {
     498             :   assert(MO);
     499          11 :   report(msg, MO->getParent());
     500          22 :   errs() << "- operand " << MONum << ":   ";
     501          11 :   MO->print(errs(), MOVRegType, TRI);
     502          11 :   errs() << "\n";
     503          11 : }
     504             : 
     505           0 : void MachineVerifier::report_context(SlotIndex Pos) const {
     506           0 :   errs() << "- at:          " << Pos << '\n';
     507           0 : }
     508             : 
     509           0 : void MachineVerifier::report_context(const LiveInterval &LI) const {
     510           0 :   errs() << "- interval:    " << LI << '\n';
     511           0 : }
     512             : 
     513           0 : void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
     514             :                                      LaneBitmask LaneMask) const {
     515           0 :   report_context_liverange(LR);
     516           0 :   report_context_vreg_regunit(VRegUnit);
     517           0 :   if (LaneMask.any())
     518           0 :     report_context_lanemask(LaneMask);
     519           0 : }
     520             : 
     521           0 : void MachineVerifier::report_context(const LiveRange::Segment &S) const {
     522           0 :   errs() << "- segment:     " << S << '\n';
     523           0 : }
     524             : 
     525           0 : void MachineVerifier::report_context(const VNInfo &VNI) const {
     526           0 :   errs() << "- ValNo:       " << VNI.id << " (def " << VNI.def << ")\n";
     527           0 : }
     528             : 
     529           0 : void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
     530           0 :   errs() << "- liverange:   " << LR << '\n';
     531           0 : }
     532             : 
     533           0 : void MachineVerifier::report_context_vreg(unsigned VReg) const {
     534           0 :   errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
     535           0 : }
     536             : 
     537           0 : void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
     538           0 :   if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
     539           0 :     report_context_vreg(VRegOrUnit);
     540             :   } else {
     541           0 :     errs() << "- regunit:     " << printRegUnit(VRegOrUnit, TRI) << '\n';
     542             :   }
     543           0 : }
     544             : 
     545           0 : void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
     546           0 :   errs() << "- lanemask:    " << PrintLaneMask(LaneMask) << '\n';
     547           0 : }
     548             : 
     549     2033714 : void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
     550     2033714 :   BBInfo &MInfo = MBBInfoMap[MBB];
     551     2033714 :   if (!MInfo.reachable) {
     552     1875327 :     MInfo.reachable = true;
     553     1875327 :     for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
     554     2407174 :            SuE = MBB->succ_end(); SuI != SuE; ++SuI)
     555      531847 :       markReachable(*SuI);
     556             :   }
     557     2033714 : }
     558             : 
     559     1501887 : void MachineVerifier::visitMachineFunctionBefore() {
     560     1501887 :   lastIndex = SlotIndex();
     561     7509435 :   regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
     562     1502171 :                                            : TRI->getReservedRegs(*MF);
     563             : 
     564     3003774 :   if (!MF->empty())
     565     1501867 :     markReachable(&MF->front());
     566             : 
     567             :   // Build a set of the basic blocks in the function.
     568     1501887 :   FunctionBlocks.clear();
     569     4880349 :   for (const auto &MBB : *MF) {
     570     1876575 :     FunctionBlocks.insert(&MBB);
     571     3753150 :     BBInfo &MInfo = MBBInfoMap[&MBB];
     572             : 
     573     1876575 :     MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
     574     3753150 :     if (MInfo.Preds.size() != MBB.pred_size())
     575           0 :       report("MBB has duplicate entries in its predecessor list.", &MBB);
     576             : 
     577     1876575 :     MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
     578     3753150 :     if (MInfo.Succs.size() != MBB.succ_size())
     579           0 :       report("MBB has duplicate entries in its successor list.", &MBB);
     580             :   }
     581             : 
     582             :   // Check that the register use lists are sane.
     583     1501887 :   MRI->verifyUseLists();
     584             : 
     585     3003774 :   if (!MF->empty())
     586     1501867 :     verifyStackFrame();
     587     1501887 : }
     588             : 
     589             : // Does iterator point to a and b as the first two elements?
     590             : static bool matchPair(MachineBasicBlock::const_succ_iterator i,
     591             :                       const MachineBasicBlock *a, const MachineBasicBlock *b) {
     592      158141 :   if (*i == a)
     593       82082 :     return *++i == b;
     594       76059 :   if (*i == b)
     595       76059 :     return *++i == a;
     596             :   return false;
     597             : }
     598             : 
     599             : void
     600     1876575 : MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
     601     1876575 :   FirstTerminator = nullptr;
     602             : 
     603     1876575 :   if (!MF->getProperties().hasProperty(
     604     2564235 :       MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) {
     605             :     // If this block has allocatable physical registers live-in, check that
     606             :     // it is an entry block or landing pad.
     607     1601187 :     for (const auto &LI : MBB->liveins()) {
     608     1824444 :       if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
     609     1821810 :           MBB->getIterator() != MBB->getParent()->begin()) {
     610           0 :         report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
     611             :       }
     612             :     }
     613             :   }
     614             : 
     615             :   // Count the number of landing pad successors.
     616             :   SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
     617             :   for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
     618     2408728 :        E = MBB->succ_end(); I != E; ++I) {
     619      532153 :     if ((*I)->isEHPad())
     620        7375 :       LandingPadSuccs.insert(*I);
     621      532153 :     if (!FunctionBlocks.count(*I))
     622           0 :       report("MBB has successor that isn't part of the function.", MBB);
     623     1064306 :     if (!MBBInfoMap[*I].Preds.count(MBB)) {
     624           0 :       report("Inconsistent CFG", MBB);
     625           0 :       errs() << "MBB is not in the predecessor list of the successor "
     626           0 :              << printMBBReference(*(*I)) << ".\n";
     627             :     }
     628             :   }
     629             : 
     630             :   // Check the predecessor list.
     631             :   for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
     632     2408728 :        E = MBB->pred_end(); I != E; ++I) {
     633      532153 :     if (!FunctionBlocks.count(*I))
     634           0 :       report("MBB has predecessor that isn't part of the function.", MBB);
     635     1064306 :     if (!MBBInfoMap[*I].Succs.count(MBB)) {
     636           0 :       report("Inconsistent CFG", MBB);
     637           0 :       errs() << "MBB is not in the successor list of the predecessor "
     638           0 :              << printMBBReference(*(*I)) << ".\n";
     639             :     }
     640             :   }
     641             : 
     642     1876575 :   const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
     643     1876575 :   const BasicBlock *BB = MBB->getBasicBlock();
     644     1876575 :   const Function &F = MF->getFunction();
     645     1876810 :   if (LandingPadSuccs.size() > 1 &&
     646         235 :       !(AsmInfo &&
     647         235 :         AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
     648     1876575 :         BB && isa<SwitchInst>(BB->getTerminator())) &&
     649         235 :       !isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
     650           0 :     report("MBB has more than one landing pad successor", MBB);
     651             : 
     652             :   // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
     653     1876575 :   MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
     654             :   SmallVector<MachineOperand, 4> Cond;
     655     3753150 :   if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
     656     1876575 :                           Cond)) {
     657             :     // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
     658             :     // check whether its answers match up with reality.
     659      357907 :     if (!TBB && !FBB) {
     660             :       // Block falls through to its successor.
     661      157337 :       MachineFunction::const_iterator MBBI = MBB->getIterator();
     662             :       ++MBBI;
     663      314674 :       if (MBBI == MF->end()) {
     664             :         // It's possible that the block legitimately ends with a noreturn
     665             :         // call or an unreachable, in which case it won't actually fall
     666             :         // out the bottom of the function.
     667      250676 :       } else if (MBB->succ_size() == LandingPadSuccs.size()) {
     668             :         // It's possible that the block legitimately ends with a noreturn
     669             :         // call or an unreachable, in which case it won't actuall fall
     670             :         // out of the block.
     671      116012 :       } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
     672           0 :         report("MBB exits via unconditional fall-through but doesn't have "
     673             :                "exactly one CFG successor!", MBB);
     674      116012 :       } else if (!MBB->isSuccessor(&*MBBI)) {
     675           0 :         report("MBB exits via unconditional fall-through but its successor "
     676             :                "differs from its CFG successor!", MBB);
     677             :       }
     678      298561 :       if (!MBB->empty() && MBB->back().isBarrier() &&
     679          36 :           !TII->isPredicated(MBB->back())) {
     680           0 :         report("MBB exits via unconditional fall-through but ends with a "
     681             :                "barrier instruction!", MBB);
     682             :       }
     683      157337 :       if (!Cond.empty()) {
     684           0 :         report("MBB exits via unconditional fall-through but has a condition!",
     685             :                MBB);
     686             :       }
     687      200570 :     } else if (TBB && !FBB && Cond.empty()) {
     688             :       // Block unconditionally branches somewhere.
     689             :       // If the block has exactly one successor, that happens to be a
     690             :       // landingpad, accept it as valid control flow.
     691       84502 :       if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
     692           0 :           (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
     693       42251 :            *MBB->succ_begin() != *LandingPadSuccs.begin())) {
     694           0 :         report("MBB exits via unconditional branch but doesn't have "
     695             :                "exactly one CFG successor!", MBB);
     696       42251 :       } else if (!MBB->isSuccessor(TBB)) {
     697           0 :         report("MBB exits via unconditional branch but the CFG "
     698             :                "successor doesn't match the actual successor!", MBB);
     699             :       }
     700       42251 :       if (MBB->empty()) {
     701           0 :         report("MBB exits via unconditional branch but doesn't contain "
     702             :                "any instructions!", MBB);
     703       42251 :       } else if (!MBB->back().isBarrier()) {
     704           0 :         report("MBB exits via unconditional branch but doesn't end with a "
     705             :                "barrier instruction!", MBB);
     706       42251 :       } else if (!MBB->back().isTerminator()) {
     707           0 :         report("MBB exits via unconditional branch but the branch isn't a "
     708             :                "terminator instruction!", MBB);
     709             :       }
     710      316638 :     } else if (TBB && !FBB && !Cond.empty()) {
     711             :       // Block conditionally branches somewhere, otherwise falls through.
     712       72784 :       MachineFunction::const_iterator MBBI = MBB->getIterator();
     713             :       ++MBBI;
     714      145568 :       if (MBBI == MF->end()) {
     715           0 :         report("MBB conditionally falls through out of function!", MBB);
     716       72784 :       } else if (MBB->succ_size() == 1) {
     717             :         // A conditional branch with only one successor is weird, but allowed.
     718          44 :         if (&*MBBI != TBB)
     719           0 :           report("MBB exits via conditional branch/fall-through but only has "
     720             :                  "one CFG successor!", MBB);
     721          44 :         else if (TBB != *MBB->succ_begin())
     722           0 :           report("MBB exits via conditional branch/fall-through but the CFG "
     723             :                  "successor don't match the actual successor!", MBB);
     724       72740 :       } else if (MBB->succ_size() != 2) {
     725           0 :         report("MBB exits via conditional branch/fall-through but doesn't have "
     726             :                "exactly two CFG successors!", MBB);
     727       72740 :       } else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
     728           0 :         report("MBB exits via conditional branch/fall-through but the CFG "
     729             :                "successors don't match the actual successors!", MBB);
     730             :       }
     731       72784 :       if (MBB->empty()) {
     732           0 :         report("MBB exits via conditional branch/fall-through but doesn't "
     733             :                "contain any instructions!", MBB);
     734       72784 :       } else if (MBB->back().isBarrier()) {
     735           0 :         report("MBB exits via conditional branch/fall-through but ends with a "
     736             :                "barrier instruction!", MBB);
     737       72784 :       } else if (!MBB->back().isTerminator()) {
     738           0 :         report("MBB exits via conditional branch/fall-through but the branch "
     739             :                "isn't a terminator instruction!", MBB);
     740             :       }
     741      171070 :     } else if (TBB && FBB) {
     742             :       // Block conditionally branches somewhere, otherwise branches
     743             :       // somewhere else.
     744       85535 :       if (MBB->succ_size() == 1) {
     745             :         // A conditional branch with only one successor is weird, but allowed.
     746         134 :         if (FBB != TBB)
     747           0 :           report("MBB exits via conditional branch/branch through but only has "
     748             :                  "one CFG successor!", MBB);
     749         134 :         else if (TBB != *MBB->succ_begin())
     750           0 :           report("MBB exits via conditional branch/branch through but the CFG "
     751             :                  "successor don't match the actual successor!", MBB);
     752       85401 :       } else if (MBB->succ_size() != 2) {
     753           0 :         report("MBB exits via conditional branch/branch but doesn't have "
     754             :                "exactly two CFG successors!", MBB);
     755       85401 :       } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
     756           0 :         report("MBB exits via conditional branch/branch but the CFG "
     757             :                "successors don't match the actual successors!", MBB);
     758             :       }
     759       85535 :       if (MBB->empty()) {
     760           0 :         report("MBB exits via conditional branch/branch but doesn't "
     761             :                "contain any instructions!", MBB);
     762       85535 :       } else if (!MBB->back().isBarrier()) {
     763           0 :         report("MBB exits via conditional branch/branch but doesn't end with a "
     764             :                "barrier instruction!", MBB);
     765       85535 :       } else if (!MBB->back().isTerminator()) {
     766           0 :         report("MBB exits via conditional branch/branch but the branch "
     767             :                "isn't a terminator instruction!", MBB);
     768             :       }
     769       85535 :       if (Cond.empty()) {
     770           0 :         report("MBB exits via conditinal branch/branch but there's no "
     771             :                "condition!", MBB);
     772             :       }
     773             :     } else {
     774           0 :       report("AnalyzeBranch returned invalid data!", MBB);
     775             :     }
     776             :   }
     777             : 
     778             :   regsLive.clear();
     779     3753150 :   if (MRI->tracksLiveness()) {
     780     4986948 :     for (const auto &LI : MBB->liveins()) {
     781     3136254 :       if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
     782           0 :         report("MBB live-in list contains non-physical register", MBB);
     783           0 :         continue;
     784             :       }
     785     3136254 :       for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
     786    10374386 :            SubRegs.isValid(); ++SubRegs)
     787    14476264 :         regsLive.insert(*SubRegs);
     788             :     }
     789             :   }
     790             : 
     791     1876575 :   const MachineFrameInfo &MFI = MF->getFrameInfo();
     792     1876575 :   BitVector PR = MFI.getPristineRegs(*MF);
     793    16041363 :   for (unsigned I : PR.set_bits()) {
     794    14164788 :     for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
     795    37564118 :          SubRegs.isValid(); ++SubRegs)
     796    46798660 :       regsLive.insert(*SubRegs);
     797             :   }
     798             : 
     799             :   regsKilled.clear();
     800             :   regsDefined.clear();
     801             : 
     802     1876575 :   if (Indexes)
     803      270433 :     lastIndex = Indexes->getMBBStartIdx(MBB);
     804     1876575 : }
     805             : 
     806             : // This function gets called for all bundle headers, including normal
     807             : // stand-alone unbundled instructions.
     808    22287175 : void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
     809    22287175 :   if (Indexes && Indexes->hasIndex(*MI)) {
     810     2962425 :     SlotIndex idx = Indexes->getInstructionIndex(*MI);
     811     2962425 :     if (!(idx > lastIndex)) {
     812           0 :       report("Instruction index out of order", MI);
     813           0 :       errs() << "Last instruction was at " << lastIndex << '\n';
     814             :     }
     815     2962425 :     lastIndex = idx;
     816             :   }
     817             : 
     818             :   // Ensure non-terminators don't follow terminators.
     819             :   // Ignore predicated terminators formed by if conversion.
     820             :   // FIXME: If conversion shouldn't need to violate this rule.
     821    22287175 :   if (MI->isTerminator() && !TII->isPredicated(*MI)) {
     822     1824665 :     if (!FirstTerminator)
     823     1729150 :       FirstTerminator = MI;
     824    20462510 :   } else if (FirstTerminator) {
     825           0 :     report("Non-terminator instruction after the first terminator", MI);
     826           0 :     errs() << "First terminator was:\t" << *FirstTerminator;
     827             :   }
     828    22287175 : }
     829             : 
     830             : // The operands on an INLINEASM instruction must follow a template.
     831             : // Verify that the flag operands make sense.
     832      119344 : void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
     833             :   // The first two operands on INLINEASM are the asm string and global flags.
     834      119344 :   if (MI->getNumOperands() < 2) {
     835           0 :     report("Too few operands on inline asm", MI);
     836           0 :     return;
     837             :   }
     838      238688 :   if (!MI->getOperand(0).isSymbol())
     839           0 :     report("Asm string must be an external symbol", MI);
     840      238688 :   if (!MI->getOperand(1).isImm())
     841           0 :     report("Asm flags must be an immediate", MI);
     842             :   // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
     843             :   // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
     844             :   // and Extra_IsConvergent = 32.
     845      119344 :   if (!isUInt<6>(MI->getOperand(1).getImm()))
     846           0 :     report("Unknown asm flags", &MI->getOperand(1), 1);
     847             : 
     848             :   static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
     849             : 
     850             :   unsigned OpNo = InlineAsm::MIOp_FirstOperand;
     851             :   unsigned NumOps;
     852      565463 :   for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
     853      446722 :     const MachineOperand &MO = MI->getOperand(OpNo);
     854             :     // There may be implicit ops after the fixed operands.
     855      446722 :     if (!MO.isImm())
     856             :       break;
     857      892238 :     NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
     858             :   }
     859             : 
     860      119344 :   if (OpNo > MI->getNumOperands())
     861           0 :     report("Missing operands in last group", MI);
     862             : 
     863             :   // An optional MDNode follows the groups.
     864      119947 :   if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
     865         246 :     ++OpNo;
     866             : 
     867             :   // All trailing operands must be implicit registers.
     868      120330 :   for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
     869         493 :     const MachineOperand &MO = MI->getOperand(OpNo);
     870         986 :     if (!MO.isReg() || !MO.isImplicit())
     871           0 :       report("Expected implicit register after groups", &MO, OpNo);
     872             :   }
     873             : }
     874             : 
     875    22311760 : void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     876    22311760 :   const MCInstrDesc &MCID = MI->getDesc();
     877    44623520 :   if (MI->getNumOperands() < MCID.getNumOperands()) {
     878          10 :     report("Too few operands", MI);
     879          20 :     errs() << MCID.getNumOperands() << " operands expected, but "
     880          20 :            << MI->getNumOperands() << " given.\n";
     881             :   }
     882             : 
     883      161158 :   if (MI->isPHI() && MF->getProperties().hasProperty(
     884             :                          MachineFunctionProperties::Property::NoPHIs))
     885           0 :     report("Found PHI instruction with NoPHIs property set", MI);
     886             : 
     887             :   // Check the tied operands.
     888    22311760 :   if (MI->isInlineAsm())
     889      119344 :     verifyInlineAsm(MI);
     890             : 
     891             :   // Check the MachineMemOperands for basic consistency.
     892    27249066 :   for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
     893    22311760 :                                   E = MI->memoperands_end();
     894    27249066 :        I != E; ++I) {
     895     9874612 :     if ((*I)->isLoad() && !MI->mayLoad())
     896           0 :       report("Missing mayLoad flag", MI);
     897     9874612 :     if ((*I)->isStore() && !MI->mayStore())
     898           0 :       report("Missing mayStore flag", MI);
     899             :   }
     900             : 
     901             :   // Debug values must not have a slot index.
     902             :   // Other instructions must have one, unless they are inside a bundle.
     903    22311760 :   if (LiveInts) {
     904     2558303 :     bool mapped = !LiveInts->isNotInMIMap(*MI);
     905             :     if (MI->isDebugInstr()) {
     906         122 :       if (mapped)
     907           0 :         report("Debug instruction has a slot index", MI);
     908     2558181 :     } else if (MI->isInsideBundle()) {
     909         277 :       if (mapped)
     910           0 :         report("Instruction inside bundle has a slot index", MI);
     911             :     } else {
     912     2557904 :       if (!mapped)
     913           0 :         report("Missing slot index", MI);
     914             :     }
     915             :   }
     916             : 
     917    44623520 :   if (isPreISelGenericOpcode(MCID.getOpcode())) {
     918        9858 :     if (isFunctionSelected)
     919           1 :       report("Unexpected generic instruction in a Selected function", MI);
     920             : 
     921             :     // Check types.
     922             :     SmallVector<LLT, 4> Types;
     923       90345 :     for (unsigned I = 0; I < MCID.getNumOperands(); ++I) {
     924       47086 :       if (!MCID.OpInfo[I].isGenericType())
     925             :         continue;
     926             :       // Generic instructions specify type equality constraints between some of
     927             :       // their operands. Make sure these are consistent.
     928       20589 :       size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
     929       41178 :       Types.resize(std::max(TypeIdx + 1, Types.size()));
     930             : 
     931       20589 :       const MachineOperand *MO = &MI->getOperand(I);
     932       20589 :       LLT OpTy = MRI->getType(MO->getReg());
     933             :       // Don't report a type mismatch if there is no actual mismatch, only a
     934             :       // type missing, to reduce noise:
     935       20589 :       if (OpTy.isValid()) {
     936             :         // Only the first valid type for a type index will be printed: don't
     937             :         // overwrite it later so it's always clear which type was expected:
     938       20584 :         if (!Types[TypeIdx].isValid())
     939       15356 :           Types[TypeIdx] = OpTy;
     940             :         else if (Types[TypeIdx] != OpTy)
     941           1 :           report("Type mismatch in generic instruction", MO, I, OpTy);
     942             :       } else {
     943             :         // Generic instructions must have types attached to their operands.
     944           5 :         report("Generic instruction is missing a virtual register type", MO, I);
     945             :       }
     946             :     }
     947             : 
     948             :     // Generic opcodes must not have physical register operands.
     949       59992 :     for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
     950       25067 :       const MachineOperand *MO = &MI->getOperand(I);
     951       47024 :       if (MO->isReg() && TargetRegisterInfo::isPhysicalRegister(MO->getReg()))
     952           0 :         report("Generic instruction cannot have physical register", MO, I);
     953             :     }
     954             :   }
     955             : 
     956    22311760 :   StringRef ErrorInfo;
     957    22311760 :   if (!TII->verifyInstruction(*MI, ErrorInfo))
     958          25 :     report(ErrorInfo.data(), MI);
     959             : 
     960             :   // Verify properties of various specific instruction types
     961    44623520 :   switch(MI->getOpcode()) {
     962             :   default:
     963             :     break;
     964        1307 :   case TargetOpcode::G_LOAD:
     965             :   case TargetOpcode::G_STORE:
     966             :     // Generic loads and stores must have a single MachineMemOperand
     967             :     // describing that access.
     968        1307 :     if (!MI->hasOneMemOperand())
     969           0 :       report("Generic instruction accessing memory must have one mem operand",
     970             :              MI);
     971             :     break;
     972          77 :   case TargetOpcode::G_PHI: {
     973         154 :     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     974         154 :     if (!DstTy.isValid() ||
     975         154 :         !std::all_of(MI->operands_begin() + 1, MI->operands_end(),
     976         619 :                      [this, &DstTy](const MachineOperand &MO) {
     977         309 :                        if (!MO.isReg())
     978             :                          return true;
     979         155 :                        LLT Ty = MRI->getType(MO.getReg());
     980         155 :                        if (!Ty.isValid() || (Ty != DstTy))
     981             :                          return false;
     982             :                        return true;
     983             :                      }))
     984           1 :       report("Generic Instruction G_PHI has operands with incompatible/missing "
     985             :              "types",
     986             :              MI);
     987             :     break;
     988             :   }
     989        2037 :   case TargetOpcode::G_SEXT:
     990             :   case TargetOpcode::G_ZEXT:
     991             :   case TargetOpcode::G_ANYEXT:
     992             :   case TargetOpcode::G_TRUNC:
     993             :   case TargetOpcode::G_FPEXT:
     994             :   case TargetOpcode::G_FPTRUNC: {
     995             :     // Number of operands and presense of types is already checked (and
     996             :     // reported in case of any issues), so no need to report them again. As
     997             :     // we're trying to report as many issues as possible at once, however, the
     998             :     // instructions aren't guaranteed to have the right number of operands or
     999             :     // types attached to them at this point
    1000             :     assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
    1001        4074 :     if (MI->getNumOperands() < MCID.getNumOperands())
    1002             :       break;
    1003        4074 :     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
    1004        4074 :     LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
    1005        4074 :     if (!DstTy.isValid() || !SrcTy.isValid())
    1006             :       break;
    1007             : 
    1008        1916 :     LLT DstElTy = DstTy.isVector() ? DstTy.getElementType() : DstTy;
    1009        1916 :     LLT SrcElTy = SrcTy.isVector() ? SrcTy.getElementType() : SrcTy;
    1010             :     if (DstElTy.isPointer() || SrcElTy.isPointer())
    1011           3 :       report("Generic extend/truncate can not operate on pointers", MI);
    1012             : 
    1013        2037 :     if (DstTy.isVector() != SrcTy.isVector()) {
    1014           2 :       report("Generic extend/truncate must be all-vector or all-scalar", MI);
    1015             :       // Generally we try to report as many issues as possible at once, but in
    1016             :       // this case it's not clear what should we be comparing the size of the
    1017             :       // scalar with: the size of the whole vector or its lane. Instead of
    1018             :       // making an arbitrary choice and emitting not so helpful message, let's
    1019             :       // avoid the extra noise and stop here.
    1020           2 :       break;
    1021             :     }
    1022         120 :     if (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements())
    1023           2 :       report("Generic vector extend/truncate must preserve number of lanes",
    1024             :              MI);
    1025        2035 :     unsigned DstSize = DstElTy.getSizeInBits();
    1026        2035 :     unsigned SrcSize = SrcElTy.getSizeInBits();
    1027        4070 :     switch (MI->getOpcode()) {
    1028        1083 :     default:
    1029        1083 :       if (DstSize <= SrcSize)
    1030           2 :         report("Generic extend has destination type no larger than source", MI);
    1031             :       break;
    1032         952 :     case TargetOpcode::G_TRUNC:
    1033             :     case TargetOpcode::G_FPTRUNC:
    1034         952 :       if (DstSize >= SrcSize)
    1035           1 :         report("Generic truncate has destination type no smaller than source",
    1036             :                MI);
    1037             :       break;
    1038             :     }
    1039             :     break;
    1040             :   }
    1041     4592830 :   case TargetOpcode::COPY: {
    1042     4592830 :     if (foundErrors)
    1043             :       break;
    1044     4592794 :     const MachineOperand &DstOp = MI->getOperand(0);
    1045             :     const MachineOperand &SrcOp = MI->getOperand(1);
    1046     9185588 :     LLT DstTy = MRI->getType(DstOp.getReg());
    1047     9185588 :     LLT SrcTy = MRI->getType(SrcOp.getReg());
    1048     4596275 :     if (SrcTy.isValid() && DstTy.isValid()) {
    1049             :       // If both types are valid, check that the types are the same.
    1050             :       if (SrcTy != DstTy) {
    1051           1 :         report("Copy Instruction is illegal with mismatching types", MI);
    1052           3 :         errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
    1053             :       }
    1054             :     }
    1055     9182107 :     if (SrcTy.isValid() || DstTy.isValid()) {
    1056             :       // If one of them have valid types, let's just check they have the same
    1057             :       // size.
    1058        9931 :       unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
    1059        9931 :       unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);
    1060             :       assert(SrcSize && "Expecting size here");
    1061             :       assert(DstSize && "Expecting size here");
    1062        9931 :       if (SrcSize != DstSize)
    1063           4 :         if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
    1064           2 :           report("Copy Instruction is illegal with mismatching sizes", MI);
    1065           4 :           errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
    1066           2 :                  << "\n";
    1067             :         }
    1068             :     }
    1069             :     break;
    1070             :   }
    1071        2923 :   case TargetOpcode::STATEPOINT:
    1072        5846 :     if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
    1073        5846 :         !MI->getOperand(StatepointOpers::NBytesPos).isImm() ||
    1074             :         !MI->getOperand(StatepointOpers::NCallArgsPos).isImm())
    1075           0 :       report("meta operands to STATEPOINT not constant!", MI);
    1076             :     break;
    1077             : 
    1078             :     auto VerifyStackMapConstant = [&](unsigned Offset) {
    1079             :       if (!MI->getOperand(Offset).isImm() ||
    1080             :           MI->getOperand(Offset).getImm() != StackMaps::ConstantOp || 
    1081             :           !MI->getOperand(Offset + 1).isImm()) 
    1082             :         report("stack map constant to STATEPOINT not well formed!", MI);
    1083             :     };
    1084             :     const unsigned VarStart = StatepointOpers(MI).getVarIdx();
    1085             :     VerifyStackMapConstant(VarStart + StatepointOpers::CCOffset);
    1086             :     VerifyStackMapConstant(VarStart + StatepointOpers::FlagsOffset);
    1087             :     VerifyStackMapConstant(VarStart + StatepointOpers::NumDeoptOperandsOffset);
    1088             : 
    1089             :     // TODO: verify we have properly encoded deopt arguments
    1090             :   };
    1091    22311760 : }
    1092             : 
    1093             : void
    1094    90535783 : MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
    1095    90535783 :   const MachineInstr *MI = MO->getParent();
    1096    90535783 :   const MCInstrDesc &MCID = MI->getDesc();
    1097    90535783 :   unsigned NumDefs = MCID.getNumDefs();
    1098    90535783 :   if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
    1099          39 :     NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
    1100             : 
    1101             :   // The first MCID.NumDefs operands must be explicit register defines
    1102    90535783 :   if (MONum < NumDefs) {
    1103    17842011 :     const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
    1104    17842011 :     if (!MO->isReg())
    1105           0 :       report("Explicit definition must be a register", MO, MONum);
    1106    17842011 :     else if (!MO->isDef() && !MCOI.isOptionalDef())
    1107           0 :       report("Explicit definition marked as use", MO, MONum);
    1108    17842011 :     else if (MO->isImplicit())
    1109           0 :       report("Explicit definition marked as implicit", MO, MONum);
    1110   145387544 :   } else if (MONum < MCID.getNumOperands()) {
    1111    54934249 :     const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
    1112             :     // Don't check if it's the last operand in a variadic instruction. See,
    1113             :     // e.g., LDM_RET in the arm back end.
    1114    80521405 :     if (MO->isReg() &&
    1115     1624464 :         !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
    1116    24840575 :       if (MO->isDef() && !MCOI.isOptionalDef())
    1117           0 :         report("Explicit operand marked as def", MO, MONum);
    1118    24840575 :       if (MO->isImplicit())
    1119           0 :         report("Explicit operand marked as implicit", MO, MONum);
    1120             :     }
    1121             : 
    1122    54934249 :     int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
    1123             :     if (TiedTo != -1) {
    1124      649324 :       if (!MO->isReg())
    1125           0 :         report("Tied use must be a register", MO, MONum);
    1126      649324 :       else if (!MO->isTied())
    1127           0 :         report("Operand should be tied", MO, MONum);
    1128      649324 :       else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
    1129           0 :         report("Tied def doesn't match MCInstrDesc", MO, MONum);
    1130     1298648 :       else if (TargetRegisterInfo::isPhysicalRegister(MO->getReg())) {
    1131      369897 :         const MachineOperand &MOTied = MI->getOperand(TiedTo);
    1132      369897 :         if (!MOTied.isReg())
    1133           0 :           report("Tied counterpart must be a register", &MOTied, TiedTo);
    1134      739794 :         else if (TargetRegisterInfo::isPhysicalRegister(MOTied.getReg()) &&
    1135             :                  MO->getReg() != MOTied.getReg())
    1136           1 :           report("Tied physical registers must match.", &MOTied, TiedTo);
    1137             :       }
    1138    79222757 :     } else if (MO->isReg() && MO->isTied())
    1139           0 :       report("Explicit operand should not be tied", MO, MONum);
    1140             :   } else {
    1141             :     // ARM adds %reg0 operands to indicate predicates. We'll allow that.
    1142    34231985 :     if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
    1143           0 :       report("Extra explicit operand on non-variadic instruction", MO, MONum);
    1144             :   }
    1145             : 
    1146    90535783 :   switch (MO->getType()) {
    1147    57968729 :   case MachineOperand::MO_Register: {
    1148    57968729 :     const unsigned Reg = MO->getReg();
    1149    57968729 :     if (!Reg)
    1150     1666882 :       return;
    1151   168144356 :     if (MRI->tracksLiveness() && !MI->isDebugValue())
    1152    55539437 :       checkLiveness(MO, MONum);
    1153             : 
    1154             :     // Verify the consistency of tied operands.
    1155    56301849 :     if (MO->isTied()) {
    1156     1311760 :       unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
    1157     1311760 :       const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
    1158     1311760 :       if (!OtherMO.isReg())
    1159           0 :         report("Must be tied to a register", MO, MONum);
    1160     1311760 :       if (!OtherMO.isTied())
    1161           0 :         report("Missing tie flags on tied operand", MO, MONum);
    1162     1311760 :       if (MI->findTiedOperandIdx(OtherIdx) != MONum)
    1163           0 :         report("Inconsistent tie links", MO, MONum);
    1164     2623520 :       if (MONum < MCID.getNumDefs()) {
    1165     1300568 :         if (OtherIdx < MCID.getNumOperands()) {
    1166             :           if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
    1167           0 :             report("Explicit def tied to explicit use without tie constraint",
    1168             :                    MO, MONum);
    1169             :         } else {
    1170         960 :           if (!OtherMO.isImplicit())
    1171           0 :             report("Explicit def should be tied to implicit use", MO, MONum);
    1172             :         }
    1173             :       }
    1174             :     }
    1175             : 
    1176             :     // Verify two-address constraints after leaving SSA form.
    1177             :     unsigned DefIdx;
    1178   107221087 :     if (!MRI->isSSA() && MO->isUse() &&
    1179    76604289 :         MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
    1180      858544 :         Reg != MI->getOperand(DefIdx).getReg())
    1181           0 :       report("Two-address instruction operands must be identical", MO, MONum);
    1182             : 
    1183             :     // Check register classes.
    1184             :     unsigned SubIdx = MO->getSubReg();
    1185             : 
    1186    56301849 :     if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
    1187    33293724 :       if (SubIdx) {
    1188           0 :         report("Illegal subregister index for physical register", MO, MONum);
    1189           0 :         return;
    1190             :       }
    1191    66587448 :       if (MONum < MCID.getNumOperands()) {
    1192    20348237 :         if (const TargetRegisterClass *DRC =
    1193    20348237 :               TII->getRegClass(MCID, MONum, TRI, *MF)) {
    1194    34492134 :           if (!DRC->contains(Reg)) {
    1195           0 :             report("Illegal physical register for instruction", MO, MONum);
    1196           0 :             errs() << printReg(Reg, TRI) << " is not a "
    1197           0 :                    << TRI->getRegClassName(DRC) << " register.\n";
    1198             :           }
    1199             :         }
    1200             :       }
    1201    33293724 :       if (MO->isRenamable()) {
    1202    23198196 :         if (MRI->isReserved(Reg)) {
    1203           0 :           report("isRenamable set on reserved register", MO, MONum);
    1204           0 :           return;
    1205             :         }
    1206             :       }
    1207             :     } else {
    1208             :       // Virtual register.
    1209    23008125 :       const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
    1210    22986306 :       if (!RC) {
    1211             :         // This is a generic virtual register.
    1212             : 
    1213             :         // If we're post-Select, we can't have gvregs anymore.
    1214       32666 :         if (isFunctionSelected) {
    1215           1 :           report("Generic virtual register invalid in a Selected function",
    1216             :                  MO, MONum);
    1217           3 :           return;
    1218             :         }
    1219             : 
    1220             :         // The gvreg must have a type and it must not have a SubIdx.
    1221       32665 :         LLT Ty = MRI->getType(Reg);
    1222       32665 :         if (!Ty.isValid()) {
    1223           0 :           report("Generic virtual register must have a valid type", MO,
    1224             :                  MONum);
    1225           0 :           return;
    1226             :         }
    1227             : 
    1228             :         const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
    1229             : 
    1230             :         // If we're post-RegBankSelect, the gvreg must have a bank.
    1231       21818 :         if (!RegBank && isFunctionRegBankSelected) {
    1232           1 :           report("Generic virtual register must have a bank in a "
    1233             :                  "RegBankSelected function",
    1234             :                  MO, MONum);
    1235           1 :           return;
    1236             :         }
    1237             : 
    1238             :         // Make sure the register fits into its register bank if any.
    1239       48605 :         if (RegBank && Ty.isValid() &&
    1240       15941 :             RegBank->getSize() < Ty.getSizeInBits()) {
    1241           0 :           report("Register bank is too small for virtual register", MO,
    1242             :                  MONum);
    1243           0 :           errs() << "Register bank " << RegBank->getName() << " too small("
    1244           0 :                  << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
    1245           0 :                  << "-bits\n";
    1246           0 :           return;
    1247             :         }
    1248       32664 :         if (SubIdx)  {
    1249           0 :           report("Generic virtual register does not subregister index", MO,
    1250             :                  MONum);
    1251           0 :           return;
    1252             :         }
    1253             : 
    1254             :         // If this is a target specific instruction and this operand
    1255             :         // has register class constraint, the virtual register must
    1256             :         // comply to it.
    1257       43387 :         if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
    1258       43037 :             MONum < MCID.getNumOperands() &&
    1259       10373 :             TII->getRegClass(MCID, MONum, TRI, *MF)) {
    1260           0 :           report("Virtual register does not match instruction constraint", MO,
    1261             :                  MONum);
    1262           0 :           errs() << "Expect register class "
    1263           0 :                  << TRI->getRegClassName(
    1264           0 :                         TII->getRegClass(MCID, MONum, TRI, *MF))
    1265           0 :                  << " but got nothing\n";
    1266           0 :           return;
    1267             :         }
    1268             : 
    1269       32664 :         break;
    1270             :       }
    1271    22975459 :       if (SubIdx) {
    1272             :         const TargetRegisterClass *SRC =
    1273     2298594 :           TRI->getSubClassWithSubReg(RC, SubIdx);
    1274     2298594 :         if (!SRC) {
    1275           0 :           report("Invalid subregister index for virtual register", MO, MONum);
    1276           0 :           errs() << "Register class " << TRI->getRegClassName(RC)
    1277           0 :               << " does not support subreg index " << SubIdx << "\n";
    1278           0 :           return;
    1279             :         }
    1280     2298594 :         if (RC != SRC) {
    1281           0 :           report("Invalid register class for subregister index", MO, MONum);
    1282           0 :           errs() << "Register class " << TRI->getRegClassName(RC)
    1283           0 :               << " does not fully support subreg index " << SubIdx << "\n";
    1284           0 :           return;
    1285             :         }
    1286             :       }
    1287    45950918 :       if (MONum < MCID.getNumOperands()) {
    1288    21384903 :         if (const TargetRegisterClass *DRC =
    1289    21384903 :               TII->getRegClass(MCID, MONum, TRI, *MF)) {
    1290    13287458 :           if (SubIdx) {
    1291             :             const TargetRegisterClass *SuperRC =
    1292      958280 :                 TRI->getLargestLegalSuperClass(RC, *MF);
    1293      958280 :             if (!SuperRC) {
    1294           0 :               report("No largest legal super class exists.", MO, MONum);
    1295           0 :               return;
    1296             :             }
    1297      958280 :             DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
    1298      958280 :             if (!DRC) {
    1299           0 :               report("No matching super-reg register class.", MO, MONum);
    1300           0 :               return;
    1301             :             }
    1302             :           }
    1303    13287458 :           if (!RC->hasSuperClassEq(DRC)) {
    1304           0 :             report("Illegal virtual register for instruction", MO, MONum);
    1305           0 :             errs() << "Expected a " << TRI->getRegClassName(DRC)
    1306           0 :                 << " register, but got a " << TRI->getRegClassName(RC)
    1307           0 :                 << " register\n";
    1308             :           }
    1309             :         }
    1310             :       }
    1311             :     }
    1312             :     break;
    1313             :   }
    1314             : 
    1315      204818 :   case MachineOperand::MO_RegisterMask:
    1316      204818 :     regMasks.push_back(MO->getRegMask());
    1317      204818 :     break;
    1318             : 
    1319             :   case MachineOperand::MO_MachineBasicBlock:
    1320      163056 :     if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
    1321           0 :       report("PHI operand is not in the CFG", MO, MONum);
    1322             :     break;
    1323             : 
    1324      400805 :   case MachineOperand::MO_FrameIndex:
    1325      479379 :     if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
    1326      413263 :         LiveInts && !LiveInts->isNotInMIMap(*MI)) {
    1327        4882 :       int FI = MO->getIndex();
    1328        4882 :       LiveInterval &LI = LiveStks->getInterval(FI);
    1329        4882 :       SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
    1330             : 
    1331        4882 :       bool stores = MI->mayStore();
    1332        4882 :       bool loads = MI->mayLoad();
    1333             :       // For a memory-to-memory move, we need to check if the frame
    1334             :       // index is used for storing or loading, by inspecting the
    1335             :       // memory operands.
    1336        4882 :       if (stores && loads) {
    1337          65 :         for (auto *MMO : MI->memoperands()) {
    1338             :           const PseudoSourceValue *PSV = MMO->getPseudoValue();
    1339          26 :           if (PSV == nullptr) continue;
    1340             :           const FixedStackPseudoSourceValue *Value =
    1341             :             dyn_cast<FixedStackPseudoSourceValue>(PSV);
    1342           0 :           if (Value == nullptr) continue;
    1343          26 :           if (Value->getFrameIndex() != FI) continue;
    1344             : 
    1345          46 :           if (MMO->isStore())
    1346             :             loads = false;
    1347             :           else
    1348             :             stores = false;
    1349             :           break;
    1350             :         }
    1351          23 :         if (loads == stores)
    1352           0 :           report("Missing fixed stack memoperand.", MI);
    1353             :       }
    1354        7640 :       if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
    1355           0 :         report("Instruction loads from dead spill slot", MO, MONum);
    1356           0 :         errs() << "Live stack: " << LI << '\n';
    1357             :       }
    1358        7006 :       if (stores && !LI.liveAt(Idx.getRegSlot())) {
    1359           0 :         report("Instruction stores to dead spill slot", MO, MONum);
    1360           0 :         errs() << "Live stack: " << LI << '\n';
    1361             :       }
    1362             :     }
    1363             :     break;
    1364             : 
    1365             :   default:
    1366             :     break;
    1367             :   }
    1368             : }
    1369             : 
    1370     4288374 : void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
    1371             :     unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
    1372             :     LaneBitmask LaneMask) {
    1373     4288374 :   LiveQueryResult LRQ = LR.Query(UseIdx);
    1374             :   // Check if we have a segment at the use, note however that we only need one
    1375             :   // live subregister range, the others may be dead.
    1376     4288374 :   if (!LRQ.valueIn() && LaneMask.none()) {
    1377           0 :     report("No live segment at use", MO, MONum);
    1378           0 :     report_context_liverange(LR);
    1379           0 :     report_context_vreg_regunit(VRegOrUnit);
    1380           0 :     report_context(UseIdx);
    1381             :   }
    1382     4288374 :   if (MO->isKill() && !LRQ.isKill()) {
    1383           0 :     report("Live range continues after kill flag", MO, MONum);
    1384           0 :     report_context_liverange(LR);
    1385           0 :     report_context_vreg_regunit(VRegOrUnit);
    1386           0 :     if (LaneMask.any())
    1387           0 :       report_context_lanemask(LaneMask);
    1388           0 :     report_context(UseIdx);
    1389             :   }
    1390     4288374 : }
    1391             : 
    1392     2710221 : void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
    1393             :     unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
    1394             :     LaneBitmask LaneMask) {
    1395     2710221 :   if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
    1396             :     assert(VNI && "NULL valno is not allowed");
    1397     2710221 :     if (VNI->def != DefIdx) {
    1398           0 :       report("Inconsistent valno->def", MO, MONum);
    1399           0 :       report_context_liverange(LR);
    1400           0 :       report_context_vreg_regunit(VRegOrUnit);
    1401           0 :       if (LaneMask.any())
    1402           0 :         report_context_lanemask(LaneMask);
    1403           0 :       report_context(*VNI);
    1404           0 :       report_context(DefIdx);
    1405             :     }
    1406             :   } else {
    1407           0 :     report("No live segment at def", MO, MONum);
    1408           0 :     report_context_liverange(LR);
    1409           0 :     report_context_vreg_regunit(VRegOrUnit);
    1410           0 :     if (LaneMask.any())
    1411           0 :       report_context_lanemask(LaneMask);
    1412           0 :     report_context(DefIdx);
    1413             :   }
    1414             :   // Check that, if the dead def flag is present, LiveInts agree.
    1415     2710221 :   if (MO->isDead()) {
    1416       33851 :     LiveQueryResult LRQ = LR.Query(DefIdx);
    1417       33851 :     if (!LRQ.isDeadDef()) {
    1418             :       // In case of physregs we can have a non-dead definition on another
    1419             :       // operand.
    1420             :       bool otherDef = false;
    1421           0 :       if (!TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
    1422           0 :         const MachineInstr &MI = *MO->getParent();
    1423           0 :         for (const MachineOperand &MO : MI.operands()) {
    1424           0 :           if (!MO.isReg() || !MO.isDef() || MO.isDead())
    1425           0 :             continue;
    1426           0 :           unsigned Reg = MO.getReg();
    1427           0 :           for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
    1428           0 :             if (*Units == VRegOrUnit) {
    1429             :               otherDef = true;
    1430             :               break;
    1431             :             }
    1432             :           }
    1433             :         }
    1434             :       }
    1435             : 
    1436           0 :       if (!otherDef) {
    1437           0 :         report("Live range continues after dead def flag", MO, MONum);
    1438           0 :         report_context_liverange(LR);
    1439           0 :         report_context_vreg_regunit(VRegOrUnit);
    1440           0 :         if (LaneMask.any())
    1441           0 :           report_context_lanemask(LaneMask);
    1442             :       }
    1443             :     }
    1444             :   }
    1445     2710221 : }
    1446             : 
    1447    55539437 : void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
    1448    55539437 :   const MachineInstr *MI = MO->getParent();
    1449    55539437 :   const unsigned Reg = MO->getReg();
    1450             : 
    1451             :   // Both use and def operands can read a register.
    1452             :   if (MO->readsReg()) {
    1453    35132109 :     if (MO->isKill())
    1454     8823858 :       addRegWithSubRegs(regsKilled, Reg);
    1455             : 
    1456             :     // Check that LiveVars knows this kill.
    1457    35133297 :     if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
    1458             :         MO->isKill()) {
    1459         507 :       LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
    1460         507 :       if (!is_contained(VI.Kills, MI))
    1461           0 :         report("Kill missing from LiveVariables", MO, MONum);
    1462             :     }
    1463             : 
    1464             :     // Check LiveInts liveness and kill.
    1465    35132109 :     if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
    1466     8504294 :       SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
    1467             :       // Check the cached regunit intervals.
    1468     8504294 :       if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
    1469     1590667 :         for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
    1470     1256222 :           if (MRI->isReservedRegUnit(*Units))
    1471          34 :             continue;
    1472     1256154 :           if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
    1473      535159 :             checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
    1474             :         }
    1475             :       }
    1476             : 
    1477     8504294 :       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    1478     2575275 :         if (LiveInts->hasInterval(Reg)) {
    1479             :           // This is a virtual register interval.
    1480     2575275 :           const LiveInterval &LI = LiveInts->getInterval(Reg);
    1481     2575275 :           checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
    1482             : 
    1483     3527237 :           if (LI.hasSubRanges() && !MO->isDef()) {
    1484             :             unsigned SubRegIdx = MO->getSubReg();
    1485             :             LaneBitmask MOMask = SubRegIdx != 0
    1486      349905 :                                ? TRI->getSubRegIndexLaneMask(SubRegIdx)
    1487     1213126 :                                : MRI->getMaxLaneMaskForVReg(Reg);
    1488             :             LaneBitmask LiveInMask;
    1489     2773696 :             for (const LiveInterval::SubRange &SR : LI.subranges()) {
    1490     2167133 :               if ((MOMask & SR.LaneMask).none())
    1491      989193 :                 continue;
    1492     1177940 :               checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
    1493     1177940 :               LiveQueryResult LRQ = SR.Query(UseIdx);
    1494     1177940 :               if (LRQ.valueIn())
    1495             :                 LiveInMask |= SR.LaneMask;
    1496             :             }
    1497             :             // At least parts of the register has to be live at the use.
    1498      606563 :             if ((LiveInMask & MOMask).none()) {
    1499           0 :               report("No live subrange at use", MO, MONum);
    1500           0 :               report_context(LI);
    1501           0 :               report_context(UseIdx);
    1502             :             }
    1503             :           }
    1504             :         } else {
    1505           0 :           report("Virtual register has no live interval", MO, MONum);
    1506             :         }
    1507             :       }
    1508             :     }
    1509             : 
    1510             :     // Use of a dead register.
    1511             :     if (!regsLive.count(Reg)) {
    1512    21067648 :       if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
    1513             :         // Reserved registers may be used even when 'dead'.
    1514    10070875 :         bool Bad = !isReserved(Reg);
    1515             :         // We are fine if just any subregister has a defined value.
    1516    10070875 :         if (Bad) {
    1517     1849137 :           for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
    1518             :                ++SubRegs) {
    1519     1918834 :             if (regsLive.count(*SubRegs)) {
    1520             :               Bad = false;
    1521             :               break;
    1522             :             }
    1523             :           }
    1524             :         }
    1525             :         // If there is an additional implicit-use of a super register we stop
    1526             :         // here. By definition we are fine if the super register is not
    1527             :         // (completely) dead, if the complete super register is dead we will
    1528             :         // get a report for its operand.
    1529    10070875 :         if (Bad) {
    1530        2222 :           for (const MachineOperand &MOP : MI->uses()) {
    1531         873 :             if (!MOP.isReg())
    1532          60 :               continue;
    1533         813 :             if (!MOP.isImplicit())
    1534         268 :               continue;
    1535        3921 :             for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
    1536             :                  ++SubRegs) {
    1537        3069 :               if (*SubRegs == Reg) {
    1538             :                 Bad = false;
    1539             :                 break;
    1540             :               }
    1541             :             }
    1542             :           }
    1543             :         }
    1544    10070875 :         if (Bad)
    1545           0 :           report("Using an undefined physical register", MO, MONum);
    1546      925898 :       } else if (MRI->def_empty(Reg)) {
    1547           0 :         report("Reading virtual register without a def", MO, MONum);
    1548             :       } else {
    1549      925898 :         BBInfo &MInfo = MBBInfoMap[MI->getParent()];
    1550             :         // We don't know which virtual registers are live in, so only complain
    1551             :         // if vreg was killed in this MBB. Otherwise keep track of vregs that
    1552             :         // must be live in. PHI instructions are handled separately.
    1553             :         if (MInfo.regsKilled.count(Reg))
    1554           0 :           report("Using a killed virtual register", MO, MONum);
    1555      462949 :         else if (!MI->isPHI())
    1556      599944 :           MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
    1557             :       }
    1558             :     }
    1559             :   }
    1560             : 
    1561    55539437 :   if (MO->isDef()) {
    1562             :     // Register defined.
    1563             :     // TODO: verify that earlyclobber ops are not used.
    1564    20577686 :     if (MO->isDead())
    1565     1852294 :       addRegWithSubRegs(regsDead, Reg);
    1566             :     else
    1567    18725392 :       addRegWithSubRegs(regsDefined, Reg);
    1568             : 
    1569             :     // Verify SSA form.
    1570    58951266 :     if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
    1571     8160980 :         std::next(MRI->def_begin(Reg)) != MRI->def_end())
    1572           0 :       report("Multiple virtual register defs in SSA form", MO, MONum);
    1573             : 
    1574             :     // Check LiveInts for a live segment, but only for virtual registers.
    1575    20577686 :     if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
    1576     2378315 :       SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
    1577             :       DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
    1578             : 
    1579     4756630 :       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    1580     1903807 :         if (LiveInts->hasInterval(Reg)) {
    1581     1903807 :           const LiveInterval &LI = LiveInts->getInterval(Reg);
    1582     1903807 :           checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
    1583             : 
    1584     1903807 :           if (LI.hasSubRanges()) {
    1585             :             unsigned SubRegIdx = MO->getSubReg();
    1586             :             LaneBitmask MOMask = SubRegIdx != 0
    1587      540142 :               ? TRI->getSubRegIndexLaneMask(SubRegIdx)
    1588     1222664 :               : MRI->getMaxLaneMaskForVReg(Reg);
    1589     2712143 :             for (const LiveInterval::SubRange &SR : LI.subranges()) {
    1590     2100811 :               if ((SR.LaneMask & MOMask).none())
    1591     1294397 :                 continue;
    1592      806414 :               checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, SR.LaneMask);
    1593             :             }
    1594             :           }
    1595             :         } else {
    1596           0 :           report("Virtual register has no Live interval", MO, MONum);
    1597             :         }
    1598             :       }
    1599             :     }
    1600             :   }
    1601    55539437 : }
    1602             : 
    1603             : void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {}
    1604             : 
    1605             : // This function gets called after visiting all instructions in a bundle. The
    1606             : // argument points to the bundle header.
    1607             : // Normal stand-alone instructions are also considered 'bundles', and this
    1608             : // function is called for all of them.
    1609    22287175 : void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
    1610    44574350 :   BBInfo &MInfo = MBBInfoMap[MI->getParent()];
    1611    22287175 :   set_union(MInfo.regsKilled, regsKilled);
    1612             :   set_subtract(regsLive, regsKilled); regsKilled.clear();
    1613             :   // Kill any masked registers.
    1614    22491993 :   while (!regMasks.empty()) {
    1615             :     const uint32_t *Mask = regMasks.pop_back_val();
    1616     5112258 :     for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
    1617    13942874 :       if (TargetRegisterInfo::isPhysicalRegister(*I) &&
    1618             :           MachineOperand::clobbersPhysReg(Mask, *I))
    1619     1817864 :         regsDead.push_back(*I);
    1620             :   }
    1621             :   set_subtract(regsLive, regsDead);   regsDead.clear();
    1622    22287175 :   set_union(regsLive, regsDefined);   regsDefined.clear();
    1623    22287175 : }
    1624             : 
    1625             : void
    1626     1876575 : MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
    1627     1876575 :   MBBInfoMap[MBB].regsLiveOut = regsLive;
    1628             :   regsLive.clear();
    1629             : 
    1630     1876575 :   if (Indexes) {
    1631      270433 :     SlotIndex stop = Indexes->getMBBEndIdx(MBB);
    1632      270433 :     if (!(stop > lastIndex)) {
    1633           0 :       report("Block ends before last instruction index", MBB);
    1634           0 :       errs() << "Block ends at " << stop
    1635           0 :           << " last instruction was at " << lastIndex << '\n';
    1636             :     }
    1637      270433 :     lastIndex = stop;
    1638             :   }
    1639     1876575 : }
    1640             : 
    1641             : // Calculate the largest possible vregsPassed sets. These are the registers that
    1642             : // can pass through an MBB live, but may not be live every time. It is assumed
    1643             : // that all vregsPassed sets are empty before the call.
    1644     1501887 : void MachineVerifier::calcRegsPassed() {
    1645             :   // First push live-out regs to successors' vregsPassed. Remember the MBBs that
    1646             :   // have any vregsPassed.
    1647             :   SmallPtrSet<const MachineBasicBlock*, 8> todo;
    1648     4880349 :   for (const auto &MBB : *MF) {
    1649     3753150 :     BBInfo &MInfo = MBBInfoMap[&MBB];
    1650     1876575 :     if (!MInfo.reachable)
    1651        1248 :       continue;
    1652             :     for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
    1653     2407174 :            SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
    1654     1063694 :       BBInfo &SInfo = MBBInfoMap[*SuI];
    1655      531847 :       if (SInfo.addPassed(MInfo.regsLiveOut))
    1656      181063 :         todo.insert(*SuI);
    1657             :     }
    1658             :   }
    1659             : 
    1660             :   // Iteratively push vregsPassed to successors. This will converge to the same
    1661             :   // final state regardless of DenseSet iteration order.
    1662     1942821 :   while (!todo.empty()) {
    1663      440934 :     const MachineBasicBlock *MBB = *todo.begin();
    1664             :     todo.erase(MBB);
    1665      220467 :     BBInfo &MInfo = MBBInfoMap[MBB];
    1666      220467 :     for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
    1667      444479 :            SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
    1668      224012 :       if (*SuI == MBB)
    1669       23645 :         continue;
    1670      400734 :       BBInfo &SInfo = MBBInfoMap[*SuI];
    1671      200367 :       if (SInfo.addPassed(MInfo.vregsPassed))
    1672      135042 :         todo.insert(*SuI);
    1673             :     }
    1674             :   }
    1675     1501887 : }
    1676             : 
    1677             : // Calculate the set of virtual registers that must be passed through each basic
    1678             : // block in order to satisfy the requirements of successor blocks. This is very
    1679             : // similar to calcRegsPassed, only backwards.
    1680     1501887 : void MachineVerifier::calcRegsRequired() {
    1681             :   // First push live-in regs to predecessors' vregsRequired.
    1682             :   SmallPtrSet<const MachineBasicBlock*, 8> todo;
    1683     4880349 :   for (const auto &MBB : *MF) {
    1684     3753150 :     BBInfo &MInfo = MBBInfoMap[&MBB];
    1685             :     for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
    1686     2408728 :            PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
    1687     1064306 :       BBInfo &PInfo = MBBInfoMap[*PrI];
    1688      532153 :       if (PInfo.addRequired(MInfo.vregsLiveIn))
    1689       68031 :         todo.insert(*PrI);
    1690             :     }
    1691             :   }
    1692             : 
    1693             :   // Iteratively push vregsRequired to predecessors. This will converge to the
    1694             :   // same final state regardless of DenseSet iteration order.
    1695     1684023 :   while (!todo.empty()) {
    1696      182136 :     const MachineBasicBlock *MBB = *todo.begin();
    1697             :     todo.erase(MBB);
    1698       91068 :     BBInfo &MInfo = MBBInfoMap[MBB];
    1699       91068 :     for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
    1700      221481 :            PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
    1701      130413 :       if (*PrI == MBB)
    1702       17832 :         continue;
    1703      225162 :       BBInfo &SInfo = MBBInfoMap[*PrI];
    1704      112581 :       if (SInfo.addRequired(MInfo.vregsRequired))
    1705       43158 :         todo.insert(*PrI);
    1706             :     }
    1707             :   }
    1708     1501887 : }
    1709             : 
    1710             : // Check PHI instructions at the beginning of MBB. It is assumed that
    1711             : // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
    1712     1876575 : void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
    1713     3753150 :   BBInfo &MInfo = MBBInfoMap[&MBB];
    1714             : 
    1715             :   SmallPtrSet<const MachineBasicBlock*, 8> seen;
    1716     3833729 :   for (const MachineInstr &Phi : MBB) {
    1717             :     if (!Phi.isPHI())
    1718             :       break;
    1719       80579 :     seen.clear();
    1720             : 
    1721       80579 :     const MachineOperand &MODef = Phi.getOperand(0);
    1722      161158 :     if (!MODef.isReg() || !MODef.isDef()) {
    1723           0 :       report("Expected first PHI operand to be a register def", &MODef, 0);
    1724           0 :       continue;
    1725             :     }
    1726      241737 :     if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
    1727      161158 :         MODef.isEarlyClobber() || MODef.isDebug())
    1728           0 :       report("Unexpected flag on PHI operand", &MODef, 0);
    1729       80579 :     unsigned DefReg = MODef.getReg();
    1730       80579 :     if (!TargetRegisterInfo::isVirtualRegister(DefReg))
    1731           0 :       report("Expected first PHI operand to be a virtual register", &MODef, 0);
    1732             : 
    1733      243635 :     for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
    1734      163056 :       const MachineOperand &MO0 = Phi.getOperand(I);
    1735      163056 :       if (!MO0.isReg()) {
    1736           0 :         report("Expected PHI operand to be a register", &MO0, I);
    1737           0 :         continue;
    1738             :       }
    1739      326112 :       if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
    1740      326112 :           MO0.isDebug() || MO0.isTied())
    1741           0 :         report("Unexpected flag on PHI operand", &MO0, I);
    1742             : 
    1743      163056 :       const MachineOperand &MO1 = Phi.getOperand(I + 1);
    1744      163056 :       if (!MO1.isMBB()) {
    1745           0 :         report("Expected PHI operand to be a basic block", &MO1, I + 1);
    1746           0 :         continue;
    1747             :       }
    1748             : 
    1749      163056 :       const MachineBasicBlock &Pre = *MO1.getMBB();
    1750      163056 :       if (!Pre.isSuccessor(&MBB)) {
    1751           0 :         report("PHI input is not a predecessor block", &MO1, I + 1);
    1752           0 :         continue;
    1753             :       }
    1754             : 
    1755      163056 :       if (MInfo.reachable) {
    1756      163056 :         seen.insert(&Pre);
    1757      326112 :         BBInfo &PrInfo = MBBInfoMap[&Pre];
    1758      326104 :         if (!MO0.isUndef() && PrInfo.reachable &&
    1759      163048 :             !PrInfo.isLiveOut(MO0.getReg()))
    1760           2 :           report("PHI operand is not live-out from predecessor", &MO0, I);
    1761             :       }
    1762             :     }
    1763             : 
    1764             :     // Did we see all predecessors?
    1765       80579 :     if (MInfo.reachable) {
    1766      243530 :       for (MachineBasicBlock *Pred : MBB.predecessors()) {
    1767      162954 :         if (!seen.count(Pred)) {
    1768           0 :           report("Missing PHI operand", &Phi);
    1769           0 :           errs() << printMBBReference(*Pred)
    1770           0 :                  << " is a predecessor according to the CFG.\n";
    1771             :         }
    1772             :       }
    1773             :     }
    1774             :   }
    1775     1876575 : }
    1776             : 
    1777     1501887 : void MachineVerifier::visitMachineFunctionAfter() {
    1778     1501887 :   calcRegsPassed();
    1779             : 
    1780     4880349 :   for (const MachineBasicBlock &MBB : *MF)
    1781     1876575 :     checkPHIOps(MBB);
    1782             : 
    1783             :   // Now check liveness info if available
    1784     1501887 :   calcRegsRequired();
    1785             : 
    1786             :   // Check for killed virtual registers that should be live out.
    1787     4880349 :   for (const auto &MBB : *MF) {
    1788     3753150 :     BBInfo &MInfo = MBBInfoMap[&MBB];
    1789             :     for (RegSet::iterator
    1790     2261061 :          I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
    1791             :          ++I)
    1792             :       if (MInfo.regsKilled.count(*I)) {
    1793           0 :         report("Virtual register killed in block, but needed live out.", &MBB);
    1794           0 :         errs() << "Virtual register " << printReg(*I)
    1795           0 :                << " is used after the block.\n";
    1796             :       }
    1797             :   }
    1798             : 
    1799     3003774 :   if (!MF->empty()) {
    1800     3003734 :     BBInfo &MInfo = MBBInfoMap[&MF->front()];
    1801             :     for (RegSet::iterator
    1802     1501867 :          I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
    1803             :          ++I) {
    1804           0 :       report("Virtual register defs don't dominate all uses.", MF);
    1805           0 :       report_context_vreg(*I);
    1806             :     }
    1807             :   }
    1808             : 
    1809     1501887 :   if (LiveVars)
    1810         117 :     verifyLiveVariables();
    1811     1501887 :   if (LiveInts)
    1812      180807 :     verifyLiveIntervals();
    1813     1501887 : }
    1814             : 
    1815         117 : void MachineVerifier::verifyLiveVariables() {
    1816             :   assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
    1817        1284 :   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
    1818         525 :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
    1819         525 :     LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
    1820        1749 :     for (const auto &MBB : *MF) {
    1821        1398 :       BBInfo &MInfo = MBBInfoMap[&MBB];
    1822             : 
    1823             :       // Our vregsRequired should be identical to LiveVariables' AliveBlocks
    1824             :       if (MInfo.vregsRequired.count(Reg)) {
    1825           0 :         if (!VI.AliveBlocks.test(MBB.getNumber())) {
    1826           0 :           report("LiveVariables: Block missing from AliveBlocks", &MBB);
    1827           0 :           errs() << "Virtual register " << printReg(Reg)
    1828           0 :                  << " must be live through the block.\n";
    1829             :         }
    1830             :       } else {
    1831         699 :         if (VI.AliveBlocks.test(MBB.getNumber())) {
    1832           0 :           report("LiveVariables: Block should not be in AliveBlocks", &MBB);
    1833           0 :           errs() << "Virtual register " << printReg(Reg)
    1834           0 :                  << " is not needed live through the block.\n";
    1835             :         }
    1836             :       }
    1837             :     }
    1838             :   }
    1839         117 : }
    1840             : 
    1841      180807 : void MachineVerifier::verifyLiveIntervals() {
    1842             :   assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
    1843     8437194 :   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
    1844             :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
    1845             : 
    1846             :     // Spilling and splitting may leave unused registers around. Skip them.
    1847     8075580 :     if (MRI->reg_nodbg_empty(Reg))
    1848     2547729 :       continue;
    1849             : 
    1850     1490061 :     if (!LiveInts->hasInterval(Reg)) {
    1851           0 :       report("Missing live interval for virtual register", MF);
    1852           0 :       errs() << printReg(Reg, TRI) << " still has defs or uses\n";
    1853           0 :       continue;
    1854             :     }
    1855             : 
    1856     1490061 :     const LiveInterval &LI = LiveInts->getInterval(Reg);
    1857             :     assert(Reg == LI.reg && "Invalid reg to interval mapping");
    1858     1490061 :     verifyLiveInterval(LI);
    1859             :   }
    1860             : 
    1861             :   // Verify all the cached regunit intervals.
    1862   192856833 :   for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
    1863   385352052 :     if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
    1864      613907 :       verifyLiveRange(*LR, i);
    1865      180807 : }
    1866             : 
    1867     3366442 : void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
    1868             :                                            const VNInfo *VNI, unsigned Reg,
    1869             :                                            LaneBitmask LaneMask) {
    1870     3366442 :   if (VNI->isUnused())
    1871             :     return;
    1872             : 
    1873             :   const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
    1874             : 
    1875     3363184 :   if (!DefVNI) {
    1876           0 :     report("Value not live at VNInfo def and not marked unused", MF);
    1877           0 :     report_context(LR, Reg, LaneMask);
    1878           0 :     report_context(*VNI);
    1879           0 :     return;
    1880             :   }
    1881             : 
    1882     3363184 :   if (DefVNI != VNI) {
    1883           0 :     report("Live segment at def has different VNInfo", MF);
    1884           0 :     report_context(LR, Reg, LaneMask);
    1885           0 :     report_context(*VNI);
    1886           0 :     return;
    1887             :   }
    1888             : 
    1889     3363184 :   const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
    1890     3363184 :   if (!MBB) {
    1891           0 :     report("Invalid VNInfo definition index", MF);
    1892           0 :     report_context(LR, Reg, LaneMask);
    1893           0 :     report_context(*VNI);
    1894           0 :     return;
    1895             :   }
    1896             : 
    1897     3363184 :   if (VNI->isPHIDef()) {
    1898      866132 :     if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
    1899           0 :       report("PHIDef VNInfo is not defined at MBB start", MBB);
    1900           0 :       report_context(LR, Reg, LaneMask);
    1901           0 :       report_context(*VNI);
    1902             :     }
    1903             :     return;
    1904             :   }
    1905             : 
    1906             :   // Non-PHI def.
    1907             :   const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
    1908     2930118 :   if (!MI) {
    1909           0 :     report("No instruction at VNInfo def index", MBB);
    1910           0 :     report_context(LR, Reg, LaneMask);
    1911           0 :     report_context(*VNI);
    1912           0 :     return;
    1913             :   }
    1914             : 
    1915     2930118 :   if (Reg != 0) {
    1916             :     bool hasDef = false;
    1917             :     bool isEarlyClobber = false;
    1918    15333990 :     for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
    1919    29251549 :       if (!MOI->isReg() || !MOI->isDef())
    1920     8875827 :         continue;
    1921     3537343 :       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    1922     3093607 :         if (MOI->getReg() != Reg)
    1923      382953 :           continue;
    1924             :       } else {
    1925     1270722 :         if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
    1926      383250 :             !TRI->hasRegUnit(MOI->getReg(), Reg))
    1927      232442 :           continue;
    1928             :       }
    1929     3728471 :       if (LaneMask.any() &&
    1930     1613018 :           (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
    1931          14 :         continue;
    1932             :       hasDef = true;
    1933     2921934 :       if (MOI->isEarlyClobber())
    1934             :         isEarlyClobber = true;
    1935             :     }
    1936             : 
    1937     2920820 :     if (!hasDef) {
    1938           0 :       report("Defining instruction does not modify register", MI);
    1939           0 :       report_context(LR, Reg, LaneMask);
    1940           0 :       report_context(*VNI);
    1941             :     }
    1942             : 
    1943             :     // Early clobber defs begin at USE slots, but other defs must begin at
    1944             :     // DEF slots.
    1945     2920820 :     if (isEarlyClobber) {
    1946       14266 :       if (!VNI->def.isEarlyClobber()) {
    1947           0 :         report("Early clobber def must be at an early-clobber slot", MBB);
    1948           0 :         report_context(LR, Reg, LaneMask);
    1949           0 :         report_context(*VNI);
    1950             :       }
    1951     2906554 :     } else if (!VNI->def.isRegister()) {
    1952           0 :       report("Non-PHI, non-early clobber def must be at a register slot", MBB);
    1953           0 :       report_context(LR, Reg, LaneMask);
    1954           0 :       report_context(*VNI);
    1955             :     }
    1956             :   }
    1957             : }
    1958             : 
    1959     3384226 : void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
    1960             :                                              const LiveRange::const_iterator I,
    1961             :                                              unsigned Reg, LaneBitmask LaneMask)
    1962             : {
    1963             :   const LiveRange::Segment &S = *I;
    1964     3384226 :   const VNInfo *VNI = S.valno;
    1965             :   assert(VNI && "Live segment has no valno");
    1966             : 
    1967    10152678 :   if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
    1968           0 :     report("Foreign valno in live segment", MF);
    1969           0 :     report_context(LR, Reg, LaneMask);
    1970           0 :     report_context(S);
    1971           0 :     report_context(*VNI);
    1972             :   }
    1973             : 
    1974     3384226 :   if (VNI->isUnused()) {
    1975           0 :     report("Live segment valno is marked unused", MF);
    1976           0 :     report_context(LR, Reg, LaneMask);
    1977           0 :     report_context(S);
    1978             :   }
    1979             : 
    1980     3384226 :   const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
    1981     3384226 :   if (!MBB) {
    1982           0 :     report("Bad start of live segment, no basic block", MF);
    1983           0 :     report_context(LR, Reg, LaneMask);
    1984           0 :     report_context(S);
    1985           0 :     return;
    1986             :   }
    1987     3384226 :   SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
    1988     3384226 :   if (S.start != MBBStartIdx && S.start != VNI->def) {
    1989           0 :     report("Live segment must begin at MBB entry or valno def", MBB);
    1990           0 :     report_context(LR, Reg, LaneMask);
    1991           0 :     report_context(S);
    1992             :   }
    1993             : 
    1994             :   const MachineBasicBlock *EndMBB =
    1995     6768452 :     LiveInts->getMBBFromIndex(S.end.getPrevSlot());
    1996     3384226 :   if (!EndMBB) {
    1997           0 :     report("Bad end of live segment, no basic block", MF);
    1998           0 :     report_context(LR, Reg, LaneMask);
    1999           0 :     report_context(S);
    2000           0 :     return;
    2001             :   }
    2002             : 
    2003             :   // No more checks for live-out segments.
    2004     6768452 :   if (S.end == LiveInts->getMBBEndIdx(EndMBB))
    2005             :     return;
    2006             : 
    2007             :   // RegUnit intervals are allowed dead phis.
    2008     1027991 :   if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
    2009     3703606 :       S.start == VNI->def && S.end == VNI->def.getDeadSlot())
    2010             :     return;
    2011             : 
    2012             :   // The live segment is ending inside EndMBB
    2013             :   const MachineInstr *MI =
    2014             :     LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
    2015     3298218 :   if (!MI) {
    2016           0 :     report("Live segment doesn't end at a valid instruction", EndMBB);
    2017           0 :     report_context(LR, Reg, LaneMask);
    2018           0 :     report_context(S);
    2019           0 :     return;
    2020             :   }
    2021             : 
    2022             :   // The block slot must refer to a basic block boundary.
    2023     3298218 :   if (S.end.isBlock()) {
    2024           0 :     report("Live segment ends at B slot of an instruction", EndMBB);
    2025           0 :     report_context(LR, Reg, LaneMask);
    2026           0 :     report_context(S);
    2027             :   }
    2028             : 
    2029     3298218 :   if (S.end.isDead()) {
    2030             :     // Segment ends on the dead slot.
    2031             :     // That means there must be a dead def.
    2032      127001 :     if (!SlotIndex::isSameInstr(S.start, S.end)) {
    2033           0 :       report("Live segment ending at dead slot spans instructions", EndMBB);
    2034           0 :       report_context(LR, Reg, LaneMask);
    2035           0 :       report_context(S);
    2036             :     }
    2037             :   }
    2038             : 
    2039             :   // A live segment can only end at an early-clobber slot if it is being
    2040             :   // redefined by an early-clobber def.
    2041     3298218 :   if (S.end.isEarlyClobber()) {
    2042       16296 :     if (I+1 == LR.end() || (I+1)->start != S.end) {
    2043           0 :       report("Live segment ending at early clobber slot must be "
    2044             :              "redefined by an EC def in the same instruction", EndMBB);
    2045           0 :       report_context(LR, Reg, LaneMask);
    2046           0 :       report_context(S);
    2047             :     }
    2048             :   }
    2049             : 
    2050             :   // The following checks only apply to virtual registers. Physreg liveness
    2051             :   // is too weird to check.
    2052     3298218 :   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    2053             :     // A live segment can end with either a redefinition, a kill flag on a
    2054             :     // use, or a dead flag on a def.
    2055             :     bool hasRead = false;
    2056             :     bool hasSubRegDef = false;
    2057             :     bool hasDeadDef = false;
    2058    17595281 :     for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
    2059    27035746 :       if (!MOI->isReg() || MOI->getReg() != Reg)
    2060    12116080 :         continue;
    2061             :       unsigned Sub = MOI->getSubReg();
    2062      693966 :       LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
    2063     3497552 :                                  : LaneBitmask::getAll();
    2064     2803586 :       if (MOI->isDef()) {
    2065      451415 :         if (Sub != 0) {
    2066             :           hasSubRegDef = true;
    2067             :           // An operand %0:sub0 reads %0:sub1..n. Invert the lane
    2068             :           // mask for subregister defs. Read-undef defs will be handled by
    2069             :           // readsReg below.
    2070             :           SLM = ~SLM;
    2071             :         }
    2072      451415 :         if (MOI->isDead())
    2073             :           hasDeadDef = true;
    2074             :       }
    2075     3646175 :       if (LaneMask.any() && (LaneMask & SLM).none())
    2076       16056 :         continue;
    2077             :       if (MOI->readsReg())
    2078             :         hasRead = true;
    2079             :     }
    2080     2675615 :     if (S.end.isDead()) {
    2081             :       // Make sure that the corresponding machine operand for a "dead" live
    2082             :       // range has the dead flag. We cannot perform this check for subregister
    2083             :       // liveranges as partially dead values are allowed.
    2084       39091 :       if (LaneMask.none() && !hasDeadDef) {
    2085           0 :         report("Instruction ending live segment on dead slot has no dead flag",
    2086             :                MI);
    2087           0 :         report_context(LR, Reg, LaneMask);
    2088           0 :         report_context(S);
    2089             :       }
    2090             :     } else {
    2091     2636524 :       if (!hasRead) {
    2092             :         // When tracking subregister liveness, the main range must start new
    2093             :         // values on partial register writes, even if there is no read.
    2094           2 :         if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
    2095             :             !hasSubRegDef) {
    2096           0 :           report("Instruction ending live segment doesn't read the register",
    2097             :                  MI);
    2098           0 :           report_context(LR, Reg, LaneMask);
    2099           0 :           report_context(S);
    2100             :         }
    2101             :       }
    2102             :     }
    2103             :   }
    2104             : 
    2105             :   // Now check all the basic blocks in this live segment.
    2106     3298218 :   MachineFunction::const_iterator MFI = MBB->getIterator();
    2107             :   // Is this live segment the beginning of a non-PHIDef VN?
    2108     6589975 :   if (S.start == VNI->def && !VNI->isPHIDef()) {
    2109             :     // Not live-in to any blocks.
    2110     2869476 :     if (MBB == EndMBB)
    2111             :       return;
    2112             :     // Skip this block.
    2113             :     ++MFI;
    2114             :   }
    2115             :   while (true) {
    2116             :     assert(LiveInts->isLiveInToMBB(LR, &*MFI));
    2117             :     // We don't know how to track physregs into a landing pad.
    2118      927443 :     if (!TargetRegisterInfo::isVirtualRegister(Reg) &&
    2119      402802 :         MFI->isEHPad()) {
    2120          56 :       if (&*MFI == EndMBB)
    2121             :         break;
    2122             :       ++MFI;
    2123           0 :       continue;
    2124             :     }
    2125             : 
    2126             :     // Is VNI a PHI-def in the current block?
    2127      953808 :     bool IsPHI = VNI->isPHIDef() &&
    2128      429223 :       VNI->def == LiveInts->getMBBStartIdx(&*MFI);
    2129             : 
    2130             :     // Check that VNI is live-out of all predecessors.
    2131             :     for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
    2132      707649 :          PE = MFI->pred_end(); PI != PE; ++PI) {
    2133      183064 :       SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
    2134      183064 :       const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
    2135             : 
    2136             :       // All predecessors must have a live-out value. However for a phi
    2137             :       // instruction with subregister intervals
    2138             :       // only one of the subregisters (not necessarily the current one) needs to
    2139             :       // be defined.
    2140      183064 :       if (!PVNI && (LaneMask.none() || !IsPHI) ) {
    2141           0 :         report("Register not marked live out of predecessor", *PI);
    2142           0 :         report_context(LR, Reg, LaneMask);
    2143           0 :         report_context(*VNI);
    2144           0 :         errs() << " live into " << printMBBReference(*MFI) << '@'
    2145           0 :                << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
    2146           0 :                << PEnd << '\n';
    2147             :         continue;
    2148             :       }
    2149             : 
    2150             :       // Only PHI-defs can take different predecessor values.
    2151      183064 :       if (!IsPHI && PVNI != VNI) {
    2152           0 :         report("Different value live out of predecessor", *PI);
    2153           0 :         report_context(LR, Reg, LaneMask);
    2154           0 :         errs() << "Valno #" << PVNI->id << " live out of "
    2155           0 :                << printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
    2156           0 :                << VNI->id << " live into " << printMBBReference(*MFI) << '@'
    2157           0 :                << LiveInts->getMBBStartIdx(&*MFI) << '\n';
    2158             :       }
    2159             :     }
    2160      524585 :     if (&*MFI == EndMBB)
    2161             :       break;
    2162             :     ++MFI;
    2163             :   }
    2164             : }
    2165             : 
    2166     2893088 : void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
    2167             :                                       LaneBitmask LaneMask) {
    2168     9625972 :   for (const VNInfo *VNI : LR.valnos)
    2169     3366442 :     verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
    2170             : 
    2171     9661540 :   for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
    2172     3384226 :     verifyLiveRangeSegment(LR, I, Reg, LaneMask);
    2173     2893088 : }
    2174             : 
    2175     1490061 : void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
    2176     1490061 :   unsigned Reg = LI.reg;
    2177             :   assert(TargetRegisterInfo::isVirtualRegister(Reg));
    2178     1490061 :   verifyLiveRange(LI, Reg);
    2179             : 
    2180             :   LaneBitmask Mask;
    2181     1490061 :   LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
    2182     2279181 :   for (const LiveInterval::SubRange &SR : LI.subranges()) {
    2183      789120 :     if ((Mask & SR.LaneMask).any()) {
    2184           0 :       report("Lane masks of sub ranges overlap in live interval", MF);
    2185           0 :       report_context(LI);
    2186             :     }
    2187      789120 :     if ((SR.LaneMask & ~MaxMask).any()) {
    2188           0 :       report("Subrange lanemask is invalid", MF);
    2189           0 :       report_context(LI);
    2190             :     }
    2191      789120 :     if (SR.empty()) {
    2192           0 :       report("Subrange must not be empty", MF);
    2193           0 :       report_context(SR, LI.reg, SR.LaneMask);
    2194             :     }
    2195             :     Mask |= SR.LaneMask;
    2196      789120 :     verifyLiveRange(SR, LI.reg, SR.LaneMask);
    2197      789120 :     if (!LI.covers(SR)) {
    2198           0 :       report("A Subrange is not covered by the main range", MF);
    2199           0 :       report_context(LI);
    2200             :     }
    2201             :   }
    2202             : 
    2203             :   // Check the LI only has one connected component.
    2204     1490061 :   ConnectedVNInfoEqClasses ConEQ(*LiveInts);
    2205     1490061 :   unsigned NumComp = ConEQ.Classify(LI);
    2206     1490061 :   if (NumComp > 1) {
    2207           0 :     report("Multiple connected components in live interval", MF);
    2208           0 :     report_context(LI);
    2209           0 :     for (unsigned comp = 0; comp != NumComp; ++comp) {
    2210           0 :       errs() << comp << ": valnos";
    2211           0 :       for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
    2212           0 :            E = LI.vni_end(); I!=E; ++I)
    2213           0 :         if (comp == ConEQ.getEqClass(*I))
    2214           0 :           errs() << ' ' << (*I)->id;
    2215           0 :       errs() << '\n';
    2216             :     }
    2217             :   }
    2218     1490061 : }
    2219             : 
    2220             : namespace {
    2221             : 
    2222             :   // FrameSetup and FrameDestroy can have zero adjustment, so using a single
    2223             :   // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
    2224             :   // value is zero.
    2225             :   // We use a bool plus an integer to capture the stack state.
    2226             :   struct StackStateOfBB {
    2227             :     StackStateOfBB() = default;
    2228             :     StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
    2229             :       EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
    2230             :       ExitIsSetup(ExitSetup) {}
    2231             : 
    2232             :     // Can be negative, which means we are setting up a frame.
    2233             :     int EntryValue = 0;
    2234             :     int ExitValue = 0;
    2235             :     bool EntryIsSetup = false;
    2236             :     bool ExitIsSetup = false;
    2237             :   };
    2238             : 
    2239             : } // end anonymous namespace
    2240             : 
    2241             : /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
    2242             : /// by a FrameDestroy <n>, stack adjustments are identical on all
    2243             : /// CFG edges to a merge point, and frame is destroyed at end of a return block.
    2244     1501867 : void MachineVerifier::verifyStackFrame() {
    2245     1501867 :   unsigned FrameSetupOpcode   = TII->getCallFrameSetupOpcode();
    2246     1501867 :   unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
    2247     1501867 :   if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
    2248        3473 :     return;
    2249             : 
    2250             :   SmallVector<StackStateOfBB, 8> SPState;
    2251     2996788 :   SPState.resize(MF->getNumBlockIDs());
    2252             :   df_iterator_default_set<const MachineBasicBlock*> Reachable;
    2253             : 
    2254             :   // Visit the MBBs in DFS order.
    2255             :   for (df_ext_iterator<const MachineFunction *,
    2256             :                        df_iterator_default_set<const MachineBasicBlock *>>
    2257     1498394 :        DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
    2258     3370014 :        DFI != DFE; ++DFI) {
    2259     1871620 :     const MachineBasicBlock *MBB = *DFI;
    2260             : 
    2261             :     StackStateOfBB BBState;
    2262             :     // Check the exit state of the DFS stack predecessor.
    2263     1871620 :     if (DFI.getPathLength() >= 2) {
    2264      373226 :       const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
    2265             :       assert(Reachable.count(StackPred) &&
    2266             :              "DFS stack predecessor is already visited.\n");
    2267      746452 :       BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
    2268      373226 :       BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
    2269             :       BBState.ExitValue = BBState.EntryValue;
    2270             :       BBState.ExitIsSetup = BBState.EntryIsSetup;
    2271             :     }
    2272             : 
    2273             :     // Update stack state by checking contents of MBB.
    2274    25995590 :     for (const auto &I : *MBB) {
    2275    44504700 :       if (I.getOpcode() == FrameSetupOpcode) {
    2276      115259 :         if (BBState.ExitIsSetup)
    2277           1 :           report("FrameSetup is after another FrameSetup", &I);
    2278      230518 :         BBState.ExitValue -= TII->getFrameTotalSize(I);
    2279             :         BBState.ExitIsSetup = true;
    2280             :       }
    2281             : 
    2282    44504700 :       if (I.getOpcode() == FrameDestroyOpcode) {
    2283      230518 :         int Size = TII->getFrameTotalSize(I);
    2284      115259 :         if (!BBState.ExitIsSetup)
    2285           1 :           report("FrameDestroy is not after a FrameSetup", &I);
    2286      115259 :         int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
    2287             :                                                BBState.ExitValue;
    2288      115259 :         if (BBState.ExitIsSetup && AbsSPAdj != Size) {
    2289           1 :           report("FrameDestroy <n> is after FrameSetup <m>", &I);
    2290           2 :           errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
    2291           1 :               << AbsSPAdj << ">.\n";
    2292             :         }
    2293      115259 :         BBState.ExitValue += Size;
    2294             :         BBState.ExitIsSetup = false;
    2295             :       }
    2296             :     }
    2297     3743240 :     SPState[MBB->getNumber()] = BBState;
    2298             : 
    2299             :     // Make sure the exit state of any predecessor is consistent with the entry
    2300             :     // state.
    2301             :     for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
    2302     2403199 :          E = MBB->pred_end(); I != E; ++I) {
    2303      990613 :       if (Reachable.count(*I) &&
    2304     1377102 :           (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
    2305      459034 :            SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
    2306           0 :         report("The exit stack state of a predecessor is inconsistent.", MBB);
    2307           0 :         errs() << "Predecessor " << printMBBReference(*(*I))
    2308           0 :                << " has exit state (" << SPState[(*I)->getNumber()].ExitValue
    2309           0 :                << ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while "
    2310           0 :                << printMBBReference(*MBB) << " has entry state ("
    2311           0 :                << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
    2312             :       }
    2313             :     }
    2314             : 
    2315             :     // Make sure the entry state of any successor is consistent with the exit
    2316             :     // state.
    2317             :     for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
    2318     2403131 :          E = MBB->succ_end(); I != E; ++I) {
    2319      648391 :       if (Reachable.count(*I) &&
    2320      350640 :           (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
    2321      116880 :            SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
    2322           0 :         report("The entry stack state of a successor is inconsistent.", MBB);
    2323           0 :         errs() << "Successor " << printMBBReference(*(*I))
    2324           0 :                << " has entry state (" << SPState[(*I)->getNumber()].EntryValue
    2325           0 :                << ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while "
    2326           0 :                << printMBBReference(*MBB) << " has exit state ("
    2327           0 :                << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
    2328             :       }
    2329             :     }
    2330             : 
    2331             :     // Make sure a basic block with return ends with zero stack adjustment.
    2332     3727448 :     if (!MBB->empty() && MBB->back().isReturn()) {
    2333     1514969 :       if (BBState.ExitIsSetup)
    2334           0 :         report("A return block ends with a FrameSetup.", MBB);
    2335     1514969 :       if (BBState.ExitValue)
    2336           0 :         report("A return block ends with a nonzero stack adjustment.", MBB);
    2337             :     }
    2338             :   }
    2339             : }

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