LCOV - code coverage report
Current view: top level - lib/CodeGen - ProcessImplicitDefs.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 61 63 96.8 %
Date: 2017-09-14 15:23:50 Functions: 8 9 88.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===---------------------- ProcessImplicitDefs.cpp -----------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : 
      10             : #include "llvm/ADT/SetVector.h"
      11             : #include "llvm/Analysis/AliasAnalysis.h"
      12             : #include "llvm/CodeGen/MachineFunctionPass.h"
      13             : #include "llvm/CodeGen/MachineInstr.h"
      14             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      15             : #include "llvm/CodeGen/Passes.h"
      16             : #include "llvm/Support/Debug.h"
      17             : #include "llvm/Support/raw_ostream.h"
      18             : #include "llvm/Target/TargetInstrInfo.h"
      19             : #include "llvm/Target/TargetSubtargetInfo.h"
      20             : 
      21             : using namespace llvm;
      22             : 
      23             : #define DEBUG_TYPE "processimpdefs"
      24             : 
      25             : namespace {
      26             : /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
      27             : /// for each use. Add isUndef marker to implicit_def defs and their uses.
      28       31001 : class ProcessImplicitDefs : public MachineFunctionPass {
      29             :   const TargetInstrInfo *TII;
      30             :   const TargetRegisterInfo *TRI;
      31             :   MachineRegisterInfo *MRI;
      32             : 
      33             :   SmallSetVector<MachineInstr*, 16> WorkList;
      34             : 
      35             :   void processImplicitDef(MachineInstr *MI);
      36             :   bool canTurnIntoImplicitDef(MachineInstr *MI);
      37             : 
      38             : public:
      39             :   static char ID;
      40             : 
      41       31198 :   ProcessImplicitDefs() : MachineFunctionPass(ID) {
      42       15599 :     initializeProcessImplicitDefsPass(*PassRegistry::getPassRegistry());
      43       15599 :   }
      44             : 
      45             :   void getAnalysisUsage(AnalysisUsage &au) const override;
      46             : 
      47             :   bool runOnMachineFunction(MachineFunction &fn) override;
      48             : };
      49             : } // end anonymous namespace
      50             : 
      51             : char ProcessImplicitDefs::ID = 0;
      52             : char &llvm::ProcessImplicitDefsID = ProcessImplicitDefs::ID;
      53             : 
      54      197996 : INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE,
      55             :                 "Process Implicit Definitions", false, false)
      56             : 
      57       15548 : void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
      58       15548 :   AU.setPreservesCFG();
      59       15548 :   AU.addPreserved<AAResultsWrapperPass>();
      60       15548 :   MachineFunctionPass::getAnalysisUsage(AU);
      61       15548 : }
      62             : 
      63       32394 : bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
      64       56206 :   if (!MI->isCopyLike() &&
      65       39718 :       !MI->isInsertSubreg() &&
      66       11615 :       !MI->isRegSequence() &&
      67             :       !MI->isPHI())
      68             :     return false;
      69       81611 :   for (const MachineOperand &MO : MI->operands())
      70      149036 :     if (MO.isReg() && MO.isUse() && MO.readsReg())
      71             :       return false;
      72             :   return true;
      73             : }
      74             : 
      75       32481 : void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
      76             :   DEBUG(dbgs() << "Processing " << *MI);
      77       32481 :   unsigned Reg = MI->getOperand(0).getReg();
      78             : 
      79       32481 :   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
      80             :     // For virtual registers, mark all uses as <undef>, and convert users to
      81             :     // implicit-def when possible.
      82      125985 :     for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
      83       32394 :       MO.setIsUndef();
      84       32394 :       MachineInstr *UserMI = MO.getParent();
      85       32394 :       if (!canTurnIntoImplicitDef(UserMI))
      86       27859 :         continue;
      87             :       DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
      88       13605 :       UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
      89        4535 :       WorkList.insert(UserMI);
      90             :     }
      91       31197 :     MI->eraseFromParent();
      92       31197 :     return;
      93             :   }
      94             : 
      95             :   // This is a physreg implicit-def.
      96             :   // Look for the first instruction to use or define an alias.
      97        2568 :   MachineBasicBlock::instr_iterator UserMI = MI->getIterator();
      98        2568 :   MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end();
      99        1284 :   bool Found = false;
     100        2370 :   for (++UserMI; UserMI != UserE; ++UserMI) {
     101       19285 :     for (MachineOperand &MO : UserMI->operands()) {
     102       14545 :       if (!MO.isReg())
     103        2113 :         continue;
     104       12432 :       unsigned UserReg = MO.getReg();
     105       23670 :       if (!TargetRegisterInfo::isPhysicalRegister(UserReg) ||
     106       11238 :           !TRI->regsOverlap(Reg, UserReg))
     107       11072 :         continue;
     108             :       // UserMI uses or redefines Reg. Set <undef> flags on all uses.
     109        1360 :       Found = true;
     110        1360 :       if (MO.isUse())
     111             :         MO.setIsUndef();
     112             :     }
     113        2370 :     if (Found)
     114             :       break;
     115             :   }
     116             : 
     117             :   // If we found the using MI, we can erase the IMPLICIT_DEF.
     118        1284 :   if (Found) {
     119             :     DEBUG(dbgs() << "Physreg user: " << *UserMI);
     120        1284 :     MI->eraseFromParent();
     121        1284 :     return;
     122             :   }
     123             : 
     124             :   // Using instr wasn't found, it could be in another block.
     125             :   // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
     126           0 :   for (unsigned i = MI->getNumOperands() - 1; i; --i)
     127           0 :     MI->RemoveOperand(i);
     128             :   DEBUG(dbgs() << "Keeping physreg: " << *MI);
     129             : }
     130             : 
     131             : /// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
     132             : /// <undef> operands.
     133      135772 : bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
     134             : 
     135             :   DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
     136             :                << "********** Function: " << MF.getName() << '\n');
     137             : 
     138      135772 :   bool Changed = false;
     139             : 
     140      135772 :   TII = MF.getSubtarget().getInstrInfo();
     141      135772 :   TRI = MF.getSubtarget().getRegisterInfo();
     142      135772 :   MRI = &MF.getRegInfo();
     143             :   assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
     144             :   assert(WorkList.empty() && "Inconsistent worklist state");
     145             : 
     146      271544 :   for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end();
     147      418462 :        MFI != MFE; ++MFI) {
     148             :     // Scan the basic block for implicit defs.
     149      565380 :     for (MachineBasicBlock::instr_iterator MBBI = MFI->instr_begin(),
     150      565380 :          MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI)
     151     7736536 :       if (MBBI->isImplicitDef())
     152       55892 :         WorkList.insert(&*MBBI);
     153             : 
     154      565380 :     if (WorkList.empty())
     155      265866 :       continue;
     156             : 
     157             :     DEBUG(dbgs() << "BB#" << MFI->getNumber() << " has " << WorkList.size()
     158             :                  << " implicit defs.\n");
     159             :     Changed = true;
     160             : 
     161             :     // Drain the WorkList to recursively process any new implicit defs.
     162       64962 :     do processImplicitDef(WorkList.pop_back_val());
     163       64962 :     while (!WorkList.empty());
     164             :   }
     165      135772 :   return Changed;
     166             : }

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