LCOV - code coverage report
Current view: top level - lib/CodeGen - RegAllocBase.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 58 59 98.3 %
Date: 2017-09-14 15:23:50 Functions: 6 7 85.7 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines the RegAllocBase class which provides common functionality
      11             : // for LiveIntervalUnion-based register allocators.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "RegAllocBase.h"
      16             : #include "Spiller.h"
      17             : #include "llvm/ADT/Statistic.h"
      18             : #include "llvm/CodeGen/LiveIntervalAnalysis.h"
      19             : #include "llvm/CodeGen/LiveRangeEdit.h"
      20             : #include "llvm/CodeGen/LiveRegMatrix.h"
      21             : #include "llvm/CodeGen/MachineInstr.h"
      22             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      23             : #include "llvm/CodeGen/VirtRegMap.h"
      24             : #include "llvm/Support/CommandLine.h"
      25             : #include "llvm/Support/Debug.h"
      26             : #include "llvm/Support/ErrorHandling.h"
      27             : #include "llvm/Support/Timer.h"
      28             : #include "llvm/Support/raw_ostream.h"
      29             : #include "llvm/Target/TargetRegisterInfo.h"
      30             : 
      31             : using namespace llvm;
      32             : 
      33             : #define DEBUG_TYPE "regalloc"
      34             : 
      35             : STATISTIC(NumNewQueued    , "Number of new live ranges queued");
      36             : 
      37             : // Temporary verification option until we can put verification inside
      38             : // MachineVerifier.
      39             : static cl::opt<bool, true>
      40      216918 : VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
      41      289224 :                cl::desc("Verify during register allocation"));
      42             : 
      43             : const char RegAllocBase::TimerGroupName[] = "regalloc";
      44             : const char RegAllocBase::TimerGroupDescription[] = "Register Allocation";
      45             : bool RegAllocBase::VerifyEnabled = false;
      46             : 
      47             : //===----------------------------------------------------------------------===//
      48             : //                         RegAllocBase Implementation
      49             : //===----------------------------------------------------------------------===//
      50             : 
      51             : // Pin the vtable to this file.
      52           0 : void RegAllocBase::anchor() {}
      53             : 
      54      134827 : void RegAllocBase::init(VirtRegMap &vrm,
      55             :                         LiveIntervals &lis,
      56             :                         LiveRegMatrix &mat) {
      57      134827 :   TRI = &vrm.getTargetRegInfo();
      58      134827 :   MRI = &vrm.getRegInfo();
      59      134827 :   VRM = &vrm;
      60      134827 :   LIS = &lis;
      61      134827 :   Matrix = &mat;
      62      134827 :   MRI->freezeReservedRegs(vrm.getMachineFunction());
      63      134827 :   RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
      64      134827 : }
      65             : 
      66             : // Visit all the live registers. If they are already assigned to a physical
      67             : // register, unify them with the corresponding LiveIntervalUnion, otherwise push
      68             : // them on the priority queue for later assignment.
      69      134827 : void RegAllocBase::seedLiveRegs() {
      70             :   NamedRegionTimer T("seed", "Seed Live Regs", TimerGroupName,
      71      808962 :                      TimerGroupDescription, TimePassesIsEnabled);
      72     2586212 :   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
      73     2316558 :     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
      74     4633116 :     if (MRI->reg_nodbg_empty(Reg))
      75     1182108 :       continue;
      76     1134450 :     enqueue(&LIS->getInterval(Reg));
      77             :   }
      78      134827 : }
      79             : 
      80             : // Top-level driver to manage the queue of unassigned VirtRegs and call the
      81             : // selectOrSplit implementation.
      82      134827 : void RegAllocBase::allocatePhysRegs() {
      83      134827 :   seedLiveRegs();
      84             : 
      85             :   // Continue assigning vregs one at a time to available physical registers.
      86     1457768 :   while (LiveInterval *VirtReg = dequeue()) {
      87             :     assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
      88             : 
      89             :     // Unused registers can appear when the spiller coalesces snippets.
      90     2647384 :     if (MRI->reg_nodbg_empty(VirtReg->reg)) {
      91             :       DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
      92        1496 :       aboutToRemoveInterval(*VirtReg);
      93        1496 :       LIS->removeInterval(VirtReg->reg);
      94        3085 :       continue;
      95             :     }
      96             : 
      97             :     // Invalidate all interference queries, live ranges could have changed.
      98     2642896 :     Matrix->invalidateVirtRegs();
      99             : 
     100             :     // selectOrSplit requests the allocator to return an available physical
     101             :     // register if possible and populate a list of new live intervals that
     102             :     // result from splitting.
     103             :     DEBUG(dbgs() << "\nselectOrSplit "
     104             :           << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
     105             :           << ':' << *VirtReg << " w=" << VirtReg->weight << '\n');
     106             :     typedef SmallVector<unsigned, 4> VirtRegVec;
     107     2642800 :     VirtRegVec SplitVRegs;
     108     1321448 :     unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
     109             : 
     110     1321448 :     if (AvailablePhysReg == ~0u) {
     111             :       // selectOrSplit failed to find a register!
     112             :       // Probably caused by an inline asm.
     113          96 :       MachineInstr *MI = nullptr;
     114             :       for (MachineRegisterInfo::reg_instr_iterator
     115          96 :            I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
     116         160 :            I != E; ) {
     117         471 :         MachineInstr *TmpMI = &*(I++);
     118         157 :         if (TmpMI->isInlineAsm()) {
     119             :           MI = TmpMI;
     120             :           break;
     121             :         }
     122             :       }
     123          96 :       if (MI)
     124          93 :         MI->emitError("inline assembly requires more registers than available");
     125             :       else
     126           3 :         report_fatal_error("ran out of registers during register allocation");
     127             :       // Keep going after reporting the error.
     128         186 :       VRM->assignVirt2Phys(VirtReg->reg,
     129         279 :                  RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
     130          93 :       continue;
     131             :     }
     132             : 
     133     1321352 :     if (AvailablePhysReg)
     134     1221150 :       Matrix->assign(*VirtReg, AvailablePhysReg);
     135             : 
     136     4153722 :     for (unsigned Reg : SplitVRegs) {
     137             :       assert(LIS->hasInterval(Reg));
     138             : 
     139      189666 :       LiveInterval *SplitVirtReg = &LIS->getInterval(Reg);
     140             :       assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
     141      386029 :       if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
     142             :         assert(SplitVirtReg->empty() && "Non-empty but used interval");
     143             :         DEBUG(dbgs() << "not queueing unused  " << *SplitVirtReg << '\n');
     144        6697 :         aboutToRemoveInterval(*SplitVirtReg);
     145        6697 :         LIS->removeInterval(SplitVirtReg->reg);
     146        6697 :         continue;
     147             :       }
     148             :       DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
     149             :       assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
     150             :              "expect split value in virtual register");
     151      182969 :       enqueue(SplitVirtReg);
     152             :       ++NumNewQueued;
     153             :     }
     154             :   }
     155      134824 : }
     156             : 
     157      134824 : void RegAllocBase::postOptimization() {
     158      134824 :   spiller().postOptimization();
     159      143082 :   for (auto DeadInst : DeadRemats) {
     160       16516 :     LIS->RemoveMachineInstrFromMaps(*DeadInst);
     161        8258 :     DeadInst->eraseFromParent();
     162             :   }
     163      134824 :   DeadRemats.clear();
     164      351742 : }

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