LCOV - code coverage report
Current view: top level - lib/CodeGen - RegAllocPBQP.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 307 346 88.7 %
Date: 2017-09-14 15:23:50 Functions: 31 38 81.6 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- RegAllocPBQP.cpp ---- PBQP Register Allocator ----------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
      11             : // register allocator for LLVM. This allocator works by constructing a PBQP
      12             : // problem representing the register allocation problem under consideration,
      13             : // solving this using a PBQP solver, and mapping the solution back to a
      14             : // register assignment. If any variables are selected for spilling then spill
      15             : // code is inserted and the process repeated.
      16             : //
      17             : // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
      18             : // for register allocation. For more information on PBQP for register
      19             : // allocation, see the following papers:
      20             : //
      21             : //   (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
      22             : //   PBQP. In Proceedings of the 7th Joint Modular Languages Conference
      23             : //   (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
      24             : //
      25             : //   (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
      26             : //   architectures. In Proceedings of the Joint Conference on Languages,
      27             : //   Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
      28             : //   NY, USA, 139-148.
      29             : //
      30             : //===----------------------------------------------------------------------===//
      31             : 
      32             : #include "llvm/CodeGen/RegAllocPBQP.h"
      33             : #include "RegisterCoalescer.h"
      34             : #include "Spiller.h"
      35             : #include "llvm/ADT/ArrayRef.h"
      36             : #include "llvm/ADT/BitVector.h"
      37             : #include "llvm/ADT/DenseMap.h"
      38             : #include "llvm/ADT/DenseSet.h"
      39             : #include "llvm/ADT/STLExtras.h"
      40             : #include "llvm/ADT/SmallPtrSet.h"
      41             : #include "llvm/ADT/SmallVector.h"
      42             : #include "llvm/ADT/StringRef.h"
      43             : #include "llvm/Analysis/AliasAnalysis.h"
      44             : #include "llvm/CodeGen/CalcSpillWeights.h"
      45             : #include "llvm/CodeGen/LiveInterval.h"
      46             : #include "llvm/CodeGen/LiveIntervalAnalysis.h"
      47             : #include "llvm/CodeGen/LiveRangeEdit.h"
      48             : #include "llvm/CodeGen/LiveStackAnalysis.h"
      49             : #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
      50             : #include "llvm/CodeGen/MachineDominators.h"
      51             : #include "llvm/CodeGen/MachineFunction.h"
      52             : #include "llvm/CodeGen/MachineFunctionPass.h"
      53             : #include "llvm/CodeGen/MachineInstr.h"
      54             : #include "llvm/CodeGen/MachineLoopInfo.h"
      55             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      56             : #include "llvm/CodeGen/PBQP/Graph.h"
      57             : #include "llvm/CodeGen/PBQP/Math.h"
      58             : #include "llvm/CodeGen/PBQP/Solution.h"
      59             : #include "llvm/CodeGen/PBQPRAConstraint.h"
      60             : #include "llvm/CodeGen/RegAllocRegistry.h"
      61             : #include "llvm/CodeGen/SlotIndexes.h"
      62             : #include "llvm/CodeGen/VirtRegMap.h"
      63             : #include "llvm/IR/Function.h"
      64             : #include "llvm/IR/Module.h"
      65             : #include "llvm/MC/MCRegisterInfo.h"
      66             : #include "llvm/Pass.h"
      67             : #include "llvm/Support/CommandLine.h"
      68             : #include "llvm/Support/Compiler.h"
      69             : #include "llvm/Support/Debug.h"
      70             : #include "llvm/Support/FileSystem.h"
      71             : #include "llvm/Support/Printable.h"
      72             : #include "llvm/Support/raw_ostream.h"
      73             : #include "llvm/Target/TargetRegisterInfo.h"
      74             : #include "llvm/Target/TargetSubtargetInfo.h"
      75             : #include <algorithm>
      76             : #include <cassert>
      77             : #include <cstddef>
      78             : #include <limits>
      79             : #include <map>
      80             : #include <memory>
      81             : #include <queue>
      82             : #include <set>
      83             : #include <sstream>
      84             : #include <string>
      85             : #include <system_error>
      86             : #include <tuple>
      87             : #include <utility>
      88             : #include <vector>
      89             : 
      90             : using namespace llvm;
      91             : 
      92             : #define DEBUG_TYPE "regalloc"
      93             : 
      94             : static RegisterRegAlloc
      95       72306 : RegisterPBQPRepAlloc("pbqp", "PBQP register allocator",
      96       72306 :                        createDefaultPBQPRegisterAllocator);
      97             : 
      98             : static cl::opt<bool>
      99       72306 : PBQPCoalescing("pbqp-coalescing",
     100      216918 :                 cl::desc("Attempt coalescing during PBQP register allocation."),
     101      289224 :                 cl::init(false), cl::Hidden);
     102             : 
     103             : #ifndef NDEBUG
     104             : static cl::opt<bool>
     105             : PBQPDumpGraphs("pbqp-dump-graphs",
     106             :                cl::desc("Dump graphs for each function/round in the compilation unit."),
     107             :                cl::init(false), cl::Hidden);
     108             : #endif
     109             : 
     110             : namespace {
     111             : 
     112             : ///
     113             : /// PBQP based allocators solve the register allocation problem by mapping
     114             : /// register allocation problems to Partitioned Boolean Quadratic
     115             : /// Programming problems.
     116          35 : class RegAllocPBQP : public MachineFunctionPass {
     117             : public:
     118             :   static char ID;
     119             : 
     120             :   /// Construct a PBQP register allocator.
     121           7 :   RegAllocPBQP(char *cPassID = nullptr)
     122          28 :       : MachineFunctionPass(ID), customPassID(cPassID) {
     123           7 :     initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
     124           7 :     initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
     125           7 :     initializeLiveStacksPass(*PassRegistry::getPassRegistry());
     126           7 :     initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
     127           7 :   }
     128             : 
     129             :   /// Return the pass name.
     130           7 :   StringRef getPassName() const override { return "PBQP Register Allocator"; }
     131             : 
     132             :   /// PBQP analysis usage.
     133             :   void getAnalysisUsage(AnalysisUsage &au) const override;
     134             : 
     135             :   /// Perform register allocation
     136             :   bool runOnMachineFunction(MachineFunction &MF) override;
     137             : 
     138           7 :   MachineFunctionProperties getRequiredProperties() const override {
     139          21 :     return MachineFunctionProperties().set(
     140          21 :         MachineFunctionProperties::Property::NoPHIs);
     141             :   }
     142             : 
     143             : private:
     144             :   using LI2NodeMap = std::map<const LiveInterval *, unsigned>;
     145             :   using Node2LIMap = std::vector<const LiveInterval *>;
     146             :   using AllowedSet = std::vector<unsigned>;
     147             :   using AllowedSetMap = std::vector<AllowedSet>;
     148             :   using RegPair = std::pair<unsigned, unsigned>;
     149             :   using CoalesceMap = std::map<RegPair, PBQP::PBQPNum>;
     150             :   using RegSet = std::set<unsigned>;
     151             : 
     152             :   char *customPassID;
     153             : 
     154             :   RegSet VRegsToAlloc, EmptyIntervalVRegs;
     155             : 
     156             :   /// Inst which is a def of an original reg and whose defs are already all
     157             :   /// dead after remat is saved in DeadRemats. The deletion of such inst is
     158             :   /// postponed till all the allocations are done, so its remat expr is
     159             :   /// always available for the remat of all the siblings of the original reg.
     160             :   SmallPtrSet<MachineInstr *, 32> DeadRemats;
     161             : 
     162             :   /// \brief Finds the initial set of vreg intervals to allocate.
     163             :   void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
     164             : 
     165             :   /// \brief Constructs an initial graph.
     166             :   void initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM, Spiller &VRegSpiller);
     167             : 
     168             :   /// \brief Spill the given VReg.
     169             :   void spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals,
     170             :                  MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
     171             :                  Spiller &VRegSpiller);
     172             : 
     173             :   /// \brief Given a solved PBQP problem maps this solution back to a register
     174             :   /// assignment.
     175             :   bool mapPBQPToRegAlloc(const PBQPRAGraph &G,
     176             :                          const PBQP::Solution &Solution,
     177             :                          VirtRegMap &VRM,
     178             :                          Spiller &VRegSpiller);
     179             : 
     180             :   /// \brief Postprocessing before final spilling. Sets basic block "live in"
     181             :   /// variables.
     182             :   void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
     183             :                      VirtRegMap &VRM) const;
     184             : 
     185             :   void postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS);
     186             : };
     187             : 
     188             : char RegAllocPBQP::ID = 0;
     189             : 
     190             : /// @brief Set spill costs for each node in the PBQP reg-alloc graph.
     191          14 : class SpillCosts : public PBQPRAConstraint {
     192             : public:
     193           8 :   void apply(PBQPRAGraph &G) override {
     194           8 :     LiveIntervals &LIS = G.getMetadata().LIS;
     195             : 
     196             :     // A minimum spill costs, so that register constraints can can be set
     197             :     // without normalization in the [0.0:MinSpillCost( interval.
     198           8 :     const PBQP::PBQPNum MinSpillCost = 10.0;
     199             : 
     200         179 :     for (auto NId : G.nodeIds()) {
     201             :       PBQP::PBQPNum SpillCost =
     202         310 :         LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight;
     203         155 :       if (SpillCost == 0.0)
     204             :         SpillCost = std::numeric_limits<PBQP::PBQPNum>::min();
     205             :       else
     206         155 :         SpillCost += MinSpillCost;
     207         465 :       PBQPRAGraph::RawVector NodeCosts(G.getNodeCosts(NId));
     208         310 :       NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost;
     209         465 :       G.setNodeCosts(NId, std::move(NodeCosts));
     210             :     }
     211           8 :   }
     212             : };
     213             : 
     214             : /// @brief Add interference edges between overlapping vregs.
     215          14 : class Interference : public PBQPRAConstraint {
     216             : private:
     217             :   using AllowedRegVecPtr = const PBQP::RegAlloc::AllowedRegVector *;
     218             :   using IKey = std::pair<AllowedRegVecPtr, AllowedRegVecPtr>;
     219             :   using IMatrixCache = DenseMap<IKey, PBQPRAGraph::MatrixPtr>;
     220             :   using DisjointAllowedRegsCache = DenseSet<IKey>;
     221             :   using IEdgeKey = std::pair<PBQP::GraphBase::NodeId, PBQP::GraphBase::NodeId>;
     222             :   using IEdgeCache = DenseSet<IEdgeKey>;
     223             : 
     224        1074 :   bool haveDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
     225             :                                PBQPRAGraph::NodeId MId,
     226             :                                const DisjointAllowedRegsCache &D) const {
     227        3222 :     const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
     228        3222 :     const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
     229             : 
     230        1074 :     if (NRegs == MRegs)
     231             :       return false;
     232             : 
     233         644 :     if (NRegs < MRegs)
     234        1710 :       return D.count(IKey(NRegs, MRegs)) > 0;
     235             : 
     236         222 :     return D.count(IKey(MRegs, NRegs)) > 0;
     237             :   }
     238             : 
     239          14 :   void setDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
     240             :                               PBQPRAGraph::NodeId MId,
     241             :                               DisjointAllowedRegsCache &D) {
     242          42 :     const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
     243          42 :     const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
     244             : 
     245             :     assert(NRegs != MRegs && "AllowedRegs can not be disjoint with itself");
     246             : 
     247          14 :     if (NRegs < MRegs)
     248          42 :       D.insert(IKey(NRegs, MRegs));
     249             :     else
     250           0 :       D.insert(IKey(MRegs, NRegs));
     251          14 :   }
     252             : 
     253             :   // Holds (Interval, CurrentSegmentID, and NodeId). The first two are required
     254             :   // for the fast interference graph construction algorithm. The last is there
     255             :   // to save us from looking up node ids via the VRegToNode map in the graph
     256             :   // metadata.
     257             :   using IntervalInfo =
     258             :       std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>;
     259             : 
     260             :   static SlotIndex getStartPoint(const IntervalInfo &I) {
     261        6933 :     return std::get<0>(I)->segments[std::get<1>(I)].start;
     262             :   }
     263             : 
     264             :   static SlotIndex getEndPoint(const IntervalInfo &I) {
     265        5373 :     return std::get<0>(I)->segments[std::get<1>(I)].end;
     266             :   }
     267             : 
     268             :   static PBQP::GraphBase::NodeId getNodeId(const IntervalInfo &I) {
     269        1243 :     return std::get<2>(I);
     270             :   }
     271             : 
     272        1009 :   static bool lowestStartPoint(const IntervalInfo &I1,
     273             :                                const IntervalInfo &I2) {
     274             :     // Condition reversed because priority queue has the *highest* element at
     275             :     // the front, rather than the lowest.
     276        3027 :     return getStartPoint(I1) > getStartPoint(I2);
     277             :   }
     278             : 
     279         749 :   static bool lowestEndPoint(const IntervalInfo &I1,
     280             :                              const IntervalInfo &I2) {
     281         749 :     SlotIndex E1 = getEndPoint(I1);
     282         749 :     SlotIndex E2 = getEndPoint(I2);
     283             : 
     284         749 :     if (E1 < E2)
     285             :       return true;
     286             : 
     287         364 :     if (E1 > E2)
     288             :       return false;
     289             : 
     290             :     // If two intervals end at the same point, we need a way to break the tie or
     291             :     // the set will assume they're actually equal and refuse to insert a
     292             :     // "duplicate". Just compare the vregs - fast and guaranteed unique.
     293         338 :     return std::get<0>(I1)->reg < std::get<0>(I2)->reg;
     294             :   }
     295             : 
     296             :   static bool isAtLastSegment(const IntervalInfo &I) {
     297         432 :     return std::get<1>(I) == std::get<0>(I)->size() - 1;
     298             :   }
     299             : 
     300             :   static IntervalInfo nextSegment(const IntervalInfo &I) {
     301          42 :     return std::make_tuple(std::get<0>(I), std::get<1>(I) + 1, std::get<2>(I));
     302             :   }
     303             : 
     304             : public:
     305           8 :   void apply(PBQPRAGraph &G) override {
     306             :     // The following is loosely based on the linear scan algorithm introduced in
     307             :     // "Linear Scan Register Allocation" by Poletto and Sarkar. This version
     308             :     // isn't linear, because the size of the active set isn't bound by the
     309             :     // number of registers, but rather the size of the largest clique in the
     310             :     // graph. Still, we expect this to be better than N^2.
     311           8 :     LiveIntervals &LIS = G.getMetadata().LIS;
     312             : 
     313             :     // Interferenc matrices are incredibly regular - they're only a function of
     314             :     // the allowed sets, so we cache them to avoid the overhead of constructing
     315             :     // and uniquing them.
     316          16 :     IMatrixCache C;
     317             : 
     318             :     // Finding an edge is expensive in the worst case (O(max_clique(G))). So
     319             :     // cache locally edges we have already seen.
     320          16 :     IEdgeCache EC;
     321             : 
     322             :     // Cache known disjoint allowed registers pairs
     323          16 :     DisjointAllowedRegsCache D;
     324             : 
     325             :     using IntervalSet = std::set<IntervalInfo, decltype(&lowestEndPoint)>;
     326             :     using IntervalQueue =
     327             :         std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
     328             :                             decltype(&lowestStartPoint)>;
     329          32 :     IntervalSet Active(lowestEndPoint);
     330          24 :     IntervalQueue Inactive(lowestStartPoint);
     331             : 
     332             :     // Start by building the inactive set.
     333         179 :     for (auto NId : G.nodeIds()) {
     334         310 :       unsigned VReg = G.getNodeMetadata(NId).getVReg();
     335         155 :       LiveInterval &LI = LIS.getInterval(VReg);
     336             :       assert(!LI.empty() && "PBQP graph contains node for empty interval");
     337         465 :       Inactive.push(std::make_tuple(&LI, 0, NId));
     338             :     }
     339             : 
     340         346 :     while (!Inactive.empty()) {
     341             :       // Tentatively grab the "next" interval - this choice may be overriden
     342             :       // below.
     343         169 :       IntervalInfo Cur = Inactive.top();
     344             : 
     345             :       // Retire any active intervals that end before Cur starts.
     346         169 :       IntervalSet::iterator RetireItr = Active.begin();
     347         606 :       while (RetireItr != Active.end() &&
     348        1172 :              (getEndPoint(*RetireItr) <= getStartPoint(Cur))) {
     349             :         // If this interval has subsequent segments, add the next one to the
     350             :         // inactive list.
     351         288 :         if (!isAtLastSegment(*RetireItr))
     352          28 :           Inactive.push(nextSegment(*RetireItr));
     353             : 
     354             :         ++RetireItr;
     355             :       }
     356         338 :       Active.erase(Active.begin(), RetireItr);
     357             : 
     358             :       // One of the newly retired segments may actually start before the
     359             :       // Cur segment, so re-grab the front of the inactive list.
     360         338 :       Cur = Inactive.top();
     361         169 :       Inactive.pop();
     362             : 
     363             :       // At this point we know that Cur overlaps all active intervals. Add the
     364             :       // interference edges.
     365         169 :       PBQP::GraphBase::NodeId NId = getNodeId(Cur);
     366        2824 :       for (const auto &A : Active) {
     367        1074 :         PBQP::GraphBase::NodeId MId = getNodeId(A);
     368             : 
     369             :         // Do not add an edge when the nodes' allowed registers do not
     370             :         // intersect: there is obviously no interference.
     371        1074 :         if (haveDisjointAllowedRegs(G, NId, MId, D))
     372        1000 :           continue;
     373             : 
     374             :         // Check that we haven't already added this edge
     375        1794 :         IEdgeKey EK(std::min(NId, MId), std::max(NId, MId));
     376         598 :         if (EC.count(EK))
     377          48 :           continue;
     378             : 
     379             :         // This is a new edge - add it to the graph.
     380         550 :         if (!createInterferenceEdge(G, NId, MId, C))
     381          14 :           setDisjointAllowedRegs(G, NId, MId, D);
     382             :         else
     383         536 :           EC.insert(EK);
     384             :       }
     385             : 
     386             :       // Finally, add Cur to the Active set.
     387         169 :       Active.insert(Cur);
     388             :     }
     389           8 :   }
     390             : 
     391             : private:
     392             :   // Create an Interference edge and add it to the graph, unless it is
     393             :   // a null matrix, meaning the nodes' allowed registers do not have any
     394             :   // interference. This case occurs frequently between integer and floating
     395             :   // point registers for example.
     396             :   // return true iff both nodes interferes.
     397         550 :   bool createInterferenceEdge(PBQPRAGraph &G,
     398             :                               PBQPRAGraph::NodeId NId, PBQPRAGraph::NodeId MId,
     399             :                               IMatrixCache &C) {
     400             :     const TargetRegisterInfo &TRI =
     401         550 :         *G.getMetadata().MF.getSubtarget().getRegisterInfo();
     402        1650 :     const auto &NRegs = G.getNodeMetadata(NId).getAllowedRegs();
     403        1650 :     const auto &MRegs = G.getNodeMetadata(MId).getAllowedRegs();
     404             : 
     405             :     // Try looking the edge costs up in the IMatrixCache first.
     406        1100 :     IKey K(&NRegs, &MRegs);
     407         550 :     IMatrixCache::iterator I = C.find(K);
     408        1100 :     if (I != C.end()) {
     409        1488 :       G.addEdgeBypassingCostAllocator(NId, MId, I->second);
     410             :       return true;
     411             :     }
     412             : 
     413          54 :     PBQPRAGraph::RawMatrix M(NRegs.size() + 1, MRegs.size() + 1, 0);
     414             :     bool NodesInterfere = false;
     415        3054 :     for (unsigned I = 0; I != NRegs.size(); ++I) {
     416        3000 :       unsigned PRegN = NRegs[I];
     417       41868 :       for (unsigned J = 0; J != MRegs.size(); ++J) {
     418       80736 :         unsigned PRegM = MRegs[J];
     419       40368 :         if (TRI.regsOverlap(PRegN, PRegM)) {
     420        1928 :           M[I + 1][J + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
     421         964 :           NodesInterfere = true;
     422             :         }
     423             :       }
     424             :     }
     425             : 
     426          54 :     if (!NodesInterfere)
     427             :       return false;
     428             : 
     429         120 :     PBQPRAGraph::EdgeId EId = G.addEdge(NId, MId, std::move(M));
     430         160 :     C[K] = G.getEdgeCostsPtr(EId);
     431             : 
     432             :     return true;
     433             :   }
     434             : };
     435             : 
     436          10 : class Coalescing : public PBQPRAConstraint {
     437             : public:
     438           5 :   void apply(PBQPRAGraph &G) override {
     439           5 :     MachineFunction &MF = G.getMetadata().MF;
     440           5 :     MachineBlockFrequencyInfo &MBFI = G.getMetadata().MBFI;
     441          10 :     CoalescerPair CP(*MF.getSubtarget().getRegisterInfo());
     442             : 
     443             :     // Scan the machine function and add a coalescing cost whenever CoalescerPair
     444             :     // gives the Ok.
     445          23 :     for (const auto &MBB : MF) {
     446         362 :       for (const auto &MI : MBB) {
     447             :         // Skip not-coalescable or already coalesced copies.
     448         165 :         if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
     449         139 :           continue;
     450             : 
     451          26 :         unsigned DstReg = CP.getDstReg();
     452          26 :         unsigned SrcReg = CP.getSrcReg();
     453             : 
     454          26 :         const float Scale = 1.0f / MBFI.getEntryFreq();
     455          52 :         PBQP::PBQPNum CBenefit = MBFI.getBlockFreq(&MBB).getFrequency() * Scale;
     456             : 
     457          26 :         if (CP.isPhys()) {
     458          22 :           if (!MF.getRegInfo().isAllocatable(DstReg))
     459           0 :             continue;
     460             : 
     461          44 :           PBQPRAGraph::NodeId NId = G.getMetadata().getNodeIdForVReg(SrcReg);
     462             : 
     463             :           const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed =
     464          66 :             G.getNodeMetadata(NId).getAllowedRegs();
     465             : 
     466          22 :           unsigned PRegOpt = 0;
     467        1249 :           while (PRegOpt < Allowed.size() && Allowed[PRegOpt] != DstReg)
     468         402 :             ++PRegOpt;
     469             : 
     470          22 :           if (PRegOpt < Allowed.size()) {
     471          63 :             PBQPRAGraph::RawVector NewCosts(G.getNodeCosts(NId));
     472          42 :             NewCosts[PRegOpt + 1] -= CBenefit;
     473          63 :             G.setNodeCosts(NId, std::move(NewCosts));
     474             :           }
     475             :         } else {
     476           8 :           PBQPRAGraph::NodeId N1Id = G.getMetadata().getNodeIdForVReg(DstReg);
     477           8 :           PBQPRAGraph::NodeId N2Id = G.getMetadata().getNodeIdForVReg(SrcReg);
     478             :           const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed1 =
     479          12 :             &G.getNodeMetadata(N1Id).getAllowedRegs();
     480             :           const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed2 =
     481          12 :             &G.getNodeMetadata(N2Id).getAllowedRegs();
     482             : 
     483           8 :           PBQPRAGraph::EdgeId EId = G.findEdge(N1Id, N2Id);
     484           4 :           if (EId == G.invalidEdgeId()) {
     485           0 :             PBQPRAGraph::RawMatrix Costs(Allowed1->size() + 1,
     486           0 :                                          Allowed2->size() + 1, 0);
     487           0 :             addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
     488           0 :             G.addEdge(N1Id, N2Id, std::move(Costs));
     489             :           } else {
     490           8 :             if (G.getEdgeNode1Id(EId) == N2Id) {
     491           0 :               std::swap(N1Id, N2Id);
     492             :               std::swap(Allowed1, Allowed2);
     493             :             }
     494          12 :             PBQPRAGraph::RawMatrix Costs(G.getEdgeCosts(EId));
     495           4 :             addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
     496          12 :             G.updateEdgeCosts(EId, std::move(Costs));
     497             :           }
     498             :         }
     499             :       }
     500             :     }
     501           5 :   }
     502             : 
     503             : private:
     504           4 :   void addVirtRegCoalesce(
     505             :                     PBQPRAGraph::RawMatrix &CostMat,
     506             :                     const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed1,
     507             :                     const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed2,
     508             :                     PBQP::PBQPNum Benefit) {
     509             :     assert(CostMat.getRows() == Allowed1.size() + 1 && "Size mismatch.");
     510             :     assert(CostMat.getCols() == Allowed2.size() + 1 && "Size mismatch.");
     511         131 :     for (unsigned I = 0; I != Allowed1.size(); ++I) {
     512         254 :       unsigned PReg1 = Allowed1[I];
     513        4160 :       for (unsigned J = 0; J != Allowed2.size(); ++J) {
     514        8066 :         unsigned PReg2 = Allowed2[J];
     515        4033 :         if (PReg1 == PReg2)
     516         254 :           CostMat[I + 1][J + 1] -= Benefit;
     517             :       }
     518             :     }
     519           4 :   }
     520             : };
     521             : 
     522             : } // end anonymous namespace
     523             : 
     524             : // Out-of-line destructor/anchor for PBQPRAConstraint.
     525             : PBQPRAConstraint::~PBQPRAConstraint() = default;
     526             : 
     527           0 : void PBQPRAConstraint::anchor() {}
     528             : 
     529           0 : void PBQPRAConstraintList::anchor() {}
     530             : 
     531           7 : void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
     532           7 :   au.setPreservesCFG();
     533           7 :   au.addRequired<AAResultsWrapperPass>();
     534           7 :   au.addPreserved<AAResultsWrapperPass>();
     535           7 :   au.addRequired<SlotIndexes>();
     536           7 :   au.addPreserved<SlotIndexes>();
     537           7 :   au.addRequired<LiveIntervals>();
     538           7 :   au.addPreserved<LiveIntervals>();
     539             :   //au.addRequiredID(SplitCriticalEdgesID);
     540           7 :   if (customPassID)
     541           0 :     au.addRequiredID(*customPassID);
     542           7 :   au.addRequired<LiveStacks>();
     543           7 :   au.addPreserved<LiveStacks>();
     544           7 :   au.addRequired<MachineBlockFrequencyInfo>();
     545           7 :   au.addPreserved<MachineBlockFrequencyInfo>();
     546           7 :   au.addRequired<MachineLoopInfo>();
     547           7 :   au.addPreserved<MachineLoopInfo>();
     548           7 :   au.addRequired<MachineDominatorTree>();
     549           7 :   au.addPreserved<MachineDominatorTree>();
     550           7 :   au.addRequired<VirtRegMap>();
     551           7 :   au.addPreserved<VirtRegMap>();
     552           7 :   MachineFunctionPass::getAnalysisUsage(au);
     553           7 : }
     554             : 
     555           7 : void RegAllocPBQP::findVRegIntervalsToAlloc(const MachineFunction &MF,
     556             :                                             LiveIntervals &LIS) {
     557           7 :   const MachineRegisterInfo &MRI = MF.getRegInfo();
     558             : 
     559             :   // Iterate over all live ranges.
     560         224 :   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
     561         210 :     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
     562         210 :     if (MRI.reg_nodbg_empty(Reg))
     563          65 :       continue;
     564         145 :     LiveInterval &LI = LIS.getInterval(Reg);
     565             : 
     566             :     // If this live interval is non-empty we will use pbqp to allocate it.
     567             :     // Empty intervals we allocate in a simple post-processing stage in
     568             :     // finalizeAlloc.
     569         290 :     if (!LI.empty()) {
     570         143 :       VRegsToAlloc.insert(LI.reg);
     571             :     } else {
     572           2 :       EmptyIntervalVRegs.insert(LI.reg);
     573             :     }
     574             :   }
     575           7 : }
     576             : 
     577        4144 : static bool isACalleeSavedRegister(unsigned reg, const TargetRegisterInfo &TRI,
     578             :                                    const MachineFunction &MF) {
     579        4144 :   const MCPhysReg *CSR = MF.getRegInfo().getCalleeSavedRegs();
     580       74100 :   for (unsigned i = 0; CSR[i] != 0; ++i)
     581       71252 :     if (TRI.regsOverlap(reg, CSR[i]))
     582             :       return true;
     583             :   return false;
     584             : }
     585             : 
     586           8 : void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM,
     587             :                                    Spiller &VRegSpiller) {
     588           8 :   MachineFunction &MF = G.getMetadata().MF;
     589             : 
     590           8 :   LiveIntervals &LIS = G.getMetadata().LIS;
     591           8 :   const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
     592             :   const TargetRegisterInfo &TRI =
     593           8 :       *G.getMetadata().MF.getSubtarget().getRegisterInfo();
     594             : 
     595          40 :   std::vector<unsigned> Worklist(VRegsToAlloc.begin(), VRegsToAlloc.end());
     596             : 
     597         163 :   while (!Worklist.empty()) {
     598         155 :     unsigned VReg = Worklist.back();
     599         310 :     Worklist.pop_back();
     600             : 
     601             :     const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
     602         155 :     LiveInterval &VRegLI = LIS.getInterval(VReg);
     603             : 
     604             :     // Record any overlaps with regmask operands.
     605         310 :     BitVector RegMaskOverlaps;
     606         155 :     LIS.checkRegMaskInterference(VRegLI, RegMaskOverlaps);
     607             : 
     608             :     // Compute an initial allowed set for the current vreg.
     609         310 :     std::vector<unsigned> VRegAllowed;
     610         155 :     ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
     611        4625 :     for (unsigned I = 0; I != RawPRegOrder.size(); ++I) {
     612        8940 :       unsigned PReg = RawPRegOrder[I];
     613        8940 :       if (MRI.isReserved(PReg))
     614         399 :         continue;
     615             : 
     616             :       // vregLI crosses a regmask operand that clobbers preg.
     617        4758 :       if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg))
     618         217 :         continue;
     619             : 
     620             :       // vregLI overlaps fixed regunit interference.
     621        4180 :       bool Interference = false;
     622       12554 :       for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
     623        8642 :         if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
     624             :           Interference = true;
     625             :           break;
     626             :         }
     627             :       }
     628        4180 :       if (Interference)
     629          36 :         continue;
     630             : 
     631             :       // preg is usable for this virtual register.
     632        4144 :       VRegAllowed.push_back(PReg);
     633             :     }
     634             : 
     635             :     // Check for vregs that have no allowed registers. These should be
     636             :     // pre-spilled and the new vregs added to the worklist.
     637         155 :     if (VRegAllowed.empty()) {
     638           0 :       SmallVector<unsigned, 8> NewVRegs;
     639           0 :       spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
     640           0 :       Worklist.insert(Worklist.end(), NewVRegs.begin(), NewVRegs.end());
     641             :       continue;
     642             :     }
     643             : 
     644         465 :     PBQPRAGraph::RawVector NodeCosts(VRegAllowed.size() + 1, 0);
     645             : 
     646             :     // Tweak cost of callee saved registers, as using then force spilling and
     647             :     // restoring them. This would only happen in the prologue / epilogue though.
     648       12742 :     for (unsigned i = 0; i != VRegAllowed.size(); ++i)
     649        8288 :       if (isACalleeSavedRegister(VRegAllowed[i], TRI, MF))
     650        2592 :         NodeCosts[1 + i] += 1.0;
     651             : 
     652         465 :     PBQPRAGraph::NodeId NId = G.addNode(std::move(NodeCosts));
     653         465 :     G.getNodeMetadata(NId).setVReg(VReg);
     654         465 :     G.getNodeMetadata(NId).setAllowedRegs(
     655         620 :       G.getMetadata().getAllowedRegs(std::move(VRegAllowed)));
     656         310 :     G.getMetadata().setNodeIdForVReg(VReg, NId);
     657             :   }
     658           8 : }
     659             : 
     660          10 : void RegAllocPBQP::spillVReg(unsigned VReg,
     661             :                              SmallVectorImpl<unsigned> &NewIntervals,
     662             :                              MachineFunction &MF, LiveIntervals &LIS,
     663             :                              VirtRegMap &VRM, Spiller &VRegSpiller) {
     664          20 :   VRegsToAlloc.erase(VReg);
     665          10 :   LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM,
     666          30 :                     nullptr, &DeadRemats);
     667          10 :   VRegSpiller.spill(LRE);
     668             : 
     669          10 :   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
     670             :   (void)TRI;
     671             :   DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: "
     672             :                << LRE.getParent().weight << ", New vregs: ");
     673             : 
     674             :   // Copy any newly inserted live intervals into the list of regs to
     675             :   // allocate.
     676          34 :   for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end();
     677          14 :        I != E; ++I) {
     678           4 :     const LiveInterval &LI = LIS.getInterval(*I);
     679             :     assert(!LI.empty() && "Empty spill range.");
     680             :     DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " ");
     681           8 :     VRegsToAlloc.insert(LI.reg);
     682             :   }
     683             : 
     684             :   DEBUG(dbgs() << ")\n");
     685          10 : }
     686             : 
     687           8 : bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
     688             :                                      const PBQP::Solution &Solution,
     689             :                                      VirtRegMap &VRM,
     690             :                                      Spiller &VRegSpiller) {
     691           8 :   MachineFunction &MF = G.getMetadata().MF;
     692           8 :   LiveIntervals &LIS = G.getMetadata().LIS;
     693           8 :   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
     694             :   (void)TRI;
     695             : 
     696             :   // Set to true if we have any spills
     697           8 :   bool AnotherRoundNeeded = false;
     698             : 
     699             :   // Clear the existing allocation.
     700           8 :   VRM.clearAllVirt();
     701             : 
     702             :   // Iterate over the nodes mapping the PBQP solution to a register
     703             :   // assignment.
     704         179 :   for (auto NId : G.nodeIds()) {
     705         310 :     unsigned VReg = G.getNodeMetadata(NId).getVReg();
     706         155 :     unsigned AllocOption = Solution.getSelection(NId);
     707             : 
     708         155 :     if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) {
     709         580 :       unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1];
     710             :       DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> "
     711             :             << TRI.getName(PReg) << "\n");
     712             :       assert(PReg != 0 && "Invalid preg selected.");
     713         145 :       VRM.assignVirt2Phys(VReg, PReg);
     714             :     } else {
     715             :       // Spill VReg. If this introduces new intervals we'll need another round
     716             :       // of allocation.
     717          20 :       SmallVector<unsigned, 8> NewVRegs;
     718          10 :       spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
     719          10 :       AnotherRoundNeeded |= !NewVRegs.empty();
     720             :     }
     721             :   }
     722             : 
     723           8 :   return !AnotherRoundNeeded;
     724             : }
     725             : 
     726           7 : void RegAllocPBQP::finalizeAlloc(MachineFunction &MF,
     727             :                                  LiveIntervals &LIS,
     728             :                                  VirtRegMap &VRM) const {
     729           7 :   MachineRegisterInfo &MRI = MF.getRegInfo();
     730             : 
     731             :   // First allocate registers for the empty intervals.
     732             :   for (RegSet::const_iterator
     733          21 :          I = EmptyIntervalVRegs.begin(), E = EmptyIntervalVRegs.end();
     734           9 :          I != E; ++I) {
     735           2 :     LiveInterval &LI = LIS.getInterval(*I);
     736             : 
     737           4 :     unsigned PReg = MRI.getSimpleHint(LI.reg);
     738             : 
     739           2 :     if (PReg == 0) {
     740           4 :       const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
     741           2 :       const ArrayRef<MCPhysReg> RawPRegOrder = RC.getRawAllocationOrder(MF);
     742           6 :       for (unsigned CandidateReg : RawPRegOrder) {
     743           8 :         if (!VRM.getRegInfo().isReserved(CandidateReg)) {
     744             :           PReg = CandidateReg;
     745             :           break;
     746             :         }
     747             :       }
     748             :       assert(PReg &&
     749             :              "No un-reserved physical registers in this register class");
     750             :     }
     751             : 
     752           2 :     VRM.assignVirt2Phys(LI.reg, PReg);
     753             :   }
     754           7 : }
     755             : 
     756           7 : void RegAllocPBQP::postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS) {
     757           7 :   VRegSpiller.postOptimization();
     758             :   /// Remove dead defs because of rematerialization.
     759           7 :   for (auto DeadInst : DeadRemats) {
     760           0 :     LIS.RemoveMachineInstrFromMaps(*DeadInst);
     761           0 :     DeadInst->eraseFromParent();
     762             :   }
     763           7 :   DeadRemats.clear();
     764           7 : }
     765             : 
     766         134 : static inline float normalizePBQPSpillWeight(float UseDefFreq, unsigned Size,
     767             :                                          unsigned NumInstr) {
     768             :   // All intervals have a spill weight that is mostly proportional to the number
     769             :   // of uses, with uses in loops having a bigger weight.
     770         268 :   return NumInstr * normalizeSpillWeight(UseDefFreq, Size, 1);
     771             : }
     772             : 
     773           7 : bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
     774           7 :   LiveIntervals &LIS = getAnalysis<LiveIntervals>();
     775             :   MachineBlockFrequencyInfo &MBFI =
     776           7 :     getAnalysis<MachineBlockFrequencyInfo>();
     777             : 
     778           7 :   VirtRegMap &VRM = getAnalysis<VirtRegMap>();
     779             : 
     780           7 :   calculateSpillWeightsAndHints(LIS, MF, &VRM, getAnalysis<MachineLoopInfo>(),
     781             :                                 MBFI, normalizePBQPSpillWeight);
     782             : 
     783          21 :   std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
     784             : 
     785           7 :   MF.getRegInfo().freezeReservedRegs(MF);
     786             : 
     787             :   DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
     788             : 
     789             :   // Allocator main loop:
     790             :   //
     791             :   // * Map current regalloc problem to a PBQP problem
     792             :   // * Solve the PBQP problem
     793             :   // * Map the solution back to a register allocation
     794             :   // * Spill if necessary
     795             :   //
     796             :   // This process is continued till no more spills are generated.
     797             : 
     798             :   // Find the vreg intervals in need of allocation.
     799           7 :   findVRegIntervalsToAlloc(MF, LIS);
     800             : 
     801             : #ifndef NDEBUG
     802             :   const Function &F = *MF.getFunction();
     803             :   std::string FullyQualifiedName =
     804             :     F.getParent()->getModuleIdentifier() + "." + F.getName().str();
     805             : #endif
     806             : 
     807             :   // If there are non-empty intervals allocate them using pbqp.
     808          14 :   if (!VRegsToAlloc.empty()) {
     809           7 :     const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
     810             :     std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
     811          14 :       llvm::make_unique<PBQPRAConstraintList>();
     812          42 :     ConstraintsRoot->addConstraint(llvm::make_unique<SpillCosts>());
     813          42 :     ConstraintsRoot->addConstraint(llvm::make_unique<Interference>());
     814           7 :     if (PBQPCoalescing)
     815          30 :       ConstraintsRoot->addConstraint(llvm::make_unique<Coalescing>());
     816          21 :     ConstraintsRoot->addConstraint(Subtarget.getCustomPBQPConstraints());
     817             : 
     818           7 :     bool PBQPAllocComplete = false;
     819           7 :     unsigned Round = 0;
     820             : 
     821          23 :     while (!PBQPAllocComplete) {
     822             :       DEBUG(dbgs() << "  PBQP Regalloc round " << Round << ":\n");
     823             : 
     824          24 :       PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
     825           8 :       initializeGraph(G, VRM, *VRegSpiller);
     826           8 :       ConstraintsRoot->apply(G);
     827             : 
     828             : #ifndef NDEBUG
     829             :       if (PBQPDumpGraphs) {
     830             :         std::ostringstream RS;
     831             :         RS << Round;
     832             :         std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
     833             :                                     ".pbqpgraph";
     834             :         std::error_code EC;
     835             :         raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text);
     836             :         DEBUG(dbgs() << "Dumping graph for round " << Round << " to \""
     837             :               << GraphFileName << "\"\n");
     838             :         G.dump(OS);
     839             :       }
     840             : #endif
     841             : 
     842          16 :       PBQP::Solution Solution = PBQP::RegAlloc::solve(G);
     843           8 :       PBQPAllocComplete = mapPBQPToRegAlloc(G, Solution, VRM, *VRegSpiller);
     844           8 :       ++Round;
     845             :     }
     846             :   }
     847             : 
     848             :   // Finalise allocation, allocate empty ranges.
     849           7 :   finalizeAlloc(MF, LIS, VRM);
     850           7 :   postOptimization(*VRegSpiller, LIS);
     851          14 :   VRegsToAlloc.clear();
     852          14 :   EmptyIntervalVRegs.clear();
     853             : 
     854             :   DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n");
     855             : 
     856          14 :   return true;
     857             : }
     858             : 
     859             : /// Create Printable object for node and register info.
     860             : static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId,
     861             :                                const PBQP::RegAlloc::PBQPRAGraph &G) {
     862           0 :   return Printable([NId, &G](raw_ostream &OS) {
     863           0 :     const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
     864           0 :     const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
     865           0 :     unsigned VReg = G.getNodeMetadata(NId).getVReg();
     866           0 :     const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
     867           0 :     OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')';
     868           0 :   });
     869             : }
     870             : 
     871             : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     872             : LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const {
     873             :   for (auto NId : nodeIds()) {
     874             :     const Vector &Costs = getNodeCosts(NId);
     875             :     assert(Costs.getLength() != 0 && "Empty vector in graph.");
     876             :     OS << PrintNodeInfo(NId, *this) << ": " << Costs << '\n';
     877             :   }
     878             :   OS << '\n';
     879             : 
     880             :   for (auto EId : edgeIds()) {
     881             :     NodeId N1Id = getEdgeNode1Id(EId);
     882             :     NodeId N2Id = getEdgeNode2Id(EId);
     883             :     assert(N1Id != N2Id && "PBQP graphs should not have self-edges.");
     884             :     const Matrix &M = getEdgeCosts(EId);
     885             :     assert(M.getRows() != 0 && "No rows in matrix.");
     886             :     assert(M.getCols() != 0 && "No cols in matrix.");
     887             :     OS << PrintNodeInfo(N1Id, *this) << ' ' << M.getRows() << " rows / ";
     888             :     OS << PrintNodeInfo(N2Id, *this) << ' ' << M.getCols() << " cols:\n";
     889             :     OS << M << '\n';
     890             :   }
     891             : }
     892             : 
     893             : LLVM_DUMP_METHOD void PBQP::RegAlloc::PBQPRAGraph::dump() const {
     894             :   dump(dbgs());
     895             : }
     896             : #endif
     897             : 
     898           0 : void PBQP::RegAlloc::PBQPRAGraph::printDot(raw_ostream &OS) const {
     899           0 :   OS << "graph {\n";
     900           0 :   for (auto NId : nodeIds()) {
     901           0 :     OS << "  node" << NId << " [ label=\""
     902           0 :        << PrintNodeInfo(NId, *this) << "\\n"
     903           0 :        << getNodeCosts(NId) << "\" ]\n";
     904             :   }
     905             : 
     906           0 :   OS << "  edge [ len=" << nodeIds().size() << " ]\n";
     907           0 :   for (auto EId : edgeIds()) {
     908           0 :     OS << "  node" << getEdgeNode1Id(EId)
     909           0 :        << " -- node" << getEdgeNode2Id(EId)
     910           0 :        << " [ label=\"";
     911           0 :     const Matrix &EdgeCosts = getEdgeCosts(EId);
     912           0 :     for (unsigned i = 0; i < EdgeCosts.getRows(); ++i) {
     913           0 :       OS << EdgeCosts.getRowAsVector(i) << "\\n";
     914             :     }
     915           0 :     OS << "\" ]\n";
     916             :   }
     917           0 :   OS << "}\n";
     918           0 : }
     919             : 
     920           7 : FunctionPass *llvm::createPBQPRegisterAllocator(char *customPassID) {
     921           7 :   return new RegAllocPBQP(customPassID);
     922             : }
     923             : 
     924           7 : FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
     925           7 :   return createPBQPRegisterAllocator();
     926      216918 : }

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