LCOV - code coverage report
Current view: top level - lib/CodeGen - RegUsageInfoCollector.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 56 56 100.0 %
Date: 2018-06-17 00:07:59 Functions: 9 10 90.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : ///
      10             : /// This pass is required to take advantage of the interprocedural register
      11             : /// allocation infrastructure.
      12             : ///
      13             : /// This pass is simple MachineFunction pass which collects register usage
      14             : /// details by iterating through each physical registers and checking
      15             : /// MRI::isPhysRegUsed() then creates a RegMask based on this details.
      16             : /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
      17             : ///
      18             : //===----------------------------------------------------------------------===//
      19             : 
      20             : #include "llvm/ADT/Statistic.h"
      21             : #include "llvm/CodeGen/MachineBasicBlock.h"
      22             : #include "llvm/CodeGen/MachineFunctionPass.h"
      23             : #include "llvm/CodeGen/MachineInstr.h"
      24             : #include "llvm/CodeGen/MachineOperand.h"
      25             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      26             : #include "llvm/CodeGen/Passes.h"
      27             : #include "llvm/CodeGen/RegisterUsageInfo.h"
      28             : #include "llvm/Support/Debug.h"
      29             : #include "llvm/Support/raw_ostream.h"
      30             : #include "llvm/CodeGen/TargetFrameLowering.h"
      31             : 
      32             : using namespace llvm;
      33             : 
      34             : #define DEBUG_TYPE "ip-regalloc"
      35             : 
      36             : STATISTIC(NumCSROpt,
      37             :           "Number of functions optimized for callee saved registers");
      38             : 
      39             : namespace llvm {
      40             : void initializeRegUsageInfoCollectorPass(PassRegistry &);
      41             : }
      42             : 
      43             : namespace {
      44        1779 : class RegUsageInfoCollector : public MachineFunctionPass {
      45             : public:
      46        1787 :   RegUsageInfoCollector() : MachineFunctionPass(ID) {
      47        1787 :     PassRegistry &Registry = *PassRegistry::getPassRegistry();
      48        1787 :     initializeRegUsageInfoCollectorPass(Registry);
      49        1787 :   }
      50             : 
      51        1776 :   StringRef getPassName() const override {
      52        1776 :     return "Register Usage Information Collector Pass";
      53             :   }
      54             : 
      55             :   void getAnalysisUsage(AnalysisUsage &AU) const override;
      56             : 
      57             :   bool runOnMachineFunction(MachineFunction &MF) override;
      58             : 
      59             :   // Call determineCalleeSaves and then also set the bits for subregs and
      60             :   // fully saved superregs.
      61             :   static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
      62             : 
      63             :   static char ID;
      64             : };
      65             : } // end of anonymous namespace
      66             : 
      67             : char RegUsageInfoCollector::ID = 0;
      68             : 
      69        1787 : INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector",
      70             :                       "Register Usage Information Collector", false, false)
      71        1787 : INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo)
      72        7148 : INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector",
      73             :                     "Register Usage Information Collector", false, false)
      74             : 
      75        1787 : FunctionPass *llvm::createRegUsageInfoCollector() {
      76        1787 :   return new RegUsageInfoCollector();
      77             : }
      78             : 
      79        1776 : void RegUsageInfoCollector::getAnalysisUsage(AnalysisUsage &AU) const {
      80             :   AU.addRequired<PhysicalRegisterUsageInfo>();
      81             :   AU.setPreservesAll();
      82        1776 :   MachineFunctionPass::getAnalysisUsage(AU);
      83        1776 : }
      84             : 
      85       17577 : bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
      86       17577 :   MachineRegisterInfo *MRI = &MF.getRegInfo();
      87       17577 :   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
      88       17577 :   const TargetMachine &TM = MF.getTarget();
      89             : 
      90             :   LLVM_DEBUG(dbgs() << " -------------------- " << getPassName()
      91             :                     << " -------------------- \n");
      92             :   LLVM_DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
      93             : 
      94             :   std::vector<uint32_t> RegMask;
      95             : 
      96             :   // Compute the size of the bit vector to represent all the registers.
      97             :   // The bit vector is broken into 32-bit chunks, thus takes the ceil of
      98             :   // the number of registers divided by 32 for the size.
      99       17577 :   unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
     100       17577 :   RegMask.resize(RegMaskSize, 0xFFFFFFFF);
     101             : 
     102       17577 :   const Function &F = MF.getFunction();
     103             : 
     104       17577 :   PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
     105             : 
     106             :   PRUI->setTargetMachine(&TM);
     107             : 
     108             :   LLVM_DEBUG(dbgs() << "Clobbered Registers: ");
     109             : 
     110             :   BitVector SavedRegs;
     111       17577 :   computeCalleeSavedRegs(SavedRegs, MF);
     112             : 
     113             :   const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask();
     114             :   auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
     115     5845478 :     RegMask[Reg / 32] &= ~(1u << Reg % 32);
     116             :   };
     117             :   // Scan all the physical registers. When a register is defined in the current
     118             :   // function set it and all the aliasing registers as defined in the regmask.
     119    62235690 :   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
     120             :     // Don't count registers that are saved and restored.
     121    62218113 :     if (SavedRegs.test(PReg))
     122         500 :       continue;
     123             :     // If a register is defined by an instruction mark it as defined together
     124             :     // with all it's unsaved aliases.
     125    62217613 :     if (!MRI->def_empty(PReg)) {
     126     5239016 :       for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
     127     2453270 :         if (!SavedRegs.test(*AI))
     128             :           SetRegAsDefined(*AI);
     129      166238 :       continue;
     130             :     }
     131             :     // If a register is in the UsedPhysRegsMask set then mark it as defined.
     132             :     // All clobbered aliases will also be in the set, so we can skip setting
     133             :     // as defined all the aliases here.
     134    62051375 :     if (UsedPhysRegsMask.test(PReg))
     135             :       SetRegAsDefined(PReg);
     136             :   }
     137             : 
     138       17577 :   if (TargetFrameLowering::isSafeForNoCSROpt(F)) {
     139             :     ++NumCSROpt;
     140             :     LLVM_DEBUG(dbgs() << MF.getName()
     141             :                       << " function optimized for not having CSR.\n");
     142             :   }
     143             : 
     144             :   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
     145             :     if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
     146             :       LLVM_DEBUG(dbgs() << printReg(PReg, TRI) << " ");
     147             : 
     148             :   LLVM_DEBUG(dbgs() << " \n----------------------------------------\n");
     149             : 
     150       35154 :   PRUI->storeUpdateRegUsageInfo(&F, std::move(RegMask));
     151             : 
     152       17577 :   return false;
     153             : }
     154             : 
     155       17577 : void RegUsageInfoCollector::
     156             : computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
     157       17577 :   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
     158       17577 :   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
     159             : 
     160             :   // Target will return the set of registers that it saves/restores as needed.
     161             :   SavedRegs.clear();
     162       17577 :   TFI->determineCalleeSaves(MF, SavedRegs);
     163             : 
     164             :   // Insert subregs.
     165       17577 :   const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
     166      740133 :   for (unsigned i = 0; CSRegs[i]; ++i) {
     167      361278 :     unsigned Reg = CSRegs[i];
     168      361278 :     if (SavedRegs.test(Reg))
     169         603 :       for (MCSubRegIterator SR(Reg, TRI, false); SR.isValid(); ++SR)
     170             :         SavedRegs.set(*SR);
     171             :   }
     172             : 
     173             :   // Insert any register fully saved via subregisters.
     174    62235690 :   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
     175    62218113 :     if (SavedRegs.test(PReg))
     176         327 :       continue;
     177             : 
     178             :     // Check if PReg is fully covered by its subregs.
     179             :     bool CoveredBySubRegs = false;
     180  7956711354 :     for (const TargetRegisterClass *RC : TRI->regclasses())
     181  4638446652 :       if (RC->CoveredBySubRegs && RC->contains(PReg)) {
     182             :         CoveredBySubRegs = true;
     183             :         break;
     184             :       }
     185    62217786 :     if (!CoveredBySubRegs)
     186    37731986 :       continue;
     187             : 
     188             :     // Add PReg to SavedRegs if all subregs are saved.
     189             :     bool AllSubRegsSaved = true;
     190    48973985 :     for (MCSubRegIterator SR(PReg, TRI, false); SR.isValid(); ++SR)
     191    24488012 :       if (!SavedRegs.test(*SR)) {
     192             :         AllSubRegsSaved = false;
     193             :         break;
     194             :       }
     195    24485800 :     if (AllSubRegsSaved)
     196             :       SavedRegs.set(PReg);
     197             :   }
     198       17577 : }

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