LCOV - code coverage report
Current view: top level - lib/CodeGen - RegisterClassInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 84 84 100.0 %
Date: 2017-09-14 15:23:50 Functions: 5 5 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the RegisterClassInfo class which provides dynamic
      11             : // information about target register classes. Callee-saved vs. caller-saved and
      12             : // reserved registers depend on calling conventions and other dynamic
      13             : // information, so some things cannot be determined statically.
      14             : //
      15             : //===----------------------------------------------------------------------===//
      16             : 
      17             : #include "llvm/CodeGen/RegisterClassInfo.h"
      18             : #include "llvm/ADT/ArrayRef.h"
      19             : #include "llvm/ADT/BitVector.h"
      20             : #include "llvm/ADT/SmallVector.h"
      21             : #include "llvm/CodeGen/MachineFunction.h"
      22             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      23             : #include "llvm/MC/MCRegisterInfo.h"
      24             : #include "llvm/Support/CommandLine.h"
      25             : #include "llvm/Support/Debug.h"
      26             : #include "llvm/Support/raw_ostream.h"
      27             : #include "llvm/Target/TargetFrameLowering.h"
      28             : #include "llvm/Target/TargetRegisterInfo.h"
      29             : #include "llvm/Target/TargetSubtargetInfo.h"
      30             : #include <algorithm>
      31             : #include <cassert>
      32             : #include <cstdint>
      33             : 
      34             : using namespace llvm;
      35             : 
      36             : #define DEBUG_TYPE "regalloc"
      37             : 
      38             : static cl::opt<unsigned>
      39      361530 : StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
      40      289224 :          cl::desc("Limit all regclasses to N registers"));
      41             : 
      42             : RegisterClassInfo::RegisterClassInfo() = default;
      43             : 
      44      761406 : void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
      45      761406 :   bool Update = false;
      46      761406 :   MF = &mf;
      47             : 
      48             :   // Allocate new array the first time we see a new target.
      49      761406 :   if (MF->getSubtarget().getRegisterInfo() != TRI) {
      50       85338 :     TRI = MF->getSubtarget().getRegisterInfo();
      51     7211815 :     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
      52       85338 :     unsigned NumPSets = TRI->getNumRegPressureSets();
      53      170676 :     PSetLimits.reset(new unsigned[NumPSets]);
      54      256014 :     std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
      55             :     Update = true;
      56             :   }
      57             : 
      58             :   // Does this MF have different CSRs?
      59             :   assert(TRI && "no register info set");
      60             : 
      61             :   // Get the callee saved registers.
      62      761406 :   const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
      63      761406 :   if (Update || CSR != CalleeSavedRegs) {
      64             :     // Build a CSRAlias map. Every CSR alias saves the last
      65             :     // overlapping CSR.
      66       92031 :     CalleeSavedAliases.resize(TRI->getNumRegs(), 0);
      67     1558758 :     for (const MCPhysReg *I = CSR; *I; ++I)
      68    33141100 :       for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
      69    30207646 :         CalleeSavedAliases[*AI] = *I;
      70             : 
      71             :     Update = true;
      72             :   }
      73      761406 :   CalleeSavedRegs = CSR;
      74             : 
      75             :   // Different reserved registers?
      76     1522812 :   const BitVector &RR = MF->getRegInfo().getReservedRegs();
      77     1438654 :   if (Reserved.size() != RR.size() || RR != Reserved) {
      78       98937 :     Update = true;
      79       98937 :     Reserved = RR;
      80             :   }
      81             : 
      82             :   // Invalidate cached information from previous function.
      83      662469 :   if (Update)
      84      100834 :     ++Tag;
      85      761406 : }
      86             : 
      87             : /// compute - Compute the preferred allocation order for RC with reserved
      88             : /// registers filtered out. Volatile registers come first followed by CSR
      89             : /// aliases ordered according to the CSR order specified by the target.
      90      331518 : void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
      91             :   assert(RC && "no register class given");
      92      994554 :   RCInfo &RCI = RegClass[RC->getID()];
      93             : 
      94             :   // Raw register count, including all reserved regs.
      95      663036 :   unsigned NumRegs = RC->getNumRegs();
      96             : 
      97      663036 :   if (!RCI.Order)
      98      175049 :     RCI.Order.reset(new MCPhysReg[NumRegs]);
      99             : 
     100      331518 :   unsigned N = 0;
     101      663036 :   SmallVector<MCPhysReg, 16> CSRAlias;
     102      331518 :   unsigned MinCost = 0xff;
     103      331518 :   unsigned LastCost = ~0u;
     104      331518 :   unsigned LastCostChange = 0;
     105             : 
     106             :   // FIXME: Once targets reserve registers instead of removing them from the
     107             :   // allocation order, we can simply use begin/end here.
     108      663036 :   ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
     109    11925059 :   for (unsigned i = 0; i != RawOrder.size(); ++i) {
     110    23187082 :     unsigned PhysReg = RawOrder[i];
     111             :     // Remove reserved registers from the allocation order.
     112    23187082 :     if (Reserved.test(PhysReg))
     113     1439388 :       continue;
     114    20308306 :     unsigned Cost = TRI->getCostPerUse(PhysReg);
     115    10154153 :     MinCost = std::min(MinCost, Cost);
     116             : 
     117    20308306 :     if (CalleeSavedAliases[PhysReg])
     118             :       // PhysReg aliases a CSR, save it for later.
     119      836119 :       CSRAlias.push_back(PhysReg);
     120             :     else {
     121     9318034 :       if (Cost != LastCost)
     122      271826 :         LastCostChange = N;
     123    18636068 :       RCI.Order[N++] = PhysReg;
     124     9318034 :       LastCost = Cost;
     125             :     }
     126             :   }
     127      331518 :   RCI.NumRegs = N + CSRAlias.size();
     128             :   assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
     129             : 
     130             :   // CSR aliases go after the volatile registers, preserve the target's order.
     131     1499155 :   for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
     132     1672238 :     unsigned PhysReg = CSRAlias[i];
     133     1672238 :     unsigned Cost = TRI->getCostPerUse(PhysReg);
     134      836119 :     if (Cost != LastCost)
     135       90235 :       LastCostChange = N;
     136     1672238 :     RCI.Order[N++] = PhysReg;
     137      836119 :     LastCost = Cost;
     138             :   }
     139             : 
     140             :   // Register allocator stress test.  Clip register class to N registers.
     141      331593 :   if (StressRA && RCI.NumRegs > StressRA)
     142          68 :     RCI.NumRegs = StressRA;
     143             : 
     144             :   // Check if RC is a proper sub-class.
     145      331518 :   if (const TargetRegisterClass *Super =
     146      331518 :           TRI->getLargestLegalSuperClass(RC, *MF))
     147      331518 :     if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
     148       70936 :       RCI.ProperSubClass = true;
     149             : 
     150      331518 :   RCI.MinCost = uint8_t(MinCost);
     151      331518 :   RCI.LastCostChange = LastCostChange;
     152             : 
     153             :   DEBUG({
     154             :     dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
     155             :     for (unsigned I = 0; I != RCI.NumRegs; ++I)
     156             :       dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
     157             :     dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
     158             :   });
     159             : 
     160             :   // RCI is now up-to-date.
     161      331518 :   RCI.Tag = Tag;
     162      331518 : }
     163             : 
     164             : /// This is not accurate because two overlapping register sets may have some
     165             : /// nonoverlapping reserved registers. However, computing the allocation order
     166             : /// for all register classes would be too expensive.
     167      231134 : unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
     168      231134 :   const TargetRegisterClass *RC = nullptr;
     169      231134 :   unsigned NumRCUnits = 0;
     170    21286536 :   for (const TargetRegisterClass *C : TRI->regclasses()) {
     171    20824268 :     const int *PSetID = TRI->getRegClassPressureSets(C);
     172   198915218 :     for (; *PSetID != -1; ++PSetID) {
     173    90786701 :       if ((unsigned)*PSetID == Idx)
     174             :         break;
     175             :     }
     176    20824268 :     if (*PSetID == -1)
     177    19083042 :       continue;
     178             : 
     179             :     // Found a register class that counts against this pressure set.
     180             :     // For efficiency, only compute the set order for the largest set.
     181     1741226 :     unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
     182     1741226 :     if (!RC || NUnits > NumRCUnits) {
     183      267393 :       RC = C;
     184      267393 :       NumRCUnits = NUnits;
     185             :     }
     186             :   }
     187      231134 :   compute(RC);
     188      462268 :   unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
     189      231134 :   return TRI->getRegPressureSetLimit(*MF, Idx) -
     190      231134 :          TRI->getRegClassWeight(RC).RegWeight * NReserved;
     191      216918 : }

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