LCOV - code coverage report
Current view: top level - lib/CodeGen - RegisterClassInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 68 68 100.0 %
Date: 2018-06-17 00:07:59 Functions: 5 5 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the RegisterClassInfo class which provides dynamic
      11             : // information about target register classes. Callee-saved vs. caller-saved and
      12             : // reserved registers depend on calling conventions and other dynamic
      13             : // information, so some things cannot be determined statically.
      14             : //
      15             : //===----------------------------------------------------------------------===//
      16             : 
      17             : #include "llvm/CodeGen/RegisterClassInfo.h"
      18             : #include "llvm/ADT/ArrayRef.h"
      19             : #include "llvm/ADT/BitVector.h"
      20             : #include "llvm/ADT/SmallVector.h"
      21             : #include "llvm/CodeGen/MachineFunction.h"
      22             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      23             : #include "llvm/CodeGen/TargetFrameLowering.h"
      24             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      25             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      26             : #include "llvm/MC/MCRegisterInfo.h"
      27             : #include "llvm/Support/CommandLine.h"
      28             : #include "llvm/Support/Debug.h"
      29             : #include "llvm/Support/raw_ostream.h"
      30             : #include <algorithm>
      31             : #include <cassert>
      32             : #include <cstdint>
      33             : 
      34             : using namespace llvm;
      35             : 
      36             : #define DEBUG_TYPE "regalloc"
      37             : 
      38             : static cl::opt<unsigned>
      39      303507 : StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
      40      202338 :          cl::desc("Limit all regclasses to N registers"));
      41             : 
      42             : RegisterClassInfo::RegisterClassInfo() = default;
      43             : 
      44     1071161 : void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
      45             :   bool Update = false;
      46     1071161 :   MF = &mf;
      47             : 
      48             :   // Allocate new array the first time we see a new target.
      49     1071161 :   if (MF->getSubtarget().getRegisterInfo() != TRI) {
      50      105817 :     TRI = MF->getSubtarget().getRegisterInfo();
      51     8043654 :     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
      52             :     Update = true;
      53             :   }
      54             : 
      55             :   // Does this MF have different CSRs?
      56             :   assert(TRI && "no register info set");
      57             : 
      58             :   // Get the callee saved registers.
      59     1071161 :   const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
      60     1071161 :   if (Update || CSR != CalleeSavedRegs) {
      61             :     // Build a CSRAlias map. Every CSR alias saves the last
      62             :     // overlapping CSR.
      63      114095 :     CalleeSavedAliases.resize(TRI->getNumRegs(), 0);
      64     3912891 :     for (const MCPhysReg *I = CSR; *I; ++I)
      65    46237136 :       for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
      66    42438340 :         CalleeSavedAliases[*AI] = *I;
      67             : 
      68             :     Update = true;
      69             :   }
      70     1071161 :   CalleeSavedRegs = CSR;
      71             : 
      72             :   // Different reserved registers?
      73     1071161 :   const BitVector &RR = MF->getRegInfo().getReservedRegs();
      74     2038278 :   if (Reserved.size() != RR.size() || RR != Reserved) {
      75             :     Update = true;
      76      121209 :     Reserved = RR;
      77             :   }
      78             : 
      79             :   // Invalidate cached information from previous function.
      80      949952 :   if (Update) {
      81      123605 :     unsigned NumPSets = TRI->getNumRegPressureSets();
      82      123605 :     PSetLimits.reset(new unsigned[NumPSets]);
      83             :     std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
      84      123605 :     ++Tag;
      85             :   }
      86     1071161 : }
      87             : 
      88             : /// compute - Compute the preferred allocation order for RC with reserved
      89             : /// registers filtered out. Volatile registers come first followed by CSR
      90             : /// aliases ordered according to the CSR order specified by the target.
      91      468996 : void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
      92             :   assert(RC && "no register class given");
      93      937992 :   RCInfo &RCI = RegClass[RC->getID()];
      94             : 
      95             :   // Raw register count, including all reserved regs.
      96             :   unsigned NumRegs = RC->getNumRegs();
      97             : 
      98      468996 :   if (!RCI.Order)
      99      230932 :     RCI.Order.reset(new MCPhysReg[NumRegs]);
     100             : 
     101             :   unsigned N = 0;
     102             :   SmallVector<MCPhysReg, 16> CSRAlias;
     103      468996 :   unsigned MinCost = 0xff;
     104             :   unsigned LastCost = ~0u;
     105             :   unsigned LastCostChange = 0;
     106             : 
     107             :   // FIXME: Once targets reserve registers instead of removing them from the
     108             :   // allocation order, we can simply use begin/end here.
     109      468996 :   ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
     110    34422202 :   for (unsigned i = 0; i != RawOrder.size(); ++i) {
     111    16976603 :     unsigned PhysReg = RawOrder[i];
     112             :     // Remove reserved registers from the allocation order.
     113    16976603 :     if (Reserved.test(PhysReg))
     114     1927835 :       continue;
     115    30097536 :     unsigned Cost = TRI->getCostPerUse(PhysReg);
     116    15048768 :     MinCost = std::min(MinCost, Cost);
     117             : 
     118    15048768 :     if (CalleeSavedAliases[PhysReg])
     119             :       // PhysReg aliases a CSR, save it for later.
     120     1418624 :       CSRAlias.push_back(PhysReg);
     121             :     else {
     122    13630144 :       if (Cost != LastCost)
     123             :         LastCostChange = N;
     124    27260288 :       RCI.Order[N++] = PhysReg;
     125             :       LastCost = Cost;
     126             :     }
     127             :   }
     128      468996 :   RCI.NumRegs = N + CSRAlias.size();
     129             :   assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
     130             : 
     131             :   // CSR aliases go after the volatile registers, preserve the target's order.
     132     3306244 :   for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
     133     2837248 :     unsigned PhysReg = CSRAlias[i];
     134     1418624 :     unsigned Cost = TRI->getCostPerUse(PhysReg);
     135     1418624 :     if (Cost != LastCost)
     136             :       LastCostChange = N;
     137     2837248 :     RCI.Order[N++] = PhysReg;
     138             :     LastCost = Cost;
     139             :   }
     140             : 
     141             :   // Register allocator stress test.  Clip register class to N registers.
     142      468996 :   if (StressRA && RCI.NumRegs > StressRA)
     143          99 :     RCI.NumRegs = StressRA;
     144             : 
     145             :   // Check if RC is a proper sub-class.
     146      468996 :   if (const TargetRegisterClass *Super =
     147      468996 :           TRI->getLargestLegalSuperClass(RC, *MF))
     148      468996 :     if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
     149       92299 :       RCI.ProperSubClass = true;
     150             : 
     151      468996 :   RCI.MinCost = uint8_t(MinCost);
     152      468996 :   RCI.LastCostChange = LastCostChange;
     153             : 
     154             :   LLVM_DEBUG({
     155             :     dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
     156             :     for (unsigned I = 0; I != RCI.NumRegs; ++I)
     157             :       dbgs() << ' ' << printReg(RCI.Order[I], TRI);
     158             :     dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
     159             :   });
     160             : 
     161             :   // RCI is now up-to-date.
     162      468996 :   RCI.Tag = Tag;
     163      468996 : }
     164             : 
     165             : /// This is not accurate because two overlapping register sets may have some
     166             : /// nonoverlapping reserved registers. However, computing the allocation order
     167             : /// for all register classes would be too expensive.
     168      341902 : unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
     169             :   const TargetRegisterClass *RC = nullptr;
     170             :   unsigned NumRCUnits = 0;
     171    51602682 :   for (const TargetRegisterClass *C : TRI->regclasses()) {
     172    25459439 :     const int *PSetID = TRI->getRegClassPressureSets(C);
     173   210928285 :     for (; *PSetID != -1; ++PSetID) {
     174    95076965 :       if ((unsigned)*PSetID == Idx)
     175             :         break;
     176             :     }
     177    25459439 :     if (*PSetID == -1)
     178    23116897 :       continue;
     179             : 
     180             :     // Found a register class that counts against this pressure set.
     181             :     // For efficiency, only compute the set order for the largest set.
     182     2342542 :     unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
     183     2342542 :     if (!RC || NUnits > NumRCUnits) {
     184             :       RC = C;
     185             :       NumRCUnits = NUnits;
     186             :     }
     187             :   }
     188      341902 :   compute(RC);
     189      683804 :   unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
     190      341902 :   return TRI->getRegPressureSetLimit(*MF, Idx) -
     191      341902 :          TRI->getRegClassWeight(RC).RegWeight * NReserved;
     192      303507 : }

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