LCOV - code coverage report
Current view: top level - lib/CodeGen - RegisterCoalescer.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 976 1082 90.2 %
Date: 2018-06-17 00:07:59 Functions: 62 65 95.4 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface ------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file implements the generic RegisterCoalescer interface which
      11             : // is used as the common interface used by all clients and
      12             : // implementations of register coalescing.
      13             : //
      14             : //===----------------------------------------------------------------------===//
      15             : 
      16             : #include "RegisterCoalescer.h"
      17             : #include "llvm/ADT/ArrayRef.h"
      18             : #include "llvm/ADT/BitVector.h"
      19             : #include "llvm/ADT/STLExtras.h"
      20             : #include "llvm/ADT/SmallPtrSet.h"
      21             : #include "llvm/ADT/SmallVector.h"
      22             : #include "llvm/ADT/Statistic.h"
      23             : #include "llvm/Analysis/AliasAnalysis.h"
      24             : #include "llvm/CodeGen/LiveInterval.h"
      25             : #include "llvm/CodeGen/LiveIntervals.h"
      26             : #include "llvm/CodeGen/LiveRangeEdit.h"
      27             : #include "llvm/CodeGen/MachineBasicBlock.h"
      28             : #include "llvm/CodeGen/MachineFunction.h"
      29             : #include "llvm/CodeGen/MachineFunctionPass.h"
      30             : #include "llvm/CodeGen/MachineInstr.h"
      31             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      32             : #include "llvm/CodeGen/MachineLoopInfo.h"
      33             : #include "llvm/CodeGen/MachineOperand.h"
      34             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      35             : #include "llvm/CodeGen/Passes.h"
      36             : #include "llvm/CodeGen/RegisterClassInfo.h"
      37             : #include "llvm/CodeGen/SlotIndexes.h"
      38             : #include "llvm/CodeGen/TargetInstrInfo.h"
      39             : #include "llvm/CodeGen/TargetOpcodes.h"
      40             : #include "llvm/CodeGen/TargetRegisterInfo.h"
      41             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      42             : #include "llvm/IR/DebugLoc.h"
      43             : #include "llvm/MC/LaneBitmask.h"
      44             : #include "llvm/MC/MCInstrDesc.h"
      45             : #include "llvm/MC/MCRegisterInfo.h"
      46             : #include "llvm/Pass.h"
      47             : #include "llvm/Support/CommandLine.h"
      48             : #include "llvm/Support/Compiler.h"
      49             : #include "llvm/Support/Debug.h"
      50             : #include "llvm/Support/ErrorHandling.h"
      51             : #include "llvm/Support/raw_ostream.h"
      52             : #include <algorithm>
      53             : #include <cassert>
      54             : #include <iterator>
      55             : #include <limits>
      56             : #include <tuple>
      57             : #include <utility>
      58             : #include <vector>
      59             : 
      60             : using namespace llvm;
      61             : 
      62             : #define DEBUG_TYPE "regalloc"
      63             : 
      64             : STATISTIC(numJoins    , "Number of interval joins performed");
      65             : STATISTIC(numCrossRCs , "Number of cross class joins performed");
      66             : STATISTIC(numCommutes , "Number of instruction commuting performed");
      67             : STATISTIC(numExtends  , "Number of copies extended");
      68             : STATISTIC(NumReMats   , "Number of instructions re-materialized");
      69             : STATISTIC(NumInflated , "Number of register classes inflated");
      70             : STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested");
      71             : STATISTIC(NumLaneResolves,  "Number of dead lane conflicts resolved");
      72             : 
      73      101169 : static cl::opt<bool> EnableJoining("join-liveintervals",
      74      101169 :                                    cl::desc("Coalesce copies (default=true)"),
      75      303507 :                                    cl::init(true), cl::Hidden);
      76             : 
      77      101169 : static cl::opt<bool> UseTerminalRule("terminal-rule",
      78      101169 :                                      cl::desc("Apply the terminal rule"),
      79      303507 :                                      cl::init(false), cl::Hidden);
      80             : 
      81             : /// Temporary flag to test critical edge unsplitting.
      82             : static cl::opt<bool>
      83      101169 : EnableJoinSplits("join-splitedges",
      84      202338 :   cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden);
      85             : 
      86             : /// Temporary flag to test global copy optimization.
      87             : static cl::opt<cl::boolOrDefault>
      88      101169 : EnableGlobalCopies("join-globalcopies",
      89      101169 :   cl::desc("Coalesce copies that span blocks (default=subtarget)"),
      90      303507 :   cl::init(cl::BOU_UNSET), cl::Hidden);
      91             : 
      92             : static cl::opt<bool>
      93      101169 : VerifyCoalescing("verify-coalescing",
      94      101169 :          cl::desc("Verify machine instrs before and after register coalescing"),
      95      303507 :          cl::Hidden);
      96             : 
      97             : namespace {
      98             : 
      99       76072 :   class RegisterCoalescer : public MachineFunctionPass,
     100             :                             private LiveRangeEdit::Delegate {
     101             :     MachineFunction* MF;
     102             :     MachineRegisterInfo* MRI;
     103             :     const TargetRegisterInfo* TRI;
     104             :     const TargetInstrInfo* TII;
     105             :     LiveIntervals *LIS;
     106             :     const MachineLoopInfo* Loops;
     107             :     AliasAnalysis *AA;
     108             :     RegisterClassInfo RegClassInfo;
     109             : 
     110             :     /// A LaneMask to remember on which subregister live ranges we need to call
     111             :     /// shrinkToUses() later.
     112             :     LaneBitmask ShrinkMask;
     113             : 
     114             :     /// True if the main range of the currently coalesced intervals should be
     115             :     /// checked for smaller live intervals.
     116             :     bool ShrinkMainRange;
     117             : 
     118             :     /// True if the coalescer should aggressively coalesce global copies
     119             :     /// in favor of keeping local copies.
     120             :     bool JoinGlobalCopies;
     121             : 
     122             :     /// True if the coalescer should aggressively coalesce fall-thru
     123             :     /// blocks exclusively containing copies.
     124             :     bool JoinSplitEdges;
     125             : 
     126             :     /// Copy instructions yet to be coalesced.
     127             :     SmallVector<MachineInstr*, 8> WorkList;
     128             :     SmallVector<MachineInstr*, 8> LocalWorkList;
     129             : 
     130             :     /// Set of instruction pointers that have been erased, and
     131             :     /// that may be present in WorkList.
     132             :     SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
     133             : 
     134             :     /// Dead instructions that are about to be deleted.
     135             :     SmallVector<MachineInstr*, 8> DeadDefs;
     136             : 
     137             :     /// Virtual registers to be considered for register class inflation.
     138             :     SmallVector<unsigned, 8> InflateRegs;
     139             : 
     140             :     /// Recursively eliminate dead defs in DeadDefs.
     141             :     void eliminateDeadDefs();
     142             : 
     143             :     /// LiveRangeEdit callback for eliminateDeadDefs().
     144             :     void LRE_WillEraseInstruction(MachineInstr *MI) override;
     145             : 
     146             :     /// Coalesce the LocalWorkList.
     147             :     void coalesceLocals();
     148             : 
     149             :     /// Join compatible live intervals
     150             :     void joinAllIntervals();
     151             : 
     152             :     /// Coalesce copies in the specified MBB, putting
     153             :     /// copies that cannot yet be coalesced into WorkList.
     154             :     void copyCoalesceInMBB(MachineBasicBlock *MBB);
     155             : 
     156             :     /// Tries to coalesce all copies in CurrList. Returns true if any progress
     157             :     /// was made.
     158             :     bool copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList);
     159             : 
     160             :     /// Attempt to join intervals corresponding to SrcReg/DstReg, which are the
     161             :     /// src/dst of the copy instruction CopyMI.  This returns true if the copy
     162             :     /// was successfully coalesced away. If it is not currently possible to
     163             :     /// coalesce this interval, but it may be possible if other things get
     164             :     /// coalesced, then it returns true by reference in 'Again'.
     165             :     bool joinCopy(MachineInstr *TheCopy, bool &Again);
     166             : 
     167             :     /// Attempt to join these two intervals.  On failure, this
     168             :     /// returns false.  The output "SrcInt" will not have been modified, so we
     169             :     /// can use this information below to update aliases.
     170             :     bool joinIntervals(CoalescerPair &CP);
     171             : 
     172             :     /// Attempt joining two virtual registers. Return true on success.
     173             :     bool joinVirtRegs(CoalescerPair &CP);
     174             : 
     175             :     /// Attempt joining with a reserved physreg.
     176             :     bool joinReservedPhysReg(CoalescerPair &CP);
     177             : 
     178             :     /// Add the LiveRange @p ToMerge as a subregister liverange of @p LI.
     179             :     /// Subranges in @p LI which only partially interfere with the desired
     180             :     /// LaneMask are split as necessary. @p LaneMask are the lanes that
     181             :     /// @p ToMerge will occupy in the coalescer register. @p LI has its subrange
     182             :     /// lanemasks already adjusted to the coalesced register.
     183             :     void mergeSubRangeInto(LiveInterval &LI, const LiveRange &ToMerge,
     184             :                            LaneBitmask LaneMask, CoalescerPair &CP);
     185             : 
     186             :     /// Join the liveranges of two subregisters. Joins @p RRange into
     187             :     /// @p LRange, @p RRange may be invalid afterwards.
     188             :     void joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
     189             :                           LaneBitmask LaneMask, const CoalescerPair &CP);
     190             : 
     191             :     /// We found a non-trivially-coalescable copy. If the source value number is
     192             :     /// defined by a copy from the destination reg see if we can merge these two
     193             :     /// destination reg valno# into a single value number, eliminating a copy.
     194             :     /// This returns true if an interval was modified.
     195             :     bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
     196             : 
     197             :     /// Return true if there are definitions of IntB
     198             :     /// other than BValNo val# that can reach uses of AValno val# of IntA.
     199             :     bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
     200             :                               VNInfo *AValNo, VNInfo *BValNo);
     201             : 
     202             :     /// We found a non-trivially-coalescable copy.
     203             :     /// If the source value number is defined by a commutable instruction and
     204             :     /// its other operand is coalesced to the copy dest register, see if we
     205             :     /// can transform the copy into a noop by commuting the definition.
     206             :     /// This returns true if an interval was modified.
     207             :     bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
     208             : 
     209             :     /// We found a copy which can be moved to its less frequent predecessor.
     210             :     bool removePartialRedundancy(const CoalescerPair &CP, MachineInstr &CopyMI);
     211             : 
     212             :     /// If the source of a copy is defined by a
     213             :     /// trivial computation, replace the copy by rematerialize the definition.
     214             :     bool reMaterializeTrivialDef(const CoalescerPair &CP, MachineInstr *CopyMI,
     215             :                                  bool &IsDefCopy);
     216             : 
     217             :     /// Return true if a copy involving a physreg should be joined.
     218             :     bool canJoinPhys(const CoalescerPair &CP);
     219             : 
     220             :     /// Replace all defs and uses of SrcReg to DstReg and update the subregister
     221             :     /// number if it is not zero. If DstReg is a physical register and the
     222             :     /// existing subregister number of the def / use being updated is not zero,
     223             :     /// make sure to set it to the correct physical subregister.
     224             :     void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
     225             : 
     226             :     /// If the given machine operand reads only undefined lanes add an undef
     227             :     /// flag.
     228             :     /// This can happen when undef uses were previously concealed by a copy
     229             :     /// which we coalesced. Example:
     230             :     ///    %0:sub0<def,read-undef> = ...
     231             :     ///    %1 = COPY %0           <-- Coalescing COPY reveals undef
     232             :     ///       = use %1:sub1       <-- hidden undef use
     233             :     void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
     234             :                       MachineOperand &MO, unsigned SubRegIdx);
     235             : 
     236             :     /// Handle copies of undef values.
     237             :     /// Returns true if @p CopyMI was a copy of an undef value and eliminated.
     238             :     bool eliminateUndefCopy(MachineInstr *CopyMI);
     239             : 
     240             :     /// Check whether or not we should apply the terminal rule on the
     241             :     /// destination (Dst) of \p Copy.
     242             :     /// When the terminal rule applies, Copy is not profitable to
     243             :     /// coalesce.
     244             :     /// Dst is terminal if it has exactly one affinity (Dst, Src) and
     245             :     /// at least one interference (Dst, Dst2). If Dst is terminal, the
     246             :     /// terminal rule consists in checking that at least one of
     247             :     /// interfering node, say Dst2, has an affinity of equal or greater
     248             :     /// weight with Src.
     249             :     /// In that case, Dst2 and Dst will not be able to be both coalesced
     250             :     /// with Src. Since Dst2 exposes more coalescing opportunities than
     251             :     /// Dst, we can drop \p Copy.
     252             :     bool applyTerminalRule(const MachineInstr &Copy) const;
     253             : 
     254             :     /// Wrapper method for \see LiveIntervals::shrinkToUses.
     255             :     /// This method does the proper fixing of the live-ranges when the afore
     256             :     /// mentioned method returns true.
     257       32868 :     void shrinkToUses(LiveInterval *LI,
     258             :                       SmallVectorImpl<MachineInstr * > *Dead = nullptr) {
     259       32868 :       if (LIS->shrinkToUses(LI, Dead)) {
     260             :         /// Check whether or not \p LI is composed by multiple connected
     261             :         /// components and if that is the case, fix that.
     262             :         SmallVector<LiveInterval*, 8> SplitLIs;
     263          39 :         LIS->splitSeparateComponents(*LI, SplitLIs);
     264             :       }
     265       32868 :     }
     266             : 
     267             :     /// Wrapper Method to do all the necessary work when an Instruction is
     268             :     /// deleted.
     269             :     /// Optimizations should use this to make sure that deleted instructions
     270             :     /// are always accounted for.
     271       36640 :     void deleteInstr(MachineInstr* MI) {
     272       36640 :       ErasedInstrs.insert(MI);
     273       36640 :       LIS->RemoveMachineInstrFromMaps(*MI);
     274       36640 :       MI->eraseFromParent();
     275       36640 :     }
     276             : 
     277             :   public:
     278             :     static char ID; ///< Class identification, replacement for typeinfo
     279             : 
     280       19121 :     RegisterCoalescer() : MachineFunctionPass(ID) {
     281       19121 :       initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
     282       19121 :     }
     283             : 
     284             :     void getAnalysisUsage(AnalysisUsage &AU) const override;
     285             : 
     286             :     void releaseMemory() override;
     287             : 
     288             :     /// This is the pass entry point.
     289             :     bool runOnMachineFunction(MachineFunction&) override;
     290             : 
     291             :     /// Implement the dump method.
     292             :     void print(raw_ostream &O, const Module* = nullptr) const override;
     293             :   };
     294             : 
     295             : } // end anonymous namespace
     296             : 
     297             : char RegisterCoalescer::ID = 0;
     298             : 
     299             : char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
     300             : 
     301       26770 : INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
     302             :                       "Simple Register Coalescing", false, false)
     303       26770 : INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
     304       26770 : INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
     305       26770 : INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
     306       26770 : INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
     307      293434 : INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
     308             :                     "Simple Register Coalescing", false, false)
     309             : 
     310     4490659 : static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
     311             :                         unsigned &Src, unsigned &Dst,
     312             :                         unsigned &SrcSub, unsigned &DstSub) {
     313     4490659 :   if (MI->isCopy()) {
     314     3541515 :     Dst = MI->getOperand(0).getReg();
     315     3541515 :     DstSub = MI->getOperand(0).getSubReg();
     316     3541515 :     Src = MI->getOperand(1).getReg();
     317     3541515 :     SrcSub = MI->getOperand(1).getSubReg();
     318      949144 :   } else if (MI->isSubregToReg()) {
     319       83755 :     Dst = MI->getOperand(0).getReg();
     320      167510 :     DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
     321       83755 :                                       MI->getOperand(3).getImm());
     322       83755 :     Src = MI->getOperand(2).getReg();
     323       83755 :     SrcSub = MI->getOperand(2).getSubReg();
     324             :   } else
     325             :     return false;
     326             :   return true;
     327             : }
     328             : 
     329             : /// Return true if this block should be vacated by the coalescer to eliminate
     330             : /// branches. The important cases to handle in the coalescer are critical edges
     331             : /// split during phi elimination which contain only copies. Simple blocks that
     332             : /// contain non-branches should also be vacated, but this can be handled by an
     333             : /// earlier pass similar to early if-conversion.
     334           0 : static bool isSplitEdge(const MachineBasicBlock *MBB) {
     335           0 :   if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
     336             :     return false;
     337             : 
     338           0 :   for (const auto &MI : *MBB) {
     339           0 :     if (!MI.isCopyLike() && !MI.isUnconditionalBranch())
     340           0 :       return false;
     341             :   }
     342           0 :   return true;
     343             : }
     344             : 
     345     1623580 : bool CoalescerPair::setRegisters(const MachineInstr *MI) {
     346     1623580 :   SrcReg = DstReg = 0;
     347     1623580 :   SrcIdx = DstIdx = 0;
     348     1623580 :   NewRC = nullptr;
     349     1623580 :   Flipped = CrossClass = false;
     350             : 
     351             :   unsigned Src, Dst, SrcSub, DstSub;
     352     1623580 :   if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
     353             :     return false;
     354     1623443 :   Partial = SrcSub || DstSub;
     355             : 
     356             :   // If one register is a physreg, it must be Dst.
     357     3246886 :   if (TargetRegisterInfo::isPhysicalRegister(Src)) {
     358      766432 :     if (TargetRegisterInfo::isPhysicalRegister(Dst))
     359             :       return false;
     360             :     std::swap(Src, Dst);
     361             :     std::swap(SrcSub, DstSub);
     362      382310 :     Flipped = true;
     363             :   }
     364             : 
     365     1622537 :   const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
     366             : 
     367     3245074 :   if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
     368             :     // Eliminate DstSub on a physreg.
     369      871396 :     if (DstSub) {
     370           2 :       Dst = TRI.getSubReg(Dst, DstSub);
     371           2 :       if (!Dst) return false;
     372           2 :       DstSub = 0;
     373             :     }
     374             : 
     375             :     // Eliminate SrcSub by picking a corresponding Dst superregister.
     376      871396 :     if (SrcSub) {
     377       34839 :       Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
     378       11613 :       if (!Dst) return false;
     379     2579251 :     } else if (!MRI.getRegClass(Src)->contains(Dst)) {
     380             :       return false;
     381             :     }
     382             :   } else {
     383             :     // Both registers are virtual.
     384      751141 :     const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
     385             :     const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
     386             : 
     387             :     // Both registers have subreg indices.
     388      751141 :     if (SrcSub && DstSub) {
     389             :       // Copies between different sub-registers are never coalescable.
     390       50902 :       if (Src == Dst && SrcSub != DstSub)
     391             :         return false;
     392             : 
     393       47522 :       NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
     394             :                                          SrcIdx, DstIdx);
     395       47522 :       if (!NewRC)
     396             :         return false;
     397      700239 :     } else if (DstSub) {
     398             :       // SrcReg will be merged with a sub-register of DstReg.
     399      161391 :       SrcIdx = DstSub;
     400      161391 :       NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
     401      538848 :     } else if (SrcSub) {
     402             :       // DstReg will be merged with a sub-register of SrcReg.
     403      102033 :       DstIdx = SrcSub;
     404      102033 :       NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
     405             :     } else {
     406             :       // This is a straight copy without sub-registers.
     407      436815 :       NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
     408             :     }
     409             : 
     410             :     // The combined constraint may be impossible to satisfy.
     411      747272 :     if (!NewRC)
     412             :       return false;
     413             : 
     414             :     // Prefer SrcReg to be a sub-register of DstReg.
     415             :     // FIXME: Coalescer should support subregs symmetrically.
     416      709555 :     if (DstIdx && !SrcIdx) {
     417             :       std::swap(Src, Dst);
     418             :       std::swap(SrcIdx, DstIdx);
     419       97488 :       Flipped = !Flipped;
     420             :     }
     421             : 
     422      709555 :     CrossClass = NewRC != DstRC || NewRC != SrcRC;
     423             :   }
     424             :   // Check our invariants
     425             :   assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
     426             :   assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
     427             :          "Cannot have a physical SubIdx");
     428     1577325 :   SrcReg = Src;
     429     1577325 :   DstReg = Dst;
     430     1577325 :   return true;
     431             : }
     432             : 
     433       88077 : bool CoalescerPair::flip() {
     434      176154 :   if (TargetRegisterInfo::isPhysicalRegister(DstReg))
     435             :     return false;
     436             :   std::swap(SrcReg, DstReg);
     437             :   std::swap(SrcIdx, DstIdx);
     438       88077 :   Flipped = !Flipped;
     439       88077 :   return true;
     440             : }
     441             : 
     442     2166119 : bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
     443     2166119 :   if (!MI)
     444             :     return false;
     445             :   unsigned Src, Dst, SrcSub, DstSub;
     446     2159019 :   if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
     447             :     return false;
     448             : 
     449             :   // Find the virtual register that is SrcReg.
     450     1293767 :   if (Dst == SrcReg) {
     451             :     std::swap(Src, Dst);
     452             :     std::swap(SrcSub, DstSub);
     453     1003095 :   } else if (Src != SrcReg) {
     454             :     return false;
     455             :   }
     456             : 
     457             :   // Now check that Dst matches DstReg.
     458     2342180 :   if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
     459      483482 :     if (!TargetRegisterInfo::isPhysicalRegister(Dst))
     460             :       return false;
     461             :     assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
     462             :     // DstSub could be set for a physreg from INSERT_SUBREG.
     463      232199 :     if (DstSub)
     464           0 :       Dst = TRI.getSubReg(Dst, DstSub);
     465             :     // Full copy of Src.
     466      232199 :     if (!SrcSub)
     467      227886 :       return DstReg == Dst;
     468             :     // This is a partial register copy. Check that the parts match.
     469        4313 :     return TRI.getSubReg(DstReg, SrcSub) == Dst;
     470             :   } else {
     471             :     // DstReg is virtual.
     472      929349 :     if (DstReg != Dst)
     473             :       return false;
     474             :     // Registers match, do the subregisters line up?
     475      900192 :     return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
     476     1800384 :            TRI.composeSubRegIndices(DstIdx, DstSub);
     477             :   }
     478             : }
     479             : 
     480       18976 : void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
     481       18976 :   AU.setPreservesCFG();
     482             :   AU.addRequired<AAResultsWrapperPass>();
     483             :   AU.addRequired<LiveIntervals>();
     484             :   AU.addPreserved<LiveIntervals>();
     485             :   AU.addPreserved<SlotIndexes>();
     486             :   AU.addRequired<MachineLoopInfo>();
     487             :   AU.addPreserved<MachineLoopInfo>();
     488       18976 :   AU.addPreservedID(MachineDominatorsID);
     489       18976 :   MachineFunctionPass::getAnalysisUsage(AU);
     490       18976 : }
     491             : 
     492       23964 : void RegisterCoalescer::eliminateDeadDefs() {
     493             :   SmallVector<unsigned, 8> NewRegs;
     494       47928 :   LiveRangeEdit(nullptr, NewRegs, *MF, *LIS,
     495       23964 :                 nullptr, this).eliminateDeadDefs(DeadDefs);
     496       23964 : }
     497             : 
     498       23965 : void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
     499             :   // MI may be in WorkList. Make sure we don't visit it.
     500       23965 :   ErasedInstrs.insert(MI);
     501       23965 : }
     502             : 
     503       54930 : bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
     504             :                                              MachineInstr *CopyMI) {
     505             :   assert(!CP.isPartial() && "This doesn't work for partial copies.");
     506             :   assert(!CP.isPhys() && "This doesn't work for physreg copies.");
     507             : 
     508             :   LiveInterval &IntA =
     509       54930 :     LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
     510             :   LiveInterval &IntB =
     511       54930 :     LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
     512       54930 :   SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
     513             : 
     514             :   // We have a non-trivially-coalescable copy with IntA being the source and
     515             :   // IntB being the dest, thus this defines a value number in IntB.  If the
     516             :   // source value number (in IntA) is defined by a copy from B, see if we can
     517             :   // merge these two pieces of B into a single value number, eliminating a copy.
     518             :   // For example:
     519             :   //
     520             :   //  A3 = B0
     521             :   //    ...
     522             :   //  B1 = A3      <- this copy
     523             :   //
     524             :   // In this case, B0 can be extended to where the B1 copy lives, allowing the
     525             :   // B1 value number to be replaced with B0 (which simplifies the B
     526             :   // liveinterval).
     527             : 
     528             :   // BValNo is a value number in B that is defined by a copy from A.  'B1' in
     529             :   // the example above.
     530       54930 :   LiveInterval::iterator BS = IntB.FindSegmentContaining(CopyIdx);
     531       54930 :   if (BS == IntB.end()) return false;
     532       54930 :   VNInfo *BValNo = BS->valno;
     533             : 
     534             :   // Get the location that B is defined at.  Two options: either this value has
     535             :   // an unknown definition point or it is defined at CopyIdx.  If unknown, we
     536             :   // can't process it.
     537       54930 :   if (BValNo->def != CopyIdx) return false;
     538             : 
     539             :   // AValNo is the value number in A that defines the copy, A3 in the example.
     540       54930 :   SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
     541       54930 :   LiveInterval::iterator AS = IntA.FindSegmentContaining(CopyUseIdx);
     542             :   // The live segment might not exist after fun with physreg coalescing.
     543       54930 :   if (AS == IntA.end()) return false;
     544       54930 :   VNInfo *AValNo = AS->valno;
     545             : 
     546             :   // If AValNo is defined as a copy from IntB, we can potentially process this.
     547             :   // Get the instruction that defines this value number.
     548             :   MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
     549             :   // Don't allow any partial copies, even if isCoalescable() allows them.
     550       54930 :   if (!CP.isCoalescable(ACopyMI) || !ACopyMI->isFullCopy())
     551             :     return false;
     552             : 
     553             :   // Get the Segment in IntB that this value number starts with.
     554             :   LiveInterval::iterator ValS =
     555          24 :     IntB.FindSegmentContaining(AValNo->def.getPrevSlot());
     556          24 :   if (ValS == IntB.end())
     557             :     return false;
     558             : 
     559             :   // Make sure that the end of the live segment is inside the same block as
     560             :   // CopyMI.
     561             :   MachineInstr *ValSEndInst =
     562             :     LIS->getInstructionFromIndex(ValS->end.getPrevSlot());
     563          24 :   if (!ValSEndInst || ValSEndInst->getParent() != CopyMI->getParent())
     564             :     return false;
     565             : 
     566             :   // Okay, we now know that ValS ends in the same block that the CopyMI
     567             :   // live-range starts.  If there are no intervening live segments between them
     568             :   // in IntB, we can merge them.
     569           7 :   if (ValS+1 != BS) return false;
     570             : 
     571             :   LLVM_DEBUG(dbgs() << "Extending: " << printReg(IntB.reg, TRI));
     572             : 
     573           7 :   SlotIndex FillerStart = ValS->end, FillerEnd = BS->start;
     574             :   // We are about to delete CopyMI, so need to remove it as the 'instruction
     575             :   // that defines this value #'. Update the valnum with the new defining
     576             :   // instruction #.
     577           7 :   BValNo->def = FillerStart;
     578             : 
     579             :   // Okay, we can merge them.  We need to insert a new liverange:
     580             :   // [ValS.end, BS.begin) of either value number, then we merge the
     581             :   // two value numbers.
     582           7 :   IntB.addSegment(LiveInterval::Segment(FillerStart, FillerEnd, BValNo));
     583             : 
     584             :   // Okay, merge "B1" into the same value number as "B0".
     585           7 :   if (BValNo != ValS->valno)
     586           7 :     IntB.MergeValueNumberInto(BValNo, ValS->valno);
     587             : 
     588             :   // Do the same for the subregister segments.
     589           7 :   for (LiveInterval::SubRange &S : IntB.subranges()) {
     590           0 :     VNInfo *SubBValNo = S.getVNInfoAt(CopyIdx);
     591           0 :     S.addSegment(LiveInterval::Segment(FillerStart, FillerEnd, SubBValNo));
     592             :     VNInfo *SubValSNo = S.getVNInfoAt(AValNo->def.getPrevSlot());
     593           0 :     if (SubBValNo != SubValSNo)
     594           0 :       S.MergeValueNumberInto(SubBValNo, SubValSNo);
     595             :   }
     596             : 
     597             :   LLVM_DEBUG(dbgs() << "   result = " << IntB << '\n');
     598             : 
     599             :   // If the source instruction was killing the source register before the
     600             :   // merge, unset the isKill marker given the live range has been extended.
     601           7 :   int UIdx = ValSEndInst->findRegisterUseOperandIdx(IntB.reg, true);
     602           7 :   if (UIdx != -1) {
     603           0 :     ValSEndInst->getOperand(UIdx).setIsKill(false);
     604             :   }
     605             : 
     606             :   // Rewrite the copy. If the copy instruction was killing the destination
     607             :   // register before the merge, find the last use and trim the live range. That
     608             :   // will also add the isKill marker.
     609           7 :   CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
     610           7 :   if (AS->end == CopyIdx)
     611           1 :     shrinkToUses(&IntA);
     612             : 
     613             :   ++numExtends;
     614             :   return true;
     615             : }
     616             : 
     617          56 : bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
     618             :                                              LiveInterval &IntB,
     619             :                                              VNInfo *AValNo,
     620             :                                              VNInfo *BValNo) {
     621             :   // If AValNo has PHI kills, conservatively assume that IntB defs can reach
     622             :   // the PHI values.
     623          56 :   if (LIS->hasPHIKill(IntA, AValNo))
     624             :     return true;
     625             : 
     626         772 :   for (LiveRange::Segment &ASeg : IntA.segments) {
     627         361 :     if (ASeg.valno != AValNo) continue;
     628             :     LiveInterval::iterator BI =
     629          53 :       std::upper_bound(IntB.begin(), IntB.end(), ASeg.start);
     630          53 :     if (BI != IntB.begin())
     631          53 :       --BI;
     632         393 :     for (; BI != IntB.end() && ASeg.end >= BI->start; ++BI) {
     633         107 :       if (BI->valno == BValNo)
     634             :         continue;
     635         106 :       if (BI->start <= ASeg.start && BI->end > ASeg.start)
     636             :         return true;
     637          54 :       if (BI->start > ASeg.start && BI->start < ASeg.end)
     638             :         return true;
     639             :     }
     640             :   }
     641             :   return false;
     642             : }
     643             : 
     644             : /// Copy segements with value number @p SrcValNo from liverange @p Src to live
     645             : /// range @Dst and use value number @p DstValNo there.
     646          49 : static void addSegmentsWithValNo(LiveRange &Dst, VNInfo *DstValNo,
     647             :                                  const LiveRange &Src, const VNInfo *SrcValNo) {
     648         757 :   for (const LiveRange::Segment &S : Src.segments) {
     649         354 :     if (S.valno != SrcValNo)
     650         304 :       continue;
     651          50 :     Dst.addSegment(LiveRange::Segment(S.start, S.end, DstValNo));
     652             :   }
     653          49 : }
     654             : 
     655       54923 : bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
     656             :                                                  MachineInstr *CopyMI) {
     657             :   assert(!CP.isPhys());
     658             : 
     659             :   LiveInterval &IntA =
     660       54923 :       LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
     661             :   LiveInterval &IntB =
     662       54923 :       LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
     663             : 
     664             :   // We found a non-trivially-coalescable copy with IntA being the source and
     665             :   // IntB being the dest, thus this defines a value number in IntB.  If the
     666             :   // source value number (in IntA) is defined by a commutable instruction and
     667             :   // its other operand is coalesced to the copy dest register, see if we can
     668             :   // transform the copy into a noop by commuting the definition. For example,
     669             :   //
     670             :   //  A3 = op A2 killed B0
     671             :   //    ...
     672             :   //  B1 = A3      <- this copy
     673             :   //    ...
     674             :   //     = op A3   <- more uses
     675             :   //
     676             :   // ==>
     677             :   //
     678             :   //  B2 = op B0 killed A2
     679             :   //    ...
     680             :   //  B1 = B2      <- now an identity copy
     681             :   //    ...
     682             :   //     = op B2   <- more uses
     683             : 
     684             :   // BValNo is a value number in B that is defined by a copy from A. 'B1' in
     685             :   // the example above.
     686       54923 :   SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
     687       54923 :   VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
     688             :   assert(BValNo != nullptr && BValNo->def == CopyIdx);
     689             : 
     690             :   // AValNo is the value number in A that defines the copy, A3 in the example.
     691       54923 :   VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
     692             :   assert(AValNo && !AValNo->isUnused() && "COPY source not live");
     693       54923 :   if (AValNo->isPHIDef())
     694             :     return false;
     695             :   MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
     696       47823 :   if (!DefMI)
     697             :     return false;
     698       47823 :   if (!DefMI->isCommutable())
     699             :     return false;
     700             :   // If DefMI is a two-address instruction then commuting it will change the
     701             :   // destination register.
     702        5799 :   int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
     703             :   assert(DefIdx != -1);
     704             :   unsigned UseOpIdx;
     705        5799 :   if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
     706             :     return false;
     707             : 
     708             :   // FIXME: The code below tries to commute 'UseOpIdx' operand with some other
     709             :   // commutable operand which is expressed by 'CommuteAnyOperandIndex'value
     710             :   // passed to the method. That _other_ operand is chosen by
     711             :   // the findCommutedOpIndices() method.
     712             :   //
     713             :   // That is obviously an area for improvement in case of instructions having
     714             :   // more than 2 operands. For example, if some instruction has 3 commutable
     715             :   // operands then all possible variants (i.e. op#1<->op#2, op#1<->op#3,
     716             :   // op#2<->op#3) of commute transformation should be considered/tried here.
     717        5618 :   unsigned NewDstIdx = TargetInstrInfo::CommuteAnyOperandIndex;
     718        5618 :   if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx))
     719             :     return false;
     720             : 
     721        5492 :   MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
     722        5492 :   unsigned NewReg = NewDstMO.getReg();
     723       10928 :   if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill())
     724             :     return false;
     725             : 
     726             :   // Make sure there are no other definitions of IntB that would reach the
     727             :   // uses which the new definition can reach.
     728          56 :   if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
     729             :     return false;
     730             : 
     731             :   // If some of the uses of IntA.reg is already coalesced away, return false.
     732             :   // It's not possible to determine whether it's safe to perform the coalescing.
     733         496 :   for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) {
     734         394 :     MachineInstr *UseMI = MO.getParent();
     735         394 :     unsigned OpNo = &MO - &UseMI->getOperand(0);
     736         788 :     SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI);
     737         394 :     LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
     738         721 :     if (US == IntA.end() || US->valno != AValNo)
     739         327 :       continue;
     740             :     // If this use is tied to a def, we can't rewrite the register.
     741          67 :     if (UseMI->isRegTiedToDefOperand(OpNo))
     742           0 :       return false;
     743             :   }
     744             : 
     745             :   LLVM_DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
     746             :                     << *DefMI);
     747             : 
     748             :   // At this point we have decided that it is legal to do this
     749             :   // transformation.  Start by commuting the instruction.
     750          51 :   MachineBasicBlock *MBB = DefMI->getParent();
     751             :   MachineInstr *NewMI =
     752          51 :       TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx);
     753          51 :   if (!NewMI)
     754             :     return false;
     755          98 :   if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
     756          98 :       TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
     757          98 :       !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
     758             :     return false;
     759          49 :   if (NewMI != DefMI) {
     760           0 :     LIS->ReplaceMachineInstrInMaps(*DefMI, *NewMI);
     761             :     MachineBasicBlock::iterator Pos = DefMI;
     762             :     MBB->insert(Pos, NewMI);
     763             :     MBB->erase(DefMI);
     764             :   }
     765             : 
     766             :   // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
     767             :   // A = or A, B
     768             :   // ...
     769             :   // B = A
     770             :   // ...
     771             :   // C = killed A
     772             :   // ...
     773             :   //   = B
     774             : 
     775             :   // Update uses of IntA of the specific Val# with IntB.
     776          49 :   for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
     777             :                                          UE = MRI->use_end();
     778         461 :        UI != UE; /* ++UI is below because of possible MI removal */) {
     779             :     MachineOperand &UseMO = *UI;
     780             :     ++UI;
     781         412 :     if (UseMO.isUndef())
     782           0 :       continue;
     783         412 :     MachineInstr *UseMI = UseMO.getParent();
     784         436 :     if (UseMI->isDebugValue()) {
     785             :       // FIXME These don't have an instruction index.  Not clear we have enough
     786             :       // info to decide whether to do this replacement or not.  For now do it.
     787          24 :       UseMO.setReg(NewReg);
     788          24 :       continue;
     789             :     }
     790         388 :     SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
     791         388 :     LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
     792             :     assert(US != IntA.end() && "Use must be live");
     793         388 :     if (US->valno != AValNo)
     794         325 :       continue;
     795             :     // Kill flags are no longer accurate. They are recomputed after RA.
     796             :     UseMO.setIsKill(false);
     797          63 :     if (TargetRegisterInfo::isPhysicalRegister(NewReg))
     798           0 :       UseMO.substPhysReg(NewReg, *TRI);
     799             :     else
     800          63 :       UseMO.setReg(NewReg);
     801          63 :     if (UseMI == CopyMI)
     802          49 :       continue;
     803          14 :     if (!UseMI->isCopy())
     804           9 :       continue;
     805          10 :     if (UseMI->getOperand(0).getReg() != IntB.reg ||
     806             :         UseMI->getOperand(0).getSubReg())
     807           4 :       continue;
     808             : 
     809             :     // This copy will become a noop. If it's defining a new val#, merge it into
     810             :     // BValNo.
     811             :     SlotIndex DefIdx = UseIdx.getRegSlot();
     812             :     VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
     813           1 :     if (!DVNI)
     814           0 :       continue;
     815             :     LLVM_DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
     816             :     assert(DVNI->def == DefIdx);
     817           1 :     BValNo = IntB.MergeValueNumberInto(DVNI, BValNo);
     818           1 :     for (LiveInterval::SubRange &S : IntB.subranges()) {
     819           0 :       VNInfo *SubDVNI = S.getVNInfoAt(DefIdx);
     820           0 :       if (!SubDVNI)
     821           0 :         continue;
     822             :       VNInfo *SubBValNo = S.getVNInfoAt(CopyIdx);
     823             :       assert(SubBValNo->def == CopyIdx);
     824           0 :       S.MergeValueNumberInto(SubDVNI, SubBValNo);
     825             :     }
     826             : 
     827           1 :     deleteInstr(UseMI);
     828             :   }
     829             : 
     830             :   // Extend BValNo by merging in IntA live segments of AValNo. Val# definition
     831             :   // is updated.
     832          49 :   BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
     833          49 :   if (IntB.hasSubRanges()) {
     834           0 :     if (!IntA.hasSubRanges()) {
     835           0 :       LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntA.reg);
     836           0 :       IntA.createSubRangeFrom(Allocator, Mask, IntA);
     837             :     }
     838             :     SlotIndex AIdx = CopyIdx.getRegSlot(true);
     839           0 :     for (LiveInterval::SubRange &SA : IntA.subranges()) {
     840           0 :       VNInfo *ASubValNo = SA.getVNInfoAt(AIdx);
     841             :       assert(ASubValNo != nullptr);
     842             : 
     843           0 :       IntB.refineSubRanges(Allocator, SA.LaneMask,
     844           0 :           [&Allocator,&SA,CopyIdx,ASubValNo](LiveInterval::SubRange &SR) {
     845             :         VNInfo *BSubValNo = SR.empty()
     846           0 :           ? SR.getNextValue(CopyIdx, Allocator)
     847           0 :           : SR.getVNInfoAt(CopyIdx);
     848             :         assert(BSubValNo != nullptr);
     849           0 :         addSegmentsWithValNo(SR, BSubValNo, SA, ASubValNo);
     850           0 :       });
     851             :     }
     852             :   }
     853             : 
     854          49 :   BValNo->def = AValNo->def;
     855          49 :   addSegmentsWithValNo(IntB, BValNo, IntA, AValNo);
     856             :   LLVM_DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
     857             : 
     858          49 :   LIS->removeVRegDefAt(IntA, AValNo->def);
     859             : 
     860             :   LLVM_DEBUG(dbgs() << "\t\ttrimmed:  " << IntA << '\n');
     861             :   ++numCommutes;
     862          49 :   return true;
     863             : }
     864             : 
     865             : /// For copy B = A in BB2, if A is defined by A = B in BB0 which is a
     866             : /// predecessor of BB2, and if B is not redefined on the way from A = B
     867             : /// in BB2 to B = A in BB2, B = A in BB2 is partially redundant if the
     868             : /// execution goes through the path from BB0 to BB2. We may move B = A
     869             : /// to the predecessor without such reversed copy.
     870             : /// So we will transform the program from:
     871             : ///   BB0:
     872             : ///      A = B;    BB1:
     873             : ///       ...         ...
     874             : ///     /     \      /
     875             : ///             BB2:
     876             : ///               ...
     877             : ///               B = A;
     878             : ///
     879             : /// to:
     880             : ///
     881             : ///   BB0:         BB1:
     882             : ///      A = B;        ...
     883             : ///       ...          B = A;
     884             : ///     /     \       /
     885             : ///             BB2:
     886             : ///               ...
     887             : ///
     888             : /// A special case is when BB0 and BB2 are the same BB which is the only
     889             : /// BB in a loop:
     890             : ///   BB1:
     891             : ///        ...
     892             : ///   BB0/BB2:  ----
     893             : ///        B = A;   |
     894             : ///        ...      |
     895             : ///        A = B;   |
     896             : ///          |-------
     897             : ///          |
     898             : /// We may hoist B = A from BB0/BB2 to BB1.
     899             : ///
     900             : /// The major preconditions for correctness to remove such partial
     901             : /// redundancy include:
     902             : /// 1. A in B = A in BB2 is defined by a PHI in BB2, and one operand of
     903             : ///    the PHI is defined by the reversed copy A = B in BB0.
     904             : /// 2. No B is referenced from the start of BB2 to B = A.
     905             : /// 3. No B is defined from A = B to the end of BB0.
     906             : /// 4. BB1 has only one successor.
     907             : ///
     908             : /// 2 and 4 implicitly ensure B is not live at the end of BB1.
     909             : /// 4 guarantees BB2 is hotter than BB1, so we can only move a copy to a
     910             : /// colder place, which not only prevent endless loop, but also make sure
     911             : /// the movement of copy is beneficial.
     912       54874 : bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
     913             :                                                 MachineInstr &CopyMI) {
     914             :   assert(!CP.isPhys());
     915             :   if (!CopyMI.isFullCopy())
     916             :     return false;
     917             : 
     918       54874 :   MachineBasicBlock &MBB = *CopyMI.getParent();
     919       54874 :   if (MBB.isEHPad())
     920             :     return false;
     921             : 
     922       54848 :   if (MBB.pred_size() != 2)
     923             :     return false;
     924             : 
     925             :   LiveInterval &IntA =
     926        9378 :       LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
     927             :   LiveInterval &IntB =
     928        9378 :       LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
     929             : 
     930             :   // A is defined by PHI at the entry of MBB.
     931        9378 :   SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
     932        9378 :   VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx);
     933             :   assert(AValNo && !AValNo->isUnused() && "COPY source not live");
     934        9378 :   if (!AValNo->isPHIDef())
     935             :     return false;
     936             : 
     937             :   // No B is referenced before CopyMI in MBB.
     938       10402 :   if (IntB.overlaps(LIS->getMBBStartIdx(&MBB), CopyIdx))
     939             :     return false;
     940             : 
     941             :   // MBB has two predecessors: one contains A = B so no copy will be inserted
     942             :   // for it. The other one will have a copy moved from MBB.
     943             :   bool FoundReverseCopy = false;
     944             :   MachineBasicBlock *CopyLeftBB = nullptr;
     945       15204 :   for (MachineBasicBlock *Pred : MBB.predecessors()) {
     946       20272 :     VNInfo *PVal = IntA.getVNInfoBefore(LIS->getMBBEndIdx(Pred));
     947       10136 :     MachineInstr *DefMI = LIS->getInstructionFromIndex(PVal->def);
     948       15861 :     if (!DefMI || !DefMI->isFullCopy()) {
     949             :       CopyLeftBB = Pred;
     950        5725 :       continue;
     951             :     }
     952             :     // Check DefMI is a reverse copy and it is in BB Pred.
     953       13122 :     if (DefMI->getOperand(0).getReg() != IntA.reg ||
     954        8933 :         DefMI->getOperand(1).getReg() != IntB.reg ||
     955         111 :         DefMI->getParent() != Pred) {
     956             :       CopyLeftBB = Pred;
     957        4300 :       continue;
     958             :     }
     959             :     // If there is any other def of B after DefMI and before the end of Pred,
     960             :     // we need to keep the copy of B = A at the end of Pred if we remove
     961             :     // B = A from MBB.
     962             :     bool ValB_Changed = false;
     963        1027 :     for (auto VNI : IntB.valnos) {
     964         458 :       if (VNI->isUnused())
     965           0 :         continue;
     966         530 :       if (PVal->def < VNI->def && VNI->def < LIS->getMBBEndIdx(Pred)) {
     967             :         ValB_Changed = true;
     968             :         break;
     969             :       }
     970             :     }
     971         111 :     if (ValB_Changed) {
     972             :       CopyLeftBB = Pred;
     973           0 :       continue;
     974             :     }
     975             :     FoundReverseCopy = true;
     976             :   }
     977             : 
     978             :   // If no reverse copy is found in predecessors, nothing to do.
     979        5068 :   if (!FoundReverseCopy)
     980             :     return false;
     981             : 
     982             :   // If CopyLeftBB is nullptr, it means every predecessor of MBB contains
     983             :   // reverse copy, CopyMI can be removed trivially if only IntA/IntB is updated.
     984             :   // If CopyLeftBB is not nullptr, move CopyMI from MBB to CopyLeftBB and
     985             :   // update IntA/IntB.
     986             :   //
     987             :   // If CopyLeftBB is not nullptr, ensure CopyLeftBB has a single succ so
     988             :   // MBB is hotter than CopyLeftBB.
     989         222 :   if (CopyLeftBB && CopyLeftBB->succ_size() > 1)
     990             :     return false;
     991             : 
     992             :   // Now (almost sure it's) ok to move copy.
     993          99 :   if (CopyLeftBB) {
     994             :     // Position in CopyLeftBB where we should insert new copy.
     995          99 :     auto InsPos = CopyLeftBB->getFirstTerminator();
     996             : 
     997             :     // Make sure that B isn't referenced in the terminators (if any) at the end
     998             :     // of the predecessor since we're about to insert a new definition of B
     999             :     // before them.
    1000          99 :     if (InsPos != CopyLeftBB->end()) {
    1001          84 :       SlotIndex InsPosIdx = LIS->getInstructionIndex(*InsPos).getRegSlot(true);
    1002          84 :       if (IntB.overlaps(InsPosIdx, LIS->getMBBEndIdx(CopyLeftBB)))
    1003           1 :         return false;
    1004             :     }
    1005             : 
    1006             :     LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to "
    1007             :                       << printMBBReference(*CopyLeftBB) << '\t' << CopyMI);
    1008             : 
    1009             :     // Insert new copy to CopyLeftBB.
    1010         196 :     MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(),
    1011          98 :                                       TII->get(TargetOpcode::COPY), IntB.reg)
    1012          98 :                                   .addReg(IntA.reg);
    1013             :     SlotIndex NewCopyIdx =
    1014         196 :         LIS->InsertMachineInstrInMaps(*NewCopyMI).getRegSlot();
    1015         196 :     IntB.createDeadDef(NewCopyIdx, LIS->getVNInfoAllocator());
    1016          98 :     for (LiveInterval::SubRange &SR : IntB.subranges())
    1017           0 :       SR.createDeadDef(NewCopyIdx, LIS->getVNInfoAllocator());
    1018             : 
    1019             :     // If the newly created Instruction has an address of an instruction that was
    1020             :     // deleted before (object recycled by the allocator) it needs to be removed from
    1021             :     // the deleted list.
    1022             :     ErasedInstrs.erase(NewCopyMI);
    1023             :   } else {
    1024             :     LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from "
    1025             :                       << printMBBReference(MBB) << '\t' << CopyMI);
    1026             :   }
    1027             : 
    1028             :   // Remove CopyMI.
    1029             :   // Note: This is fine to remove the copy before updating the live-ranges.
    1030             :   // While updating the live-ranges, we only look at slot indices and
    1031             :   // never go back to the instruction.
    1032             :   // Mark instructions as deleted.
    1033          98 :   deleteInstr(&CopyMI);
    1034             : 
    1035             :   // Update the liveness.
    1036             :   SmallVector<SlotIndex, 8> EndPoints;
    1037          98 :   VNInfo *BValNo = IntB.Query(CopyIdx).valueOutOrDead();
    1038         196 :   LIS->pruneValue(*static_cast<LiveRange *>(&IntB), CopyIdx.getRegSlot(),
    1039             :                   &EndPoints);
    1040             :   BValNo->markUnused();
    1041             :   // Extend IntB to the EndPoints of its original live interval.
    1042          98 :   LIS->extendToIndices(IntB, EndPoints);
    1043             : 
    1044             :   // Now, do the same for its subranges.
    1045          98 :   for (LiveInterval::SubRange &SR : IntB.subranges()) {
    1046             :     EndPoints.clear();
    1047           0 :     VNInfo *BValNo = SR.Query(CopyIdx).valueOutOrDead();
    1048             :     assert(BValNo && "All sublanes should be live");
    1049           0 :     LIS->pruneValue(SR, CopyIdx.getRegSlot(), &EndPoints);
    1050             :     BValNo->markUnused();
    1051           0 :     LIS->extendToIndices(SR, EndPoints);
    1052             :   }
    1053             : 
    1054             :   // Finally, update the live-range of IntA.
    1055          98 :   shrinkToUses(&IntA);
    1056             :   return true;
    1057             : }
    1058             : 
    1059             : /// Returns true if @p MI defines the full vreg @p Reg, as opposed to just
    1060             : /// defining a subregister.
    1061       33796 : static bool definesFullReg(const MachineInstr &MI, unsigned Reg) {
    1062             :   assert(!TargetRegisterInfo::isPhysicalRegister(Reg) &&
    1063             :          "This code cannot handle physreg aliasing");
    1064       41152 :   for (const MachineOperand &Op : MI.operands()) {
    1065       71270 :     if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
    1066        2452 :       continue;
    1067             :     // Return true if we define the full register or don't care about the value
    1068             :     // inside other subregisters.
    1069       46061 :     if (Op.getSubReg() == 0 || Op.isUndef())
    1070             :       return true;
    1071             :   }
    1072             :   return false;
    1073             : }
    1074             : 
    1075      911993 : bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
    1076             :                                                 MachineInstr *CopyMI,
    1077             :                                                 bool &IsDefCopy) {
    1078      911993 :   IsDefCopy = false;
    1079      911993 :   unsigned SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
    1080      911993 :   unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
    1081      911993 :   unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
    1082      911993 :   unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
    1083      911993 :   if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
    1084             :     return false;
    1085             : 
    1086      568103 :   LiveInterval &SrcInt = LIS->getInterval(SrcReg);
    1087     1136206 :   SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI);
    1088      568103 :   VNInfo *ValNo = SrcInt.Query(CopyIdx).valueIn();
    1089             :   assert(ValNo && "CopyMI input register not live");
    1090     1122962 :   if (ValNo->isPHIDef() || ValNo->isUnused())
    1091             :     return false;
    1092             :   MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
    1093      554859 :   if (!DefMI)
    1094             :     return false;
    1095             :   if (DefMI->isCopyLike()) {
    1096      116394 :     IsDefCopy = true;
    1097      116394 :     return false;
    1098             :   }
    1099      438465 :   if (!TII->isAsCheapAsAMove(*DefMI))
    1100             :     return false;
    1101       49822 :   if (!TII->isTriviallyReMaterializable(*DefMI, AA))
    1102             :     return false;
    1103       33796 :   if (!definesFullReg(*DefMI, SrcReg))
    1104             :     return false;
    1105       32570 :   bool SawStore = false;
    1106       32570 :   if (!DefMI->isSafeToMove(AA, SawStore))
    1107             :     return false;
    1108       32570 :   const MCInstrDesc &MCID = DefMI->getDesc();
    1109       32570 :   if (MCID.getNumDefs() != 1)
    1110             :     return false;
    1111             :   // Only support subregister destinations when the def is read-undef.
    1112       32570 :   MachineOperand &DstOperand = CopyMI->getOperand(0);
    1113       32570 :   unsigned CopyDstReg = DstOperand.getReg();
    1114       32616 :   if (DstOperand.getSubReg() && !DstOperand.isUndef())
    1115             :     return false;
    1116             : 
    1117             :   // If both SrcIdx and DstIdx are set, correct rematerialization would widen
    1118             :   // the register substantially (beyond both source and dest size). This is bad
    1119             :   // for performance since it can cascade through a function, introducing many
    1120             :   // extra spills and fills (e.g. ARM can easily end up copying QQQQPR registers
    1121             :   // around after a few subreg copies).
    1122       32568 :   if (SrcIdx && DstIdx)
    1123             :     return false;
    1124             : 
    1125       32568 :   const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
    1126       32568 :   if (!DefMI->isImplicitDef()) {
    1127       32568 :     if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
    1128             :       unsigned NewDstReg = DstReg;
    1129             : 
    1130       57172 :       unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(),
    1131       28586 :                                               DefMI->getOperand(0).getSubReg());
    1132       28586 :       if (NewDstIdx)
    1133       10093 :         NewDstReg = TRI->getSubReg(DstReg, NewDstIdx);
    1134             : 
    1135             :       // Finally, make sure that the physical subregister that will be
    1136             :       // constructed later is permitted for the instruction.
    1137       57172 :       if (!DefRC->contains(NewDstReg))
    1138             :         return false;
    1139             :     } else {
    1140             :       // Theoretically, some stack frame reference could exist. Just make sure
    1141             :       // it hasn't actually happened.
    1142             :       assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
    1143             :              "Only expect to deal with virtual or physical registers");
    1144             :     }
    1145             :   }
    1146             : 
    1147             :   DebugLoc DL = CopyMI->getDebugLoc();
    1148       32568 :   MachineBasicBlock *MBB = CopyMI->getParent();
    1149             :   MachineBasicBlock::iterator MII =
    1150             :     std::next(MachineBasicBlock::iterator(CopyMI));
    1151       32568 :   TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, *DefMI, *TRI);
    1152             :   MachineInstr &NewMI = *std::prev(MII);
    1153       32568 :   NewMI.setDebugLoc(DL);
    1154             : 
    1155             :   // In a situation like the following:
    1156             :   //     %0:subreg = instr              ; DefMI, subreg = DstIdx
    1157             :   //     %1        = copy %0:subreg ; CopyMI, SrcIdx = 0
    1158             :   // instead of widening %1 to the register class of %0 simply do:
    1159             :   //     %1 = instr
    1160       32568 :   const TargetRegisterClass *NewRC = CP.getNewRC();
    1161       32568 :   if (DstIdx != 0) {
    1162          58 :     MachineOperand &DefMO = NewMI.getOperand(0);
    1163          58 :     if (DefMO.getSubReg() == DstIdx) {
    1164             :       assert(SrcIdx == 0 && CP.isFlipped()
    1165             :              && "Shouldn't have SrcIdx+DstIdx at this point");
    1166          45 :       const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
    1167             :       const TargetRegisterClass *CommonRC =
    1168          45 :         TRI->getCommonSubClass(DefRC, DstRC);
    1169          45 :       if (CommonRC != nullptr) {
    1170             :         NewRC = CommonRC;
    1171             :         DstIdx = 0;
    1172             :         DefMO.setSubReg(0);
    1173             :         DefMO.setIsUndef(false); // Only subregs can have def+undef.
    1174             :       }
    1175             :     }
    1176             :   }
    1177             : 
    1178             :   // CopyMI may have implicit operands, save them so that we can transfer them
    1179             :   // over to the newly materialized instruction after CopyMI is removed.
    1180             :   SmallVector<MachineOperand, 4> ImplicitOps;
    1181       65136 :   ImplicitOps.reserve(CopyMI->getNumOperands() -
    1182       32568 :                       CopyMI->getDesc().getNumOperands());
    1183       32569 :   for (unsigned I = CopyMI->getDesc().getNumOperands(),
    1184       32568 :                 E = CopyMI->getNumOperands();
    1185       32569 :        I != E; ++I) {
    1186           1 :     MachineOperand &MO = CopyMI->getOperand(I);
    1187           1 :     if (MO.isReg()) {
    1188             :       assert(MO.isImplicit() && "No explicit operands after implict operands.");
    1189             :       // Discard VReg implicit defs.
    1190           2 :       if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
    1191           1 :         ImplicitOps.push_back(MO);
    1192             :     }
    1193             :   }
    1194             : 
    1195       32568 :   LIS->ReplaceMachineInstrInMaps(*CopyMI, NewMI);
    1196       32568 :   CopyMI->eraseFromParent();
    1197       32568 :   ErasedInstrs.insert(CopyMI);
    1198             : 
    1199             :   // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
    1200             :   // We need to remember these so we can add intervals once we insert
    1201             :   // NewMI into SlotIndexes.
    1202             :   SmallVector<unsigned, 4> NewMIImplDefs;
    1203       43647 :   for (unsigned i = NewMI.getDesc().getNumOperands(),
    1204       32568 :                 e = NewMI.getNumOperands();
    1205       43647 :        i != e; ++i) {
    1206       11079 :     MachineOperand &MO = NewMI.getOperand(i);
    1207       22158 :     if (MO.isReg() && MO.isDef()) {
    1208             :       assert(MO.isImplicit() && MO.isDead() &&
    1209             :              TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
    1210       10016 :       NewMIImplDefs.push_back(MO.getReg());
    1211             :     }
    1212             :   }
    1213             : 
    1214       32568 :   if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
    1215        3982 :     unsigned NewIdx = NewMI.getOperand(0).getSubReg();
    1216             : 
    1217        3982 :     if (DefRC != nullptr) {
    1218        3982 :       if (NewIdx)
    1219         919 :         NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx);
    1220             :       else
    1221        3063 :         NewRC = TRI->getCommonSubClass(NewRC, DefRC);
    1222             :       assert(NewRC && "subreg chosen for remat incompatible with instruction");
    1223             :     }
    1224             :     // Remap subranges to new lanemask and change register class.
    1225        3982 :     LiveInterval &DstInt = LIS->getInterval(DstReg);
    1226        3984 :     for (LiveInterval::SubRange &SR : DstInt.subranges()) {
    1227           4 :       SR.LaneMask = TRI->composeSubRegIndexLaneMask(DstIdx, SR.LaneMask);
    1228             :     }
    1229        3982 :     MRI->setRegClass(DstReg, NewRC);
    1230             : 
    1231             :     // Update machine operands and add flags.
    1232        3982 :     updateRegDefsUses(DstReg, DstReg, DstIdx);
    1233        3982 :     NewMI.getOperand(0).setSubReg(NewIdx);
    1234             :     // updateRegDefUses can add an "undef" flag to the definition, since
    1235             :     // it will replace DstReg with DstReg.DstIdx. If NewIdx is 0, make
    1236             :     // sure that "undef" is not set.
    1237        3982 :     if (NewIdx == 0)
    1238        3063 :       NewMI.getOperand(0).setIsUndef(false);
    1239             :     // Add dead subregister definitions if we are defining the whole register
    1240             :     // but only part of it is live.
    1241             :     // This could happen if the rematerialization instruction is rematerializing
    1242             :     // more than actually is used in the register.
    1243             :     // An example would be:
    1244             :     // %1 = LOAD CONSTANTS 5, 8 ; Loading both 5 and 8 in different subregs
    1245             :     // ; Copying only part of the register here, but the rest is undef.
    1246             :     // %2:sub_16bit<def, read-undef> = COPY %1:sub_16bit
    1247             :     // ==>
    1248             :     // ; Materialize all the constants but only using one
    1249             :     // %2 = LOAD_CONSTANTS 5, 8
    1250             :     //
    1251             :     // at this point for the part that wasn't defined before we could have
    1252             :     // subranges missing the definition.
    1253        3982 :     if (NewIdx == 0 && DstInt.hasSubRanges()) {
    1254           1 :       SlotIndex CurrIdx = LIS->getInstructionIndex(NewMI);
    1255             :       SlotIndex DefIndex =
    1256           2 :           CurrIdx.getRegSlot(NewMI.getOperand(0).isEarlyClobber());
    1257           1 :       LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(DstReg);
    1258           1 :       VNInfo::Allocator& Alloc = LIS->getVNInfoAllocator();
    1259           2 :       for (LiveInterval::SubRange &SR : DstInt.subranges()) {
    1260           1 :         if (!SR.liveAt(DefIndex))
    1261           0 :           SR.createDeadDef(DefIndex, Alloc);
    1262             :         MaxMask &= ~SR.LaneMask;
    1263             :       }
    1264           1 :       if (MaxMask.any()) {
    1265           0 :         LiveInterval::SubRange *SR = DstInt.createSubRange(Alloc, MaxMask);
    1266           0 :         SR->createDeadDef(DefIndex, Alloc);
    1267             :       }
    1268             :     }
    1269             : 
    1270             :     // Make sure that the subrange for resultant undef is removed
    1271             :     // For example:
    1272             :     //   %1:sub1<def,read-undef> = LOAD CONSTANT 1
    1273             :     //   %2 = COPY %1
    1274             :     // ==>
    1275             :     //   %2:sub1<def, read-undef> = LOAD CONSTANT 1
    1276             :     //     ; Correct but need to remove the subrange for %2:sub0
    1277             :     //     ; as it is now undef
    1278        3982 :     if (NewIdx != 0 && DstInt.hasSubRanges()) {
    1279             :       // The affected subregister segments can be removed.
    1280           1 :       SlotIndex CurrIdx = LIS->getInstructionIndex(NewMI);
    1281           1 :       LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(NewIdx);
    1282             :       bool UpdatedSubRanges = false;
    1283           3 :       for (LiveInterval::SubRange &SR : DstInt.subranges()) {
    1284           2 :         if ((SR.LaneMask & DstMask).none()) {
    1285             :           LLVM_DEBUG(dbgs()
    1286             :                      << "Removing undefined SubRange "
    1287             :                      << PrintLaneMask(SR.LaneMask) << " : " << SR << "\n");
    1288             :           // VNI is in ValNo - remove any segments in this SubRange that have this ValNo
    1289           2 :           if (VNInfo *RmValNo = SR.getVNInfoAt(CurrIdx.getRegSlot())) {
    1290           1 :             SR.removeValNo(RmValNo);
    1291             :             UpdatedSubRanges = true;
    1292             :           }
    1293             :         }
    1294             :       }
    1295           1 :       if (UpdatedSubRanges)
    1296           1 :         DstInt.removeEmptySubRanges();
    1297             :     }
    1298       28586 :   } else if (NewMI.getOperand(0).getReg() != CopyDstReg) {
    1299             :     // The New instruction may be defining a sub-register of what's actually
    1300             :     // been asked for. If so it must implicitly define the whole thing.
    1301             :     assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
    1302             :            "Only expect virtual or physical registers in remat");
    1303             :     NewMI.getOperand(0).setIsDead(true);
    1304       11057 :     NewMI.addOperand(MachineOperand::CreateReg(
    1305             :         CopyDstReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/));
    1306             :     // Record small dead def live-ranges for all the subregisters
    1307             :     // of the destination register.
    1308             :     // Otherwise, variables that live through may miss some
    1309             :     // interferences, thus creating invalid allocation.
    1310             :     // E.g., i386 code:
    1311             :     // %1 = somedef ; %1 GR8
    1312             :     // %2 = remat ; %2 GR32
    1313             :     // CL = COPY %2.sub_8bit
    1314             :     // = somedef %1 ; %1 GR8
    1315             :     // =>
    1316             :     // %1 = somedef ; %1 GR8
    1317             :     // dead ECX = remat ; implicit-def CL
    1318             :     // = somedef %1 ; %1 GR8
    1319             :     // %1 will see the inteferences with CL but not with CH since
    1320             :     // no live-ranges would have been created for ECX.
    1321             :     // Fix that!
    1322       11057 :     SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
    1323       11057 :     for (MCRegUnitIterator Units(NewMI.getOperand(0).getReg(), TRI);
    1324       36319 :          Units.isValid(); ++Units)
    1325       50524 :       if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
    1326        7413 :         LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
    1327             :   }
    1328             : 
    1329       65136 :   if (NewMI.getOperand(0).getSubReg())
    1330             :     NewMI.getOperand(0).setIsUndef();
    1331             : 
    1332             :   // Transfer over implicit operands to the rematerialized instruction.
    1333       32570 :   for (MachineOperand &MO : ImplicitOps)
    1334           1 :     NewMI.addOperand(MO);
    1335             : 
    1336       32568 :   SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
    1337       42584 :   for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
    1338       20032 :     unsigned Reg = NewMIImplDefs[i];
    1339       30048 :     for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
    1340       20032 :       if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
    1341          13 :         LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
    1342             :   }
    1343             : 
    1344             :   LLVM_DEBUG(dbgs() << "Remat: " << NewMI);
    1345             :   ++NumReMats;
    1346             : 
    1347             :   // The source interval can become smaller because we removed a use.
    1348       32568 :   shrinkToUses(&SrcInt, &DeadDefs);
    1349       32568 :   if (!DeadDefs.empty()) {
    1350             :     // If the virtual SrcReg is completely eliminated, update all DBG_VALUEs
    1351             :     // to describe DstReg instead.
    1352       47604 :     for (MachineOperand &UseMO : MRI->use_operands(SrcReg)) {
    1353         128 :       MachineInstr *UseMI = UseMO.getParent();
    1354         128 :       if (UseMI->isDebugValue()) {
    1355         128 :         UseMO.setReg(DstReg);
    1356             :         // Move the debug value directly after the def of the rematerialized
    1357             :         // value in DstReg.
    1358         256 :         MBB->splice(std::next(NewMI.getIterator()), UseMI->getParent(), UseMI);
    1359             :         LLVM_DEBUG(dbgs() << "\t\tupdated: " << *UseMI);
    1360             :       }
    1361             :     }
    1362       23738 :     eliminateDeadDefs();
    1363             :   }
    1364             : 
    1365             :   return true;
    1366             : }
    1367             : 
    1368      708026 : bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
    1369             :   // ProcessImpicitDefs may leave some copies of <undef> values, it only removes
    1370             :   // local variables. When we have a copy like:
    1371             :   //
    1372             :   //   %1 = COPY undef %2
    1373             :   //
    1374             :   // We delete the copy and remove the corresponding value number from %1.
    1375             :   // Any uses of that value number are marked as <undef>.
    1376             : 
    1377             :   // Note that we do not query CoalescerPair here but redo isMoveInstr as the
    1378             :   // CoalescerPair may have a new register class with adjusted subreg indices
    1379             :   // at this point.
    1380             :   unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
    1381      708026 :   isMoveInstr(*TRI, CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
    1382             : 
    1383      708026 :   SlotIndex Idx = LIS->getInstructionIndex(*CopyMI);
    1384      708026 :   const LiveInterval &SrcLI = LIS->getInterval(SrcReg);
    1385             :   // CopyMI is undef iff SrcReg is not live before the instruction.
    1386      708026 :   if (SrcSubIdx != 0 && SrcLI.hasSubRanges()) {
    1387       75602 :     LaneBitmask SrcMask = TRI->getSubRegIndexLaneMask(SrcSubIdx);
    1388      175857 :     for (const LiveInterval::SubRange &SR : SrcLI.subranges()) {
    1389      175857 :       if ((SR.LaneMask & SrcMask).none())
    1390      100255 :         continue;
    1391       75602 :       if (SR.liveAt(Idx))
    1392             :         return false;
    1393             :     }
    1394      632424 :   } else if (SrcLI.liveAt(Idx))
    1395             :     return false;
    1396             : 
    1397             :   LLVM_DEBUG(dbgs() << "\tEliminating copy of <undef> value\n");
    1398             : 
    1399             :   // Remove any DstReg segments starting at the instruction.
    1400           1 :   LiveInterval &DstLI = LIS->getInterval(DstReg);
    1401             :   SlotIndex RegIndex = Idx.getRegSlot();
    1402             :   // Remove value or merge with previous one in case of a subregister def.
    1403           1 :   if (VNInfo *PrevVNI = DstLI.getVNInfoAt(Idx)) {
    1404             :     VNInfo *VNI = DstLI.getVNInfoAt(RegIndex);
    1405           0 :     DstLI.MergeValueNumberInto(VNI, PrevVNI);
    1406             : 
    1407             :     // The affected subregister segments can be removed.
    1408           0 :     LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(DstSubIdx);
    1409           0 :     for (LiveInterval::SubRange &SR : DstLI.subranges()) {
    1410           0 :       if ((SR.LaneMask & DstMask).none())
    1411           0 :         continue;
    1412             : 
    1413           0 :       VNInfo *SVNI = SR.getVNInfoAt(RegIndex);
    1414             :       assert(SVNI != nullptr && SlotIndex::isSameInstr(SVNI->def, RegIndex));
    1415           0 :       SR.removeValNo(SVNI);
    1416             :     }
    1417           0 :     DstLI.removeEmptySubRanges();
    1418             :   } else
    1419           1 :     LIS->removeVRegDefAt(DstLI, RegIndex);
    1420             : 
    1421             :   // Mark uses as undef.
    1422           4 :   for (MachineOperand &MO : MRI->reg_nodbg_operands(DstReg)) {
    1423           2 :     if (MO.isDef() /*|| MO.isUndef()*/)
    1424           2 :       continue;
    1425           1 :     const MachineInstr &MI = *MO.getParent();
    1426           2 :     SlotIndex UseIdx = LIS->getInstructionIndex(MI);
    1427           2 :     LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
    1428             :     bool isLive;
    1429           1 :     if (!UseMask.all() && DstLI.hasSubRanges()) {
    1430             :       isLive = false;
    1431           0 :       for (const LiveInterval::SubRange &SR : DstLI.subranges()) {
    1432           0 :         if ((SR.LaneMask & UseMask).none())
    1433           0 :           continue;
    1434           0 :         if (SR.liveAt(UseIdx)) {
    1435             :           isLive = true;
    1436             :           break;
    1437             :         }
    1438             :       }
    1439             :     } else
    1440           1 :       isLive = DstLI.liveAt(UseIdx);
    1441           1 :     if (isLive)
    1442           0 :       continue;
    1443             :     MO.setIsUndef(true);
    1444             :     LLVM_DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI);
    1445             :   }
    1446             : 
    1447             :   // A def of a subregister may be a use of the other subregisters, so
    1448             :   // deleting a def of a subregister may also remove uses. Since CopyMI
    1449             :   // is still part of the function (but about to be erased), mark all
    1450             :   // defs of DstReg in it as <undef>, so that shrinkToUses would
    1451             :   // ignore them.
    1452           5 :   for (MachineOperand &MO : CopyMI->operands())
    1453           4 :     if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
    1454             :       MO.setIsUndef(true);
    1455           1 :   LIS->shrinkToUses(&DstLI);
    1456             : 
    1457           1 :   return true;
    1458             : }
    1459             : 
    1460      382088 : void RegisterCoalescer::addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
    1461             :                                      MachineOperand &MO, unsigned SubRegIdx) {
    1462      382088 :   LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx);
    1463      382088 :   if (MO.isDef())
    1464             :     Mask = ~Mask;
    1465             :   bool IsUndef = true;
    1466      959489 :   for (const LiveInterval::SubRange &S : Int.subranges()) {
    1467      959439 :     if ((S.LaneMask & Mask).none())
    1468             :       continue;
    1469      417530 :     if (S.liveAt(UseIdx)) {
    1470             :       IsUndef = false;
    1471             :       break;
    1472             :     }
    1473             :   }
    1474      382088 :   if (IsUndef) {
    1475             :     MO.setIsUndef(true);
    1476             :     // We found out some subregister use is actually reading an undefined
    1477             :     // value. In some cases the whole vreg has become undefined at this
    1478             :     // point so we have to potentially shrink the main range if the
    1479             :     // use was ending a live segment there.
    1480          50 :     LiveQueryResult Q = Int.Query(UseIdx);
    1481          50 :     if (Q.valueOut() == nullptr)
    1482           0 :       ShrinkMainRange = true;
    1483             :   }
    1484      382088 : }
    1485             : 
    1486      667786 : void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
    1487             :                                           unsigned DstReg,
    1488             :                                           unsigned SubIdx) {
    1489             :   bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
    1490      667786 :   LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg);
    1491             : 
    1492      631302 :   if (DstInt && DstInt->hasSubRanges() && DstReg != SrcReg) {
    1493      791404 :     for (MachineOperand &MO : MRI->reg_operands(DstReg)) {
    1494             :       unsigned SubReg = MO.getSubReg();
    1495     1065763 :       if (SubReg == 0 || MO.isUndef())
    1496      409728 :         continue;
    1497      309922 :       MachineInstr &MI = *MO.getParent();
    1498      309922 :       if (MI.isDebugValue())
    1499           0 :         continue;
    1500      619844 :       SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot(true);
    1501      309922 :       addUndefFlag(*DstInt, UseIdx, MO, SubReg);
    1502             :     }
    1503             :   }
    1504             : 
    1505             :   SmallPtrSet<MachineInstr*, 8> Visited;
    1506             :   for (MachineRegisterInfo::reg_instr_iterator
    1507      667786 :        I = MRI->reg_instr_begin(SrcReg), E = MRI->reg_instr_end();
    1508     1625970 :        I != E; ) {
    1509             :     MachineInstr *UseMI = &*(I++);
    1510             : 
    1511             :     // Each instruction can only be rewritten once because sub-register
    1512             :     // composition is not always idempotent. When SrcReg != DstReg, rewriting
    1513             :     // the UseMI operands removes them from the SrcReg use-def chain, but when
    1514             :     // SrcReg is DstReg we could encounter UseMI twice if it has multiple
    1515             :     // operands mentioning the virtual register.
    1516      959872 :     if (SrcReg == DstReg && !Visited.insert(UseMI).second)
    1517        1688 :       continue;
    1518             : 
    1519             :     SmallVector<unsigned,8> Ops;
    1520             :     bool Reads, Writes;
    1521     1912992 :     std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
    1522             : 
    1523             :     // If SrcReg wasn't read, it may still be the case that DstReg is live-in
    1524             :     // because SrcReg is a sub-register.
    1525     2027272 :     if (DstInt && !Reads && SubIdx && !UseMI->isDebugValue())
    1526      343656 :       Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));
    1527             : 
    1528             :     // Replace SrcReg with DstReg in all UseMI operands.
    1529     1996672 :     for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
    1530     2080352 :       MachineOperand &MO = UseMI->getOperand(Ops[i]);
    1531             : 
    1532             :       // Adjust <undef> flags in case of sub-register joins. We don't want to
    1533             :       // turn a full def into a read-modify-write sub-register def and vice
    1534             :       // versa.
    1535     1372974 :       if (SubIdx && MO.isDef())
    1536      191034 :         MO.setIsUndef(!Reads);
    1537             : 
    1538             :       // A subreg use of a partially undef (super) register may be a complete
    1539             :       // undef use now and then has to be marked that way.
    1540     1372974 :       if (SubIdx != 0 && MO.isUse() && MRI->shouldTrackSubRegLiveness(DstReg)) {
    1541       72166 :         if (!DstInt->hasSubRanges()) {
    1542           1 :           BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
    1543           1 :           LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(DstInt->reg);
    1544           1 :           DstInt->createSubRangeFrom(Allocator, Mask, *DstInt);
    1545             :         }
    1546             :         SlotIndex MIIdx = UseMI->isDebugValue()
    1547           2 :                               ? LIS->getSlotIndexes()->getIndexBefore(*UseMI)
    1548       72168 :                               : LIS->getInstructionIndex(*UseMI);
    1549       72166 :         SlotIndex UseIdx = MIIdx.getRegSlot(true);
    1550       72166 :         addUndefFlag(*DstInt, UseIdx, MO, SubIdx);
    1551             :       }
    1552             : 
    1553     1040176 :       if (DstIsPhys)
    1554       57604 :         MO.substPhysReg(DstReg, *TRI);
    1555             :       else
    1556      982572 :         MO.substVirtReg(DstReg, SubIdx, *TRI);
    1557             :     }
    1558             : 
    1559             :     LLVM_DEBUG({
    1560             :       dbgs() << "\t\tupdated: ";
    1561             :       if (!UseMI->isDebugValue())
    1562             :         dbgs() << LIS->getInstructionIndex(*UseMI) << "\t";
    1563             :       dbgs() << *UseMI;
    1564             :     });
    1565             :   }
    1566      667786 : }
    1567             : 
    1568      867750 : bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
    1569             :   // Always join simple intervals that are defined by a single copy from a
    1570             :   // reserved register. This doesn't increase register pressure, so it is
    1571             :   // always beneficial.
    1572     1735500 :   if (!MRI->isReserved(CP.getDstReg())) {
    1573             :     LLVM_DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
    1574             :     return false;
    1575             :   }
    1576             : 
    1577       38789 :   LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
    1578       38789 :   if (JoinVInt.containsOneValue())
    1579             :     return true;
    1580             : 
    1581             :   LLVM_DEBUG(
    1582             :       dbgs() << "\tCannot join complex intervals into reserved register.\n");
    1583             :   return false;
    1584             : }
    1585             : 
    1586     1623418 : bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
    1587     1623418 :   Again = false;
    1588             :   LLVM_DEBUG(dbgs() << LIS->getInstructionIndex(*CopyMI) << '\t' << *CopyMI);
    1589             : 
    1590     1623418 :   CoalescerPair CP(*TRI);
    1591     1623418 :   if (!CP.setRegisters(CopyMI)) {
    1592             :     LLVM_DEBUG(dbgs() << "\tNot coalescable.\n");
    1593             :     return false;
    1594             :   }
    1595             : 
    1596     1577301 :   if (CP.getNewRC()) {
    1597      709551 :     auto SrcRC = MRI->getRegClass(CP.getSrcReg());
    1598      709551 :     auto DstRC = MRI->getRegClass(CP.getDstReg());
    1599      709551 :     unsigned SrcIdx = CP.getSrcIdx();
    1600      709551 :     unsigned DstIdx = CP.getDstIdx();
    1601      709551 :     if (CP.isFlipped()) {
    1602             :       std::swap(SrcIdx, DstIdx);
    1603             :       std::swap(SrcRC, DstRC);
    1604             :     }
    1605     1419102 :     if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx,
    1606      709551 :                              CP.getNewRC(), *LIS)) {
    1607             :       LLVM_DEBUG(dbgs() << "\tSubtarget bailed on coalescing.\n");
    1608             :       return false;
    1609             :     }
    1610             :   }
    1611             : 
    1612             :   // Dead code elimination. This really should be handled by MachineDCE, but
    1613             :   // sometimes dead copies slip through, and we can't generate invalid live
    1614             :   // ranges.
    1615     1576002 :   if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
    1616             :     LLVM_DEBUG(dbgs() << "\tCopy is dead.\n");
    1617         226 :     DeadDefs.push_back(CopyMI);
    1618         226 :     eliminateDeadDefs();
    1619         226 :     return true;
    1620             :   }
    1621             : 
    1622             :   // Eliminate undefs.
    1623     1575776 :   if (!CP.isPhys() && eliminateUndefCopy(CopyMI)) {
    1624           1 :     deleteInstr(CopyMI);
    1625           1 :     return false;  // Not coalescable.
    1626             :   }
    1627             : 
    1628             :   // Coalesced copies are normally removed immediately, but transformations
    1629             :   // like removeCopyByCommutingDef() can inadvertently create identity copies.
    1630             :   // When that happens, just join the values and remove the copy.
    1631     1575775 :   if (CP.getSrcReg() == CP.getDstReg()) {
    1632           0 :     LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
    1633             :     LLVM_DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
    1634           0 :     const SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI);
    1635           0 :     LiveQueryResult LRQ = LI.Query(CopyIdx);
    1636           0 :     if (VNInfo *DefVNI = LRQ.valueDefined()) {
    1637             :       VNInfo *ReadVNI = LRQ.valueIn();
    1638             :       assert(ReadVNI && "No value before copy and no <undef> flag.");
    1639             :       assert(ReadVNI != DefVNI && "Cannot read and define the same value.");
    1640           0 :       LI.MergeValueNumberInto(DefVNI, ReadVNI);
    1641             : 
    1642             :       // Process subregister liveranges.
    1643           0 :       for (LiveInterval::SubRange &S : LI.subranges()) {
    1644           0 :         LiveQueryResult SLRQ = S.Query(CopyIdx);
    1645           0 :         if (VNInfo *SDefVNI = SLRQ.valueDefined()) {
    1646             :           VNInfo *SReadVNI = SLRQ.valueIn();
    1647           0 :           S.MergeValueNumberInto(SDefVNI, SReadVNI);
    1648             :         }
    1649             :       }
    1650             :       LLVM_DEBUG(dbgs() << "\tMerged values:          " << LI << '\n');
    1651             :     }
    1652           0 :     deleteInstr(CopyMI);
    1653             :     return true;
    1654             :   }
    1655             : 
    1656             :   // Enforce policies.
    1657     1575775 :   if (CP.isPhys()) {
    1658             :     LLVM_DEBUG(dbgs() << "\tConsidering merging "
    1659             :                       << printReg(CP.getSrcReg(), TRI) << " with "
    1660             :                       << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n');
    1661      867750 :     if (!canJoinPhys(CP)) {
    1662             :       // Before giving up coalescing, if definition of source is defined by
    1663             :       // trivial computation, try rematerializing it.
    1664             :       bool IsDefCopy;
    1665      829507 :       if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
    1666             :         return true;
    1667      800921 :       if (IsDefCopy)
    1668       93060 :         Again = true;  // May be possible to coalesce later.
    1669             :       return false;
    1670             :     }
    1671             :   } else {
    1672             :     // When possible, let DstReg be the larger interval.
    1673     1115594 :     if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).size() >
    1674      407569 :                            LIS->getInterval(CP.getDstReg()).size())
    1675       88077 :       CP.flip();
    1676             : 
    1677             :     LLVM_DEBUG({
    1678             :       dbgs() << "\tConsidering merging to "
    1679             :              << TRI->getRegClassName(CP.getNewRC()) << " with ";
    1680             :       if (CP.getDstIdx() && CP.getSrcIdx())
    1681             :         dbgs() << printReg(CP.getDstReg()) << " in "
    1682             :                << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
    1683             :                << printReg(CP.getSrcReg()) << " in "
    1684             :                << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
    1685             :       else
    1686             :         dbgs() << printReg(CP.getSrcReg(), TRI) << " in "
    1687             :                << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
    1688             :     });
    1689             :   }
    1690             : 
    1691      746268 :   ShrinkMask = LaneBitmask::getNone();
    1692      746268 :   ShrinkMainRange = false;
    1693             : 
    1694             :   // Okay, attempt to join these two intervals.  On failure, this returns false.
    1695             :   // Otherwise, if one of the intervals being joined is a physreg, this method
    1696             :   // always canonicalizes DstInt to be it.  The output "SrcInt" will not have
    1697             :   // been modified, so we can use this information below to update aliases.
    1698      746268 :   if (!joinIntervals(CP)) {
    1699             :     // Coalescing failed.
    1700             : 
    1701             :     // If definition of source is defined by trivial computation, try
    1702             :     // rematerializing it.
    1703             :     bool IsDefCopy;
    1704       82486 :     if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
    1705             :       return true;
    1706             : 
    1707             :     // If we can eliminate the copy without merging the live segments, do so
    1708             :     // now.
    1709       78504 :     if (!CP.isPartial() && !CP.isPhys()) {
    1710      109853 :       if (adjustCopiesBackFrom(CP, CopyMI) ||
    1711       54923 :           removeCopyByCommutingDef(CP, CopyMI)) {
    1712          56 :         deleteInstr(CopyMI);
    1713             :         LLVM_DEBUG(dbgs() << "\tTrivial!\n");
    1714          56 :         return true;
    1715             :       }
    1716             :     }
    1717             : 
    1718             :     // Try and see if we can partially eliminate the copy by moving the copy to
    1719             :     // its predecessor.
    1720       78448 :     if (!CP.isPartial() && !CP.isPhys())
    1721       54874 :       if (removePartialRedundancy(CP, *CopyMI))
    1722             :         return true;
    1723             : 
    1724             :     // Otherwise, we are unable to join the intervals.
    1725             :     LLVM_DEBUG(dbgs() << "\tInterference!\n");
    1726       78350 :     Again = true;  // May be possible to coalesce later.
    1727       78350 :     return false;
    1728             :   }
    1729             : 
    1730             :   // Coalescing to a virtual register that is of a sub-register class of the
    1731             :   // other. Make sure the resulting register is set to the right register class.
    1732      663782 :   if (CP.isCrossClass()) {
    1733             :     ++numCrossRCs;
    1734      294669 :     MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
    1735             :   }
    1736             : 
    1737             :   // Removing sub-register copies can ease the register class constraints.
    1738             :   // Make sure we attempt to inflate the register class of DstReg.
    1739      663782 :   if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
    1740       41664 :     InflateRegs.push_back(CP.getDstReg());
    1741             : 
    1742             :   // CopyMI has been erased by joinIntervals at this point. Remove it from
    1743             :   // ErasedInstrs since copyCoalesceWorkList() won't add a successful join back
    1744             :   // to the work list. This keeps ErasedInstrs from growing needlessly.
    1745      663782 :   ErasedInstrs.erase(CopyMI);
    1746             : 
    1747             :   // Rewrite all SrcReg operands to DstReg.
    1748             :   // Also update DstReg operands to include DstIdx if it is set.
    1749      663782 :   if (CP.getDstIdx())
    1750          22 :     updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
    1751      663782 :   updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
    1752             : 
    1753             :   // Shrink subregister ranges if necessary.
    1754      663782 :   if (ShrinkMask.any()) {
    1755          37 :     LiveInterval &LI = LIS->getInterval(CP.getDstReg());
    1756         125 :     for (LiveInterval::SubRange &S : LI.subranges()) {
    1757          88 :       if ((S.LaneMask & ShrinkMask).none())
    1758          43 :         continue;
    1759             :       LLVM_DEBUG(dbgs() << "Shrink LaneUses (Lane " << PrintLaneMask(S.LaneMask)
    1760             :                         << ")\n");
    1761          45 :       LIS->shrinkToUses(S, LI.reg);
    1762             :     }
    1763          37 :     LI.removeEmptySubRanges();
    1764             :   }
    1765      663782 :   if (ShrinkMainRange) {
    1766           0 :     LiveInterval &LI = LIS->getInterval(CP.getDstReg());
    1767           0 :     shrinkToUses(&LI);
    1768             :   }
    1769             : 
    1770             :   // SrcReg is guaranteed to be the register whose live interval that is
    1771             :   // being merged.
    1772      663782 :   LIS->removeInterval(CP.getSrcReg());
    1773             : 
    1774             :   // Update regalloc hint.
    1775      663782 :   TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
    1776             : 
    1777             :   LLVM_DEBUG({
    1778             :     dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx())
    1779             :            << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
    1780             :     dbgs() << "\tResult = ";
    1781             :     if (CP.isPhys())
    1782             :       dbgs() << printReg(CP.getDstReg(), TRI);
    1783             :     else
    1784             :       dbgs() << LIS->getInterval(CP.getDstReg());
    1785             :     dbgs() << '\n';
    1786             :   });
    1787             : 
    1788             :   ++numJoins;
    1789      663782 :   return true;
    1790             : }
    1791             : 
    1792       38243 : bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
    1793       38243 :   unsigned DstReg = CP.getDstReg();
    1794       38243 :   unsigned SrcReg = CP.getSrcReg();
    1795             :   assert(CP.isPhys() && "Must be a physreg copy");
    1796             :   assert(MRI->isReserved(DstReg) && "Not a reserved register");
    1797       38243 :   LiveInterval &RHS = LIS->getInterval(SrcReg);
    1798             :   LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << '\n');
    1799             : 
    1800             :   assert(RHS.containsOneValue() && "Invalid join with reserved register");
    1801             : 
    1802             :   // Optimization for reserved registers like ESP. We can only merge with a
    1803             :   // reserved physreg if RHS has a single value that is a copy of DstReg.
    1804             :   // The live range of the reserved register will look like a set of dead defs
    1805             :   // - we don't properly track the live range of reserved registers.
    1806             : 
    1807             :   // Deny any overlapping intervals.  This depends on all the reserved
    1808             :   // register live ranges to look like dead defs.
    1809       38243 :   if (!MRI->isConstantPhysReg(DstReg)) {
    1810      141929 :     for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
    1811             :       // Abort if not all the regunits are reserved.
    1812      210689 :       for (MCRegUnitRootIterator RI(*UI, TRI); RI.isValid(); ++RI) {
    1813      140474 :         if (!MRI->isReserved(*RI))
    1814             :           return false;
    1815             :       }
    1816      140430 :       if (RHS.overlaps(LIS->getRegUnit(*UI))) {
    1817             :         LLVM_DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI)
    1818             :                           << '\n');
    1819             :         return false;
    1820             :       }
    1821             :     }
    1822             : 
    1823             :     // We must also check for overlaps with regmask clobbers.
    1824             :     BitVector RegMaskUsable;
    1825       35519 :     if (LIS->checkRegMaskInterference(RHS, RegMaskUsable) &&
    1826             :         !RegMaskUsable.test(DstReg)) {
    1827             :       LLVM_DEBUG(dbgs() << "\t\tRegMask interference\n");
    1828             :       return false;
    1829             :     }
    1830             :   }
    1831             : 
    1832             :   // Skip any value computations, we are not adding new values to the
    1833             :   // reserved register.  Also skip merging the live ranges, the reserved
    1834             :   // register live range doesn't need to be accurate as long as all the
    1835             :   // defs are there.
    1836             : 
    1837             :   // Delete the identity copy.
    1838             :   MachineInstr *CopyMI;
    1839       36509 :   if (CP.isFlipped()) {
    1840             :     // Physreg is copied into vreg
    1841             :     //   %y = COPY %physreg_x
    1842             :     //   ...  //< no other def of %x here
    1843             :     //   use %y
    1844             :     // =>
    1845             :     //   ...
    1846             :     //   use %x
    1847       36445 :     CopyMI = MRI->getVRegDef(SrcReg);
    1848             :   } else {
    1849             :     // VReg is copied into physreg:
    1850             :     //   %y = def
    1851             :     //   ... //< no other def or use of %y here
    1852             :     //   %y = COPY %physreg_x
    1853             :     // =>
    1854             :     //   %y = def
    1855             :     //   ...
    1856          64 :     if (!MRI->hasOneNonDBGUse(SrcReg)) {
    1857             :       LLVM_DEBUG(dbgs() << "\t\tMultiple vreg uses!\n");
    1858             :       return false;
    1859             :     }
    1860             : 
    1861          56 :     if (!LIS->intervalIsInOneMBB(RHS)) {
    1862             :       LLVM_DEBUG(dbgs() << "\t\tComplex control flow!\n");
    1863             :       return false;
    1864             :     }
    1865             : 
    1866          43 :     MachineInstr &DestMI = *MRI->getVRegDef(SrcReg);
    1867          86 :     CopyMI = &*MRI->use_instr_nodbg_begin(SrcReg);
    1868          43 :     SlotIndex CopyRegIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
    1869          43 :     SlotIndex DestRegIdx = LIS->getInstructionIndex(DestMI).getRegSlot();
    1870             : 
    1871          43 :     if (!MRI->isConstantPhysReg(DstReg)) {
    1872             :       // We checked above that there are no interfering defs of the physical
    1873             :       // register. However, for this case, where we intend to move up the def of
    1874             :       // the physical register, we also need to check for interfering uses.
    1875          42 :       SlotIndexes *Indexes = LIS->getSlotIndexes();
    1876             :       for (SlotIndex SI = Indexes->getNextNonNullIndex(DestRegIdx);
    1877          77 :            SI != CopyRegIdx; SI = Indexes->getNextNonNullIndex(SI)) {
    1878             :         MachineInstr *MI = LIS->getInstructionFromIndex(SI);
    1879          78 :         if (MI->readsRegister(DstReg, TRI)) {
    1880             :           LLVM_DEBUG(dbgs() << "\t\tInterference (read): " << *MI);
    1881             :           return false;
    1882             :         }
    1883             :       }
    1884             :     }
    1885             : 
    1886             :     // We're going to remove the copy which defines a physical reserved
    1887             :     // register, so remove its valno, etc.
    1888             :     LLVM_DEBUG(dbgs() << "\t\tRemoving phys reg def of "
    1889             :                       << printReg(DstReg, TRI) << " at " << CopyRegIdx << "\n");
    1890             : 
    1891          39 :     LIS->removePhysRegDefAt(DstReg, CopyRegIdx);
    1892             :     // Create a new dead def at the new def location.
    1893         125 :     for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
    1894          94 :       LiveRange &LR = LIS->getRegUnit(*UI);
    1895          94 :       LR.createDeadDef(DestRegIdx, LIS->getVNInfoAllocator());
    1896             :     }
    1897             :   }
    1898             : 
    1899       36484 :   deleteInstr(CopyMI);
    1900             : 
    1901             :   // We don't track kills for reserved registers.
    1902       36484 :   MRI->clearKillFlags(CP.getSrcReg());
    1903             : 
    1904       36484 :   return true;
    1905             : }
    1906             : 
    1907             : //===----------------------------------------------------------------------===//
    1908             : //                 Interference checking and interval joining
    1909             : //===----------------------------------------------------------------------===//
    1910             : //
    1911             : // In the easiest case, the two live ranges being joined are disjoint, and
    1912             : // there is no interference to consider. It is quite common, though, to have
    1913             : // overlapping live ranges, and we need to check if the interference can be
    1914             : // resolved.
    1915             : //
    1916             : // The live range of a single SSA value forms a sub-tree of the dominator tree.
    1917             : // This means that two SSA values overlap if and only if the def of one value
    1918             : // is contained in the live range of the other value. As a special case, the
    1919             : // overlapping values can be defined at the same index.
    1920             : //
    1921             : // The interference from an overlapping def can be resolved in these cases:
    1922             : //
    1923             : // 1. Coalescable copies. The value is defined by a copy that would become an
    1924             : //    identity copy after joining SrcReg and DstReg. The copy instruction will
    1925             : //    be removed, and the value will be merged with the source value.
    1926             : //
    1927             : //    There can be several copies back and forth, causing many values to be
    1928             : //    merged into one. We compute a list of ultimate values in the joined live
    1929             : //    range as well as a mappings from the old value numbers.
    1930             : //
    1931             : // 2. IMPLICIT_DEF. This instruction is only inserted to ensure all PHI
    1932             : //    predecessors have a live out value. It doesn't cause real interference,
    1933             : //    and can be merged into the value it overlaps. Like a coalescable copy, it
    1934             : //    can be erased after joining.
    1935             : //
    1936             : // 3. Copy of external value. The overlapping def may be a copy of a value that
    1937             : //    is already in the other register. This is like a coalescable copy, but
    1938             : //    the live range of the source register must be trimmed after erasing the
    1939             : //    copy instruction:
    1940             : //
    1941             : //      %src = COPY %ext
    1942             : //      %dst = COPY %ext  <-- Remove this COPY, trim the live range of %ext.
    1943             : //
    1944             : // 4. Clobbering undefined lanes. Vector registers are sometimes built by
    1945             : //    defining one lane at a time:
    1946             : //
    1947             : //      %dst:ssub0<def,read-undef> = FOO
    1948             : //      %src = BAR
    1949             : //      %dst:ssub1 = COPY %src
    1950             : //
    1951             : //    The live range of %src overlaps the %dst value defined by FOO, but
    1952             : //    merging %src into %dst:ssub1 is only going to clobber the ssub1 lane
    1953             : //    which was undef anyway.
    1954             : //
    1955             : //    The value mapping is more complicated in this case. The final live range
    1956             : //    will have different value numbers for both FOO and BAR, but there is no
    1957             : //    simple mapping from old to new values. It may even be necessary to add
    1958             : //    new PHI values.
    1959             : //
    1960             : // 5. Clobbering dead lanes. A def may clobber a lane of a vector register that
    1961             : //    is live, but never read. This can happen because we don't compute
    1962             : //    individual live ranges per lane.
    1963             : //
    1964             : //      %dst = FOO
    1965             : //      %src = BAR
    1966             : //      %dst:ssub1 = COPY %src
    1967             : //
    1968             : //    This kind of interference is only resolved locally. If the clobbered
    1969             : //    lane value escapes the block, the join is aborted.
    1970             : 
    1971             : namespace {
    1972             : 
    1973             : /// Track information about values in a single virtual register about to be
    1974             : /// joined. Objects of this class are always created in pairs - one for each
    1975             : /// side of the CoalescerPair (or one for each lane of a side of the coalescer
    1976             : /// pair)
    1977     3486060 : class JoinVals {
    1978             :   /// Live range we work on.
    1979             :   LiveRange &LR;
    1980             : 
    1981             :   /// (Main) register we work on.
    1982             :   const unsigned Reg;
    1983             : 
    1984             :   /// Reg (and therefore the values in this liverange) will end up as
    1985             :   /// subregister SubIdx in the coalesced register. Either CP.DstIdx or
    1986             :   /// CP.SrcIdx.
    1987             :   const unsigned SubIdx;
    1988             : 
    1989             :   /// The LaneMask that this liverange will occupy the coalesced register. May
    1990             :   /// be smaller than the lanemask produced by SubIdx when merging subranges.
    1991             :   const LaneBitmask LaneMask;
    1992             : 
    1993             :   /// This is true when joining sub register ranges, false when joining main
    1994             :   /// ranges.
    1995             :   const bool SubRangeJoin;
    1996             : 
    1997             :   /// Whether the current LiveInterval tracks subregister liveness.
    1998             :   const bool TrackSubRegLiveness;
    1999             : 
    2000             :   /// Values that will be present in the final live range.
    2001             :   SmallVectorImpl<VNInfo*> &NewVNInfo;
    2002             : 
    2003             :   const CoalescerPair &CP;
    2004             :   LiveIntervals *LIS;
    2005             :   SlotIndexes *Indexes;
    2006             :   const TargetRegisterInfo *TRI;
    2007             : 
    2008             :   /// Value number assignments. Maps value numbers in LI to entries in
    2009             :   /// NewVNInfo. This is suitable for passing to LiveInterval::join().
    2010             :   SmallVector<int, 8> Assignments;
    2011             : 
    2012             :   /// Conflict resolution for overlapping values.
    2013             :   enum ConflictResolution {
    2014             :     /// No overlap, simply keep this value.
    2015             :     CR_Keep,
    2016             : 
    2017             :     /// Merge this value into OtherVNI and erase the defining instruction.
    2018             :     /// Used for IMPLICIT_DEF, coalescable copies, and copies from external
    2019             :     /// values.
    2020             :     CR_Erase,
    2021             : 
    2022             :     /// Merge this value into OtherVNI but keep the defining instruction.
    2023             :     /// This is for the special case where OtherVNI is defined by the same
    2024             :     /// instruction.
    2025             :     CR_Merge,
    2026             : 
    2027             :     /// Keep this value, and have it replace OtherVNI where possible. This
    2028             :     /// complicates value mapping since OtherVNI maps to two different values
    2029             :     /// before and after this def.
    2030             :     /// Used when clobbering undefined or dead lanes.
    2031             :     CR_Replace,
    2032             : 
    2033             :     /// Unresolved conflict. Visit later when all values have been mapped.
    2034             :     CR_Unresolved,
    2035             : 
    2036             :     /// Unresolvable conflict. Abort the join.
    2037             :     CR_Impossible
    2038             :   };
    2039             : 
    2040             :   /// Per-value info for LI. The lane bit masks are all relative to the final
    2041             :   /// joined register, so they can be compared directly between SrcReg and
    2042             :   /// DstReg.
    2043             :   struct Val {
    2044             :     ConflictResolution Resolution = CR_Keep;
    2045             : 
    2046             :     /// Lanes written by this def, 0 for unanalyzed values.
    2047             :     LaneBitmask WriteLanes;
    2048             : 
    2049             :     /// Lanes with defined values in this register. Other lanes are undef and
    2050             :     /// safe to clobber.
    2051             :     LaneBitmask ValidLanes;
    2052             : 
    2053             :     /// Value in LI being redefined by this def.
    2054             :     VNInfo *RedefVNI = nullptr;
    2055             : 
    2056             :     /// Value in the other live range that overlaps this def, if any.
    2057             :     VNInfo *OtherVNI = nullptr;
    2058             : 
    2059             :     /// Is this value an IMPLICIT_DEF that can be erased?
    2060             :     ///
    2061             :     /// IMPLICIT_DEF values should only exist at the end of a basic block that
    2062             :     /// is a predecessor to a phi-value. These IMPLICIT_DEF instructions can be
    2063             :     /// safely erased if they are overlapping a live value in the other live
    2064             :     /// interval.
    2065             :     ///
    2066             :     /// Weird control flow graphs and incomplete PHI handling in
    2067             :     /// ProcessImplicitDefs can very rarely create IMPLICIT_DEF values with
    2068             :     /// longer live ranges. Such IMPLICIT_DEF values should be treated like
    2069             :     /// normal values.
    2070             :     bool ErasableImplicitDef = false;
    2071             : 
    2072             :     /// True when the live range of this value will be pruned because of an
    2073             :     /// overlapping CR_Replace value in the other live range.
    2074             :     bool Pruned = false;
    2075             : 
    2076             :     /// True once Pruned above has been computed.
    2077             :     bool PrunedComputed = false;
    2078             : 
    2079             :     Val() = default;
    2080             : 
    2081             :     bool isAnalyzed() const { return WriteLanes.any(); }
    2082             :   };
    2083             : 
    2084             :   /// One entry per value number in LI.
    2085             :   SmallVector<Val, 8> Vals;
    2086             : 
    2087             :   /// Compute the bitmask of lanes actually written by DefMI.
    2088             :   /// Set Redef if there are any partial register definitions that depend on the
    2089             :   /// previous value of the register.
    2090             :   LaneBitmask computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const;
    2091             : 
    2092             :   /// Find the ultimate value that VNI was copied from.
    2093             :   std::pair<const VNInfo*,unsigned> followCopyChain(const VNInfo *VNI) const;
    2094             : 
    2095             :   bool valuesIdentical(VNInfo *Val0, VNInfo *Val1, const JoinVals &Other) const;
    2096             : 
    2097             :   /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
    2098             :   /// Return a conflict resolution when possible, but leave the hard cases as
    2099             :   /// CR_Unresolved.
    2100             :   /// Recursively calls computeAssignment() on this and Other, guaranteeing that
    2101             :   /// both OtherVNI and RedefVNI have been analyzed and mapped before returning.
    2102             :   /// The recursion always goes upwards in the dominator tree, making loops
    2103             :   /// impossible.
    2104             :   ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other);
    2105             : 
    2106             :   /// Compute the value assignment for ValNo in RI.
    2107             :   /// This may be called recursively by analyzeValue(), but never for a ValNo on
    2108             :   /// the stack.
    2109             :   void computeAssignment(unsigned ValNo, JoinVals &Other);
    2110             : 
    2111             :   /// Assuming ValNo is going to clobber some valid lanes in Other.LR, compute
    2112             :   /// the extent of the tainted lanes in the block.
    2113             :   ///
    2114             :   /// Multiple values in Other.LR can be affected since partial redefinitions
    2115             :   /// can preserve previously tainted lanes.
    2116             :   ///
    2117             :   ///   1 %dst = VLOAD           <-- Define all lanes in %dst
    2118             :   ///   2 %src = FOO             <-- ValNo to be joined with %dst:ssub0
    2119             :   ///   3 %dst:ssub1 = BAR       <-- Partial redef doesn't clear taint in ssub0
    2120             :   ///   4 %dst:ssub0 = COPY %src <-- Conflict resolved, ssub0 wasn't read
    2121             :   ///
    2122             :   /// For each ValNo in Other that is affected, add an (EndIndex, TaintedLanes)
    2123             :   /// entry to TaintedVals.
    2124             :   ///
    2125             :   /// Returns false if the tainted lanes extend beyond the basic block.
    2126             :   bool
    2127             :   taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
    2128             :               SmallVectorImpl<std::pair<SlotIndex, LaneBitmask>> &TaintExtent);
    2129             : 
    2130             :   /// Return true if MI uses any of the given Lanes from Reg.
    2131             :   /// This does not include partial redefinitions of Reg.
    2132             :   bool usesLanes(const MachineInstr &MI, unsigned, unsigned, LaneBitmask) const;
    2133             : 
    2134             :   /// Determine if ValNo is a copy of a value number in LR or Other.LR that will
    2135             :   /// be pruned:
    2136             :   ///
    2137             :   ///   %dst = COPY %src
    2138             :   ///   %src = COPY %dst  <-- This value to be pruned.
    2139             :   ///   %dst = COPY %src  <-- This value is a copy of a pruned value.
    2140             :   bool isPrunedValue(unsigned ValNo, JoinVals &Other);
    2141             : 
    2142             : public:
    2143     1743030 :   JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask,
    2144             :            SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp,
    2145             :            LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin,
    2146             :            bool TrackSubRegLiveness)
    2147     1743030 :     : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask),
    2148             :       SubRangeJoin(SubRangeJoin), TrackSubRegLiveness(TrackSubRegLiveness),
    2149     1743030 :       NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
    2150    10458180 :       TRI(TRI), Assignments(LR.getNumValNums(), -1), Vals(LR.getNumValNums()) {}
    2151             : 
    2152             :   /// Analyze defs in LR and compute a value mapping in NewVNInfo.
    2153             :   /// Returns false if any conflicts were impossible to resolve.
    2154             :   bool mapValues(JoinVals &Other);
    2155             : 
    2156             :   /// Try to resolve conflicts that require all values to be mapped.
    2157             :   /// Returns false if any conflicts were impossible to resolve.
    2158             :   bool resolveConflicts(JoinVals &Other);
    2159             : 
    2160             :   /// Prune the live range of values in Other.LR where they would conflict with
    2161             :   /// CR_Replace values in LR. Collect end points for restoring the live range
    2162             :   /// after joining.
    2163             :   void pruneValues(JoinVals &Other, SmallVectorImpl<SlotIndex> &EndPoints,
    2164             :                    bool changeInstrs);
    2165             : 
    2166             :   /// Removes subranges starting at copies that get removed. This sometimes
    2167             :   /// happens when undefined subranges are copied around. These ranges contain
    2168             :   /// no useful information and can be removed.
    2169             :   void pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask);
    2170             : 
    2171             :   /// Pruning values in subranges can lead to removing segments in these
    2172             :   /// subranges started by IMPLICIT_DEFs. The corresponding segments in
    2173             :   /// the main range also need to be removed. This function will mark
    2174             :   /// the corresponding values in the main range as pruned, so that
    2175             :   /// eraseInstrs can do the final cleanup.
    2176             :   /// The parameter @p LI must be the interval whose main range is the
    2177             :   /// live range LR.
    2178             :   void pruneMainSegments(LiveInterval &LI, bool &ShrinkMainRange);
    2179             : 
    2180             :   /// Erase any machine instructions that have been coalesced away.
    2181             :   /// Add erased instructions to ErasedInstrs.
    2182             :   /// Add foreign virtual registers to ShrinkRegs if their live range ended at
    2183             :   /// the erased instrs.
    2184             :   void eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
    2185             :                    SmallVectorImpl<unsigned> &ShrinkRegs,
    2186             :                    LiveInterval *LI = nullptr);
    2187             : 
    2188             :   /// Remove liverange defs at places where implicit defs will be removed.
    2189             :   void removeImplicitDefs();
    2190             : 
    2191             :   /// Get the value assignments suitable for passing to LiveInterval::join.
    2192      790788 :   const int *getAssignments() const { return Assignments.data(); }
    2193             : };
    2194             : 
    2195             : } // end anonymous namespace
    2196             : 
    2197     3171917 : LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
    2198             :   const {
    2199             :   LaneBitmask L;
    2200    20855835 :   for (const MachineOperand &MO : DefMI->operands()) {
    2201    12502582 :     if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef())
    2202     5670016 :       continue;
    2203     3171943 :     L |= TRI->getSubRegIndexLaneMask(
    2204     6343886 :            TRI->composeSubRegIndices(SubIdx, MO.getSubReg()));
    2205             :     if (MO.readsReg())
    2206      381871 :       Redef = true;
    2207             :   }
    2208     3171917 :   return L;
    2209             : }
    2210             : 
    2211       14535 : std::pair<const VNInfo*, unsigned> JoinVals::followCopyChain(
    2212             :     const VNInfo *VNI) const {
    2213       14535 :   unsigned Reg = this->Reg;
    2214             : 
    2215       34367 :   while (!VNI->isPHIDef()) {
    2216       19685 :     SlotIndex Def = VNI->def;
    2217             :     MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
    2218             :     assert(MI && "No defining instruction");
    2219             :     if (!MI->isFullCopy())
    2220        9769 :       return std::make_pair(VNI, Reg);
    2221       14283 :     unsigned SrcReg = MI->getOperand(1).getReg();
    2222       14283 :     if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
    2223             :       return std::make_pair(VNI, Reg);
    2224             : 
    2225        9916 :     const LiveInterval &LI = LIS->getInterval(SrcReg);
    2226             :     const VNInfo *ValueIn;
    2227             :     // No subrange involved.
    2228        9916 :     if (!SubRangeJoin || !LI.hasSubRanges()) {
    2229        9899 :       LiveQueryResult LRQ = LI.Query(Def);
    2230        9899 :       ValueIn = LRQ.valueIn();
    2231             :     } else {
    2232             :       // Query subranges. Pick the first matching one.
    2233             :       ValueIn = nullptr;
    2234          42 :       for (const LiveInterval::SubRange &S : LI.subranges()) {
    2235             :         // Transform lanemask to a mask in the joined live interval.
    2236          42 :         LaneBitmask SMask = TRI->composeSubRegIndexLaneMask(SubIdx, S.LaneMask);
    2237          42 :         if ((SMask & LaneMask).none())
    2238          25 :           continue;
    2239          17 :         LiveQueryResult LRQ = S.Query(Def);
    2240          17 :         ValueIn = LRQ.valueIn();
    2241          17 :         break;
    2242             :       }
    2243             :     }
    2244        9916 :     if (ValueIn == nullptr)
    2245             :       break;
    2246             :     VNI = ValueIn;
    2247             :     Reg = SrcReg;
    2248             :   }
    2249             :   return std::make_pair(VNI, Reg);
    2250             : }
    2251             : 
    2252        7308 : bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
    2253             :                                const JoinVals &Other) const {
    2254             :   const VNInfo *Orig0;
    2255             :   unsigned Reg0;
    2256       14616 :   std::tie(Orig0, Reg0) = followCopyChain(Value0);
    2257        7308 :   if (Orig0 == Value1)
    2258             :     return true;
    2259             : 
    2260             :   const VNInfo *Orig1;
    2261             :   unsigned Reg1;
    2262       14454 :   std::tie(Orig1, Reg1) = Other.followCopyChain(Value1);
    2263             : 
    2264             :   // The values are equal if they are defined at the same place and use the
    2265             :   // same register. Note that we cannot compare VNInfos directly as some of
    2266             :   // them might be from a copy created in mergeSubRangeInto()  while the other
    2267             :   // is from the original LiveInterval.
    2268        7227 :   return Orig0->def == Orig1->def && Reg0 == Reg1;
    2269             : }
    2270             : 
    2271             : JoinVals::ConflictResolution
    2272     4223775 : JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
    2273     4223775 :   Val &V = Vals[ValNo];
    2274             :   assert(!V.isAnalyzed() && "Value has already been analyzed!");
    2275     4223775 :   VNInfo *VNI = LR.getValNumInfo(ValNo);
    2276     4223775 :   if (VNI->isUnused()) {
    2277        1312 :     V.WriteLanes = LaneBitmask::getAll();
    2278        1312 :     return CR_Keep;
    2279             :   }
    2280             : 
    2281             :   // Get the instruction defining this value, compute the lanes written.
    2282             :   const MachineInstr *DefMI = nullptr;
    2283     4222463 :   if (VNI->isPHIDef()) {
    2284             :     // Conservatively assume that all lanes in a PHI are valid.
    2285      707865 :     LaneBitmask Lanes = SubRangeJoin ? LaneBitmask::getLane(0)
    2286      707865 :                                      : TRI->getSubRegIndexLaneMask(SubIdx);
    2287      707865 :     V.ValidLanes = V.WriteLanes = Lanes;
    2288             :   } else {
    2289             :     DefMI = Indexes->getInstructionFromIndex(VNI->def);
    2290             :     assert(DefMI != nullptr);
    2291     3514598 :     if (SubRangeJoin) {
    2292             :       // We don't care about the lanes when joining subregister ranges.
    2293      342681 :       V.WriteLanes = V.ValidLanes = LaneBitmask::getLane(0);
    2294      342681 :       if (DefMI->isImplicitDef()) {
    2295         104 :         V.ValidLanes = LaneBitmask::getNone();
    2296         104 :         V.ErasableImplicitDef = true;
    2297             :       }
    2298             :     } else {
    2299     3171917 :       bool Redef = false;
    2300     3171917 :       V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef);
    2301             : 
    2302             :       // If this is a read-modify-write instruction, there may be more valid
    2303             :       // lanes than the ones written by this instruction.
    2304             :       // This only covers partial redef operands. DefMI may have normal use
    2305             :       // operands reading the register. They don't contribute valid lanes.
    2306             :       //
    2307             :       // This adds ssub1 to the set of valid lanes in %src:
    2308             :       //
    2309             :       //   %src:ssub1 = FOO
    2310             :       //
    2311             :       // This leaves only ssub1 valid, making any other lanes undef:
    2312             :       //
    2313             :       //   %src:ssub1<def,read-undef> = FOO %src:ssub2
    2314             :       //
    2315             :       // The <read-undef> flag on the def operand means that old lane values are
    2316             :       // not important.
    2317     3171917 :       if (Redef) {
    2318      381845 :         V.RedefVNI = LR.Query(VNI->def).valueIn();
    2319             :         assert((TrackSubRegLiveness || V.RedefVNI) &&
    2320             :                "Instruction is reading nonexistent value");
    2321      381845 :         if (V.RedefVNI != nullptr) {
    2322      381845 :           computeAssignment(V.RedefVNI->id, Other);
    2323      381845 :           V.ValidLanes |= Vals[V.RedefVNI->id].ValidLanes;
    2324             :         }
    2325             :       }
    2326             : 
    2327             :       // An IMPLICIT_DEF writes undef values.
    2328     3171917 :       if (DefMI->isImplicitDef()) {
    2329             :         // We normally expect IMPLICIT_DEF values to be live only until the end
    2330             :         // of their block. If the value is really live longer and gets pruned in
    2331             :         // another block, this flag is cleared again.
    2332        8473 :         V.ErasableImplicitDef = true;
    2333             :         V.ValidLanes &= ~V.WriteLanes;
    2334             :       }
    2335             :     }
    2336             :   }
    2337             : 
    2338             :   // Find the value in Other that overlaps VNI->def, if any.
    2339     4222463 :   LiveQueryResult OtherLRQ = Other.LR.Query(VNI->def);
    2340             : 
    2341             :   // It is possible that both values are defined by the same instruction, or
    2342             :   // the values are PHIs defined in the same block. When that happens, the two
    2343             :   // values should be merged into one, but not into any preceding value.
    2344             :   // The first value defined or visited gets CR_Keep, the other gets CR_Merge.
    2345     4955291 :   if (VNInfo *OtherVNI = OtherLRQ.valueDefined()) {
    2346             :     assert(SlotIndex::isSameInstr(VNI->def, OtherVNI->def) && "Broken LRQ");
    2347             : 
    2348             :     // One value stays, the other is merged. Keep the earlier one, or the first
    2349             :     // one we see.
    2350        6002 :     if (OtherVNI->def < VNI->def)
    2351           0 :       Other.computeAssignment(OtherVNI->id, *this);
    2352        6002 :     else if (VNI->def < OtherVNI->def && OtherLRQ.valueIn()) {
    2353             :       // This is an early-clobber def overlapping a live-in value in the other
    2354             :       // register. Not mergeable.
    2355           0 :       V.OtherVNI = OtherLRQ.valueIn();
    2356           0 :       return CR_Impossible;
    2357             :     }
    2358        6002 :     V.OtherVNI = OtherVNI;
    2359        6002 :     Val &OtherV = Other.Vals[OtherVNI->id];
    2360             :     // Keep this value, check for conflicts when analyzing OtherVNI.
    2361        6002 :     if (!OtherV.isAnalyzed())
    2362             :       return CR_Keep;
    2363             :     // Both sides have been analyzed now.
    2364             :     // Allow overlapping PHI values. Any real interference would show up in a
    2365             :     // predecessor, the PHI itself can't introduce any conflicts.
    2366        1900 :     if (VNI->isPHIDef())
    2367             :       return CR_Merge;
    2368          85 :     if ((V.ValidLanes & OtherV.ValidLanes).any())
    2369             :       // Overlapping lanes can't be resolved.
    2370             :       return CR_Impossible;
    2371             :     else
    2372          13 :       return CR_Merge;
    2373             :   }
    2374             : 
    2375             :   // No simultaneous def. Is Other live at the def?
    2376     4216461 :   V.OtherVNI = OtherLRQ.valueIn();
    2377     4216461 :   if (!V.OtherVNI)
    2378             :     // No overlap, no conflict.
    2379             :     return CR_Keep;
    2380             : 
    2381             :   assert(!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) && "Broken LRQ");
    2382             : 
    2383             :   // We have overlapping values, or possibly a kill of Other.
    2384             :   // Recursively compute assignments up the dominator tree.
    2385     1139659 :   Other.computeAssignment(V.OtherVNI->id, *this);
    2386     1139659 :   Val &OtherV = Other.Vals[V.OtherVNI->id];
    2387             : 
    2388             :   // Check if OtherV is an IMPLICIT_DEF that extends beyond its basic block.
    2389             :   // This shouldn't normally happen, but ProcessImplicitDefs can leave such
    2390             :   // IMPLICIT_DEF instructions behind, and there is nothing wrong with it
    2391             :   // technically.
    2392             :   //
    2393             :   // When it happens, treat that IMPLICIT_DEF as a normal value, and don't try
    2394             :   // to erase the IMPLICIT_DEF instruction.
    2395     1140169 :   if (OtherV.ErasableImplicitDef && DefMI &&
    2396         510 :       DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) {
    2397             :     LLVM_DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def
    2398             :                       << " extends into "
    2399             :                       << printMBBReference(*DefMI->getParent())
    2400             :                       << ", keeping it.\n");
    2401           1 :     OtherV.ErasableImplicitDef = false;
    2402             :   }
    2403             : 
    2404             :   // Allow overlapping PHI values. Any real interference would show up in a
    2405             :   // predecessor, the PHI itself can't introduce any conflicts.
    2406     1139659 :   if (VNI->isPHIDef())
    2407             :     return CR_Replace;
    2408             : 
    2409             :   // Check for simple erasable conflicts.
    2410     1136524 :   if (DefMI->isImplicitDef()) {
    2411             :     // We need the def for the subregister if there is nothing else live at the
    2412             :     // subrange at this point.
    2413        1673 :     if (TrackSubRegLiveness
    2414        1697 :         && (V.WriteLanes & (OtherV.ValidLanes | OtherV.WriteLanes)).none())
    2415             :       return CR_Replace;
    2416             :     return CR_Erase;
    2417             :   }
    2418             : 
    2419             :   // Include the non-conflict where DefMI is a coalescable copy that kills
    2420             :   // OtherVNI. We still want the copy erased and value numbers merged.
    2421     1134851 :   if (CP.isCoalescable(DefMI)) {
    2422             :     // Some of the lanes copied from OtherVNI may be undef, making them undef
    2423             :     // here too.
    2424             :     V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
    2425      895137 :     return CR_Erase;
    2426             :   }
    2427             : 
    2428             :   // This may not be a real conflict if DefMI simply kills Other and defines
    2429             :   // VNI.
    2430      245018 :   if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)
    2431             :     return CR_Keep;
    2432             : 
    2433             :   // Handle the case where VNI and OtherVNI can be proven to be identical:
    2434             :   //
    2435             :   //   %other = COPY %ext
    2436             :   //   %this  = COPY %ext <-- Erase this copy
    2437             :   //
    2438       10183 :   if (DefMI->isFullCopy() && !CP.isPartial()
    2439        7308 :       && valuesIdentical(VNI, V.OtherVNI, Other))
    2440             :     return CR_Erase;
    2441             : 
    2442             :   // If the lanes written by this instruction were all undef in OtherVNI, it is
    2443             :   // still safe to join the live ranges. This can't be done with a simple value
    2444             :   // mapping, though - OtherVNI will map to multiple values:
    2445             :   //
    2446             :   //   1 %dst:ssub0 = FOO                <-- OtherVNI
    2447             :   //   2 %src = BAR                      <-- VNI
    2448             :   //   3 %dst:ssub1 = COPY killed %src    <-- Eliminate this copy.
    2449             :   //   4 BAZ killed %dst
    2450             :   //   5 QUUX killed %src
    2451             :   //
    2452             :   // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace
    2453             :   // handles this complex value mapping.
    2454      234155 :   if ((V.WriteLanes & OtherV.ValidLanes).none())
    2455             :     return CR_Replace;
    2456             : 
    2457             :   // If the other live range is killed by DefMI and the live ranges are still
    2458             :   // overlapping, it must be because we're looking at an early clobber def:
    2459             :   //
    2460             :   //   %dst<def,early-clobber> = ASM killed %src
    2461             :   //
    2462             :   // In this case, it is illegal to merge the two live ranges since the early
    2463             :   // clobber def would clobber %src before it was read.
    2464      113963 :   if (OtherLRQ.isKill()) {
    2465             :     // This case where the def doesn't overlap the kill is handled above.
    2466             :     assert(VNI->def.isEarlyClobber() &&
    2467             :            "Only early clobber defs can overlap a kill");
    2468             :     return CR_Impossible;
    2469             :   }
    2470             : 
    2471             :   // VNI is clobbering live lanes in OtherVNI, but there is still the
    2472             :   // possibility that no instructions actually read the clobbered lanes.
    2473             :   // If we're clobbering all the lanes in OtherVNI, at least one must be read.
    2474             :   // Otherwise Other.RI wouldn't be live here.
    2475      227898 :   if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes).none())
    2476             :     return CR_Impossible;
    2477             : 
    2478             :   // We need to verify that no instructions are reading the clobbered lanes. To
    2479             :   // save compile time, we'll only check that locally. Don't allow the tainted
    2480             :   // value to escape the basic block.
    2481       51610 :   MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
    2482      103220 :   if (OtherLRQ.endPoint() >= Indexes->getMBBEndIdx(MBB))
    2483             :     return CR_Impossible;
    2484             : 
    2485             :   // There are still some things that could go wrong besides clobbered lanes
    2486             :   // being read, for example OtherVNI may be only partially redefined in MBB,
    2487             :   // and some clobbered lanes could escape the block. Save this analysis for
    2488             :   // resolveConflicts() when all values have been mapped. We need to know
    2489             :   // RedefVNI and WriteLanes for any later defs in MBB, and we can't compute
    2490             :   // that now - the recursive analyzeValue() calls must go upwards in the
    2491             :   // dominator tree.
    2492       50395 :   return CR_Unresolved;
    2493             : }
    2494             : 
    2495     5691374 : void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
    2496     5691374 :   Val &V = Vals[ValNo];
    2497     5691374 :   if (V.isAnalyzed()) {
    2498             :     // Recursion should always move up the dominator tree, so ValNo is not
    2499             :     // supposed to reappear before it has been assigned.
    2500             :     assert(Assignments[ValNo] != -1 && "Bad recursion?");
    2501             :     return;
    2502             :   }
    2503     4223775 :   switch ((V.Resolution = analyzeValue(ValNo, Other))) {
    2504      898900 :   case CR_Erase:
    2505             :   case CR_Merge:
    2506             :     // Merge this ValNo into OtherVNI.
    2507             :     assert(V.OtherVNI && "OtherVNI not assigned, can't merge.");
    2508             :     assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion");
    2509     1797800 :     Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
    2510             :     LLVM_DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@'
    2511             :                       << LR.getValNumInfo(ValNo)->def << " into "
    2512             :                       << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@'
    2513             :                       << V.OtherVNI->def << " --> @"
    2514             :                       << NewVNInfo[Assignments[ValNo]]->def << '\n');
    2515      898900 :     break;
    2516      173729 :   case CR_Replace:
    2517             :   case CR_Unresolved: {
    2518             :     // The other value is going to be pruned if this join is successful.
    2519             :     assert(V.OtherVNI && "OtherVNI not assigned, can't prune");
    2520      173729 :     Val &OtherV = Other.Vals[V.OtherVNI->id];
    2521             :     // We cannot erase an IMPLICIT_DEF if we don't have valid values for all
    2522             :     // its lanes.
    2523      173729 :     if ((OtherV.WriteLanes & ~V.ValidLanes).any() && TrackSubRegLiveness)
    2524       86850 :       OtherV.ErasableImplicitDef = false;
    2525      173729 :     OtherV.Pruned = true;
    2526             :     LLVM_FALLTHROUGH;
    2527             :   }
    2528     3324875 :   default:
    2529             :     // This value number needs to go in the final joined live range.
    2530     6649750 :     Assignments[ValNo] = NewVNInfo.size();
    2531     6649750 :     NewVNInfo.push_back(LR.getValNumInfo(ValNo));
    2532     3324875 :     break;
    2533             :   }
    2534             : }
    2535             : 
    2536     1696464 : bool JoinVals::mapValues(JoinVals &Other) {
    2537    11611836 :   for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
    2538     4169870 :     computeAssignment(i, Other);
    2539     8339740 :     if (Vals[i].Resolution == CR_Impossible) {
    2540             :       LLVM_DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << i
    2541             :                         << '@' << LR.getValNumInfo(i)->def << '\n');
    2542             :       return false;
    2543             :     }
    2544             :   }
    2545             :   return true;
    2546             : }
    2547             : 
    2548       46667 : bool JoinVals::
    2549             : taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
    2550             :             SmallVectorImpl<std::pair<SlotIndex, LaneBitmask>> &TaintExtent) {
    2551       46667 :   VNInfo *VNI = LR.getValNumInfo(ValNo);
    2552       46667 :   MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
    2553       46667 :   SlotIndex MBBEnd = Indexes->getMBBEndIdx(MBB);
    2554             : 
    2555             :   // Scan Other.LR from VNI.def to MBBEnd.
    2556       46667 :   LiveInterval::iterator OtherI = Other.LR.find(VNI->def);
    2557             :   assert(OtherI != Other.LR.end() && "No conflict?");
    2558             :   do {
    2559             :     // OtherI is pointing to a tainted value. Abort the join if the tainted
    2560             :     // lanes escape the block.
    2561       76644 :     SlotIndex End = OtherI->end;
    2562       76644 :     if (End >= MBBEnd) {
    2563             :       LLVM_DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':'
    2564             :                         << OtherI->valno->id << '@' << OtherI->start << '\n');
    2565             :       return false;
    2566             :     }
    2567             :     LLVM_DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':'
    2568             :                       << OtherI->valno->id << '@' << OtherI->start << " to "
    2569             :                       << End << '\n');
    2570             :     // A dead def is not a problem.
    2571       76631 :     if (End.isDead())
    2572             :       break;
    2573       76631 :     TaintExtent.push_back(std::make_pair(End, TaintedLanes));
    2574             : 
    2575             :     // Check for another def in the MBB.
    2576      206896 :     if (++OtherI == Other.LR.end() || OtherI->start >= MBBEnd)
    2577             :       break;
    2578             : 
    2579             :     // Lanes written by the new def are no longer tainted.
    2580       53599 :     const Val &OV = Other.Vals[OtherI->valno->id];
    2581             :     TaintedLanes &= ~OV.WriteLanes;
    2582       53599 :     if (!OV.RedefVNI)
    2583             :       break;
    2584       53367 :   } while (TaintedLanes.any());
    2585             :   return true;
    2586             : }
    2587             : 
    2588      527274 : bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx,
    2589             :                          LaneBitmask Lanes) const {
    2590             :   if (MI.isDebugInstr())
    2591             :     return false;
    2592     4289126 :   for (const MachineOperand &MO : MI.operands()) {
    2593     5067989 :     if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
    2594             :       continue;
    2595           4 :     if (!MO.readsReg())
    2596             :       continue;
    2597      110201 :     unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg());
    2598      220402 :     if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any())
    2599             :       return true;
    2600             :   }
    2601             :   return false;
    2602             : }
    2603             : 
    2604     1608737 : bool JoinVals::resolveConflicts(JoinVals &Other) {
    2605    11015354 :   for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
    2606     3919251 :     Val &V = Vals[i];
    2607             :     assert(V.Resolution != CR_Impossible && "Unresolvable conflict");
    2608     3919251 :     if (V.Resolution != CR_Unresolved)
    2609     3872584 :       continue;
    2610             :     LLVM_DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i << '@'
    2611             :                       << LR.getValNumInfo(i)->def << '\n');
    2612       46667 :     if (SubRangeJoin)
    2613       20311 :       return false;
    2614             : 
    2615             :     ++NumLaneConflicts;
    2616             :     assert(V.OtherVNI && "Inconsistent conflict resolution.");
    2617       46667 :     VNInfo *VNI = LR.getValNumInfo(i);
    2618       46667 :     const Val &OtherV = Other.Vals[V.OtherVNI->id];
    2619             : 
    2620             :     // VNI is known to clobber some lanes in OtherVNI. If we go ahead with the
    2621             :     // join, those lanes will be tainted with a wrong value. Get the extent of
    2622             :     // the tainted lanes.
    2623       46667 :     LaneBitmask TaintedLanes = V.WriteLanes & OtherV.ValidLanes;
    2624             :     SmallVector<std::pair<SlotIndex, LaneBitmask>, 8> TaintExtent;
    2625       46667 :     if (!taintExtent(i, TaintedLanes, Other, TaintExtent))
    2626             :       // Tainted lanes would extend beyond the basic block.
    2627             :       return false;
    2628             : 
    2629             :     assert(!TaintExtent.empty() && "There should be at least one conflict.");
    2630             : 
    2631             :     // Now look at the instructions from VNI->def to TaintExtent (inclusive).
    2632       46654 :     MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
    2633       46654 :     MachineBasicBlock::iterator MI = MBB->begin();
    2634       46654 :     if (!VNI->isPHIDef()) {
    2635       46654 :       MI = Indexes->getInstructionFromIndex(VNI->def);
    2636             :       // No need to check the instruction defining VNI for reads.
    2637             :       ++MI;
    2638             :     }
    2639             :     assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) &&
    2640             :            "Interference ends on VNI->def. Should have been handled earlier");
    2641             :     MachineInstr *LastMI =
    2642       46654 :       Indexes->getInstructionFromIndex(TaintExtent.front().first);
    2643             :     assert(LastMI && "Range must end at a proper instruction");
    2644             :     unsigned TaintNum = 0;
    2645             :     while (true) {
    2646             :       assert(MI != MBB->end() && "Bad LastMI");
    2647     1054548 :       if (usesLanes(*MI, Other.Reg, Other.SubIdx, TaintedLanes)) {
    2648             :         LLVM_DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
    2649             :         return false;
    2650             :       }
    2651             :       // LastMI is the last instruction to use the current value.
    2652      506976 :       if (&*MI == LastMI) {
    2653      112002 :         if (++TaintNum == TaintExtent.size())
    2654             :           break;
    2655             :         LastMI = Indexes->getInstructionFromIndex(TaintExtent[TaintNum].first);
    2656             :         assert(LastMI && "Range must end at a proper instruction");
    2657       29645 :         TaintedLanes = TaintExtent[TaintNum].second;
    2658             :       }
    2659             :       ++MI;
    2660             :     }
    2661             : 
    2662             :     // The tainted lanes are unused.
    2663       26356 :     V.Resolution = CR_Replace;
    2664             :     ++NumLaneResolves;
    2665             :   }
    2666             :   return true;
    2667             : }
    2668             : 
    2669     1632423 : bool JoinVals::isPrunedValue(unsigned ValNo, JoinVals &Other) {
    2670     1632423 :   Val &V = Vals[ValNo];
    2671     1632423 :   if (V.Pruned || V.PrunedComputed)
    2672             :     return V.Pruned;
    2673             : 
    2674     1597801 :   if (V.Resolution != CR_Erase && V.Resolution != CR_Merge)
    2675             :     return V.Pruned;
    2676             : 
    2677             :   // Follow copies up the dominator tree and check if any intermediate value
    2678             :   // has been pruned.
    2679      816208 :   V.PrunedComputed = true;
    2680      816208 :   V.Pruned = Other.isPrunedValue(V.OtherVNI->id, *this);
    2681      816208 :   return V.Pruned;
    2682             : }
    2683             : 
    2684     1581576 : void JoinVals::pruneValues(JoinVals &Other,
    2685             :                            SmallVectorImpl<SlotIndex> &EndPoints,
    2686             :                            bool changeInstrs) {
    2687    10919708 :   for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
    2688     7756556 :     SlotIndex Def = LR.getValNumInfo(i)->def;
    2689     3878278 :     switch (Vals[i].Resolution) {
    2690             :     case CR_Keep:
    2691             :       break;
    2692      113103 :     case CR_Replace: {
    2693             :       // This value takes precedence over the value in Other.LR.
    2694      113103 :       LIS->pruneValue(Other.LR, Def, &EndPoints);
    2695             :       // Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
    2696             :       // instructions are only inserted to provide a live-out value for PHI
    2697             :       // predecessors, so the instruction should simply go away once its value
    2698             :       // has been replaced.
    2699      113103 :       Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
    2700      113125 :       bool EraseImpDef = OtherV.ErasableImplicitDef &&
    2701          22 :                          OtherV.Resolution == CR_Keep;
    2702      113103 :       if (!Def.isBlock()) {
    2703      112990 :         if (changeInstrs) {
    2704             :           // Remove <def,read-undef> flags. This def is now a partial redef.
    2705             :           // Also remove dead flags since the joined live range will
    2706             :           // continue past this instruction.
    2707      430138 :           for (MachineOperand &MO :
    2708      543127 :                Indexes->getInstructionFromIndex(Def)->operands()) {
    2709      690239 :             if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
    2710      169590 :               if (MO.getSubReg() != 0 && MO.isUndef() && !EraseImpDef)
    2711             :                 MO.setIsUndef(false);
    2712             :               MO.setIsDead(false);
    2713             :             }
    2714             :           }
    2715             :         }
    2716             :         // This value will reach instructions below, but we need to make sure
    2717             :         // the live range also reaches the instruction at Def.
    2718      112990 :         if (!EraseImpDef)
    2719      112968 :           EndPoints.push_back(Def);
    2720             :       }
    2721             :       LLVM_DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Def
    2722             :                         << ": " << Other.LR << '\n');
    2723             :       break;
    2724             :     }
    2725      816215 :     case CR_Erase:
    2726             :     case CR_Merge:
    2727      816215 :       if (isPrunedValue(i, Other)) {
    2728             :         // This value is ultimately a copy of a pruned value in LR or Other.LR.
    2729             :         // We can no longer trust the value mapping computed by
    2730             :         // computeAssignment(), the value that was originally copied could have
    2731             :         // been replaced.
    2732       32714 :         LIS->pruneValue(LR, Def, &EndPoints);
    2733             :         LLVM_DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at "
    2734             :                           << Def << ": " << LR << '\n');
    2735             :       }
    2736             :       break;
    2737           0 :     case CR_Unresolved:
    2738             :     case CR_Impossible:
    2739           0 :       llvm_unreachable("Unresolved conflicts");
    2740             :     }
    2741             :   }
    2742     1581576 : }
    2743             : 
    2744      276618 : void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) {
    2745             :   // Look for values being erased.
    2746             :   bool DidPrune = false;
    2747     1573666 :   for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
    2748             :     // We should trigger in all cases in which eraseInstrs() does something.
    2749             :     // match what eraseInstrs() is doing, print a message so
    2750     1374097 :     if (Vals[i].Resolution != CR_Erase &&
    2751      266095 :         (Vals[i].Resolution != CR_Keep || !Vals[i].ErasableImplicitDef ||
    2752          69 :          !Vals[i].Pruned))
    2753      353667 :       continue;
    2754             : 
    2755             :     // Check subranges at the point where the copy will be removed.
    2756      313096 :     SlotIndex Def = LR.getValNumInfo(i)->def;
    2757             :     // Print message so mismatches with eraseInstrs() can be diagnosed.
    2758             :     LLVM_DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def
    2759             :                       << '\n');
    2760      712982 :     for (LiveInterval::SubRange &S : LI.subranges()) {
    2761      556434 :       LiveQueryResult Q = S.Query(Def);
    2762             : 
    2763             :       // If a subrange starts at the copy then an undefined value has been
    2764             :       // copied and we must remove that subrange value as well.
    2765             :       VNInfo *ValueOut = Q.valueOutOrDead();
    2766      557336 :       if (ValueOut != nullptr && Q.valueIn() == nullptr) {
    2767             :         LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask)
    2768             :                           << " at " << Def << "\n");
    2769         902 :         LIS->pruneValue(S, Def, nullptr);
    2770             :         DidPrune = true;
    2771             :         // Mark value number as unused.
    2772             :         ValueOut->markUnused();
    2773         902 :         continue;
    2774             :       }
    2775             :       // If a subrange ends at the copy, then a value was copied but only
    2776             :       // partially used later. Shrink the subregister range appropriately.
    2777      967719 :       if (Q.valueIn() != nullptr && Q.valueOut() == nullptr) {
    2778             :         LLVM_DEBUG(dbgs() << "\t\tDead uses at sublane "
    2779             :                           << PrintLaneMask(S.LaneMask) << " at " << Def
    2780             :                           << "\n");
    2781             :         ShrinkMask |= S.LaneMask;
    2782             :       }
    2783             :     }
    2784             :   }
    2785      276618 :   if (DidPrune)
    2786         574 :     LI.removeEmptySubRanges();
    2787      276618 : }
    2788             : 
    2789             : /// Check if any of the subranges of @p LI contain a definition at @p Def.
    2790      192668 : static bool isDefInSubRange(LiveInterval &LI, SlotIndex Def) {
    2791      464288 :   for (LiveInterval::SubRange &SR : LI.subranges()) {
    2792      464288 :     if (VNInfo *VNI = SR.Query(Def).valueOutOrDead())
    2793      459265 :       if (VNI->def == Def)
    2794             :         return true;
    2795             :   }
    2796             :   return false;
    2797             : }
    2798             : 
    2799      138309 : void JoinVals::pruneMainSegments(LiveInterval &LI, bool &ShrinkMainRange) {
    2800             :   assert(&static_cast<LiveRange&>(LI) == &LR);
    2801             : 
    2802      984852 :   for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
    2803      708234 :     if (Vals[i].Resolution != CR_Keep)
    2804      160330 :       continue;
    2805      193787 :     VNInfo *VNI = LR.getValNumInfo(i);
    2806      387573 :     if (VNI->isUnused() || VNI->isPHIDef() || isDefInSubRange(LI, VNI->def))
    2807      193787 :       continue;
    2808           0 :     Vals[i].Pruned = true;
    2809           0 :     ShrinkMainRange = true;
    2810             :   }
    2811      138309 : }
    2812             : 
    2813      326980 : void JoinVals::removeImplicitDefs() {
    2814     1345142 :   for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
    2815      345591 :     Val &V = Vals[i];
    2816      345591 :     if (V.Resolution != CR_Keep || !V.ErasableImplicitDef || !V.Pruned)
    2817      345590 :       continue;
    2818             : 
    2819           1 :     VNInfo *VNI = LR.getValNumInfo(i);
    2820             :     VNI->markUnused();
    2821           1 :     LR.removeValNo(VNI);
    2822             :   }
    2823      326980 : }
    2824             : 
    2825     1254596 : void JoinVals::eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
    2826             :                            SmallVectorImpl<unsigned> &ShrinkRegs,
    2827             :                            LiveInterval *LI) {
    2828     9574566 :   for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
    2829             :     // Get the def location before markUnused() below invalidates it.
    2830     7065374 :     SlotIndex Def = LR.getValNumInfo(i)->def;
    2831     3532687 :     switch (Vals[i].Resolution) {
    2832     2764703 :     case CR_Keep: {
    2833             :       // If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
    2834             :       // longer. The IMPLICIT_DEF instructions are only inserted by
    2835             :       // PHIElimination to guarantee that all PHI predecessors have a value.
    2836     2764703 :       if (!Vals[i].ErasableImplicitDef || !Vals[i].Pruned)
    2837             :         break;
    2838             :       // Remove value number i from LR.
    2839             :       // For intervals with subranges, removing a segment from the main range
    2840             :       // may require extending the previous segment: for each definition of
    2841             :       // a subregister, there will be a corresponding def in the main range.
    2842             :       // That def may fall in the middle of a segment from another subrange.
    2843             :       // In such cases, removing this def from the main range must be
    2844             :       // complemented by extending the main range to account for the liveness
    2845             :       // of the other subrange.
    2846             :       VNInfo *VNI = LR.getValNumInfo(i);
    2847          20 :       SlotIndex Def = VNI->def;
    2848             :       // The new end point of the main range segment to be extended.
    2849          20 :       SlotIndex NewEnd;
    2850          20 :       if (LI != nullptr) {
    2851          17 :         LiveRange::iterator I = LR.FindSegmentContaining(Def);
    2852             :         assert(I != LR.end());
    2853             :         // Do not extend beyond the end of the segment being removed.
    2854             :         // The segment may have been pruned in preparation for joining
    2855             :         // live ranges.
    2856          17 :         NewEnd = I->end;
    2857             :       }
    2858             : 
    2859          20 :       LR.removeValNo(VNI);
    2860             :       // Note that this VNInfo is reused and still referenced in NewVNInfo,
    2861             :       // make it appear like an unused value number.
    2862             :       VNI->markUnused();
    2863             : 
    2864          20 :       if (LI != nullptr && LI->hasSubRanges()) {
    2865             :         assert(static_cast<LiveRange*>(LI) == &LR);
    2866             :         // Determine the end point based on the subrange information:
    2867             :         // minimum of (earliest def of next segment,
    2868             :         //             latest end point of containing segment)
    2869           0 :         SlotIndex ED, LE;
    2870           0 :         for (LiveInterval::SubRange &SR : LI->subranges()) {
    2871           0 :           LiveRange::iterator I = SR.find(Def);
    2872           0 :           if (I == SR.end())
    2873           0 :             continue;
    2874           0 :           if (I->start > Def)
    2875           0 :             ED = ED.isValid() ? std::min(ED, I->start) : I->start;
    2876             :           else
    2877           0 :             LE = LE.isValid() ? std::max(LE, I->end) : I->end;
    2878             :         }
    2879           0 :         if (LE.isValid())
    2880           0 :           NewEnd = std::min(NewEnd, LE);
    2881           0 :         if (ED.isValid())
    2882           0 :           NewEnd = std::min(NewEnd, ED);
    2883             : 
    2884             :         // We only want to do the extension if there was a subrange that
    2885             :         // was live across Def.
    2886           0 :         if (LE.isValid()) {
    2887           0 :           LiveRange::iterator S = LR.find(Def);
    2888           0 :           if (S != LR.begin())
    2889           0 :             std::prev(S)->end = NewEnd;
    2890             :         }
    2891             :       }
    2892             :       LLVM_DEBUG({
    2893             :         dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LR << '\n';
    2894             :         if (LI != nullptr)
    2895             :           dbgs() << "\t\t  LHS = " << *LI << '\n';
    2896             :       });
    2897             :       LLVM_FALLTHROUGH;
    2898             :     }
    2899             : 
    2900             :     case CR_Erase: {
    2901             :       MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
    2902             :       assert(MI && "No instruction to erase");
    2903      654626 :       if (MI->isCopy()) {
    2904      626597 :         unsigned Reg = MI->getOperand(1).getReg();
    2905      626597 :         if (TargetRegisterInfo::isVirtualRegister(Reg) &&
    2906      797669 :             Reg != CP.getSrcReg() && Reg != CP.getDstReg())
    2907         201 :           ShrinkRegs.push_back(Reg);
    2908             :       }
    2909      654626 :       ErasedInstrs.insert(MI);
    2910             :       LLVM_DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
    2911      654626 :       LIS->RemoveMachineInstrFromMaps(*MI);
    2912      654626 :       MI->eraseFromParent();
    2913      654626 :       break;
    2914             :     }
    2915             :     default:
    2916             :       break;
    2917             :     }
    2918             :   }
    2919     1254596 : }
    2920             : 
    2921      163490 : void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
    2922             :                                          LaneBitmask LaneMask,
    2923             :                                          const CoalescerPair &CP) {
    2924             :   SmallVector<VNInfo*, 16> NewVNInfo;
    2925             :   JoinVals RHSVals(RRange, CP.getSrcReg(), CP.getSrcIdx(), LaneMask,
    2926      163492 :                    NewVNInfo, CP, LIS, TRI, true, true);
    2927             :   JoinVals LHSVals(LRange, CP.getDstReg(), CP.getDstIdx(), LaneMask,
    2928      163492 :                    NewVNInfo, CP, LIS, TRI, true, true);
    2929             : 
    2930             :   // Compute NewVNInfo and resolve conflicts (see also joinVirtRegs())
    2931             :   // We should be able to resolve all conflicts here as we could successfully do
    2932             :   // it on the mainrange already. There is however a problem when multiple
    2933             :   // ranges get mapped to the "overflow" lane mask bit which creates unexpected
    2934             :   // interferences.
    2935      163490 :   if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals)) {
    2936             :     // We already determined that it is legal to merge the intervals, so this
    2937             :     // should never fail.
    2938           0 :     llvm_unreachable("*** Couldn't join subrange!\n");
    2939             :   }
    2940      326980 :   if (!LHSVals.resolveConflicts(RHSVals) ||
    2941      163490 :       !RHSVals.resolveConflicts(LHSVals)) {
    2942             :     // We already determined that it is legal to merge the intervals, so this
    2943             :     // should never fail.
    2944           0 :     llvm_unreachable("*** Couldn't join subrange!\n");
    2945             :   }
    2946             : 
    2947             :   // The merging algorithm in LiveInterval::join() can't handle conflicting
    2948             :   // value mappings, so we need to remove any live ranges that overlap a
    2949             :   // CR_Replace resolution. Collect a set of end points that can be used to
    2950             :   // restore the live range after joining.
    2951             :   SmallVector<SlotIndex, 8> EndPoints;
    2952      163490 :   LHSVals.pruneValues(RHSVals, EndPoints, false);
    2953      163490 :   RHSVals.pruneValues(LHSVals, EndPoints, false);
    2954             : 
    2955      163490 :   LHSVals.removeImplicitDefs();
    2956      163490 :   RHSVals.removeImplicitDefs();
    2957             : 
    2958             :   LRange.verify();
    2959             :   RRange.verify();
    2960             : 
    2961             :   // Join RRange into LHS.
    2962      163490 :   LRange.join(RRange, LHSVals.getAssignments(), RHSVals.getAssignments(),
    2963             :               NewVNInfo);
    2964             : 
    2965             :   LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << LRange << "\n");
    2966      163490 :   if (EndPoints.empty())
    2967             :     return;
    2968             : 
    2969             :   // Recompute the parts of the live range we had to remove because of
    2970             :   // CR_Replace conflicts.
    2971             :   LLVM_DEBUG({
    2972             :     dbgs() << "\t\trestoring liveness to " << EndPoints.size() << " points: ";
    2973             :     for (unsigned i = 0, n = EndPoints.size(); i != n; ++i) {
    2974             :       dbgs() << EndPoints[i];
    2975             :       if (i != n-1)
    2976             :         dbgs() << ',';
    2977             :     }
    2978             :     dbgs() << ":  " << LRange << '\n';
    2979             :   });
    2980           2 :   LIS->extendToIndices(LRange, EndPoints);
    2981             : }
    2982             : 
    2983      162535 : void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
    2984             :                                           const LiveRange &ToMerge,
    2985             :                                           LaneBitmask LaneMask,
    2986             :                                           CoalescerPair &CP) {
    2987      162535 :   BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
    2988      325070 :   LI.refineSubRanges(Allocator, LaneMask,
    2989      491232 :       [this,&Allocator,&ToMerge,&CP](LiveInterval::SubRange &SR) {
    2990      163871 :     if (SR.empty()) {
    2991         762 :       SR.assign(ToMerge, Allocator);
    2992             :     } else {
    2993             :       // joinSubRegRange() destroys the merged range, so we need a copy.
    2994      163490 :       LiveRange RangeCopy(ToMerge, Allocator);
    2995      163490 :       joinSubRegRanges(SR, RangeCopy, SR.LaneMask, CP);
    2996             :     }
    2997      163871 :   });
    2998      162535 : }
    2999             : 
    3000      708025 : bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
    3001             :   SmallVector<VNInfo*, 16> NewVNInfo;
    3002      708025 :   LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
    3003      708025 :   LiveInterval &LHS = LIS->getInterval(CP.getDstReg());
    3004      708025 :   bool TrackSubRegLiveness = MRI->shouldTrackSubRegLiveness(*CP.getNewRC());
    3005             :   JoinVals RHSVals(RHS, CP.getSrcReg(), CP.getSrcIdx(), LaneBitmask::getNone(),
    3006     1416050 :                    NewVNInfo, CP, LIS, TRI, false, TrackSubRegLiveness);
    3007             :   JoinVals LHSVals(LHS, CP.getDstReg(), CP.getDstIdx(), LaneBitmask::getNone(),
    3008     1416050 :                    NewVNInfo, CP, LIS, TRI, false, TrackSubRegLiveness);
    3009             : 
    3010             :   LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << "\n\t\tLHS = " << LHS << '\n');
    3011             : 
    3012             :   // First compute NewVNInfo and the simple value mappings.
    3013             :   // Detect impossible conflicts early.
    3014      708025 :   if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
    3015             :     return false;
    3016             : 
    3017             :   // Some conflicts can only be resolved after all values have been mapped.
    3018      647609 :   if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
    3019             :     return false;
    3020             : 
    3021             :   // All clear, the live ranges can be merged.
    3022      627298 :   if (RHS.hasSubRanges() || LHS.hasSubRanges()) {
    3023      138309 :     BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
    3024             : 
    3025             :     // Transform lanemasks from the LHS to masks in the coalesced register and
    3026             :     // create initial subranges if necessary.
    3027      138309 :     unsigned DstIdx = CP.getDstIdx();
    3028      138309 :     if (!LHS.hasSubRanges()) {
    3029         229 :       LaneBitmask Mask = DstIdx == 0 ? CP.getNewRC()->getLaneMask()
    3030         458 :                                      : TRI->getSubRegIndexLaneMask(DstIdx);
    3031             :       // LHS must support subregs or we wouldn't be in this codepath.
    3032             :       assert(Mask.any());
    3033         229 :       LHS.createSubRangeFrom(Allocator, Mask, LHS);
    3034      138080 :     } else if (DstIdx != 0) {
    3035             :       // Transform LHS lanemasks to new register class if necessary.
    3036           0 :       for (LiveInterval::SubRange &R : LHS.subranges()) {
    3037           0 :         LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask);
    3038           0 :         R.LaneMask = Mask;
    3039             :       }
    3040             :     }
    3041             :     LLVM_DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg()) << ' ' << LHS
    3042             :                       << '\n');
    3043             : 
    3044             :     // Determine lanemasks of RHS in the coalesced register and merge subranges.
    3045      138309 :     unsigned SrcIdx = CP.getSrcIdx();
    3046      138309 :     if (!RHS.hasSubRanges()) {
    3047         564 :       LaneBitmask Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask()
    3048      236514 :                                      : TRI->getSubRegIndexLaneMask(SrcIdx);
    3049      118257 :       mergeSubRangeInto(LHS, RHS, Mask, CP);
    3050             :     } else {
    3051             :       // Pair up subranges and merge.
    3052       64330 :       for (LiveInterval::SubRange &R : RHS.subranges()) {
    3053       88556 :         LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(SrcIdx, R.LaneMask);
    3054       44278 :         mergeSubRangeInto(LHS, R, Mask, CP);
    3055             :       }
    3056             :     }
    3057             :     LLVM_DEBUG(dbgs() << "\tJoined SubRanges " << LHS << "\n");
    3058             : 
    3059             :     // Pruning implicit defs from subranges may result in the main range
    3060             :     // having stale segments.
    3061      138309 :     LHSVals.pruneMainSegments(LHS, ShrinkMainRange);
    3062             : 
    3063      138309 :     LHSVals.pruneSubRegValues(LHS, ShrinkMask);
    3064      138309 :     RHSVals.pruneSubRegValues(LHS, ShrinkMask);
    3065             :   }
    3066             : 
    3067             :   // The merging algorithm in LiveInterval::join() can't handle conflicting
    3068             :   // value mappings, so we need to remove any live ranges that overlap a
    3069             :   // CR_Replace resolution. Collect a set of end points that can be used to
    3070             :   // restore the live range after joining.
    3071             :   SmallVector<SlotIndex, 8> EndPoints;
    3072      627298 :   LHSVals.pruneValues(RHSVals, EndPoints, true);
    3073      627298 :   RHSVals.pruneValues(LHSVals, EndPoints, true);
    3074             : 
    3075             :   // Erase COPY and IMPLICIT_DEF instructions. This may cause some external
    3076             :   // registers to require trimming.
    3077             :   SmallVector<unsigned, 8> ShrinkRegs;
    3078      627298 :   LHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs, &LHS);
    3079      627298 :   RHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
    3080      627700 :   while (!ShrinkRegs.empty())
    3081         402 :     shrinkToUses(&LIS->getInterval(ShrinkRegs.pop_back_val()));
    3082             : 
    3083             :   // Join RHS into LHS.
    3084      627298 :   LHS.join(RHS, LHSVals.getAssignments(), RHSVals.getAssignments(), NewVNInfo);
    3085             : 
    3086             :   // Kill flags are going to be wrong if the live ranges were overlapping.
    3087             :   // Eventually, we should simply clear all kill flags when computing live
    3088             :   // ranges. They are reinserted after register allocation.
    3089      627298 :   MRI->clearKillFlags(LHS.reg);
    3090      627298 :   MRI->clearKillFlags(RHS.reg);
    3091             : 
    3092      627298 :   if (!EndPoints.empty()) {
    3093             :     // Recompute the parts of the live range we had to remove because of
    3094             :     // CR_Replace conflicts.
    3095             :     LLVM_DEBUG({
    3096             :       dbgs() << "\t\trestoring liveness to " << EndPoints.size() << " points: ";
    3097             :       for (unsigned i = 0, n = EndPoints.size(); i != n; ++i) {
    3098             :         dbgs() << EndPoints[i];
    3099             :         if (i != n-1)
    3100             :           dbgs() << ',';
    3101             :       }
    3102             :       dbgs() << ":  " << LHS << '\n';
    3103             :     });
    3104       78635 :     LIS->extendToIndices((LiveRange&)LHS, EndPoints);
    3105             :   }
    3106             : 
    3107             :   return true;
    3108             : }
    3109             : 
    3110      746268 : bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
    3111      746268 :   return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(CP);
    3112             : }
    3113             : 
    3114             : namespace {
    3115             : 
    3116             : /// Information concerning MBB coalescing priority.
    3117             : struct MBBPriorityInfo {
    3118             :   MachineBasicBlock *MBB;
    3119             :   unsigned Depth;
    3120             :   bool IsSplit;
    3121             : 
    3122             :   MBBPriorityInfo(MachineBasicBlock *mbb, unsigned depth, bool issplit)
    3123      342791 :     : MBB(mbb), Depth(depth), IsSplit(issplit) {}
    3124             : };
    3125             : 
    3126             : } // end anonymous namespace
    3127             : 
    3128             : /// C-style comparator that sorts first based on the loop depth of the basic
    3129             : /// block (the unsigned), and then on the MBB number.
    3130             : ///
    3131             : /// EnableGlobalCopies assumes that the primary sort key is loop depth.
    3132      740899 : static int compareMBBPriority(const MBBPriorityInfo *LHS,
    3133             :                               const MBBPriorityInfo *RHS) {
    3134             :   // Deeper loops first
    3135      740899 :   if (LHS->Depth != RHS->Depth)
    3136       61242 :     return LHS->Depth > RHS->Depth ? -1 : 1;
    3137             : 
    3138             :   // Try to unsplit critical edges next.
    3139      679657 :   if (LHS->IsSplit != RHS->IsSplit)
    3140           0 :     return LHS->IsSplit ? -1 : 1;
    3141             : 
    3142             :   // Prefer blocks that are more connected in the CFG. This takes care of
    3143             :   // the most difficult copies first while intervals are short.
    3144     1359314 :   unsigned cl = LHS->MBB->pred_size() + LHS->MBB->succ_size();
    3145     1359314 :   unsigned cr = RHS->MBB->pred_size() + RHS->MBB->succ_size();
    3146      679657 :   if (cl != cr)
    3147      337128 :     return cl > cr ? -1 : 1;
    3148             : 
    3149             :   // As a last resort, sort by block number.
    3150      342529 :   return LHS->MBB->getNumber() < RHS->MBB->getNumber() ? -1 : 1;
    3151             : }
    3152             : 
    3153             : /// \returns true if the given copy uses or defines a local live range.
    3154     1424549 : static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) {
    3155     1424549 :   if (!Copy->isCopy())
    3156             :     return false;
    3157             : 
    3158     2793556 :   if (Copy->getOperand(1).isUndef())
    3159             :     return false;
    3160             : 
    3161     1396743 :   unsigned SrcReg = Copy->getOperand(1).getReg();
    3162     1396743 :   unsigned DstReg = Copy->getOperand(0).getReg();
    3163             :   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)
    3164     2459033 :       || TargetRegisterInfo::isPhysicalRegister(DstReg))
    3165             :     return false;
    3166             : 
    3167      675810 :   return LIS->intervalIsInOneMBB(LIS->getInterval(SrcReg))
    3168      750046 :     || LIS->intervalIsInOneMBB(LIS->getInterval(DstReg));
    3169             : }
    3170             : 
    3171      864056 : bool RegisterCoalescer::
    3172             : copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
    3173             :   bool Progress = false;
    3174     3060634 :   for (unsigned i = 0, e = CurrList.size(); i != e; ++i) {
    3175     4393156 :     if (!CurrList[i])
    3176     1120993 :       continue;
    3177             :     // Skip instruction pointers that have already been erased, for example by
    3178             :     // dead code elimination.
    3179     1674072 :     if (ErasedInstrs.count(CurrList[i])) {
    3180       25327 :       CurrList[i] = nullptr;
    3181       25327 :       continue;
    3182             :     }
    3183     1623418 :     bool Again = false;
    3184     1623418 :     bool Success = joinCopy(CurrList[i], Again);
    3185     1623418 :     Progress |= Success;
    3186     1623418 :     if (Success || !Again)
    3187     1452008 :       CurrList[i] = nullptr;
    3188             :   }
    3189      864056 :   return Progress;
    3190             : }
    3191             : 
    3192             : /// Check if DstReg is a terminal node.
    3193             : /// I.e., it does not have any affinity other than \p Copy.
    3194          21 : static bool isTerminalReg(unsigned DstReg, const MachineInstr &Copy,
    3195             :                           const MachineRegisterInfo *MRI) {
    3196             :   assert(Copy.isCopyLike());
    3197             :   // Check if the destination of this copy as any other affinity.
    3198          50 :   for (const MachineInstr &MI : MRI->reg_nodbg_instructions(DstReg))
    3199          48 :     if (&MI != &Copy && MI.isCopyLike())
    3200             :       return false;
    3201             :   return true;
    3202             : }
    3203             : 
    3204     1552540 : bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const {
    3205             :   assert(Copy.isCopyLike());
    3206     1552540 :   if (!UseTerminalRule)
    3207             :     return false;
    3208             :   unsigned DstReg, DstSubReg, SrcReg, SrcSubReg;
    3209          33 :   isMoveInstr(*TRI, &Copy, SrcReg, DstReg, SrcSubReg, DstSubReg);
    3210             :   // Check if the destination of this copy has any other affinity.
    3211          58 :   if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
    3212             :       // If SrcReg is a physical register, the copy won't be coalesced.
    3213             :       // Ignoring it may have other side effect (like missing
    3214             :       // rematerialization). So keep it.
    3215          53 :       TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
    3216          20 :       !isTerminalReg(DstReg, Copy, MRI))
    3217             :     return false;
    3218             : 
    3219             :   // DstReg is a terminal node. Check if it interferes with any other
    3220             :   // copy involving SrcReg.
    3221           2 :   const MachineBasicBlock *OrigBB = Copy.getParent();
    3222           2 :   const LiveInterval &DstLI = LIS->getInterval(DstReg);
    3223           9 :   for (const MachineInstr &MI : MRI->reg_nodbg_instructions(SrcReg)) {
    3224             :     // Technically we should check if the weight of the new copy is
    3225             :     // interesting compared to the other one and update the weight
    3226             :     // of the copies accordingly. However, this would only work if
    3227             :     // we would gather all the copies first then coalesce, whereas
    3228             :     // right now we interleave both actions.
    3229             :     // For now, just consider the copies that are in the same block.
    3230          12 :     if (&MI == &Copy || !MI.isCopyLike() || MI.getParent() != OrigBB)
    3231          10 :       continue;
    3232             :     unsigned OtherReg, OtherSubReg, OtherSrcReg, OtherSrcSubReg;
    3233           1 :     isMoveInstr(*TRI, &Copy, OtherSrcReg, OtherReg, OtherSrcSubReg,
    3234             :                 OtherSubReg);
    3235           1 :     if (OtherReg == SrcReg)
    3236           0 :       OtherReg = OtherSrcReg;
    3237             :     // Check if OtherReg is a non-terminal.
    3238           3 :     if (TargetRegisterInfo::isPhysicalRegister(OtherReg) ||
    3239           1 :         isTerminalReg(OtherReg, MI, MRI))
    3240           0 :       continue;
    3241             :     // Check that OtherReg interfere with DstReg.
    3242           2 :     if (LIS->getInterval(OtherReg).overlaps(DstLI)) {
    3243             :       LLVM_DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg)
    3244             :                         << '\n');
    3245           1 :       return true;
    3246             :     }
    3247             :   }
    3248             :   return false;
    3249             : }
    3250             : 
    3251             : void
    3252      342791 : RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
    3253             :   LLVM_DEBUG(dbgs() << MBB->getName() << ":\n");
    3254             : 
    3255             :   // Collect all copy-like instructions in MBB. Don't start coalescing anything
    3256             :   // yet, it might invalidate the iterator.
    3257             :   const unsigned PrevSize = WorkList.size();
    3258      342791 :   if (JoinGlobalCopies) {
    3259             :     SmallVector<MachineInstr*, 2> LocalTerminals;
    3260             :     SmallVector<MachineInstr*, 2> GlobalTerminals;
    3261             :     // Coalesce copies bottom-up to coalesce local defs before local uses. They
    3262             :     // are not inherently easier to resolve, but slightly preferable until we
    3263             :     // have local live range splitting. In particular this is required by
    3264             :     // cmp+jmp macro fusion.
    3265      304279 :     for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
    3266     4268720 :          MII != E; ++MII) {
    3267     2539892 :       if (!MII->isCopyLike())
    3268     2539892 :         continue;
    3269     1424549 :       bool ApplyTerminalRule = applyTerminalRule(*MII);
    3270     2849098 :       if (isLocalCopy(&(*MII), LIS)) {
    3271      648516 :         if (ApplyTerminalRule)
    3272           1 :           LocalTerminals.push_back(&(*MII));
    3273             :         else
    3274     1297030 :           LocalWorkList.push_back(&(*MII));
    3275             :       } else {
    3276      776033 :         if (ApplyTerminalRule)
    3277           0 :           GlobalTerminals.push_back(&(*MII));
    3278             :         else
    3279     1552066 :           WorkList.push_back(&(*MII));
    3280             :       }
    3281             :     }
    3282             :     // Append the copies evicted by the terminal rule at the end of the list.
    3283      608558 :     LocalWorkList.append(LocalTerminals.begin(), LocalTerminals.end());
    3284      608558 :     WorkList.append(GlobalTerminals.begin(), GlobalTerminals.end());
    3285             :   }
    3286             :   else {
    3287             :     SmallVector<MachineInstr*, 2> Terminals;
    3288      436025 :     for (MachineInstr &MII : *MBB)
    3289             :       if (MII.isCopyLike()) {
    3290      127991 :         if (applyTerminalRule(MII))
    3291           0 :           Terminals.push_back(&MII);
    3292             :         else
    3293      127991 :           WorkList.push_back(&MII);
    3294             :       }
    3295             :     // Append the copies evicted by the terminal rule at the end of the list.
    3296       77024 :     WorkList.append(Terminals.begin(), Terminals.end());
    3297             :   }
    3298             :   // Try coalescing the collected copies immediately, and remove the nulls.
    3299             :   // This prevents the WorkList from getting too large since most copies are
    3300             :   // joinable on the first attempt.
    3301             :   MutableArrayRef<MachineInstr*>
    3302      342791 :     CurrList(WorkList.begin() + PrevSize, WorkList.end());
    3303      342791 :   if (copyCoalesceWorkList(CurrList))
    3304      251886 :     WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
    3305             :                                nullptr), WorkList.end());
    3306      342791 : }
    3307             : 
    3308      338801 : void RegisterCoalescer::coalesceLocals() {
    3309      338801 :   copyCoalesceWorkList(LocalWorkList);
    3310      987317 :   for (unsigned j = 0, je = LocalWorkList.size(); j != je; ++j) {
    3311     1297032 :     if (LocalWorkList[j])
    3312       30654 :       WorkList.push_back(LocalWorkList[j]);
    3313             :   }
    3314             :   LocalWorkList.clear();
    3315      338801 : }
    3316             : 
    3317      181495 : void RegisterCoalescer::joinAllIntervals() {
    3318             :   LLVM_DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
    3319             :   assert(WorkList.empty() && LocalWorkList.empty() && "Old data still around.");
    3320             : 
    3321             :   std::vector<MBBPriorityInfo> MBBs;
    3322      362990 :   MBBs.reserve(MF->size());
    3323      705781 :   for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
    3324             :     MachineBasicBlock *MBB = &*I;
    3325      685582 :     MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
    3326      342791 :                                    JoinSplitEdges && isSplitEdge(MBB)));
    3327             :   }
    3328             :   array_pod_sort(MBBs.begin(), MBBs.end(), compareMBBPriority);
    3329             : 
    3330             :   // Coalesce intervals in MBB priority order.
    3331             :   unsigned CurrDepth = std::numeric_limits<unsigned>::max();
    3332      705781 :   for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
    3333             :     // Try coalescing the collected local copies for deeper loops.
    3334      647070 :     if (JoinGlobalCopies && MBBs[i].Depth < CurrDepth) {
    3335      157306 :       coalesceLocals();
    3336      314612 :       CurrDepth = MBBs[i].Depth;
    3337             :     }
    3338      685582 :     copyCoalesceInMBB(MBBs[i].MBB);
    3339             :   }
    3340      181495 :   coalesceLocals();
    3341             : 
    3342             :   // Joining intervals can allow other intervals to be joined.  Iteratively join
    3343             :   // until we make no progress.
    3344      182464 :   while (copyCoalesceWorkList(WorkList))
    3345             :     /* empty */ ;
    3346      181495 : }
    3347             : 
    3348      181523 : void RegisterCoalescer::releaseMemory() {
    3349      181523 :   ErasedInstrs.clear();
    3350             :   WorkList.clear();
    3351             :   DeadDefs.clear();
    3352             :   InflateRegs.clear();
    3353      181523 : }
    3354             : 
    3355      181498 : bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
    3356      181498 :   MF = &fn;
    3357      181498 :   MRI = &fn.getRegInfo();
    3358      181498 :   const TargetSubtargetInfo &STI = fn.getSubtarget();
    3359      181498 :   TRI = STI.getRegisterInfo();
    3360      181498 :   TII = STI.getInstrInfo();
    3361      181498 :   LIS = &getAnalysis<LiveIntervals>();
    3362      362996 :   AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
    3363      181498 :   Loops = &getAnalysis<MachineLoopInfo>();
    3364      181498 :   if (EnableGlobalCopies == cl::BOU_UNSET)
    3365      181498 :     JoinGlobalCopies = STI.enableJoinGlobalCopies();
    3366             :   else
    3367           0 :     JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);
    3368             : 
    3369             :   // The MachineScheduler does not currently require JoinSplitEdges. This will
    3370             :   // either be enabled unconditionally or replaced by a more general live range
    3371             :   // splitting optimization.
    3372      181498 :   JoinSplitEdges = EnableJoinSplits;
    3373             : 
    3374             :   LLVM_DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
    3375             :                     << "********** Function: " << MF->getName() << '\n');
    3376             : 
    3377      181498 :   if (VerifyCoalescing)
    3378          46 :     MF->verify(this, "Before register coalescing");
    3379             : 
    3380      181498 :   RegClassInfo.runOnMachineFunction(fn);
    3381             : 
    3382             :   // Join (coalesce) intervals if requested.
    3383      181498 :   if (EnableJoining)
    3384      181495 :     joinAllIntervals();
    3385             : 
    3386             :   // After deleting a lot of copies, register classes may be less constrained.
    3387             :   // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
    3388             :   // DPR inflation.
    3389             :   array_pod_sort(InflateRegs.begin(), InflateRegs.end());
    3390             :   InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
    3391             :                     InflateRegs.end());
    3392             :   LLVM_DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size()
    3393             :                     << " regs.\n");
    3394      205503 :   for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
    3395       48010 :     unsigned Reg = InflateRegs[i];
    3396       48010 :     if (MRI->reg_nodbg_empty(Reg))
    3397         824 :       continue;
    3398       23181 :     if (MRI->recomputeRegClass(Reg)) {
    3399             :       LLVM_DEBUG(dbgs() << printReg(Reg) << " inflated to "
    3400             :                         << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n');
    3401             :       ++NumInflated;
    3402             : 
    3403        3793 :       LiveInterval &LI = LIS->getInterval(Reg);
    3404        3793 :       if (LI.hasSubRanges()) {
    3405             :         // If the inflated register class does not support subregisters anymore
    3406             :         // remove the subranges.
    3407           0 :         if (!MRI->shouldTrackSubRegLiveness(Reg)) {
    3408           0 :           LI.clearSubRanges();
    3409             :         } else {
    3410             : #ifndef NDEBUG
    3411             :           LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
    3412             :           // If subranges are still supported, then the same subregs
    3413             :           // should still be supported.
    3414             :           for (LiveInterval::SubRange &S : LI.subranges()) {
    3415             :             assert((S.LaneMask & ~MaxMask).none());
    3416             :           }
    3417             : #endif
    3418             :         }
    3419             :       }
    3420             :     }
    3421             :   }
    3422             : 
    3423             :   LLVM_DEBUG(dump());
    3424      181498 :   if (VerifyCoalescing)
    3425          46 :     MF->verify(this, "After register coalescing");
    3426      181498 :   return true;
    3427             : }
    3428             : 
    3429           0 : void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {
    3430           0 :    LIS->print(O, m);
    3431      303507 : }

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